[Lldb-commits] [lldb] [InstCombine] Canonicalize `and(zext(A), B)` into `select A, B & 1, 0` (PR #66740)

2023-09-19 Thread Yingwei Zheng via lldb-commits

dtcxzyw wrote:

> We should use rebase instead of merge. And I recommend force push to change 
> the code before the review starts.

I am confused with the LLVM GitHub user guide. I witnessed someone mess up by 
doing rebase + force push.
Examples: #65853 #65543 #65535


https://github.com/llvm/llvm-project/pull/66740
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[Lldb-commits] [lldb] ca723f2 - [lldb][Docs] Document our major differences from the LLVM style (#66345)

2023-09-19 Thread via lldb-commits

Author: David Spickett
Date: 2023-09-19T08:23:00+01:00
New Revision: ca723f2d40baf6c84e4c0907040e0c3f226d6302

URL: 
https://github.com/llvm/llvm-project/commit/ca723f2d40baf6c84e4c0907040e0c3f226d6302
DIFF: 
https://github.com/llvm/llvm-project/commit/ca723f2d40baf6c84e4c0907040e0c3f226d6302.diff

LOG: [lldb][Docs] Document our major differences from the LLVM style (#66345)

Running:
$ clang-format -i $(find -regex "\./lldb/.*\.c") $(find -regex
"\./lldb/.*\.cpp") $(find -regex "\./lldb/.*\.h")

Resulted in:
 1602 files changed, 25090 insertions(+), 25849 deletions(-)
(note: this includes tests which we wouldn't format, just using this as
an example)

The vast majority of which were whitespace changes. So as far as
formatting we're not deviating from llvm for any reason other than not
churning old code.

Formatting aside, the major features of lldb (single line if, early
return) are all reflected in llvm's style. We differ mainly on variable
naming (proposed to change in
https://llvm.org/docs/Proposals/VariableNames.html anyway) and use of
asserts. Which was already documented.

Added: 


Modified: 
lldb/docs/resources/contributing.rst

Removed: 




diff  --git a/lldb/docs/resources/contributing.rst 
b/lldb/docs/resources/contributing.rst
index 54917f1ce8175b3..5ac4afb82a0747a 100644
--- a/lldb/docs/resources/contributing.rst
+++ b/lldb/docs/resources/contributing.rst
@@ -18,19 +18,45 @@ Please refer to the `LLVM Developer Policy
 authoring and uploading a patch. LLDB 
diff ers from the LLVM Developer
 Policy in the following respects.
 
- - **Test infrastructure**: Like LLVM it is  important to submit tests with 
your
-   patches, but note that LLDB uses a 
diff erent system for tests. Refer to the
-   `test documentation `_ for more details and the ``lldb/test``
-   folder on disk for examples.
-
- - **Coding Style**: LLDB's code style 
diff ers from
-   `LLVM's coding style `_.
-   Unfortunately there is no document describing the 
diff erences. Please be
-   consistent with the existing code.
-
 For anything not explicitly listed here, assume that LLDB follows the LLVM
 policy.
 
+Coding Style
+
+
+LLDB's code style 
diff ers from `LLVM's coding style 
`_
+in a few ways. The 2 main ones are:
+
+* `Variable and function naming 
`_:
+
+  * Variables are ``snake_case``.
+
+  * Functions and methods are ``UpperCamelCase``.
+
+  * Static, global and member variables have ``s_``, ``g_`` and ``_m``
+prefixes respectively.
+
+* `Use of asserts 
`_:
+  See the :ref:`section below`.
+
+For any other contradications, consider the
+`golden rule `_
+before choosing to update the style of existing code.
+
+All new code in LLDB should be formatted with clang-format. Existing code may
+not conform and should be updated prior to being modified. Bulk reformatting
+is discouraged.
+
+Test Infrastructure

+
+Like LLVM it is important to submit tests with your patches, but note that  a
+subset of LLDB tests (the API tests) use a 
diff erent system. Refer to the
+`test documentation `_ for more details and the
+`lldb/test `_ folder
+for examples.
+
+.. _Error handling:
 
 Error handling and use of assertions in LLDB
 
@@ -42,14 +68,13 @@ be extra thoughtful about how to handle errors. Below are a 
couple
 rules of thumb:
 
 * Invalid input.  To deal with invalid input, such as malformed DWARF,
-  missing object files, or otherwise inconsistent debug info, LLVM's
+  missing object files, or otherwise inconsistent debug info,
   error handling types such as `llvm::Expected
   `_ or
-  `std::optional
-  `_ should be
-  used. Functions that may fail should return their result using these
-  wrapper types instead of using a bool to indicate success. Returning
-  a default value when an error occurred is also discouraged.
+  ``std::optional`` should be used. Functions that may fail
+  should return their result using these wrapper types instead of
+  using a bool to indicate success. Returning a default value when an
+  error occurred is also discouraged.
 
 * Assertions.  Assertions (from ``assert.h``) should be used liberally
   to assert internal consistency.  Assertions shall **never** be
@@ -71,16 +96,18 @@ rules of thumb:
   behaves like ``assert()``. When asserts are disabled, it will print a
   warning and encourage the user to file a bug report, similar to
   LLVM's crash handler, and the

[Lldb-commits] [lldb] [lldb][Docs] Document our major differences from the LLVM style (PR #66345)

2023-09-19 Thread David Spickett via lldb-commits

https://github.com/DavidSpickett closed 
https://github.com/llvm/llvm-project/pull/66345
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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread Muhammad Omair Javaid via Phabricator via lldb-commits
omjavaid added inline comments.



Comment at: 
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py:201
+self.runCmd("register write za '{}'".format(za_value))
+self.expect("register read za", substrs=[za_value])

How can we differentiate between disabled ZA (read as all zeros) and enabled ZA 
actually set to all zeros?



Comment at: 
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py:104
+if mode == Mode.SSVE:
+cflags += " -DUSE_SSVE"
+self.build(dictionary={"CFLAGS_EXTRAS": cflags})

is there a reference somewhere in clang or gcc documentation for USE_SSVE flag?



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile:3
+
+CFLAGS_EXTRAS := -march=armv8-a+sve+sme -lpthread
+

is USE_SSVE a subset of sve+sme? 


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[Lldb-commits] [lldb] [LLDB] Add a setting for printing ValueObject hex values without leading zeroes (PR #66548)

2023-09-19 Thread David Spickett via lldb-commits

DavidSpickett wrote:

This is failing on Arm 32 bit 
(https://lab.llvm.org/buildbot/#/builders/17/builds/43300), I'll reproduce and 
fix it. I expect it just needs to expect 8 hex characters instead of 16.

https://github.com/llvm/llvm-project/pull/66548
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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett added inline comments.



Comment at: 
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py:201
+self.runCmd("register write za '{}'".format(za_value))
+self.expect("register read za", substrs=[za_value])

omjavaid wrote:
> How can we differentiate between disabled ZA (read as all zeros) and enabled 
> ZA actually set to all zeros?
In this specific test we write a non-zero value to avoid that issue, but I 
assume you mean generally.

The user should refer to the SVCR register, SVCR.ZA specifically, to know if 
the value they're seeing is the active ZA or not. You can see an example of 
that if you look at the changes to this file in 
https://reviews.llvm.org/D154927.

Again, the user has to know what bit to look for but I'll eventually address 
that with the register fields work.



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile:3
+
+CFLAGS_EXTRAS := -march=armv8-a+sve+sme -lpthread
+

omjavaid wrote:
> is USE_SSVE a subset of sve+sme? 
It's a define I made up for the purposes of the test, it's in the existing 
tests but not well documented. I'll push something to address that in the 
existing tests and check the new ones here for this and other defines I've 
added.

We need sve to update sve registers and sme to be able to move into the za 
register (/the rows of the za register).


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[Lldb-commits] [lldb] Support target names with dots in more utilities (PR #65812)

2023-09-19 Thread James Henderson via lldb-commits

https://github.com/jh7370 approved this pull request.

Force pushing (and therefore rebasing) is [supposed to be 
avoided](https://llvm.org/docs/GitHub.html#rebasing-pull-requests-and-force-pushes)
 unless it's absolutely necessary. Was a rebase actually required for this 
change? One of the motivations to avoid force pushes is that I can no longer 
see what changed versus my previous review, which is a fairly major usability 
issue for reviewing. Fortunately, this is a small review...

By the way, did you mean to have two commits in your PR?

LGTM, aside from a comment on the TODO.

https://github.com/llvm/llvm-project/pull/65812
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[Lldb-commits] [lldb] Support target names with dots in more utilities (PR #65812)

2023-09-19 Thread James Henderson via lldb-commits


@@ -5,11 +5,14 @@
 # RUN: mkdir %t
 # RUN: ln -s llvm-ranlib %t/llvm-ranlib-9
 # RUN: ln -s llvm-ranlib %t/ranlib.exe
+# RUN: ln -s llvm-ranlib %t/x86_64-unknown-freebsd13.2-llvm-ranlib

jh7370 wrote:

Let's put the new test files and deletion of this old test in a different PR. 
The old code was untested, so we're not making things worse, but it also helps 
keep the PRs focused. Aside: if we're deleting this old file, I think it would 
be a good idea to add one or two cases to the llvm-ar test showing the 
"llvm-ranlib" name.

https://github.com/llvm/llvm-project/pull/65812
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[Lldb-commits] [lldb] Support target names with dots in more utilities (PR #65812)

2023-09-19 Thread James Henderson via lldb-commits


@@ -1696,6 +1696,40 @@ TEST(Support, ReplacePathPrefix) {
   EXPECT_EQ(Path, "C:\\old/foo\\bar");
 }
 
+TEST(Support, FindProgramName) {
+  StringRef WindowsProgName =
+  path::program_name("C:\\Test\\foo.exe", path::Style::windows);
+  EXPECT_EQ(WindowsProgName, "foo");
+
+  StringRef WindowsProgNameManyDots = path::program_name(
+  "C:\\Test.7\\x86_64-freebsd14.0-clang.exe", path::Style::windows);
+  EXPECT_EQ(WindowsProgNameManyDots, "x86_64-freebsd14.0-clang");
+
+  StringRef PosixProgName =
+  path::program_name("/var/empty/clang.exe", path::Style::posix);
+  EXPECT_EQ(PosixProgName, "clang");
+
+  StringRef PosixProgNameManyDotsExe = path::program_name(
+  "/llvm-test16.4/x86_64-portbld-freebsd13.2-llvm-ar.exe",
+  path::Style::posix);
+  EXPECT_EQ(PosixProgNameManyDotsExe, "x86_64-portbld-freebsd13.2-llvm-ar");
+
+  StringRef PosixProgNameManyDots = path::program_name(
+  "/llvm-test16.4/x86_64-portbld-freebsd13.2-llvm-ar", path::Style::posix);
+  EXPECT_EQ(PosixProgNameManyDots, "x86_64-portbld-freebsd13.2-llvm-ar");
+
+  StringRef PosixProgNameSh =
+  
path::program_name("/llvm-test16.4/x86_64-portbld-freebsd13.2-llvm-ar.sh",
+ path::Style::posix);
+  EXPECT_EQ(PosixProgNameSh, "x86_64-portbld-freebsd13.2-llvm-ar.sh");
+
+  // TODO: determine if this is correct. What happens on windows with an 
executable
+  // named ".exe"?

jh7370 wrote:

I just used the Windows UI to rename a file to ".exe" and it works fine (both 
renaming and susbequent execution of the file from the command-line). 
Meanwhile, the documented behaviour of `stem` is that something containing only 
a single dot will result in an empty string, which I think we should be 
mirroring here. I think the behaviour tested here is therefore correct and you 
can probably drop the TODO note.

https://github.com/llvm/llvm-project/pull/65812
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[Lldb-commits] [lldb] 9568601 - [lldb] Correct expected output for variable on 32 bit platforms

2023-09-19 Thread David Spickett via lldb-commits

Author: David Spickett
Date: 2023-09-19T08:28:34Z
New Revision: 956860168b56f135b9facf3827ae9f3634d41f40

URL: 
https://github.com/llvm/llvm-project/commit/956860168b56f135b9facf3827ae9f3634d41f40
DIFF: 
https://github.com/llvm/llvm-project/commit/956860168b56f135b9facf3827ae9f3634d41f40.diff

LOG: [lldb] Correct expected output for variable on 32 bit platforms

710276a2505514634a7cc805461b1219dcef9337 added settings to control
leading zeros but the initial test case assumed a 64 bit target.

Added: 


Modified: 
lldb/test/API/python_api/value/TestValueAPI.py

Removed: 




diff  --git a/lldb/test/API/python_api/value/TestValueAPI.py 
b/lldb/test/API/python_api/value/TestValueAPI.py
index 3855c67c8d37257..75052671d8d26c3 100644
--- a/lldb/test/API/python_api/value/TestValueAPI.py
+++ b/lldb/test/API/python_api/value/TestValueAPI.py
@@ -210,7 +210,7 @@ def test(self):
 # Check that hex value printing works as expected.
 self.assertEqual(
 frame0.FindVariable("fixed_int_ptr").GetValue(),
-"0x00aa",
+"0x00aa" if target.addr_size == 4 else "0x00aa",
 )
 self.runCmd("settings set 
target.show-hex-variable-values-with-leading-zeroes false")
 self.assertEqual(



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[Lldb-commits] [lldb] [InstCombine] Canonicalize `and(zext(A), B)` into `select A, B & 1, 0` (PR #66740)

2023-09-19 Thread Nikita Popov via lldb-commits

nikic wrote:

I think this is the right canonicalization at the IR level, as select allows 
better analysis than zext(icmp). However, this seems to be universally worse 
for the backend: https://llvm.godbolt.org/z/Yh7brfc8b So I think we would need 
an SDAG undo transform. Interestingly, this already happens for riscv64, so 
maybe the undo transform already exists but is not enabled for all target.

@goldsteinn What do you think?

https://github.com/llvm/llvm-project/pull/66740
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[Lldb-commits] [lldb] 91f46ec - [lldb][AArch64] Document how to control the SVE/SSVE tests

2023-09-19 Thread David Spickett via lldb-commits

Author: David Spickett
Date: 2023-09-19T08:51:37Z
New Revision: 91f46ece9efca7a1109b5837a1b24f2a251bb0cc

URL: 
https://github.com/llvm/llvm-project/commit/91f46ece9efca7a1109b5837a1b24f2a251bb0cc
DIFF: 
https://github.com/llvm/llvm-project/commit/91f46ece9efca7a1109b5837a1b24f2a251bb0cc.diff

LOG: [lldb][AArch64] Document how to control the SVE/SSVE tests

A lot of these use defines that I made up for this purpose,
which is not obvious at first glance. Document that at the top
of each file.

Added: 


Modified: 
lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c

Removed: 




diff  --git 
a/lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c 
b/lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
index b8db8852b8ed51a..93100f01502f8ba 100644
--- a/lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
+++ b/lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
@@ -1,5 +1,9 @@
 #include 
 
+// If this program receives 0 arguments, it will use non-streaming SVE
+// registers. If the number of arguments is >= 1, it will use streaming SVE
+// registers.
+
 #ifndef HWCAP2_SME
 #define HWCAP2_SME (1 << 23)
 #endif

diff  --git 
a/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
 
b/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
index 0bb6b3b57046f89..d126f8d75fb0c7c 100644
--- 
a/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
+++ 
b/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
@@ -2,6 +2,9 @@
 #include 
 #include 
 
+// If USE_SSVE is defined, this program will use streaming mode SVE registers
+// instead of non-streaming mode SVE registers.
+
 #ifndef PR_SME_SET_VL
 #define PR_SME_SET_VL 63
 #endif

diff  --git 
a/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
 
b/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
index b4623fe12725a2a..b07fb62ed85b74c 100644
--- 
a/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
+++ 
b/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
@@ -1,6 +1,10 @@
 #include 
 #include 
 
+// If START_SSVE is defined, this program will start in streaming SVE mode
+// (it will later enter and exit streaming mode a few times). Otherwise, it
+// will start in non-streaming SVE mode.
+
 #ifndef PR_SME_SET_VL
 #define PR_SME_SET_VL 63
 #endif

diff  --git 
a/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c 
b/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
index 2156f094cab5c5f..0a05a9a5a59de17 100644
--- a/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
+++ b/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
@@ -1,6 +1,16 @@
 #include 
 #include 
 
+// If SSVE is defined, this program will start in streaming SVE mode. 
Otherwise,
+// if SVE is defined, it will start in non-streaming mode and activate the SVE
+// registers by writing to one of them. If neither SSVE or SVE are defined,
+// the program will start in non-streaming mode, with the SVE registers
+// inactive.
+//
+// For most programs the 
diff erence between inactive non-streaming SVE and
+// active is transparent. For lldb, there are some 
diff erences in how we use
+// ptrace in either scenario.
+
 // base is added to each value. If base = 2, then v0 = 2, v1 = 3, etc.
 void write_simd_regs(unsigned base) {
 #define WRITE_SIMD(NUM)
\



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[Lldb-commits] [lldb] [LLDB] Add a setting for printing ValueObject hex values without leading zeroes (PR #66548)

2023-09-19 Thread David Spickett via lldb-commits

DavidSpickett wrote:

https://github.com/llvm/llvm-project/commit/956860168b56f135b9facf3827ae9f3634d41f40

https://github.com/llvm/llvm-project/pull/66548
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[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557007.
DavidSpickett added a comment.

Rebase


Repository:
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CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D159502

Files:
  lldb/include/lldb/Utility/RegisterValue.h
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h

Index: lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
===
--- lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
+++ lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
@@ -119,6 +119,10 @@
 {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_SVE},
 };
 
+constexpr RegsetDesc AARCH64_ZA_Desc[] = {
+{llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_ZA},
+};
+
 constexpr RegsetDesc AARCH64_PAC_Desc[] = {
 {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_PAC_MASK},
 };
Index: lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
===
--- lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
+++ lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
@@ -113,7 +113,7 @@
 m_sve_state = SVEState::Disabled;
 
   if (m_sve_state != SVEState::Disabled)
-m_register_info_up->ConfigureVectorLength(
+m_register_info_up->ConfigureVectorLengthSVE(
 sve::vq_from_vl(m_sve_vector_length));
 }
 
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -30,6 +30,7 @@
 eRegsetMaskPAuth = 4,
 eRegsetMaskMTE = 8,
 eRegsetMaskTLS = 16,
+eRegsetMaskZA = 32,
 eRegsetMaskDynamic = ~1,
   };
 
@@ -106,7 +107,11 @@
 
   void AddRegSetTLS(bool has_tpidr2);
 
-  uint32_t ConfigureVectorLength(uint32_t sve_vq);
+  void AddRegSetSME();
+
+  uint32_t ConfigureVectorLengthSVE(uint32_t sve_vq);
+
+  void ConfigureVectorLengthZA(uint32_t za_vq);
 
   bool VectorSizeIsValid(uint32_t vq) {
 // coverity[unsigned_compare]
@@ -117,6 +122,7 @@
 
   bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }
   bool IsSSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }
+  bool IsZAEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskZA); }
   bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }
   bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }
   bool IsTLSEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); }
@@ -128,6 +134,7 @@
   bool IsPAuthReg(unsigned reg) const;
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
+  bool IsSMEReg(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
@@ -137,6 +144,7 @@
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
+  uint32_t GetSMEOffset() const;
 
 private:
   typedef std::map>
@@ -145,7 +153,10 @@
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
+  uint32_t m_za_reg_vq = eVectorQuadwordAArch64;
 
+  // In normal operation this is const. Only when SVE or SME registers change
+  // size is it either replaced or the content modified.
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 
@@ -164,6 +175,7 @@
   std::vector pauth_regnum_collection;
   std::vector m_mte_regnum_collection;
   std::vector m_tls_regnum_collection;
+  std::vector m_sme_regnum_collection;
 };
 
 #endif
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,6 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
+static lldb_private::RegisterInfo g_register_infos_sme[] =
+// 16 is a default size we will change later.
+{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+  KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+
 // Number of register sets provided 

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557008.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159503/new/

https://reviews.llvm.org/D159503

Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -135,12 +135,14 @@
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
   bool IsSMEReg(unsigned reg) const;
+  bool IsSMERegZA(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
   uint32_t GetRegNumSVEVG() const;
+  uint32_t GetRegNumSMESVG() const;
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,10 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
-static lldb_private::RegisterInfo g_register_infos_sme[] =
+static lldb_private::RegisterInfo g_register_infos_sme[] = {
+DEFINE_EXTENSION_REG(svg),
 // 16 is a default size we will change later.
-{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
-  KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+ KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
 
 // Number of register sets provided by this context.
 enum {
@@ -96,7 +97,7 @@
   k_num_mte_register = 1,
   // Number of TLS registers is dynamic so it is not listed here.
   k_num_pauth_register = 2,
-  k_num_sme_register = 1,
+  k_num_sme_register = 2,
   k_num_register_sets_default = 2,
   k_num_register_sets = 3
 };
@@ -448,7 +449,7 @@
   // dynamic set and is just 1 register so we make an exception to const here.
   lldb_private::RegisterInfo *non_const_reginfo =
   const_cast(m_register_info_p);
-  non_const_reginfo[m_sme_regnum_collection[0]].byte_size =
+  non_const_reginfo[m_sme_regnum_collection[1]].byte_size =
   (za_vq * 16) * (za_vq * 16);
 }
 
@@ -471,6 +472,10 @@
   return sve_vg == reg;
 }
 
+bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
+  return reg == m_sme_regnum_collection[1];
+}
+
 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
   return llvm::is_contained(pauth_regnum_collection, reg);
 }
@@ -497,6 +502,10 @@
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
 
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const {
+  return m_sme_regnum_collection[0];
+}
+
 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
   return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
 }
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -114,6 +114,12 @@
 
   uint64_t m_mte_ctrl_reg;
 
+  struct sme_pseudo_regs {
+uint64_t svg_reg;
+  };
+
+  struct sme_pseudo_regs m_sme_pseudo_regs;
+
   struct tls_regs {
 uint64_t tpidr_reg;
 // Only valid when SME is present.
@@ -144,6 +150,8 @@
 
   Status WriteTLS();
 
+  Status ReadSMESVG();
+
   Status ReadZAHeader();
 
   Status ReadZA();
@@ -176,6 +184,8 @@
 
   void *GetTLSBuffer() { return &m_tls_regs; }
 
+  void *GetSMEPseudoBuffer() { return &m_sme_pseudo_regs; }
+
   void *GetSVEBuffer() { return m_sve_ptrace_payload.data(); }
 
   size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
@@ -194,6 +204,8 @@
 
   size_t GetTLSBufferSize() { return m_tls_size; }
 
+  size_t GetSMEPseudoBufferSize() { return sizeof(m_sme_pseudo_regs); }
+
   llvm::Error ReadHardwareDebugInfo() override;
 
   llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -147,6 +147,7 @@
   ::memset(&m_sve_header, 0, sizeof(m_sve_header));
   ::mems

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557009.
DavidSpickett marked an inline comment as done.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159504/new/

https://reviews.llvm.org/D159504

Files:
  lldb/include/lldb/Target/DynamicRegisterInfo.h
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp

Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -614,10 +614,11 @@
   ConfigureOffsets();
 
   // Check if register info is reconfigurable
-  // AArch64 SVE register set has configurable register sizes
+  // AArch64 SVE register set has configurable register sizes, as does the ZA
+  // register that SME added (the streaming state of SME reuses the SVE state).
   if (arch.GetTriple().isAArch64()) {
 for (const auto ® : m_regs) {
-  if (strcmp(reg.name, "vg") == 0) {
+  if ((strcmp(reg.name, "vg") == 0) || (strcmp(reg.name, "svg") == 0)) {
 m_is_reconfigurable = true;
 break;
   }
Index: lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -1660,17 +1660,18 @@
 gdb_thread->PrivateSetRegisterValue(lldb_regnum, buffer_sp->GetData());
   }
 
-  // AArch64 SVE specific code below calls AArch64SVEReconfigure to update
-  // SVE register sizes and offsets if value of VG register has changed
-  // since last stop.
+  // AArch64 SVE/SME specific code below updates SVE and ZA register sizes and
+  // offsets if value of VG or SVG registers has changed since last stop.
   const ArchSpec &arch = GetTarget().GetArchitecture();
   if (arch.IsValid() && arch.GetTriple().isAArch64()) {
 GDBRemoteRegisterContext *reg_ctx_sp =
 static_cast(
 gdb_thread->GetRegisterContext().get());
 
-if (reg_ctx_sp)
-  reg_ctx_sp->AArch64SVEReconfigure();
+if (reg_ctx_sp) {
+  reg_ctx_sp->AArch64Reconfigure();
+  reg_ctx_sp->InvalidateAllRegisters();
+}
   }
 
   thread_sp->SetName(thread_name.empty() ? nullptr : thread_name.c_str());
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
@@ -39,6 +39,7 @@
   ~GDBRemoteDynamicRegisterInfo() override = default;
 
   void UpdateARM64SVERegistersInfos(uint64_t vg);
+  void UpdateARM64SMERegistersInfos(uint64_t svg);
 };
 
 class GDBRemoteRegisterContext : public RegisterContext {
@@ -77,7 +78,8 @@
   uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,
uint32_t num) override;
 
-  bool AArch64SVEReconfigure();
+  // Reconfigure variable sized registers for AArch64 SVE and SME.
+  void AArch64Reconfigure();
 
 protected:
   friend class ThreadGDBRemote;
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -373,14 +373,14 @@
   if (dst == nullptr)
 return false;
 
-  // Code below is specific to AArch64 target in SVE state
+  // Code below is specific to AArch64 target in SVE or SME state
   // If vector granule (vg) register is being written then thread's
   // register context reconfiguration is triggered on success.
-  bool do_reconfigure_arm64_sve = false;
+  // We do not allow writes to SVG so it is not mentioned here.
   const ArchSpec &arch = process->GetTarget().GetArchitecture();
-  if (arch.IsValid() && arch.GetTriple().isAArch64())
-if (strcmp(reg_info->name, "vg") == 0)
-  do_reconfigure_arm64_sve = true;
+  bool do_reconfigure_arm64_sve = arch.IsValid() &&
+  arch.GetTriple().isAArch64() &&
+  (strcmp(reg_info->name, "vg") == 0);
 
   if (data.CopyByteOrderedData(data_offset,// src offset
reg_info->byte_size,// src length
@@ -400,10 +400,10 @@
 {m_reg_data.GetDataStart(), size_t(m_reg_data.GetByteSize())}))
 
 {
-  SetAllRegisterValid(false);
-
   if (do_reconfigure_arm64_sve)
-AArch64SVEReconfigure();
+AArch64Reconfigure();
+
+  InvalidateAllRe

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett marked 2 inline comments as done.
DavidSpickett added inline comments.



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile:3
+
+CFLAGS_EXTRAS := -march=armv8-a+sve+sme -lpthread
+

DavidSpickett wrote:
> omjavaid wrote:
> > is USE_SSVE a subset of sve+sme? 
> It's a define I made up for the purposes of the test, it's in the existing 
> tests but not well documented. I'll push something to address that in the 
> existing tests and check the new ones here for this and other defines I've 
> added.
> 
> We need sve to update sve registers and sme to be able to move into the za 
> register (/the rows of the za register).
https://github.com/llvm/llvm-project/commit/91f46ece9efca7a1109b5837a1b24f2a251bb0cc

USE_SSVE and friends are just defines `-D...` made up for specific tests.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D159505/new/

https://reviews.llvm.org/D159505

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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557010.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159505/new/

https://reviews.llvm.org/D159505

Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,226 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm volatile("pfalse p11.b\n\t");
+  asm volatile("pfalse p12.b\n\t");
+  asm volatile("pfalse p13.b\n\t");
+  asm volatile

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557011.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154927/new/

https://reviews.llvm.org/D154927

Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
===
--- lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
@@ -164,6 +164,10 @@
 self.runCmd("register read " + sve_reg_names)
 sve_values = self.res.GetOutput()
 
+svcr_value = 1 if sve_mode == Mode.SSVE else 0
+if za_state == ZA.Enabled:
+svcr_value += 2
+
 def check_regs():
 if za_state == ZA.Enabled:
 self.check_za(start_vl)
@@ -175,6 +179,7 @@
 self.assertEqual(start_vg, self.read_vg())
 
 self.expect("register read " + sve_reg_names, substrs=[sve_values])
+self.expect("register read svcr", substrs=["0x{:016x}".format(svcr_value)])
 
 for expr in exprs:
 expr_cmd = "expression {}()".format(expr)
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
@@ -9,7 +9,7 @@
 #define PR_SME_SET_VL 63
 #endif
 
-#define SMSTART() asm volatile("msr  s0_3_c4_c7_3, xzr" /*smstart*/)
+#define SMSTART_SM() asm volatile("msr  s0_3_c4_c3_3, xzr" /*smstart sm*/)
 
 void write_sve_regs() {
   // We assume the smefa64 feature is present, which allows ffr access
@@ -130,18 +130,18 @@
   // Note that doing a syscall brings you back to non-streaming mode, so we
   // don't need to SMSTOP here.
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   prctl(SET_VL_OPT, 8 * 4);
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   return 1;
 }
 
 int main() {
 #ifdef START_SSVE
-  SMSTART();
+  SMSTART_SM();
 #endif
   write_sve_regs();
 
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
@@ -24,7 +24,15 @@
 reg_value.GetByteSize(), expected, 'Verify "%s" == %i' % (name, expected)
 )
 
-def check_sve_regs_read(self, z_reg_size):
+def check_sve_regs_read(self, z_reg_size, expected_mode):
+if self.isAArch64SME():
+# This test uses SMSTART SM, which only enables streaming mode,
+# leaving ZA disabled.
+expected_value = "1" if expected_mode == Mode.SSVE else "0"
+self.expect(
+"register read svcr", substrs=["0x000" + expected_value]
+)
+
 p_reg_size = int(z_reg_size / 8)
 
 for i in range(32):
@@ -168,7 +176,7 @@
 
 vg_reg_value = sve_registers.GetChildMemberWithName("vg").GetValueAsUnsigned()
 z_reg_size = vg_reg_value * 8
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 # Evaluate simple expression and print function expr_eval_func address.
 self.expect("expression expr_eval_func", substrs=["= 0x"])
@@ -184,7 +192,7 @@
 
 # We called a jitted function above which must not have changed SVE
 # vector length or register values.
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 self.check_sve_regs_read_after_write(z_reg_size)
 
Index: lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
===
--- lldb/test/API/comma

[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557012.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158500/new/

https://reviews.llvm.org/D158500

Files:
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
  lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py
  lldb/test/API/linux/aarch64/sme_core_file/core_0_16_32_1
  lldb/test/API/linux/aarch64/sme_core_file/core_0_32_16_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_16_32_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_32_16_1
  lldb/test/API/linux/aarch64/sme_core_file/main.c

Index: lldb/test/API/linux/aarch64/sme_core_file/main.c
===
--- /dev/null
+++ lldb/test/API/linux/aarch64/sme_core_file/main.c
@@ -0,0 +1,140 @@
+// clang-format off
+// Compile with:
+// clang -target aarch64-unknown-linux-gnu main.c -o a.out -g -march=armv8.6-a+sve+sme
+//
+// For minimal corefile size, do this before running the program:
+// echo 0x20 > /proc/self/coredeump_filter
+//
+// Must be run on a system that has SVE and SME, including the smefa64
+// extension. Example command:
+// main 0 32 64 1
+//
+// This would not enter streaming mode, set non-streaming VL to 32
+// bytes, streaming VL to 64 bytes and enable ZA.
+// clang-format on
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+
+void set_sve_registers() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+void set_za_register(int streaming_vl) {
+#define MAX_VL_BYTES 256
+  uint8_t data[MAX_VL_BYTES];
+
+  for (unsigned i = 0; i < streaming_vl; ++i) {
+for (unsigned j = 0; j < MAX_VL_BYTES; ++j)
+  data[j] = i + 1;
+asm volatile("mov w12, %w0\n\t"
+ "ldr za[w12, 0], [%1]\n\t" ::"r"(i),
+ "r"(&data)
+ : "w12");
+  }
+}
+
+void set_tpidr2(uint64_t value) {
+  __asm__ volatile("msr S3_3_C13_C0_5, %0" ::"r"(value));
+}
+
+int main(int argc, char **argv) {
+  // Arguments:
+  //  SVE mode: 1 for streaming SVE (SSVE), any other value
+  //  for non-streaming SVE mode.
+  //   Non-Streaming Vector length: In bytes, an integer e.g. "32".
+  //   Streaming Vector length: As above, but for streaming mode.
+  //   ZA mode: 1 for enabled, any other value for disabled.
+  if (argc != 5)
+return 1;
+
+  // We assume this is run on 

[Lldb-commits] [PATCH] D158506: [lldb][AArch64] Add release notes and documentation for SME

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557013.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158506/new/

https://reviews.llvm.org/D158506

Files:
  lldb/docs/index.rst
  lldb/docs/use/aarch64-linux.rst
  llvm/docs/ReleaseNotes.rst

Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -183,6 +183,10 @@
 * Methods in SBHostOS related to threads have had their implementations
   removed. These methods will return a value indicating failure.
 
+* LLDB now supports debugging the Scalable Matrix Extension (SME) on AArch64
+  Linux for both running processes and core files. For details refer to the
+  `AArch64 Linux documentation `_.
+
 Changes to Sanitizers
 -
 * HWASan now defaults to detecting use-after-scope bugs.
Index: lldb/docs/use/aarch64-linux.rst
===
--- /dev/null
+++ lldb/docs/use/aarch64-linux.rst
@@ -0,0 +1,190 @@
+Using LLDB On AArch64 Linux
+===
+
+This page explains the details of debugging certain AArch64 extensions using
+LLDB. If something is not mentioned here, it likely works as you would expect.
+
+This is not a replacement for ptrace and Linux Kernel documentation. This covers
+how LLDB has chosen to use those things and how that effects your experience as
+a user.
+
+Scalable Vector Extension (SVE)
+---
+
+See `here `__
+to learn about the extension and `here `__
+for the Linux Kernel's handling of it.
+
+In LLDB you will be able to see the following new registers:
+
+* ``z0-z31`` vector registers, each one has size equal to the vector length.
+* ``p0-p15`` predicate registers, each one containing 1 bit per byte in the vector
+  length. Making each one vector length / 8 sized.
+* ``ffr`` the first fault register, same size as a predicate register.
+* ``vg``, the vector length in "granules". Each granule is 8 bytes.
+
+.. code-block::
+
+   Scalable Vector Extension Registers:
+ vg = 0x0002
+ z0 = {0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 <...> }
+   <...>
+ p0 = {0xff 0xff}
+   <...>
+ffr = {0xff 0xff}
+
+The example above has a vector length of 16 bytes. Within LLDB you will always
+see "vg" as in the ``vg`` register, which is 2 in this case (8*2 = 16).
+Elsewhere you may see "vq" which is the vector length in quadwords (16 bytes)
+elsewhere. Where you see "vl", it is in bytes.
+
+Changing the Vector Length
+..
+
+While you can count the size of a P or Z register, it is intended that ``vg`` be
+used to find the current vector length.
+
+vg can be written. Writing the current vector length changes nothing. If you
+increase the vector length, the registers will likely be reset to 0. If you
+decrease it, LLDB will truncate the Z registers but everything else will be reset
+to 0.
+
+Generally you should not assume that SVE state after changing the vector length
+is in any way the same as it was previously. If you need to do it, do it before
+a function's first use of SVE.
+
+Z Register Presentation
+...
+
+LLDB makes no attempt to predict how an SVE Z register will be used. Even if the
+next SVE instruction (which may some distance away) would use, for example, 32
+bit elements, LLDB prints ``z0`` as single bytes.
+
+If you know what format you are going to use, give a format option::
+
+  (lldb) register read z0 -f uint32_t[]
+  z0 = {0x01010101 0x01010101 0x01010101 0x01010101}
+
+FPSIMD and SVE Modes
+
+
+Prior to the debugee's first use of SVE, it is in what the Linux Kernel terms
+SIMD mode. Only the FPU is being used. In this state LLDB will still show the
+SVE registers however the values are simply the FPU values zero extended up to
+the vector length.
+
+On first access to SVE, the process goes into SVE mode. Now the Z values are
+in the real Z registers.
+
+You can also trigger this with LLDB by writing to an SVE register. Note that
+there is no way to undo this change from within LLDB. However, the debugee
+itself could do something to end up back in SIMD mode.
+
+Expression evaluation
+.
+
+If you evaluate an expression, all SVE state is saved prior to, and restored
+after the expression has been evaluated. Including the register values and
+vector length.
+
+Scalable Matrix Extension (SME)
+---
+
+See `here `__
+to learn about the extension and `h

[Lldb-commits] [PATCH] D158514: [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA regdef

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557014.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158514/new/

https://reviews.llvm.org/D158514

Files:
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py


Index: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
===
--- 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
+++ 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
@@ -125,11 +125,13 @@
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(4, 2)
 self.runCmd("register write vg 2")
+self.check_disabled_za_register(2)
 
 elif stopped_at_line_number == thY_break_line1:
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(2, 3)
 self.runCmd("register write vg 4")
+self.check_disabled_za_register(4)
 
 self.runCmd("thread continue 2")
 self.runCmd("thread continue 3")
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -781,6 +781,11 @@
   std::optional svg_reg_value;
   const RegisterInfo *svg_reg_info = m_reg_info_sp->GetRegisterInfo("svg");
   if (svg_reg_info) {
+// When vg is written it is automatically made invalid. Writing vg will 
also
+// change svg if we're in streaming mode but it will not be made invalid
+// so do this manually so the following read gets the latest svg value.
+SetRegisterIsValid(svg_reg_info, false);
+
 uint32_t svg_reg_num = svg_reg_info->kinds[eRegisterKindLLDB];
 uint64_t reg_value = ReadRegisterAsUnsigned(svg_reg_num, fail_value);
 if (reg_value != fail_value && reg_value <= 32)


Index: lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
===
--- lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
@@ -125,11 +125,13 @@
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(4, 2)
 self.runCmd("register write vg 2")
+self.check_disabled_za_register(2)
 
 elif stopped_at_line_number == thY_break_line1:
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(2, 3)
 self.runCmd("register write vg 4")
+self.check_disabled_za_register(4)
 
 self.runCmd("thread continue 2")
 self.runCmd("thread continue 3")
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -781,6 +781,11 @@
   std::optional svg_reg_value;
   const RegisterInfo *svg_reg_info = m_reg_info_sp->GetRegisterInfo("svg");
   if (svg_reg_info) {
+// When vg is written it is automatically made invalid. Writing vg will also
+// change svg if we're in streaming mode but it will not be made invalid
+// so do this manually so the following read gets the latest svg value.
+SetRegisterIsValid(svg_reg_info, false);
+
 uint32_t svg_reg_num = svg_reg_info->kinds[eRegisterKindLLDB];
 uint64_t reg_value = ReadRegisterAsUnsigned(svg_reg_num, fail_value);
 if (reg_value != fail_value && reg_value <= 32)
___
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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread Muhammad Omair Javaid via Phabricator via lldb-commits
omjavaid accepted this revision.
omjavaid added a comment.
This revision is now accepted and ready to land.

this looks good




Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c:12
+//   (this is just how ptrace works).
+// * Writing to an inactive ZA produces a SIGILL.
+

Is this a kernel requirement or just the way ptrace is implemented.?


Repository:
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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett added inline comments.



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c:12
+//   (this is just how ptrace works).
+// * Writing to an inactive ZA produces a SIGILL.
+

omjavaid wrote:
> Is this a kernel requirement or just the way ptrace is implemented.?
It's an architecture decision, I'll clarify the comment.


Repository:
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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557021.
DavidSpickett added a comment.

Clarify comment about SIGILL from inactive ZA.

Fix some leftover clang-format issues.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159505/new/

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Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,225 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm volatile("pfalse p11.b\n\t");
+  asm vo

[Lldb-commits] [lldb] d99d9d8 - [lldb][AArch64] Add SME's Array Storage (ZA) register

2023-09-19 Thread David Spickett via lldb-commits

Author: David Spickett
Date: 2023-09-19T10:49:57Z
New Revision: d99d9d8b74ffcb8ac418fcdafa750b07f2bd9935

URL: 
https://github.com/llvm/llvm-project/commit/d99d9d8b74ffcb8ac418fcdafa750b07f2bd9935
DIFF: 
https://github.com/llvm/llvm-project/commit/d99d9d8b74ffcb8ac418fcdafa750b07f2bd9935.diff

LOG: [lldb][AArch64] Add SME's Array Storage (ZA) register

Note: This requires later commits for ZA to function properly,
it is split for ease of review. Testing is also in a later patch.

The "Matrix" part of the Scalable Matrix Extension is a new register
"ZA". You can think of this as a square matrix made up of scalable rows,
where each row is one scalable vector long. However it is not made
of the existing scalable vector registers, it is its own register.
Meaning that the size of ZA is the vector length in bytes * the vector
length in bytes.

https://developer.arm.com/documentation/ddi0616/latest/

It uses the streaming vector length, even when streaming mode itself
is not active. For this reason, it's register data header always
includes the streaming vector length.

Due to it's size I've changed kMaxRegisterByteSize to the maximum
possible ZA size and kTypicalRegisterByteSize will be the maximum
possible scalable vector size. Therefore ZA transactions will cause heap
allocations, and non ZA registers will perform exactly as before.

ZA can be enabled and disabled independently of streaming mode. The way
this works in ptrace is different to SVE versus streaming SVE. Writing
NT_ARM_ZA without register data disables ZA, writing NT_ARM_ZA with
register data enables ZA (LLDB will only support the latter, and only
because it's convenient for us to do so).

https://kernel.org/doc/html/v6.2/arm64/sme.html

LLDB does not handle registers that can appear and dissappear at
runtime. Rather than add complexity to implement that, LLDB will
show a block of 0s when ZA is disabled.

The alternative is not only updating the vector lengths every stop,
but every register definition. It's possible but I'm not sure it's worth
pursuing.

Users should refer to the SVCR register (added in later patches)
for the final word on whether ZA is active or not.

Writing to "VG" during streaming mode will change the size of the
streaming sve registers and ZA. LLDB will not attempt to preserve
register values in this case, we'll just read back the undefined
content the kernel shows. This is in line with, as stated, the
kernel ABIs and the prospective software ABIs look like.

ZA is defined as a vector of size SVL*SVL, so the display in lldb
is very basic. A giant block of values. This is no worse than SVE,
just larger. There is scope to improve this but that can wait
until we see some use cases.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D159502

Added: 


Modified: 
lldb/include/lldb/Utility/RegisterValue.h
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
lldb/source/Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h
lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
lldb/source/Plugins/Process/elf-core/RegisterUtilities.h

Removed: 




diff  --git a/lldb/include/lldb/Utility/RegisterValue.h 
b/lldb/include/lldb/Utility/RegisterValue.h
index a86767dfaf512bc..49aaf68be17fc59 100644
--- a/lldb/include/lldb/Utility/RegisterValue.h
+++ b/lldb/include/lldb/Utility/RegisterValue.h
@@ -33,7 +33,9 @@ class RegisterValue {
 // byte AArch64 SVE.
 kTypicalRegisterByteSize = 256u,
 // Anything else we'll heap allocate storage for it.
-kMaxRegisterByteSize = kTypicalRegisterByteSize,
+// 256x256 to support 256 byte AArch64 SME's array storage (ZA) register.
+// Which is a square of vector length x vector length.
+kMaxRegisterByteSize = 256u * 256u,
   };
 
   typedef llvm::SmallVector BytesContainer;

diff  --git 
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp 
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
index df83a833dfaf9d1..8d743a4ff83d22e 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -41,6 +41,10 @@
   0x40b /* ARM Scalable Matrix Extension, Streaming SVE mode */
 #endif
 
+#ifndef NT_ARM_ZA
+#define NT_ARM_ZA 0x40c /* ARM Scalable Matrix Extension, Array Storage */
+#endif
+
 #ifndef NT_ARM_PAC_MASK
 #define NT_ARM_PAC_MASK 0x406 /* Pointer authentication code masks */
 #endif
@@ -90,6 +94,16 @@ 
NativeRegisterContextLinux::CreateH

[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd99d9d8b74ff: [lldb][AArch64] Add SME's Array Storage 
(ZA) register (authored by DavidSpickett).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159502/new/

https://reviews.llvm.org/D159502

Files:
  lldb/include/lldb/Utility/RegisterValue.h
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h

Index: lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
===
--- lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
+++ lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
@@ -119,6 +119,10 @@
 {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_SVE},
 };
 
+constexpr RegsetDesc AARCH64_ZA_Desc[] = {
+{llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_ZA},
+};
+
 constexpr RegsetDesc AARCH64_PAC_Desc[] = {
 {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_PAC_MASK},
 };
Index: lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
===
--- lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
+++ lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
@@ -113,7 +113,7 @@
 m_sve_state = SVEState::Disabled;
 
   if (m_sve_state != SVEState::Disabled)
-m_register_info_up->ConfigureVectorLength(
+m_register_info_up->ConfigureVectorLengthSVE(
 sve::vq_from_vl(m_sve_vector_length));
 }
 
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -30,6 +30,7 @@
 eRegsetMaskPAuth = 4,
 eRegsetMaskMTE = 8,
 eRegsetMaskTLS = 16,
+eRegsetMaskZA = 32,
 eRegsetMaskDynamic = ~1,
   };
 
@@ -106,7 +107,11 @@
 
   void AddRegSetTLS(bool has_tpidr2);
 
-  uint32_t ConfigureVectorLength(uint32_t sve_vq);
+  void AddRegSetSME();
+
+  uint32_t ConfigureVectorLengthSVE(uint32_t sve_vq);
+
+  void ConfigureVectorLengthZA(uint32_t za_vq);
 
   bool VectorSizeIsValid(uint32_t vq) {
 // coverity[unsigned_compare]
@@ -117,6 +122,7 @@
 
   bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }
   bool IsSSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }
+  bool IsZAEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskZA); }
   bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }
   bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }
   bool IsTLSEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); }
@@ -128,6 +134,7 @@
   bool IsPAuthReg(unsigned reg) const;
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
+  bool IsSMEReg(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
@@ -137,6 +144,7 @@
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
+  uint32_t GetSMEOffset() const;
 
 private:
   typedef std::map>
@@ -145,7 +153,10 @@
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
+  uint32_t m_za_reg_vq = eVectorQuadwordAArch64;
 
+  // In normal operation this is const. Only when SVE or SME registers change
+  // size is it either replaced or the content modified.
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 
@@ -164,6 +175,7 @@
   std::vector pauth_regnum_collection;
   std::vector m_mte_regnum_collection;
   std::vector m_tls_regnum_collection;
+  std::vector m_sme_regnum_collection;
 };
 
 #endif
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,6 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
+static lldb_private::RegisterInfo g_register_infos_sme[] =
+// 16 is a default size we will change later.
+{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfU

[Lldb-commits] [lldb] a0768b8 - [lldb][AArch64] Add SME streaming vector length pseduo register

2023-09-19 Thread David Spickett via lldb-commits

Author: David Spickett
Date: 2023-09-19T11:18:27Z
New Revision: a0768b8237ad83a6493a5053e615e0c38d7410ee

URL: 
https://github.com/llvm/llvm-project/commit/a0768b8237ad83a6493a5053e615e0c38d7410ee
DIFF: 
https://github.com/llvm/llvm-project/commit/a0768b8237ad83a6493a5053e615e0c38d7410ee.diff

LOG: [lldb][AArch64] Add SME streaming vector length pseduo register

This adds a register "svg" which mirrors SVE's "vg" register.
This reports the streaming vector length at all times, read
from the ZA ptrace header.

This register is needed first to implement ZA resizing as
the streaming vector length changes. Like vg, svg will be
expedited to the client so it can reconfigure its register
definitions.

The other use is for users to be able to know the streaming
vector length without resorting to counting the (many, many)
bytes in ZA, or temporarily entering streaming mode (which
would be destructive).

Some refactoring has been done so we don't have to recalculate the
register offsets twice.

Testing for this will come in a later patch.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D159503

Added: 


Modified: 
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

Removed: 




diff  --git 
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp 
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
index 8d743a4ff83d22e..7d246eeb5fc9b7e 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -147,6 +147,7 @@ 
NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
   ::memset(&m_sve_header, 0, sizeof(m_sve_header));
   ::memset(&m_pac_mask, 0, sizeof(m_pac_mask));
   ::memset(&m_tls_regs, 0, sizeof(m_tls_regs));
+  ::memset(&m_sme_pseudo_regs, 0, sizeof(m_sme_pseudo_regs));
 
   m_mte_ctrl_reg = 0;
 
@@ -329,30 +330,40 @@ NativeRegisterContextLinux_arm64::ReadRegister(const 
RegisterInfo *reg_info,
 assert(offset < GetMTEControlSize());
 src = (uint8_t *)GetMTEControl() + offset;
   } else if (IsSME(reg)) {
-error = ReadZAHeader();
-if (error.Fail())
-  return error;
+if (GetRegisterInfo().IsSMERegZA(reg)) {
+  error = ReadZAHeader();
+  if (error.Fail())
+return error;
 
-// If there is only a header and no registers, ZA is inactive. Read as 0
-// in this case.
-if (m_za_header.size == sizeof(m_za_header)) {
-  // This will get reconfigured/reset later, so we are safe to use it.
-  // ZA is a square of VL * VL and the ptrace buffer also includes the
-  // header itself.
-  m_za_ptrace_payload.resize(((m_za_header.vl) * (m_za_header.vl)) +
- GetZAHeaderSize());
-  std::fill(m_za_ptrace_payload.begin(), m_za_ptrace_payload.end(), 0);
+  // If there is only a header and no registers, ZA is inactive. Read as 0
+  // in this case.
+  if (m_za_header.size == sizeof(m_za_header)) {
+// This will get reconfigured/reset later, so we are safe to use it.
+// ZA is a square of VL * VL and the ptrace buffer also includes the
+// header itself.
+m_za_ptrace_payload.resize(((m_za_header.vl) * (m_za_header.vl)) +
+   GetZAHeaderSize());
+std::fill(m_za_ptrace_payload.begin(), m_za_ptrace_payload.end(), 0);
+  } else {
+// ZA is active, read the real register.
+error = ReadZA();
+if (error.Fail())
+  return error;
+  }
+
+  // ZA is part of the SME set but uses a seperate member buffer for
+  // storage. Therefore its effective byte offset is always 0 even if it
+  // isn't 0 within the SME register set.
+  src = (uint8_t *)GetZABuffer() + GetZAHeaderSize();
 } else {
-  // ZA is active, read the real register.
-  error = ReadZA();
+  error = ReadSMESVG();
   if (error.Fail())
 return error;
-}
 
-// ZA is part of the SME set but uses a seperate member buffer for storage.
-// Therefore its effective byte offset is always 0 even if it isn't 0 
within
-// the SME register set.
-src = (uint8_t *)GetZABuffer() + GetZAHeaderSize();
+  offset = reg_info->byte_offset - GetRegisterInfo().GetSMEOffset();
+  assert(offset < GetSMEPseudoBufferSize());
+  src = (uint8_t *)GetSMEPseudoBuffer() + offset;
+}
   } else
 return Status("failed - register wasn't recognized to be a GPR or an FPR, "
   "write strategy unknown");
@@ -538,6 +549,9 @@ Status NativeRegisterContextLinux_arm64::WriteRegister(
 
 return WriteTLS();
   } els

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa0768b8237ad: [lldb][AArch64] Add SME streaming vector 
length pseduo register (authored by DavidSpickett).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159503/new/

https://reviews.llvm.org/D159503

Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -135,12 +135,14 @@
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
   bool IsSMEReg(unsigned reg) const;
+  bool IsSMERegZA(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
   uint32_t GetRegNumSVEVG() const;
+  uint32_t GetRegNumSMESVG() const;
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,10 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
-static lldb_private::RegisterInfo g_register_infos_sme[] =
+static lldb_private::RegisterInfo g_register_infos_sme[] = {
+DEFINE_EXTENSION_REG(svg),
 // 16 is a default size we will change later.
-{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
-  KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+ KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
 
 // Number of register sets provided by this context.
 enum {
@@ -96,7 +97,7 @@
   k_num_mte_register = 1,
   // Number of TLS registers is dynamic so it is not listed here.
   k_num_pauth_register = 2,
-  k_num_sme_register = 1,
+  k_num_sme_register = 2,
   k_num_register_sets_default = 2,
   k_num_register_sets = 3
 };
@@ -448,7 +449,7 @@
   // dynamic set and is just 1 register so we make an exception to const here.
   lldb_private::RegisterInfo *non_const_reginfo =
   const_cast(m_register_info_p);
-  non_const_reginfo[m_sme_regnum_collection[0]].byte_size =
+  non_const_reginfo[m_sme_regnum_collection[1]].byte_size =
   (za_vq * 16) * (za_vq * 16);
 }
 
@@ -471,6 +472,10 @@
   return sve_vg == reg;
 }
 
+bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
+  return reg == m_sme_regnum_collection[1];
+}
+
 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
   return llvm::is_contained(pauth_regnum_collection, reg);
 }
@@ -497,6 +502,10 @@
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
 
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const {
+  return m_sme_regnum_collection[0];
+}
+
 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
   return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
 }
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -114,6 +114,12 @@
 
   uint64_t m_mte_ctrl_reg;
 
+  struct sme_pseudo_regs {
+uint64_t svg_reg;
+  };
+
+  struct sme_pseudo_regs m_sme_pseudo_regs;
+
   struct tls_regs {
 uint64_t tpidr_reg;
 // Only valid when SME is present.
@@ -144,6 +150,8 @@
 
   Status WriteTLS();
 
+  Status ReadSMESVG();
+
   Status ReadZAHeader();
 
   Status ReadZA();
@@ -176,6 +184,8 @@
 
   void *GetTLSBuffer() { return &m_tls_regs; }
 
+  void *GetSMEPseudoBuffer() { return &m_sme_pseudo_regs; }
+
   void *GetSVEBuffer() { return m_sve_ptrace_payload.data(); }
 
   size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
@@ -194,6 +204,8 @@
 
   size_t GetTLSBufferSize() { return m_tls_size; }
 
+  size_t GetSMEPseudoBufferSize() { return sizeof(m_sme_pseudo_regs); }
+
   llvm::Error ReadHardwareDebugInfo() override;
 
   llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ lldb/source/Plugins/Process/Linux/NativeRegi

[Lldb-commits] [lldb] 46b961f - [lldb][AArch64] Implement resizing of SME's ZA register

2023-09-19 Thread David Spickett via lldb-commits

Author: David Spickett
Date: 2023-09-19T12:05:22Z
New Revision: 46b961f36bc5b1105356d1701f0c7c9d439be9c8

URL: 
https://github.com/llvm/llvm-project/commit/46b961f36bc5b1105356d1701f0c7c9d439be9c8
DIFF: 
https://github.com/llvm/llvm-project/commit/46b961f36bc5b1105356d1701f0c7c9d439be9c8.diff

LOG: [lldb][AArch64] Implement resizing of SME's ZA register

The size of ZA depends on the streaming vector length regardless
of the active mode. So in addition to vg (which reports the active
mode) we must send the client svg.

Otherwise the mechanics are the same as for non-streaming SVE.
Use the svg value to update the defined size of ZA, accounting
for the fact that ZA is not a single vector but a suqare matrix.

So if svg is 8, a single streaming vector would be 8*8 = 64 bytes.
ZA is that squared, so 64*64 = 4096 bytes.

Testing is included in a later patch.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D159504

Added: 


Modified: 
lldb/include/lldb/Target/DynamicRegisterInfo.h
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
lldb/source/Target/DynamicRegisterInfo.cpp

Removed: 




diff  --git a/lldb/include/lldb/Target/DynamicRegisterInfo.h 
b/lldb/include/lldb/Target/DynamicRegisterInfo.h
index 22ad6335fe43847..fb22885e713d672 100644
--- a/lldb/include/lldb/Target/DynamicRegisterInfo.h
+++ b/lldb/include/lldb/Target/DynamicRegisterInfo.h
@@ -93,6 +93,8 @@ class DynamicRegisterInfo {
 return llvm::iterator_range(m_regs);
   }
 
+  void ConfigureOffsets();
+
 protected:
   // Classes that inherit from DynamicRegisterInfo can see and modify these
   typedef std::vector set_collection;
@@ -116,8 +118,6 @@ class DynamicRegisterInfo {
 
   void Finalize(const lldb_private::ArchSpec &arch);
 
-  void ConfigureOffsets();
-
   reg_collection m_regs;
   set_collection m_sets;
   set_reg_num_collection m_set_reg_nums;

diff  --git 
a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp 
b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
index bd9211bbaad5293..16dde28f6ee5396 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -373,14 +373,14 @@ bool GDBRemoteRegisterContext::WriteRegisterBytes(const 
RegisterInfo *reg_info,
   if (dst == nullptr)
 return false;
 
-  // Code below is specific to AArch64 target in SVE state
+  // Code below is specific to AArch64 target in SVE or SME state
   // If vector granule (vg) register is being written then thread's
   // register context reconfiguration is triggered on success.
-  bool do_reconfigure_arm64_sve = false;
+  // We do not allow writes to SVG so it is not mentioned here.
   const ArchSpec &arch = process->GetTarget().GetArchitecture();
-  if (arch.IsValid() && arch.GetTriple().isAArch64())
-if (strcmp(reg_info->name, "vg") == 0)
-  do_reconfigure_arm64_sve = true;
+  bool do_reconfigure_arm64_sve = arch.IsValid() &&
+  arch.GetTriple().isAArch64() &&
+  (strcmp(reg_info->name, "vg") == 0);
 
   if (data.CopyByteOrderedData(data_offset,// src offset
reg_info->byte_size,// src length
@@ -400,10 +400,10 @@ bool GDBRemoteRegisterContext::WriteRegisterBytes(const 
RegisterInfo *reg_info,
 {m_reg_data.GetDataStart(), size_t(m_reg_data.GetByteSize())}))
 
 {
-  SetAllRegisterValid(false);
-
   if (do_reconfigure_arm64_sve)
-AArch64SVEReconfigure();
+AArch64Reconfigure();
+
+  InvalidateAllRegisters();
 
   return true;
 }
@@ -435,8 +435,10 @@ bool GDBRemoteRegisterContext::WriteRegisterBytes(const 
RegisterInfo *reg_info,
   // This is an actual register, write it
   success = SetPrimordialRegister(reg_info, gdb_comm);
 
-  if (success && do_reconfigure_arm64_sve)
-AArch64SVEReconfigure();
+  if (success && do_reconfigure_arm64_sve) {
+AArch64Reconfigure();
+InvalidateAllRegisters();
+  }
 }
 
 // Check if writing this register will invalidate any other register
@@ -760,37 +762,47 @@ uint32_t 
GDBRemoteRegisterContext::ConvertRegisterKindToRegisterNumber(
   return m_reg_info_sp->ConvertRegisterKindToRegisterNumber(kind, num);
 }
 
-bool GDBRemoteRegisterContext::AArch64SVEReconfigure() {
-  if (!m_reg_info_sp)
-return false;
-
-  const RegisterInfo *reg_info = m_reg_info_sp->GetRegisterInfo("vg");
-  if (!reg_info)
-return false;
-
-  uint64_t fail_value = LLDB_INVALID_ADDRESS;
-  uint32_t vg_reg_num = reg_info->kinds[eRegisterKindLLDB];
-  u

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rG46b961f36bc5: [lldb][AArch64] Implement resizing of 
SME's ZA register (authored by DavidSpickett).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159504/new/

https://reviews.llvm.org/D159504

Files:
  lldb/include/lldb/Target/DynamicRegisterInfo.h
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp

Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -614,10 +614,11 @@
   ConfigureOffsets();
 
   // Check if register info is reconfigurable
-  // AArch64 SVE register set has configurable register sizes
+  // AArch64 SVE register set has configurable register sizes, as does the ZA
+  // register that SME added (the streaming state of SME reuses the SVE state).
   if (arch.GetTriple().isAArch64()) {
 for (const auto ® : m_regs) {
-  if (strcmp(reg.name, "vg") == 0) {
+  if ((strcmp(reg.name, "vg") == 0) || (strcmp(reg.name, "svg") == 0)) {
 m_is_reconfigurable = true;
 break;
   }
Index: lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -1660,17 +1660,18 @@
 gdb_thread->PrivateSetRegisterValue(lldb_regnum, buffer_sp->GetData());
   }
 
-  // AArch64 SVE specific code below calls AArch64SVEReconfigure to update
-  // SVE register sizes and offsets if value of VG register has changed
-  // since last stop.
+  // AArch64 SVE/SME specific code below updates SVE and ZA register sizes and
+  // offsets if value of VG or SVG registers has changed since last stop.
   const ArchSpec &arch = GetTarget().GetArchitecture();
   if (arch.IsValid() && arch.GetTriple().isAArch64()) {
 GDBRemoteRegisterContext *reg_ctx_sp =
 static_cast(
 gdb_thread->GetRegisterContext().get());
 
-if (reg_ctx_sp)
-  reg_ctx_sp->AArch64SVEReconfigure();
+if (reg_ctx_sp) {
+  reg_ctx_sp->AArch64Reconfigure();
+  reg_ctx_sp->InvalidateAllRegisters();
+}
   }
 
   thread_sp->SetName(thread_name.empty() ? nullptr : thread_name.c_str());
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
@@ -39,6 +39,7 @@
   ~GDBRemoteDynamicRegisterInfo() override = default;
 
   void UpdateARM64SVERegistersInfos(uint64_t vg);
+  void UpdateARM64SMERegistersInfos(uint64_t svg);
 };
 
 class GDBRemoteRegisterContext : public RegisterContext {
@@ -77,7 +78,8 @@
   uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,
uint32_t num) override;
 
-  bool AArch64SVEReconfigure();
+  // Reconfigure variable sized registers for AArch64 SVE and SME.
+  void AArch64Reconfigure();
 
 protected:
   friend class ThreadGDBRemote;
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -373,14 +373,14 @@
   if (dst == nullptr)
 return false;
 
-  // Code below is specific to AArch64 target in SVE state
+  // Code below is specific to AArch64 target in SVE or SME state
   // If vector granule (vg) register is being written then thread's
   // register context reconfiguration is triggered on success.
-  bool do_reconfigure_arm64_sve = false;
+  // We do not allow writes to SVG so it is not mentioned here.
   const ArchSpec &arch = process->GetTarget().GetArchitecture();
-  if (arch.IsValid() && arch.GetTriple().isAArch64())
-if (strcmp(reg_info->name, "vg") == 0)
-  do_reconfigure_arm64_sve = true;
+  bool do_reconfigure_arm64_sve = arch.IsValid() &&
+  arch.GetTriple().isAArch64() &&
+  (strcmp(reg_info->name, "vg") == 0);
 
   if (data.CopyByteOrderedData(data_offset,// src offset
reg_info->byte_size,// src length
@@ -400,10 +400,10 @@
 {m_reg_data.GetDataStart(), size_t(m_reg_data.GetByteSize())}))
 
 {
-  SetAllRegisterValid(false);
-
   if (do_reconfigure_arm64_sve)
-AArch64SVEReconfigure();
+ 

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett updated this revision to Diff 557034.
DavidSpickett added a comment.

Fix some python formatting.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159505/new/

https://reviews.llvm.org/D159505

Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,225 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm volatile("pfalse p11.b\n\t");
+  asm volatile("pfalse p12.b\n\t");
+  asm volatile("pfalse p13.b\n

[Lldb-commits] [lldb] e96adfd - [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread David Spickett via lldb-commits

Author: David Spickett
Date: 2023-09-19T12:18:23Z
New Revision: e96adfd0dbcf84c27be2087371890f4228890609

URL: 
https://github.com/llvm/llvm-project/commit/e96adfd0dbcf84c27be2087371890f4228890609
DIFF: 
https://github.com/llvm/llvm-project/commit/e96adfd0dbcf84c27be2087371890f4228890609.diff

LOG: [lldb][AArch64] Add testing for SME's ZA and SVG registers

An SME enabled program has the following extra state:
* Streaming mode or non-streaming mode.
* ZA enabled or disabled.
* The active vector length.

Covering the transition between all possible states and all other
possible states is not viable, therefore the testing added here is a cross
section of that, all of which found real bugs in LLDB and the Linux
Kernel during development.

Many of those transitions will not be possible via LLDB
(e.g. disabling ZA) and many more are possible but unlikely to be
used in normal use.

Added testing:
* TestSVEThreadedDynamic now checks for correct SVG values.
* New test TestZAThreadedDynamic creates 3 threads with different ZA sizes
  and states and switches between them verifying the register value
  (derived from the existing threaded SVE test).
* New test TestZARegisterSaveRestore starts in a given SME state, runs a
  set of expressions in various orders, then checks that the original
  state has been restored.
* TestArm64DynamicRegsets has ZA and SVG checks added, including writing
  to ZA to enable it.

Running these tests will as usual require QEMU as there is no
real SME hardware available at this time, and a very recent
kernel.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D159505

Added: 

lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile

lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py

lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c

lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile

lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Modified: 

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py

Removed: 




diff  --git 
a/lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
 
b/lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
index d3f53f0e95dfcb5..4f4da2b5223fb15 100644
--- 
a/lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
+++ 
b/lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
@@ -70,15 +70,13 @@ def sve_regs_read_dynamic(self, sve_registers):
 self.runCmd("register write ffr " + "'" + p_regs_value + "'")
 self.expect("register read ffr", substrs=[p_regs_value])
 
-@no_debug_info_test
-@skipIf(archs=no_match(["aarch64"]))
-@skipIf(oslist=no_match(["linux"]))
-def test_aarch64_dynamic_regset_config(self):
-"""Test AArch64 Dynamic Register sets configuration."""
+def setup_register_config_test(self, run_args=None):
 self.build()
 self.line = line_number("main.c", "// Set a break point here.")
 
 exe = self.getBuildArtifact("a.out")
+if run_args is not None:
+self.runCmd("settings set target.run-args " + run_args)
 self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
 
 lldbutil.run_break_set_by_file_and_line(
@@ -92,12 +90,16 @@ def test_aarch64_dynamic_regset_config(self):
 substrs=["stop reason = breakpoint 1."],
 )
 
-target = self.dbg.GetSelectedTarget()
-process = target.GetProcess()
-thread = process.GetThreadAtIndex(0)
-currentFrame = thread.GetFrameAtIndex(0)
+return self.thread().GetSelectedFrame().GetRegisters()
+
+@no_debug_info_test
+@skipIf(archs=no_match(["aarch64"]))
+@skipIf(oslist=no_match(["linux"]))
+def test_aarch64_dynamic_regset_config(self):
+"""Test AArch64 Dynamic Register sets configuration."""
+register_sets = self.setup_register_config_test()
 
-for registerSet in currentFrame.GetRegisters():
+for registerSet in register_sets:
 if "Scalable Vector Extension Registers" in registerSet.GetName():
 self.assertTrue(
 self.isAArch64SVE(),
@@ -120,6 +122,19 @@ def test_aarch64_dynamic_regset_config(self):
 )
 self.expect("register read data_mask", substrs=["data_mask = 
0x"])
 self.expect("register read code_mask", substrs=

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe96adfd0dbcf: [lldb][AArch64] Add testing for SME's ZA 
and SVG registers (authored by DavidSpickett).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159505/new/

https://reviews.llvm.org/D159505

Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,225 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm volatile("pfals

[Lldb-commits] [lldb] [LLDB] Add a setting for printing ValueObject hex values without leading zeroes (PR #66548)

2023-09-19 Thread Walter Erquinigo via lldb-commits

walter-erquinigo wrote:

Thanks, man!

On Tue, Sep 19, 2023, 4:53 AM David Spickett ***@***.***>
wrote:

> 9568601
> 
>
> —
> Reply to this email directly, view it on GitHub
> ,
> or unsubscribe
> 
> .
> You are receiving this because you modified the open/close state.Message
> ID: ***@***.***>
>


https://github.com/llvm/llvm-project/pull/66548
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[Lldb-commits] [lldb] [lldb][AArch64] Add release notes and documentation for SME (PR #66767)

2023-09-19 Thread David Spickett via lldb-commits

https://github.com/DavidSpickett created 
https://github.com/llvm/llvm-project/pull/66767

This adds a release note for all the SME support now in LLDB and a page where I 
have documented the user experience (for want of a better term) when using SVE 
and SME.

This includes things like which mode transitions can or cannot be triggered 
from within LLDB. I hope this will serve to A: document what I've implemented 
and B: be a user's guide to these extensions.

(though it is not a design document, read the commits and code for that sort of 
detail)

Differential Revision: https://reviews.llvm.org/D158506

>From 7397eafda815fb4c53b45d09b47911a05b71e843 Mon Sep 17 00:00:00 2001
From: David Spickett 
Date: Tue, 22 Aug 2023 11:12:23 +0100
Subject: [PATCH] [lldb][AArch64] Add release notes and documentation for SME

This adds a release note for all the SME support now in LLDB
and a page where I have documented the user experience (for want
of a better term) when using SVE and SME.

This includes things like which mode transitions can or cannot
be triggered from within LLDB. I hope this will serve to A: document
what I've implemented and B: be a user's guide to these extensions.

(though it is not a design document, read the commits and code
for that sort of detail)

Differential Revision: https://reviews.llvm.org/D158506
---
 lldb/docs/index.rst |   1 +
 lldb/docs/use/aarch64-linux.rst | 190 
 llvm/docs/ReleaseNotes.rst  |   4 +
 3 files changed, 195 insertions(+)
 create mode 100644 lldb/docs/use/aarch64-linux.rst

diff --git a/lldb/docs/index.rst b/lldb/docs/index.rst
index 2eb57cefbd883ea..2fff25b27b974ea 100644
--- a/lldb/docs/index.rst
+++ b/lldb/docs/index.rst
@@ -125,6 +125,7 @@ interesting areas to contribute to lldb.
use/qemu-testing
use/intel_pt
use/ondemand
+   use/aarch64-linux
use/troubleshooting
use/links
Man Page 
diff --git a/lldb/docs/use/aarch64-linux.rst b/lldb/docs/use/aarch64-linux.rst
new file mode 100644
index 000..850a5e5a5837cda
--- /dev/null
+++ b/lldb/docs/use/aarch64-linux.rst
@@ -0,0 +1,190 @@
+Using LLDB On AArch64 Linux
+===
+
+This page explains the details of debugging certain AArch64 extensions using
+LLDB. If something is not mentioned here, it likely works as you would expect.
+
+This is not a replacement for ptrace and Linux Kernel documentation. This 
covers
+how LLDB has chosen to use those things and how that effects your experience as
+a user.
+
+Scalable Vector Extension (SVE)
+---
+
+See `here 
`__
+to learn about the extension and `here 
`__
+for the Linux Kernel's handling of it.
+
+In LLDB you will be able to see the following new registers:
+
+* ``z0-z31`` vector registers, each one has size equal to the vector length.
+* ``p0-p15`` predicate registers, each one containing 1 bit per byte in the 
vector
+  length. Making each one vector length / 8 sized.
+* ``ffr`` the first fault register, same size as a predicate register.
+* ``vg``, the vector length in "granules". Each granule is 8 bytes.
+
+.. code-block::
+
+   Scalable Vector Extension Registers:
+ vg = 0x0002
+ z0 = {0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 <...> }
+   <...>
+ p0 = {0xff 0xff}
+   <...>
+ffr = {0xff 0xff}
+
+The example above has a vector length of 16 bytes. Within LLDB you will always
+see "vg" as in the ``vg`` register, which is 2 in this case (8*2 = 16).
+Elsewhere you may see "vq" which is the vector length in quadwords (16 bytes)
+elsewhere. Where you see "vl", it is in bytes.
+
+Changing the Vector Length
+..
+
+While you can count the size of a P or Z register, it is intended that ``vg`` 
be
+used to find the current vector length.
+
+vg can be written. Writing the current vector length changes nothing. If you
+increase the vector length, the registers will likely be reset to 0. If you
+decrease it, LLDB will truncate the Z registers but everything else will be 
reset
+to 0.
+
+Generally you should not assume that SVE state after changing the vector length
+is in any way the same as it was previously. If you need to do it, do it before
+a function's first use of SVE.
+
+Z Register Presentation
+...
+
+LLDB makes no attempt to predict how an SVE Z register will be used. Even if 
the
+next SVE instruction (which may some distance away) would use, for example, 32
+bit elements, LLDB prints ``z0`` as single bytes.
+
+If you know what format you are going to use, give a format option::
+
+  (lldb) register read z0 -f uint32_t[]
+  z0 = {0x01010101 0x01010101 0x01010101 0x01010101}
+
+FPSIMD and SVE Modes
+
+
+Prior to the debugee's first use of SVE, it is in what the Linux Kernel terms

[Lldb-commits] [lldb] [lldb][AArch64] Add release notes and documentation for SME (PR #66767)

2023-09-19 Thread David Spickett via lldb-commits

DavidSpickett wrote:

Replaces https://reviews.llvm.org/D158506.

https://github.com/llvm/llvm-project/pull/66767
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[Lldb-commits] [PATCH] D158506: [lldb][AArch64] Add release notes and documentation for SME

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett abandoned this revision.
DavidSpickett added a comment.

Moved to https://github.com/llvm/llvm-project/pull/66767.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158506/new/

https://reviews.llvm.org/D158506

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[Lldb-commits] [lldb] [lldb][AArch64] Add release notes and documentation for SME (PR #66767)

2023-09-19 Thread via lldb-commits

llvmbot wrote:




@llvm/pr-subscribers-lldb


Changes

This adds a release note for all the SME support now in LLDB and a page where I 
have documented the user experience (for want of a better term) when using SVE 
and SME.

This includes things like which mode transitions can or cannot be triggered 
from within LLDB. I hope this will serve to A: document what I've implemented 
and B: be a user's guide to these extensions.

(though it is not a design document, read the commits and code for that sort of 
detail)

Differential Revision: https://reviews.llvm.org/D158506

---
Full diff: https://github.com/llvm/llvm-project/pull/66767.diff


3 Files Affected:

- (modified) lldb/docs/index.rst (+1) 
- (added) lldb/docs/use/aarch64-linux.rst (+190) 
- (modified) llvm/docs/ReleaseNotes.rst (+4) 


``diff
diff --git a/lldb/docs/index.rst b/lldb/docs/index.rst
index 2eb57cefbd883ea..2fff25b27b974ea 100644
--- a/lldb/docs/index.rst
+++ b/lldb/docs/index.rst
@@ -125,6 +125,7 @@ interesting areas to contribute to lldb.
use/qemu-testing
use/intel_pt
use/ondemand
+   use/aarch64-linux
use/troubleshooting
use/links
Man Page 
diff --git a/lldb/docs/use/aarch64-linux.rst b/lldb/docs/use/aarch64-linux.rst
new file mode 100644
index 000..850a5e5a5837cda
--- /dev/null
+++ b/lldb/docs/use/aarch64-linux.rst
@@ -0,0 +1,190 @@
+Using LLDB On AArch64 Linux
+===
+
+This page explains the details of debugging certain AArch64 extensions using
+LLDB. If something is not mentioned here, it likely works as you would expect.
+
+This is not a replacement for ptrace and Linux Kernel documentation. This 
covers
+how LLDB has chosen to use those things and how that effects your experience as
+a user.
+
+Scalable Vector Extension (SVE)
+---
+
+See `here 
`__
+to learn about the extension and `here 
`__
+for the Linux Kernel's handling of it.
+
+In LLDB you will be able to see the following new registers:
+
+* ``z0-z31`` vector registers, each one has size equal to the vector length.
+* ``p0-p15`` predicate registers, each one containing 1 bit per byte in the 
vector
+  length. Making each one vector length / 8 sized.
+* ``ffr`` the first fault register, same size as a predicate register.
+* ``vg``, the vector length in "granules". Each granule is 8 bytes.
+
+.. code-block::
+
+   Scalable Vector Extension Registers:
+ vg = 0x0002
+ z0 = {0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 <...> }
+   <...>
+ p0 = {0xff 0xff}
+   <...>
+ffr = {0xff 0xff}
+
+The example above has a vector length of 16 bytes. Within LLDB you will always
+see "vg" as in the ``vg`` register, which is 2 in this case (8*2 = 16).
+Elsewhere you may see "vq" which is the vector length in quadwords (16 bytes)
+elsewhere. Where you see "vl", it is in bytes.
+
+Changing the Vector Length
+..
+
+While you can count the size of a P or Z register, it is intended that ``vg`` 
be
+used to find the current vector length.
+
+vg can be written. Writing the current vector length changes nothing. If you
+increase the vector length, the registers will likely be reset to 0. If you
+decrease it, LLDB will truncate the Z registers but everything else will be 
reset
+to 0.
+
+Generally you should not assume that SVE state after changing the vector length
+is in any way the same as it was previously. If you need to do it, do it before
+a function's first use of SVE.
+
+Z Register Presentation
+...
+
+LLDB makes no attempt to predict how an SVE Z register will be used. Even if 
the
+next SVE instruction (which may some distance away) would use, for example, 32
+bit elements, LLDB prints ``z0`` as single bytes.
+
+If you know what format you are going to use, give a format option::
+
+  (lldb) register read z0 -f uint32_t[]
+  z0 = {0x01010101 0x01010101 0x01010101 0x01010101}
+
+FPSIMD and SVE Modes
+
+
+Prior to the debugee's first use of SVE, it is in what the Linux Kernel terms
+SIMD mode. Only the FPU is being used. In this state LLDB will still show the
+SVE registers however the values are simply the FPU values zero extended up to
+the vector length.
+
+On first access to SVE, the process goes into SVE mode. Now the Z values are
+in the real Z registers.
+
+You can also trigger this with LLDB by writing to an SVE register. Note that
+there is no way to undo this change from within LLDB. However, the debugee
+itself could do something to end up back in SIMD mode.
+
+Expression evaluation
+.
+
+If you evaluate an expression, all SVE state is saved prior to, and restored
+after the expression has been evaluated. Including the register values and
+vector length.
+
+Scalable Matrix Extension (SME)
+-

[Lldb-commits] [lldb] [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA regdef (PR #66768)

2023-09-19 Thread David Spickett via lldb-commits

https://github.com/DavidSpickett created 
https://github.com/llvm/llvm-project/pull/66768

This fixes a bug where writing vg during streaming mode could prevent you 
reading za directly afterwards.

vg is invalided when the write happens. SVE is reconfigured by reading back the 
new value from the remote. So far so good.

For SME, we read SVG which in some situations appeared to remain valid but have 
a value of 0 (perhaps it had never been read). This meant lldb expected the 
size of za to be 0 bytes and rejected the remote's response.

To fix this, invalidate svg before reconfiguring. This ensures that the value 
used is the latest one from the remote.

The bug may depend on timing, I could not find a consistent way to trigger it. 
I originally found it when checking whether za is disabled after a vg change, 
so I've added checks for that to TestZAThreadedDynamic.

Differential Revision: https://reviews.llvm.org/D158514

>From f4915dd9acd3b819a9745dee1d410b465edd57c4 Mon Sep 17 00:00:00 2001
From: David Spickett 
Date: Tue, 22 Aug 2023 14:42:35 +0100
Subject: [PATCH] [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA
 regdef

This fixes a bug where writing vg during streaming mode
could prevent you reading za directly afterwards.

vg is invalided when the write happens. SVE is reconfigured
by reading back the new value from the remote. So far so good.

For SME, we read SVG which in some situations appeared to remain
valid but have a value of 0 (perhaps it had never been read).
This meant lldb expected the size of za to be 0 bytes and
rejected the remote's response.

To fix this, invalidate svg before reconfiguring. This ensures
that the value used is the latest one from the remote.

The bug may depend on timing, I could not find a consistent way
to trigger it. I originally found it when checking whether za
is disabled after a vg change, so I've added checks for that
to TestZAThreadedDynamic.

Differential Revision: https://reviews.llvm.org/D158514
---
 .../Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp  | 5 +
 .../za_dynamic_resize/TestZAThreadedDynamic.py   | 2 ++
 2 files changed, 7 insertions(+)

diff --git 
a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp 
b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
index 16dde28f6ee5396..13365dc312f5b66 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -781,6 +781,11 @@ void GDBRemoteRegisterContext::AArch64Reconfigure() {
   std::optional svg_reg_value;
   const RegisterInfo *svg_reg_info = m_reg_info_sp->GetRegisterInfo("svg");
   if (svg_reg_info) {
+// When vg is written it is automatically made invalid. Writing vg will 
also
+// change svg if we're in streaming mode but it will not be made invalid
+// so do this manually so the following read gets the latest svg value.
+SetRegisterIsValid(svg_reg_info, false);
+
 uint32_t svg_reg_num = svg_reg_info->kinds[eRegisterKindLLDB];
 uint64_t reg_value = ReadRegisterAsUnsigned(svg_reg_num, fail_value);
 if (reg_value != fail_value && reg_value <= 32)
diff --git 
a/lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
 
b/lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
index 65d1071c26b2a34..d2a26ce71bde1d8 100644
--- 
a/lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
+++ 
b/lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
@@ -125,11 +125,13 @@ def za_test_impl(self, enable_za):
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(4, 2)
 self.runCmd("register write vg 2")
+self.check_disabled_za_register(2)
 
 elif stopped_at_line_number == thY_break_line1:
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(2, 3)
 self.runCmd("register write vg 4")
+self.check_disabled_za_register(4)
 
 self.runCmd("thread continue 2")
 self.runCmd("thread continue 3")

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[Lldb-commits] [lldb] [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA regdef (PR #66768)

2023-09-19 Thread David Spickett via lldb-commits

DavidSpickett wrote:

Replaces https://reviews.llvm.org/D158514.

https://github.com/llvm/llvm-project/pull/66768
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[Lldb-commits] [PATCH] D158514: [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA regdef

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett abandoned this revision.
DavidSpickett added a comment.

Moved to https://github.com/llvm/llvm-project/pull/66768.


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[Lldb-commits] [lldb] [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA regdef (PR #66768)

2023-09-19 Thread via lldb-commits

llvmbot wrote:




@llvm/pr-subscribers-lldb


Changes

This fixes a bug where writing vg during streaming mode could prevent you 
reading za directly afterwards.

vg is invalided when the write happens. SVE is reconfigured by reading back the 
new value from the remote. So far so good.

For SME, we read SVG which in some situations appeared to remain valid but have 
a value of 0 (perhaps it had never been read). This meant lldb expected the 
size of za to be 0 bytes and rejected the remote's response.

To fix this, invalidate svg before reconfiguring. This ensures that the value 
used is the latest one from the remote.

The bug may depend on timing, I could not find a consistent way to trigger it. 
I originally found it when checking whether za is disabled after a vg change, 
so I've added checks for that to TestZAThreadedDynamic.

Differential Revision: https://reviews.llvm.org/D158514

---
Full diff: https://github.com/llvm/llvm-project/pull/66768.diff


2 Files Affected:

- (modified) 
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp (+5) 
- (modified) 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
 (+2) 


``diff
diff --git 
a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp 
b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
index 16dde28f6ee5396..13365dc312f5b66 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -781,6 +781,11 @@ void GDBRemoteRegisterContext::AArch64Reconfigure() {
   std::optional svg_reg_value;
   const RegisterInfo *svg_reg_info = m_reg_info_sp->GetRegisterInfo("svg");
   if (svg_reg_info) {
+// When vg is written it is automatically made invalid. Writing vg will 
also
+// change svg if we're in streaming mode but it will not be made invalid
+// so do this manually so the following read gets the latest svg value.
+SetRegisterIsValid(svg_reg_info, false);
+
 uint32_t svg_reg_num = svg_reg_info->kinds[eRegisterKindLLDB];
 uint64_t reg_value = ReadRegisterAsUnsigned(svg_reg_num, fail_value);
 if (reg_value != fail_value && reg_value <= 32)
diff --git 
a/lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
 
b/lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
index 65d1071c26b2a34..d2a26ce71bde1d8 100644
--- 
a/lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
+++ 
b/lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
@@ -125,11 +125,13 @@ def za_test_impl(self, enable_za):
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(4, 2)
 self.runCmd("register write vg 2")
+self.check_disabled_za_register(2)
 
 elif stopped_at_line_number == thY_break_line1:
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(2, 3)
 self.runCmd("register write vg 4")
+self.check_disabled_za_register(4)
 
 self.runCmd("thread continue 2")
 self.runCmd("thread continue 3")

``




https://github.com/llvm/llvm-project/pull/66768
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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

2023-09-19 Thread Ted Woodward via Phabricator via lldb-commits
ted updated this revision to Diff 557049.
ted added a comment.

Fix crash when there was no process.
Remove bugs in function call setup when using IR interpreter.
Change flag tests to use lldb_private::Flags for flags testing


Repository:
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Files:
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1550,6 +1550,8 @@
 ArchSpec::eRISCV_float_abi_quad)
   features_str += "+f,+d,+q,";
 // FIXME: how do we detect features such as `+a`, `+m`?
+// Turn them on by default now, since everyone seems to use them
+features_str += "+a,+m,";
   }
 
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,12 @@
+add_lldb_library(lldbPluginABIRISCV PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+lldbPluginProcessUtility
+  LINK_COMPONENTS
+Support
+TargetParser
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,131 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+// Other libraries and framework includes
+#include 
+
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::RegInfoBasedABI {
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override;
+
+  // Special thread plan for GDB style non-jit function calls.
+  bool
+  PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+ lldb::addr_t functionAddress, lldb::addr_t returnAddress,
+ llvm::Type &prototype,
+ llvm::ArrayRef args) const override;
+
+  bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override;
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+   lldb::ValueObjectSP &new_value) override;
+
+  lldb::ValueObjectSP
+  GetReturnValueObjectImpl(lldb_private::Thread &thread,
+   lldb_private::CompilerType &type) const override;
+
+  // Specialized to work with llvm IR types.
+  lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread &thread,
+   llvm::Type &type) const override;
+
+  bool
+  CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+  bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+  bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+  bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned, unless the E ABI is used
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+lldb_private::Flags arch_flags = arch.GetFlags();
+if (arch_flags.Test(lldb_private::ArchSpec::eRISCV_rve))
+  return (cfa & 0x3ull) == 0;
+return (cfa & 0xfull) == 0;
+  }
+
+  void SetIsRV64(bool is_rv64) { m_is_rv64 = is_rv64; }
+
+  bool CodeAddressIsValid(lldb::addr_t pc) override {
+// Calls can use the least significant bit to store auxiliary information,
+// so no strict check is done for alignment.
+
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+
+//  & 2 set is a fault if C extension is not used.
+l

[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett added inline comments.



Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:262
+  // NOTE: It's unsafe to iterate through LLDB_REGNUM_GENERICs
+  // But the a registers re sequential in the RISC-V register space
+  ++reg_index;

Seems like `are` got split up here.



Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:203
+  size_t reg_size = m_is_rv64 ? 8 : 4;
+  size_t word_size = m_is_rv64 ? 8 : 4;
+  // Push host data onto target.

DavidSpickett wrote:
> word_size = reg_size; ?
This.


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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

2023-09-19 Thread David Spickett via Phabricator via lldb-commits
DavidSpickett added a comment.

FYI I will be away next week, and the week after that Phab is supposed to be 
made read-only. So look to @jasonmolenda to approve in that time frame, or we 
can take this to a PR after that.




Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:133
+ABISysV_riscv::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+  if (process_sp) {
+process_sp->SetCanInterpretFunctionCalls(true);

Do you know why this check is needed? Is there a specific test that hits this?

The other ABI plugins seem to sidestep this by not having to `->` on it, but 
that could just be luck.


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[Lldb-commits] [lldb] [InstCombine] Canonicalize `and(zext(A), B)` into `select A, B & 1, 0` (PR #66740)

2023-09-19 Thread via lldb-commits

goldsteinn wrote:

Created: https://github.com/llvm/llvm-project/pull/66793 which fixes the 
backend regression this can cause.

https://github.com/llvm/llvm-project/pull/66740
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[Lldb-commits] [lldb] [lldb][Docs] Document our major differences from the LLVM style (PR #66345)

2023-09-19 Thread Dave Lee via lldb-commits


@@ -18,19 +18,45 @@ Please refer to the `LLVM Developer Policy
 authoring and uploading a patch. LLDB differs from the LLVM Developer
 Policy in the following respects.
 
- - **Test infrastructure**: Like LLVM it is  important to submit tests with 
your
-   patches, but note that LLDB uses a different system for tests. Refer to the
-   `test documentation `_ for more details and the ``lldb/test``
-   folder on disk for examples.
-
- - **Coding Style**: LLDB's code style differs from
-   `LLVM's coding style `_.
-   Unfortunately there is no document describing the differences. Please be
-   consistent with the existing code.
-
 For anything not explicitly listed here, assume that LLDB follows the LLVM
 policy.
 
+Coding Style
+
+
+LLDB's code style differs from `LLVM's coding style 
`_
+in a few ways. The 2 main ones are:
+
+* `Variable and function naming 
`_:
+
+  * Variables are ``snake_case``.
+
+  * Functions and methods are ``UpperCamelCase``.
+
+  * Static, global and member variables have ``s_``, ``g_`` and ``_m``

kastiglione wrote:

typo: `_m` should be `m_`.

https://github.com/llvm/llvm-project/pull/66345
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[Lldb-commits] [lldb] [lldb][NFCI] Remove unneeded ConstString from intel-pt plugin (PR #66721)

2023-09-19 Thread Alex Langford via lldb-commits

https://github.com/bulbazord closed 
https://github.com/llvm/llvm-project/pull/66721
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[Lldb-commits] [lldb] 45e6e4d - [lldb][NFCI] Remove unneeded ConstString from intel-pt plugin (#66721)

2023-09-19 Thread via lldb-commits

Author: Alex Langford
Date: 2023-09-19T10:49:38-07:00
New Revision: 45e6e4d70e1e5bdd7d9f04dfd0f4cc8798bcde0c

URL: 
https://github.com/llvm/llvm-project/commit/45e6e4d70e1e5bdd7d9f04dfd0f4cc8798bcde0c
DIFF: 
https://github.com/llvm/llvm-project/commit/45e6e4d70e1e5bdd7d9f04dfd0f4cc8798bcde0c.diff

LOG: [lldb][NFCI] Remove unneeded ConstString from intel-pt plugin (#66721)

This is a follow-up to 14d95b26aee0ac0ac8a70252e8a3c7a986e0e812. I would
have changed it in that commit, but I don't build the intel-pt plugin so
I didn't see this until later.

Added: 


Modified: 
lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.cpp
lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.h

Removed: 




diff  --git a/lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.cpp 
b/lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.cpp
index bcac731713bb24b..015faa89fcfada8 100644
--- a/lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.cpp
+++ b/lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.cpp
@@ -48,8 +48,8 @@ enum {
 #include "TraceIntelPTPropertiesEnum.inc"
 };
 
-ConstString TraceIntelPT::PluginProperties::GetSettingName() {
-  return ConstString(TraceIntelPT::GetPluginNameStatic());
+llvm::StringRef TraceIntelPT::PluginProperties::GetSettingName() {
+  return TraceIntelPT::GetPluginNameStatic();
 }
 
 TraceIntelPT::PluginProperties::PluginProperties() : Properties() {

diff  --git a/lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.h 
b/lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.h
index 20faabdce790241..da9cefe9ed95d67 100644
--- a/lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.h
+++ b/lldb/source/Plugins/Trace/intel-pt/TraceIntelPT.h
@@ -26,7 +26,7 @@ class TraceIntelPT : public Trace {
   /// Properties to be used with the `settings` command.
   class PluginProperties : public Properties {
   public:
-static ConstString GetSettingName();
+static llvm::StringRef GetSettingName();
 
 PluginProperties();
 



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[Lldb-commits] [lldb] d5a62b7 - [lldb][NFCI] Remove unneccessary allocation in ScriptInterpreterPythonImpl::GetSyntheticTypeName (#66724)

2023-09-19 Thread via lldb-commits

Author: Alex Langford
Date: 2023-09-19T10:49:53-07:00
New Revision: d5a62b78b8ae1856e9eecf7d034ce6a1fbc0a76a

URL: 
https://github.com/llvm/llvm-project/commit/d5a62b78b8ae1856e9eecf7d034ce6a1fbc0a76a
DIFF: 
https://github.com/llvm/llvm-project/commit/d5a62b78b8ae1856e9eecf7d034ce6a1fbc0a76a.diff

LOG: [lldb][NFCI] Remove unneccessary allocation in 
ScriptInterpreterPythonImpl::GetSyntheticTypeName (#66724)

Instead of copying memory out of the PythonString (via a std::string)
and then using that to create a ConstString, it would make more sense to
just create the ConstString from the original StringRef in the first
place.

Added: 


Modified: 
lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp

Removed: 




diff  --git 
a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp 
b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
index 3fbab6bacec7dbb..6280084ca806828 100644
--- a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
+++ b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
@@ -2438,24 +2438,11 @@ ConstString 
ScriptInterpreterPythonImpl::GetSyntheticTypeName(
   }
 
   PythonObject py_return = std::move(expected_py_return.get());
+  if (!py_return.IsAllocated() || !PythonString::Check(py_return.get()))
+return {};
 
-  ConstString ret_val;
-  bool got_string = false;
-  std::string buffer;
-
-  if (py_return.IsAllocated() && PythonString::Check(py_return.get())) {
-PythonString py_string(PyRefType::Borrowed, py_return.get());
-llvm::StringRef return_data(py_string.GetString());
-if (!return_data.empty()) {
-  buffer.assign(return_data.data(), return_data.size());
-  got_string = true;
-}
-  }
-
-  if (got_string)
-ret_val.SetCStringWithLength(buffer.c_str(), buffer.size());
-
-  return ret_val;
+  PythonString type_name(PyRefType::Borrowed, py_return.get());
+  return ConstString(py_string.GetString());
 }
 
 bool ScriptInterpreterPythonImpl::RunScriptFormatKeyword(



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[Lldb-commits] [lldb] [lldb][NFCI] Remove unneccessary allocation in ScriptInterpreterPythonImpl::GetSyntheticTypeName (PR #66724)

2023-09-19 Thread Alex Langford via lldb-commits

https://github.com/bulbazord closed 
https://github.com/llvm/llvm-project/pull/66724
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[Lldb-commits] [lldb] [lldb][NFCI] Remove unneccessary allocation in ScriptInterpreterPythonImpl::GetSyntheticTypeName (PR #66724)

2023-09-19 Thread Alex Langford via lldb-commits

bulbazord wrote:

I'm aware this has broken the build, working on it. Thanks for your patience.

https://github.com/llvm/llvm-project/pull/66724
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[Lldb-commits] [lldb] f1097e8 - [lldb] Fix build after d5a62b78b8ae

2023-09-19 Thread Alex Langford via lldb-commits

Author: Alex Langford
Date: 2023-09-19T10:56:13-07:00
New Revision: f1097e88d22511f3ec96386ca165b75bb75aaa7a

URL: 
https://github.com/llvm/llvm-project/commit/f1097e88d22511f3ec96386ca165b75bb75aaa7a
DIFF: 
https://github.com/llvm/llvm-project/commit/f1097e88d22511f3ec96386ca165b75bb75aaa7a.diff

LOG: [lldb] Fix build after d5a62b78b8ae

I renamed something but forgot to update the uses of it. Minor thinko.

Added: 


Modified: 
lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp

Removed: 




diff  --git 
a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp 
b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
index 6280084ca806828..0d6ff6660acd3db 100644
--- a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
+++ b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
@@ -2442,7 +2442,7 @@ ConstString 
ScriptInterpreterPythonImpl::GetSyntheticTypeName(
 return {};
 
   PythonString type_name(PyRefType::Borrowed, py_return.get());
-  return ConstString(py_string.GetString());
+  return ConstString(type_name.GetString());
 }
 
 bool ScriptInterpreterPythonImpl::RunScriptFormatKeyword(



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[Lldb-commits] [lldb] [lldb][NFCI] Remove unneccessary allocation in ScriptInterpreterPythonImpl::GetSyntheticTypeName (PR #66724)

2023-09-19 Thread Alex Langford via lldb-commits

bulbazord wrote:

Fixed with `f1097e88d22511f3ec96386ca165b75bb75aaa7a`.

https://github.com/llvm/llvm-project/pull/66724
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[Lldb-commits] [lldb] 7265f79 - Fix a bug with cancelling "attach -w" after you have run a process previously (#65822)

2023-09-19 Thread via lldb-commits

Author: jimingham
Date: 2023-09-19T11:25:53-07:00
New Revision: 7265f792dc8e1157a3874aee5f8aed6d4d8236e7

URL: 
https://github.com/llvm/llvm-project/commit/7265f792dc8e1157a3874aee5f8aed6d4d8236e7
DIFF: 
https://github.com/llvm/llvm-project/commit/7265f792dc8e1157a3874aee5f8aed6d4d8236e7.diff

LOG: Fix a bug with cancelling "attach -w" after you have run a process 
previously (#65822)

The problem is that the when the "attach" command is initiated, the
ExecutionContext for the command has a process - it's the exited one
from the previour run. But the `attach wait` creates a new process for
the attach, and then errors out instead of interrupting when it finds
that its process and the one in the command's ExecutionContext don't
match.

This change checks that if we're returning a target from
GetExecutionContext, we fill the context with it's current process, not
some historical one.

Added: 


Modified: 
lldb/include/lldb/Interpreter/CommandInterpreter.h
lldb/source/Interpreter/CommandInterpreter.cpp
lldb/source/Target/Process.cpp
lldb/test/API/commands/process/attach/TestProcessAttach.py
lldb/test/API/commands/process/attach/main.cpp

Removed: 




diff  --git a/lldb/include/lldb/Interpreter/CommandInterpreter.h 
b/lldb/include/lldb/Interpreter/CommandInterpreter.h
index 747188a15312fa3..960a1c18f0130ab 100644
--- a/lldb/include/lldb/Interpreter/CommandInterpreter.h
+++ b/lldb/include/lldb/Interpreter/CommandInterpreter.h
@@ -447,7 +447,7 @@ class CommandInterpreter : public Broadcaster,
 
   Debugger &GetDebugger() { return m_debugger; }
 
-  ExecutionContext GetExecutionContext() const;
+  ExecutionContext GetExecutionContext();
 
   lldb::PlatformSP GetPlatform(bool prefer_target_platform);
 
@@ -661,7 +661,7 @@ class CommandInterpreter : public Broadcaster,
 
   void GetProcessOutput();
 
-  bool DidProcessStopAbnormally() const;
+  bool DidProcessStopAbnormally();
 
   void SetSynchronous(bool value);
 

diff  --git a/lldb/source/Interpreter/CommandInterpreter.cpp 
b/lldb/source/Interpreter/CommandInterpreter.cpp
index dcff53ff843f328..9f1f520abb198f0 100644
--- a/lldb/source/Interpreter/CommandInterpreter.cpp
+++ b/lldb/source/Interpreter/CommandInterpreter.cpp
@@ -2471,7 +2471,7 @@ PlatformSP CommandInterpreter::GetPlatform(bool 
prefer_target_platform) {
   return platform_sp;
 }
 
-bool CommandInterpreter::DidProcessStopAbnormally() const {
+bool CommandInterpreter::DidProcessStopAbnormally() {
   auto exe_ctx = GetExecutionContext();
   TargetSP target_sp = exe_ctx.GetTargetSP();
   if (!target_sp)
@@ -2976,10 +2976,22 @@ void 
CommandInterpreter::FindCommandsForApropos(llvm::StringRef search_word,
m_alias_dict);
 }
 
-ExecutionContext CommandInterpreter::GetExecutionContext() const {
-  return !m_overriden_exe_contexts.empty()
- ? m_overriden_exe_contexts.top()
- : m_debugger.GetSelectedExecutionContext();
+ExecutionContext CommandInterpreter::GetExecutionContext() {
+  ExecutionContext exe_ctx;
+  if (!m_overriden_exe_contexts.empty()) {
+// During the course of a command, the target may have replaced the 
process 
+// coming in with another.  I fix that here:
+exe_ctx = m_overriden_exe_contexts.top();
+// Don't use HasProcessScope, that returns false if there is a process but
+// it's no longer valid, which is one of the cases we want to catch here.
+if (exe_ctx.HasTargetScope() && exe_ctx.GetProcessPtr()) {
+  ProcessSP actual_proc_sp = exe_ctx.GetTargetSP()->GetProcessSP();
+  if (actual_proc_sp != exe_ctx.GetProcessSP())
+m_overriden_exe_contexts.top().SetContext(actual_proc_sp);
+}
+return m_overriden_exe_contexts.top();
+  }
+  return m_debugger.GetSelectedExecutionContext();
 }
 
 void CommandInterpreter::OverrideExecutionContext(
@@ -3172,12 +3184,17 @@ void 
CommandInterpreter::IOHandlerInputComplete(IOHandler &io_handler,
 }
 
 bool CommandInterpreter::IOHandlerInterrupt(IOHandler &io_handler) {
+  // InterruptCommand returns true if this is the first time
+  // we initiate an interrupt for this command.  So we give the
+  // command a chance to handle the interrupt on the first
+  // interrupt, but if that didn't do anything, a second
+  // interrupt will do more work to halt the process/interpreter.
+  if (InterruptCommand()) 
+return true;
+
   ExecutionContext exe_ctx(GetExecutionContext());
   Process *process = exe_ctx.GetProcessPtr();
 
-  if (InterruptCommand())
-return true;
-
   if (process) {
 StateType state = process->GetState();
 if (StateIsRunningState(state)) {

diff  --git a/lldb/source/Target/Process.cpp b/lldb/source/Target/Process.cpp
index f82ab05362fbee9..d30557312f7a8f9 100644
--- a/lldb/source/Target/Process.cpp
+++ b/lldb/source/Target/Process.cpp
@@ -3153,23 +3153,22 @@ Status Process::Halt(bool clear_thread_plans, bool 
use_run_lock) {
  

[Lldb-commits] [lldb] Fix a bug with cancelling "attach -w" after you have run a process previously (PR #65822)

2023-09-19 Thread via lldb-commits

https://github.com/jimingham closed 
https://github.com/llvm/llvm-project/pull/65822
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[Lldb-commits] [lldb] [Clang] Static member initializers are not immediate escalating context. (PR #66021)

2023-09-19 Thread via lldb-commits

https://github.com/cor3ntin updated 
https://github.com/llvm/llvm-project/pull/66021

>From a3390c4ac8bba43e73ea41f4af85b37df97b1098 Mon Sep 17 00:00:00 2001
From: Corentin Jabot 
Date: Mon, 11 Sep 2023 23:40:38 +0200
Subject: [PATCH 1/4] [Clang] Static member initializers are not immediate
 escalating context.

Per CWG2760, default members initializers should be consider
part the body of consstructors, which mean they are evaluated
in an immediate escalating context.

However, this does not apply to static members.

This patch produces some extraneous diagnostics, unfortunately
we do not have a good way to report an error back to the
initializer and this is a preexisting issue

Fixes #65985
---
 clang/docs/ReleaseNotes.rst   |  4 
 clang/lib/Parse/ParseDeclCXX.cpp  | 12 --
 .../SemaCXX/cxx2b-consteval-propagate.cpp | 23 +++
 3 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 3cdad2f7b9f0e5a..8c8ec0e11e3dd7d 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -281,6 +281,10 @@ Bug Fixes to C++ Support
   a non-template inner-class between the function and the class template.
   (`#65810 `_)
 
+- Fix a crash when calling a non-constant immediate function
+  in the initializer of a static data member.
+  (`#65985 _`).
+
 Bug Fixes to AST Handling
 ^
 - Fixed an import failure of recursive friend class template.
diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp
index 730b6e55246d6b7..b4a72d599da6655 100644
--- a/clang/lib/Parse/ParseDeclCXX.cpp
+++ b/clang/lib/Parse/ParseDeclCXX.cpp
@@ -3230,13 +3230,21 @@ ExprResult Parser::ParseCXXMemberInitializer(Decl *D, 
bool IsFunction,
   assert(Tok.isOneOf(tok::equal, tok::l_brace) &&
  "Data member initializer not starting with '=' or '{'");
 
+  bool IsFieldInitialization = isa_and_present(D);
+
   EnterExpressionEvaluationContext Context(
   Actions,
-  isa_and_present(D)
+  IsFieldInitialization
   ? Sema::ExpressionEvaluationContext::PotentiallyEvaluatedIfUsed
   : Sema::ExpressionEvaluationContext::PotentiallyEvaluated,
   D);
-  Actions.ExprEvalContexts.back().InImmediateEscalatingFunctionContext = true;
+
+  // CWG2760
+  // Default member initializers used to initialize a base or member subobject
+  // [...] are considered to be part of the function body
+  Actions.ExprEvalContexts.back().InImmediateEscalatingFunctionContext =
+  IsFieldInitialization;
+
   if (TryConsumeToken(tok::equal, EqualLoc)) {
 if (Tok.is(tok::kw_delete)) {
   // In principle, an initializer of '= delete p;' is legal, but it will
diff --git a/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp 
b/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
index c5eb7f139327505..f967ce6554d777c 100644
--- a/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
+++ b/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
@@ -330,3 +330,26 @@ struct S {
 S s(0); // expected-note {{in the default initializer of 'j'}}
 
 }
+
+namespace GH65985 {
+
+int consteval operator""_foo(unsigned long long V) {
+return 0;
+}
+int consteval operator""_bar(unsigned long long V); // expected-note 3{{here}}
+
+struct C {
+static const int a = 1_foo;
+static constexpr int b = 1_foo;
+static const int c = 1_bar; // expected-error {{call to consteval function 
'GH65985::operator""_bar' is not a constant expression}} \
+// expected-note {{undefined function 
'operator""_bar' cannot be used in a constant expression}} \
+// expected-error {{in-class initializer for 
static data member is not a constant expression}}
+
+// FIXME: remove duplicate diagnostics
+static constexpr int d = 1_bar; // expected-error {{call to consteval 
function 'GH65985::operator""_bar' is not a constant expression}} \
+// expected-note {{undefined function 
'operator""_bar' cannot be used in a constant expression}} \
+// expected-error {{constexpr variable 'd' 
must be initialized by a constant expression}}  \
+// expected-note {{undefined function 
'operator""_bar' cannot be used in a constant expression}}
+};
+
+}

>From 12e04c8bd51d1f4e0d77969642f115b554b3a589 Mon Sep 17 00:00:00 2001
From: Corentin Jabot 
Date: Wed, 13 Sep 2023 10:10:28 +0200
Subject: [PATCH 2/4] Add more tests

---
 clang/test/SemaCXX/cxx2a-consteval.cpp| 35 +++
 .../SemaCXX/cxx2b-consteval-propagate.cpp | 23 
 2 files changed, 35 insertions(+), 23 deletions(-)

diff --git a/clang/test/SemaCXX/cxx2a-consteval.cpp 
b/clang/test/SemaCXX/cxx2a-consteval.cpp
index d98ec8048c32466..82d3212ed815

[Lldb-commits] [lldb] [Clang] Static member initializers are not immediate escalating context. (PR #66021)

2023-09-19 Thread via lldb-commits

https://github.com/cor3ntin updated 
https://github.com/llvm/llvm-project/pull/66021

>From a3390c4ac8bba43e73ea41f4af85b37df97b1098 Mon Sep 17 00:00:00 2001
From: Corentin Jabot 
Date: Mon, 11 Sep 2023 23:40:38 +0200
Subject: [PATCH 1/5] [Clang] Static member initializers are not immediate
 escalating context.

Per CWG2760, default members initializers should be consider
part the body of consstructors, which mean they are evaluated
in an immediate escalating context.

However, this does not apply to static members.

This patch produces some extraneous diagnostics, unfortunately
we do not have a good way to report an error back to the
initializer and this is a preexisting issue

Fixes #65985
---
 clang/docs/ReleaseNotes.rst   |  4 
 clang/lib/Parse/ParseDeclCXX.cpp  | 12 --
 .../SemaCXX/cxx2b-consteval-propagate.cpp | 23 +++
 3 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 3cdad2f7b9f0e5a..8c8ec0e11e3dd7d 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -281,6 +281,10 @@ Bug Fixes to C++ Support
   a non-template inner-class between the function and the class template.
   (`#65810 `_)
 
+- Fix a crash when calling a non-constant immediate function
+  in the initializer of a static data member.
+  (`#65985 _`).
+
 Bug Fixes to AST Handling
 ^
 - Fixed an import failure of recursive friend class template.
diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp
index 730b6e55246d6b7..b4a72d599da6655 100644
--- a/clang/lib/Parse/ParseDeclCXX.cpp
+++ b/clang/lib/Parse/ParseDeclCXX.cpp
@@ -3230,13 +3230,21 @@ ExprResult Parser::ParseCXXMemberInitializer(Decl *D, 
bool IsFunction,
   assert(Tok.isOneOf(tok::equal, tok::l_brace) &&
  "Data member initializer not starting with '=' or '{'");
 
+  bool IsFieldInitialization = isa_and_present(D);
+
   EnterExpressionEvaluationContext Context(
   Actions,
-  isa_and_present(D)
+  IsFieldInitialization
   ? Sema::ExpressionEvaluationContext::PotentiallyEvaluatedIfUsed
   : Sema::ExpressionEvaluationContext::PotentiallyEvaluated,
   D);
-  Actions.ExprEvalContexts.back().InImmediateEscalatingFunctionContext = true;
+
+  // CWG2760
+  // Default member initializers used to initialize a base or member subobject
+  // [...] are considered to be part of the function body
+  Actions.ExprEvalContexts.back().InImmediateEscalatingFunctionContext =
+  IsFieldInitialization;
+
   if (TryConsumeToken(tok::equal, EqualLoc)) {
 if (Tok.is(tok::kw_delete)) {
   // In principle, an initializer of '= delete p;' is legal, but it will
diff --git a/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp 
b/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
index c5eb7f139327505..f967ce6554d777c 100644
--- a/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
+++ b/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
@@ -330,3 +330,26 @@ struct S {
 S s(0); // expected-note {{in the default initializer of 'j'}}
 
 }
+
+namespace GH65985 {
+
+int consteval operator""_foo(unsigned long long V) {
+return 0;
+}
+int consteval operator""_bar(unsigned long long V); // expected-note 3{{here}}
+
+struct C {
+static const int a = 1_foo;
+static constexpr int b = 1_foo;
+static const int c = 1_bar; // expected-error {{call to consteval function 
'GH65985::operator""_bar' is not a constant expression}} \
+// expected-note {{undefined function 
'operator""_bar' cannot be used in a constant expression}} \
+// expected-error {{in-class initializer for 
static data member is not a constant expression}}
+
+// FIXME: remove duplicate diagnostics
+static constexpr int d = 1_bar; // expected-error {{call to consteval 
function 'GH65985::operator""_bar' is not a constant expression}} \
+// expected-note {{undefined function 
'operator""_bar' cannot be used in a constant expression}} \
+// expected-error {{constexpr variable 'd' 
must be initialized by a constant expression}}  \
+// expected-note {{undefined function 
'operator""_bar' cannot be used in a constant expression}}
+};
+
+}

>From 12e04c8bd51d1f4e0d77969642f115b554b3a589 Mon Sep 17 00:00:00 2001
From: Corentin Jabot 
Date: Wed, 13 Sep 2023 10:10:28 +0200
Subject: [PATCH 2/5] Add more tests

---
 clang/test/SemaCXX/cxx2a-consteval.cpp| 35 +++
 .../SemaCXX/cxx2b-consteval-propagate.cpp | 23 
 2 files changed, 35 insertions(+), 23 deletions(-)

diff --git a/clang/test/SemaCXX/cxx2a-consteval.cpp 
b/clang/test/SemaCXX/cxx2a-consteval.cpp
index d98ec8048c32466..82d3212ed815

[Lldb-commits] [lldb] [lldb] Add interface to check if UserExpression::Parse() is cacheable (PR #66826)

2023-09-19 Thread Augusto Noronha via lldb-commits

https://github.com/augusto2112 created 
https://github.com/llvm/llvm-project/pull/66826

When setting conditional breakpoints, we currently assume that a call to 
UserExpression::Parse() can be cached and resued multiple times. This may not 
be true for every user expression. Add a new method so subclasses of 
UserExpression can customize if they are parseable or not.

>From 5593f33bea5ebf0362b69d4b4a70a65edd77ca9d Mon Sep 17 00:00:00 2001
From: Augusto Noronha 
Date: Tue, 19 Sep 2023 13:27:41 -0700
Subject: [PATCH] [lldb] Add interface to check if UserExpression::Parse() is
 cacheable

When setting conditional breakpoints, we currently assume that a call to
UserExpression::Parse() can be cached and resued multiple times. This
may not be true for every user expression. Add a new method so
subclasses of UserExpression can customize if they are parseable or not.
---
 lldb/include/lldb/Expression/UserExpression.h | 2 ++
 lldb/source/Breakpoint/BreakpointLocation.cpp | 1 +
 2 files changed, 3 insertions(+)

diff --git a/lldb/include/lldb/Expression/UserExpression.h 
b/lldb/include/lldb/Expression/UserExpression.h
index 2d62fa37a24c2c4..03aa5e87c4cd579 100644
--- a/lldb/include/lldb/Expression/UserExpression.h
+++ b/lldb/include/lldb/Expression/UserExpression.h
@@ -192,6 +192,8 @@ class UserExpression : public Expression {
   /// expression.  Text() should contain the definition of this function.
   const char *FunctionName() override { return "$__lldb_expr"; }
 
+  /// Returns whether the call to Parse on this user expression is cacheable.
+  virtual bool IsParseCacheable() { return true; }
   /// Return the language that should be used when parsing.  To use the
   /// default, return eLanguageTypeUnknown.
   lldb::LanguageType Language() const override { return m_language; }
diff --git a/lldb/source/Breakpoint/BreakpointLocation.cpp 
b/lldb/source/Breakpoint/BreakpointLocation.cpp
index 0fcefe5c63be749..2d2e00883f32ef7 100644
--- a/lldb/source/Breakpoint/BreakpointLocation.cpp
+++ b/lldb/source/Breakpoint/BreakpointLocation.cpp
@@ -250,6 +250,7 @@ bool BreakpointLocation::ConditionSaysStop(ExecutionContext 
&exe_ctx,
   DiagnosticManager diagnostics;
 
   if (condition_hash != m_condition_hash || !m_user_expression_sp ||
+  !m_user_expression_sp->IsParseCacheable() ||
   !m_user_expression_sp->MatchesContext(exe_ctx)) {
 LanguageType language = eLanguageTypeUnknown;
 // See if we can figure out the language from the frame, otherwise use the

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[Lldb-commits] [lldb] [Clang] Static member initializers are not immediate escalating context. (PR #66021)

2023-09-19 Thread via lldb-commits

https://github.com/cor3ntin closed 
https://github.com/llvm/llvm-project/pull/66021
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[Lldb-commits] [lldb] Fix a bug with cancelling "attach -w" after you have run a process previously (PR #65822)

2023-09-19 Thread Daniel Thornburgh via lldb-commits

mysterymath wrote:

It looks like this is breaking buildbots:
https://lab.llvm.org/buildbot/#/builders/68/builds/60267

The test can't find `main.cpp`, and it looks like the immediately preceding 
test issues an `os.chdir`. It has a hook to reset it, but maybe there's some 
problem with it? 

https://github.com/llvm/llvm-project/pull/65822
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[Lldb-commits] [lldb] [lldb-vscode] Show addresses next to dereferenced summaries when using enableAutoVariableSummaries (PR #66551)

2023-09-19 Thread Walter Erquinigo via lldb-commits

https://github.com/walter-erquinigo updated 
https://github.com/llvm/llvm-project/pull/66551

>From 4c9d8d3f5be34d5ffec502a8fa891b603549b2cc Mon Sep 17 00:00:00 2001
From: walter erquinigo 
Date: Fri, 15 Sep 2023 16:50:35 -0400
Subject: [PATCH] [lldb-vscode] Use auto summaries when variables have values

Auto summaries were only being used when non-pointer/reference variables didn't 
have values nor summaries. Greg pointed out that it should be better to simply 
use auto summaries when the variable doesn't have a summary of its own, 
regardless of other conditions.
This led to code simplification and correct visualization of auto summaries for 
pointer/reference types.
---
 .../evaluate/TestVSCode_evaluate.py   |  3 +-
 .../API/tools/lldb-vscode/evaluate/main.cpp   |  3 +-
 lldb/tools/lldb-vscode/JSONUtils.cpp  | 80 +++
 3 files changed, 31 insertions(+), 55 deletions(-)

diff --git a/lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py 
b/lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py
index 3cfe02ef6aa1576..d1b73e1a057e1da 100644
--- a/lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py
+++ b/lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py
@@ -63,8 +63,9 @@ def run_test_evaluate_expressions(
 "struct1", "{foo:15}" if enableAutoVariableSummaries else 
"my_struct @ 0x"
 )
 self.assertEvaluate(
-"struct2", "{foo:16}" if enableAutoVariableSummaries else "0x.*"
+"struct2", "0x.* {foo:16}" if enableAutoVariableSummaries else 
"0x.*"
 )
+self.assertEvaluate("struct3", "0x.*0")
 self.assertEvaluate("struct1.foo", "15")
 self.assertEvaluate("struct2->foo", "16")
 
diff --git a/lldb/test/API/tools/lldb-vscode/evaluate/main.cpp 
b/lldb/test/API/tools/lldb-vscode/evaluate/main.cpp
index 3a541b21b220828..f09d00e6444bb79 100644
--- a/lldb/test/API/tools/lldb-vscode/evaluate/main.cpp
+++ b/lldb/test/API/tools/lldb-vscode/evaluate/main.cpp
@@ -18,6 +18,7 @@ struct my_struct {
 int main(int argc, char const *argv[]) {
   my_struct struct1 = {15};
   my_struct *struct2 = new my_struct{16};
+  my_struct *struct3 = nullptr;
   int var1 = 20;
   int var2 = 21;
   int var3 = static_int; // breakpoint 1
@@ -43,6 +44,6 @@ int main(int argc, char const *argv[]) {
   my_bool_vec.push_back(true);
   my_bool_vec.push_back(false); // breakpoint 6
   my_bool_vec.push_back(true); // breakpoint 7
-  
+
   return 0;
 }
diff --git a/lldb/tools/lldb-vscode/JSONUtils.cpp 
b/lldb/tools/lldb-vscode/JSONUtils.cpp
index c6b422e4d7a02e6..6cf753170d8429f 100644
--- a/lldb/tools/lldb-vscode/JSONUtils.cpp
+++ b/lldb/tools/lldb-vscode/JSONUtils.cpp
@@ -136,14 +136,14 @@ std::vector GetStrings(const 
llvm::json::Object *obj,
 /// first children, so that the user can get a glimpse of its contents at a
 /// glance.
 static std::optional
-GetSyntheticSummaryForContainer(lldb::SBValue &v) {
+TryCreateAutoSummaryForContainer(lldb::SBValue &v) {
   // We gate this feature because it performs GetNumChildren(), which can
   // cause performance issues because LLDB needs to complete possibly huge
   // types.
   if (!g_vsc.enable_auto_variable_summaries)
 return std::nullopt;
 
-  if (v.TypeIsPointerType() || !v.MightHaveChildren())
+  if (!v.MightHaveChildren())
 return std::nullopt;
   /// As this operation can be potentially slow, we limit the total time spent
   /// fetching children to a few ms.
@@ -194,28 +194,18 @@ GetSyntheticSummaryForContainer(lldb::SBValue &v) {
   return summary;
 }
 
-/// Return whether we should dereference an SBValue in order to generate a more
-/// meaningful summary string.
-static bool ShouldBeDereferencedForSummary(lldb::SBValue &v) {
+/// Try to create a summary string for the given value that doesn't have a
+/// summary of its own.
+static std::optional TryCreateAutoSummary(lldb::SBValue value) {
   if (!g_vsc.enable_auto_variable_summaries)
-return false;
-
-  if (!v.GetType().IsPointerType() && !v.GetType().IsReferenceType())
-return false;
-
-  // If we are referencing a pointer, we don't dereference to avoid confusing
-  // the user with the addresses that could shown in the summary.
-  if (v.Dereference().GetType().IsPointerType())
-return false;
-
-  // If it's synthetic or a pointer to a basic type that provides a summary, we
-  // don't dereference.
-  if ((v.IsSynthetic() || v.GetType().GetPointeeType().GetBasicType() !=
-  lldb::eBasicTypeInvalid) &&
-  !llvm::StringRef(v.GetSummary()).empty()) {
-return false;
-  }
-  return true;
+return std::nullopt;
+
+  // We use the dereferenced value for generating the summary.
+  if (value.GetType().IsPointerType() || value.GetType().IsReferenceType())
+value = value.Dereference();
+
+  // We only support auto summaries for containers.
+  return TryCreateAutoSummaryForContainer(value);
 }
 
 void SetValueForKey(lldb::SBValue &v, llvm::jso

[Lldb-commits] [lldb] [lldb-vscode] Use auto summaries whenever variables don't have a summary (PR #66551)

2023-09-19 Thread Walter Erquinigo via lldb-commits

https://github.com/walter-erquinigo edited 
https://github.com/llvm/llvm-project/pull/66551
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[Lldb-commits] [lldb] [lldb-vscode] Use auto summaries whenever variables don't have a summary (PR #66551)

2023-09-19 Thread Walter Erquinigo via lldb-commits

https://github.com/walter-erquinigo edited 
https://github.com/llvm/llvm-project/pull/66551
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[Lldb-commits] [lldb] [lldb-vscode] Use auto summaries whenever variables don't have a summary (PR #66551)

2023-09-19 Thread Walter Erquinigo via lldb-commits

https://github.com/walter-erquinigo edited 
https://github.com/llvm/llvm-project/pull/66551
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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

2023-09-19 Thread Jason Molenda via Phabricator via lldb-commits
jasonmolenda added inline comments.



Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:135
+process_sp->SetCanInterpretFunctionCalls(true);
+process_sp->SetCanJIT(false);
+  }

These should not be set in the ABI, please remove these.  These are probably 
correct for the qemu environment you're testing against, but if we're connected 
to a remote stub that can allocate memory (_M packet), we can JIT code. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159101/new/

https://reviews.llvm.org/D159101

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[Lldb-commits] [lldb] 74338bf - A test was changing directory and then incorrectly restoring the directory

2023-09-19 Thread Jim Ingham via lldb-commits

Author: Jim Ingham
Date: 2023-09-19T16:46:08-07:00
New Revision: 74338bfe0cfec8b8db24af131cdeb664e346a1b5

URL: 
https://github.com/llvm/llvm-project/commit/74338bfe0cfec8b8db24af131cdeb664e346a1b5
DIFF: 
https://github.com/llvm/llvm-project/commit/74338bfe0cfec8b8db24af131cdeb664e346a1b5.diff

LOG: A test was changing directory and then incorrectly restoring the directory
to the "testdir" which is the build directory for that test, not the
original source directory.  That caused subsequent tests to fail.

Added: 


Modified: 
lldb/test/API/commands/process/attach/TestProcessAttach.py

Removed: 




diff  --git a/lldb/test/API/commands/process/attach/TestProcessAttach.py 
b/lldb/test/API/commands/process/attach/TestProcessAttach.py
index 67bb134ec0148a0..99ff3a4ec4db816 100644
--- a/lldb/test/API/commands/process/attach/TestProcessAttach.py
+++ b/lldb/test/API/commands/process/attach/TestProcessAttach.py
@@ -74,7 +74,8 @@ def test_attach_to_process_from_
diff erent_dir_by_id(self):
 popen = self.spawnSubprocess(exe)
 
 os.chdir(newdir)
-self.addTearDownHook(lambda: os.chdir(testdir))
+sourcedir = self.getSourceDir()
+self.addTearDownHook(lambda: os.chdir(sourcedir))
 self.runCmd("process attach -p " + str(popen.pid))
 
 target = self.dbg.GetSelectedTarget()



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[Lldb-commits] [lldb] Fix a bug with cancelling "attach -w" after you have run a process previously (PR #65822)

2023-09-19 Thread via lldb-commits

jimingham wrote:

Good eye!

The cleanup actually does run but it was told to reset the directory to the 
"testdir" which is:

build/lldb-test-build.noindex/commands/process/attach/TestProcessAttach.test_attach_to_process_from_different_dir_by_id

but the tests are supposed to start in the source directory.  I fixed that in:

74338bfe0cfec8b8db24af131cdeb664e346a1b5

teach me to just run the test I added!
 
Jim


> On Sep 19, 2023, at 3:05 PM, Daniel Thornburgh ***@***.***> wrote:
> 
> 
> It looks like this is breaking buildbots:
> https://lab.llvm.org/buildbot/#/builders/68/builds/60267
> 
> The test can't find main.cpp, and it looks like the immediately preceding 
> test issues an os.chdir. It has a hook to reset it, but maybe there's some 
> problem with it?
> 
> —
> Reply to this email directly, view it on GitHub 
> , or 
> unsubscribe 
> .
> You are receiving this because you modified the open/close state.
> 



https://github.com/llvm/llvm-project/pull/65822
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[Lldb-commits] [lldb] [lldb] Add interface to check if UserExpression::Parse() is cacheable (PR #66826)

2023-09-19 Thread via lldb-commits

https://github.com/jimingham approved this pull request.

Presumably this will do something for Swift expressions?  I don't think there's 
any reason that the expression for a location in C/C++/ObjC code would not be 
cacheable, so the fact that this is a no-op in all of llvm.org lldb is expected.

https://github.com/llvm/llvm-project/pull/66826
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[Lldb-commits] [lldb] b927490 - [lldb][NFCI] Remove unused struct ConstString::StringIsEqual

2023-09-19 Thread Alex Langford via lldb-commits

Author: Alex Langford
Date: 2023-09-19T17:39:22-07:00
New Revision: b927490d73eebe0a7e8071047d79a330145b0488

URL: 
https://github.com/llvm/llvm-project/commit/b927490d73eebe0a7e8071047d79a330145b0488
DIFF: 
https://github.com/llvm/llvm-project/commit/b927490d73eebe0a7e8071047d79a330145b0488.diff

LOG: [lldb][NFCI] Remove unused struct ConstString::StringIsEqual

This doesn't seem to be used at all, no need to keep it around.

Added: 


Modified: 
lldb/include/lldb/Utility/ConstString.h

Removed: 




diff  --git a/lldb/include/lldb/Utility/ConstString.h 
b/lldb/include/lldb/Utility/ConstString.h
index c23c6fd3546e55f..cbea4cbf916a430 100644
--- a/lldb/include/lldb/Utility/ConstString.h
+++ b/lldb/include/lldb/Utility/ConstString.h
@@ -78,22 +78,6 @@ class ConstString {
   /// from \a cstr.
   explicit ConstString(const char *cstr, size_t max_cstr_len);
 
-  /// C string equality binary predicate function object for ConstString
-  /// objects.
-  struct StringIsEqual {
-/// C equality test.
-///
-/// Two C strings are equal when they are contained in ConstString objects
-/// when their pointer values are equal to each other.
-///
-/// \return
-/// Returns \b true if the C string in \a lhs is equal to
-/// the C string value in \a rhs, \b false otherwise.
-bool operator()(const char *lhs, const char *rhs) const {
-  return lhs == rhs;
-}
-  };
-
   /// Convert to bool operator.
   ///
   /// This allows code to check a ConstString object to see if it contains a



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[Lldb-commits] [lldb] [lldb-vscode] Use auto summaries whenever variables don't have a summary (PR #66551)

2023-09-19 Thread Greg Clayton via lldb-commits

https://github.com/clayborg approved this pull request.

Much better solution that doesn't depend on having a pointer.

https://github.com/llvm/llvm-project/pull/66551
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