[PATCH 1/4] DW DMAC: rename is_private property as ordered by DT policy
Rename is_private to is-private as ordered by DT policy. The change leaves the support for the old format. Signed-off-by: Eugeniy Paltsev --- drivers/dma/dw/platform.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c index 5bda0eb..4103f1d 100644 --- a/drivers/dma/dw/platform.c +++ b/drivers/dma/dw/platform.c @@ -128,6 +128,8 @@ dw_dma_parse_dt(struct platform_device *pdev) if (of_property_read_bool(np, "is_private")) pdata->is_private = true; + else if (of_property_read_bool(np, "is-private")) + pdata->is_private = true; if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) pdata->chan_allocation_order = (unsigned char)tmp; -- 2.5.5 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 2/4] DW DMAC: add is-memcpu property to device tree
Memory-to-memory dma transfers were disabled by default if we used DT to cofigure DMAC. Add is-memcpu property, so it became possible to enable memory-to-memory transfers support via DT. Signed-off-by: Eugeniy Paltsev --- drivers/dma/dw/platform.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c index 4103f1d..daeceac 100644 --- a/drivers/dma/dw/platform.c +++ b/drivers/dma/dw/platform.c @@ -131,6 +131,9 @@ dw_dma_parse_dt(struct platform_device *pdev) else if (of_property_read_bool(np, "is-private")) pdata->is_private = true; + if (of_property_read_bool(np, "is-memcpu")) + pdata->is_memcpy = true; + if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) pdata->chan_allocation_order = (unsigned char)tmp; -- 2.5.5 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 3/4] DW DMAC: add hw-llp property to device tree
Several versions of DW DMAC have multi block transfers hardware
support. Hardware support of multi block transfers is disabled
by default if we use DT to configure DMAC and software emulation
of multi block transfers used instead.
Add hw-llp property, so it is possible to enable hardware
multi block transfers (if present) via DT.
Signed-off-by: Eugeniy Paltsev
---
drivers/dma/dw/core.c| 2 +-
drivers/dma/dw/platform.c| 5 +
include/linux/platform_data/dma-dw.h | 4 ++--
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index c2c0a61..e3ff4ea 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
} else {
dwc->block_size = pdata->block_size;
- dwc->nollp = pdata->is_nollp;
+ dwc->nollp = pdata->hw_llp[i];
}
}
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index daeceac..2722e60 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -151,6 +151,11 @@ dw_dma_parse_dt(struct platform_device *pdev)
pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
}
+ if (!of_property_read_u32_array(np, "hw-llp", arr, nr_masters)) {
+ for (tmp = 0; tmp < nr_masters; tmp++)
+ pdata->hw_llp[tmp] = arr[tmp];
+ }
+
return pdata;
}
#else
diff --git a/include/linux/platform_data/dma-dw.h
b/include/linux/platform_data/dma-dw.h
index 5f0e11e..5bc8124 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -40,19 +40,18 @@ struct dw_dma_slave {
* @is_private: The device channels should be marked as private and not for
* by the general purpose DMA channel allocator.
* @is_memcpy: The device channels do support memory-to-memory transfers.
- * @is_nollp: The device channels does not support multi block transfers.
* @chan_allocation_order: Allocate channels starting from 0 or 7
* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
* @block_size: Maximum block size supported by the controller
* @nr_masters: Number of AHB masters supported by the controller
* @data_width: Maximum data width supported by hardware per AHB master
* (in bytes, power of 2)
+ * @hw_llp: Multi block transfers supported by hardware per AHB master.
*/
struct dw_dma_platform_data {
unsigned intnr_channels;
boolis_private;
boolis_memcpy;
- boolis_nollp;
#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
unsigned char chan_allocation_order;
@@ -62,6 +61,7 @@ struct dw_dma_platform_data {
unsigned intblock_size;
unsigned char nr_masters;
unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
+ unsigned char hw_llp[DW_DMA_MAX_NR_MASTERS];
};
#endif /* _PLATFORM_DATA_DMA_DW_H */
--
2.5.5
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[PATCH 0/4] DW DMAC: update device tree
It wasn't possible to enable some features like memory-to-memory transfers or multi block transfers via DT. It is fixed by these patches. * Rename is_private to is-private as ordered by DT policy. (just for cleanup) The change leaves the support for the old format. * Add is-memcpu property, so it is possible to enable memory-to-memory transfers support via DT. * Add hw-llp property, so it is possible to enable hardware multi block transfers support via DT. * Update DW DMAC device tree documentation. Eugeniy Paltsev (4): DW DMAC: rename is_private property as ordered by DT policy DW DMAC: add is-memcpu property to device tree DW DMAC: add hw-llp property to device tree Update device tree Synopsys DW DMAC documentation Documentation/devicetree/bindings/dma/snps-dma.txt | 10 -- drivers/dma/dw/core.c | 2 +- drivers/dma/dw/platform.c | 10 ++ include/linux/platform_data/dma-dw.h | 4 ++-- 4 files changed, 21 insertions(+), 5 deletions(-) -- 2.5.5 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 4/4] Update device tree Synopsys DW DMAC documentation
* Rename is_private to is-private as ordered by DT policy.
The change leaves the support for the old format.
* Add is-memcpu property, so it is possible to
enable memory-to-memory transfers support via DT.
* Add hw-llp property, so it is possible to enable
hardware multi block transfers support via DT.
Fix white spaces.
Signed-off-by: Eugeniy Paltsev
---
Documentation/devicetree/bindings/dma/snps-dma.txt | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt
b/Documentation/devicetree/bindings/dma/snps-dma.txt
index 0f55832..d41d960 100644
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -20,13 +20,19 @@ Required properties:
Deprecated properties:
- data_width: Maximum data width supported by hardware per AHB master
(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
+- is_private: The device channels should be marked as private and not for by
the
+ general purpose DMA channel allocator. False if not passed.
Optional properties:
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
-- is_private: The device channels should be marked as private and not for by
the
+- is-private: The device channels should be marked as private and not for by
the
general purpose DMA channel allocator. False if not passed.
+- is-memcpu: The device channels do support memory-to-memory transfers. False
+ if not passed.
+- hw-llp: Multi block transfers supported by hardware per AHB master.
+ 0 (default): not supported, 1: supported.
Example:
@@ -56,7 +62,7 @@ The four cells in order are:
4. Peripheral master for transfers on allocated channel
Example:
-
+
serial@e000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xe000 0x1000>;
--
2.5.5
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Re: [PATCH 1/4] DW DMAC: rename is_private property as ordered by DT policy
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote: > Rename is_private to is-private as ordered by DT policy. > The change leaves the support for the old format. > > Signed-off-by: Eugeniy Paltsev > --- > drivers/dma/dw/platform.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c > index 5bda0eb..4103f1d 100644 > --- a/drivers/dma/dw/platform.c > +++ b/drivers/dma/dw/platform.c > @@ -128,6 +128,8 @@ dw_dma_parse_dt(struct platform_device *pdev) > > if (of_property_read_bool(np, "is_private")) > pdata->is_private = true; > + else if (of_property_read_bool(np, "is-private")) > + pdata->is_private = true; First, try new one, then fall back. > > if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) > pdata->chan_allocation_order = (unsigned char)tmp; -- Andy Shevchenko Intel Finland Oy ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 4/4] Update device tree Synopsys DW DMAC documentation
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote: > * Rename is_private to is-private as ordered by DT policy. > The change leaves the support for the old format. > > * Add is-memcpu property, so it is possible to > enable memory-to-memory transfers support via DT. > > * Add hw-llp property, so it is possible to enable > hardware multi block transfers support via DT. > > Fix white spaces. > > Signed-off-by: Eugeniy Paltsev > --- > Documentation/devicetree/bindings/dma/snps-dma.txt | 10 -- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt > b/Documentation/devicetree/bindings/dma/snps-dma.txt > index 0f55832..d41d960 100644 > --- a/Documentation/devicetree/bindings/dma/snps-dma.txt > +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt > @@ -20,13 +20,19 @@ Required properties: > Deprecated properties: > - data_width: Maximum data width supported by hardware per AHB master > (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) > +- is_private: The device channels should be marked as private and not > for by the > + general purpose DMA channel allocator. False if not passed. This... > > > Optional properties: > - interrupt-parent: Should be the phandle for the interrupt > controller > that services interrupts for this device > -- is_private: The device channels should be marked as private and not > for by the > +- is-private: The device channels should be marked as private and not > for by the > general purpose DMA channel allocator. False if not passed. ...and this is a part of patch 1. > +- is-memcpu: The device channels do support memory-to-memory memcpy > transfers. > False > + if not passed. > +- hw-llp: Multi block transfers supported by hardware per AHB master. > + 0 (default): not supported, 1: supported. Overall, since we are going to expose some properties to the Device Tree I would really think twice about naming. Better if we reuse something existing already. So, what I can see is dmacap,private dmacap,memcpy Here is a selling point as well, i.e. standardization. 'hw-llp' sounds too tricky, perhaps 'multi-block' is better and could be re-used. > > Example: > > @@ -56,7 +62,7 @@ The four cells in order are: > 4. Peripheral master for transfers on allocated channel > > Example: > - > + No, no need to touch this. -- Andy Shevchenko Intel Finland Oy ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 2/4] DW DMAC: add is-memcpu property to device tree
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote: > Memory-to-memory dma transfers were disabled by default if we > used DT to cofigure DMAC. > Add is-memcpu property, so it became possible to enable > memory-to-memory transfers support via DT. Fix "memcpu" to "memcpy" everywhere you use it. > > Signed-off-by: Eugeniy Paltsev > --- > drivers/dma/dw/platform.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c > index 4103f1d..daeceac 100644 > --- a/drivers/dma/dw/platform.c > +++ b/drivers/dma/dw/platform.c > @@ -131,6 +131,9 @@ dw_dma_parse_dt(struct platform_device *pdev) > else if (of_property_read_bool(np, "is-private")) > pdata->is_private = true; > > + if (of_property_read_bool(np, "is-memcpu")) > + pdata->is_memcpy = true; > + > if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) > pdata->chan_allocation_order = (unsigned char)tmp; > -- Andy Shevchenko Intel Finland Oy ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 3/4] DW DMAC: add hw-llp property to device tree
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote:
> Several versions of DW DMAC have multi block transfers hardware
> support. Hardware support of multi block transfers is disabled
> by default if we use DT to configure DMAC and software emulation
> of multi block transfers used instead.
> Add hw-llp property, so it is possible to enable hardware
> multi block transfers (if present) via DT.
You forgot to explain the conversion from per device value to per
channel one.
>
> Signed-off-by: Eugeniy Paltsev
> ---
> drivers/dma/dw/core.c| 2 +-
> drivers/dma/dw/platform.c| 5 +
> include/linux/platform_data/dma-dw.h | 4 ++--
> 3 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> index c2c0a61..e3ff4ea 100644
> --- a/drivers/dma/dw/core.c
> +++ b/drivers/dma/dw/core.c
> @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
> (dwc_params >> DWC_PARAMS_MBLK_EN &
> 0x1) == 0;
> } else {
> dwc->block_size = pdata->block_size;
> - dwc->nollp = pdata->is_nollp;
> + dwc->nollp = pdata->hw_llp[i];
> }
> }
>
> diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
> index daeceac..2722e60 100644
> --- a/drivers/dma/dw/platform.c
> +++ b/drivers/dma/dw/platform.c
> @@ -151,6 +151,11 @@ dw_dma_parse_dt(struct platform_device *pdev)
> pdata->data_width[tmp] = BIT(arr[tmp] &
> 0x07);
> }
>
> + if (!of_property_read_u32_array(np, "hw-llp", arr,
> nr_masters)) {
> + for (tmp = 0; tmp < nr_masters; tmp++)
> + pdata->hw_llp[tmp] = arr[tmp];
> + }
> +
> return pdata;
> }
> #else
> diff --git a/include/linux/platform_data/dma-dw.h
> b/include/linux/platform_data/dma-dw.h
> index 5f0e11e..5bc8124 100644
> --- a/include/linux/platform_data/dma-dw.h
> +++ b/include/linux/platform_data/dma-dw.h
> @@ -40,19 +40,18 @@ struct dw_dma_slave {
> * @is_private: The device channels should be marked as private and
> not for
> * by the general purpose DMA channel allocator.
> * @is_memcpy: The device channels do support memory-to-memory
> transfers.
> - * @is_nollp: The device channels does not support multi block
> transfers.
> * @chan_allocation_order: Allocate channels starting from 0 or 7
> * @chan_priority: Set channel priority increasing from 0 to 7 or 7
> to 0.
> * @block_size: Maximum block size supported by the controller
> * @nr_masters: Number of AHB masters supported by the controller
> * @data_width: Maximum data width supported by hardware per AHB
> master
> * (in bytes, power of 2)
> + * @hw_llp: Multi block transfers supported by hardware per AHB
> master.
> */
> struct dw_dma_platform_data {
> unsigned intnr_channels;
> boolis_private;
> boolis_memcpy;
> - boolis_nollp;
> #define CHAN_ALLOCATION_ASCENDING0 /* zero to seven */
> #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero
> */
> unsigned char chan_allocation_order;
> @@ -62,6 +61,7 @@ struct dw_dma_platform_data {
> unsigned intblock_size;
> unsigned char nr_masters;
> unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
> + unsigned char hw_llp[DW_DMA_MAX_NR_MASTERS];
> };
>
> #endif /* _PLATFORM_DATA_DMA_DW_H */
--
Andy Shevchenko
Intel Finland Oy
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Re: [PATCH 0/4] DW DMAC: update device tree
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote: > It wasn't possible to enable some features like > memory-to-memory transfers or multi block transfers via DT. > It is fixed by these patches. > > * Rename is_private to is-private as ordered by DT policy. > (just for cleanup) The change leaves the support for the > old format. > > * Add is-memcpu property, so it is possible to > enable memory-to-memory transfers support via DT. > > * Add hw-llp property, so it is possible to enable > hardware multi block transfers support via DT. > > * Update DW DMAC device tree documentation. I have few comments I posted. Besides that don't forget about current users of the DT properties you standardized (by naming). Better you convert them at the same time. Older DT (blobs) are being still supported. Otherwise looks okay after you address all my comments and maybe others will do some. The DT people ACK is a must before this goes somewhere. Also, please keep Cc list as small as possible. For example I'm not sure Viresh has time to look at them, but he might keep an eye on the dmaengine mailing list. Same about Dan. > > Eugeniy Paltsev (4): > DW DMAC: rename is_private property as ordered by DT policy > DW DMAC: add is-memcpu property to device tree > DW DMAC: add hw-llp property to device tree > Update device tree Synopsys DW DMAC documentation > > Documentation/devicetree/bindings/dma/snps-dma.txt | 10 -- > drivers/dma/dw/core.c | 2 +- > drivers/dma/dw/platform.c | 10 ++ > include/linux/platform_data/dma-dw.h | 4 ++-- > 4 files changed, 21 insertions(+), 5 deletions(-) > -- Andy Shevchenko Intel Finland Oy ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 4/4] Update device tree Synopsys DW DMAC documentation
Hi Andy, On Wed, 2016-11-16 at 17:10 +0200, Andy Shevchenko wrote: > Overall, since we are going to expose some properties to the Device > Tree > I would really think twice about naming. Better if we reuse something > existing already. > > So, what I can see is > > dmacap,private > dmacap,memcpy > > Here is a selling point as well, i.e. standardization. > As I can see these property name used only in "mv_xor" driver. And they are marked as deprecated. So, I'm not sure if I should used these names. I agree with other comments. -- Paltsev Eugeniy ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 4/4] Update device tree Synopsys DW DMAC documentation
On Wed, 2016-11-16 at 17:01 +, Eugeniy Paltsev wrote: > On Wed, 2016-11-16 at 17:10 +0200, Andy Shevchenko wrote: > > Overall, since we are going to expose some properties to the Device > > Tree > > I would really think twice about naming. Better if we reuse > > something > > existing already. > > > > So, what I can see is > > > > dmacap,private > > dmacap,memcpy > > > > Here is a selling point as well, i.e. standardization. > > > > As I can see these property name used only in "mv_xor" driver. And > they are marked as deprecated. > So, I'm not sure if I should used these names. Oh, good catch! So, then I leave this to DT experienced guys to decide. Rob? -- Andy Shevchenko Intel Finland Oy ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 4/4] Update device tree Synopsys DW DMAC documentation
On Wed, Nov 16, 2016 at 12:08 PM, Andy Shevchenko wrote: > On Wed, 2016-11-16 at 17:01 +, Eugeniy Paltsev wrote: >> On Wed, 2016-11-16 at 17:10 +0200, Andy Shevchenko wrote: >> > Overall, since we are going to expose some properties to the Device >> > Tree >> > I would really think twice about naming. Better if we reuse >> > something >> > existing already. >> > >> > So, what I can see is >> > >> > dmacap,private >> > dmacap,memcpy >> > >> > Here is a selling point as well, i.e. standardization. >> > >> >> As I can see these property name used only in "mv_xor" driver. And >> they are marked as deprecated. >> So, I'm not sure if I should used these names. > > Oh, good catch! So, then I leave this to DT experienced guys to decide. > Rob? Well, maybe they were deprecated for a reason? This all seems like user configuration to me. So either they don't belong in DT or should be common if they do. Rob ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [uclibc-ng-devel] [PATCH] ARC: string: handle gcc 6.x macro changes
Hi Vineet, Vineet Gupta wrote, > In gcc 6.x cleanup, the macros got renamed. > (Need to support the old toggle for some more time) Applied and pushed, thx Waldemar ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v8 3/3] clocksource: Add clockevent support to NPS400 driver
From: Noam Camus
Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to control clock events per HW thread.
The design idea is that for each core there is dedicated register
(TSI) serving all 16 HW threads.
The register is a bitmask with one bit for each HW thread.
When HW thread wants that next expiration of timer interrupt will
hit it then the proper bit should be set in this dedicated register.
When timer expires all HW threads within this core which their bit
is set at the TSI register will be interrupted.
Driver can be used from device tree by:
compatible = "ezchip,nps400-timer0" <-- for clocksource
compatible = "ezchip,nps400-timer1" <-- for clockevent
Note that name convention for timer0/timer1 was taken from legacy
ARC design. This design is our base before adding HW threads.
For backward compatibility we keep "ezchip,nps400-timer" for clocksource
Signed-off-by: Noam Camus
Acked-by: Daniel Lezcano
Acked-by: Rob Herring
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 --
.../bindings/timer/ezchip,nps400-timer0.txt| 17 ++
.../bindings/timer/ezchip,nps400-timer1.txt| 15 ++
drivers/clocksource/timer-nps.c| 170
4 files changed, 202 insertions(+), 15 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644
Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
create mode 100644
Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
deleted file mode 100644
index c8c03d7..000
--- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-NPS Network Processor
-
-Required properties:
-
-- compatible : should be "ezchip,nps400-timer"
-
-Clocks required for compatible = "ezchip,nps400-timer":
-- clocks : Must contain a single entry describing the clock input
-
-Example:
-
-timer {
- compatible = "ezchip,nps400-timer";
- clocks = <&sysclk>;
-};
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
new file mode 100644
index 000..e3cfce8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
@@ -0,0 +1,17 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer0"
+
+Clocks required for compatible = "ezchip,nps400-timer0":
+- interrupts : The interrupt of the first timer
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer0";
+ interrupts = <3>;
+ clocks = <&sysclk>;
+};
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
new file mode 100644
index 000..c0ab419
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer1"
+
+Clocks required for compatible = "ezchip,nps400-timer1":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer1";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
index 0c8e21f..b4c8a02 100644
--- a/drivers/clocksource/timer-nps.c
+++ b/drivers/clocksource/timer-nps.c
@@ -111,3 +111,173 @@ static int __init nps_setup_clocksource(struct
device_node *node)
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
nps_setup_clocksource);
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
+ nps_setup_clocksource);
+
+#ifdef CONFIG_EZNPS_MTM_EXT
+#include
+
+/* Timer related Aux registers */
+#define NPS_REG_TIMER0_TSI 0xF850
+#define NPS_REG_TIMER0_LIMIT 0x23
+#define NPS_REG_TIMER0_CTRL0x22
+#define NPS_REG_TIMER0_CNT 0x21
+
+/*
+ * Interrupt Enabled (IE) - re-arm the timer
+ * Not Halted (NH) - is cleared when working with JTAG (for debug)
+ */
+#define TIMER0_CTRL_IE BIT(0)
+#define TIMER0_CTRL_NH BIT(1)
+
+static unsigned long nps_timer0_freq;
+static unsigned long nps_timer0_irq;
+
+static void nps_clkevent_rm_thread(void)
+{
+ int thread;
+ unsigned int cflags, enabled_threads;
+
+ hw_schd_save(&cflags);
+
+ enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
+
+ /* remove thread from TSI1 */
+ thread = read_aux_reg(CTOP_AUX_THREAD_ID)
