Re: [PATCH v4] MIPS: add speculation_barrier support

[YunQiang Su]

YunQiang Su  于2023年5月12日周五 18:30写道：
>
> speculation_barrier for MIPS needs sync+jr.hb (r2+),
> so we implement __speculation_barrier in libgcc, like arm32 does.
>
> gcc/ChangeLog:
> * config/mips/mips-protos.h (mips_emit_speculation_barrier): New
> prototype.
> * config/mips/mips.cc (speculation_barrier_libfunc): New static
> variable.
> (mips_init_libfuncs): Initialize it.
> (mips_emit_speculation_barrier): New function.
> * config/mips/mips.md (speculation_barrier): Call
> mips_emit_speculation_barrier.
> * configure.ac: error if gas doesn't accept ssnop for mips1.
> * configure: regenerated.
> * doc/install.texi: documents mips requires binutils 2.21+.
>
> libgcc/ChangeLog:
> * config/mips/lib1funcs.S: New file.
> define __speculation_barrier and include mips16.S.
> * config/mips/t-mips: define LIB1ASMSRC as mips/lib1funcs.S.
> define LIB1ASMFUNCS as _speculation_barrier.
> set version info for __speculation_barrier.
> * config/mips/libgcc-mips.ver: New file.
> * config/mips/t-mips16: don't define LIB1ASMSRC as mips16.S is
> included in lib1funcs.S now.

If no objection, I will commit this V4 patch.

> ---
>  gcc/config/mips/mips-protos.h  |  2 +
>  gcc/config/mips/mips.cc| 13 +++
>  gcc/config/mips/mips.md| 12 ++
>  gcc/configure  | 32 +++
>  gcc/configure.ac   |  7 
>  gcc/doc/install.texi   |  2 +
>  libgcc/config/mips/lib1funcs.S | 62 ++
>  libgcc/config/mips/libgcc-mips.ver | 21 ++
>  libgcc/config/mips/t-mips  |  7 
>  libgcc/config/mips/t-mips16|  3 +-
>  10 files changed, 159 insertions(+), 2 deletions(-)
>  create mode 100644 libgcc/config/mips/lib1funcs.S
>  create mode 100644 libgcc/config/mips/libgcc-mips.ver
>
> diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
> index 20483469105..da7902c235b 100644
> --- a/gcc/config/mips/mips-protos.h
> +++ b/gcc/config/mips/mips-protos.h
> @@ -388,4 +388,6 @@ extern void mips_register_frame_header_opt (void);
>  extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
>  extern void mips_expand_vec_cmp_expr (rtx *);
>
> +extern void mips_emit_speculation_barrier_function (void);
> +
>  #endif /* ! GCC_MIPS_PROTOS_H */
> diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
> index ca822758b41..139707fda34 100644
> --- a/gcc/config/mips/mips.cc
> +++ b/gcc/config/mips/mips.cc
> @@ -13611,6 +13611,9 @@ mips_autovectorize_vector_modes (vector_modes *modes, 
> bool)
>return 0;
>  }
>
> +
> +static GTY(()) rtx speculation_barrier_libfunc;
> +
>  /* Implement TARGET_INIT_LIBFUNCS.  */
>
>  static void
> @@ -13680,6 +13683,7 @@ mips_init_libfuncs (void)
>synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
>init_sync_libfuncs (UNITS_PER_WORD);
>  }
> +  speculation_barrier_libfunc = init_one_libfunc ("__speculation_barrier");
>  }
>
>  /* Build up a multi-insn sequence that loads label TARGET into $AT.  */
> @@ -19092,6 +19096,15 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, 
> int *hilo_delay,
>}
>  }
>
> +/* Emit a speculation barrier.
> +   JR.HB is needed, so we need to put
> +   speculation_barrier_libfunc in libgcc */
> +void
> +mips_emit_speculation_barrier_function ()
> +{
> +  emit_library_call (speculation_barrier_libfunc, LCT_NORMAL, VOIDmode);
> +}
> +
>  /* A SEQUENCE is breakable iff the branch inside it has a compact form
> and the target has compact branches.  */
>
> diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
> index ac1d77afc7d..5d04ac566dd 100644
> --- a/gcc/config/mips/mips.md
> +++ b/gcc/config/mips/mips.md
> @@ -160,6 +160,8 @@
>;; The `.insn' pseudo-op.
>UNSPEC_INSN_PSEUDO
>UNSPEC_JRHB
> +
> +  VUNSPEC_SPECULATION_BARRIER
>  ])
>
>  (define_constants
> @@ -7455,6 +7457,16 @@
>mips_expand_conditional_move (operands);
>DONE;
>  })
> +
> +(define_expand "speculation_barrier"
> +  [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
> +  ""
> +  "
> +  mips_emit_speculation_barrier_function ();
> +  DONE;
> +  "
> +)
> +
>
>  ;;
>  ;;  
> diff --git a/gcc/configure b/gcc/configure
> index 191f68581b3..e55b40d7f4c 100755
> --- a/gcc/configure
> +++ b/gcc/configure
> @@ -28699,6 +28699,38 @@ $as_echo "#define HAVE_L

[PATCH v2 2/2] MIPS: Don't expand large unaligned block move

[YunQiang Su]

For large unaligned block move, lib call may have better performance
than expanding.

Let's just return, if length is
larger than 64 on O32
larger than 128 on N32/N64.

Here are some test results:

CPU Aligned O32 N32 N64
Cavium 7130 1   72  192 192
Cavium 7130 2   96  192 192
Cavium 7130 4   +inf192 192
Cavium 7130 8   +inf+inf+inf
LS3A 2000   1   32  32  64
LS3A 2000   2   32  64  64
LS3A 2000   4   +inf32  48
LS3A 2000   8   +inf+inf+inf
LS3A 4000   1   32  64  128
LS3A 4000   2   64  64  128
LS3A 4000   4   192 128 192
LS3A 4000   8   192 +inf+inf
Ingenic X2000   1   96  -   -
Ingenic X2000   2   96  -   -
Ingenic X2000   4   +inf-   -
interAptiv  1   64  -   -
interAptiv  2   64  -   -
interAptiv  4   +inf-   -
P6600   1   64  128 128
P6600   2   64  128 128
P6600   4   256 192 128
P6600   8   +inf+inf+inf
P6600   1U  48  48  48  -mno-unaligned-access
P6600   2U  128 96  96  -mno-unaligned-access
P6600   4U  384 768 768 -mno-unaligned-access
P6600   8U  1024+inf+inf-mno-unaligned-access
I6500   1   384 896 640
I6500   2   256 768 512
I6500   4   384 704 512
I6500   8   512 10241024
I6500   1U  32  32  32  -mno-unaligned-access
I6500   2U  96  64  64  -mno-unaligned-access
I6500   4U  384 640 768 -mno-unaligned-access
I6500   8U  256 +inf+inf-mno-unaligned-access

When the length of block move is larger than this value,
(g)libc call has better performance.

gcc/
* config/mips/mips.cc (mips_expand_block_move): don't expand
large unaligned block move.

gcc/testsuite/
* gcc.target/mips/expand-block-move-large.c: new test.
---
 gcc/config/mips/mips.cc   |  6 +
 .../gcc.target/mips/expand-block-move-large.c | 22 +++
 2 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/expand-block-move-large.c

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ca297e3c1e5..7a7f4be627f 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -8308,6 +8308,12 @@ mips_expand_block_move (rtx dest, rtx src, rtx length)
  || MEM_ALIGN (dest) < MIPS_MIN_MOVE_MEM_ALIGN))
 return false;
 
+  if ((ISA_HAS_LWL_LWR || ISA_HAS_UNALIGNED_ACCESS)
+  && INTVAL (length) > MIPS_MAX_MOVE_BYTES_STRAIGHT * 2
+  && MEM_ALIGN (src) < BITS_PER_WORD
+  && MEM_ALIGN (dest) < BITS_PER_WORD)
+return false;
+
   if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER)
 {
   mips_block_move_straight (dest, src, INTVAL (length));
diff --git a/gcc/testsuite/gcc.target/mips/expand-block-move-large.c 
b/gcc/testsuite/gcc.target/mips/expand-block-move-large.c
new file mode 100644
index 000..98705f6c560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/expand-block-move-large.c
@@ -0,0 +1,22 @@
+/* { dg-final { scan-assembler "memcpy" } } */
+/* { dg-final { scan-assembler-not "lwl" } } */
+/* { dg-final { scan-assembler-not "swl" } } */
+/* { dg-final { scan-assembler-not "lwr" } } */
+/* { dg-final { scan-assembler-not "swr" } } */
+/* { dg-final { scan-assembler-not "ldl" } } */
+/* { dg-final { scan-assembler-not "sdl" } } */
+/* { dg-final { scan-assembler-not "ldr" } } */
+/* { dg-final { scan-assembler-not "sdr" } } */
+
+char a[4097], b[4097];
+#ifdef __mips64
+#define MAX_SIZE 128
+#else
+#define MAX_SIZE 64
+#endif
+
+NOCOMPRESSION void
+foo ()
+{
+  __builtin_memcpy(&a[1], &b[1], MAX_SIZE + 16);
+}
-- 
2.30.2

[PATCH v2 1/2] MIPS: Use unaligned access to expand block_move on r6

[YunQiang Su]

MIPSr6 support unaligned memory access with normal lh/sh/lw/sw/ld/sd
instructions, and thus lwl/lwr/ldl/ldr and swl/swr/sdl/sdr is removed.

For microarchitecture, these memory access instructions issue 2
operation if the address is not aligned, which is like what lwl family
do.

For some situation (such as accessing boundary of pages) on some
microarchitectures, the unaligned access may not be good enough,
then the kernel should trap&emu it: the kernel may need
-mno-unalgined-access option.

gcc/
* config/mips/mips.cc (mips_expand_block_move): don't expand for
r6 with -mno-unaligned-access option if one or both of src and
dest are unaligned. restruct: return directly if length is not const.
(mips_block_move_straight): emit_move if ISA_HAS_UNALIGNED_ACCESS.

gcc/testsuite/
* gcc.target/mips/expand-block-move-r6-no-unaligned.c: new test.
* gcc.target/mips/expand-block-move-r6.c: new test.
---
 gcc/config/mips/mips.cc   | 36 ++-
 .../mips/expand-block-move-r6-no-unaligned.c  | 15 
 .../gcc.target/mips/expand-block-move-r6.c| 20 +++
 3 files changed, 54 insertions(+), 17 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/mips/expand-block-move-r6-no-unaligned.c
 create mode 100644 gcc/testsuite/gcc.target/mips/expand-block-move-r6.c

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ca491b981a3..ca297e3c1e5 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -8167,8 +8167,9 @@ mips_block_move_straight (rtx dest, rtx src, 
HOST_WIDE_INT length)
  For ISA_HAS_LWL_LWR we rely on the lwl/lwr & swl/swr load. Otherwise
  picking the minimum of alignment or BITS_PER_WORD gets us the
  desired size for bits.  */
-
-  if (!ISA_HAS_LWL_LWR)
+  if (ISA_HAS_UNALIGNED_ACCESS)
+bits = BITS_PER_WORD;
+  else if (!ISA_HAS_LWL_LWR)
 bits = MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest)));
   else
 {
@@ -8190,7 +8191,7 @@ mips_block_move_straight (rtx dest, rtx src, 
HOST_WIDE_INT length)
   for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
 {
   regs[i] = gen_reg_rtx (mode);
-  if (MEM_ALIGN (src) >= bits)
+  if (ISA_HAS_UNALIGNED_ACCESS || MEM_ALIGN (src) >= bits)
mips_emit_move (regs[i], adjust_address (src, mode, offset));
   else
{
@@ -8203,7 +8204,7 @@ mips_block_move_straight (rtx dest, rtx src, 
HOST_WIDE_INT length)
 
   /* Copy the chunks to the destination.  */
   for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
-if (MEM_ALIGN (dest) >= bits)
+if (ISA_HAS_UNALIGNED_ACCESS || MEM_ALIGN (dest) >= bits)
   mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
 else
   {
@@ -8299,25 +8300,26 @@ mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT 
length,
 bool
 mips_expand_block_move (rtx dest, rtx src, rtx length)
 {
-  if (!ISA_HAS_LWL_LWR
+  if (!CONST_INT_P (length))
+return false;
+
+  if (mips_isa_rev >= 6 && !ISA_HAS_UNALIGNED_ACCESS
   && (MEM_ALIGN (src) < MIPS_MIN_MOVE_MEM_ALIGN
  || MEM_ALIGN (dest) < MIPS_MIN_MOVE_MEM_ALIGN))
 return false;
 
-  if (CONST_INT_P (length))
+  if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER)
 {
-  if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
-   {
- mips_block_move_straight (dest, src, INTVAL (length));
- return true;
-   }
-  else if (optimize)
-   {
- mips_block_move_loop (dest, src, INTVAL (length),
-   MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
- return true;
-   }
+  mips_block_move_straight (dest, src, INTVAL (length));
+  return true;
 }
+  else if (optimize)
+{
+  mips_block_move_loop (dest, src, INTVAL (length),
+   MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
+  return true;
+}
+
   return false;
 }
 
diff --git a/gcc/testsuite/gcc.target/mips/expand-block-move-r6-no-unaligned.c 
b/gcc/testsuite/gcc.target/mips/expand-block-move-r6-no-unaligned.c
new file mode 100644
index 000..0fdcac2d30b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/expand-block-move-r6-no-unaligned.c
@@ -0,0 +1,15 @@
+/* { dg-options "isa_rev>=6 -mno-unaligned-access" } */
+/* { dg-final { scan-assembler "memcpy" } } */
+
+char a[4097], b[4097];
+#ifdef __mips64
+#define MAX_SIZE 128
+#else
+#define MAX_SIZE 64
+#endif
+
+NOCOMPRESSION void
+foo ()
+{
+  __builtin_memcpy(&a[1], &b[1], MAX_SIZE-16);
+}
diff --git a/gcc/testsuite/gcc.target/mips/expand-block-move-r6.c 
b/gcc/testsuite/gcc.target/mips/expand-block-move-r6.c
new file mode 100644
index 000..9e247b15d06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/expand-block-move-r6.c
@@ -0,0 +1,20 @@
+/* { dg-options "isa_rev>=6" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" } { "" } } */
+/* { dg-final { scan-assembler-not "memcpy" } } */
+/* { dg-final { scan-assembler-n

[PATCH v5] MIPS: Add speculation_barrier support

[YunQiang Su]

speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.

gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
variable.
(mips_init_libfuncs): Initialize it.
(mips_emit_speculation_barrier): New function.
* config/mips/mips.md (speculation_barrier): Call
mips_emit_speculation_barrier.

libgcc/ChangeLog:
* config/mips/lib1funcs.S: New file.
define __speculation_barrier and include mips16.S.
* config/mips/t-mips: define LIB1ASMSRC as mips/lib1funcs.S.
define LIB1ASMFUNCS as _speculation_barrier.
set version info for __speculation_barrier.
* config/mips/libgcc-mips.ver: New file.
* config/mips/t-mips16: don't define LIB1ASMSRC as mips16.S
included in lib1funcs.S now.
---
 gcc/config/mips/mips-protos.h  |  2 +
 gcc/config/mips/mips.cc| 12 ++
 gcc/config/mips/mips.md| 12 ++
 libgcc/config/mips/lib1funcs.S | 65 ++
 libgcc/config/mips/libgcc-mips.ver | 21 ++
 libgcc/config/mips/t-mips  |  7 
 libgcc/config/mips/t-mips16|  3 +-
 7 files changed, 120 insertions(+), 2 deletions(-)
 create mode 100644 libgcc/config/mips/lib1funcs.S
 create mode 100644 libgcc/config/mips/libgcc-mips.ver

diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 20483469105..da7902c235b 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -388,4 +388,6 @@ extern void mips_register_frame_header_opt (void);
 extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
 extern void mips_expand_vec_cmp_expr (rtx *);
 
+extern void mips_emit_speculation_barrier_function (void);
+
 #endif /* ! GCC_MIPS_PROTOS_H */
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ca491b981a3..c1d1691306e 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -13611,6 +13611,9 @@ mips_autovectorize_vector_modes (vector_modes *modes, 
bool)
   return 0;
 }
 
+
+static GTY (()) rtx speculation_barrier_libfunc;
+
 /* Implement TARGET_INIT_LIBFUNCS.  */
 
 static void
@@ -13680,6 +13683,7 @@ mips_init_libfuncs (void)
   synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
   init_sync_libfuncs (UNITS_PER_WORD);
 }
+  speculation_barrier_libfunc = init_one_libfunc ("__speculation_barrier");
 }
 
 /* Build up a multi-insn sequence that loads label TARGET into $AT.  */
@@ -19092,6 +19096,14 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, 
int *hilo_delay,
   }
 }
 
+/* Emit a speculation barrier.
+   JR.HB is needed, so we put speculation_barrier_libfunc in libgcc.  */
+void
+mips_emit_speculation_barrier_function ()
+{
+  emit_library_call (speculation_barrier_libfunc, LCT_NORMAL, VOIDmode);
+}
+
 /* A SEQUENCE is breakable iff the branch inside it has a compact form
and the target has compact branches.  */
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index ac1d77afc7d..5d04ac566dd 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -160,6 +160,8 @@
   ;; The `.insn' pseudo-op.
   UNSPEC_INSN_PSEUDO
   UNSPEC_JRHB
+
+  VUNSPEC_SPECULATION_BARRIER
 ])
 
 (define_constants
@@ -7455,6 +7457,16 @@
   mips_expand_conditional_move (operands);
   DONE;
 })
+
+(define_expand "speculation_barrier"
+  [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
+  ""
+  "
+  mips_emit_speculation_barrier_function ();
+  DONE;
+  "
+)
+
 
 ;;
 ;;  
diff --git a/libgcc/config/mips/lib1funcs.S b/libgcc/config/mips/lib1funcs.S
new file mode 100644
index 000..97a3655e8ab
--- /dev/null
+++ b/libgcc/config/mips/lib1funcs.S
@@ -0,0 +1,65 @@
+/* Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 3, or (at your option) any
+later version.
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+.  */
+
+//#include "mips16.S"
+
+#ifdef L_speculation_barrier
+
+/* MIPS16e1 has no sync/jr.hb instructions, and MIPS16e2 lacks o

[COMMITTED] MAINTAINERS: Add myself as MIPS port maintainer

[YunQiang Su]

ChangeLog:

* MAINTAINERS (CPU Port Maintainers): Add myself as MIPS
port maintainer.
(Write After Approval): Remove myself.
---
 MAINTAINERS | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4a7c963914b..c8b787b6e1e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -91,7 +91,7 @@ m68k port Andreas Schwab  

 m68k-motorola-sysv portPhilippe De Muyter  
 mcore port Nick Clifton
 microblaze Michael Eager   
-mips port  Matthew Fortune 
+mips port  YunQiang Su 
 mmix port  Hans-Peter Nilsson  
 mn10300 port   Jeff Law
 mn10300 port   Alexandre Oliva 
@@ -652,7 +652,6 @@ Basile Starynkevitch

 Jakub Staszak  
 Graham Stott   
 Jeff Sturm 
-YunQiang Su
 Robert Suchanek
 Andrew Sutton  
 Gabriele Svelto
-- 
2.30.2

[PATCH] MAINTAINERS: move Matthew Fortune to Write After Approval

[YunQiang Su]

In 4fe6e12204535545edf7f035d4dc79c1404058cf, I should have added
Matthew Fortune to the Write After Approval section, while replacing
the MIPS Maintainer position.

ChangeLog:

* MAINTAINERS (Write After Approval): move Matthew Fortune
to Write After Approval.
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index c8b787b6e1e..89b9289830f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -412,6 +412,7 @@ Li Feng 

 Thomas Fitzsimmons 
 Alexander Fomin

 Brian Ford 
+Matthew Fortune
 John Freeman   
 Nathan Froyd   
 Chao-ying Fu   
-- 
2.30.2

[RFC] Store_bit_field_1: Use mode of SUBREG instead of REG

[YunQiang Su]

PR #104914

When work with
  int val;
  ((unsigned char*)&val)[0] = *buf;
The RTX mode is obtained from REG instead of SUBREG,
which make D is used instead of .
Thus something wrong happens on sign-extend default architectures,
like MIPS64.

gcc/ChangeLog:
PR: 104914.
* expmed.cc(store_bit_field_1): Get mode from original
str_rtx instead of op0.
---
 gcc/expmed.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/expmed.cc b/gcc/expmed.cc
index fbd4ce2d42f..37f90912122 100644
--- a/gcc/expmed.cc
+++ b/gcc/expmed.cc
@@ -849,7 +849,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
poly_uint64 bitnum,
  if we aren't.  This must come after the entire register case above,
  since that case is valid for any mode.  The following cases are only
  valid for integral modes.  */
-  opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (op0));
+  opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (str_rtx));
   scalar_int_mode imode;
   if (!op0_mode.exists (&imode) || imode != GET_MODE (op0))
 {
-- 
2.30.2

Re: [RFC] Store_bit_field_1: Use mode of SUBREG instead of REG

[YunQiang Su]

> 2023年7月12日 15:44，Richard Biener  写道：
> 
> On Wed, Jul 12, 2023 at 5:20 AM YunQiang Su  wrote:
>> 
>> PR #104914
>> 
>> When work with
>>  int val;
>>  ((unsigned char*)&val)[0] = *buf;
>> The RTX mode is obtained from REG instead of SUBREG,
>> which make D is used instead of .
>> Thus something wrong happens on sign-extend default architectures,
>> like MIPS64.
>> 
>> gcc/ChangeLog:
>>PR: 104914.
>>* expmed.cc(store_bit_field_1): Get mode from original
>>str_rtx instead of op0.
>> ---
>> gcc/expmed.cc | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/gcc/expmed.cc b/gcc/expmed.cc
>> index fbd4ce2d42f..37f90912122 100644
>> --- a/gcc/expmed.cc
>> +++ b/gcc/expmed.cc
>> @@ -849,7 +849,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
>> poly_uint64 bitnum,
>>  if we aren't.  This must come after the entire register case above,
>>  since that case is valid for any mode.  The following cases are only
>>  valid for integral modes.  */
>> -  opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (op0));
>> +  opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (str_rtx));
> 
> I don't think this is correct - op0_mode is used to store into op0, and we are
> just requiring that it is an integer mode and equal to the original
> mode.  I suppose
> your patch makes us go to the fallback code instead, but it's surely
> for the wrong

diff --git a/gcc/expmed.cc b/gcc/expmed.cc
index fbd4ce2d42f..feee8c82f59 100644
--- a/gcc/expmed.cc
+++ b/gcc/expmed.cc
@@ -850,6 +861,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
poly_uint64 bitnum,
  since that case is valid for any mode.  The following cases are only
  valid for integral modes.  */
   opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (op0));
+  opt_scalar_int_mode str_mode = int_mode_for_mode (GET_MODE (str_rtx));
   scalar_int_mode imode;
   if (!op0_mode.exists (&imode) || imode != GET_MODE (op0))
 {
@@ -881,8 +893,14 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
poly_uint64 bitnum,
op0 = gen_lowpart (op0_mode.require (), op0);
 }
 
-  return store_integral_bit_field (op0, op0_mode, ibitsize, ibitnum,
-  bitregion_start, bitregion_end,
+  bool use_str_mode = false;
+  if (GET_MODE_CLASS(GET_MODE (str_rtx)) == MODE_INT
+  && GET_MODE_CLASS(GET_MODE (op0)) == MODE_INT
+  && known_gt (GET_MODE_SIZE(GET_MODE(op0)), 
GET_MODE_SIZE(GET_MODE(str_rtx
+   use_str_mode = true;
+  return store_integral_bit_field (op0,
+  use_str_mode ? str_mode : op0_mode,
+  ibitsize, ibitnum, bitregion_start, 
bitregion_end,
   fieldmode, value, reverse, fallback_p);
 }

> reason.  I also wonder why we don't just check GET_MODE_CLASS
> (GET_MODE (op0)) == MODE_CLASS_INT ...
> 

In fact I have no idea. Maybe there are some other tricky cases.

>>   scalar_int_mode imode;
>>   if (!op0_mode.exists (&imode) || imode != GET_MODE (op0))
>> {
>> --
>> 2.30.2

[PATCH] Store_bit_field_1: Use SUBREG instead of REG if possible

[YunQiang Su]

PR #104914

When work with
  int val;
  ((unsigned char*)&val)[3] = *buf;
  if (val > 0) ...
The RTX mode is obtained from REG instead of SUBREG, which make
D is used instead of .  Thus something wrong happens
on sign-extend default architectures, like MIPS64.

Let's use str_rtx and mode of str_rtx as the parameters for
store_integral_bit_field if:
  modes of op0 and str_rtx are INT;
  length of op0 is greater than str_rtx.

This patch has been tested on aarch64-linux-gnu, x86_64-linux-gnu,
mips64el-linux-gnuabi64 without regression.

gcc/ChangeLog:
PR: 104914.
* expmed.cc(store_bit_field_1): Pass str_rtx and its mode
to store_integral_bit_field if the length of op0 is greater
than str_rtx.

gcc/testsuite/ChangeLog:
PR: 104914.
* gcc.target/mips/pr104914.c: New testcase.
---
 gcc/expmed.cc|  20 +-
 gcc/testsuite/gcc.target/mips/pr104914.c |  17 ++
 gcc/xx   | 233 +++
 gcc/xx.log   |   1 +
 4 files changed, 268 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/pr104914.c
 create mode 100644 gcc/xx
 create mode 100644 gcc/xx.log

diff --git a/gcc/expmed.cc b/gcc/expmed.cc
index fbd4ce2d42f..5531c19e891 100644
--- a/gcc/expmed.cc
+++ b/gcc/expmed.cc
@@ -850,6 +850,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
poly_uint64 bitnum,
  since that case is valid for any mode.  The following cases are only
  valid for integral modes.  */
   opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (op0));
+  opt_scalar_int_mode str_mode = int_mode_for_mode (GET_MODE (str_rtx));
   scalar_int_mode imode;
   if (!op0_mode.exists (&imode) || imode != GET_MODE (op0))
 {
@@ -881,9 +882,22 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
poly_uint64 bitnum,
op0 = gen_lowpart (op0_mode.require (), op0);
 }
 
-  return store_integral_bit_field (op0, op0_mode, ibitsize, ibitnum,
-  bitregion_start, bitregion_end,
-  fieldmode, value, reverse, fallback_p);
+  /* If MODEs of str_rtx and op0 are INT, and the length of op0 is greater than
+ str_rtx, it means that str_rtx has a shorter SUBREG: int32 on 64 mach/ABI
+ is an example.  For this case, we should use the mode of SUBREG, otherwise
+ bad code will generate for sign-extension ports, like MIPS.  */
+  bool use_str_mode = false;
+  if (GET_MODE_CLASS (GET_MODE (str_rtx)) == MODE_INT
+  && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
+  && known_gt (GET_MODE_SIZE (GET_MODE (op0)),
+  GET_MODE_SIZE (GET_MODE (str_rtx
+use_str_mode = true;
+
+  return store_integral_bit_field (use_str_mode ? str_rtx : op0,
+  use_str_mode ? str_mode : op0_mode,
+  ibitsize, ibitnum, bitregion_start,
+  bitregion_end, fieldmode, value,
+  reverse, fallback_p);
 }
 
 /* Subroutine of store_bit_field_1, with the same arguments, except
diff --git a/gcc/testsuite/gcc.target/mips/pr104914.c 
b/gcc/testsuite/gcc.target/mips/pr104914.c
new file mode 100644
index 000..fd6ef6af446
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr104914.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=mips64r2 -mabi=64" } */
+
+/* { dg-final { scan-assembler-not "\tdins\t" } } */
+
+NOMIPS16 int test (const unsigned char *buf)
+{
+  int val;
+  ((unsigned char*)&val)[0] = *buf++;
+  ((unsigned char*)&val)[1] = *buf++;
+  ((unsigned char*)&val)[2] = *buf++;
+  ((unsigned char*)&val)[3] = *buf++;
+  if(val > 0)
+return 1;
+  else
+return 0;
+}
diff --git a/gcc/xx b/gcc/xx
new file mode 100644
index 000..664e8ba8b25
--- /dev/null
+++ b/gcc/xx
@@ -0,0 +1,233 @@
+DEFTREECODE (ERROR_MARK, "error_mark", tcc_exceptional, 0)
+DEFTREECODE (IDENTIFIER_NODE, "identifier_node", tcc_exceptional, 0)
+DEFTREECODE (TREE_LIST, "tree_list", tcc_exceptional, 0)
+DEFTREECODE (TREE_VEC, "tree_vec", tcc_exceptional, 0)
+DEFTREECODE (BLOCK, "block", tcc_exceptional, 0)
+DEFTREECODE (OFFSET_TYPE, "offset_type", tcc_type, 0)
+DEFTREECODE (ENUMERAL_TYPE, "enumeral_type", tcc_type, 0)
+DEFTREECODE (BOOLEAN_TYPE, "boolean_type", tcc_type, 0)
+DEFTREECODE (INTEGER_TYPE, "integer_type", tcc_type, 0)
+DEFTREECODE (REAL_TYPE, "real_type", tcc_type, 0)
+DEFTREECODE (POINTER_TYPE, "pointer_type", tcc_type, 0)
+DEFTREECODE (REFERENCE_TYPE, "reference_type", tcc_type, 0)
+DEFTREECODE (NULLPTR_TYPE, "nullptr_type", tcc_type, 0)
+DEFTREECODE (FIXED_POINT_TYPE, "fixed_point_type", tcc_type, 0)
+DEFTREECODE (COMPLEX_TYPE, "complex_type", tcc_type, 0)
+DEFTREECODE (VECTOR_TYPE, "vector_type", tcc_type, 0)
+DEFTREECODE (ARRAY_TYPE, "array_type", tcc_type, 0)
+DEFTREECODE (RECORD_TYPE, "record_type", tcc_type, 0)
+DEFTREECODE (UNION_TYPE, "union_type", tcc_type,

[PATCH v2] Store_bit_field_1: Use SUBREG instead of REG if possible

[YunQiang Su]

PR #104914

When work with
  int val;
  ((unsigned char*)&val)[3] = *buf;
  if (val > 0) ...
The RTX mode is obtained from REG instead of SUBREG, which make
D is used instead of .  Thus something wrong happens
on sign-extend default architectures, like MIPS64.

Let's use str_rtx and mode of str_rtx as the parameters for
store_integral_bit_field if:
  modes of op0 and str_rtx are INT;
  length of op0 is greater than str_rtx.

This patch has been tested on aarch64-linux-gnu, x86_64-linux-gnu,
mips64el-linux-gnuabi64 without regression.

gcc/ChangeLog:
PR: 104914.
* expmed.cc(store_bit_field_1): Pass str_rtx and its mode
to store_integral_bit_field if the length of op0 is greater
than str_rtx.

gcc/testsuite/ChangeLog:
PR: 104914.
* gcc.target/mips/pr104914.c: New testcase.
---
 gcc/expmed.cc| 20 +---
 gcc/testsuite/gcc.target/mips/pr104914.c | 17 +
 2 files changed, 34 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/pr104914.c

diff --git a/gcc/expmed.cc b/gcc/expmed.cc
index fbd4ce2d42f..5531c19e891 100644
--- a/gcc/expmed.cc
+++ b/gcc/expmed.cc
@@ -850,6 +850,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
poly_uint64 bitnum,
  since that case is valid for any mode.  The following cases are only
  valid for integral modes.  */
   opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (op0));
+  opt_scalar_int_mode str_mode = int_mode_for_mode (GET_MODE (str_rtx));
   scalar_int_mode imode;
   if (!op0_mode.exists (&imode) || imode != GET_MODE (op0))
 {
@@ -881,9 +882,22 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
poly_uint64 bitnum,
op0 = gen_lowpart (op0_mode.require (), op0);
 }
 
-  return store_integral_bit_field (op0, op0_mode, ibitsize, ibitnum,
-  bitregion_start, bitregion_end,
-  fieldmode, value, reverse, fallback_p);
+  /* If MODEs of str_rtx and op0 are INT, and the length of op0 is greater than
+ str_rtx, it means that str_rtx has a shorter SUBREG: int32 on 64 mach/ABI
+ is an example.  For this case, we should use the mode of SUBREG, otherwise
+ bad code will generate for sign-extension ports, like MIPS.  */
+  bool use_str_mode = false;
+  if (GET_MODE_CLASS (GET_MODE (str_rtx)) == MODE_INT
+  && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
+  && known_gt (GET_MODE_SIZE (GET_MODE (op0)),
+  GET_MODE_SIZE (GET_MODE (str_rtx
+use_str_mode = true;
+
+  return store_integral_bit_field (use_str_mode ? str_rtx : op0,
+  use_str_mode ? str_mode : op0_mode,
+  ibitsize, ibitnum, bitregion_start,
+  bitregion_end, fieldmode, value,
+  reverse, fallback_p);
 }
 
 /* Subroutine of store_bit_field_1, with the same arguments, except
diff --git a/gcc/testsuite/gcc.target/mips/pr104914.c 
b/gcc/testsuite/gcc.target/mips/pr104914.c
new file mode 100644
index 000..fd6ef6af446
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr104914.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=mips64r2 -mabi=64" } */
+
+/* { dg-final { scan-assembler-not "\tdins\t" } } */
+
+NOMIPS16 int test (const unsigned char *buf)
+{
+  int val;
+  ((unsigned char*)&val)[0] = *buf++;
+  ((unsigned char*)&val)[1] = *buf++;
+  ((unsigned char*)&val)[2] = *buf++;
+  ((unsigned char*)&val)[3] = *buf++;
+  if(val > 0)
+return 1;
+  else
+return 0;
+}
-- 
2.30.2

[PATCH] MIPS: improve -march=native arch detection

[YunQiang Su]

If we cannot get info from options and cpuinfo, we try to get from:
  1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7
  2. _MIPS_ARCH from host compiler.

This can fix the wrong loader usage on r5/r6 platform with
 -march=native.

gcc/ChangeLog:
* config/mips/driver-native.cc (host_detect_local_cpu):
  try getauxval(AT_BASE_PLATFORM) and _MIPS_ARCH, too.
---
 gcc/config/mips/driver-native.cc | 22 +++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/gcc/config/mips/driver-native.cc b/gcc/config/mips/driver-native.cc
index 47627f85ce1..9aa7044c0b8 100644
--- a/gcc/config/mips/driver-native.cc
+++ b/gcc/config/mips/driver-native.cc
@@ -19,6 +19,7 @@ along with GCC; see the file COPYING3.  If not see
 
 #define IN_TARGET_CODE 1
 
+#include 
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
@@ -46,15 +47,15 @@ host_detect_local_cpu (int argc, const char **argv)
   bool arch;
 
   if (argc < 1)
-return NULL;
+goto fallback_cpu;
 
   arch = strcmp (argv[0], "arch") == 0;
   if (!arch && strcmp (argv[0], "tune"))
-return NULL;
+goto fallback_cpu;
 
   f = fopen ("/proc/cpuinfo", "r");
   if (f == NULL)
-return NULL;
+goto fallback_cpu;
 
   while (fgets (buf, sizeof (buf), f) != NULL)
 if (startswith (buf, "cpu model"))
@@ -84,8 +85,23 @@ host_detect_local_cpu (int argc, const char **argv)
 
   fclose (f);
 
+fallback_cpu:
+/*FIXME: how about other OSes, like FreeBSD? */
+#ifdef __linux__
+  /*Note: getauxval may return NULL as:
+   * AT_BASE_PLATFORM is supported since Linux 5.7
+   * Or from older version of qemu-user
+   * */
+  if (cpu == NULL)
+cpu = (const char *) getauxval (AT_BASE_PLATFORM);
+#endif
+
   if (cpu == NULL)
+#if defined (_MIPS_ARCH)
+cpu = _MIPS_ARCH;
+#else
 return NULL;
+#endif
 
   return concat ("-m", argv[0], "=", cpu, NULL);
 }
-- 
2.30.2

[RFC] Combine zero_extract and sign_extend for TARGET_TRULY_NOOP_TRUNCATION

[YunQiang Su]

PR #104914

On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
zero_extract (SI, SI) can be sign-extended.  So, if a zero_extract (DI,
DI) following with an sign_extend(SI, DI) can be merged to a single
zero_extract (SI, SI).

gcc/ChangeLog:
PR: 104914.
* combine.cc (try_combine): Combine zero_extract (DI, DI) and
  following sign_extend (DI, SI) for
  TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true.
  (subst): Allow replacing reg(DI) with subreg(SI (reg DI))
  if to is SImode and from is DImode for
  TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true.

gcc/testsuite/ChangeLog:
PR: 104914.
* gcc.target/mips/pr104914.c: New testcase.
---
 gcc/combine.cc   | 88 
 gcc/testsuite/gcc.target/mips/pr104914.c | 17 +
 2 files changed, 90 insertions(+), 15 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/pr104914.c

diff --git a/gcc/combine.cc b/gcc/combine.cc
index e46d202d0a7..701b7c33b17 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -3294,15 +3294,64 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, 
rtx_insn *i0,
   n_occurrences = 0;   /* `subst' counts here */
   subst_low_luid = DF_INSN_LUID (i2);
 
-  /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
-copy of I2SRC each time we substitute it, in order to avoid creating
-self-referential RTL when we will be substituting I1SRC for I1DEST
-later.  Likewise if I0 feeds into I2, either directly or indirectly
-through I1, and I0DEST is in I0SRC.  */
-  newpat = subst (PATTERN (i3), i2dest, i2src, false, false,
- (i1_feeds_i2_n && i1dest_in_i1src)
- || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
- && i0dest_in_i0src));
+  /* Try to combine zero_extract (DImode) and sign_extend (SImode to 
DImode)
+for TARGET_TRULY_NOOP_TRUNCATION.  The RTL may look like:
+
+(insn 10 49 11 2 (set (zero_extract:DI (reg/v:DI 200 [ val ])
+   (const_int 8 [0x8])
+   (const_int 0 [0]))
+(subreg:DI (reg:QI 202 [ *buf_8(D) ]) 0)) "xx.c":4:29 278 {*insvdi}
+(expr_list:REG_DEAD (reg:QI 202 [ *buf_8(D) ]) (nil)))
+(insn 11 10 12 2 (set (reg/v:DI 200 [ val ])
+
+(sign_extend:DI (subreg:SI (reg/v:DI 200 [ val ]) 0))) 238 
{extendsidi2}
+(nil))
+
+Since these architectures (MIPS64 as an example), the 32bit operation
+instructions will sign-extend the reuslt to 64bit.  The result can be:
+
+(insn 10 49 11 2 (set (zero_extract:SI (subreg:SI (reg/v:DI 200 [ val 
]) 0)
+  (const_int 8 [0x8])
+  (const_int 0 [0]))
+(subreg:SI (reg:QI 202 [ *buf_8(D) ]) 0)) "xx.c":4:29 280 {*insvsi}
+(expr_list:REG_DEAD (reg:QI 202 [ *buf_8(D) ]) (nil)))
+   */
+  if (i0 == 0 && i1 == 0 && i3 != 0 && i2 != 0 && GET_CODE (i2) == INSN
+ && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i2)) == SET
+ && GET_CODE (PATTERN (i3)) == SET
+ && GET_CODE (SET_DEST (single_set (i2))) == ZERO_EXTRACT
+ && GET_CODE (SET_SRC (single_set (i3))) == SIGN_EXTEND
+ && SUBREG_P (XEXP (SET_SRC (single_set (i3)), 0))
+ && REGNO (SUBREG_REG (XEXP (SET_SRC (single_set (i3)), 0)))
+== REGNO (SET_DEST (single_set (i3)))
+ && REGNO (XEXP (SET_DEST (single_set (i2)), 0))
+== REGNO (SET_DEST (single_set (i3)))
+ && GET_MODE (SET_DEST (single_set (i2))) == DImode
+ && GET_MODE (SET_DEST (single_set (i3))) == DImode
+ && GET_MODE (XEXP (SET_SRC (single_set (i3)), 0)) == SImode
+ && TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode))
+   {
+ newpat = copy_rtx (PATTERN (i2));
+ PUT_MODE (SET_DEST (newpat), SImode);
+ PUT_MODE (SET_SRC (newpat), SImode);
+
+ rtx i2dest_r = XEXP (SET_DEST (newpat), 0);
+ rtx i3src_r = XEXP (SET_SRC (single_set (i3)), 0);
+ newpat = subst (newpat, i2dest_r, i3src_r, false, false, false);
+   }
+  else
+   {
+ /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a
+unique copy of I2SRC each time we substitute it, in order to
+avoid creating self-referential RTL when we will be substituting
+I1SRC for I1DEST later.  Likewise if I0 feeds into I2, either
+directly or indirectly through I1, and I0DEST is in I0SRC.  */
+ newpat = subst (
+ PATTERN (i3), i2dest, i2src, false, false,
+ (i1_feeds_i2_n && i1dest_in_i1src)
+ || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
+ && i0dest_in_i0src));
+   }
   substed_i2 = true;
 
   /* Record whether I2's body now appears within I3's body.  */
@@ -5482,13

Re: [PATCH v5] MIPS: Add speculation_barrier support

[YunQiang Su]

Richard Earnshaw (lists) via Gcc-patches 
于2023年6月8日周四 20:36写道：
>
>
> On 01/06/2023 05:26, YunQiang Su wrote:
> > speculation_barrier for MIPS needs sync+jr.hb (r2+),
> > so we implement __speculation_barrier in libgcc, like arm32 does.
> >
> > gcc/ChangeLog:
> >   * config/mips/mips-protos.h (mips_emit_speculation_barrier): New
> >  prototype.
> >   * config/mips/mips.cc (speculation_barrier_libfunc): New static
> >  variable.
> >   (mips_init_libfuncs): Initialize it.
> >   (mips_emit_speculation_barrier): New function.
> >   * config/mips/mips.md (speculation_barrier): Call
> >  mips_emit_speculation_barrier.
> >
> > libgcc/ChangeLog:
> >   * config/mips/lib1funcs.S: New file.
> >   define __speculation_barrier and include mips16.S.
> >   * config/mips/t-mips: define LIB1ASMSRC as mips/lib1funcs.S.
> >   define LIB1ASMFUNCS as _speculation_barrier.
> >   set version info for __speculation_barrier.
> >   * config/mips/libgcc-mips.ver: New file.
> >   * config/mips/t-mips16: don't define LIB1ASMSRC as mips16.S
> >   included in lib1funcs.S now.
> > ---
>
> Please remember to cite PR86793 when committing this fix.
>

Ohh, sorry. I forget it. I commented there.
I have no permission to close this bug report. Can you help to close it?

> R.
>
> >   gcc/config/mips/mips-protos.h  |  2 +
> >   gcc/config/mips/mips.cc| 12 ++
> >   gcc/config/mips/mips.md| 12 ++
> >   libgcc/config/mips/lib1funcs.S | 65 ++
> >   libgcc/config/mips/libgcc-mips.ver | 21 ++
> >   libgcc/config/mips/t-mips  |  7 
> >   libgcc/config/mips/t-mips16|  3 +-
> >   7 files changed, 120 insertions(+), 2 deletions(-)
> >   create mode 100644 libgcc/config/mips/lib1funcs.S
> >   create mode 100644 libgcc/config/mips/libgcc-mips.ver
> >
> > diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
> > index 20483469105..da7902c235b 100644
> > --- a/gcc/config/mips/mips-protos.h
> > +++ b/gcc/config/mips/mips-protos.h
> > @@ -388,4 +388,6 @@ extern void mips_register_frame_header_opt (void);
> >   extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
> >   extern void mips_expand_vec_cmp_expr (rtx *);
> >
> > +extern void mips_emit_speculation_barrier_function (void);
> > +
> >   #endif /* ! GCC_MIPS_PROTOS_H */
> > diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
> > index ca491b981a3..c1d1691306e 100644
> > --- a/gcc/config/mips/mips.cc
> > +++ b/gcc/config/mips/mips.cc
> > @@ -13611,6 +13611,9 @@ mips_autovectorize_vector_modes (vector_modes 
> > *modes, bool)
> > return 0;
> >   }
> >
> > +
> > +static GTY (()) rtx speculation_barrier_libfunc;
> > +
> >   /* Implement TARGET_INIT_LIBFUNCS.  */
> >
> >   static void
> > @@ -13680,6 +13683,7 @@ mips_init_libfuncs (void)
> > synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
> > init_sync_libfuncs (UNITS_PER_WORD);
> >   }
> > +  speculation_barrier_libfunc = init_one_libfunc ("__speculation_barrier");
> >   }
> >
> >   /* Build up a multi-insn sequence that loads label TARGET into $AT.  */
> > @@ -19092,6 +19096,14 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn 
> > *insn, int *hilo_delay,
> > }
> >   }
> >
> > +/* Emit a speculation barrier.
> > +   JR.HB is needed, so we put speculation_barrier_libfunc in libgcc.  */
> > +void
> > +mips_emit_speculation_barrier_function ()
> > +{
> > +  emit_library_call (speculation_barrier_libfunc, LCT_NORMAL, VOIDmode);
> > +}
> > +
> >   /* A SEQUENCE is breakable iff the branch inside it has a compact form
> >  and the target has compact branches.  */
> >
> > diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
> > index ac1d77afc7d..5d04ac566dd 100644
> > --- a/gcc/config/mips/mips.md
> > +++ b/gcc/config/mips/mips.md
> > @@ -160,6 +160,8 @@
> > ;; The `.insn' pseudo-op.
> > UNSPEC_INSN_PSEUDO
> > UNSPEC_JRHB
> > +
> > +  VUNSPEC_SPECULATION_BARRIER
> >   ])
> >
> >   (define_constants
> > @@ -7455,6 +7457,16 @@
> > mips_expand_conditional_move (operands);
> > DONE;
> >   })
> > +
> > +(define_expand "speculation_barrier"
> > +  [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULA

[PATCH] MIPS: Use -mnan value for -mabs if not specified

[YunQiang Su]

On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008.
Let's use this behaivor by default in GCC, aka
gcc -mnan=2008 -c fabs.c
will imply `-mabs=2008`.

And of course, `gcc -mnan=2008 -mabs=legacy` can continue workable
like previous.

gcc/ChangeLog:

* config/mips/mips.cc(mips_option_override): Set mips_abs to
2008, if mips_abs is default and mips_nan is 2008.
* testsuite/gcc.target/mips/fabs-nan2008.c: New test.
* testsuite/gcc.target/mips/fabsf-nan2008.c: New test.
---
 gcc/config/mips/mips.cc   |  2 ++
 gcc/testsuite/gcc.target/mips/fabs-nan2008.c  | 10 ++
 gcc/testsuite/gcc.target/mips/fabsf-nan2008.c | 10 ++
 3 files changed, 22 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/fabs-nan2008.c
 create mode 100644 gcc/testsuite/gcc.target/mips/fabsf-nan2008.c

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index f9861020902..7fd54503660 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -20549,6 +20549,8 @@ mips_option_override (void)
   /* Set NaN and ABS defaults.  */
   if (mips_nan == MIPS_IEEE_754_DEFAULT && !ISA_HAS_IEEE_754_LEGACY)
 mips_nan = MIPS_IEEE_754_2008;
+  if (mips_abs == MIPS_IEEE_754_DEFAULT && mips_nan == MIPS_IEEE_754_2008)
+mips_abs = MIPS_IEEE_754_2008;
   if (mips_abs == MIPS_IEEE_754_DEFAULT && !ISA_HAS_IEEE_754_LEGACY)
 mips_abs = MIPS_IEEE_754_2008;
 
diff --git a/gcc/testsuite/gcc.target/mips/fabs-nan2008.c 
b/gcc/testsuite/gcc.target/mips/fabs-nan2008.c
new file mode 100644
index 000..9e2719bbf36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/fabs-nan2008.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=2008" } */
+
+NOMIPS16 double
+fabs_2008 (double d)
+{
+  return __builtin_fabs (d);
+}
+
+/* { dg-final { scan-assembler "\tabs\\.d\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/fabsf-nan2008.c 
b/gcc/testsuite/gcc.target/mips/fabsf-nan2008.c
new file mode 100644
index 000..11c423429d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/fabsf-nan2008.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=2008" } */
+
+NOMIPS16 float
+fabsf_2008 (float f)
+{
+  return __builtin_fabsf (f);
+}
+
+/* { dg-final { scan-assembler "\tabs\\.s\t" } } */
-- 
2.39.2

[PATCH v3] MIPS: add speculation_barrier support

[YunQiang Su]

speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.

gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
variable.
(mips_init_libfuncs): Initialize it.
(mips_emit_speculation_barrier): New function.
* config/mips/mips.md (speculation_barrier): Call
mips_emit_speculation_barrier.
* configure.ac: error if gas doesn't accept ssnop for mips1.
* configure: regenerated.
* doc/install.texi: documents mips requires binutils 2.21+.

libgcc/ChangeLog:
* config/mips/lib1funcs.S: New file.
define __speculation_barrier and include mips16.S.
* config/mips/t-mips: define LIB1ASMSRC as mips/lib1funcs.S.
define LIB1ASMFUNCS as _speculation_barrier.
set version info for __speculation_barrier.
* config/mips/libgcc-mips.ver: New file.
* config/mips/t-mips16: don't define LIB1ASMSRC as mips16.S is
included in lib1funcs.S now.
---
 gcc/config/mips/mips-protos.h  |  2 +
 gcc/config/mips/mips.cc| 13 ++
 gcc/config/mips/mips.md| 12 ++
 gcc/configure  | 32 +++
 gcc/configure.ac   |  7 
 gcc/doc/install.texi   |  2 +
 libgcc/config/mips/lib1funcs.S | 63 ++
 libgcc/config/mips/libgcc-mips.ver | 21 ++
 libgcc/config/mips/t-mips  |  7 
 libgcc/config/mips/t-mips16|  3 +-
 10 files changed, 160 insertions(+), 2 deletions(-)
 create mode 100644 libgcc/config/mips/lib1funcs.S
 create mode 100644 libgcc/config/mips/libgcc-mips.ver

diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 20483469105..da7902c235b 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -388,4 +388,6 @@ extern void mips_register_frame_header_opt (void);
 extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
 extern void mips_expand_vec_cmp_expr (rtx *);
 
+extern void mips_emit_speculation_barrier_function (void);
+
 #endif /* ! GCC_MIPS_PROTOS_H */
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ca822758b41..139707fda34 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -13611,6 +13611,9 @@ mips_autovectorize_vector_modes (vector_modes *modes, 
bool)
   return 0;
 }
 
+
+static GTY(()) rtx speculation_barrier_libfunc;
+
 /* Implement TARGET_INIT_LIBFUNCS.  */
 
 static void
@@ -13680,6 +13683,7 @@ mips_init_libfuncs (void)
   synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
   init_sync_libfuncs (UNITS_PER_WORD);
 }
+  speculation_barrier_libfunc = init_one_libfunc ("__speculation_barrier");
 }
 
 /* Build up a multi-insn sequence that loads label TARGET into $AT.  */
@@ -19092,6 +19096,15 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, 
int *hilo_delay,
   }
 }
 
+/* Emit a speculation barrier.
+   JR.HB is needed, so we need to put
+   speculation_barrier_libfunc in libgcc */
+void
+mips_emit_speculation_barrier_function ()
+{
+  emit_library_call (speculation_barrier_libfunc, LCT_NORMAL, VOIDmode);
+}
+
 /* A SEQUENCE is breakable iff the branch inside it has a compact form
and the target has compact branches.  */
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index ac1d77afc7d..5d04ac566dd 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -160,6 +160,8 @@
   ;; The `.insn' pseudo-op.
   UNSPEC_INSN_PSEUDO
   UNSPEC_JRHB
+
+  VUNSPEC_SPECULATION_BARRIER
 ])
 
 (define_constants
@@ -7455,6 +7457,16 @@
   mips_expand_conditional_move (operands);
   DONE;
 })
+
+(define_expand "speculation_barrier"
+  [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
+  ""
+  "
+  mips_emit_speculation_barrier_function ();
+  DONE;
+  "
+)
+
 
 ;;
 ;;  
diff --git a/gcc/configure b/gcc/configure
index 191f68581b3..e55b40d7f4c 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -28699,6 +28699,38 @@ $as_echo "#define HAVE_LD_PERSONALITY_RELAXATION 1" 
>>confdefs.h
 
 fi
 
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for mips1 
recognize ssnop" >&5
+$as_echo_n "checking assembler for mips1 recognize ssnop... " >&6; }
+if ${gcc_cv_as_mips1_ssnop+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  gcc_cv_as_mips1_ssnop=no
+  if test x$gcc_cv_as != x; then
+$as_echo 'ssnop' > conftest.s
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags -mabi=32 -mips1 -o conftest.o 
conftest.s >&5'
+  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ echo $ac_try
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }
+then
+   gcc_cv_as_mips1_ssnop=yes
+else
+  

[PATCH v4] MIPS: add speculation_barrier support

[YunQiang Su]

speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.

gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
variable.
(mips_init_libfuncs): Initialize it.
(mips_emit_speculation_barrier): New function.
* config/mips/mips.md (speculation_barrier): Call
mips_emit_speculation_barrier.
* configure.ac: error if gas doesn't accept ssnop for mips1.
* configure: regenerated.
* doc/install.texi: documents mips requires binutils 2.21+.

libgcc/ChangeLog:
* config/mips/lib1funcs.S: New file.
define __speculation_barrier and include mips16.S.
* config/mips/t-mips: define LIB1ASMSRC as mips/lib1funcs.S.
define LIB1ASMFUNCS as _speculation_barrier.
set version info for __speculation_barrier.
* config/mips/libgcc-mips.ver: New file.
* config/mips/t-mips16: don't define LIB1ASMSRC as mips16.S is
included in lib1funcs.S now.
---
 gcc/config/mips/mips-protos.h  |  2 +
 gcc/config/mips/mips.cc| 13 +++
 gcc/config/mips/mips.md| 12 ++
 gcc/configure  | 32 +++
 gcc/configure.ac   |  7 
 gcc/doc/install.texi   |  2 +
 libgcc/config/mips/lib1funcs.S | 62 ++
 libgcc/config/mips/libgcc-mips.ver | 21 ++
 libgcc/config/mips/t-mips  |  7 
 libgcc/config/mips/t-mips16|  3 +-
 10 files changed, 159 insertions(+), 2 deletions(-)
 create mode 100644 libgcc/config/mips/lib1funcs.S
 create mode 100644 libgcc/config/mips/libgcc-mips.ver

diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 20483469105..da7902c235b 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -388,4 +388,6 @@ extern void mips_register_frame_header_opt (void);
 extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
 extern void mips_expand_vec_cmp_expr (rtx *);
 
+extern void mips_emit_speculation_barrier_function (void);
+
 #endif /* ! GCC_MIPS_PROTOS_H */
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ca822758b41..139707fda34 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -13611,6 +13611,9 @@ mips_autovectorize_vector_modes (vector_modes *modes, 
bool)
   return 0;
 }
 
+
+static GTY(()) rtx speculation_barrier_libfunc;
+
 /* Implement TARGET_INIT_LIBFUNCS.  */
 
 static void
@@ -13680,6 +13683,7 @@ mips_init_libfuncs (void)
   synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
   init_sync_libfuncs (UNITS_PER_WORD);
 }
+  speculation_barrier_libfunc = init_one_libfunc ("__speculation_barrier");
 }
 
 /* Build up a multi-insn sequence that loads label TARGET into $AT.  */
@@ -19092,6 +19096,15 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, 
int *hilo_delay,
   }
 }
 
+/* Emit a speculation barrier.
+   JR.HB is needed, so we need to put
+   speculation_barrier_libfunc in libgcc */
+void
+mips_emit_speculation_barrier_function ()
+{
+  emit_library_call (speculation_barrier_libfunc, LCT_NORMAL, VOIDmode);
+}
+
 /* A SEQUENCE is breakable iff the branch inside it has a compact form
and the target has compact branches.  */
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index ac1d77afc7d..5d04ac566dd 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -160,6 +160,8 @@
   ;; The `.insn' pseudo-op.
   UNSPEC_INSN_PSEUDO
   UNSPEC_JRHB
+
+  VUNSPEC_SPECULATION_BARRIER
 ])
 
 (define_constants
@@ -7455,6 +7457,16 @@
   mips_expand_conditional_move (operands);
   DONE;
 })
+
+(define_expand "speculation_barrier"
+  [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
+  ""
+  "
+  mips_emit_speculation_barrier_function ();
+  DONE;
+  "
+)
+
 
 ;;
 ;;  
diff --git a/gcc/configure b/gcc/configure
index 191f68581b3..e55b40d7f4c 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -28699,6 +28699,38 @@ $as_echo "#define HAVE_LD_PERSONALITY_RELAXATION 1" 
>>confdefs.h
 
 fi
 
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for mips1 
recognize ssnop" >&5
+$as_echo_n "checking assembler for mips1 recognize ssnop... " >&6; }
+if ${gcc_cv_as_mips1_ssnop+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  gcc_cv_as_mips1_ssnop=no
+  if test x$gcc_cv_as != x; then
+$as_echo 'ssnop' > conftest.s
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags -mabi=32 -mips1 -o conftest.o 
conftest.s >&5'
+  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ echo $ac_try
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }
+then
+   gcc_cv_as_mips1_ssnop=yes
+else
+ 

[PATCH] MIPS: don't expand large block move

[YunQiang Su]

On platform with LWL/LWR, mips_block_move_loop is always used,
which expand __buildin_memcpy/strcpy to a loop of lwl/lwr/swl/swl etc.

For short (normally <=64), it has better performance,
but when the src/dest are long, use memcpy/strcpy lib call may have
better performance.

At the same time, lib call may be optimized with SIMD, so,
on the platform with SIMD, lib call may have much better performace.

gcc/ChangeLog:
* config/mips/mips.cc (mips_expand_block_move): don't expand
  if length>=64.

gcc/testsuite/ChangeLog:
* gcc.target/mips/expand-block-move-large.c: New test.
---
 gcc/config/mips/mips.cc |  6 ++
 .../gcc.target/mips/expand-block-move-large.c   | 17 +
 2 files changed, 23 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/expand-block-move-large.c

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ca491b981a3..00f26d5e923 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -8313,6 +8313,12 @@ mips_expand_block_move (rtx dest, rtx src, rtx length)
}
   else if (optimize)
{
+ /* When the length is big enough, the lib call has better performace
+than load/store insns.
+In most platform, the value is about 64-128.
+And in fact lib call may be optimized with SIMD */
+ if (INTVAL(length) >= 64)
+   return false;
  mips_block_move_loop (dest, src, INTVAL (length),
MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
  return true;
diff --git a/gcc/testsuite/gcc.target/mips/expand-block-move-large.c 
b/gcc/testsuite/gcc.target/mips/expand-block-move-large.c
new file mode 100644
index 000..ae054551a2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/expand-block-move-large.c
@@ -0,0 +1,17 @@
+/* { dg-options "isa_rev<=5" } */
+/* { dg-final { scan-assembler-not "lwl" } } */
+/* { dg-final { scan-assembler-not "swl" } } */
+/* { dg-final { scan-assembler-not "lwr" } } */
+/* { dg-final { scan-assembler-not "swr" } } */
+/* { dg-final { scan-assembler-not "ldl" } } */
+/* { dg-final { scan-assembler-not "sdl" } } */
+/* { dg-final { scan-assembler-not "ldr" } } */
+/* { dg-final { scan-assembler-not "sdr" } } */
+
+char a[4097], b[4097];
+
+NOCOMPRESSION void
+foo (volatile int *x)
+{
+  __builtin_memcpy(&a[1], &b[1], 64);
+}
-- 
2.30.2

Re: [PATCH] MIPS: don't expand large block move

[YunQiang Su]

Maciej W. Rozycki  于2023年5月20日周六 03:21写道：
>
> On Fri, 19 May 2023, Jeff Law wrote:
>
> > > diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
> > > index ca491b981a3..00f26d5e923 100644
> > > --- a/gcc/config/mips/mips.cc
> > > +++ b/gcc/config/mips/mips.cc
> > > @@ -8313,6 +8313,12 @@ mips_expand_block_move (rtx dest, rtx src, rtx
> > > length)
> > > }
> > > else if (optimize)
> > > {
> > > + /* When the length is big enough, the lib call has better performace
> > > +than load/store insns.
> > > +In most platform, the value is about 64-128.
> > > +And in fact lib call may be optimized with SIMD */
> > > + if (INTVAL(length) >= 64)
> > > +   return false;
> > Just a formatting nit.  Space between INTVAL and the open paren for its
> > argument list.
>
>  This is oddly wrapped too.  I'd move "performace" (typo there!) to the
> second line, to align better with the rest of the text.
>
>  Plus s/platform/platforms/ and there's a full stop missing along with two
> spaces at the end.  Also there's inconsistent style around <= and >=; the
> GNU Coding Standards ask for spaces around binary operators.  And "don't"
> in the change heading ought to be capitalised.
>
>  In fact, I'd justify the whole paragraph as each sentence doesn't have to
> start on a new line, and the commit description could benefit from some
> reformatting too, as it's now odd to read.
>

Thank you. I will fix these problems.

> > OK with that change.
>
>  I think the conditional would be better readable if it was flattened
> though:
>
>   if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
> ...
>   else if (INTVAL (length) >= 64)
> ...
>   else if (optimize)
> ...
>

This sounds good.

> or even:
>
>   if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
> ...
>   else if (INTVAL (length) < 64 && optimize)
> ...
>

I don't think this is a good option, since somebody may add some code,
and may break our logic.

> One just wouldn't write it as proposed if creating the whole piece from
> scratch rather than retrofitting this extra conditional.
>
>  Ultimately it may have to be tunable as LWL/LWR, etc. may be subject to
> fusion and may be faster after all.
>

oohhh, you are right.
And in fact this patch has some problems:
If the data is aligned, the value is about 1024, instead of 64-128.

>   Maciej

[PATCH 1/3] MIPS: add -mcompact-branches=prefer option

[YunQiang Su]

For MIPSr6, we may wish to use compact-branches only.
Currently, we have to use `always' option, while it is mark as conflict
with pre-R6.
  cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always

It make some trouble for distributions to make -mcompact-branches=always
default for R6 only.

The new added `prefer' option:
   just ignored by pre-R6 target.
   do the same as `always' for R6+.
---
 gcc/config/mips/mips-opts.h|  3 ++-
 gcc/config/mips/mips.h |  6 --
 gcc/config/mips/mips.opt   |  3 +++
 gcc/doc/invoke.texi|  6 ++
 gcc/testsuite/gcc.target/mips/compact-branches-8.c | 10 ++
 gcc/testsuite/gcc.target/mips/compact-branches-9.c | 10 ++
 6 files changed, 35 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-8.c
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-9.c

diff --git a/gcc/config/mips/mips-opts.h b/gcc/config/mips/mips-opts.h
index 6214849f3e1..f3804b9722b 100644
--- a/gcc/config/mips/mips-opts.h
+++ b/gcc/config/mips/mips-opts.h
@@ -51,6 +51,7 @@ enum mips_r10k_cache_barrier_setting {
 enum mips_cb_setting {
   MIPS_CB_NEVER,
   MIPS_CB_OPTIMAL,
-  MIPS_CB_ALWAYS
+  MIPS_CB_ALWAYS,
+  MIPS_CB_PREFER
 };
 #endif
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index b4a60a55d80..f8762fe6638 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -106,20 +106,22 @@ struct mips_cpu_info {
'never' policy or the 'optimal' policy on a core that lacks
compact branch instructions.  */
 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER  \
-|| (mips_cb == MIPS_CB_OPTIMAL \
+|| ((mips_cb == MIPS_CB_OPTIMAL || mips_cb == 
MIPS_CB_PREFER) \
 && !ISA_HAS_COMPACT_BRANCHES))
 
 /* Compact branches may be used if the user either selects the
'always' policy or the 'optimal' policy on a core that supports
compact branch instructions.  */
 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS  \
-|| (mips_cb == MIPS_CB_OPTIMAL \
+|| ((mips_cb == MIPS_CB_OPTIMAL || mips_cb == 
MIPS_CB_PREFER) \
 && ISA_HAS_COMPACT_BRANCHES))
 
 /* Compact branches must always be generated if the user selects
the 'always' policy or the 'optimal' policy om a core that
lacks delay slot branch instructions.  */
 #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS\
+|| (mips_cb == MIPS_CB_PREFER \
+&& ISA_HAS_COMPACT_BRANCHES)   \
 || (mips_cb == MIPS_CB_OPTIMAL \
 && !ISA_HAS_DELAY_SLOTS))
 
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 6af8037e9bd..f2d7550e36c 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -464,6 +464,9 @@ Enum(mips_cb_setting) String(optimal) Value(MIPS_CB_OPTIMAL)
 EnumValue
 Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS)
 
+EnumValue
+Enum(mips_cb_setting) String(prefer) Value(MIPS_CB_PREFER)
+
 mloongson-mmi
 Target Mask(LOONGSON_MMI)
 Use Loongson MultiMedia extensions Instructions (MMI) instructions.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3751bc3ac7c..9493c508d5b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -25199,9 +25199,11 @@ and MIPS64 architectures specifically deprecate their 
use.
 @item -mcompact-branches=never
 @itemx -mcompact-branches=optimal
 @itemx -mcompact-branches=always
+@itemx -mcompact-branches=prefer
 @opindex mcompact-branches=never
 @opindex mcompact-branches=optimal
 @opindex mcompact-branches=always
+@opindex mcompact-branches=prefer
 These options control which form of branches will be generated.  The
 default is @option{-mcompact-branches=optimal}.
 
@@ -25215,6 +25217,10 @@ used instead.
 
 This option is supported from MIPS Release 6 onwards.
 
+The @option{-mcompact-branches=prefer} option is same with
+@option{-mcompact-branches=always} for MIPS Release 6 onwards, and
+is same with @option{-mcompact-branches=never} for pre-R6.
+
 The @option{-mcompact-branches=optimal} option will cause a delay slot
 branch to be used if one is available in the current ISA and the delay
 slot is successfully filled.  If the delay slot is not filled, a compact
diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-8.c 
b/gcc/testsuite/gcc.target/mips/compact-branches-8.c
new file mode 100644
index 000..72ffcb49cfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/compact-branches-8.c
@@ -0,0 +1,10 @@
+/* { dg-options "-mno-abicalls -mcompact-branches=prefer isa_rev<=5" } */
+void bar (int);
+
+void
+foo ()
+{
+  bar (1);
+}
+
+/* { dg-final { scan-assembler "\t(j|jal)\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-9.c 
b/gcc/testsuite/gcc.target/

[PATCH 3/3] MIPS: fix compact-branches test FAIL for PIC default configuration

[YunQiang Su]

GCC may be configured to use PIC by default, then the test with
-mno-abicall may fail. Just add -fno-PIC option for it.
---
 gcc/testsuite/gcc.target/mips/compact-branches-5.c | 2 +-
 gcc/testsuite/gcc.target/mips/compact-branches-6.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-5.c 
b/gcc/testsuite/gcc.target/mips/compact-branches-5.c
index 90d312c614d..0189635bf61 100644
--- a/gcc/testsuite/gcc.target/mips/compact-branches-5.c
+++ b/gcc/testsuite/gcc.target/mips/compact-branches-5.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mcompact-branches=never isa_rev>=6" } */
+/* { dg-options "-mno-abicalls -fno-PIC -mcompact-branches=never isa_rev>=6" } 
*/
 void bar (int);
 
 void
diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-6.c 
b/gcc/testsuite/gcc.target/mips/compact-branches-6.c
index dd35a5581bd..36180b0c76c 100644
--- a/gcc/testsuite/gcc.target/mips/compact-branches-6.c
+++ b/gcc/testsuite/gcc.target/mips/compact-branches-6.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mcompact-branches=optimal isa_rev>=6" } */
+/* { dg-options "-mno-abicalls -fno-PIC -mcompact-branches=optimal isa_rev>=6" 
} */
 void bar (int);
 
 void
-- 
2.20.1

[PATCH 2/3] MIPS: add builtime option for -mcompact-branches

[YunQiang Su]

For R6+, it allows to configure gcc to use compact branches only.
---
 gcc/config.gcc   | 18 +-
 gcc/doc/install.texi | 23 +++
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 17fea83b2e4..7d50e7995d2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4743,7 +4743,7 @@ case "${target}" in
;;
 
mips*-*-*)
-   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4"
+   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4 compact-branches"
 
case ${with_float} in
"" | soft | hard)
@@ -4896,6 +4896,22 @@ case "${target}" in
exit 1
;;
esac
+
+   case ${with_compact_branches} in
+   never | always | optimal | prefer)
+   if test "$with_compact_branches" = "always" -a \
+   "$default_mips_arch" != "mips32r6" -a  \
+   "$default_mips_arch" != "mips64r6";then
+   echo "Compact-branch=always is not allowed for 
pre-R6" 1>&2
+   exit 1
+   fi
+   with_compact_branches=${with_compact_branches}
+   ;;
+   *)
+   echo "Unknown compact-branches policy used in 
--with-compact-branches" 1>&2
+   exit 1
+   ;;
+   esac
;;
 
nds32*-*-*)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 4c38244ae58..6b9520569ba 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1464,6 +1464,29 @@ systems that support conditional traps).
 Division by zero checks use the break instruction.
 @end table
 
+@item --with-compact-branches=@var{policy}
+Specify how the compiler should generate code for checking for
+division by zero.  This option is only supported on the MIPS target.
+The possibilities for @var{type} are:
+@table @code
+@item optimal
+Cause a delay slot branch to be used if one is available in the
+current ISA and the delay slot is successfully filled. If the delay slot
+is not filled, a compact branch will be chosen if one is available.
+@item never
+Ensures that compact branch instructions will never be generated.
+@item always
+Ensures that a compact branch instruction will be generated if available.
+If a compact branch instruction is not available,
+a delay slot form of the branch will be used instead.
+This option is supported from MIPS Release 6 onwards.
+@item prefer
+Ensures that a compact branch instruction will be generated if available
+on MIPS Release 6 onwards.
+Simliar with @option{always} besides that this option works for pre-R6
+target, on which, this option will just be ignored.
+@end table
+
 @c If you make --with-llsc the default for additional targets,
 @c update the --with-llsc description in the MIPS section below.
 
-- 
2.20.1

[PATCH 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

[YunQiang Su]

It is found by ada s-pack96.adb ftbfs, due to 96bit load: 96 = 64 + 32.
While the 32bit pair of l r is mark as SUBREG, so they are
not in SImode, make it fail to find suitable insn.

gcc/ChangeLog:

   * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
   If TARGET_64BIT and dest is SUBREG, we check the width, if it
   equal to SImode, we use SImode operation, just like what we are
   doing for REG one.
---
 gcc/ChangeLog  | 8 
 gcc/config/mips/mips.c | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ddf4c7f92d7..fb12eeb971d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2021-02-15  YunQiang Su  
+
+   PR target/98996
+   * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
+   If TARGET_64BIT and dest is SUBREG, we check the width, if it
+   equal to SImode, we use SImode operation, just like what we are
+   doing for REG one.
+
 2021-02-11  Eric Botcazou  
 
* config/i386/winnt.c (i386_pe_seh_unwind_emit): When switching to
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index ebb04b72b2b..b77604f935d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -8400,7 +8400,7 @@ mips_expand_ext_as_unaligned_load (rtx dest, rtx src, 
HOST_WIDE_INT width,
   /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
  be a DImode, create a new temp and emit a zero extend at the end.  */
   if (GET_MODE (dest) == DImode
-  && REG_P (dest)
+  && (REG_P (dest) || SUBREG_P(dest))
   && GET_MODE_BITSIZE (SImode) == width)
 {
   dest1 = dest;
-- 
2.20.1

[PATCH 2/2] ada: add 128bit operation to MIPS N32 and N64

[YunQiang Su]

For MIPS N64 and N32:
  add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS
  add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS

gcc/ada/ChangeLog:
PR ada/98996
* Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS)
: add 128Bit operation file to MIPS N64 and N32.
---
 gcc/ada/ChangeLog|  6 ++
 gcc/ada/Makefile.rtl | 12 
 2 files changed, 18 insertions(+)

diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index 43973550502..32e92c55ef8 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,9 @@
+2021-02-03  YunQiang Su  
+
+   PR ada/98996
+   * Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS)
+   : add 128Bit operation file to MIPS N64 and N32.
+
 2021-02-03  Eric Botcazou  
 
* gcc-interface/decl.c (components_to_record): If the first component
diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
index 35faf13ea46..d86eb8acbf3 100644
--- a/gcc/ada/Makefile.rtl
+++ b/gcc/ada/Makefile.rtl
@@ -2311,6 +2311,18 @@ ifeq ($(strip $(filter-out mips% linux%,$(target_cpu) 
$(target_os))),)
   s-tpopsp.adb

Re: [PATCH 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

[YunQiang Su]

Jeff Law  于2021年2月17日周三 上午3:16写道：
>
>
>
> On 2/14/21 6:33 PM, YunQiang Su wrote:
> > It is found by ada s-pack96.adb ftbfs, due to 96bit load: 96 = 64 + 32.
> > While the 32bit pair of l r is mark as SUBREG, so they are
> > not in SImode, make it fail to find suitable insn.
> >
> > gcc/ChangeLog:
> >
> >* config/mips/mips.c (mips_expand_ext_as_unaligned_load):
> >If TARGET_64BIT and dest is SUBREG, we check the width, if it
> >equal to SImode, we use SImode operation, just like what we are
> >doing for REG one.
> > ---
> >  gcc/ChangeLog  | 8 
> >  gcc/config/mips/mips.c | 2 +-
> >  2 files changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> > index ddf4c7f92d7..fb12eeb971d 100644
> > --- a/gcc/ChangeLog
> > +++ b/gcc/ChangeLog
> > @@ -1,3 +1,11 @@
> > +2021-02-15  YunQiang Su  
> > +
> > + PR target/98996
> > + * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
> > + If TARGET_64BIT and dest is SUBREG, we check the width, if it
> > + equal to SImode, we use SImode operation, just like what we are
> > + doing for REG one.
> Do you need to do any checking on the contents of the SUBREG?  ie, do
> you need to know if you've got (subreg (reg)) vs (subreg (mem))
>

Yes. you are right, we'd better to check it.

> Similarly I'd expect you may need to look at the mode of the inner
> object.  You could have a true subreg (outer mode is smaller than inner
> mode), but you might also be able to have a paradoxical subreg (outer
> mode is larger than inner mode).
>

I don't think that it is needed, since we we make sure that the mode
of `dest' is DImode,
and the width is SImode.

> Jeff
>

[PATCH v2 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

[YunQiang Su]

It is found by ada s-pack96.adb ftbfs, due to 96bit load: 96 = 64 + 32.
While the 32bit pair of l r is mark as SUBREG, so they are
not in SImode, make it fail to find suitable insn.

gcc/ChangeLog:

   * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
   If TARGET_64BIT and dest is SUBREG, we check the width, if it
   equal to SImode, we use SImode operation, just like what we are
   doing for REG one.
---
 gcc/ChangeLog  | 8 
 gcc/config/mips/mips.c | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0b3bdcee619..3c91791feac 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2021-02-18  YunQiang Su  
+
+   PR target/98996
+   * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
+   If TARGET_64BIT and dest is SUBREG, we check the width, if it
+   equal to SImode, we use SImode operation, just like what we are
+   doing for REG one.
+
 2021-02-17  Julian Brown  
 
* gimplify.c (gimplify_scan_omp_clauses): Handle ATTACH_DETACH
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8bd2d29552e..e901d860c3d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -8400,7 +8400,7 @@ mips_expand_ext_as_unaligned_load (rtx dest, rtx src, 
HOST_WIDE_INT width,
   /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
  be a DImode, create a new temp and emit a zero extend at the end.  */
   if (GET_MODE (dest) == DImode
-  && REG_P (dest)
+  && (REG_P (dest) || (SUBREG_P(dest) && !MEM_P(SUBREG_REG(dest
   && GET_MODE_BITSIZE (SImode) == width)
 {
   dest1 = dest;
-- 
2.20.1

[PATCH v2 2/2] ada: add 128bit operation to MIPS N32 and N64

[YunQiang Su]

For MIPS N64 and N32:
  add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS
  add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS

gcc/ada/ChangeLog:
PR ada/98996
* Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS)
: add 128Bit operation file to MIPS N64 and N32.
---
 gcc/ada/ChangeLog|  6 ++
 gcc/ada/Makefile.rtl | 12 
 2 files changed, 18 insertions(+)

diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index 52faefaa2ae..3565a32c5ac 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,9 @@
+2021-02-18  YunQiang Su  
+
+   PR ada/98996
+   * Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS)
+   : add 128Bit operation file to MIPS N64 and N32.
+
 2021-02-12  Arnaud Charlet  
 
* repinfo.ads, repinfo.adb (*SO_Ref*): Restore.
diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
index 35faf13ea46..d86eb8acbf3 100644
--- a/gcc/ada/Makefile.rtl
+++ b/gcc/ada/Makefile.rtl
@@ -2311,6 +2311,18 @@ ifeq ($(strip $(filter-out mips% linux%,$(target_cpu) 
$(target_os))),)
   s-tpopsp.adb

Re: [PATCH v2 2/2] ada: add 128bit operation to MIPS N32 and N64

[YunQiang Su]

Arnaud Charlet  于2021年2月18日周四 下午3:38写道：
>
> > For MIPS N64 and N32:
> >   add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS
> >   add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS
> >
> > gcc/ada/ChangeLog:
> >   PR ada/98996
> >   * Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS)
> >   : add 128Bit operation file to MIPS N64 and N32.
>
> Note that the ChangeLog is generated automatically these days.

Thank you for your instruction. I noticed the contrib/mklog.py.
It generate the template of ChangeLog.
Should I resend a new version of patch?

>
> The change is OK, thanks.
>
> > ---
> >  gcc/ada/ChangeLog|  6 ++
> >  gcc/ada/Makefile.rtl | 12 
> >  2 files changed, 18 insertions(+)
> >
> > diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
> > index 52faefaa2ae..3565a32c5ac 100644
> > --- a/gcc/ada/ChangeLog
> > +++ b/gcc/ada/ChangeLog
> > @@ -1,3 +1,9 @@
> > +2021-02-18  YunQiang Su  
> > +
> > + PR ada/98996
> > + * Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS)
> > + : add 128Bit operation file to MIPS N64 and N32.
> > +
> >  2021-02-12  Arnaud Charlet  
> >
> >   * repinfo.ads, repinfo.adb (*SO_Ref*): Restore.
> > diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
> > index 35faf13ea46..d86eb8acbf3 100644
> > --- a/gcc/ada/Makefile.rtl
> > +++ b/gcc/ada/Makefile.rtl
> > @@ -2311,6 +2311,18 @@ ifeq ($(strip $(filter-out mips% 
> > linux%,$(target_cpu) $(target_os))),)
> >s-tpopsp.adb >system.ads >
> > +  ifeq ($(strip $(filter-out mips64% mipsisa64%,$(target_cpu))),)
> > +ifneq ($(strip $(MULTISUBDIR)),/32)
> > +  LIBGNAT_TARGET_PAIRS += $(GNATRTL_128BIT_PAIRS)
> > +  EXTRA_GNATRTL_NONTASKING_OBJS += $(GNATRTL_128BIT_OBJS)
> > +endif
> > +  else
> > +ifeq ($(strip $(filter-out /64 /n32,$(MULTISUBDIR))),)
> > +  LIBGNAT_TARGET_PAIRS += $(GNATRTL_128BIT_PAIRS)
> > +  EXTRA_GNATRTL_NONTASKING_OBJS += $(GNATRTL_128BIT_OBJS)
> > +endif
> > +  endif
> > +
> >TOOLS_TARGET_PAIRS = indepsw.adb >
> >EXTRA_GNATRTL_TASKING_OBJS=s-linux.o
> > --
> > 2.20.1

Re: [PATCH 2/3] MIPS: add builtime option for -mcompact-branches

[YunQiang Su]

Maciej W. Rozycki  于2021年2月17日周三 上午3:45写道：
>
> On Tue, 16 Feb 2021, Jeff Law via Gcc-patches wrote:
>
> > > diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
> > > index 4c38244ae58..6b9520569ba 100644
> > > --- a/gcc/doc/install.texi
> > > +++ b/gcc/doc/install.texi
> > > @@ -1464,6 +1464,29 @@ systems that support conditional traps).
> > >  Division by zero checks use the break instruction.
> > >  @end table
> > >
> > > +@item --with-compact-branches=@var{policy}
> > > +Specify how the compiler should generate code for checking for
> > > +division by zero.  This option is only supported on the MIPS target.
> > > +The possibilities for @var{type} are:
> > Is this really correct -- I would expect that the change affects
> > branches in general, not just checks for division by zero.
>
>  I wonder if we need to multiply the options here at all.  The original
> change:  was
> discussed here: 
> in this respect:
>
> On Mon, 17 Aug 2015, Matthew Fortune wrote:
>
> > > > Compact branches are used based on a branch policy. The polices are:
> > > >
> > > > never: Only use delay slot branches
> > > > optimal: Do whatever is best for the current architecture.  This will
> > > >  generally mean that delay slot branches will be used if the 
> > > > delay
> > > >  slot gets filled but otherwise a compact branch will be used. A
> > > >  special case here is that JAL and J will not be used in R6 code
> > > >  regardless of whether the delay slot could be filled.
> > > > always: Never emit a delay slot form of a branch if a compact form 
> > > > exists.
> > > > This policy cannot apply 100% as FP branches (and MSA branches 
> > > > when
> > > > committed) only have delay slot forms.
> > > >
> > > > These user choices are combined with the features available in the 
> > > > chosen
> > > > architecture and, in particular, the optimal form will get handled like
> > > > 'never' when there are no compact branches available and will get 
> > > > handled
> > > > like 'always' when there are no delay slot branches available.
> > > >
> > >
> > > Why did you choose to make this a user-selectable option?  Why not always 
> > > generated
> > > optimal?
> > > I don't have a strong opinion about it, but the options seem to 
> > > complicate things and I'm
> > > interested in your rationale.
> >
> > This is down to micro-architecture decisions that different implementers 
> > may make.
> > Honestly, I have not absorbed all of the rationale behind choosing one form 
> > over
> > the other but our arch team have made enough comments about this to mean 
> > the support
> > in the compiler is worth the extra bit of effort. I can attempt a write-up 
> > of some
> > of the pipeline possibilities if you would like more detail but I'd 
> > probably have to
> > refresh my mind on this with our hardware teams.
>
>  My understanding therefore is that the original assumption that `optimal'
> will serve people best is no longer true.
>

I guess that `optimal' can still produce the best performance, while
the delay slot
make MIPS quite differnent with other architectures.
And the hardware engineers seems hate it also.

And we expect that MIPS can have as few as possible differnece delta
with other major architectures,
to ultily all of new framworks of community.

>  First, I think it would be good if we knew why.  I find proliferating
> variants of defaults, especially for the less obvious cases, will cause
> user confusion as one won't know what code model to expect, especially as
> (please correct me if I am wrong) we don't actually provide a way to dump
> the compiler's overridable configuration defaults.
>

So, should we provide a predefined macro for it?

>  Second, I wonder if it makes sense to just keep things simple, and rather
> than adding `prefer' (to stand for "`always' if available"), and possibly
> `avoid' (to stand for "`never' if available"), whether we shouldn't just
> relax the checks for `always' and `never', and let them through whether
> the architecture selected provides for the option chosen or not.
>

relax the `always' is what I would like to do first.
But I was afread to break some complatiable.

>  Please note that in the discussion quoted Catherine has already raised a
> concern I agree with of adding a complication here, and now we would
> complicate it even further by not only adding a fourth choice, but another
> overridable configuration default as well.

I am still concern about whether we should just set the `always' as default.
My short team plan is to set it default for Debian r6 Port.
So, at least, I wish that we can provide a buildtime option for other need.

>
>   Maciej

[PATCH v2 1/2] MIPS: Not trigger error for pre-R6 and -mcompact-branches=always

[YunQiang Su]

For MIPSr6, we may wish to use compact-branches only.
Currently, we have to use `always' option, while it is mark as conflict
with pre-R6.
  cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always
Just ignore -mcompact-branches=always for pre-R6.

This patch also defines
__mips_compact_branches_never
__mips_compact_branches_always
__mips_compact_branches_optimal
predefined macros
---
 gcc/config/mips/mips.c|  8 +--
 gcc/config/mips/mips.h| 22 ---
 gcc/doc/invoke.texi   |  1 +
 .../gcc.target/mips/compact-branches-1.c  |  2 +-
 .../gcc.target/mips/compact-branches-8.c  | 10 +
 .../gcc.target/mips/compact-branches-9.c  | 10 +
 gcc/testsuite/gcc.target/mips/mips.exp|  4 +---
 7 files changed, 38 insertions(+), 19 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-8.c
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-9.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8bd2d29552e..9a75dd61031 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -20107,13 +20107,7 @@ mips_option_override (void)
   target_flags |= MASK_ODD_SPREG;
 }
 
-  if (!ISA_HAS_COMPACT_BRANCHES && mips_cb == MIPS_CB_ALWAYS)
-{
-  error ("unsupported combination: %qs%s %s",
- mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
- "-mcompact-branches=always");
-}
-  else if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
+  if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
 {
   error ("unsupported combination: %qs%s %s",
  mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index b4a60a55d80..b8399fe1b0d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -103,11 +103,9 @@ struct mips_cpu_info {
 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
 
 /* Compact branches must not be used if the user either selects the
-   'never' policy or the 'optimal' policy on a core that lacks
+   'never' policy or the 'optimal' / 'always' policy on a core that lacks
compact branch instructions.  */
-#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER  \
-|| (mips_cb == MIPS_CB_OPTIMAL \
-&& !ISA_HAS_COMPACT_BRANCHES))
+#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER || !ISA_HAS_COMPACT_BRANCHES)
 
 /* Compact branches may be used if the user either selects the
'always' policy or the 'optimal' policy on a core that supports
@@ -117,10 +115,11 @@ struct mips_cpu_info {
 && ISA_HAS_COMPACT_BRANCHES))
 
 /* Compact branches must always be generated if the user selects
-   the 'always' policy or the 'optimal' policy om a core that
-   lacks delay slot branch instructions.  */
-#define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS\
-|| (mips_cb == MIPS_CB_OPTIMAL \
+   the 'always' policy on a core support compact branches,
+   or the 'optimal' policy on a core that lacks delay slot branch 
instructions.  */
+#define TARGET_CB_ALWAYS ((mips_cb == MIPS_CB_ALWAYS \
+&& ISA_HAS_COMPACT_BRANCHES) \
+|| (mips_cb == MIPS_CB_OPTIMAL   \
 && !ISA_HAS_DELAY_SLOTS))
 
 /* Special handling for JRC that exists in microMIPSR3 as well as R6
@@ -655,6 +654,13 @@ struct mips_cpu_info {
builtin_define ("__mips_no_lxc1_sxc1"); \
   if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4)  \
builtin_define ("__mips_no_madd4"); \
+   \
+  if (TARGET_CB_NEVER) \
+   builtin_define ("__mips_compact_branches_never");   \
+  else if (TARGET_CB_ALWAYS)   \
+   builtin_define ("__mips_compact_branches_always");  \
+  else \
+   builtin_define ("__mips_compact_branches_optimal"); \
 }  \
   while (0)
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c00514a6306..63f9b85d7ab 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -25227,6 +25227,7 @@ instruction is not available, a delay slot form of the 
branch will be
 used instead.
 
 This option is supported from MIPS Release 6 onwards.
+If it is used for pre-R6 target, it will be just ignored.
 
 The @option{-mcompact-branches=optimal} option will cause a delay slot
 branch to be used if one is available in the current ISA and the delay
diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-1.c 
b/gcc

[PATCH v2 2/2] MIPS: add builtime option for -mcompact-branches

[YunQiang Su]

For R6+ target, it allows to configure gcc to use compact branches only.
---
 gcc/config.gcc   | 12 +++-
 gcc/doc/install.texi | 19 +++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 17fea83b2e4..047f5631067 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4743,7 +4743,7 @@ case "${target}" in
;;
 
mips*-*-*)
-   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4"
+   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4 compact-branches"
 
case ${with_float} in
"" | soft | hard)
@@ -4896,6 +4896,16 @@ case "${target}" in
exit 1
;;
esac
+
+   case ${with_compact_branches} in
+   never | always | optimal)
+   with_compact_branches=${with_compact_branches}
+   ;;
+   *)
+   echo "Unknown compact-branches policy used in 
--with-compact-branches" 1>&2
+   exit 1
+   ;;
+   esac
;;
 
nds32*-*-*)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 4c38244ae58..865630826c6 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1464,6 +1464,25 @@ systems that support conditional traps).
 Division by zero checks use the break instruction.
 @end table
 
+@item --with-compact-branches=@var{policy}
+Specify how the compiler should generate code for checking for
+division by zero.  This option is only supported on the MIPS target.
+The possibilities for @var{type} are:
+@table @code
+@item optimal
+Cause a delay slot branch to be used if one is available in the
+current ISA and the delay slot is successfully filled. If the delay slot
+is not filled, a compact branch will be chosen if one is available.
+@item never
+Ensures that compact branch instructions will never be generated.
+@item always
+Ensures that a compact branch instruction will be generated if available.
+If a compact branch instruction is not available,
+a delay slot form of the branch will be used instead.
+This option is supported from MIPS Release 6 onwards.
+For pre-R6, this option is just same as never/optimal.
+@end table
+
 @c If you make --with-llsc the default for additional targets,
 @c update the --with-llsc description in the MIPS section below.
 
-- 
2.20.1

[PATCH v3 1/2] MIPS: Not trigger error for pre-R6 and -mcompact-branches=always

[YunQiang Su]

For MIPSr6, we may wish to use compact-branches only.
Currently, we have to use `always' option, while it is mark as conflict
with pre-R6.
  cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always
Just ignore -mcompact-branches=always for pre-R6.

This patch also defines
__mips_compact_branches_never
__mips_compact_branches_always
__mips_compact_branches_optimal
predefined macros

gcc/ChangeLog:
* config/mips/mips.c (mips_option_override):
* config/mips/mips.h (TARGET_RTP_PIC): not trigger error for
compact-branches=always for pre-R6.
(TARGET_CB_NEVER): Likewise.
(TARGET_CB_ALWAYS): Likewise.
(struct mips_cpu_info): define macros for compact branch policy.
* doc/invoke.texi: Document "always" with pre-R6.

gcc/testsuite/ChangeLog:
* gcc.target/mips/compact-branches-1.c: add isa_rev>=6.
* gcc.target/mips/mips.exp: don't add -mipsXXr6 option for
-mcompact-branches=always. It is usable for pre-R6 now.
* gcc.target/mips/compact-branches-8.c: New test.
* gcc.target/mips/compact-branches-9.c: New test.
---
 gcc/ChangeLog | 10 +
 gcc/config/mips/mips.c|  8 +--
 gcc/config/mips/mips.h| 22 ---
 gcc/doc/invoke.texi   |  1 +
 gcc/testsuite/ChangeLog   |  8 +++
 .../gcc.target/mips/compact-branches-1.c  |  2 +-
 .../gcc.target/mips/compact-branches-8.c  | 10 +
 .../gcc.target/mips/compact-branches-9.c  | 10 +
 gcc/testsuite/gcc.target/mips/mips.exp|  4 +---
 9 files changed, 56 insertions(+), 19 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-8.c
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-9.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eb1a44ae676..caa3fda48ce 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2021-02-20  YunQiang Su  
+
+   * config/mips/mips.c (mips_option_override):
+   * config/mips/mips.h (TARGET_RTP_PIC): not trigger error for
+   compact-branches=always for pre-R6.
+   (TARGET_CB_NEVER): Likewise.
+   (TARGET_CB_ALWAYS): Likewise.
+   (struct mips_cpu_info): define macros for compact branch policy.
+   * doc/invoke.texi: Document "always" with pre-R6.
+
 2021-02-19  Martin Sebor  
 
PR c/97172
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8bd2d29552e..9a75dd61031 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -20107,13 +20107,7 @@ mips_option_override (void)
   target_flags |= MASK_ODD_SPREG;
 }
 
-  if (!ISA_HAS_COMPACT_BRANCHES && mips_cb == MIPS_CB_ALWAYS)
-{
-  error ("unsupported combination: %qs%s %s",
- mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
- "-mcompact-branches=always");
-}
-  else if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
+  if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
 {
   error ("unsupported combination: %qs%s %s",
  mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index b4a60a55d80..b8399fe1b0d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -103,11 +103,9 @@ struct mips_cpu_info {
 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
 
 /* Compact branches must not be used if the user either selects the
-   'never' policy or the 'optimal' policy on a core that lacks
+   'never' policy or the 'optimal' / 'always' policy on a core that lacks
compact branch instructions.  */
-#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER  \
-|| (mips_cb == MIPS_CB_OPTIMAL \
-&& !ISA_HAS_COMPACT_BRANCHES))
+#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER || !ISA_HAS_COMPACT_BRANCHES)
 
 /* Compact branches may be used if the user either selects the
'always' policy or the 'optimal' policy on a core that supports
@@ -117,10 +115,11 @@ struct mips_cpu_info {
 && ISA_HAS_COMPACT_BRANCHES))
 
 /* Compact branches must always be generated if the user selects
-   the 'always' policy or the 'optimal' policy om a core that
-   lacks delay slot branch instructions.  */
-#define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS\
-|| (mips_cb == MIPS_CB_OPTIMAL \
+   the 'always' policy on a core support compact branches,
+   or the 'optimal' policy on a core that lacks delay slot branch 
instructions.  */
+#define TARGET_CB_ALWAYS ((mips_cb == MIPS_CB_ALWAYS

[PATCH v3 2/2] MIPS: add builtime option for -mcompact-branches

[YunQiang Su]

For R6+ target, it allows to configure gcc to use compact branches only.

gcc/ChangeLog:
* config.gcc: add -with-compact-branches=policy build option.
* doc/install.texi: Likewise.
---
 gcc/ChangeLog|  5 +
 gcc/config.gcc   | 12 +++-
 gcc/doc/install.texi | 19 +++
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index caa3fda48ce..c5fae50e782 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2021-02-20  YunQiang Su  
+
+   * config.gcc: add -with-compact-branches=policy build option.
+   * doc/install.texi: Likewise.
+
 2021-02-20  YunQiang Su  
 
* config/mips/mips.c (mips_option_override):
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 17fea83b2e4..047f5631067 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4743,7 +4743,7 @@ case "${target}" in
;;
 
mips*-*-*)
-   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4"
+   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4 compact-branches"
 
case ${with_float} in
"" | soft | hard)
@@ -4896,6 +4896,16 @@ case "${target}" in
exit 1
;;
esac
+
+   case ${with_compact_branches} in
+   never | always | optimal)
+   with_compact_branches=${with_compact_branches}
+   ;;
+   *)
+   echo "Unknown compact-branches policy used in 
--with-compact-branches" 1>&2
+   exit 1
+   ;;
+   esac
;;
 
nds32*-*-*)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 4c38244ae58..865630826c6 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1464,6 +1464,25 @@ systems that support conditional traps).
 Division by zero checks use the break instruction.
 @end table
 
+@item --with-compact-branches=@var{policy}
+Specify how the compiler should generate code for checking for
+division by zero.  This option is only supported on the MIPS target.
+The possibilities for @var{type} are:
+@table @code
+@item optimal
+Cause a delay slot branch to be used if one is available in the
+current ISA and the delay slot is successfully filled. If the delay slot
+is not filled, a compact branch will be chosen if one is available.
+@item never
+Ensures that compact branch instructions will never be generated.
+@item always
+Ensures that a compact branch instruction will be generated if available.
+If a compact branch instruction is not available,
+a delay slot form of the branch will be used instead.
+This option is supported from MIPS Release 6 onwards.
+For pre-R6, this option is just same as never/optimal.
+@end table
+
 @c If you make --with-llsc the default for additional targets,
 @c update the --with-llsc description in the MIPS section below.
 
-- 
2.20.1

Re: [PATCH v2 2/2] ada: add 128bit operation to MIPS N32 and N64

[YunQiang Su]

Arnaud Charlet  于2021年2月18日周四 下午4:51写道：
>
> > > > For MIPS N64 and N32:
> > > >   add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS
> > > >   add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS
> > > >
> > > > gcc/ada/ChangeLog:
> > > >   PR ada/98996
> > > >   * Makefile.rtl (LIBGNAT_TARGET_PAIRS, 
> > > > EXTRA_GNATRTL_NONTASKING_OBJS)
> > > >   : add 128Bit operation file to MIPS N64 and N32.
> > >
> > > Note that the ChangeLog is generated automatically these days.
> >
> > Thank you for your instruction. I noticed the contrib/mklog.py.
> > It generate the template of ChangeLog.
> > Should I resend a new version of patch?
>
> No need to as far as I'm concerned, you can go ahead and commit your change.

I have no permission to do so.

> There are commit hooks checking the proper format of the commit log these
> days anyway.
>
> Arno

Re: [PATCH v2 2/2] ada: add 128bit operation to MIPS N32 and N64

[YunQiang Su]

Arnaud Charlet  于2021年2月18日周四 下午3:38写道：
>
> > For MIPS N64 and N32:
> >   add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS
> >   add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS
> >
> > gcc/ada/ChangeLog:
> >   PR ada/98996
> >   * Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS)
> >   : add 128Bit operation file to MIPS N64 and N32.
>
> Note that the ChangeLog is generated automatically these days.
>
> The change is OK, thanks.

can you help me to commit this patchset?

>
> > ---
> >  gcc/ada/ChangeLog|  6 ++
> >  gcc/ada/Makefile.rtl | 12 
> >  2 files changed, 18 insertions(+)
> >
> > diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
> > index 52faefaa2ae..3565a32c5ac 100644
> > --- a/gcc/ada/ChangeLog
> > +++ b/gcc/ada/ChangeLog
> > @@ -1,3 +1,9 @@
> > +2021-02-18  YunQiang Su  
> > +
> > + PR ada/98996
> > + * Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS)
> > + : add 128Bit operation file to MIPS N64 and N32.
> > +
> >  2021-02-12  Arnaud Charlet  
> >
> >   * repinfo.ads, repinfo.adb (*SO_Ref*): Restore.
> > diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
> > index 35faf13ea46..d86eb8acbf3 100644
> > --- a/gcc/ada/Makefile.rtl
> > +++ b/gcc/ada/Makefile.rtl
> > @@ -2311,6 +2311,18 @@ ifeq ($(strip $(filter-out mips% 
> > linux%,$(target_cpu) $(target_os))),)
> >s-tpopsp.adb >system.ads >
> > +  ifeq ($(strip $(filter-out mips64% mipsisa64%,$(target_cpu))),)
> > +ifneq ($(strip $(MULTISUBDIR)),/32)
> > +  LIBGNAT_TARGET_PAIRS += $(GNATRTL_128BIT_PAIRS)
> > +  EXTRA_GNATRTL_NONTASKING_OBJS += $(GNATRTL_128BIT_OBJS)
> > +endif
> > +  else
> > +ifeq ($(strip $(filter-out /64 /n32,$(MULTISUBDIR))),)
> > +  LIBGNAT_TARGET_PAIRS += $(GNATRTL_128BIT_PAIRS)
> > +  EXTRA_GNATRTL_NONTASKING_OBJS += $(GNATRTL_128BIT_OBJS)
> > +endif
> > +  endif
> > +
> >TOOLS_TARGET_PAIRS = indepsw.adb >
> >EXTRA_GNATRTL_TASKING_OBJS=s-linux.o
> > --
> > 2.20.1

[PATCH v3 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

[YunQiang Su]

It is found by ada s-pack96.adb ftbfs, due to 96bit load: 96 = 64 + 32.
While the 32bit pair of l r is mark as SUBREG, so they are
not in SImode, make it fail to find suitable insn.

gcc/ChangeLog:

   * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
   If TARGET_64BIT and dest is SUBREG, we check the width, if it
   equal to SImode, we use SImode operation, just like what we are
   doing for REG one.
---
 gcc/ChangeLog  | 8 
 gcc/config/mips/mips.c | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3bd877243b7..e86d7817d9d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2021-02-23  YunQiang Su  
+
+   PR target/98996
+   * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
+   If TARGET_64BIT and dest is SUBREG, we check the width, if it
+   equal to SImode, we use SImode operation, just like what we are
+   doing for REG one.
+
 2021-02-22  Kyrylo Tkachov  
 
* config/aarch64/aarch64-tuning-flags.def (cse_sve_vl_constants):
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8bd2d29552e..e901d860c3d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -8400,7 +8400,7 @@ mips_expand_ext_as_unaligned_load (rtx dest, rtx src, 
HOST_WIDE_INT width,
   /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
  be a DImode, create a new temp and emit a zero extend at the end.  */
   if (GET_MODE (dest) == DImode
-  && REG_P (dest)
+  && (REG_P (dest) || (SUBREG_P(dest) && !MEM_P(SUBREG_REG(dest
   && GET_MODE_BITSIZE (SImode) == width)
 {
   dest1 = dest;
-- 
2.20.1

[PATCH v3 2/2] ada: add 128bit operation to MIPS N32 and N64

[YunQiang Su]

For MIPS N64 and N32:
  add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS
  add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS

gcc/ada/ChangeLog:
PR ada/98996
* Makefile.rtl:  add 128Bit operation file to MIPS
N64 and N32 (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS).
---
 gcc/ada/ChangeLog|  6 ++
 gcc/ada/Makefile.rtl | 12 
 2 files changed, 18 insertions(+)

diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index 52faefaa2ae..fb09986bde0 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,9 @@
+2021-02-23  YunQiang Su  
+
+   PR ada/98996
+   * Makefile.rtl:  add 128Bit operation file to MIPS
+   N64 and N32 (LIBGNAT_TARGET_PAIRS, EXTRA_GNATRTL_NONTASKING_OBJS).
+
 2021-02-12  Arnaud Charlet  
 
* repinfo.ads, repinfo.adb (*SO_Ref*): Restore.
diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
index 35faf13ea46..987eff0abba 100644
--- a/gcc/ada/Makefile.rtl
+++ b/gcc/ada/Makefile.rtl
@@ -2311,6 +2311,18 @@ ifeq ($(strip $(filter-out mips% linux%,$(target_cpu) 
$(target_os))),)
   s-tpopsp.adb

[PATCH v4 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

[YunQiang Su]

It is found by ada s-pack96.adb ftbfs, due to 96bit load: 96 = 64 + 32.
While the 32bit pair of l r is mark as SUBREG, so they are
not in SImode, make it fail to find suitable insn.

gcc/ChangeLog:

PR target/98996
* config/mips/mips.c (mips_expand_ext_as_unaligned_load):
If TARGET_64BIT and dest is SUBREG, we check the width, if it
equal to SImode, we use SImode operation, just like what we are
doing for REG one.
---
 gcc/config/mips/mips.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8bd2d29552e..e901d860c3d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -8400,7 +8400,7 @@ mips_expand_ext_as_unaligned_load (rtx dest, rtx src, 
HOST_WIDE_INT width,
   /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
  be a DImode, create a new temp and emit a zero extend at the end.  */
   if (GET_MODE (dest) == DImode
-  && REG_P (dest)
+  && (REG_P (dest) || (SUBREG_P(dest) && !MEM_P(SUBREG_REG(dest
   && GET_MODE_BITSIZE (SImode) == width)
 {
   dest1 = dest;
-- 
2.20.1

[PATCH v4 2/2] ada: add 128bit operation for MIPS N32 and N64

[YunQiang Su]

For MIPS N64 and N32:
  add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS
  add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS

gcc/ada/ChangeLog:

PR ada/98996
* Makefile.rtl: 
add 128Bit operation file for MIPS N64 and N32 to
LIBGNAT_TARGET_PAIRS and EXTRA_GNATRTL_NONTASKING_OBJS
---
 gcc/ada/Makefile.rtl | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
index 35faf13ea46..987eff0abba 100644
--- a/gcc/ada/Makefile.rtl
+++ b/gcc/ada/Makefile.rtl
@@ -2311,6 +2311,18 @@ ifeq ($(strip $(filter-out mips% linux%,$(target_cpu) 
$(target_os))),)
   s-tpopsp.adb

[PATCH v4 1/2] MIPS: Not trigger error for pre-R6 and -mcompact-branches=always

[YunQiang Su]

For MIPSr6, we may wish to use compact-branches only.
Currently, we have to use `always' option, while it is mark as conflict
with pre-R6.
  cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always
Just ignore -mcompact-branches=always for pre-R6.

This patch also defines
__mips_compact_branches_never
__mips_compact_branches_always
__mips_compact_branches_optimal
predefined macros

gcc/ChangeLog:
* config/mips/mips.c (mips_option_override):
* config/mips/mips.h (TARGET_RTP_PIC): not trigger error for
compact-branches=always for pre-R6.
(TARGET_CB_NEVER): Likewise.
(TARGET_CB_ALWAYS): Likewise.
(struct mips_cpu_info): define macros for compact branch policy.
* doc/invoke.texi: Document "always" with pre-R6.

gcc/testsuite/ChangeLog:
* gcc.target/mips/compact-branches-1.c: add isa_rev>=6.
* gcc.target/mips/mips.exp: don't add -mipsXXr6 option for
-mcompact-branches=always. It is usable for pre-R6 now.
* gcc.target/mips/compact-branches-8.c: New test.
* gcc.target/mips/compact-branches-9.c: New test.
---
 gcc/config/mips/mips.c|  8 +--
 gcc/config/mips/mips.h| 22 ---
 gcc/doc/invoke.texi   |  1 +
 .../gcc.target/mips/compact-branches-1.c  |  2 +-
 .../gcc.target/mips/compact-branches-8.c  | 10 +
 .../gcc.target/mips/compact-branches-9.c  | 10 +
 gcc/testsuite/gcc.target/mips/mips.exp|  4 +---
 7 files changed, 38 insertions(+), 19 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-8.c
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-9.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8bd2d29552e..9a75dd61031 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -20107,13 +20107,7 @@ mips_option_override (void)
   target_flags |= MASK_ODD_SPREG;
 }
 
-  if (!ISA_HAS_COMPACT_BRANCHES && mips_cb == MIPS_CB_ALWAYS)
-{
-  error ("unsupported combination: %qs%s %s",
- mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
- "-mcompact-branches=always");
-}
-  else if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
+  if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
 {
   error ("unsupported combination: %qs%s %s",
  mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index b4a60a55d80..b8399fe1b0d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -103,11 +103,9 @@ struct mips_cpu_info {
 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
 
 /* Compact branches must not be used if the user either selects the
-   'never' policy or the 'optimal' policy on a core that lacks
+   'never' policy or the 'optimal' / 'always' policy on a core that lacks
compact branch instructions.  */
-#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER  \
-|| (mips_cb == MIPS_CB_OPTIMAL \
-&& !ISA_HAS_COMPACT_BRANCHES))
+#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER || !ISA_HAS_COMPACT_BRANCHES)
 
 /* Compact branches may be used if the user either selects the
'always' policy or the 'optimal' policy on a core that supports
@@ -117,10 +115,11 @@ struct mips_cpu_info {
 && ISA_HAS_COMPACT_BRANCHES))
 
 /* Compact branches must always be generated if the user selects
-   the 'always' policy or the 'optimal' policy om a core that
-   lacks delay slot branch instructions.  */
-#define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS\
-|| (mips_cb == MIPS_CB_OPTIMAL \
+   the 'always' policy on a core support compact branches,
+   or the 'optimal' policy on a core that lacks delay slot branch 
instructions.  */
+#define TARGET_CB_ALWAYS ((mips_cb == MIPS_CB_ALWAYS \
+&& ISA_HAS_COMPACT_BRANCHES) \
+|| (mips_cb == MIPS_CB_OPTIMAL   \
 && !ISA_HAS_DELAY_SLOTS))
 
 /* Special handling for JRC that exists in microMIPSR3 as well as R6
@@ -655,6 +654,13 @@ struct mips_cpu_info {
builtin_define ("__mips_no_lxc1_sxc1"); \
   if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4)  \
builtin_define ("__mips_no_madd4"); \
+   \
+  if (TARGET_CB_NEVER) \
+   builtin_define ("__mips_compact_branches_never");   \
+  else if (TARGET_CB_ALWAYS)   \
+   builtin_define ("__mips_compact_branches_always");  \
+  else \
+   builtin_define ("

[PATCH v4 2/2] MIPS: add builtime option for -mcompact-branches

[YunQiang Su]

For R6+ target, it allows to configure gcc to use compact branches only.

gcc/ChangeLog:
* config.gcc: add -with-compact-branches=policy build option.
* doc/install.texi: Likewise.
---
 gcc/config.gcc   | 12 +++-
 gcc/doc/install.texi | 19 +++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 17fea83b2e4..047f5631067 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4743,7 +4743,7 @@ case "${target}" in
;;
 
mips*-*-*)
-   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4"
+   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4 compact-branches"
 
case ${with_float} in
"" | soft | hard)
@@ -4896,6 +4896,16 @@ case "${target}" in
exit 1
;;
esac
+
+   case ${with_compact_branches} in
+   never | always | optimal)
+   with_compact_branches=${with_compact_branches}
+   ;;
+   *)
+   echo "Unknown compact-branches policy used in 
--with-compact-branches" 1>&2
+   exit 1
+   ;;
+   esac
;;
 
nds32*-*-*)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 4c38244ae58..865630826c6 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1464,6 +1464,25 @@ systems that support conditional traps).
 Division by zero checks use the break instruction.
 @end table
 
+@item --with-compact-branches=@var{policy}
+Specify how the compiler should generate code for checking for
+division by zero.  This option is only supported on the MIPS target.
+The possibilities for @var{type} are:
+@table @code
+@item optimal
+Cause a delay slot branch to be used if one is available in the
+current ISA and the delay slot is successfully filled. If the delay slot
+is not filled, a compact branch will be chosen if one is available.
+@item never
+Ensures that compact branch instructions will never be generated.
+@item always
+Ensures that a compact branch instruction will be generated if available.
+If a compact branch instruction is not available,
+a delay slot form of the branch will be used instead.
+This option is supported from MIPS Release 6 onwards.
+For pre-R6, this option is just same as never/optimal.
+@end table
+
 @c If you make --with-llsc the default for additional targets,
 @c update the --with-llsc description in the MIPS section below.
 
-- 
2.20.1

[PATCH] MIPS: R6: load/store can process unaligned address

[YunQiang Su]

MIPS release 6 requires the lw/ld/sw/sd can work with
unaligned address, while it can be implemented by
full hardware or trap&emulate.

Since it is may be fully done by hardware, we add an
option -m(no-)unaligned-access, the kernel may need it.

gcc/ChangeLog:

* config/mips/mips.h (ISA_HAS_UNALIGNED_ACCESS):
(STRICT_ALIGNMENT): R6 can unaligned access.
* config/mips/mips.md (movmisalign): Likewise.
* config/mips/mips.opt: add -m(no-)unaligned-access
* doc/invoke.texi: Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/mips/mips.exp: add unaligned-access
* gcc.target/mips/unaligned-2.c: New test.
* gcc.target/mips/unaligned-3.c: New test.
---
 gcc/config/mips/mips.h  |  6 ++-
 gcc/config/mips/mips.md | 10 
 gcc/config/mips/mips.opt|  4 ++
 gcc/doc/invoke.texi | 10 
 gcc/testsuite/gcc.target/mips/mips.exp  |  1 +
 gcc/testsuite/gcc.target/mips/unaligned-2.c | 53 +
 gcc/testsuite/gcc.target/mips/unaligned-3.c | 53 +
 7 files changed, 136 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/unaligned-2.c
 create mode 100644 gcc/testsuite/gcc.target/mips/unaligned-3.c

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index b4a60a55d80..38c39f79ee2 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -226,6 +226,10 @@ struct mips_cpu_info {
 && (mips_isa_rev >= 6 \
 || ISA_HAS_MSA))
 
+/* ISA load/store instructions can handle unaligned address */
+#define ISA_HAS_UNALIGNED_ACCESS (TARGET_UNALIGNED_ACCESS \
+&& (mips_isa_rev >= 6))
+
 /* The ISA compression flags that are currently in effect.  */
 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
 
@@ -1665,7 +1669,7 @@ FP_ASM_SPEC "\
   (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE)
 
 /* All accesses must be aligned.  */
-#define STRICT_ALIGNMENT 1
+#define STRICT_ALIGNMENT (!ISA_HAS_UNALIGNED_ACCESS)
 
 /* Define this if you wish to imitate the way many other C compilers
handle alignment of bitfields and the structures that contain
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index eef3cfd50a8..40e29c60432 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4459,6 +4459,16 @@ (define_insn "mov_r"
   [(set_attr "move_type" "store")
(set_attr "mode" "")])
 
+;; Unaligned direct access
+(define_expand "movmisalign"
+  [(set (match_operand:JOIN_MODE 0)
+   (match_operand:JOIN_MODE 1))]
+  "ISA_HAS_UNALIGNED_ACCESS"
+{
+  if (mips_legitimize_move (mode, operands[0], operands[1]))
+DONE;
+})
+
 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
 ;; The required value is:
 ;;
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 6af8037e9bd..ebb4c616401 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -404,6 +404,10 @@ mtune=
 Target RejectNegative Joined Var(mips_tune_option) ToLower 
Enum(mips_arch_opt_value)
 -mtune=PROCESSOR   Optimize the output for PROCESSOR.
 
+munaligned-access
+Target Var(TARGET_UNALIGNED_ACCESS) Init(1)
+Generate code with unaligned load store, valid for MIPS R6.
+
 muninit-const-in-rodata
 Target Var(TARGET_UNINIT_CONST_IN_RODATA)
 Put uninitialized constants in ROM (needs -membedded-data).
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 546e95453c1..27730d1a0de 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1059,6 +1059,7 @@ Objective-C and Objective-C++ Dialects}.
 -mcheck-zero-division  -mno-check-zero-division @gol
 -mdivide-traps  -mdivide-breaks @gol
 -mload-store-pairs  -mno-load-store-pairs @gol
+-munaligned-access  -mno-unaligned-access @gol
 -mmemcpy  -mno-memcpy  -mlong-calls  -mno-long-calls @gol
 -mmad  -mno-mad  -mimadd  -mno-imadd  -mfused-madd  -mno-fused-madd  -nocpp 
@gol
 -mfix-24k  -mno-fix-24k @gol
@@ -24967,6 +24968,15 @@ instructions to enable load/store bonding.  This 
option is enabled by
 default but only takes effect when the selected architecture is known
 to support bonding.
 
+@item -munaligned-access
+@itemx -mno-unaligned-access
+@opindex munaligned-access
+@opindex mno-unaligned-access
+Enable (disable) direct unaligned access for MIPS Release 6.
+MIPSr6 requires load/store unaligned-access support,
+by hardware or trap&emulate. 
+So @option{-mno-unaligned-access} may be needed by kernel.
+
 @item -mmemcpy
 @itemx -mno-memcpy
 @opindex mmemcpy
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp 
b/gcc/testsuite/gcc.target/mips/mips.exp
index 01292316944..cb1ee7d71b5 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -264,6 +264,7 @@ set mips_option_groups {
 frame-header "-mframe-header-opt|-mno-frame-header-opt"
 stack-pro

Re: [PATCH 2/3] MIPS: add builtime option for -mcompact-branches

[YunQiang Su]

Maciej W. Rozycki  于2021年3月4日周四 上午7:50写道：
>
> On Fri, 19 Feb 2021, YunQiang Su wrote:
>
> > >  My understanding therefore is that the original assumption that `optimal'
> > > will serve people best is no longer true.
> > >
> >
> > I guess that `optimal' can still produce the best performance, while
> > the delay slot
> > make MIPS quite differnent with other architectures.
> > And the hardware engineers seems hate it also.
>
>  Right, but what does it have to do with compiler defaults?  Given what we
> have available in hardware we want the best results possible, except for
> research or special use cases (such as GAS's `-minsn32' option with
> microMIPS code).  I would like to understand what the use case is here.
>

I want to give the hardware designer the possibility to remove the
delay slot branch
instructions in future (maybe in a long term).

> > And we expect that MIPS can have as few as possible differnece delta
> > with other major architectures,
> > to ultily all of new framworks of community.
>
>  Well, machine code is inherently architecture-specific, so you can't
> have a single template that fits all.  The difference betwen processor
> architectures is more than just the bit patterns for individual opcodes
> and operand encodings (and the corresponding mnemonics and syntax for
> the assembly language).
>

Delay slot makes some troubles for newly written binary tools.
Lots of people are not used to delay slot, and then they may not
consider MIPS in some new work.
We cannot expect to much the support from them, so we have to reduce the delta.

>  For example one of the major architectures is ARM, which has conditions
> encoded with all the instructions.  And you cant mimic it with other ISAs.
> Similarly Power has 8 sets of condition codes and dedicated instructions
> to make ALU operations between these codes.  You can't do those elsewhere
> either.  Well, the MIPS or RISC-V ISAs do not have condition codes at all.
> And x86 is not a load-store architecture at all, so you'll see operations
> made directly on memory, as a destination even (let's ignore the even more
> arcane original 32-bit instruction set).
>
>  These are all considered major architectures nowadays.

Yes. "nowadays".
How about the future?
Since the MIPS is the only architecture which has delay slot, will it
be ”no-major“?

>
>  So we have got the MIPS ISA and its delay slots.  Some subsets/variations
> of the ISA have already either greatly reduced their use or eliminated
> them completely, but we went into great lengths with GCC to produce good
> code making use of these delay slots, so I think it would be a shame to

Yes. There will not be a  problem for GCC itself, while there are more and more
other tools, open source or commercial.
Since MIPS is not the de-facto majority, it is not so easy to ask them
to support MIPS.

> get this effort wasted on one hand, and MIPS code put at a disadvantage
> due to cycles wasted for pipeline stalls that could be avoided if delay
> slots were scheduled -- on the other.
>

I have some tests on I6500. The performance of delay-branch and compact-branch
are almost the same. It will not be a performance regression.

> > >  First, I think it would be good if we knew why.  I find proliferating
> > > variants of defaults, especially for the less obvious cases, will cause
> > > user confusion as one won't know what code model to expect, especially as
> > > (please correct me if I am wrong) we don't actually provide a way to dump
> > > the compiler's overridable configuration defaults.
> > >
> >
> > So, should we provide a predefined macro for it?
>
>  I've been thinking more along `gcc -v --version' dumping the invocation
> of `configure' used, but I have to correct myself here in that it already
> happens, so nothing to do.  I'm not sure why I forgot it and/or could not
> have figured it out previously.  Sorry about the confusion.
>

nop.

> > >  Second, I wonder if it makes sense to just keep things simple, and rather
> > > than adding `prefer' (to stand for "`always' if available"), and possibly
> > > `avoid' (to stand for "`never' if available"), whether we shouldn't just
> > > relax the checks for `always' and `never', and let them through whether
> > > the architecture selected provides for the option chosen or not.
> > >
> >
> > relax the `always' is what I would like to do first.
> > But I was afread to break some complatiable.
>
>  Hmm, honestly I don't think there could be any compatibility to ca

[PATCH] MIPS: use N64 ABI by default if the triple end with -gnuabi64

[YunQiang Su]

gcc/ChangeLog:

PR target/102089
* config.gcc: MIPS: use N64 ABI by default if the triple end
  with -gnuabi64, which is used by Debian since 2013.
---
 gcc/config.gcc | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 0ff5cac15..0c91be6f3 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2553,16 +2553,30 @@ mips*-*-linux*) # Linux MIPS, 
either endian.
target_cpu_default=MASK_SOFT_FLOAT_ABI
enable_mips_multilibs="yes"
;;
+   mipsisa64r6*-*-linux-gnuabi64)
+   default_mips_abi=64
+   default_mips_arch=mips64r6
+   enable_mips_multilibs="yes"
+   ;;
mipsisa64r6*-*-linux*)
default_mips_abi=n32
default_mips_arch=mips64r6
enable_mips_multilibs="yes"
;;
+   mipsisa64r2*-*-linux-gnuabi64)
+   default_mips_abi=64
+   default_mips_arch=mips64r2
+   enable_mips_multilibs="yes"
+   ;;
mipsisa64r2*-*-linux*)
default_mips_abi=n32
default_mips_arch=mips64r2
enable_mips_multilibs="yes"
;;
+   mips64*-*-linux-gnuabi64 | mipsisa64*-*-linux-gnuabi64)
+   default_mips_abi=64
+   enable_mips_multilibs="yes"
+   ;;
mips64*-*-linux* | mipsisa64*-*-linux*)
default_mips_abi=n32
enable_mips_multilibs="yes"
-- 
2.30.2

[PATCH] libffi: Fix MIPS r6 support

[YunQiang Su]

for some instructions, MIPS r6 uses different encoding other than
the previous releases.

1. mips/n32.S disable .set mips4: since it casuses old insn encoding
   is used.
   https://github.com/libffi/libffi/pull/396
2. mips/ffi.c: the encoding for JR is hardcoded: we need to use
   different value for r6 and pre-r6.
   https://github.com/libffi/libffi/pull/401

libffi/
PR libffi/83636
* src/mips/n32.S: disable .set mips4
* src/mips/ffi.c: use different JR encoding for r6.
---
 libffi/src/mips/ffi.c | 8 
 libffi/src/mips/n32.S | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/libffi/src/mips/ffi.c b/libffi/src/mips/ffi.c
index 5d0dd70cb..ecd783a56 100644
--- a/libffi/src/mips/ffi.c
+++ b/libffi/src/mips/ffi.c
@@ -698,7 +698,11 @@ ffi_prep_closure_loc (ffi_closure *closure,
   /* lui  $12,high(codeloc) */
   tramp[2] = 0x3c0c | ((unsigned)codeloc >> 16);
   /* jr   $25  */
+#if !defined(__mips_isa_rev) || (__mips_isa_rev<6)
   tramp[3] = 0x0328;
+#else
+  tramp[3] = 0x0329;
+#endif
   /* ori  $12,low(codeloc)  */
   tramp[4] = 0x358c | ((unsigned)codeloc & 0x);
 #else
@@ -726,7 +730,11 @@ ffi_prep_closure_loc (ffi_closure *closure,
   /* ori  $25,low(fn)  */
   tramp[10] = 0x3739 | ((unsigned long)fn  & 0x);
   /* jr   $25  */
+#if !defined(__mips_isa_rev) || (__mips_isa_rev<6)
   tramp[11] = 0x0328;
+#else
+  tramp[11] = 0x0329;
+#endif
   /* ori  $12,low(codeloc)  */
   tramp[12] = 0x358c | ((unsigned long)codeloc & 0x);
 
diff --git a/libffi/src/mips/n32.S b/libffi/src/mips/n32.S
index c6985d30a..06e6c4607 100644
--- a/libffi/src/mips/n32.S
+++ b/libffi/src/mips/n32.S
@@ -43,7 +43,9 @@
 #ifdef __GNUC__
.abicalls
 #endif
+#if !defined(__mips_isa_rev) || (__mips_isa_rev<6)
.set mips4
+#endif
.text
.align  2
.globl  ffi_call_N32
-- 
2.30.2

Re: [PATCH v2] [MIPS]: add .module mipsREV to all output asm file

[YunQiang Su]

在 2021/6/18 11:29, YunQiang Su 写道:

Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:
   assembler is mips1 by default,
   gcc is fpxx by default.
To assemble the output of gcc -S, we have to pass -mips2
to assembler.

gcc/ChangeLog:

 * gcc/config/mips/mips.c (mips_module_isa_name): New.
 mips_file_start: add .module mipsREV to all asm output


ping for this patch.


---
  gcc/config/mips/mips.c | 37 +
  1 file changed, 37 insertions(+)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 1f1475cf400..51cc70e6ceb 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9877,6 +9877,40 @@ mips_mdebug_abi_name (void)
  }
  }
  
+static const char *

+mips_module_isa_name()
+{
+  if (ISA_MIPS1)
+return "mips1";
+  else if (ISA_MIPS2)
+return "mips2";
+  else if (ISA_MIPS3)
+return "mips3";
+  else if (ISA_MIPS4)
+return "mips4";
+  else if (ISA_MIPS32)
+return "mips32";
+  else if (ISA_MIPS32R2)
+return "mips32r2";
+  else if (ISA_MIPS32R3)
+return "mips32r3";
+  else if (ISA_MIPS32R5)
+return "mips32r5";
+  else if (ISA_MIPS32R6)
+return "mips32r6";
+  else if (ISA_MIPS64)
+return "mips64";
+  else if (ISA_MIPS64R2)
+return "mips64r2";
+  else if (ISA_MIPS64R3)
+return "mips64r3";
+  else if (ISA_MIPS64R5)
+return "mips64r5";
+  else if (ISA_MIPS64R6)
+return "mips64r6";
+  gcc_unreachable ();
+}
+
  /* Implement TARGET_ASM_FILE_START.  */
  
  static void

@@ -9908,6 +9942,9 @@ mips_file_start (void)
  fprintf (asm_out_file, "\t.nan\t%s\n",
 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
  
+  fprintf (asm_out_file, "\t.module\t%s\n",

+  mips_module_isa_name ());
+
  #ifdef HAVE_AS_DOT_MODULE
/* Record the FP ABI.  See below for comments.  */
if (TARGET_NO_FLOAT)

[PATCH v3] MIPS: add .module mipsREV to all output asm file

[YunQiang Su]

Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:
  assembler is mips1 by default,
  gcc is fpxx by default.
To assemble the output of gcc -S, we have to pass -mips2
to assembler.

gcc/ChangeLog:

* gcc/config/mips/mips.c (mips_module_isa_name): New.
mips_file_start: add .module mipsREV to all asm output
---
 gcc/config/mips/mips.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 2f7ffe846..47c149eac 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9841,6 +9841,32 @@ mips_mdebug_abi_name (void)
 }
 }
 
+static const char *
+mips_module_isa_name ()
+{
+  switch (mips_isa)
+{
+case 1:return "mips1";
+case 2:return "mips2";
+case 3:return "mips3";
+case 4:return "mips4";
+case 32:   return "mips32";
+case 33:   return "mips32r2";
+case 34:   return "mips32r3";
+/* 35:r4 is skipped */
+case 36:   return "mips32r5";
+case 37:   return "mips32r6";
+case 64:   return "mips64";
+case 65:   return "mips64r2";
+case 66:   return "mips64r3";
+case 67:   return "mips64r5";
+/* 68:r4 is skipped */
+case 69:   return "mips64r6";
+default:
+  gcc_unreachable ();
+}
+}
+
 /* Implement TARGET_ASM_FILE_START.  */
 
 static void
@@ -9872,6 +9898,9 @@ mips_file_start (void)
 fprintf (asm_out_file, "\t.nan\t%s\n",
 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
 
+  fprintf (asm_out_file, "\t.module\t%s\n",
+  mips_module_isa_name ());
+
 #ifdef HAVE_AS_DOT_MODULE
   /* Record the FP ABI.  See below for comments.  */
   if (TARGET_NO_FLOAT)
-- 
2.30.2

Re: [PATCH v2] [MIPS]: add .module mipsREV to all output asm file

[YunQiang Su]

Xi Ruoyao via Gcc-patches  于2021年8月28日周六 下午3:09写道：
>
> On Fri, 2021-08-27 at 15:36 -0600, Jeff Law wrote:
>
> > It's easier when someone has to debug the code later.
> > enums show up in debug output by default, while #defines do not.
>
> > >
> > > switch (mips_isa)
> > >{
> > >  case MIPS_ISA_MIPS1: return "mips1";
> > >  // ...
> > >}
> > >
> > > It looks better, and (maybe) generates better code.  Just my 2 cents
> > > though.
>
> > Coding standards would have that as
> >
> > switch (mips_isa)
> >{
> >case MIPS_ISA_MIPS_1:
> >  return "mips1";
> >...
> >}
>
> There is some existing code using "case ... : return ..." in one line in
> mips.c, so I thought it was standard :(.
>
> > Presumably .module is supported by all reasonably modern versions of
> > GAS?
>
> It's added by the commit in binutils-gdb:
>
> > commit 919731affbef19fcad8dddb0a595bb05755cb345
> > Author: mfortune 
> > Date:   Tue May 20 13:28:20 2014 +0100
> >
> > Add MIPS .module directive
> >
>
> So it should be supported since binutils-2.25.
>
> If we want to support old binutils we'll need something like "-fno-mips-
> module-directive" and "--without-mips-module-directive".  My suggestion
> is just bumping the binutils requirement for mips*-*-*.
>

There is a macro, HAVE_AS_DOT_MODULE, so that we can just use it.

#ifdef HAVE_AS_DOT_MODULE
  /* Record the FP ABI.  See below for comments.  */
  if (TARGET_NO_FLOAT)
#ifdef HAVE_AS_GNU_ATTRIBUTE
fputs ("\t.gnu_attribute 4, 0\n", asm_out_file);
#else
;
#endif
  else if (!TARGET_HARD_FLOAT_ABI)
fputs ("\t.module\tsoftfloat\n", asm_out_file);
  else if (!TARGET_DOUBLE_FLOAT)
fputs ("\t.module\tsinglefloat\n", asm_out_file);
  else if (TARGET_FLOATXX)
fputs ("\t.module\tfp=xx\n", asm_out_file);
  else if (TARGET_FLOAT64)
fputs ("\t.module\tfp=64\n", asm_out_file);
  else
fputs ("\t.module\tfp=32\n", asm_out_file);

  if (TARGET_ODD_SPREG)
fputs ("\t.module\toddspreg\n", asm_out_file);
  else
fputs ("\t.module\tnooddspreg\n", asm_out_file);

#else

Thank you for your help.
>

[PATCH 1/3] md/define_c_enum: support value assignation

[YunQiang Su]

Currently, the enums from define_c_enum and define_enum can only
has values one by one from 0.

In fact we can support the behaviour just like C, aka like
  (define_enum "mips_isa" [mips1=1 mips2 mips32=32 mips32r2]),
then we can get
  enum mips_isa {
MIPS_ISA_MIPS1 = 1,
MIPS_ISA_MIPS2 = 2,
MIPS_ISA_MIPS32 = 32,
MIPS_ISA_MIPS32R2 = 33
  };

gcc/ChangeLog:
* read-md.c (md_reader::handle_enum): support value assignation.
* doc/md.texi: record define_c_enum value assignation support.
---
 gcc/doc/md.texi |  4 
 gcc/read-md.c   | 15 +--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index f8047aefc..1c1282c4c 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -11074,6 +11074,8 @@ The syntax is as follows:
 (define_c_enum "@var{name}" [
   @var{value0}
   @var{value1}
+  @var{value32}=32
+  @var{value33}
   @dots{}
   @var{valuen}
 ])
@@ -11086,6 +11088,8 @@ in @file{insn-constants.h}:
 enum @var{name} @{
   @var{value0} = 0,
   @var{value1} = 1,
+  @var{value32} = 32,
+  @var{value33} = 33,
   @dots{}
   @var{valuen} = @var{n}
 @};
diff --git a/gcc/read-md.c b/gcc/read-md.c
index bb419e0f6..43dfbe264 100644
--- a/gcc/read-md.c
+++ b/gcc/read-md.c
@@ -901,7 +901,8 @@ md_decimal_string (int number)
 void
 md_reader::handle_enum (file_location loc, bool md_p)
 {
-  char *enum_name, *value_name;
+  char *enum_name, *value_name, *token;
+  unsigned int cur_value;
   struct md_name name;
   struct enum_type *def;
   struct enum_value *ev;
@@ -928,6 +929,7 @@ md_reader::handle_enum (file_location loc, bool md_p)
   *slot = def;
 }
 
+  cur_value = def->num_values;
   require_char_ws ('[');
 
   while ((c = read_skip_spaces ()) != ']')
@@ -945,20 +947,29 @@ md_reader::handle_enum (file_location loc, bool md_p)
   if (md_p)
{
  value_name = concat (def->name, "_", name.string, NULL);
+ value_name = strtok (value_name, "=");
+ token = strtok (NULL, "=");
+ if (token)
+   cur_value = atoi (token);
  upcase_string (value_name);
  ev->name = xstrdup (name.string);
}
   else
{
  value_name = xstrdup (name.string);
+ value_name = strtok (value_name, "=");
+ token = strtok (NULL, "=");
+ if (token)
+   cur_value = atoi (token);
  ev->name = value_name;
}
   ev->def = add_constant (get_md_constants (), value_name,
- md_decimal_string (def->num_values), def);
+ md_decimal_string (cur_value), def);
 
   *def->tail_ptr = ev;
   def->tail_ptr = &ev->next;
   def->num_values++;
+  cur_value++;
 }
 }
 
-- 
2.30.2

[PATCH 2/3] MIPS: use mips_isa enum instead hardcoded numbers

[YunQiang Su]

Currently mips-cpu.defs and mips.h are using hardcoded numbers
for isa level.

Let's replace them with more readable enum mips_isa.

gcc/ChangeLog:
* config/mips/mips.md: define_enum "mips_isa".
* config/mips/mips.h (struct mips_cpu_info): use enum
  instead of int for 'isa' member.
* config/mips/mips{.h,-cpus.def}: replace hardcoded
  numbers with enum.
---
 gcc/config/mips/mips-cpus.def | 228 +-
 gcc/config/mips/mips.h|  50 
 gcc/config/mips/mips.md   |  17 +++
 3 files changed, 156 insertions(+), 139 deletions(-)

diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
index b02294be4..45fb6bc8b 100644
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -33,146 +33,146 @@ along with GCC; see the file COPYING3.  If not see
where the arguments are the fields of struct mips_cpu_info.  */
 
 /* Entries for generic ISAs.  */
-MIPS_CPU ("mips1", PROCESSOR_R3000, 1, 0)
-MIPS_CPU ("mips2", PROCESSOR_R6000, 2, PTF_AVOID_BRANCHLIKELY_SIZE)
-MIPS_CPU ("mips3", PROCESSOR_R4000, 3, PTF_AVOID_BRANCHLIKELY_SIZE)
-MIPS_CPU ("mips4", PROCESSOR_R1, 4, PTF_AVOID_BRANCHLIKELY_SIZE)
+MIPS_CPU ("mips1", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
+MIPS_CPU ("mips2", PROCESSOR_R6000, MIPS_ISA_MIPS2, 
PTF_AVOID_BRANCHLIKELY_SIZE)
+MIPS_CPU ("mips3", PROCESSOR_R4000, MIPS_ISA_MIPS3, 
PTF_AVOID_BRANCHLIKELY_SIZE)
+MIPS_CPU ("mips4", PROCESSOR_R1, MIPS_ISA_MIPS4, 
PTF_AVOID_BRANCHLIKELY_SIZE)
 /* Prefer not to use branch-likely instructions for generic MIPS32rX
and MIPS64rX code.  The instructions were officially deprecated
in revisions 2 and earlier, but revision 3 is likely to downgrade
that to a recommendation to avoid the instructions in code that
isn't tuned to a specific processor.  */
-MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY_ALWAYS)
-MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33, PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips32", PROCESSOR_4KC, MIPS_ISA_MIPS32, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
 /* mips32r3 is micromips hense why it uses the M4K processor.  */
-MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY_ALWAYS)
-MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY_ALWAYS)
-MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, 0)
-MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips32r3", PROCESSOR_M4K, MIPS_ISA_MIPS32R3, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips32r5", PROCESSOR_P5600, MIPS_ISA_MIPS32R5, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips32r6", PROCESSOR_I6400, MIPS_ISA_MIPS32R6, 0)
+MIPS_CPU ("mips64", PROCESSOR_5KC, MIPS_ISA_MIPS64, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
 /* ??? For now just tune the generic MIPS64r2 and above for 5KC as well.   */
-MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY_ALWAYS)
-MIPS_CPU ("mips64r3", PROCESSOR_5KC, 66, PTF_AVOID_BRANCHLIKELY_ALWAYS)
-MIPS_CPU ("mips64r5", PROCESSOR_5KC, 68, PTF_AVOID_BRANCHLIKELY_ALWAYS)
-MIPS_CPU ("mips64r6", PROCESSOR_I6400, 69, 0)
+MIPS_CPU ("mips64r2", PROCESSOR_5KC, MIPS_ISA_MIPS64R2, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips64r3", PROCESSOR_5KC, MIPS_ISA_MIPS64R3, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips64r5", PROCESSOR_5KC, MIPS_ISA_MIPS64R5, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips64r6", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0)
 
 /* MIPS I processors.  */
-MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
-MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
-MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
+MIPS_CPU ("r3000", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
+MIPS_CPU ("r2000", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
+MIPS_CPU ("r3900", PROCESSOR_R3900, MIPS_ISA_MIPS1, 0)
 
 /* MIPS II processors.  */
-MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
+MIPS_CPU ("r6000", PROCESSOR_R6000, MIPS_ISA_MIPS2, 0)
 
 /* MIPS III processors.  */
-MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
-MIPS_CPU ("vr4100", PROCESSOR_R4100, 3, 0)
-MIPS_CPU ("vr4111", PROCESSOR_R4111, 3, 0)
-MIPS_CPU ("vr4120", PROCESSOR_R4120, 3, 0)
-MIPS_CPU ("vr4130", PROCESSOR_R4130, 3, 0)
-MIPS_CPU ("vr4300", PROCESSOR_R4300, 3, 0)
-MIPS_CPU ("r4400", PROCESSOR_R4000, 3, 0)
-MIPS_CPU ("r4600", PROCESSOR_R4600, 3, 0)
-MIPS_CPU ("orion", PROCESSOR_R4600, 3, 0)
-MIPS_CPU ("r4650", PROCESSOR_R4650, 3, 0)
-MIPS_CPU ("r4700", PROCESSOR_R4700, 3, 0)
-MIPS_CPU ("r5900", PROCESSOR_R5900, 3, 0)
+MIPS_CPU ("r4000", PROCESSOR_R4000, MIPS_ISA_MIPS3, 0)
+MIPS_CPU ("vr4100", PROCESSOR_R4100, MIPS_ISA_MIPS3, 0)
+MIPS_CPU ("vr4111", PROCESSOR_R4111, MIPS_ISA_MIPS3, 0)
+MIPS_CPU ("vr4120", PROCESSOR_R4120, MIPS_ISA_MIPS3, 0)
+MIPS_CPU ("vr4130", PROCESSOR_R4130, MIPS_ISA_MIPS3, 0)
+MIPS_CPU ("vr4300", PROCESSOR_R4300, MIPS_ISA_MIPS3, 0)
+MIPS_CPU ("r4400", PROCESSOR_R4000, MIPS_ISA_MIPS3, 0)
+MIPS_CPU ("r4600", PROCESSOR_R4600, MIPS_ISA_MIPS3, 0)
+MIPS_CPU ("orion", PROCESSO

[PATCH 3/3] MIPS: add .module mipsREV to all output asm file

[YunQiang Su]

Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:
  assembler is mips1 by default,
  gcc is fpxx by default.
To assemble the output of gcc -S, we have to pass -mips2
to assembler.

gcc/ChangeLog:

* gcc/config/mips/mips.c (mips_module_isa_name): New.
mips_file_start: add .module mipsREV to all asm output
---
 gcc/config/mips/mips.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 2f7ffe846..b344cf3fc 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9841,6 +9841,44 @@ mips_mdebug_abi_name (void)
 }
 }
 
+static const char *
+mips_module_isa_name ()
+{
+  switch (mips_isa)
+{
+case MIPS_ISA_MIPS1:
+  return "mips1";
+case MIPS_ISA_MIPS2:
+  return "mips2";
+case MIPS_ISA_MIPS3:
+  return "mips3";
+case MIPS_ISA_MIPS4:
+  return "mips4";
+case MIPS_ISA_MIPS32:
+  return "mips32";
+case MIPS_ISA_MIPS32R2:
+  return "mips32r2";
+case MIPS_ISA_MIPS32R3:
+  return "mips32r3";
+case MIPS_ISA_MIPS32R5:
+  return "mips32r5";
+case MIPS_ISA_MIPS32R6:
+  return "mips32r6";
+case MIPS_ISA_MIPS64:
+  return "mips64";
+case MIPS_ISA_MIPS64R2:
+  return "mips64r2";
+case MIPS_ISA_MIPS64R3:
+  return "mips64r3";
+case MIPS_ISA_MIPS64R5:
+  return "mips64r5";
+case MIPS_ISA_MIPS64R6:
+  return "mips64r6";
+default:
+  gcc_unreachable ();
+}
+}
+
 /* Implement TARGET_ASM_FILE_START.  */
 
 static void
@@ -9873,6 +9911,9 @@ mips_file_start (void)
 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
 
 #ifdef HAVE_AS_DOT_MODULE
+  fprintf (asm_out_file, "\t.module\t%s\n",
+  mips_module_isa_name ());
+
   /* Record the FP ABI.  See below for comments.  */
   if (TARGET_NO_FLOAT)
 #ifdef HAVE_AS_GNU_ATTRIBUTE
-- 
2.30.2

Re: [PATCH] libffi: Fix MIPS r6 support

[YunQiang Su]

Xi Ruoyao via Gcc-patches  于2021年8月28日周六 下午3:25写道：
>
> On Fri, 2021-08-27 at 15:28 -0600, Jeff Law via Gcc-patches wrote:
> >
> >
> > On 8/26/2021 10:58 PM, YunQiang Su wrote:
> > > for some instructions, MIPS r6 uses different encoding other than
> > > the previous releases.
> > >
> > > 1. mips/n32.S disable .set mips4: since it casuses old insn encoding
> > > is used.
> > > https://github.com/libffi/libffi/pull/396
> > > 2. mips/ffi.c: the encoding for JR is hardcoded: we need to use
> > > different value for r6 and pre-r6.
> > > https://github.com/libffi/libffi/pull/401
> > >
> > > libffi/
> > > PR libffi/83636
> > > * src/mips/n32.S: disable .set mips4
> > > * src/mips/ffi.c: use different JR encoding for r6.
> > These should go to the upstream libffi project.  Once accepted there
> > you
> > can add them to GCC.
>
> Hi Jeff,
>
> The two PRs are already merged, and released since libffi-3.3.0 (now the
> upstream latest release is 3.4.2).
>
> I don't have a MIPSr6 so I can't test though.
>

We do have a qemu tarball. Please see:
Debian: http://58.246.137.130:20180/README.txt
Arch: http://58.246.137.130:20180/archlinux/dist/

> YunQiang: the commit message should mention the commit SHA in upstream
> libffi repo's main branch, instead of a URL to PR.  You can use "git
> log" in gcc repo and search for commits for libffi and learn from it.
> --
> Xi Ruoyao 
> School of Aerospace Science and Technology, Xidian University
>

[PATCH v2] libffi: Fix MIPS r6 support

[YunQiang Su]

for some instructions, MIPS r6 uses different encoding other than
the previous releases.

1. mips/n32.S disable .set mips4: since it casuses old insn encoding
   is used.
   https://github.com/libffi/libffi/pull/396 has been accepted as:
 94c102aa69b04337f63498e0e6551fcdce549ae5
2. mips/ffi.c: the encoding for JR is hardcoded: we need to use
   different value for r6 and pre-r6.
   https://github.com/libffi/libffi/pull/401 has been accpeted as:
 746dbe3a6a79a41931c03b51df2972be4d5e5028

libffi/
PR libffi/83636
* src/mips/n32.S: disable .set mips4
* src/mips/ffi.c: use different JR encoding for r6.
---
 libffi/src/mips/ffi.c | 8 
 libffi/src/mips/n32.S | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/libffi/src/mips/ffi.c b/libffi/src/mips/ffi.c
index 5d0dd70cb..ecd783a56 100644
--- a/libffi/src/mips/ffi.c
+++ b/libffi/src/mips/ffi.c
@@ -698,7 +698,11 @@ ffi_prep_closure_loc (ffi_closure *closure,
   /* lui  $12,high(codeloc) */
   tramp[2] = 0x3c0c | ((unsigned)codeloc >> 16);
   /* jr   $25  */
+#if !defined(__mips_isa_rev) || (__mips_isa_rev<6)
   tramp[3] = 0x0328;
+#else
+  tramp[3] = 0x0329;
+#endif
   /* ori  $12,low(codeloc)  */
   tramp[4] = 0x358c | ((unsigned)codeloc & 0x);
 #else
@@ -726,7 +730,11 @@ ffi_prep_closure_loc (ffi_closure *closure,
   /* ori  $25,low(fn)  */
   tramp[10] = 0x3739 | ((unsigned long)fn  & 0x);
   /* jr   $25  */
+#if !defined(__mips_isa_rev) || (__mips_isa_rev<6)
   tramp[11] = 0x0328;
+#else
+  tramp[11] = 0x0329;
+#endif
   /* ori  $12,low(codeloc)  */
   tramp[12] = 0x358c | ((unsigned long)codeloc & 0x);
 
diff --git a/libffi/src/mips/n32.S b/libffi/src/mips/n32.S
index c6985d30a..06e6c4607 100644
--- a/libffi/src/mips/n32.S
+++ b/libffi/src/mips/n32.S
@@ -43,7 +43,9 @@
 #ifdef __GNUC__
.abicalls
 #endif
+#if !defined(__mips_isa_rev) || (__mips_isa_rev<6)
.set mips4
+#endif
.text
.align  2
.globl  ffi_call_N32
-- 
2.30.2

Re: [PATCH 2/3] MIPS: use mips_isa enum instead hardcoded numbers

[YunQiang Su]

Xi Ruoyao  于2021年8月29日周日 下午1:54写道：
>
> On Sat, 2021-08-28 at 08:05 -0400, YunQiang Su wrote:
> > Currently mips-cpu.defs and mips.h are using hardcoded numbers
> > for isa level.
> >
> > Let's replace them with more readable enum mips_isa.
>
> Good, but there is something like "mips_isa_rev >= 32 && mips_isa_rev <
> 64" in mips.h and netbsd.h.  Not sure if they should be replaced
> altogether.
>

Yes. It is my fault. I missed them.
And we also need to replace the similar lines in config.gcc.

> If they are replaced as well, it will be not necessary to set special
> enum values.
>

no. mips_isa is a predefined macro exposed to C programmer.
Some existing code may depend on this behavior.

syq@XXX:~$ gcc -mabi=32 -mips64 -dM -E - < /dev/null | grep '__mips '
#define __mips 64
syq@XXX:~$ gcc -mabi=32 -mips3 -dM -E - < /dev/null | grep '__mips '
#define __mips 3
syq@XXX:~$ gcc -mabi=32 -mips32 -dM -E - < /dev/null | grep '__mips '
#define __mips 32

And codesearch give us some examples:
http://codesearch.debian.net/search?q=__mips+%3E&literal=1

> How do the others think?
>
> > gcc/ChangeLog:
> > * config/mips/mips.md: define_enum "mips_isa".
> > * config/mips/mips.h (struct mips_cpu_info): use enum
> >   instead of int for 'isa' member.
> > * config/mips/mips{.h,-cpus.def}: replace hardcoded
> >   numbers with enum.
> > ---
> >  gcc/config/mips/mips-cpus.def | 228 +
> > -
> >  gcc/config/mips/mips.h|  50 
> >  gcc/config/mips/mips.md   |  17 +++
> >  3 files changed, 156 insertions(+), 139 deletions(-)
> >
> > diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-
> > cpus.def
> > index b02294be4..45fb6bc8b 100644
> > --- a/gcc/config/mips/mips-cpus.def
> > +++ b/gcc/config/mips/mips-cpus.def
> > @@ -33,146 +33,146 @@ along with GCC; see the file COPYING3.  If not
> > see
> > where the arguments are the fields of struct mips_cpu_info.  */
> >
> >  /* Entries for generic ISAs.  */
> > -MIPS_CPU ("mips1", PROCESSOR_R3000, 1, 0)
> > -MIPS_CPU ("mips2", PROCESSOR_R6000, 2, PTF_AVOID_BRANCHLIKELY_SIZE)
> > -MIPS_CPU ("mips3", PROCESSOR_R4000, 3, PTF_AVOID_BRANCHLIKELY_SIZE)
> > -MIPS_CPU ("mips4", PROCESSOR_R1, 4, PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips1", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
> > +MIPS_CPU ("mips2", PROCESSOR_R6000, MIPS_ISA_MIPS2,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips3", PROCESSOR_R4000, MIPS_ISA_MIPS3,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips4", PROCESSOR_R1, MIPS_ISA_MIPS4,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> >  /* Prefer not to use branch-likely instructions for generic MIPS32rX
> > and MIPS64rX code.  The instructions were officially deprecated
> > in revisions 2 and earlier, but revision 3 is likely to downgrade
> > that to a recommendation to avoid the instructions in code that
> > isn't tuned to a specific processor.  */
> > -MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32", PROCESSOR_4KC, MIPS_ISA_MIPS32,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> >  /* mips32r3 is micromips hense why it uses the M4K processor.  */
> > -MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, 0)
> > -MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r3", PROCESSOR_M4K, MIPS_ISA_MIPS32R3,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r5", PROCESSOR_P5600, MIPS_ISA_MIPS32R5,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r6", PROCESSOR_I6400, MIPS_ISA_MIPS32R6, 0)
> > +MIPS_CPU ("mips64", PROCESSOR_5KC, MIPS_ISA_MIPS64,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> >  /* ??? For now just tune the generic MIPS64r2 and above for 5KC as
> > well.   */
> > -MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips64r3", PROCESS

[PATCH v2] MIPS: add .module mipsREV to all output asm file

[YunQiang Su]

Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:
  assembler is mips1 by default,
  gcc is fpxx by default.
To assemble the output of gcc -S, we have to pass -mips2
to assembler.

gcc/ChangeLog:

* gcc/config/mips/mips.c (mips_module_isa_name): New.
mips_file_start: add .module mipsREV to all asm output
---
 gcc/config/mips/mips.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 493d3de48..a7087ec0a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9841,6 +9841,44 @@ mips_mdebug_abi_name (void)
 }
 }
 
+static const char *
+mips_module_isa_name ()
+{
+  switch (mips_isa)
+{
+case MIPS_ISA_MIPS1:
+  return "mips1";
+case MIPS_ISA_MIPS2:
+  return "mips2";
+case MIPS_ISA_MIPS3:
+  return "mips3";
+case MIPS_ISA_MIPS4:
+  return "mips4";
+case MIPS_ISA_MIPS32:
+  return "mips32";
+case MIPS_ISA_MIPS32R2:
+  return "mips32r2";
+case MIPS_ISA_MIPS32R3:
+  return "mips32r3";
+case MIPS_ISA_MIPS32R5:
+  return "mips32r5";
+case MIPS_ISA_MIPS32R6:
+  return "mips32r6";
+case MIPS_ISA_MIPS64:
+  return "mips64";
+case MIPS_ISA_MIPS64R2:
+  return "mips64r2";
+case MIPS_ISA_MIPS64R3:
+  return "mips64r3";
+case MIPS_ISA_MIPS64R5:
+  return "mips64r5";
+case MIPS_ISA_MIPS64R6:
+  return "mips64r6";
+default:
+  gcc_unreachable ();
+}
+}
+
 /* Implement TARGET_ASM_FILE_START.  */
 
 static void
@@ -9873,6 +9911,9 @@ mips_file_start (void)
 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
 
 #ifdef HAVE_AS_DOT_MODULE
+  fprintf (asm_out_file, "\t.module\t%s\n",
+  mips_module_isa_name ());
+
   /* Record the FP ABI.  See below for comments.  */
   if (TARGET_NO_FLOAT)
 #ifdef HAVE_AS_GNU_ATTRIBUTE
-- 
2.30.2

Re: [PATCH v2] MIPS: add .module mipsREV to all output asm file

[YunQiang Su]

Please ignore this post, as I mistakenly used -1 instead of -2.

YunQiang Su  于2021年8月30日周一 上午10:57写道：
>
> Currently, the asm output file for MIPS has no rev info.
> It can make some trouble, for example:
>   assembler is mips1 by default,
>   gcc is fpxx by default.
> To assemble the output of gcc -S, we have to pass -mips2
> to assembler.
>
> gcc/ChangeLog:
>
> * gcc/config/mips/mips.c (mips_module_isa_name): New.
> mips_file_start: add .module mipsREV to all asm output
> ---
>  gcc/config/mips/mips.c | 41 +
>  1 file changed, 41 insertions(+)
>
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index 493d3de48..a7087ec0a 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -9841,6 +9841,44 @@ mips_mdebug_abi_name (void)
>  }
>  }
>
> +static const char *
> +mips_module_isa_name ()
> +{
> +  switch (mips_isa)
> +{
> +case MIPS_ISA_MIPS1:
> +  return "mips1";
> +case MIPS_ISA_MIPS2:
> +  return "mips2";
> +case MIPS_ISA_MIPS3:
> +  return "mips3";
> +case MIPS_ISA_MIPS4:
> +  return "mips4";
> +case MIPS_ISA_MIPS32:
> +  return "mips32";
> +case MIPS_ISA_MIPS32R2:
> +  return "mips32r2";
> +case MIPS_ISA_MIPS32R3:
> +  return "mips32r3";
> +case MIPS_ISA_MIPS32R5:
> +  return "mips32r5";
> +case MIPS_ISA_MIPS32R6:
> +  return "mips32r6";
> +case MIPS_ISA_MIPS64:
> +  return "mips64";
> +case MIPS_ISA_MIPS64R2:
> +  return "mips64r2";
> +case MIPS_ISA_MIPS64R3:
> +  return "mips64r3";
> +case MIPS_ISA_MIPS64R5:
> +  return "mips64r5";
> +case MIPS_ISA_MIPS64R6:
> +  return "mips64r6";
> +default:
> +  gcc_unreachable ();
> +}
> +}
> +
>  /* Implement TARGET_ASM_FILE_START.  */
>
>  static void
> @@ -9873,6 +9911,9 @@ mips_file_start (void)
>  mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
>
>  #ifdef HAVE_AS_DOT_MODULE
> +  fprintf (asm_out_file, "\t.module\t%s\n",
> +  mips_module_isa_name ());
> +
>/* Record the FP ABI.  See below for comments.  */
>if (TARGET_NO_FLOAT)
>  #ifdef HAVE_AS_GNU_ATTRIBUTE
> --
> 2.30.2
>

[PATCH v2 1/2] MIPS: use mips_isa enum instead hardcoded numbers

[YunQiang Su]

Currently mips-cpu.defs, mips.h, netbsd.h and config.gcc are
using hardcoded numbers for isa level.

Let's replace them with more readable enum mips_isa.

gcc/ChangeLog:
* config/mips/mips.h (struct mips_cpu_info): define enum mips_isa;
  use enum instead of int for 'isa' member.
* config/config.gcc, config/mips/mips{.h,-cpus.def},
  config/mips/netbsd.h: replace hardcoded numbers with enum.
---
 gcc/config.gcc|  62 -
 gcc/config/mips/mips-cpus.def | 228 +-
 gcc/config/mips/mips.c|   5 +-
 gcc/config/mips/mips.h|  84 -
 gcc/config/mips/netbsd.h  |   5 +-
 5 files changed, 203 insertions(+), 181 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 0c91be6f3..0eba332bd 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2512,7 +2512,7 @@ mips*-img-linux*)
tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h 
glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h 
mips/mti-linux.h"
extra_options="${extra_options} linux-android.opt"
tmake_file="${tmake_file} mips/t-img-linux"
-   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32"
+   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6 
MIPS_ABI_DEFAULT=ABI_32"
with_arch_32="mips32r6"
with_arch_64="mips64r6"
gnu_ld=yes
@@ -2522,7 +2522,7 @@ mips*-mti-linux*)
tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h 
glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h 
mips/mti-linux.h"
extra_options="${extra_options} linux-android.opt"
tmake_file="${tmake_file} mips/t-mti-linux"
-   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32"
+   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2 
MIPS_ABI_DEFAULT=ABI_32"
with_arch_32="mips32r2"
with_arch_64="mips64r2"
gnu_ld=yes
@@ -2592,14 +2592,14 @@ mips*-*-linux*) # Linux MIPS, 
either endian.
 mips*-mti-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h 
mips/sde.h mips/mti-elf.h"
tmake_file="mips/t-mti-elf"
-   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32"
+   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2 
MIPS_ABI_DEFAULT=ABI_32"
with_arch_32="mips32r2"
with_arch_64="mips64r2"
;;
 mips*-img-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h 
mips/sde.h mips/mti-elf.h"
tmake_file="mips/t-img-elf"
-   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32"
+   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6 
MIPS_ABI_DEFAULT=ABI_32"
with_arch_32="mips32r6"
with_arch_64="mips64r6"
;;
@@ -2624,22 +2624,22 @@ mips*-sde-elf*)
esac
case ${target} in
  mipsisa32r6*)
-   tm_defines="MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32"
+   tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6 
MIPS_ABI_DEFAULT=ABI_32"
;;
  mipsisa32r2*)
-   tm_defines="MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32"
+   tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2 
MIPS_ABI_DEFAULT=ABI_32"
;;
  mipsisa32*)
-   tm_defines="MIPS_ISA_DEFAULT=32 MIPS_ABI_DEFAULT=ABI_32"
+   tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32 
MIPS_ABI_DEFAULT=ABI_32"
;;
  mipsisa64r6*)
-   tm_defines="MIPS_ISA_DEFAULT=69 MIPS_ABI_DEFAULT=ABI_N32"
+   tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R6 
MIPS_ABI_DEFAULT=ABI_N32"
;;
  mipsisa64r2*)
-   tm_defines="MIPS_ISA_DEFAULT=65 MIPS_ABI_DEFAULT=ABI_N32"
+   tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2 
MIPS_ABI_DEFAULT=ABI_N32"
;;
  mipsisa64*)
-   tm_defines="MIPS_ISA_DEFAULT=64 MIPS_ABI_DEFAULT=ABI_N32"
+   tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64 
MIPS_ABI_DEFAULT=ABI_N32"
;;
esac
;;
@@ -2653,22 +2653,22 @@ mipsisa64r6-*-elf* | mipsisa64r6el-*-elf*)
tmake_file="mips/t-isa3264"
case ${target} in
  mipsisa32r6*)
-   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37"
+   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6"
;;
  mipsisa32r2*)
-   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33"
+   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2"
;;
  mipsisa32*)
-   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=32"
+   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32"
;;
  mipsisa64r6*)
-   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=69"
+   tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R6"
;;
  mipsis

[PATCH v2 2/2] MIPS: add .module mipsREV to all output asm file

[YunQiang Su]

Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:
  assembler is mips1 by default,
  gcc is fpxx by default.
To assemble the output of gcc -S, we have to pass -mips2
to assembler.

gcc/ChangeLog:

* gcc/config/mips/mips.c (mips_module_isa_name): New.
mips_file_start: add .module mipsREV to all asm output
---
 gcc/config/mips/mips.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 493d3de48..a7087ec0a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9841,6 +9841,44 @@ mips_mdebug_abi_name (void)
 }
 }
 
+static const char *
+mips_module_isa_name ()
+{
+  switch (mips_isa)
+{
+case MIPS_ISA_MIPS1:
+  return "mips1";
+case MIPS_ISA_MIPS2:
+  return "mips2";
+case MIPS_ISA_MIPS3:
+  return "mips3";
+case MIPS_ISA_MIPS4:
+  return "mips4";
+case MIPS_ISA_MIPS32:
+  return "mips32";
+case MIPS_ISA_MIPS32R2:
+  return "mips32r2";
+case MIPS_ISA_MIPS32R3:
+  return "mips32r3";
+case MIPS_ISA_MIPS32R5:
+  return "mips32r5";
+case MIPS_ISA_MIPS32R6:
+  return "mips32r6";
+case MIPS_ISA_MIPS64:
+  return "mips64";
+case MIPS_ISA_MIPS64R2:
+  return "mips64r2";
+case MIPS_ISA_MIPS64R3:
+  return "mips64r3";
+case MIPS_ISA_MIPS64R5:
+  return "mips64r5";
+case MIPS_ISA_MIPS64R6:
+  return "mips64r6";
+default:
+  gcc_unreachable ();
+}
+}
+
 /* Implement TARGET_ASM_FILE_START.  */
 
 static void
@@ -9873,6 +9911,9 @@ mips_file_start (void)
 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
 
 #ifdef HAVE_AS_DOT_MODULE
+  fprintf (asm_out_file, "\t.module\t%s\n",
+  mips_module_isa_name ());
+
   /* Record the FP ABI.  See below for comments.  */
   if (TARGET_NO_FLOAT)
 #ifdef HAVE_AS_GNU_ATTRIBUTE
-- 
2.30.2

Re: [PATCH] libffi: Fix MIPS r6 support

[YunQiang Su]

在 2021/8/30 5:00, Jeff Law 写道:



On 8/28/2021 1:23 AM, Xi Ruoyao wrote:

On Fri, 2021-08-27 at 15:28 -0600, Jeff Law via Gcc-patches wrote:


On 8/26/2021 10:58 PM, YunQiang Su wrote:

for some instructions, MIPS r6 uses different encoding other than
the previous releases.

1. mips/n32.S disable .set mips4: since it casuses old insn encoding
 is used.
 https://github.com/libffi/libffi/pull/396
2. mips/ffi.c: the encoding for JR is hardcoded: we need to use
 different value for r6 and pre-r6.
 https://github.com/libffi/libffi/pull/401

libffi/
 PR libffi/83636
 * src/mips/n32.S: disable .set mips4
 * src/mips/ffi.c: use different JR encoding for r6.

These should go to the upstream libffi project.  Once accepted there
you
can add them to GCC.

Hi Jeff,

The two PRs are already merged, and released since libffi-3.3.0 (now the
upstream latest release is 3.4.2).
ACK.  Thanks for confirming.  It's always OK to cherrypick/backport from 
libffi back to GCC.




I don't have a MIPSr6 so I can't test though.
Understood.   Me neither, but I really should get a tiny chroot for 
mipsr6 so that my tester can validate it regularly.




We have port Debian to MIPS64r6el.
http://58.246.137.130:20180/tools/tarball/
You can use both buster(Debian 10) or bullseye (Debian 11).

And both qemu-system and qemu-user can work.



Jeff
.

Re: [PATCH] libffi: Fix MIPS r6 support

[YunQiang Su]

Jeff Law via Gcc-patches  于2021年8月30日周一 下午9:48写道：
>
>
>
> On 8/30/2021 2:47 AM, YunQiang Su wrote:
> > 在 2021/8/30 5:00, Jeff Law 写道:
> >>
> >>
> >> On 8/28/2021 1:23 AM, Xi Ruoyao wrote:
> >>> On Fri, 2021-08-27 at 15:28 -0600, Jeff Law via Gcc-patches wrote:
> >>>>
> >>>> On 8/26/2021 10:58 PM, YunQiang Su wrote:
> >>>>> for some instructions, MIPS r6 uses different encoding other than
> >>>>> the previous releases.
> >>>>>
> >>>>> 1. mips/n32.S disable .set mips4: since it casuses old insn encoding
> >>>>>  is used.
> >>>>>  https://github.com/libffi/libffi/pull/396
> >>>>> 2. mips/ffi.c: the encoding for JR is hardcoded: we need to use
> >>>>>  different value for r6 and pre-r6.
> >>>>>  https://github.com/libffi/libffi/pull/401
> >>>>>
> >>>>> libffi/
> >>>>>  PR libffi/83636
> >>>>>  * src/mips/n32.S: disable .set mips4
> >>>>>  * src/mips/ffi.c: use different JR encoding for r6.
> >>>> These should go to the upstream libffi project.  Once accepted there
> >>>> you
> >>>> can add them to GCC.
> >>> Hi Jeff,
> >>>
> >>> The two PRs are already merged, and released since libffi-3.3.0 (now
> >>> the
> >>> upstream latest release is 3.4.2).
> >> ACK.  Thanks for confirming.  It's always OK to cherrypick/backport
> >> from libffi back to GCC.
> >>
> >>>
> >>> I don't have a MIPSr6 so I can't test though.
> >> Understood.   Me neither, but I really should get a tiny chroot for
> >> mipsr6 so that my tester can validate it regularly.
> >>
> >
> > We have port Debian to MIPS64r6el.
> > http://58.246.137.130:20180/tools/tarball/
> > You can use both buster(Debian 10) or bullseye (Debian 11).
> >
> > And both qemu-system and qemu-user can work.
> Understood.  I need the minimal chroot to compress down under 100M to

A minimal tarball is ready now with size about 87M.

> make gitlab happy (that's where my scripts & jenkins system expect to
> find them).  My scripts to build the chroots also ensure a consistent
> set of packages & version #s across the different systems being
> tested.   I've just never gotten around to building one for mips64r6.  I
> could probably take yours trim out unnecessary stuff and use it for
> now.  Getting a bootstrap test on the target weekly is definitely helpful.
>

That's great.
Since the minimal rootfs lacks of lots of tools, and
if you need some tools, you can just apt install them,then.

> jeff

[PATCH v2] md/define_c_enum: support value assignation

[YunQiang Su]

Currently, the enums from define_c_enum and define_enum can only
has values one by one from 0.

In fact we can support the behaviour just like C, aka like
  (define_enum "mips_isa" [(mips1 1) mips2 (mips32 32) mips32r2]),
then we can get
  enum mips_isa {
MIPS_ISA_MIPS1 = 1,
MIPS_ISA_MIPS2 = 2,
MIPS_ISA_MIPS32 = 32,
MIPS_ISA_MIPS32R2 = 33
  };

gcc/ChangeLog:
* read-md.c (md_reader::handle_enum): support value assignation.
* doc/md.texi: record define_c_enum value assignation support.
---
 gcc/doc/md.texi |  4 
 gcc/read-md.c   | 28 
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index f8047aefc..2b41cb7fb 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -11074,6 +11074,8 @@ The syntax is as follows:
 (define_c_enum "@var{name}" [
   @var{value0}
   @var{value1}
+  (@var{value32} 32)
+  @var{value33}
   @dots{}
   @var{valuen}
 ])
@@ -11086,6 +11088,8 @@ in @file{insn-constants.h}:
 enum @var{name} @{
   @var{value0} = 0,
   @var{value1} = 1,
+  @var{value32} = 32,
+  @var{value33} = 33,
   @dots{}
   @var{valuen} = @var{n}
 @};
diff --git a/gcc/read-md.c b/gcc/read-md.c
index bb419e0f6..2d01c69fc 100644
--- a/gcc/read-md.c
+++ b/gcc/read-md.c
@@ -902,7 +902,9 @@ void
 md_reader::handle_enum (file_location loc, bool md_p)
 {
   char *enum_name, *value_name;
-  struct md_name name;
+  unsigned int cur_value;
+  struct md_name name, value;
+  bool value_given;
   struct enum_type *def;
   struct enum_value *ev;
   void **slot;
@@ -928,6 +930,7 @@ md_reader::handle_enum (file_location loc, bool md_p)
   *slot = def;
 }
 
+  cur_value = def->num_values;
   require_char_ws ('[');
 
   while ((c = read_skip_spaces ()) != ']')
@@ -937,28 +940,45 @@ md_reader::handle_enum (file_location loc, bool md_p)
  error_at (loc, "unterminated construct");
  exit (1);
}
-  unread_char (c);
-  read_name (&name);
+  value_given = false;
+  if (c == '(')
+   {
+ read_name (&name);
+ read_name (&value);
+ require_char_ws (')');
+ cur_value = atoi(value.string);
+ value_given = true;
+   }
+  else
+   {
+ unread_char (c);
+ read_name (&name);
+   }
 
   ev = XNEW (struct enum_value);
   ev->next = 0;
   if (md_p)
{
  value_name = concat (def->name, "_", name.string, NULL);
+ if (value_given)
+   cur_value = atoi (value.string);
  upcase_string (value_name);
  ev->name = xstrdup (name.string);
}
   else
{
  value_name = xstrdup (name.string);
+ if (value_given)
+   cur_value = atoi (value.string);
  ev->name = value_name;
}
   ev->def = add_constant (get_md_constants (), value_name,
- md_decimal_string (def->num_values), def);
+ md_decimal_string (cur_value), def);
 
   *def->tail_ptr = ev;
   def->tail_ptr = &ev->next;
   def->num_values++;
+  cur_value++;
 }
 }
 
-- 
2.30.2

[PATCH v3] md/define_c_enum: support value assignation

[YunQiang Su]

Currently, the enums from define_c_enum and define_enum can only
has values one by one from 0.

In fact we can support the behaviour just like C, aka like
  (define_enum "mips_isa" [(mips1 1) mips2 (mips32 32) mips32r2]),
then we can get
  enum mips_isa {
MIPS_ISA_MIPS1 = 1,
MIPS_ISA_MIPS2 = 2,
MIPS_ISA_MIPS32 = 32,
MIPS_ISA_MIPS32R2 = 33
  };

gcc/ChangeLog:
* read-md.c (md_reader::handle_enum): support value assignation.
* doc/md.texi: record define_c_enum value assignation support.
---
 gcc/doc/md.texi |  4 
 gcc/read-md.c   | 21 +
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index f8047aefc..2b41cb7fb 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -11074,6 +11074,8 @@ The syntax is as follows:
 (define_c_enum "@var{name}" [
   @var{value0}
   @var{value1}
+  (@var{value32} 32)
+  @var{value33}
   @dots{}
   @var{valuen}
 ])
@@ -11086,6 +11088,8 @@ in @file{insn-constants.h}:
 enum @var{name} @{
   @var{value0} = 0,
   @var{value1} = 1,
+  @var{value32} = 32,
+  @var{value33} = 33,
   @dots{}
   @var{valuen} = @var{n}
 @};
diff --git a/gcc/read-md.c b/gcc/read-md.c
index bb419e0f6..0fbe924d1 100644
--- a/gcc/read-md.c
+++ b/gcc/read-md.c
@@ -902,7 +902,8 @@ void
 md_reader::handle_enum (file_location loc, bool md_p)
 {
   char *enum_name, *value_name;
-  struct md_name name;
+  unsigned int cur_value;
+  struct md_name name, value;
   struct enum_type *def;
   struct enum_value *ev;
   void **slot;
@@ -928,6 +929,7 @@ md_reader::handle_enum (file_location loc, bool md_p)
   *slot = def;
 }
 
+  cur_value = def->num_values;
   require_char_ws ('[');
 
   while ((c = read_skip_spaces ()) != ']')
@@ -937,8 +939,18 @@ md_reader::handle_enum (file_location loc, bool md_p)
  error_at (loc, "unterminated construct");
  exit (1);
}
-  unread_char (c);
-  read_name (&name);
+  if (c == '(')
+   {
+ read_name (&name);
+ read_name (&value);
+ require_char_ws (')');
+ cur_value = atoi(value.string);
+   }
+  else
+   {
+ unread_char (c);
+ read_name (&name);
+   }
 
   ev = XNEW (struct enum_value);
   ev->next = 0;
@@ -954,11 +966,12 @@ md_reader::handle_enum (file_location loc, bool md_p)
  ev->name = value_name;
}
   ev->def = add_constant (get_md_constants (), value_name,
- md_decimal_string (def->num_values), def);
+ md_decimal_string (cur_value), def);
 
   *def->tail_ptr = ev;
   def->tail_ptr = &ev->next;
   def->num_values++;
+  cur_value++;
 }
 }
 
-- 
2.30.2

Re: [PATCH v2] md/define_c_enum: support value assignation

[YunQiang Su]

YunQiang Su  于2021年8月31日周二 下午7:09写道：
>
> Currently, the enums from define_c_enum and define_enum can only
> has values one by one from 0.
>
> In fact we can support the behaviour just like C, aka like
>   (define_enum "mips_isa" [(mips1 1) mips2 (mips32 32) mips32r2]),
> then we can get
>   enum mips_isa {
> MIPS_ISA_MIPS1 = 1,
> MIPS_ISA_MIPS2 = 2,
> MIPS_ISA_MIPS32 = 32,
> MIPS_ISA_MIPS32R2 = 33
>   };
>
> gcc/ChangeLog:
> * read-md.c (md_reader::handle_enum): support value assignation.
> * doc/md.texi: record define_c_enum value assignation support.
> ---
>  gcc/doc/md.texi |  4 
>  gcc/read-md.c   | 28 
>  2 files changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index f8047aefc..2b41cb7fb 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -11074,6 +11074,8 @@ The syntax is as follows:
>  (define_c_enum "@var{name}" [
>@var{value0}
>@var{value1}
> +  (@var{value32} 32)
> +  @var{value33}
>@dots{}
>@var{valuen}
>  ])
> @@ -11086,6 +11088,8 @@ in @file{insn-constants.h}:
>  enum @var{name} @{
>@var{value0} = 0,
>@var{value1} = 1,
> +  @var{value32} = 32,
> +  @var{value33} = 33,
>@dots{}
>@var{valuen} = @var{n}
>  @};
> diff --git a/gcc/read-md.c b/gcc/read-md.c
> index bb419e0f6..2d01c69fc 100644
> --- a/gcc/read-md.c
> +++ b/gcc/read-md.c
> @@ -902,7 +902,9 @@ void
>  md_reader::handle_enum (file_location loc, bool md_p)
>  {
>char *enum_name, *value_name;
> -  struct md_name name;
> +  unsigned int cur_value;
> +  struct md_name name, value;
> +  bool value_given;

This flag is not needed at all. So please ignore V2.
See V3 please.

>struct enum_type *def;
>struct enum_value *ev;
>void **slot;
> @@ -928,6 +930,7 @@ md_reader::handle_enum (file_location loc, bool md_p)
>*slot = def;
>  }
>
> +  cur_value = def->num_values;
>require_char_ws ('[');
>
>while ((c = read_skip_spaces ()) != ']')
> @@ -937,28 +940,45 @@ md_reader::handle_enum (file_location loc, bool md_p)
>   error_at (loc, "unterminated construct");
>   exit (1);
> }
> -  unread_char (c);
> -  read_name (&name);
> +  value_given = false;
> +  if (c == '(')
> +   {
> + read_name (&name);
> + read_name (&value);
> + require_char_ws (')');
> + cur_value = atoi(value.string);
> + value_given = true;
> +   }
> +  else
> +   {
> + unread_char (c);
> + read_name (&name);
> +   }
>
>ev = XNEW (struct enum_value);
>ev->next = 0;
>if (md_p)
> {
>   value_name = concat (def->name, "_", name.string, NULL);
> + if (value_given)
> +   cur_value = atoi (value.string);
>   upcase_string (value_name);
>   ev->name = xstrdup (name.string);
> }
>else
> {
>   value_name = xstrdup (name.string);
> + if (value_given)
> +   cur_value = atoi (value.string);
>   ev->name = value_name;
> }
>ev->def = add_constant (get_md_constants (), value_name,
> - md_decimal_string (def->num_values), def);
> + md_decimal_string (cur_value), def);
>
>*def->tail_ptr = ev;
>def->tail_ptr = &ev->next;
>def->num_values++;
> +  cur_value++;
>  }
>  }
>
> --
> 2.30.2
>

[PATCH v2] MIPS: improve -march=native arch detection

[YunQiang Su]

If we cannot get info from options and cpuinfo, we try to get from:
  1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7
  2. _MIPS_ARCH from host compiler.

mnan=2008 option is also used if __mips_nan2008__ is used.
This can fix the wrong loader usage on r5/r6 platform with
 -march=native.

gcc/ChangeLog:
* config.gcc: set with_arch to default_mips_arch if no defined.
* config/mips/driver-native.cc (host_detect_local_cpu):
  try getauxval(AT_BASE_PLATFORM) and _MIPS_ARCH, too.
  pass -mnan=2008 if __mips_nan2008__ is defined.
* config.in: define HAVE_SYS_AUXV_H and HAVE_GETAUXVAL.
* configure.ac: detect sys/auxv.h and getauxval.
* configure: regenerated.
---
 gcc/config.gcc   |  2 ++
 gcc/config.in| 10 ++
 gcc/config/mips/driver-native.cc | 25 ++---
 gcc/configure|  4 ++--
 gcc/configure.ac |  4 ++--
 5 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f4e757bd853..181a062825d 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -5590,6 +5590,8 @@ case ${target} in
esac
if test x$with_arch != x; then
default_mips_arch=$with_arch
+   else
+   with_arch=$default_mips_arch
fi
if test x$with_abi != x; then
default_mips_abi=$with_abi
diff --git a/gcc/config.in b/gcc/config.in
index 6ac17be189e..cc217b94e0c 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -1939,6 +1939,12 @@
 #endif
 
 
+/* Define to 1 if you have the  header file. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_SYS_AUXV_H
+#endif
+
+
 /* Define to 1 if you have the  header file. */
 #ifndef USED_FOR_TARGET
 #undef HAVE_SYS_FILE_H
@@ -2672,3 +2678,7 @@
 #undef vfork
 #endif
 
+/* Define to 1 if you have the `getauxval' function. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_GETAUXVAL
+#endif
diff --git a/gcc/config/mips/driver-native.cc b/gcc/config/mips/driver-native.cc
index 47627f85ce1..327ad255c3e 100644
--- a/gcc/config/mips/driver-native.cc
+++ b/gcc/config/mips/driver-native.cc
@@ -23,6 +23,9 @@ along with GCC; see the file COPYING3.  If not see
 #include "system.h"
 #include "coretypes.h"
 #include "tm.h"
+#ifdef HAVE_SYS_AUXV_H
+#include 
+#endif
 
 /* This will be called by the spec parser in gcc.cc when it sees
a %:local_cpu_detect(args) construct.  Currently it will be called
@@ -41,6 +44,7 @@ const char *
 host_detect_local_cpu (int argc, const char **argv)
 {
   const char *cpu = NULL;
+  char *ret = NULL;
   char buf[128];
   FILE *f;
   bool arch;
@@ -54,7 +58,7 @@ host_detect_local_cpu (int argc, const char **argv)
 
   f = fopen ("/proc/cpuinfo", "r");
   if (f == NULL)
-return NULL;
+goto fallback_cpu;
 
   while (fgets (buf, sizeof (buf), f) != NULL)
 if (startswith (buf, "cpu model"))
@@ -84,8 +88,23 @@ host_detect_local_cpu (int argc, const char **argv)
 
   fclose (f);
 
+fallback_cpu:
+#if defined (__mips_nan2008)
+  ret = reconcat (ret, " -mnan=2008 ", NULL);
+#endif
+
+#ifdef HAVE_GETAUXVAL
   if (cpu == NULL)
-return NULL;
+cpu = (const char *) getauxval (AT_BASE_PLATFORM);
+#endif
+
+#if defined (_MIPS_ARCH)
+  if (cpu == NULL)
+cpu = _MIPS_ARCH;
+#endif
+
+  if (cpu)
+ret = reconcat (ret, ret, "-m", argv[0], "=", cpu, NULL);
 
-  return concat ("-m", argv[0], "=", cpu, NULL);
+  return ret;
 }
diff --git a/gcc/configure b/gcc/configure
index 817d765568e..a419ac66576 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -9327,7 +9327,7 @@ $as_echo "#define GWINSZ_IN_SYS_IOCTL 1" >>confdefs.h
 fi
 
 for ac_header in limits.h stddef.h string.h strings.h stdlib.h time.h iconv.h \
-fcntl.h ftw.h unistd.h sys/file.h sys/time.h sys/mman.h \
+fcntl.h ftw.h unistd.h sys/auxv.h sys/file.h sys/time.h 
sys/mman.h \
 sys/resource.h sys/param.h sys/times.h sys/stat.h 
sys/locking.h \
 direct.h malloc.h langinfo.h ldfcn.h locale.h wchar.h
 do :
@@ -10622,7 +10622,7 @@ fi
 for ac_func in times clock kill getrlimit setrlimit atoq \
popen sysconf strsignal getrusage nl_langinfo \
gettimeofday mbstowcs wcswidth mmap posix_fallocate setlocale \
-   clearerr_unlocked feof_unlocked   ferror_unlocked fflush_unlocked 
fgetc_unlocked fgets_unlocked   fileno_unlocked fprintf_unlocked fputc_unlocked 
fputs_unlocked   fread_unlocked fwrite_unlocked getchar_unlocked getc_unlocked  
 putchar_unlocked putc_unlocked madvise mallinfo mallinfo2 fstatat
+   clearerr_unlocked feof_unlocked   ferror_unlocked fflush_unlocked 
fgetc_unlocked fgets_unlocked   fileno_unlocked fprintf_unlocked fputc_unlocked 
fputs_unlocked   fread_unlocked fwrite_unlocked getchar_unlocked getc_unlocked  
 putchar_unlocked putc_unlocked madvise mallinfo mallinfo2 fstatat getauxval
 do :
   as_ac_var=`$as_echo "ac_cv_func

[PATCH] MIPS: fix building on multiarch platform

[YunQiang Su]

On platforms that support multiarch, such as Debian,
the filesystem hierarchy doesn't fellow the old Irix style:
lib & lib/ for native
lib64 for N64 on N32/O32 systems
lib32 for N32 on N64/O32 systems
libo32 for O32 on N64/N32 systems

Thus we cannot
 #define STANDARD_STARTFILE_PREFIX_1
 #define STANDARD_STARTFILE_PREFIX_2
on N32 or N64 systems, else collect2 won't look for libraries
on /lib/.

gcc/ChangeLog:
* configure.ac: AC_DEFINE(ENABLE_MULTIARCH, 1)
* configure: Regenerated.
* config.in: Regenerated.
* config/mips/mips.h: don't define STANDARD_STARTFILE_PREFIX_1
  if ENABLE_MULTIARCH is defined.
* config/mips/t-linux64: define correct multiarch path when
  multiarch is enabled.
---
 gcc/config.in |  6 ++
 gcc/config/mips/mips.h|  2 ++
 gcc/config/mips/t-linux64 | 21 -
 gcc/configure |  4 
 gcc/configure.ac  |  3 +++
 5 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/gcc/config.in b/gcc/config.in
index 6ac17be189e..b2ce6361327 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -2312,6 +2312,12 @@
 #endif
 
 
+/* Specify if mutliarch is enabled. */
+#ifndef USED_FOR_TARGET
+#undef ENABLE_MULTIARCH
+#endif
+
+
 /* The size of `dev_t', as computed by sizeof. */
 #ifndef USED_FOR_TARGET
 #undef SIZEOF_DEV_T
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 74b6e11aabb..fe7f5b274b9 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3427,6 +3427,7 @@ struct GTY(())  machine_function {
 
 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
need to change these from /lib and /usr/lib.  */
+#ifndef ENABLE_MULTIARCH
 #if MIPS_ABI_DEFAULT == ABI_N32
 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
@@ -3434,6 +3435,7 @@ struct GTY(())  machine_function {
 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
 #endif
+#endif
 
 /* Load store bonding is not supported by micromips and fix_24k.  The
performance can be degraded for those targets.  Hence, do not bond for
diff --git a/gcc/config/mips/t-linux64 b/gcc/config/mips/t-linux64
index 2fdd8e00407..37d176ea309 100644
--- a/gcc/config/mips/t-linux64
+++ b/gcc/config/mips/t-linux64
@@ -20,7 +20,26 @@ MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64
 MULTILIB_DIRNAMES = n32 32 64
 MIPS_EL = $(if $(filter %el, $(firstword $(subst -, ,$(target,el)
 MIPS_SOFT = $(if $(strip $(filter MASK_SOFT_FLOAT_ABI, $(target_cpu_default)) 
$(filter soft, $(with_float))),soft)
-MULTILIB_OSDIRNAMES = \
+ifeq (yes,$(enable_multiarch))
+  ifneq (,$(findstring gnuabi64,$(target)))
+MULTILIB_OSDIRNAMES = \
+   ../lib32$(call 
if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
+   ../libo32$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
+   ../lib$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
+  else ifneq (,$(findstring gnuabin32,$(target)))
+MULTILIB_OSDIRNAMES = \
+   ../lib$(call 
if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
+   ../libo32$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
+   ../lib64$(call 
if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
+  else
+MULTILIB_OSDIRNAMES = \
+   ../lib32$(call 
if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
+   ../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
+   ../lib64$(call 
if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
+  endif
+else
+  MULTILIB_OSDIRNAMES = \
../lib32$(call 
if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
../lib64$(call 
if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
+endif
diff --git a/gcc/configure b/gcc/configure
index 817d765568e..f9a796d6bb4 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -7841,6 +7841,10 @@ if test x${enable_multiarch} = xauto; then
 enable_multiarch=no
   fi
 fi
+if test x${enable_multiarch} = xyes; then
+  $as_echo "#define ENABLE_MULTIARCH 1" >>confdefs.h
+
+fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for multiarch configuration" 
>&5
 $as_echo_n "checking for multiarch configuration... " >&6; }
 
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 59f205a1781..44631e23033 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -886,6 +886,9 @@ if test x${enable_multiarch} = xauto; then
 enable_multiarch=no
   fi
 fi
+if test x${enable_multiarch} = xyes; then
+  AC_DEFINE(ENABLE_MULTIARCH, 1)
+fi
 AC_MSG_CHECKING(for multiarch configuration)
 AC_SUBST(enable_multiarch)
 AC_MSG_RESULT($enable_multiarch$ma_msg_suffix)
-- 
2.30.2

[PATCH v3] MIPS: IPL is 8bit in Cause and Status registers if TARGET_MCU

[YunQiang Su]

If MIPS MCU extension is enable, the IPL section in Cause and Status
registers has been expand to 8bit instead of 6bit.

In Cause: the bits are 10-17.
In Status: the bits are 10-16 and 18.

MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61.

gcc/ChangeLog:

* config/mips/mips.cc (mips_expand_prologue):
  IPL is 8bit for MCU ASE.
---
 gcc/config/mips/mips.cc | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index a1c4b437cd4..91e1e964f94 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12254,10 +12254,22 @@ mips_expand_prologue (void)
  /* Insert the RIPL into our copy of SR (k1) as the new IPL.  */
  if (!cfun->machine->keep_interrupts_masked_p
  && cfun->machine->int_mask == INT_MASK_EIC)
-   emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-  GEN_INT (6),
+   {
+ emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
+  TARGET_MCU ? GEN_INT (7) : GEN_INT (6),
   GEN_INT (SR_IPL),
   gen_rtx_REG (SImode, K0_REG_NUM)));
+ if (TARGET_MCU)
+   {
+ emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
+   gen_rtx_REG (SImode, K0_REG_NUM),
+   GEN_INT (7)));
+ emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
+  GEN_INT (1),
+  GEN_INT (SR_IPL+8),
+  gen_rtx_REG (SImode, K0_REG_NUM)));
+   }
+   }
 
  /* Clear all interrupt mask bits up to and including the
 handler's interrupt line.  */
-- 
2.30.2

Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

[YunQiang Su]

在 2022/2/12 16:47, Maciej W. Rozycki 写道:

On Fri, 11 Feb 2022, Jeff Law wrote:


If MIPS MCU extension is enable, the IPL section in Cause register
has been expand to 8bit instead of 6bit.

gcc/ChangeLog:

* config/mips/mips.cc (mips_expand_prologue):
  IPL is 8bit for MCU ASE.

OK


  But this is still wrong AFAICT.



Yes. you are right.


  The mask is applied to the CP0 Status register according to the comment,
but the layout of the interrupt bit-field is different between the CP0
Status and the CP0 Cause registers, so you can't just extract it from one
of the two registers and directly apply to the other.



Since our case has 128 interrupts, so I didn't find this problem.


  I would like to know how this code has been verified.


And now new version sent with the test with 256 interrupts.

See v3 please.



   Maciej
.

[PATCH] MIPS: use 8bit for IPL in Cause register

[YunQiang Su]

Since MIPS r2, the IPL section in Cause register has been expand
to 8bit instead of 6bit.

Since __attribute__((interrupt)) is only supported for r2+,
we don't need to detect the target.

gcc/ChangeLog:

* config/mips/mips.cc (mips_expand_prologue):
  IPL is 8bit for r2+.
---
 gcc/config/mips/mips.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4f9683e8bf4..bde88fb8e5a 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12255,7 +12255,7 @@ mips_expand_prologue (void)
  if (!cfun->machine->keep_interrupts_masked_p
  && cfun->machine->int_mask == INT_MASK_EIC)
emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-  GEN_INT (6),
+  GEN_INT (8),
   GEN_INT (SR_IPL),
   gen_rtx_REG (SImode, K0_REG_NUM)));
 
-- 
2.30.2

[PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

[YunQiang Su]

If MIPS MCU extension is enable, the IPL section in Cause register
has been expand to 8bit instead of 6bit.

gcc/ChangeLog:

* config/mips/mips.cc (mips_expand_prologue):
  IPL is 8bit for MCU ASE.
---
 gcc/config/mips/mips.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4f9683e8bf4..d823c459b75 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12255,7 +12255,7 @@ mips_expand_prologue (void)
  if (!cfun->machine->keep_interrupts_masked_p
  && cfun->machine->int_mask == INT_MASK_EIC)
emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-  GEN_INT (6),
+  TARGET_MCU ? GEN_INT (8) : GEN_INT (6),
   GEN_INT (SR_IPL),
   gen_rtx_REG (SImode, K0_REG_NUM)));
 
-- 
2.30.2

Re: [PATCH] MIPS: improve -march=native arch detection

[YunQiang Su]

On Tue, Aug 02, 2022 at 11:10:09AM +, YunQiang Su wrote:
> If we cannot get info from options and cpuinfo, we try to get from:
>   1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7
>   2. _MIPS_ARCH from host compiler.
> 
> This can fix the wrong loader usage on r5/r6 platform with
>  -march=native.
>

ping...

> gcc/ChangeLog:
>   * config/mips/driver-native.cc (host_detect_local_cpu):
> try getauxval(AT_BASE_PLATFORM) and _MIPS_ARCH, too.
> ---
>  gcc/config/mips/driver-native.cc | 22 +++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/gcc/config/mips/driver-native.cc 
> b/gcc/config/mips/driver-native.cc
> index 47627f85ce1..9aa7044c0b8 100644
> --- a/gcc/config/mips/driver-native.cc
> +++ b/gcc/config/mips/driver-native.cc
> @@ -19,6 +19,7 @@ along with GCC; see the file COPYING3.  If not see
>  
>  #define IN_TARGET_CODE 1
>  
> +#include 
>  #include "config.h"
>  #include "system.h"
>  #include "coretypes.h"
> @@ -46,15 +47,15 @@ host_detect_local_cpu (int argc, const char **argv)
>bool arch;
>  
>if (argc < 1)
> -return NULL;
> +goto fallback_cpu;
>  
>arch = strcmp (argv[0], "arch") == 0;
>if (!arch && strcmp (argv[0], "tune"))
> -return NULL;
> +goto fallback_cpu;
>  
>f = fopen ("/proc/cpuinfo", "r");
>if (f == NULL)
> -return NULL;
> +goto fallback_cpu;
>  
>while (fgets (buf, sizeof (buf), f) != NULL)
>  if (startswith (buf, "cpu model"))
> @@ -84,8 +85,23 @@ host_detect_local_cpu (int argc, const char **argv)
>  
>fclose (f);
>  
> +fallback_cpu:
> +/*FIXME: how about other OSes, like FreeBSD? */
> +#ifdef __linux__
> +  /*Note: getauxval may return NULL as:
> +   * AT_BASE_PLATFORM is supported since Linux 5.7
> +   * Or from older version of qemu-user
> +   * */
> +  if (cpu == NULL)
> +cpu = (const char *) getauxval (AT_BASE_PLATFORM);
> +#endif
> +
>if (cpu == NULL)
> +#if defined (_MIPS_ARCH)
> +cpu = _MIPS_ARCH;
> +#else
>  return NULL;
> +#endif
>  
>return concat ("-m", argv[0], "=", cpu, NULL);
>  }
> -- 
> 2.30.2
> 

Re: [PATCH] MIPS: improve -march=native arch detection

[YunQiang Su]

YunQiang Su  于2022年8月2日周二 19:11写道：
>
> If we cannot get info from options and cpuinfo, we try to get from:
>   1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7
>   2. _MIPS_ARCH from host compiler.
>
> This can fix the wrong loader usage on r5/r6 platform with
>  -march=native.
>

Is it treat as minor fixes?

> gcc/ChangeLog:
> * config/mips/driver-native.cc (host_detect_local_cpu):
>   try getauxval(AT_BASE_PLATFORM) and _MIPS_ARCH, too.
> ---
>  gcc/config/mips/driver-native.cc | 22 +++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/mips/driver-native.cc 
> b/gcc/config/mips/driver-native.cc
> index 47627f85ce1..9aa7044c0b8 100644
> --- a/gcc/config/mips/driver-native.cc
> +++ b/gcc/config/mips/driver-native.cc
> @@ -19,6 +19,7 @@ along with GCC; see the file COPYING3.  If not see
>
>  #define IN_TARGET_CODE 1
>
> +#include 
>  #include "config.h"
>  #include "system.h"
>  #include "coretypes.h"
> @@ -46,15 +47,15 @@ host_detect_local_cpu (int argc, const char **argv)
>bool arch;
>
>if (argc < 1)
> -return NULL;
> +goto fallback_cpu;
>
>arch = strcmp (argv[0], "arch") == 0;
>if (!arch && strcmp (argv[0], "tune"))
> -return NULL;
> +goto fallback_cpu;
>
>f = fopen ("/proc/cpuinfo", "r");
>if (f == NULL)
> -return NULL;
> +goto fallback_cpu;
>
>while (fgets (buf, sizeof (buf), f) != NULL)
>  if (startswith (buf, "cpu model"))
> @@ -84,8 +85,23 @@ host_detect_local_cpu (int argc, const char **argv)
>
>fclose (f);
>
> +fallback_cpu:
> +/*FIXME: how about other OSes, like FreeBSD? */
> +#ifdef __linux__
> +  /*Note: getauxval may return NULL as:
> +   * AT_BASE_PLATFORM is supported since Linux 5.7
> +   * Or from older version of qemu-user
> +   * */
> +  if (cpu == NULL)
> +cpu = (const char *) getauxval (AT_BASE_PLATFORM);
> +#endif
> +
>if (cpu == NULL)
> +#if defined (_MIPS_ARCH)
> +cpu = _MIPS_ARCH;
> +#else
>  return NULL;
> +#endif
>
>return concat ("-m", argv[0], "=", cpu, NULL);
>  }
> --
> 2.30.2
>

Re: [PATCH] Add MIPS Linux support to gcc.misc-tests/linkage.c (testsuite/51748)

[YunQiang Su]

Richard Sandiford via Gcc-patches 
于2021年9月1日周三 下午4:55写道：
>
> apinski--- via Gcc-patches  writes:
> > From: Andrew Pinski 
> >
> > This adds MIPS Linux support to gcc.misc-tests/linkage.exp.  Basically
> > copying what was done for MIPS IRIX and changing the options to be correct.
> >
> > OK?
> >
> > gcc/testsuite/ChangeLog:
> >
> >   PR testsuite/51748
> >   * gcc.misc-tests/linkage.exp: Add mips*-linux-* support.
>
> OK, thanks.  Searching for any match for 64 seems surprisingly general,
> but it's what other cases do and has obviously stood the test of time.
>

syq@XX:~$ gcc -mips64r2 -mabi=64 -c zz.c && file zz.o
zz.o: ELF 64-bit LSB relocatable, MIPS, MIPS64 rel2 version 1 (SYSV),
not stripped
syq@XX:~$ gcc -mips64r2 -mabi=32 -c zz.c && file zz.o
zz.o: ELF 32-bit LSB relocatable, MIPS, MIPS64 rel2 version 1 (SYSV),
not stripped
syq@XX:~$ gcc -mips64r2 -mabi=n32 -c zz.c && file zz.o
zz.o: ELF 32-bit LSB relocatable, MIPS, N32 MIPS64 rel2 version 1
(SYSV), not stripped

In the first glance, I also thought the code is wrong. While with some
check, it does work.

> Richard
>
> > ---
> >  gcc/testsuite/gcc.misc-tests/linkage.exp | 12 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/gcc/testsuite/gcc.misc-tests/linkage.exp 
> > b/gcc/testsuite/gcc.misc-tests/linkage.exp
> > index afed2b811c9..2cb109e776e 100644
> > --- a/gcc/testsuite/gcc.misc-tests/linkage.exp
> > +++ b/gcc/testsuite/gcc.misc-tests/linkage.exp
> > @@ -38,6 +38,18 @@ if { [isnative] && ![is_remote host] } then {
> >
> >   # Need to ensure ABI for native compiler matches gcc
> >   set native_cflags ""
> > + if  [istarget "mips*-linux*"] {
> > + set file_string [exec file "linkage-x.o"]
> > + if [ string match "*64*" $file_string ] {
> > + set native_cflags "-mabi=64"
> > + }
> > + if [ string match "*ELF 32*" $file_string ] {
> > + set native_cflags "-mabi=32"
> > + }
> > + if [ string match "*N32*" $file_string ] {
> > + set native_cflags "-mabi=n32"
> > + }
> > + }
> >   if  [istarget "sparc*-sun-solaris2*"] {
> >   set file_string [exec file "linkage-x.o"]
> >   if [ string match "*64*" $file_string ] {

Re: [PATCH v3] md/define_c_enum: support value assignation

[YunQiang Su]

Andrew Pinski via Gcc-patches  于2021年9月2日周四 上午5:28写道：
>
> On Tue, Aug 31, 2021 at 4:22 AM YunQiang Su  wrote:
> >
> > Currently, the enums from define_c_enum and define_enum can only
> > has values one by one from 0.
> >
> > In fact we can support the behaviour just like C, aka like
> >   (define_enum "mips_isa" [(mips1 1) mips2 (mips32 32) mips32r2]),
> > then we can get
> >   enum mips_isa {
> > MIPS_ISA_MIPS1 = 1,
> > MIPS_ISA_MIPS2 = 2,
> > MIPS_ISA_MIPS32 = 32,
> > MIPS_ISA_MIPS32R2 = 33
> >   };
> >
> > gcc/ChangeLog:
> > * read-md.c (md_reader::handle_enum): support value assignation.
> > * doc/md.texi: record define_c_enum value assignation support.
> > ---
> >  gcc/doc/md.texi |  4 
> >  gcc/read-md.c   | 21 +
> >  2 files changed, 21 insertions(+), 4 deletions(-)
> >
> > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> > index f8047aefc..2b41cb7fb 100644
> > --- a/gcc/doc/md.texi
> > +++ b/gcc/doc/md.texi
> > @@ -11074,6 +11074,8 @@ The syntax is as follows:
> >  (define_c_enum "@var{name}" [
> >@var{value0}
> >@var{value1}
> > +  (@var{value32} 32)
> > +  @var{value33}
> >@dots{}
> >@var{valuen}
> >  ])
> > @@ -11086,6 +11088,8 @@ in @file{insn-constants.h}:
> >  enum @var{name} @{
> >@var{value0} = 0,
> >@var{value1} = 1,
> > +  @var{value32} = 32,
> > +  @var{value33} = 33,
> >@dots{}
> >@var{valuen} = @var{n}
> >  @};
> > diff --git a/gcc/read-md.c b/gcc/read-md.c
> > index bb419e0f6..0fbe924d1 100644
> > --- a/gcc/read-md.c
> > +++ b/gcc/read-md.c
> > @@ -902,7 +902,8 @@ void
> >  md_reader::handle_enum (file_location loc, bool md_p)
> >  {
> >char *enum_name, *value_name;
> > -  struct md_name name;
> > +  unsigned int cur_value;
> > +  struct md_name name, value;
> >struct enum_type *def;
> >struct enum_value *ev;
> >void **slot;
> > @@ -928,6 +929,7 @@ md_reader::handle_enum (file_location loc, bool md_p)
> >*slot = def;
> >  }
> >
> > +  cur_value = def->num_values;
> >require_char_ws ('[');
> >
> >while ((c = read_skip_spaces ()) != ']')
> > @@ -937,8 +939,18 @@ md_reader::handle_enum (file_location loc, bool md_p)
> >   error_at (loc, "unterminated construct");
> >   exit (1);
> > }
> > -  unread_char (c);
> > -  read_name (&name);
> > +  if (c == '(')
> > +   {
> > + read_name (&name);
> > + read_name (&value);
> > + require_char_ws (')');
> > + cur_value = atoi(value.string);
>
> We really should be avoiding adding atoi.  Yes there are uses already

It is not user input value, as the value is from our souce code.

> in the source but https://gcc.gnu.org/PR44574 exists to track those
> uses.
>

Your problem is still exist:
 how big range should we support here, for define_enum?

> Thanks,
> Andrew
>
>
> > +   }
> > +  else
> > +   {
> > + unread_char (c);
> > + read_name (&name);
> > +   }
> >
> >ev = XNEW (struct enum_value);
> >ev->next = 0;
> > @@ -954,11 +966,12 @@ md_reader::handle_enum (file_location loc, bool md_p)
> >   ev->name = value_name;
> > }
> >ev->def = add_constant (get_md_constants (), value_name,
> > - md_decimal_string (def->num_values), def);
> > + md_decimal_string (cur_value), def);
> >
> >*def->tail_ptr = ev;
> >def->tail_ptr = &ev->next;
> >def->num_values++;
> > +  cur_value++;
> >  }
> >  }
> >
> > --
> > 2.30.2
> >

[PATCH v3] MIPS: add .module mipsREV/.set arch= to all output asm file

[YunQiang Su]

Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:

  assembler is mips1 by default,
  gcc is fpxx by default.

To assemble the output of gcc -S, we have to pass -mips2
to assembler.

The same situation is for some CPU has extension insn.
Octeon is an example.
So we can just add ".set arch=octeon".
---
 gcc/config/mips/mips.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 493d3de48..743a1d0fe 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9896,6 +9896,12 @@ mips_file_start (void)
   else
 fputs ("\t.module\tnooddspreg\n", asm_out_file);
 
+  if (!global_options_set.x_mips_arch_option
+  || startswith(mips_arch_info->name, "mips"))
+fprintf (asm_out_file, "\t.module\t%s\n", mips_arch_info->name);
+  else
+fprintf (asm_out_file, "\t.set\tarch=%s\n", mips_arch_info->name);
+
 #else
 #ifdef HAVE_AS_GNU_ATTRIBUTE
   {
-- 
2.30.2

Re: [PATCH v3] MIPS: add .module mipsREV/.set arch= to all output asm file

[YunQiang Su]

Maciej W. Rozycki  于2021年9月3日周五 上午9:48写道：
>
> On Thu, 2 Sep 2021, YunQiang Su wrote:
>
> > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> > index 493d3de48..743a1d0fe 100644
> > --- a/gcc/config/mips/mips.c
> > +++ b/gcc/config/mips/mips.c
> > @@ -9896,6 +9896,12 @@ mips_file_start (void)
> >else
> >  fputs ("\t.module\tnooddspreg\n", asm_out_file);
> >
> > +  if (!global_options_set.x_mips_arch_option
> > +  || startswith(mips_arch_info->name, "mips"))

here is a code style problem. I will fix it.

> > +fprintf (asm_out_file, "\t.module\t%s\n", mips_arch_info->name);
> > +  else
> > +fprintf (asm_out_file, "\t.set\tarch=%s\n", mips_arch_info->name);
>
>  Why not consistently `.module' for both legs?  And actually why not just
> `.module arch=...' in all cases?
>

Thanks for your advisor. I will have a try.
The reason is that I don't know this method.

>   Maciej

Re: [PATCH v3] MIPS: add .module mipsREV/.set arch= to all output asm file

[YunQiang Su]

YunQiang Su  于2021年9月3日周五 上午9:53写道：
>
> Maciej W. Rozycki  于2021年9月3日周五 上午9:48写道：
> >
> > On Thu, 2 Sep 2021, YunQiang Su wrote:
> >
> > > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> > > index 493d3de48..743a1d0fe 100644
> > > --- a/gcc/config/mips/mips.c
> > > +++ b/gcc/config/mips/mips.c
> > > @@ -9896,6 +9896,12 @@ mips_file_start (void)
> > >else
> > >  fputs ("\t.module\tnooddspreg\n", asm_out_file);
> > >
> > > +  if (!global_options_set.x_mips_arch_option
> > > +  || startswith(mips_arch_info->name, "mips"))
>
> here is a code style problem. I will fix it.
>
> > > +fprintf (asm_out_file, "\t.module\t%s\n", mips_arch_info->name);
> > > +  else
> > > +fprintf (asm_out_file, "\t.set\tarch=%s\n", mips_arch_info->name);
> >
> >  Why not consistently `.module' for both legs?  And actually why not just
> > `.module arch=...' in all cases?
> >
>
> Thanks for your advisor. I will have a try.

Ohh, it really works. w.
The testsuite is running.

> The reason is that I don't know this method.
>
> >   Maciej

[PATCH v4] MIPS: add .module arch and ase to all output asm

[YunQiang Su]

Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:

  assembler is mips1 by default,
  gcc is fpxx by default.

To assemble the output of gcc -S, we have to pass -mips2
to assembler.

The same situation is for some CPU has extension insn.
Octeon is an example.
So we can just add ".set arch=octeon".

If an ASE is enabled, .module ase will also be used.
---
 gcc/config/mips/mips.c | 37 +
 1 file changed, 37 insertions(+)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 493d3de48..ade5d7041 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9896,6 +9896,43 @@ mips_file_start (void)
   else
 fputs ("\t.module\tnooddspreg\n", asm_out_file);
 
+  fprintf (asm_out_file, "\t.module\tarch=%s\n", mips_arch_info->name);
+  /* FIXME: DSPR3 is not supported by GCC? gas does support it */
+  if (TARGET_DSPR2)
+fputs ("\t.module\tdspr2\n", asm_out_file);
+  else if (TARGET_DSP)
+fputs ("\t.module\tdsp\n", asm_out_file);
+  if (TARGET_EVA)
+fputs ("\t.module\teva\n", asm_out_file);
+  if (TARGET_MCU)
+fputs ("\t.module\tmcu\n", asm_out_file);
+  if (TARGET_MDMX)
+fputs ("\t.module\tmdmx\n", asm_out_file);
+  if (TARGET_MIPS3D)
+fputs ("\t.module\tmips3d\n", asm_out_file);
+  if (TARGET_MT)
+fputs ("\t.module\tmt\n", asm_out_file);
+  if (TARGET_SMARTMIPS)
+fputs ("\t.module\tsmartmips\n", asm_out_file);
+  if (TARGET_VIRT)
+fputs ("\t.module\tvirt\n", asm_out_file);
+  if (TARGET_MSA)
+fputs ("\t.module\tmsa\n", asm_out_file);
+  if (TARGET_XPA)
+fputs ("\t.module\txpa\n", asm_out_file);
+  /* FIXME: MIPS16E2 is not supported by GCC? gas does support it */
+  if (TARGET_CRC)
+fputs ("\t.module\tcrc\n", asm_out_file);
+  if (TARGET_GINV)
+fputs ("\t.module\tginv\n", asm_out_file);
+  if (TARGET_LOONGSON_MMI)
+fputs ("\t.module\tloongson-mmi\n", asm_out_file);
+  /* FIXME: LOONGSON-CAM is not supported by GCC? gas does support it */
+  if (TARGET_LOONGSON_EXT2)
+fputs ("\t.module\tloongson-ext2\n", asm_out_file);
+  else if (TARGET_LOONGSON_EXT)
+fputs ("\t.module\tloongson-ext\n", asm_out_file);
+
 #else
 #ifdef HAVE_AS_GNU_ATTRIBUTE
   {
-- 
2.30.2

Re: [RFC 1/7] Avoid references to register names in instruction output patterns.

[YunQiang Su]

Dragan Mladjenovic via Gcc-patches 
于2021年9月26日周日 下午9:26写道：
>
> This allows us to choose the different names if needed in the future.
>

I try to apply this patch to current gcc, I get this error:
/build/mips-mti-elf/srcs-gcc/gcc/testsuite/gcc.c-torture/compile/20010226-1.c:
In function 'foo':^M
/build/mips-mti-elf/srcs-gcc/gcc/testsuite/gcc.c-torture/compile/20010226-1.c:24:1:
internal compiler error: output_operand: invalid %-code^M
0xa435c4 output_operand_lossage(char const*, ...)^M
../../srcs-gcc/gcc/final.c:3235^M
0xa43ec6 output_asm_insn(char const*, rtx_def**)^M
../../srcs-gcc/gcc/final.c:3604^M
0xa482c7 output_asm_insn(char const*, rtx_def**)^M
../../srcs-gcc/gcc/final.c:3466^M
0xa482c7 final_scan_insn_1^M
../../srcs-gcc/gcc/final.c:2894^M
0xa485bb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)^M
../../srcs-gcc/gcc/final.c:2940^M
0xa486a6 final_1^M
../../srcs-gcc/gcc/final.c:1997^M
0xa49262 rest_of_handle_final^M
../../srcs-gcc/gcc/final.c:4285^M
0xa49262 execute^M
../../srcs-gcc/gcc/final.c:4363^M
Please submit a full bug report,^M
with preprocessed source if appropriate.^M
Please include the complete backtrace with any bug report.^M
See  for instructions.^M
compiler exited with status 1

> gcc/ChangeLog:
>
> * config/mips/mips.c (mips_print_operand_punctuation):
> Handle '&' punctuation.
> (mips_output_probe_stack_range): Use '%.' instead of $0.
> * config/mips/mips.h (GLOBAL_POINTER_REGNUM): Move to ...
> * config/mips/mips.md (GLOBAL_POINTER_REGNUM): ... here.
> (trap, *conditional_trap_reg, *msac, *muls,
> *muls_di, msubsidi4): Use '%.' instead of $0.
> (clear_hazard_): Use '%&' instead of $31.
> ---
>  gcc/config/mips/mips.c  |  9 +++--
>  gcc/config/mips/mips.h  |  4 
>  gcc/config/mips/mips.md | 17 +
>  3 files changed, 16 insertions(+), 14 deletions(-)
>  3 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index ce60c5500b7..ab63575eb26 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -8816,6 +8816,7 @@ mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
> '^' Print the name of the pic call-through register (t9 or $25).
> '+' Print the name of the gp register (usually gp or $28).
> '$' Print the name of the stack pointer register (sp or $29).
> +   '&' Print the name of the return register (ra or $31).
> ':'  Print "c" to use the compact version if the delay slot is a nop.
> '!'  Print "s" to use the short version if the delay slot contains a
> 16-bit instruction.
> @@ -8902,6 +8903,10 @@ mips_print_operand_punctuation (FILE *file, int ch)
>fputs (reg_names[STACK_POINTER_REGNUM], file);
>break;
>
> +case '&':
> +  fputs (reg_names[RETURN_ADDR_REGNUM], file);
> +  break;
> +
>  case ':':
>/* When final_sequence is 0, the delay slot will be a nop.  We can
>  use the compact version where available.  The %: formatter will
> @@ -12133,9 +12138,9 @@ mips_output_probe_stack_range (rtx reg1, rtx reg2)
>strcpy (tmp, "%(%output_asm_insn (strcat (tmp, &loop_lab[1]), xops);
>if (TARGET_64BIT)
> -output_asm_insn ("sd\t$0,0(%0)%)", xops);
> +output_asm_insn ("sd\t%.,0(%0)%)", xops);
>else
> -output_asm_insn ("sw\t$0,0(%0)%)", xops);
> +output_asm_insn ("sw\t%.,0(%0)%)", xops);
>

I guess the problem is due to this.

>return "";
>  }
> diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
> index f4e30ba3fdb..a44ccada0bc 100644
> --- a/gcc/config/mips/mips.h
> +++ b/gcc/config/mips/mips.h
> @@ -2064,10 +2064,6 @@ FP_ASM_SPEC "\
> function address than to call an address kept in a register.  */
>  #define NO_FUNCTION_CSE 1
>
> -/* The ABI-defined global pointer.  Sometimes we use a different
> -   register in leaf functions: see PIC_OFFSET_TABLE_REGNUM.  */
> -#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
> -
>  /* We normally use $28 as the global pointer.  However, when generating
> n32/64 PIC, it is better for leaf functions to use a call-clobbered
> register instead.  They can then avoid saving and restoring $28
> diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
> index dee71dc1fb0..1c8b3b98b20 100644
> --- a/gcc/config/mips/mips.md
> +++ b/gcc/config/mips/mips.md
> @@ -167,6 +167,7 @@
> (GET_FCSR_REGNUM2)
> (SET_FCSR_REGNUM4)
> (PIC_FUNCTION_ADDR_REGNUM   25)
> +   (GLOBAL_POINTER_REGNUM  28)
> (RETURN_ADDR_REGNUM 31)
> (CPRESTORE_SLOT_REGNUM  76)
> (GOT_VERSION_REGNUM 79)
> @@ -1205,7 +1206,7 @@
>""
>  {
>if (ISA_HAS_COND_TRAP)
> -return "teq\t$0,$0";
> +return "teq\t%.,%.";
>else if (TARGET_MIPS16)
>  return "break 0";
>else
> @@ -1230,7 +1231,7 @@
>   

[PATCH v3] MIPS: R6: load/store can process unaligned address

[YunQiang Su]

MIPS release 6 requires the lw/ld/sw/sd can work with
unaligned address, while it can be implemented by
full hardware or trap&emulate.

Since it doesn't have to be fully done by hardware, we add a
pair of options -m(no-)unaligned-access. Kernels may need them.

gcc/ChangeLog:

* config/mips/mips.h (ISA_HAS_UNALIGNED_ACCESS):
(STRICT_ALIGNMENT): R6 can unaligned access.
* config/mips/mips.md (movmisalign): Likewise.
* config/mips/mips.opt: add -m(no-)unaligned-access
* doc/invoke.texi: Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/mips/mips.exp: add unaligned-access
* gcc.target/mips/unaligned-2.c: New test.
* gcc.target/mips/unaligned-3.c: New test.
---
 gcc/config/mips/mips.h  |  6 ++-
 gcc/config/mips/mips.md | 10 
 gcc/config/mips/mips.opt|  4 ++
 gcc/doc/invoke.texi | 10 
 gcc/testsuite/gcc.target/mips/mips.exp  |  1 +
 gcc/testsuite/gcc.target/mips/unaligned-2.c | 53 +
 gcc/testsuite/gcc.target/mips/unaligned-3.c | 53 +
 7 files changed, 136 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/unaligned-2.c
 create mode 100644 gcc/testsuite/gcc.target/mips/unaligned-3.c

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 973372e78..34490bfc2 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -243,6 +243,10 @@ struct mips_cpu_info {
 && (mips_isa_rev >= 6 \
 || ISA_HAS_MSA))
 
+/* ISA load/store instructions can handle unaligned address */
+#define ISA_HAS_UNALIGNED_ACCESS (TARGET_UNALIGNED_ACCESS \
+&& (mips_isa_rev >= 6))
+
 /* The ISA compression flags that are currently in effect.  */
 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
 
@@ -1684,7 +1688,7 @@ FP_ASM_SPEC "\
   (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE)
 
 /* All accesses must be aligned.  */
-#define STRICT_ALIGNMENT 1
+#define STRICT_ALIGNMENT (!ISA_HAS_UNALIGNED_ACCESS)
 
 /* Define this if you wish to imitate the way many other C compilers
handle alignment of bitfields and the structures that contain
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 455b9b802..e35d57d9e 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4459,6 +4459,16 @@ (define_insn "mov_r"
   [(set_attr "move_type" "store")
(set_attr "mode" "")])
 
+;; Unaligned direct access
+(define_expand "movmisalign"
+  [(set (match_operand:JOIN_MODE 0)
+   (match_operand:JOIN_MODE 1))]
+  "ISA_HAS_UNALIGNED_ACCESS"
+{
+  if (mips_legitimize_move (mode, operands[0], operands[1]))
+DONE;
+})
+
 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
 ;; The required value is:
 ;;
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 6af8037e9..ebb4c6164 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -404,6 +404,10 @@ mtune=
 Target RejectNegative Joined Var(mips_tune_option) ToLower 
Enum(mips_arch_opt_value)
 -mtune=PROCESSOR   Optimize the output for PROCESSOR.
 
+munaligned-access
+Target Var(TARGET_UNALIGNED_ACCESS) Init(1)
+Generate code with unaligned load store, valid for MIPS R6.
+
 muninit-const-in-rodata
 Target Var(TARGET_UNINIT_CONST_IN_RODATA)
 Put uninitialized constants in ROM (needs -membedded-data).
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8b3ebcfbc..ffb1f4676 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1069,6 +1069,7 @@ Objective-C and Objective-C++ Dialects}.
 -mcheck-zero-division  -mno-check-zero-division @gol
 -mdivide-traps  -mdivide-breaks @gol
 -mload-store-pairs  -mno-load-store-pairs @gol
+-munaligned-access  -mno-unaligned-access @gol
 -mmemcpy  -mno-memcpy  -mlong-calls  -mno-long-calls @gol
 -mmad  -mno-mad  -mimadd  -mno-imadd  -mfused-madd  -mno-fused-madd  -nocpp 
@gol
 -mfix-24k  -mno-fix-24k @gol
@@ -25503,6 +25504,15 @@ instructions to enable load/store bonding.  This 
option is enabled by
 default but only takes effect when the selected architecture is known
 to support bonding.
 
+@item -munaligned-access
+@itemx -mno-unaligned-access
+@opindex munaligned-access
+@opindex mno-unaligned-access
+Enable (disable) direct unaligned access for MIPS Release 6.
+MIPSr6 requires load/store unaligned-access support,
+by hardware or trap&emulate.
+So @option{-mno-unaligned-access} may be needed by kernel.
+
 @item -mmemcpy
 @itemx -mno-memcpy
 @opindex mmemcpy
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp 
b/gcc/testsuite/gcc.target/mips/mips.exp
index d4d4b90d8..f76ab7adc 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -264,6 +264,7 @@ set mips_option_groups {
 frame-header "-mframe-header-opt|-mno-frame-header-opt"
 stack-protecto

[PATCH v5 1/2] MIPS: Not trigger error for pre-R6 and -mcompact-branches=always

[YunQiang Su]

For MIPSr6, we may wish to use compact-branches only.
Currently, we have to use `always' option, while it is mark as conflict
with pre-R6.
  cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always
Just ignore -mcompact-branches=always for pre-R6.

This patch also defines
__mips_compact_branches_never
__mips_compact_branches_always
__mips_compact_branches_optimal
predefined macros

gcc/ChangeLog:
* config/mips/mips.c (mips_option_override):
* config/mips/mips.h (TARGET_RTP_PIC): not trigger error for
compact-branches=always for pre-R6.
(TARGET_CB_NEVER): Likewise.
(TARGET_CB_ALWAYS): Likewise.
(struct mips_cpu_info): define macros for compact branch policy.
* doc/invoke.texi: Document "always" with pre-R6.

gcc/testsuite/ChangeLog:
* gcc.target/mips/compact-branches-1.c: add isa_rev>=6.
* gcc.target/mips/mips.exp: don't add -mipsXXr6 option for
-mcompact-branches=always. It is usable for pre-R6 now.
* gcc.target/mips/compact-branches-8.c: New test.
* gcc.target/mips/compact-branches-9.c: New test.
---
 gcc/config/mips/mips.c|  8 +--
 gcc/config/mips/mips.h| 22 ---
 gcc/doc/invoke.texi   | 10 +
 .../gcc.target/mips/compact-branches-1.c  |  2 +-
 .../gcc.target/mips/compact-branches-8.c  | 10 +
 .../gcc.target/mips/compact-branches-9.c  | 10 +
 gcc/testsuite/gcc.target/mips/mips.exp|  4 +---
 7 files changed, 43 insertions(+), 23 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-8.c
 create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-9.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 315545966f8..805ba8240e0 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -20107,13 +20107,7 @@ mips_option_override (void)
   target_flags |= MASK_ODD_SPREG;
 }
 
-  if (!ISA_HAS_COMPACT_BRANCHES && mips_cb == MIPS_CB_ALWAYS)
-{
-  error ("unsupported combination: %qs%s %s",
- mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
- "-mcompact-branches=always");
-}
-  else if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
+  if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
 {
   error ("unsupported combination: %qs%s %s",
  mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 47aac9d3d61..d845813f102 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -103,11 +103,9 @@ struct mips_cpu_info {
 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
 
 /* Compact branches must not be used if the user either selects the
-   'never' policy or the 'optimal' policy on a core that lacks
+   'never' policy or the 'optimal' / 'always' policy on a core that lacks
compact branch instructions.  */
-#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER  \
-|| (mips_cb == MIPS_CB_OPTIMAL \
-&& !ISA_HAS_COMPACT_BRANCHES))
+#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER || !ISA_HAS_COMPACT_BRANCHES)
 
 /* Compact branches may be used if the user either selects the
'always' policy or the 'optimal' policy on a core that supports
@@ -117,10 +115,11 @@ struct mips_cpu_info {
 && ISA_HAS_COMPACT_BRANCHES))
 
 /* Compact branches must always be generated if the user selects
-   the 'always' policy or the 'optimal' policy om a core that
-   lacks delay slot branch instructions.  */
-#define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS\
-|| (mips_cb == MIPS_CB_OPTIMAL \
+   the 'always' policy on a core support compact branches,
+   or the 'optimal' policy on a core that lacks delay slot branch 
instructions.  */
+#define TARGET_CB_ALWAYS ((mips_cb == MIPS_CB_ALWAYS \
+&& ISA_HAS_COMPACT_BRANCHES) \
+|| (mips_cb == MIPS_CB_OPTIMAL   \
 && !ISA_HAS_DELAY_SLOTS))
 
 /* Special handling for JRC that exists in microMIPSR3 as well as R6
@@ -655,6 +654,13 @@ struct mips_cpu_info {
builtin_define ("__mips_no_lxc1_sxc1"); \
   if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4)  \
builtin_define ("__mips_no_madd4"); \
+   \
+  if (TARGET_CB_NEVER) \
+   builtin_define ("__mips_compact_branches_never");   \
+  else if (TARGET_CB_ALWAYS)   \
+   builtin_define ("__mips_compact_branches_always");  \
+  else \
+   builtin_d

[PATCH v5 2/2] MIPS: add builtime option for -mcompact-branches

[YunQiang Su]

For R6+ target, it allows to configure gcc to use compact branches only
if avaiable.

gcc/ChangeLog:
* config.gcc: add -with-compact-branches=policy build option.
* doc/install.texi: Likewise.
* config/mips/mips.h: Likewise.
---
 gcc/config.gcc | 13 +++--
 gcc/config/mips/mips.h |  3 ++-
 gcc/doc/install.texi   | 19 +++
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 92fad8e20ca..ac411f66de2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4724,7 +4724,7 @@ case "${target}" in
;;
 
mips*-*-*)
-   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4"
+   supported_defaults="abi arch arch_32 arch_64 float fpu nan 
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 
madd4 compact-branches"
 
case ${with_float} in
"" | soft | hard)
@@ -4877,6 +4877,15 @@ case "${target}" in
exit 1
;;
esac
+
+   case ${with_compact_branches} in
+   "" | never | always | optimal)
+   ;;
+   *)
+   echo "Unknown compact-branches policy used in 
--with-compact-branches" 1>&2
+   exit 1
+   ;;
+   esac
;;
 
nds32*-*-*)
@@ -5389,7 +5398,7 @@ case ${target} in
 esac
 
 t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 
schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls 
lxc1-sxc1 madd4"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 
schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls 
lxc1-sxc1 madd4 compact-branches"
 for option in $all_defaults
 do
eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index d845813f102..64d7a66f8b6 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -897,7 +897,8 @@ struct mips_cpu_info {
   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
   {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" },   \
   {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
-  {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
+  {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" }, \
+  {"compact-branches", "%{!mcompact-branches=*:-mcompact-branches=%(VALUE)}" } 
\
 
 /* A spec that infers the:
-mnan=2008 setting from a -mips argument,
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index d2cab15d9fd..b9980186ed3 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1464,6 +1464,25 @@ systems that support conditional traps).
 Division by zero checks use the break instruction.
 @end table
 
+@item --with-compact-branches=@var{policy}
+Specify how the compiler should generate branch instructions.
+This option is only supported on the MIPS target.
+The possibilities for @var{type} are:
+@table @code
+@item optimal
+Cause a delay slot branch to be used if one is available in the
+current ISA and the delay slot is successfully filled. If the delay slot
+is not filled, a compact branch will be chosen if one is available.
+@item never
+Ensures that compact branch instructions will never be generated.
+@item always
+Ensures that a compact branch instruction will be generated if available.
+If a compact branch instruction is not available,
+a delay slot form of the branch will be used instead.
+This option is supported from MIPS Release 6 onwards.
+For pre-R6/microMIPS/MIPS16, this option is just same as never/optimal.
+@end table
+
 @c If you make --with-llsc the default for additional targets,
 @c update the --with-llsc description in the MIPS section below.
 
-- 
2.30.2

[PATCH v2] MIPS: R6: load/store can process unaligned address

[YunQiang Su]

MIPS release 6 requires the lw/ld/sw/sd can work with
unaligned address, while it can be implemented by
full hardware or trap&emulate.

Since it is may be fully done by hardware, we add an
option -m(no-)unaligned-access, the kernel may need it.

gcc/ChangeLog:

* config/mips/mips.h (ISA_HAS_UNALIGNED_ACCESS):
(STRICT_ALIGNMENT): R6 can unaligned access.
* config/mips/mips.md (movmisalign): Likewise.
* config/mips/mips.opt: add -m(no-)unaligned-access
* doc/invoke.texi: Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/mips/mips.exp: add unaligned-access
* gcc.target/mips/unaligned-2.c: New test.
* gcc.target/mips/unaligned-3.c: New test.
---
 gcc/config/mips/mips.h  |  6 ++-
 gcc/config/mips/mips.md | 10 
 gcc/config/mips/mips.opt|  4 ++
 gcc/doc/invoke.texi | 10 
 gcc/testsuite/gcc.target/mips/mips.exp  |  1 +
 gcc/testsuite/gcc.target/mips/unaligned-2.c | 53 +
 gcc/testsuite/gcc.target/mips/unaligned-3.c | 53 +
 7 files changed, 136 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/unaligned-2.c
 create mode 100644 gcc/testsuite/gcc.target/mips/unaligned-3.c

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 47aac9d3d61..22a0d449aab 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -226,6 +226,10 @@ struct mips_cpu_info {
 && (mips_isa_rev >= 6 \
 || ISA_HAS_MSA))
 
+/* ISA load/store instructions can handle unaligned address */
+#define ISA_HAS_UNALIGNED_ACCESS (TARGET_UNALIGNED_ACCESS \
+&& (mips_isa_rev >= 6))
+
 /* The ISA compression flags that are currently in effect.  */
 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
 
@@ -1666,7 +1670,7 @@ FP_ASM_SPEC "\
   (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE)
 
 /* All accesses must be aligned.  */
-#define STRICT_ALIGNMENT 1
+#define STRICT_ALIGNMENT (!ISA_HAS_UNALIGNED_ACCESS)
 
 /* Define this if you wish to imitate the way many other C compilers
handle alignment of bitfields and the structures that contain
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index eef3cfd50a8..40e29c60432 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4459,6 +4459,16 @@ (define_insn "mov_r"
   [(set_attr "move_type" "store")
(set_attr "mode" "")])
 
+;; Unaligned direct access
+(define_expand "movmisalign"
+  [(set (match_operand:JOIN_MODE 0)
+   (match_operand:JOIN_MODE 1))]
+  "ISA_HAS_UNALIGNED_ACCESS"
+{
+  if (mips_legitimize_move (mode, operands[0], operands[1]))
+DONE;
+})
+
 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
 ;; The required value is:
 ;;
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 6af8037e9bd..ebb4c616401 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -404,6 +404,10 @@ mtune=
 Target RejectNegative Joined Var(mips_tune_option) ToLower 
Enum(mips_arch_opt_value)
 -mtune=PROCESSOR   Optimize the output for PROCESSOR.
 
+munaligned-access
+Target Var(TARGET_UNALIGNED_ACCESS) Init(1)
+Generate code with unaligned load store, valid for MIPS R6.
+
 muninit-const-in-rodata
 Target Var(TARGET_UNINIT_CONST_IN_RODATA)
 Put uninitialized constants in ROM (needs -membedded-data).
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 40cacc6f8e7..211a709fff8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1062,6 +1062,7 @@ Objective-C and Objective-C++ Dialects}.
 -mcheck-zero-division  -mno-check-zero-division @gol
 -mdivide-traps  -mdivide-breaks @gol
 -mload-store-pairs  -mno-load-store-pairs @gol
+-munaligned-access  -mno-unaligned-access @gol
 -mmemcpy  -mno-memcpy  -mlong-calls  -mno-long-calls @gol
 -mmad  -mno-mad  -mimadd  -mno-imadd  -mfused-madd  -mno-fused-madd  -nocpp 
@gol
 -mfix-24k  -mno-fix-24k @gol
@@ -24999,6 +25000,15 @@ instructions to enable load/store bonding.  This 
option is enabled by
 default but only takes effect when the selected architecture is known
 to support bonding.
 
+@item -munaligned-access
+@itemx -mno-unaligned-access
+@opindex munaligned-access
+@opindex mno-unaligned-access
+Enable (disable) direct unaligned access for MIPS Release 6.
+MIPSr6 requires load/store unaligned-access support,
+by hardware or trap&emulate. 
+So @option{-mno-unaligned-access} may be needed by kernel.
+
 @item -mmemcpy
 @itemx -mno-memcpy
 @opindex mmemcpy
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp 
b/gcc/testsuite/gcc.target/mips/mips.exp
index 01292316944..cb1ee7d71b5 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -264,6 +264,7 @@ set mips_option_groups {
 frame-header "-mframe-header-opt|-mno-frame-header-opt"
 stack-pro

[commit] MIPS: Add -m(no-)strict-align option

[YunQiang Su]

We support options -m(no-)unaligned-access 2 years ago, while
currently most of other ports prefer -m(no-)strict-align.
Let's support -m(no-)strict-align, and keep -m(no-)unaligned-access
as alias.

gcc
* config/mips/mips.opt: Support -mstrict-align, and use
TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
as alias.
* config/mips/mips.h: Use TARGET_STRICT_ALIGN.
* config/mips/mips.opt.urls: Regenerate.
* doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
---
 gcc/config/mips/mips.h|  2 +-
 gcc/config/mips/mips.opt  | 12 ++--
 gcc/config/mips/mips.opt.urls |  6 ++
 gcc/doc/invoke.texi   | 18 --
 4 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 7145d23c650..6444a68dfd5 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -251,7 +251,7 @@ struct mips_cpu_info {
 || ISA_HAS_MSA))
 
 /* ISA load/store instructions can handle unaligned address */
-#define ISA_HAS_UNALIGNED_ACCESS (TARGET_UNALIGNED_ACCESS \
+#define ISA_HAS_UNALIGNED_ACCESS (!TARGET_STRICT_ALIGN \
 && (mips_isa_rev >= 6))
 
 /* The ISA compression flags that are currently in effect.  */
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index ce36942aabe..c1abb36212f 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -429,9 +429,17 @@ mtune=
 Target RejectNegative Joined Var(mips_tune_option) ToLower 
Enum(mips_arch_opt_value)
 -mtune=PROCESSOR   Optimize the output for PROCESSOR.
 
+mstrict-align
+Target Var(TARGET_STRICT_ALIGN) Init(0)
+Don't generate code with unaligned load store, only valid for MIPS R6.
+
 munaligned-access
-Target Var(TARGET_UNALIGNED_ACCESS) Init(1)
-Generate code with unaligned load store, valid for MIPS R6.
+Target RejectNegative Alias(mstrict-align) NegativeAlias
+Generate code with unaligned load store for R6 (alias of -mno-strict-align).
+
+mno-unaligned-access
+Target RejectNegative Alias(mstrict-align)
+Don't generate code with unaligned load store for R6 (alias of -mstrict-align).
 
 muninit-const-in-rodata
 Target Var(TARGET_UNINIT_CONST_IN_RODATA)
diff --git a/gcc/config/mips/mips.opt.urls b/gcc/config/mips/mips.opt.urls
index 96aba041026..9d166646d65 100644
--- a/gcc/config/mips/mips.opt.urls
+++ b/gcc/config/mips/mips.opt.urls
@@ -233,9 +233,15 @@ UrlSuffix(gcc/MIPS-Options.html#index-mmadd4)
 mtune=
 UrlSuffix(gcc/MIPS-Options.html#index-mtune-10)
 
+mstrict-align
+UrlSuffix(gcc/MIPS-Options.html#index-mstrict-align-3)
+
 munaligned-access
 UrlSuffix(gcc/MIPS-Options.html#index-munaligned-access-1)
 
+mno-unaligned-access
+UrlSuffix(gcc/MIPS-Options.html#index-mno-unaligned-access-1)
+
 muninit-const-in-rodata
 UrlSuffix(gcc/MIPS-Options.html#index-muninit-const-in-rodata)
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 85c938d4a14..864768fd2f4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1143,7 +1143,8 @@ Objective-C and Objective-C++ Dialects}.
 -mcheck-zero-division  -mno-check-zero-division
 -mdivide-traps  -mdivide-breaks
 -mload-store-pairs  -mno-load-store-pairs
--munaligned-access  -mno-unaligned-access
+-mstrict-align  -mno-strict-align
+-mno-unaligned-access  -munaligned-access
 -mmemcpy  -mno-memcpy  -mlong-calls  -mno-long-calls
 -mmad  -mno-mad  -mimadd  -mno-imadd  -mfused-madd  -mno-fused-madd  -nocpp
 -mfix-24k  -mno-fix-24k
@@ -28561,14 +28562,19 @@ instructions to enable load/store bonding.  This 
option is enabled by
 default but only takes effect when the selected architecture is known
 to support bonding.
 
+@opindex mstrict-align
+@opindex mno-strict-align
 @opindex munaligned-access
 @opindex mno-unaligned-access
-@item -munaligned-access
+@item -mstrict-align
+@itemx -mno-strict-align
+@itemx -munaligned-access
 @itemx -mno-unaligned-access
-Enable (disable) direct unaligned access for MIPS Release 6.
-MIPSr6 requires load/store unaligned-access support,
-by hardware or trap&emulate.
-So @option{-mno-unaligned-access} may be needed by kernel.
+Disable (enable) direct unaligned access for MIPS Release 6.
+MIPSr6 requires load/store unaligned-access support, by hardware or
+trap&emulate.  So @option{-mstrict-align} may be needed by kernel.  The
+options @option{-munaligned-access} and @option{-mno-unaligned-access}
+are obsoleted, and only for backward-compatible.
 
 @opindex mmemcpy
 @opindex mno-memcpy
-- 
2.39.2

Re: CI for "Option handling: add documentation URLs"

[YunQiang Su]

Great work. The CI works well now: it blames me ;)
https://builder.sourceware.org/buildbot/#/builders/269/builds/3846

When I add '-mstrict-align' option to MIPS,
the riscv.opt.urls, sysv4.opt.urls, xtensa.opt.urls are changed also.
(why they are effected?

So what's the best practice for this cases?
Should I push a new commit? Or in fact a single commit is preferred?

-- 
YunQiang Su

[commit] Regenerate opt.urls

[YunQiang Su]

Fixes: acc38ff59976 ("MIPS: Add -m(no-)strict-align option")

gcc/ChangeLog:

* config/riscv/riscv.opt.urls: Regenerated.
* config/rs6000/sysv4.opt.urls: Likewise.
* config/xtensa/xtensa.opt.urls: Likewise.
---
 gcc/config/riscv/riscv.opt.urls   | 2 +-
 gcc/config/rs6000/sysv4.opt.urls  | 2 +-
 gcc/config/xtensa/xtensa.opt.urls | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv.opt.urls b/gcc/config/riscv/riscv.opt.urls
index f40795866cf..da31820e234 100644
--- a/gcc/config/riscv/riscv.opt.urls
+++ b/gcc/config/riscv/riscv.opt.urls
@@ -44,7 +44,7 @@ UrlSuffix(gcc/RISC-V-Options.html#index-mshorten-memrefs)
 ; skipping UrlSuffix for 'mcmodel=' due to finding no URLs
 
 mstrict-align
-UrlSuffix(gcc/RISC-V-Options.html#index-mstrict-align-3)
+UrlSuffix(gcc/RISC-V-Options.html#index-mstrict-align-4)
 
 ; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs
 
diff --git a/gcc/config/rs6000/sysv4.opt.urls b/gcc/config/rs6000/sysv4.opt.urls
index f8d58d6602c..c155cddfa36 100644
--- a/gcc/config/rs6000/sysv4.opt.urls
+++ b/gcc/config/rs6000/sysv4.opt.urls
@@ -12,7 +12,7 @@ mbit-align
 UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mbit-align)
 
 mstrict-align
-UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mstrict-align-4)
+UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mstrict-align-5)
 
 mrelocatable
 UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mrelocatable)
diff --git a/gcc/config/xtensa/xtensa.opt.urls 
b/gcc/config/xtensa/xtensa.opt.urls
index 146db23d1e3..1f193a7da0c 100644
--- a/gcc/config/xtensa/xtensa.opt.urls
+++ b/gcc/config/xtensa/xtensa.opt.urls
@@ -33,5 +33,5 @@ mabi=windowed
 UrlSuffix(gcc/Xtensa-Options.html#index-mabi_003dwindowed)
 
 mstrict-align
-UrlSuffix(gcc/Xtensa-Options.html#index-mstrict-align-5)
+UrlSuffix(gcc/Xtensa-Options.html#index-mstrict-align-6)
 
-- 
2.39.2

[PATCH] Predefine __STRICT_ALIGN__ if STRICT_ALIGNMENT

[YunQiang Su]

Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
and RISC-V predefines __riscv_misaligned_avoid, while other ports
that support -mstrict-align/-mno-unaligned-access don't have such
macro, and these backend macros are only avaiable for c-family.
Note: Arm64 always predefine __ARM_FEATURE_UNALIGNED: See #111555.

Let's add a generic one.

__STRICT_ALIGN__ is used instead of __STRICT_ALIGNMENT__, due to that
the later is used by some softwares, such as lzo2, syslinux etc.

gcc
* cppbuiltin.cc: Predefine __STRICT_ALIGNMENT__ if
STRICT_ALIGNMENT.
---
 gcc/cppbuiltin.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/cppbuiltin.cc b/gcc/cppbuiltin.cc
index c4bfc2917dc..d32efdf9a07 100644
--- a/gcc/cppbuiltin.cc
+++ b/gcc/cppbuiltin.cc
@@ -123,6 +123,9 @@ define_builtin_macros_for_compilation_flags (cpp_reader 
*pfile)
 
   cpp_define_formatted (pfile, "__FINITE_MATH_ONLY__=%d",
flag_finite_math_only);
+
+  if (STRICT_ALIGNMENT)
+cpp_define (pfile, "__STRICT_ALIGNMENT__");
 }
 
 
-- 
2.39.2

Re: [PATCH] Predefine __STRICT_ALIGN__ if STRICT_ALIGNMENT

[YunQiang Su]

Sam James  于2024年3月17日周日 14:04写道：
>
> YunQiang Su  writes:
>
> > Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
> > and RISC-V predefines __riscv_misaligned_avoid, while other ports
> > that support -mstrict-align/-mno-unaligned-access don't have such
> > macro, and these backend macros are only avaiable for c-family.
> > Note: Arm64 always predefine __ARM_FEATURE_UNALIGNED: See #111555.
>
> I would say tag the bug even if you're not fixing it, as it was related
> enough for you to cite it.
>

I am not sure that it is a bug for aarch64. This macro may be used to
determine whether hardware can support misaligned access, and
maybe all of Aarch64 CPUs can support it.

It should be determined by ARM people.

[PATCH] MIPS: Predefine __mips_strict_alignment if STRICT_ALIGNMENT

[YunQiang Su]

Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
and RISC-V predefines __riscv_misaligned_avoid.

Let's define __mips_strict_alignment for MIPSr6 and -mstrict-align
is used.

Not that, this macro is always defined for pre-R6.

gcc
config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Predefine
__mips_strict_alignment if STRICT_ALIGNMENT.
---
 gcc/config/mips/mips.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 6444a68dfd5..616a275b918 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -694,6 +694,9 @@ struct mips_cpu_info {
builtin_define ("__mips_compact_branches_always");  \
   else \
builtin_define ("__mips_compact_branches_optimal"); \
+   \
+  if (STRICT_ALIGNMENT)\
+   builtin_define ("__mips_strict_alignment"); \
 }  \
   while (0)
 
-- 
2.39.2

Re: [PATCH v2] MIPS: Add MIN/MAX.fmt instructions support for MIPS R6

[YunQiang Su]

Jie Mei  于2024年3月25日周一 17:46写道：
>
> This patch adds the smin/smax RTL mode for the
> min/max.fmt instructions.
>
> Also, since the min/max.fmt instrucions applies to the
> IEEE 754-2008 "minNum" and "maxNum" operations, this
> patch also provides the new "fmin3" and
> "fmax3" modes.
>
> gcc/ChangeLog:
>
> * config/mips/i6400.md (i6400_fpu_minmax): New
> define_insn_reservation.
> * config/mips/mips.h (ISA_HAS_FMIN_FMAX): Define new macro.
> * config/mips/mips.md (UNSPEC_FMIN): New unspec.
> (UNSPEC_FMAX): Same as above.
> (type): Add fminmax.
> (smin3): Generates MIN.fmt instructions.
> (smax3): Generates MAX.fmt instructions.
> (fmin3): Generates MIN.fmt instructions.
> (fmax3): Generates MAX.fmt instructions.
> * config/mips/p6600.md (p6600_fpu_fabs): Include fminmax
> type.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/mips/mips-minmax.c: New test for MIPS R6.
> ---
>  gcc/config/mips/i6400.md|  6 +++
>  gcc/config/mips/mips.h  |  2 +
>  gcc/config/mips/mips.md | 50 -
>  gcc/config/mips/p6600.md|  2 +-
>  gcc/testsuite/gcc.target/mips/mips-minmax.c | 40 +
>  5 files changed, 97 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/mips/mips-minmax.c
>
> diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md
> index 9f216fe0210..d6f691ee217 100644
> --- a/gcc/config/mips/i6400.md
> +++ b/gcc/config/mips/i6400.md
> @@ -219,6 +219,12 @@
> (eq_attr "type" "fabs,fneg,fmove"))
>"i6400_fpu_short, i6400_fpu_apu")
>
> +;; min, max
> +(define_insn_reservation "i6400_fpu_minmax" 2
> +  (and (eq_attr "cpu" "i6400")
> +   (eq_attr "type" "fminmax"))
> +  "i6400_fpu_short+i6400_fpu_logic")
> +
>  ;; fadd, fsub, fcvt
>  (define_insn_reservation "i6400_fpu_fadd" 4
>(and (eq_attr "cpu" "i6400")
> diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
> index 7145d23c650..5ce984ac99b 100644
> --- a/gcc/config/mips/mips.h
> +++ b/gcc/config/mips/mips.h
> @@ -1259,6 +1259,8 @@ struct mips_cpu_info {
>  #define ISA_HAS_9BIT_DISPLACEMENT  (mips_isa_rev >= 6  \
>  || ISA_HAS_MIPS16E2)
>
> +#define ISA_HAS_FMIN_FMAX  (mips_isa_rev >= 6)
> +
>  /* ISA has data indexed prefetch instructions.  This controls use of
> 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
> (prefx is a cop1x instruction, so can only be used if FP is
> diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
> index b0fb5850a9e..26f758c90dd 100644
> --- a/gcc/config/mips/mips.md
> +++ b/gcc/config/mips/mips.md
> @@ -97,6 +97,10 @@
>UNSPEC_GET_FCSR
>UNSPEC_SET_FCSR
>
> +  ;; Floating-point unspecs.
> +  UNSPEC_FMIN
> +  UNSPEC_FMAX
> +
>;; HI/LO moves.
>UNSPEC_MFHI
>UNSPEC_MTHI
> @@ -370,6 +374,7 @@
>  ;; frsqrt   floating point reciprocal square root
>  ;; frsqrt1  floating point reciprocal square root step1
>  ;; frsqrt2  floating point reciprocal square root step2
> +;; fminmax  floating point min/max
>  ;; dspmac   DSP MAC instructions not saturating the accumulator
>  ;; dspmacsatDSP MAC instructions that saturate the accumulator
>  ;; accext   DSP accumulator extract instructions
> @@ -387,8 +392,8 @@
> 
> prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
> shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
> fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
> -   frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
> -   multi,atomic,syncloop,nop,ghost,multimem,
> +   frsqrt,frsqrt1,frsqrt2,fminmax,dspmac,dspmacsat,accext,accmod,dspalu,
> +   dspalusat,multi,atomic,syncloop,nop,ghost,multimem,
> simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd,
> simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp,
> simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill,
> @@ -7971,6 +7976,47 @@
>[(set_attr "move_type" "load")
> (set_attr "insn_count" "2")])
>
> +;;
> +;;  Float point MIN/MAX
> +;;
> +
> +(define_insn "smin3"
> +  [(set (match_operand:SCALARF 0 "register_operand" "=f")
> +   (smin:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
> + (match_operand:SCALARF 2 "register_operand" "f")))]
> +  "ISA_HAS_FMIN_FMAX"
> +  "min.\t%0,%1,%2"
> +  [(set_attr "type" "fminmax")
> +   (set_attr "mode" "")])
> +
> +(define_insn "smax3"
> +  [(set (match_operand:SCALARF 0 "register_operand" "=f")
> +   (smax:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
> + (match_operand:SCALARF 2 "register_operand" "f")))]
> +  "ISA_HAS_FMIN_FMAX"
> +  "max.\t%0,%1,%2"
> +  [(set_attr "type" "fminmax")
> +  (set_attr "mode" "")])

Re: [PATCH] mips: Fix C23 (...) functions returning large aggregates [PR114175]

[YunQiang Su]

Xi Ruoyao  于2024年3月20日周三 15:12写道：
>
> We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named
> arguments and there is nothing to advance, but that is not the case
> for (...) functions returning by hidden reference which have one such
> artificial argument.  This is causing gcc.dg/c23-stdarg-{6,8,9}.c to
> fail.
>
> Fix the issue by checking if arg.type is NULL, as r14-9503 explains.
>
> gcc/ChangeLog:
>
> PR target/114175
> * config/mips/mips.cc (mips_setup_incoming_varargs): Only skip
> mips_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
> functions if arg.type is NULL.
> ---
>
> Bootstrapped and regtested on mips64el-linux-gnuabi64.  Ok for trunk?
>

Thanks. LGTM.

>  gcc/config/mips/mips.cc | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
> index 68e2ae8d8fa..ce764a5cb35 100644
> --- a/gcc/config/mips/mips.cc
> +++ b/gcc/config/mips/mips.cc
> @@ -6834,7 +6834,13 @@ mips_setup_incoming_varargs (cumulative_args_t cum,
>   argument.  Advance a local copy of CUM past the last "real" named
>   argument, to find out how many registers are left over.  */
>local_cum = *get_cumulative_args (cum);
> -  if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)))
> +
> +  /* For a C23 variadic function w/o any named argument, and w/o an
> + artifical argument for large return value, skip advancing args.
> + There is such an artifical argument iff. arg.type is non-NULL
> + (PR 114175).  */
> +  if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))
> +  || arg.type != NULL_TREE)
>  mips_function_arg_advance (pack_cumulative_args (&local_cum), arg);
>
>/* Found out how many registers we need to save.  */
> --
> 2.44.0
>

Re: [PATCH] MIPS: Fix wrong MSA FP vector negation

[YunQiang Su]

Xi Ruoyao  于2024年2月5日周一 02:01写道：
>
> We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
> wrong because -0.0 is not 0 - 0.0.  This causes some Python tests to
> fail when Python is built with MSA enabled.
>
> Use the bnegi.df instructions to simply reverse the sign bit instead.
>
> gcc/ChangeLog:
>
> * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
> (neg2): Change the mode iterator from MSA to IMSA because
> in FP arithmetic we cannot use (0 - x) for -x.
> (neg2): New define_insn to implement FP vector negation,
> using a bnegi instruction to negate the sign bit.
> ---
>
> Bootstrapped and regtested on mips64el-linux-gnuabi64.  Ok for trunk
> and/or release branches?
>
>  gcc/config/mips/mips-msa.md | 18 +++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>

LGTM, while I guess that we also need a test case.

> diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
> index 83d9a08e360..920161ed1d8 100644
> --- a/gcc/config/mips/mips-msa.md
> +++ b/gcc/config/mips/mips-msa.md
> @@ -231,6 +231,10 @@ (define_mode_attr bitimm
> (V4SI  "uimm5")
> (V2DI  "uimm6")])
>
> +;; The index of sign bit in FP vector elements.
> +(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63")
> +(V4SF "31") (V8SF "31")])
> +
>  (define_expand "vec_init"
>[(match_operand:MSA 0 "register_operand")
> (match_operand:MSA 1 "")]
> @@ -597,9 +601,9 @@ (define_expand "abs2"
>  })
>
>  (define_expand "neg2"
> -  [(set (match_operand:MSA 0 "register_operand")
> -   (minus:MSA (match_dup 2)
> -  (match_operand:MSA 1 "register_operand")))]
> +  [(set (match_operand:IMSA 0 "register_operand")
> +   (minus:IMSA (match_dup 2)
> +  (match_operand:IMSA 1 "register_operand")))]
>"ISA_HAS_MSA"
>  {
>rtx reg = gen_reg_rtx (mode);
> @@ -607,6 +611,14 @@ (define_expand "neg2"
>operands[2] = reg;
>  })
>
> +(define_insn "neg2"
> +  [(set (match_operand:FMSA 0 "register_operand" "=f")
> +   (neg (match_operand:FMSA 1 "register_operand" "f")))]
> +  "ISA_HAS_MSA"
> +  "bnegi.\t%w0,%w1,"
> +  [(set_attr "type" "simd_bit")
> +   (set_attr "mode" "")])
> +
>  (define_expand "msa_ldi"
>[(match_operand:IMSA 0 "register_operand")
> (match_operand 1 "const_imm10_operand")]
> --
> 2.43.0
>

Re: CI for "Option handling: add documentation URLs"

[YunQiang Su]

Mark Wielaard  于2024年2月19日周一 06:58写道：
>
> Hi David,
>
> On Thu, Jan 04, 2024 at 09:57:09AM -0500, David Malcolm wrote:
> > I've pushed the .opt.urls patch kit to gcc trunk [1], so hopefully the
> > CI check you wrote can go live now.
>
> And then I was on vacation myself and forgot. I am sorry.
>
> So, I did try the regenerate-opt-urls locally, and it did generate the
> attached diff. Which seems to show we really need this automated.
>
> Going over the diff. The -Winfinite-recursion in rust does indeed seem
> new.  As do the -mapx-inline-asm-use-gpr32 and mevex512 for i386.  And
> the avr options -mskip-bug, -mflmap and mrodata-in-ram.  The change in
> common.opt.urls for -Wuse-after-free comes from it being moved from
> c++ to the c-family. The changes in mips.opt.urls seem to come from
> commit 46df1369 "doc/invoke: Remove duplicate explicit-relocs entry of
> MIPS".
>

For MIPS, it's due to malformed patches to invoke.text.
I will fix them.

> The changes in c.opt.urls seem mostly reordering. The sorting makes
> more sense after the diff imho. And must have come from commit
> 4666cbde5 "Sort warning options in c-family/c.opt".
>
> Also the documentation for -Warray-parameter was fixed.
>
> So I think the regenerate-opt-urls check does work as intended. So
> lets automate it, because it looks like nobody regenerated the
> url.opts after updating the documentation.
>
> But we should first apply this diff. Could you double check it is
> sane/correct?
>
> Thanks,
>
> Mark



-- 
YunQiang Su

[commit] invoke.texi: Fix some skipping UrlSuffix problem for MIPS

[YunQiang Su]

The problem is that, there are these lines in mips.opt.urls:
  ; skipping UrlSuffix for 'mabi=' due to finding no URLs
  ; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs
  ; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs

These lines is not fixed by this patch due to that we don't
document these options:
  ; skipping UrlSuffix for 'mlra' due to finding no URLs
  ; skipping UrlSuffix for 'mdebug' due to finding no URLs
  ; skipping UrlSuffix for 'meb' due to finding no URLs
  ; skipping UrlSuffix for 'mel' due to finding no URLs

gcc
* doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
problem of mabi=, mno-flush-func, mexplicit-relocs;
add missing leading - of mbranch-cost option.
* config/mips/mips.opt.urls: Regenerate.
---
 gcc/config/mips/mips.opt.urls | 12 ++--
 gcc/doc/invoke.texi   | 14 +-
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/gcc/config/mips/mips.opt.urls b/gcc/config/mips/mips.opt.urls
index ff2f0aee0e3..96aba041026 100644
--- a/gcc/config/mips/mips.opt.urls
+++ b/gcc/config/mips/mips.opt.urls
@@ -6,7 +6,8 @@ UrlSuffix(gcc/MIPS-Options.html#index-EB-2)
 EL
 UrlSuffix(gcc/MIPS-Options.html#index-EL-2)
 
-; skipping UrlSuffix for 'mabi=' due to finding no URLs
+mabi=
+UrlSuffix(gcc/MIPS-Options.html#index-mabi-3)
 
 mabicalls
 UrlSuffix(gcc/MIPS-Options.html#index-mabicalls)
@@ -65,9 +66,15 @@ UrlSuffix(gcc/MIPS-Options.html#index-membedded-data)
 meva
 UrlSuffix(gcc/MIPS-Options.html#index-meva)
 
+mexplicit-relocs=
+UrlSuffix(gcc/MIPS-Options.html#index-mexplicit-relocs-2)
+
 mexplicit-relocs
 UrlSuffix(gcc/MIPS-Options.html#index-mexplicit-relocs-2)
 
+mno-explicit-relocs
+UrlSuffix(gcc/MIPS-Options.html#index-mno-explicit-relocs-2)
+
 mextern-sdata
 UrlSuffix(gcc/MIPS-Options.html#index-mextern-sdata)
 
@@ -173,7 +180,8 @@ UrlSuffix(gcc/MIPS-Options.html#index-mno-float)
 mmcu
 UrlSuffix(gcc/MIPS-Options.html#index-mmcu-1)
 
-; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs
+mno-flush-func
+UrlSuffix(gcc/MIPS-Options.html#index-mno-flush-func-1)
 
 mno-mdmx
 UrlSuffix(gcc/MIPS-Options.html#index-mno-mdmx)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8219a6a5947..58527e1ea3c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -27995,11 +27995,7 @@ Aliases of @option{-minterlink-compressed} and
 @option{-mno-interlink-compressed}.  These options predate the microMIPS ASE
 and are retained for backwards compatibility.
 
-@opindex mabi=32
-@opindex mabi=o64
-@opindex mabi=n32
-@opindex mabi=64
-@opindex mabi=eabi
+@opindex mabi
 @item -mabi=32
 @itemx -mabi=o64
 @itemx -mabi=n32
@@ -28486,9 +28482,8 @@ Enable (disable) use of the @code{%hi()} and 
@code{%lo()} assembler
 relocation operators.  This option has been superseded by
 @option{-mexplicit-relocs} but is retained for backwards compatibility.
 
-@opindex mexplicit-relocs=none
-@opindex mexplicit-relocs=base
-@opindex mexplicit-relocs=pcrel
+@opindex mexplicit-relocs
+@opindex mno-explicit-relocs
 @item -mexplicit-relocs=none
 @itemx -mexplicit-relocs=base
 @itemx -mexplicit-relocs=pcrel
@@ -28767,6 +28762,7 @@ Disable the insertion of cache barriers.  This is the 
default setting.
 @end table
 
 @opindex mflush-func
+@opindex mno-flush-func
 @item -mflush-func=@var{func}
 @itemx -mno-flush-func
 Specifies the function to call to flush the I and D caches, or to not
@@ -28778,7 +28774,7 @@ depends on the target GCC was configured for, but 
commonly is either
 @code{_flush_func} or @code{__cpu_flush}.
 
 @opindex mbranch-cost
-@item mbranch-cost=@var{num}
+@item -mbranch-cost=@var{num}
 Set the cost of branches to roughly @var{num} ``simple'' instructions.
 This cost is only a heuristic and is not guaranteed to produce
 consistent results across releases.  A zero cost redundantly selects
-- 
2.39.2

[commit] MIPS: Add ATTRIBUTE_UNUSED to mips_start_function_definition

[YunQiang Su]

Fix build warning:
  mips.cc: warning: unused parameter 'decl'.

gcc
* config/mips/mips.cc (mips_start_function_definition):
Add ATTRIBUTE_UNUSED.
---
 gcc/config/mips/mips.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 60b336e43d0..e752019b5e2 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -7330,7 +7330,8 @@ mips_start_unique_function (const char *name)
function contains MIPS16 code.  */
 
 static void
-mips_start_function_definition (const char *name, bool mips16_p, tree decl)
+mips_start_function_definition (const char *name, bool mips16_p,
+   tree decl ATTRIBUTE_UNUSED)
 {
   if (mips16_p)
 fprintf (asm_out_file, "\t.set\tmips16\n");
-- 
2.39.2

Re: [pushed][PR112918][LRA]: Fixing IRA ICE on m68k

[YunQiang Su]

Vladimir Makarov  于2024年1月11日周四 22:35写道：
>
> The following patch fixes
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918
>
> The patch was successfully bootstrapped and tested on x86_64, aarch64,
> ppc64le

This patch causes some ICE on MIPS:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113354

PS: how to test cross build for mips:

1. apt install g++-multilib-mipsel-linux-gnu
2. apply patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641619.html
3. ../configure --target=mipsel-linux-gnu \
  --includedir=/usr/mipsel-linux-gnu/include --enable-multilib \
  --with-arch-32=mips32r2 --with-fp-32=xx \
  --enable-multiarch --enable-targets=all \
  --with-arch-64=mips64r2 --prefix=/usr --disable-libsanitizer
4. make -j

-- 
YunQiang Su

[PATCH] MIPS: avoid $gp store if global_pointer is not $gp

[YunQiang Su]

$GP is used for expanding GOT load, and in the afterward passes,
we will try to use a temporary register instead.

If sucess, we have no need to store and reload $gp. The example
of failure is that the function calls a preemtive function.

We shouldn't use $GP for any other purpose in the code we generate.
If a user's inline asm code clobbers $GP, it's their duty to save
and restore $GP.

gcc
* config/mips/mips.cc (mips_compute_frame_info): If another
register is used as global_pointer, mark $GP live false.

gcc/testsuite
* gcc.target/mips/mips.exp (mips_option_groups):
Add -mxgot/-mno-xgot options.
* gcc.target/mips/xgot-n32-avoid-gp.c: New test.
* gcc.target/mips/xgot-n32-need-gp.c: New test.
---
 gcc/config/mips/mips.cc   |  2 ++
 gcc/testsuite/gcc.target/mips/mips.exp|  1 +
 gcc/testsuite/gcc.target/mips/xgot-n32-avoid-gp.c | 11 +++
 gcc/testsuite/gcc.target/mips/xgot-n32-need-gp.c  | 11 +++
 4 files changed, 25 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/xgot-n32-avoid-gp.c
 create mode 100644 gcc/testsuite/gcc.target/mips/xgot-n32-need-gp.c

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index e752019b5e2..30e99811ff6 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -11353,6 +11353,8 @@ mips_compute_frame_info (void)
  in, which is why the global_pointer field is initialised here and not
  earlier.  */
   cfun->machine->global_pointer = mips_global_pointer ();
+  if (cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
+df_set_regs_ever_live (GLOBAL_POINTER_REGNUM, false);
 
   offset = frame->args_size + frame->cprestore_size;
 
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp 
b/gcc/testsuite/gcc.target/mips/mips.exp
index 9f8d533cfa5..e028bc93b40 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -266,6 +266,7 @@ set mips_option_groups {
 stack-protector "-fstack-protector"
 stdlib "REQUIRES_STDLIB"
 unaligned-access "-m(no-|)unaligned-access"
+xgot "-m(no-|)xgot"
 }
 
 for { set option 0 } { $option < 32 } { incr option } {
diff --git a/gcc/testsuite/gcc.target/mips/xgot-n32-avoid-gp.c 
b/gcc/testsuite/gcc.target/mips/xgot-n32-avoid-gp.c
new file mode 100644
index 000..3f52fc5a765
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/xgot-n32-avoid-gp.c
@@ -0,0 +1,11 @@
+/* Check if we skip store and load gp if there is no stub function call.  */
+/* { dg-options "-mips64r2 -mxgot -mabi=n32 -fPIC" } */
+
+extern int a;
+int
+foo ()
+{
+  return a;
+}
+/* { dg-final { scan-assembler-not "\tsd\t\\\$28," } } */
+/* { dg-final { scan-assembler-not "\tld\t\\\$28," } } */
diff --git a/gcc/testsuite/gcc.target/mips/xgot-n32-need-gp.c 
b/gcc/testsuite/gcc.target/mips/xgot-n32-need-gp.c
new file mode 100644
index 000..631409cb7fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/xgot-n32-need-gp.c
@@ -0,0 +1,11 @@
+/* We cannot skip store and load gp if there is stub function call.  */
+/* { dg-options "-mips64r2 -mxgot -mabi=n32 -fPIC" } */
+
+extern int f();
+int
+foo ()
+{
+  return f();
+}
+/* { dg-final { scan-assembler "\tsd\t\\\$28," } } */
+/* { dg-final { scan-assembler "\tld\t\\\$28," } } */
-- 
2.39.2

Re: MIPS: the method of getting GOT address for PIC code

[YunQiang Su]

YunQiang Su  于2023年8月25日周五 15:16写道：
>
> When working on LLVM, I found this problem
> https://github.com/llvm/llvm-project/issues/64974.
> Maybe it's time for us to reconsider the way of getting GOT address
> for PIC code.
>

I have my draft patch pushed to GitHub:
https://github.com/wzssyqa/gcc/tree/pcrel
And the patch is also attached.

Any comment is welcome.

-- 
YunQiang Su


0001-MIPS-PCREL-support.patch
Description: Binary data

Re: [PATCH v2] LoongArch: testsuite:Added additional vectorization "-mlsx" option.

[YunQiang Su]

Xi Ruoyao  于2024年1月15日周一 12:11写道：
>
> On Mon, 2024-01-15 at 09:29 +0800, chenxiaolong wrote:
> > At 21:13 +0800 on Saturday, 2024-01-13, Xi Ruoyao wrote：
> > > At 15:28 +0800 on Saturday 2024-01-13, chenxiaolong wrote：
> > > > gcc/testsuite/ChangeLog:
> > > >
> > > >   * gcc.dg/pr104992.c: Added additional "-mlsx" compilation
> > > > options.
> > > >   * gcc.dg/signbit-2.c: Dito.
> > > >   * gcc.dg/tree-ssa/scev-16.c: Dito.
> > > >   * gfortran.dg/graphite/vect-pr40979.f90: Dito.
> > > >   * gfortran.dg/vect/fast-math-mgrid-resid.f: Dito.
> > >
> > > I don't feel it right about the changes to pr104992.c and scev-16.c
> > > because no other architectures add special options there.  Why are we
> > > so special?
>
> >
> > Because on the LoongArch architecture, GCC requires the addition of
> > vectorization options in order to generate vector code. Use the
> > check_effective_target_vect_cmdline_needed command in the lib/target-
> > supports.exp file to set whether the command line option is needed to
> > enable vectorizations. For example, ia64,x86,aarch64, and riscv
> > architectures, vectorization is enabled by default.
>
> But no.  The default baseline of 32-bit x86 is i686, which is basically
> a Pentium III launched in 1999 without any vector instructions.
>
> We are still missing something here.
>
There is a line
 #define vector __attribute__((vector_size(4*sizeof(int
I guess it is the syntax needs to be supported.




-- 
YunQiang Su

Re: [PATCH] combine: Don't optimize SIGN_EXTEND of MEM on WORD_REGISTER_OPERATIONS targets [PR113010]

[YunQiang Su]

Greg McGary  于2024年1月17日周三 06:20写道：
>
> The sign bit of a sign-extending load cannot be known until runtime,
> so don't attempt to simplify it in the combiner.
>
> 2024-01-11  Greg McGary  
>
> PR rtl-optimization/113010
> * combine.cc (expand_compound_operation): Don't simplify
> SIGN_EXTEND of a MEM on WORD_REGISTER_OPERATIONS targets
>
> * gcc.c-torture/execute/pr113010.c: New test.
> ---
>  gcc/combine.cc | 5 +
>  gcc/testsuite/gcc.c-torture/execute/pr113010.c | 9 +
>  2 files changed, 14 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr113010.c
>
> diff --git a/gcc/combine.cc b/gcc/combine.cc
> index 812553c091e..ba587184dfc 100644
> --- a/gcc/combine.cc
> +++ b/gcc/combine.cc
> @@ -7208,6 +7208,11 @@ expand_compound_operation (rtx x)
>if (len == 0)
> return x;
>
> +  /* Sign-extending loads can never be simplified at compile time.  */
> +  if (WORD_REGISTER_OPERATIONS && MEM_P (XEXP (x, 0))
> + && load_extend_op (inner_mode) == SIGN_EXTEND)
> +   return x;
> +
>break;
>
>  case ZERO_EXTRACT:
> diff --git a/gcc/testsuite/gcc.c-torture/execute/pr113010.c 
> b/gcc/testsuite/gcc.c-torture/execute/pr113010.c
> new file mode 100644
> index 000..a95c613c1df
> --- /dev/null
> +++ b/gcc/testsuite/gcc.c-torture/execute/pr113010.c
> @@ -0,0 +1,9 @@
> +int minus_1 = -1;
> +
> +int
> +main ()
> +{
> +  if ((0, 0xul) >= minus_1)

There is a warning option:

-Wsign-compare
Warn when a comparison between signed and unsigned values could
produce an incorrect result when the signed value is converted to unsigned.

> +__builtin_abort ();
> +  return 0;
> +}
> --
> 2.34.1
>


-- 
YunQiang Su

[commit] Sanitizer/MIPS: Use $t9 for preemptible function call

[YunQiang Su]

From: YunQiang Su 

Currently, almost all of the shared libraries of MIPS, rely on $t9
to get the address of current function, instead of PCREL instructions,
even on MIPSr6. So we have to set $t9 properly.

To get the address of preemptible function, we need the help of GOT.
MIPS/O32 has .cpload, which can help to generate 3 instructions to get GOT.
For __mips64, we can get GOT by:

lui $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)
daddu $t8, $t8, $t9
daddiu $t8, $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)

And then get the address of __interceptor_func, and jump to it

ld $t9, %got_disp(_interceptor" SANITIZER_STRINGIFY(func) ")($t8)
jr $t9

Upstream-Commit: 0a64367a72f1634321f5051221f05f2f364bd882

libsanitizer

* interception/interception.h (substitution_##func_name):
Use macro C_ASM_TAIL_CALL.
* sanitizer_common/sanitizer_asm.h: Define C_ASM_TAIL_CALL
for MIPS with help of t9.
---
 libsanitizer/interception/interception.h  |  5 ++--
 libsanitizer/sanitizer_common/sanitizer_asm.h | 23 +++
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/libsanitizer/interception/interception.h 
b/libsanitizer/interception/interception.h
index 9d8b60b2eef..58e969378a9 100644
--- a/libsanitizer/interception/interception.h
+++ b/libsanitizer/interception/interception.h
@@ -205,8 +205,9 @@ const interpose_substitution substitution_##func_name[] 
\
  ASM_TYPE_FUNCTION_STR "\n"
\
SANITIZER_STRINGIFY(TRAMPOLINE(func)) ":\n" 
\
SANITIZER_STRINGIFY(CFI_STARTPROC) "\n" 
\
-   SANITIZER_STRINGIFY(ASM_TAIL_CALL) " __interceptor_"
\
- SANITIZER_STRINGIFY(ASM_PREEMPTIBLE_SYM(func)) "\n"   
\
+   C_ASM_TAIL_CALL(SANITIZER_STRINGIFY(TRAMPOLINE(func)),  
\
+   "__interceptor_"
\
+ SANITIZER_STRINGIFY(ASM_PREEMPTIBLE_SYM(func))) "\n"  
\
SANITIZER_STRINGIFY(CFI_ENDPROC) "\n"   
\
".size  " SANITIZER_STRINGIFY(TRAMPOLINE(func)) ", "
\
 ".-" SANITIZER_STRINGIFY(TRAMPOLINE(func)) "\n"
\
diff --git a/libsanitizer/sanitizer_common/sanitizer_asm.h 
b/libsanitizer/sanitizer_common/sanitizer_asm.h
index bbb18cfbdf1..3af66a4e449 100644
--- a/libsanitizer/sanitizer_common/sanitizer_asm.h
+++ b/libsanitizer/sanitizer_common/sanitizer_asm.h
@@ -53,6 +53,29 @@
 # define ASM_TAIL_CALL tail
 #endif
 
+// Currently, almost all of the shared libraries rely on the value of
+// $t9 to get the address of current function, instead of PCREL, even
+// on MIPSr6. To be compatiable with them, we have to set $t9 properly.
+// MIPS uses GOT to get the address of preemptible functions.
+#if defined(__mips64)
+#  define C_ASM_TAIL_CALL(t_func, i_func)   \
+"lui $t8, %hi(%neg(%gp_rel(" t_func ")))\n" \
+"daddu $t8, $t8, $t9\n" \
+"daddiu $t8, $t8, %lo(%neg(%gp_rel(" t_func ")))\n" \
+"ld $t9, %got_disp(" i_func ")($t8)\n"  \
+"jr $t9\n"
+#elif defined(__mips__)
+#  define C_ASM_TAIL_CALL(t_func, i_func)   \
+".setnoreorder\n"   \
+".cpload $t9\n" \
+".setreorder\n" \
+"lw $t9, %got(" i_func ")($gp)\n"   \
+"jr $t9\n"
+#elif defined(ASM_TAIL_CALL)
+#  define C_ASM_TAIL_CALL(t_func, i_func)   \
+SANITIZER_STRINGIFY(ASM_TAIL_CALL) " " i_func
+#endif
+
 #if defined(__ELF__) && defined(__x86_64__) || defined(__i386__) || \
 defined(__riscv)
 # define ASM_PREEMPTIBLE_SYM(sym) sym@plt
-- 
2.39.2

[PATCH] MIPS: Accept arguments for -mexplicit-relocs

[YunQiang Su]

GAS introduced explicit relocs since 2001, and %pcrel_hi/low were
introduced in 2014.  In future, we may introduce more.

Let's convert -mexplicit-relocs option, and accpet options:
none, base, pcrel.

We also update gcc/configure.ac to set the value to option
the gas support when GCC itself is built.

gcc
* configure.ac: Detect the explicit relocs support for
mips, and define C macro MIPS_EXPLICIT_RELOCS.
* config.in: Regenerated.
* configure: Regenerated.
* doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
* config/mips/mips-opts.h: Define enum mips_explicit_relocs.
* config/mips/mips.cc(mips_set_compression_mode): Sorry if
!TARGET_EXPLICIT_RELOCS instead of just set it.
* config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
* config/mips/mips.opt: Introduce -mexplicit-relocs= option
and define -m(no-)explicit-relocs as aliases.
---
 gcc/config.in   |  6 +
 gcc/config/mips/mips-opts.h |  7 +
 gcc/config/mips/mips.cc |  5 ++--
 gcc/config/mips/mips.h  |  8 ++
 gcc/config/mips/mips.opt| 25 --
 gcc/configure   | 51 -
 gcc/configure.ac| 21 +++
 gcc/doc/invoke.texi | 16 
 8 files changed, 124 insertions(+), 15 deletions(-)

diff --git a/gcc/config.in b/gcc/config.in
index 99fd2d89fe3..ce1d073833f 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -2356,6 +2356,12 @@
 #endif
 
 
+/* Define if assembler supports %reloc. */
+#ifndef USED_FOR_TARGET
+#undef MIPS_EXPLICIT_RELOCS
+#endif
+
+
 /* Define if host mkdir takes a single argument. */
 #ifndef USED_FOR_TARGET
 #undef MKDIR_TAKES_ONE_ARG
diff --git a/gcc/config/mips/mips-opts.h b/gcc/config/mips/mips-opts.h
index 57bdbdfa721..4b0c2c09a3d 100644
--- a/gcc/config/mips/mips-opts.h
+++ b/gcc/config/mips/mips-opts.h
@@ -53,4 +53,11 @@ enum mips_cb_setting {
   MIPS_CB_OPTIMAL,
   MIPS_CB_ALWAYS
 };
+
+/* Enumerates the setting of the -mexplicit-relocs= option.  */
+enum mips_explicit_relocs {
+  MIPS_EXPLICIT_RELOCS_NONE,
+  MIPS_EXPLICIT_RELOCS_BASE,
+  MIPS_EXPLICIT_RELOCS_PCREL
+};
 #endif
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 30e99811ff6..68e2ae8d8fa 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -20033,8 +20033,6 @@ mips_set_compression_mode (unsigned int 
compression_mode)
 call.  */
   flag_move_loop_invariants = 0;
 
-  target_flags |= MASK_EXPLICIT_RELOCS;
-
   /* Experiments suggest we get the best overall section-anchor
 results from using the range of an unextended LW or SW.  Code
 that makes heavy use of byte or short accesses can do better
@@ -20064,6 +20062,9 @@ mips_set_compression_mode (unsigned int 
compression_mode)
 
   if (TARGET_MSA)
sorry ("MSA MIPS16 code");
+
+  if (!TARGET_EXPLICIT_RELOCS)
+   sorry ("MIPS16 requires %<-mexplicit-relocs%>");
 }
   else
 {
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 8768933ba37..7145d23c650 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -145,6 +145,14 @@ struct mips_cpu_info {
  || TARGET_MICROMIPS)  \
 && mips_cb != MIPS_CB_NEVER)
 
+/* True if assembler support %gp_rel etc.  */
+#define TARGET_EXPLICIT_RELOCS \
+  (mips_opt_explicit_relocs >= MIPS_EXPLICIT_RELOCS_BASE)
+
+/* True if assembler support %pcrel_hi/%pcrel_lo.  */
+#define TARGET_EXPLICIT_RELOCS_PCREL \
+  (mips_opt_explicit_relocs >= MIPS_EXPLICIT_RELOCS_PCREL)
+
 /* True if the output file is marked as ".abicalls; .option pic0"
(-call_nonpic).  */
 #define TARGET_ABICALLS_PIC0 \
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index e8b411a8ffe..ce36942aabe 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -145,9 +145,30 @@ meva
 Target Var(TARGET_EVA)
 Use Enhanced Virtual Addressing instructions.
 
+Enum
+Name(mips_explicit_relocs) Type(int)
+The code model option names for -mexplicit-relocs:
+
+EnumValue
+Enum(mips_explicit_relocs) String(none) Value(MIPS_EXPLICIT_RELOCS_NONE)
+
+EnumValue
+Enum(mips_explicit_relocs) String(base) Value(MIPS_EXPLICIT_RELOCS_BASE)
+
+EnumValue
+Enum(mips_explicit_relocs) String(pcrel) Value(MIPS_EXPLICIT_RELOCS_PCREL)
+
+mexplicit-relocs=
+Target RejectNegative Joined Enum(mips_explicit_relocs) 
Var(mips_opt_explicit_relocs) Init(MIPS_EXPLICIT_RELOCS)
+Use %reloc() assembly operators.
+
 mexplicit-relocs
-Target Mask(EXPLICIT_RELOCS)
-Use NewABI-style %reloc() assembly operators.
+Target RejectNegative Alias(mexplicit-relocs=,base)
+Use %reloc() assembly operators (for backward compatibility).
+
+mno-explicit-relocs
+Target RejectNegative Alias(mexplicit-relocs=,none)
+Don't use %reloc() assembly operators (for backward compatibility).
 
 mextern-sdata