Re: [PATCH] minimal support for xtheadv

2023-11-09 Thread Yixuan Chen 
Hi Kito and Christoph,

XYenChi (oriachi...@gmail.com) is my e-mail address too. I didn't notice
the git email config have changed, very sorry about that.

We want to support other operate system project from our team, so port the
XTheadV. If T-Head and VRULL have made great progress, it's pleasure to
follow your work. By the way, I have sent the opcode patch to binutils, if
you have any concern, please check the patch:
https://sourceware.org/pipermail/binutils/2023-November/130431.html

If our team could provide any help, please let us know.

Best regards
Yixuan

Christoph Müllner  于2023年11月9日周四 16:06写道：

> On Thu, Nov 9, 2023 at 8:39 AM Kito Cheng  wrote:
> >
> > Hi Yi Xuan:
> >
> > This patch is trivial, and generally LGTM, but I would require putting
> > the spec into
> https://github.com/riscv-non-isa/riscv-toolchain-conventions
> > before merging this, also don't forget include "RISC-V:" in the title,
> > it would be easier to track during the RISC-V GCC sync meeting :)
> >
> > And I am a little bit confused by the author's info? is it from you or
> > "XYenChi "? or oriachi...@gmail.com is also your
> > mail address?
> >
> > cc Christoph since I believe you may know more about that process.
> > cc JoJo since you are T-head folk :P
>
> Hi Yi Xuan and Kito,
>
> I was not aware that CAS is working on getting T-Head's Vector
> extension supported.
> My biggest concern with this patch is that "XTheadV" does not have a
> specification.
>
> T-Head and VRULL are currently working on support patches for T-Head's
> Vector extension
> implementation. We've named the extension XTheadVector.
> Supporting XTheadVector means to address a range of issues (e.g.
> defining a formal ISA
> vendor extension specification, extension discovery, addressing
> implementation details,
> differences among available cores, intrinsics, ...).
> We've already made good progress on that and expect to publish first
> results soon.
>
> BR
> Christoph
>
> >
> >
> > On Wed, Nov 8, 2023 at 9:13 PM  wrote:
> > >
> > > From: XYenChi 
> > >
> > > This patch is for support xtheadv.
> > >
> > > gcc/ChangeLog:
> > >
> > > 2023-11-08  Chen Yixuan  
> > >
> > > * common/config/riscv/riscv-common.cc: Add xthead minimal
> support.
> > >
> > > gcc/config/ChangeLog:
> > >
> > > 2023-11-08  Chen Yixuan  
> > >
> > > * riscv/riscv.opt: Add xthead minimal support.
> > > ---
> > >  gcc/common/config/riscv/riscv-common.cc | 2 ++
> > >  gcc/config/riscv/riscv.opt  | 2 ++
> > >  2 files changed, 4 insertions(+)
> > >
> > > diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> > > index 526dbb7603b..d5ea0ee9b70 100644
> > > --- a/gcc/common/config/riscv/riscv-common.cc
> > > +++ b/gcc/common/config/riscv/riscv-common.cc
> > > @@ -325,6 +325,7 @@ static const struct riscv_ext_version
> riscv_ext_version_table[] =
> > >{"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
> > >{"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
> > >{"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
> > > +  {"xtheadv",ISA_SPEC_CLASS_NONE, 0, 7},
> > >
> > >{"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
> > >
> > > @@ -1680,6 +1681,7 @@ static const riscv_ext_flag_table_t
> riscv_ext_flag_table[] =
> > >{"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext,
> MASK_XTHEADMEMIDX},
> > >{"xtheadmempair", &gcc_options::x_riscv_xthead_subext,
> MASK_XTHEADMEMPAIR},
> > >{"xtheadsync",&gcc_options::x_riscv_xthead_subext,
> MASK_XTHEADSYNC},
> > > +  {"xtheadv",   &gcc_options::x_riscv_xthead_subext,
> MASK_XTHEADV},
> > >
> > >{"xventanacondops", &gcc_options::x_riscv_xventana_subext,
> MASK_XVENTANACONDOPS},
> > >
> > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> > > index 70d78151cee..2bbdf680fa2 100644
> > > --- a/gcc/config/riscv/riscv.opt
> > > +++ b/gcc/config/riscv/riscv.opt
> > > @@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
> > >
> > >  Mask(XTHEADSYNC)Var(riscv_xthead_subext)
> > >
> > > +Mask(XTHEADV)   Var(riscv_xthead_subext)
> > > +
> > >  TargetVariable
> > >  int riscv_xventana_subext
> > >
> > > --
> > > 2.42.0
> > >
>

[PATCH] Optimize testcase

2022-11-15 Thread Yixuan Chen 
From: Oria Chen 

gcc/testsuite/ChangeLog:

2022-11-15  Yixuan Chen  

* gcc.dg/fold-overflow-1.c: Optimize testcase, because riscv will use 
".LC0" intead of ".LC1" and ".LC2" with "-O" compile option
---
 gcc/testsuite/gcc.dg/fold-overflow-1.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/fold-overflow-1.c 
b/gcc/testsuite/gcc.dg/fold-overflow-1.c
index 108df4e3155..02598bfa3d3 100644
--- a/gcc/testsuite/gcc.dg/fold-overflow-1.c
+++ b/gcc/testsuite/gcc.dg/fold-overflow-1.c
@@ -18,5 +18,6 @@ float foo2(void)
   return 1.0f/0.0f;
 }
 
-/* { dg-final { scan-assembler-times "2139095040" 2 { target { ! mmix-*-* } } 
} } */
+/* { dg-final { scan-assembler-times "2139095040" 2 { target { ! { mmix-*-*  
riscv*-*-* } } } } } */
 /* { dg-final { scan-assembler-times "#7f80" 2 { target mmix-*-* } } } */
+/* { dg-final { scan-assembler-times "2139095040" 3 { target riscv*-*-* } } } 
*/
-- 
2.37.2

[PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

2022-11-17 Thread Yixuan Chen 
2022-11-17  Yixuan Chen  

* gcc/testsuite/gcc.dg/pr25521.c: Add compile option 
"-msmall-data-limit=0" to avoid using .srodata section for riscv.
---
 gcc/testsuite/gcc.dg/pr25521.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c
index 74fe2ae6626..628ddf1a761 100644
--- a/gcc/testsuite/gcc.dg/pr25521.c
+++ b/gcc/testsuite/gcc.dg/pr25521.c
@@ -2,7 +2,8 @@
sections.
 
{ dg-require-effective-target elf }
-   { dg-do compile } */
+   { dg-do compile }
+   { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */
 
 const volatile int foo = 30;
 
-- 
2.37.2

[PATCH] optimize the testcase for architectures that use ".srodata"

2022-11-17 Thread Yixuan Chen 
2022-11-18  Yixuan Chen  

* gcc.dg/pr25521.c: optimize the testcast for architectures that use 
".srodata"

testsuite/gcc.dg/pr25521.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c
index 74fe2ae6626..63363a03b9f 100644
--- a/gcc/testsuite/gcc.dg/pr25521.c
+++ b/gcc/testsuite/gcc.dg/pr25521.c
@@ -7,4 +7,4 @@
 const volatile int foo = 30;
 
 
-/* { dg-final { scan-assembler "\\.rodata" } } */
+/* { dg-final { scan-assembler "\\.s\?rodata" } } */
-- 
2.37.2

[PATCH] Riscv don't support "-fprefetch-loop-arrays", skip.

2022-11-22 Thread Yixuan Chen 
gcc/testsuite/ChangeLog:

Riscv don't support "-fprefetch-loop-arrays" option, skip.

2022-11-22  Yixuan Chen  

* gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" 
option, skip.
---
 gcc/testsuite/gcc.dg/pr106397.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
index 2bc17f8cf80..7b507125575 100644
--- a/gcc/testsuite/gcc.dg/pr106397.c
+++ b/gcc/testsuite/gcc.dg/pr106397.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param 
prefetch-latency=3 -fprefetch-loop-arrays" } */
 /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* 
x86_64-*-* } && ia32 } } } */
-
+/* { dg-skip-if "" { riscv*-*-* } } */
 int
 bar (void)
 {
-- 
2.37.2

[PATCH] Ver2: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.

2022-11-22 Thread Yixuan Chen 
gcc/testsuite/ChangeLog:

Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.

2022-11-22  Yixuan Chen  

* gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" 
option, add "-w" option.
---
 gcc/testsuite/gcc.dg/pr106397.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
index 2bc17f8cf80..b0983b61dfc 100644
--- a/gcc/testsuite/gcc.dg/pr106397.c
+++ b/gcc/testsuite/gcc.dg/pr106397.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param 
prefetch-latency=3 -fprefetch-loop-arrays" } */
 /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* 
x86_64-*-* } && ia32 } } } */
+/* { dg-additional-options "-w" { target riscv*-*-* } } */
 
 int
 bar (void)
-- 
2.37.2

[PATCH]RISC-V:Add xuantie C909, C910, C920v1 and C920v2 to -mcpu

2025-03-17 Thread Yixuan Chen 
gcc/ChangeLog:

* config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c910.
(RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2.
* config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info.
* doc/invoke.texi: Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/mcpu-xt-c908.c: New test.
* gcc.target/riscv/mcpu-xt-c910.c: New test.
* gcc.target/riscv/mcpu-xt-c920v1.c: New test.
* gcc.target/riscv/mcpu-xt-c920v2.c: New test.

Add xuantie C909, C910, C920v1 and C920v2 to -mcpu
Tune info copied 
from:https://github.com/XUANTIE-RV/gcc/blob/xuantie-gcc-10.2.0/gcc/config/riscv/riscv-xuantie-tune.h
No C920 related tune info, use generic_ooo.
---
 gcc/config/riscv/riscv-cores.def  | 25 ++
 gcc/config/riscv/riscv.cc | 34 +++
 gcc/doc/invoke.texi   |  4 +--
 .../gcc.target/riscv/mcpu-thead-c908.c| 34 +++
 .../gcc.target/riscv/mcpu-thead-c910.c| 29 
 .../gcc.target/riscv/mcpu-thead-c920v1.c  | 30 
 .../gcc.target/riscv/mcpu-thead-c920v2.c  | 29 
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c | 34 +++
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c | 29 
 .../gcc.target/riscv/mcpu-xt-c920v1.c | 30 
 .../gcc.target/riscv/mcpu-xt-c920v2.c | 29 
 11 files changed, 305 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c908.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c910.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c920v1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c920v2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 2918496bcd0..857ab0a3819 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -41,6 +41,10 @@ RISCV_TUNE("sifive-p400-series", sifive_p400, 
sifive_p400_tune_info)
 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
 RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("xt-c908", generic, xt_c908_tune_info)
+RISCV_TUNE("xt-c910", generic, xt_c910_tune_info)
+RISCV_TUNE("xt-c920v1", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
@@ -93,6 +97,27 @@ RISCV_CORE("thead-c906",  
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
  "xtheadmemidx_xtheadmempair_xtheadsync",
  "thead-c906")
 
+RISCV_CORE("xt-c908", 
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync_"
+ "zihintpause_zfh_zba_zbb_zbc_zbs",
+ "xt-c908")
+
+RISCV_CORE("xt-c910", 
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync_zfh",
+ "xt-c910")
+
+RISCV_CORE("xt-c920v1",   
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_"
+ 
"xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector_zfh",
+ "xt-c920v1")
+
+RISCV_CORE("xt-c920v2",   
"rv64imafdcv_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync_zfh",
+ "xt-c920v2")
+
 RISCV_CORE("tt-ascalon-d8",   "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_"
  "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_"
  "zifencei_zihintntl_zihintpause_zimop_za64rs_"
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38f3ae7cd84..3dfb0a71f88 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -554,6 +554,40 @@ static const struct riscv_tune_param thead_c906_tune_info 
= {
   NULL,/* loop_align */
 };
 
+/* Costs to use w

[PATCH v2]RISC-V:Add xuantie C908, C910, C920v1 and C920v2 to -mcpu

2025-03-17 Thread Yixuan Chen 
gcc/ChangeLog:

* config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c910.
(RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2.
* config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info.
* doc/invoke.texi: Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/mcpu-xt-c908.c: New test.
* gcc.target/riscv/mcpu-xt-c910.c: New test.
* gcc.target/riscv/mcpu-xt-c920v1.c: New test.
* gcc.target/riscv/mcpu-xt-c920v2.c: New test.

Fix v1 Subject issue and ISA string issue.

Add xuantie C909, C910, C920v1 and C920v2 to -mcpu
Tune info copied 
from:https://github.com/XUANTIE-RV/gcc/blob/xuantie-gcc-10.2.0/gcc/config/riscv/riscv-xuantie-tune.h
No C920 related tune info, use generic_ooo.
Add xuantie C909, C910, C920v1 and C920v2 to -mcpu
Tune info copied 
from:https://github.com/XUANTIE-RV/gcc/blob/xuantie-gcc-10.2.0/gcc/config/riscv/riscv-xuantie-tune.h
No C920 related tune info, use generic_ooo.
---
 gcc/config/riscv/riscv-cores.def  | 25 ++
 gcc/config/riscv/riscv.cc | 34 +++
 gcc/doc/invoke.texi   |  4 +--
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c | 34 +++
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c | 29 
 .../gcc.target/riscv/mcpu-xt-c920v1.c | 30 
 .../gcc.target/riscv/mcpu-xt-c920v2.c | 30 
 7 files changed, 184 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 2918496bcd0..af45ec57e90 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -41,6 +41,10 @@ RISCV_TUNE("sifive-p400-series", sifive_p400, 
sifive_p400_tune_info)
 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
 RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("xt-c908", generic, xt_c908_tune_info)
+RISCV_TUNE("xt-c910", generic, xt_c910_tune_info)
+RISCV_TUNE("xt-c920v1", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
@@ -93,6 +97,27 @@ RISCV_CORE("thead-c906",  
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
  "xtheadmemidx_xtheadmempair_xtheadsync",
  "thead-c906")
 
+RISCV_CORE("xt-c908", "rv64imafdc_zihintpause_zfh_zba_zbb_zbc_zbs_"
+ "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c908")
+
+RISCV_CORE("xt-c910", 
"rv64imafdc_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c910")
+
+RISCV_CORE("xt-c920v1",   
"rv64imafdc_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_"
+ 
"xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector",
+ "xt-c920v1")
+
+RISCV_CORE("xt-c920v2",   
"rv64imafdcv_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c920v2")
+
 RISCV_CORE("tt-ascalon-d8",   "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_"
  "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_"
  "zifencei_zihintntl_zihintpause_zimop_za64rs_"
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38f3ae7cd84..3dfb0a71f88 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -554,6 +554,40 @@ static const struct riscv_tune_param thead_c906_tune_info 
= {
   NULL,/* loop_align */
 };
 
+/* Costs to use when optimizing for xuantie C908.  */
+const struct riscv_tune_param xt_c908_tune_info = {
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},   /* fp_add */
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},   /* fp_mul */
+  {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
+  {COSTS_N_INSNS (3), COST

Re: [PATCH v2]RISC-V:Add xuantie C908, C910, C920v1 and C920v2 to -mcpu

2025-03-20 Thread Yixuan Chen 
Hi Majin,

 Thanks for your suggestion,
Look like the document don't contain the following tune information:
/* fmv_cost */, /* vector_unaligned_access */, /* use_divmod_expansion */,
and /* overlap_op_by_pieces */
, I will follow your further modification and wait for the gcc16 window to
send the patch v3 fixing the c920v1 name issue. But it's ok for me that
either of you and me to send the patch,
If you have any concern please contact me.

Best regards
Yixuan Chen



Jin Ma  于2025年3月20日周四 16:12写道：

> On Mon, 17 Mar 2025 17:31:36 +0800, Yixuan Chen wrote:
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908,
> xt-c910.
> > (RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2.
> > * config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info.
> > * doc/invoke.texi: Add xt-c908, xt-c910 and xt-c920v1 and
> xt-c920v2.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/mcpu-xt-c908.c: New test.
> > * gcc.target/riscv/mcpu-xt-c910.c: New test.
> > * gcc.target/riscv/mcpu-xt-c920v1.c: New test.
> > * gcc.target/riscv/mcpu-xt-c920v2.c: New test.
> >
> > Fix v1 Subject issue and ISA string issue.
> >
> > Add xuantie C909, C910, C920v1 and C920v2 to -mcpu
>
> Hi, Yixuan,
>
> I suggest changing C920v1 to C920, as this would better align with the
> actual naming conventions of the CPU.
>
> > Tune info copied from:
> https://github.com/XUANTIE-RV/gcc/blob/xuantie-gcc-10.2.0/gcc/config/riscv/riscv-xuantie-tune.h
> > No C920 related tune info, use generic_ooo.
>
> This is feasible for now; we can make further modifications later.
>
> > Add xuantie C909, C910, C920v1 and C920v2 to -mcpu
> > Tune info copied from:
> https://github.com/XUANTIE-RV/gcc/blob/xuantie-gcc-10.2.0/gcc/config/riscv/riscv-xuantie-tune.h
> > No C920 related tune info, use generic_ooo.
> > ---
> >  gcc/config/riscv/riscv-cores.def  | 25 ++
> >  gcc/config/riscv/riscv.cc | 34 +++
> >  gcc/doc/invoke.texi   |  4 +--
> >  gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c | 34 +++
> >  gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c | 29 
> >  .../gcc.target/riscv/mcpu-xt-c920v1.c | 30 
> >  .../gcc.target/riscv/mcpu-xt-c920v2.c | 30 
> >  7 files changed, 184 insertions(+), 2 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v1.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
> >
> > diff --git a/gcc/config/riscv/riscv-cores.def
> b/gcc/config/riscv/riscv-cores.def
> > index 2918496bcd0..af45ec57e90 100644
> > --- a/gcc/config/riscv/riscv-cores.def
> > +++ b/gcc/config/riscv/riscv-cores.def
> > @@ -41,6 +41,10 @@ RISCV_TUNE("sifive-p400-series", sifive_p400,
> sifive_p400_tune_info)
> >  RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
> >  RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info)
> >  RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
> > +RISCV_TUNE("xt-c908", generic, xt_c908_tune_info)
> > +RISCV_TUNE("xt-c910", generic, xt_c910_tune_info)
> > +RISCV_TUNE("xt-c920v1", generic, generic_ooo_tune_info)
> > +RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
> >  RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
> >  RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
> >  RISCV_TUNE("size", generic, optimize_size_tune_info)
> > @@ -93,6 +97,27 @@ RISCV_CORE("thead-c906",
> "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
> > "xtheadmemidx_xtheadmempair_xtheadsync",
> > "thead-c906")
> >
> > +RISCV_CORE("xt-c908",
>  "rv64imafdc_zihintpause_zfh_zba_zbb_zbc_zbs_"
> > +   "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
> > +   "xtheadcondmov_xtheadfmemidx_xtheadmac_"
> > +   "xtheadmemidx_xtheadmempair_xtheadsync",
> > +   "xt-c908")
> > +
> > +RISCV_CORE("xt-c910",
>  "rv64imafdc_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo

[PATCH] [RISC-V]Support -mcpu for Xuantie cpu

2025-04-20 Thread Yixuan Chen 
gcc/ChangeLog:

* config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c908v, 
xt-c910, xt-c910v2, xt-c920, xt-c920v2.
(RISCV_CORE): Add xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, 
xt-c920v2
* config/riscv/riscv.cc: Add xt-c908, xt-c908v, xt-c910, xt-c910v2, 
xt-c920, xt-c920v2
* doc/invoke.texi:  Add xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, 
xt-c920v2

gcc/testsuite/ChangeLog:

* gcc.target/riscv/mcpu-xt-c908.c: test -mcpu=xt-c908.
* gcc.target/riscv/mcpu-xt-c910.c: test -mcpu=xt-c910.
* gcc.target/riscv/mcpu-xt-c920v2.c: test -mcpu=xt-c920v2.
* gcc.target/riscv/mcpu-xt-c908v.c: test -mcpu=xt-c908v.
* gcc.target/riscv/mcpu-xt-c910v2.c: test -mcpu=xt-c910v2.
* gcc.target/riscv/mcpu-xt-c920.c: test -mcpu=xt-c920.

Support -mcpu=xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, xt-c920v2
for Xuantie series cpu.
ref:https://www.xrvm.cn/community/download?id=4224248662731067392

without fmv_cost, vector_unaligned_access, use_divmod_expansion, 
overlap_op_by_pieces, fill the tune info with generic ooo for further 
modification.
---
 gcc/config/riscv/riscv-cores.def  | 48 
 gcc/doc/invoke.texi   |  7 ++-
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c | 48 
 .../gcc.target/riscv/mcpu-xt-c908v.c  | 50 +
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c | 35 
 .../gcc.target/riscv/mcpu-xt-c910v2.c | 51 +
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c | 34 +++
 .../gcc.target/riscv/mcpu-xt-c920v2.c | 56 +++
 8 files changed, 326 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 2918496bcd0..e31afc3fe70 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -41,6 +41,12 @@ RISCV_TUNE("sifive-p400-series", sifive_p400, 
sifive_p400_tune_info)
 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
 RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("xt-c908", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c908v", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c910", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c910v2", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c920", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
@@ -93,6 +99,48 @@ RISCV_CORE("thead-c906",  
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
  "xtheadmemidx_xtheadmempair_xtheadsync",
  "thead-c906")

+RISCV_CORE("xt-c908", "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_"
+ "zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_"
+ "sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_"
+ "xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_"
+ "xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c908")
+RISCV_CORE("xt-c908v","rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_"
+ "zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_"
+ "zvfh_sstc_svinval_svnapot_svpbmt__xtheadba_"
+ "xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_"
+ "xtheadfmemidx_xtheadmac_xtheadmemidx_"
+ "xtheadmempair_xtheadsync_xtheadvdot",
+ "xt-c908")
+RISCV_CORE("xt-c910", "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
+ "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c910")
+RISCV_CORE("xt-c910v2",   "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_"
+ "zicsr_zifencei _zihintntl_zihintpause_zihpm_"
+ "zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_"
+ "zbs_sscofpmf_sstc_svinval_svnapot_svpbmt_"
+ "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+