[PATCH][wwwdoc] gcc-14: Add arm cortex-m52 cpu support

[Chung-Ju Wu]

Hi Gerald,

The Arm Cortex-M52 CPU has been added to the upstream:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642230.html

I would like to document this on the gcc-14 changes.html page.
Attached is the patch for gcc-wwwdocs repository.

Is it OK?

Regards,
jasonwucjFrom 2513e83f07490451eb4be593454afa1f513b6153 Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Thu, 7 Dec 2023 13:33:43 +0800
Subject: [PATCH] gcc-14: Add arm cortex-m52 cpu support

---
 htdocs/gcc-14/changes.html | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index e3a68998..0e3557c7 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -328,7 +328,12 @@ a work-in-progress.
 
 
 
-
+arm
+
+  The Cortex-M52 CPU is now supported through the cortex-m52
+  argument to the -mcpu and -mtune options.
+  
+
 
 
 
-- 
2.34.3

Re: [PATCH][wwwdoc] gcc-14: Add arm cortex-m52 cpu support

[Chung-Ju Wu]

On 2024/01/10 22:52 UTC+8, Gerald Pfeifer wrote:

On Wed, 10 Jan 2024, Kyrylo Tkachov wrote:

Hi Gerald,

The Arm Cortex-M52 CPU has been added to the upstream:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642230.html

I would like to document this on the gcc-14 changes.html page.

I can approve these as port maintainer. The entry is okay.


Yes and yes, and thanks and thanks! :-)

Gerald


Hi Kyrylo & Gerald,

Thank both of you for the approval. :)

The patch is committed as:
  
https://gcc.gnu.org/git/?p=gcc-wwwdocs.git;a=commit;h=b4fd94ebe3f1b50a1d83d0c3cfdad37fd467d44c


Regards,
jasonwucj

[PATCH 1/2] arm: Add cortex-m52 core

[Chung-Ju Wu]

Hi,

Recently, Arm announced the Cortex-M52, delivering increased performance
in DSP and ML along with a range of other features and benefits.
For the completeness of Arm ecosystem, we hope that cortex-m52 support
could be available in gcc-14.

Attached is the patch to support cortex-m52 cpu with MVE and PACBTI enabled in 
GCC.
Bootstrapped and tested on arm-none-eabi.

Is it OK for trunk?

Regards,
jasonwucjFrom d0856b516c5d270a852f3edd9df5dadccde5b94e Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Wed, 6 Dec 2023 15:49:58 +0800
Subject: [PATCH 1/2] arm: Add support for Arm Cortex-M52 CPU.

This patch adds the -mcpu support for the Arm Cortex-M52 CPU which is
an Armv8.1-M Mainline CPU supporting MVE and PACBTI by default.

-mcpu=cortex-m52 switch by default matches to 
-march=armv8.1-m.main+pacbti+mve.fp+fp.dp.

The cde feature is supported by specifying +cdecpN (e.g. 
-mcpu=cortex-m52+cdecp),
where N is the coprocessor number 0 to 7.

Also following options are provided to disable default features.
+nomve.fp (disables MVE Floating point)
+nomve (disables MVE Integer and MVE Floating point)
+nodsp (disables dsp, MVE Integer and MVE Floating point)
+nopacbti (disables pacbti)
+nofp (disables floating point and MVE floating point)

Signed-off-by: Chung-Ju Wu 

gcc/ChangeLog:

* config/arm/arm-cpus.in (cortex-m52): New cpu.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
---
 gcc/config/arm/arm-cpus.in| 21 +
 gcc/config/arm/arm-tables.opt |  3 +++
 gcc/config/arm/arm-tune.md|  6 +++---
 3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 6fa7e315ef0..451b15fe9f9 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1641,6 +1641,27 @@ begin cpu cortex-m35p
  costs v7m
 end cpu cortex-m35p
 
+begin cpu cortex-m52
+ cname cortexm52
+ tune flags LDSCHED
+ architecture armv8.1-m.main+pacbti+mve.fp+fp.dp
+ option nopacbti remove pacbti
+ option nomve.fp remove mve_float
+ option nomve remove mve mve_float
+ option nofp remove ALL_FP mve_float
+ option nodsp remove MVE mve_float
+ option cdecp0 add cdecp0
+ option cdecp1 add cdecp1
+ option cdecp2 add cdecp2
+ option cdecp3 add cdecp3
+ option cdecp4 add cdecp4
+ option cdecp5 add cdecp5
+ option cdecp6 add cdecp6
+ option cdecp7 add cdecp7
+ isa quirk_no_asmcpu quirk_vlldm
+ costs v7m
+end cpu cortex-m52
+
 begin cpu cortex-m55
  cname cortexm55
  tune flags LDSCHED
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 9d6ae875ede..d3eb9a97739 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m33) Value( 
TARGET_CPU_cortexm33)
 EnumValue
 Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p)
 
+EnumValue
+Enum(processor_type) String(cortex-m52) Value( TARGET_CPU_cortexm52)
+
 EnumValue
 Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55)
 
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 7318f03b97e..6a631d82966 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -49,7 +49,7 @@
cortexa710,cortexx1,cortexx1c,
neoversen1,cortexa75cortexa55,cortexa76cortexa55,
neoversev1,neoversen2,cortexm23,
-   cortexm33,cortexm35p,cortexm55,
-   starmc1,cortexm85,cortexr52,
-   cortexr52plus"
+   cortexm33,cortexm35p,cortexm52,
+   cortexm55,starmc1,cortexm85,
+   cortexr52,cortexr52plus"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
-- 
2.34.3

[PATCH 2/2] arm: Add cortex-m52 doc

[Chung-Ju Wu]

Hi,

This is the patch to add cortex-m52 in the Arm-related options
sections of the gcc invoke.texi documentation.

Is it OK for trunk?

Regards,
jasonwucjFrom b7ce3d499d4bf087ec54a5f834876c9108d46c3d Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Thu, 7 Dec 2023 11:26:25 +0800
Subject: [PATCH 2/2] arm: Add Arm Cortex-M52 CPU documentation.

Signed-off-by: Chung-Ju Wu 

gcc/ChangeLog:

* doc/invoke.texi: Update docs.
---
 gcc/doc/invoke.texi | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d71583853f0..bdbe0074cb4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23094,7 +23094,7 @@ Permissible names are: @samp{arm7tdmi}, 
@samp{arm7tdmi-s}, @samp{arm710t},
 @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus},
 @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
-@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1},
+@samp{cortex-m35p}, @samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85}, 
@samp{cortex-x1},
 @samp{cortex-x1c}, @samp{cortex-m1.small-multiply}, 
@samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
 @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale},
@@ -23160,34 +23160,34 @@ The following extension options are common to the 
listed CPUs:
 @table @samp
 @item +nodsp
 Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p},
-@samp{cortex-m55} and @samp{cortex-m85}. Also disable the M-Profile Vector
-Extension (MVE) integer and single precision floating-point instructions on
-@samp{cortex-m55} and @samp{cortex-m85}.
+@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
+Also disable the M-Profile Vector Extension (MVE) integer and
+single precision floating-point instructions on
+@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
 
 @item +nopacbti
 Disable the Pointer Authentication and Branch Target Identification Extension
-on @samp{cortex-m85}.
+on @samp{cortex-m52} and @samp{cortex-m85}.
 
 @item +nomve
 Disable the M-Profile Vector Extension (MVE) integer and single precision
-floating-point instructions on @samp{cortex-m55} and @samp{cortex-m85}.
+floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55} and 
@samp{cortex-m85}.
 
 @item +nomve.fp
 Disable the M-Profile Vector Extension (MVE) single precision floating-point
-instructions on @samp{cortex-m55} and @samp{cortex-m85}.
+instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
 
 @item +cdecp0, +cdecp1, ... , +cdecp7
 Enable the Custom Datapath Extension (CDE) on selected coprocessors according
-to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}.
+to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52} 
and @samp{cortex-m55}.
 
 @item  +nofp
 Disables the floating-point instructions on @samp{arm9e},
 @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
 @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
 @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
-@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p},
-@samp{cortex-m55} and @samp{cortex-m85}.
+@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
 Disables the floating-point and SIMD instructions on
 @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
 @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
@@ -23530,9 +23530,9 @@ Development Tools Engineering Specification", which can 
be found on
 Mitigate against a potential security issue with the @code{VLLDM} instruction
 in some M-profile devices when using CMSE (CVE-2021-365465).  This option is
 enabled by default when the option @option{-mcpu=} is used with
-@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55}, @code{cortex-m85}
-or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465} can be 
used
-to disable the mitigation.
+@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m52}, @code{cortex-m55},
+@code{cortex-m85} or @code{star-mc1}. The option 
@option{-mno-fix-cmse-cve-2021-35465}
+can be used to disable the mitigation.
 
 @opindex mstack-protector-guard
 @opindex mstack-protector-guard-offset
-- 
2.34.3

Re: [PATCH 1/2] arm: Add cortex-m52 core

[Chung-Ju Wu]

On 2024/01/08 22:31 UTC+8, Kyrylo Tkachov wrote:

Hi jasonwucj,


-Original Message-
From: Chung-Ju Wu 
Sent: Monday, January 8, 2024 6:16 AM
To: gcc-patches ; Kyrylo Tkachov
; Richard Earnshaw 
Cc: jason...@anshingtek.com.tw
Subject: [PATCH 1/2] arm: Add cortex-m52 core

Hi,

Recently, Arm announced the Cortex-M52, delivering increased performance
in DSP and ML along with a range of other features and benefits.
For the completeness of Arm ecosystem, we hope that cortex-m52 support
could be available in gcc-14.

Attached is the patch to support cortex-m52 cpu with MVE and PACBTI enabled in
GCC.
Bootstrapped and tested on arm-none-eabi.

Is it OK for trunk?


The patch looks good to me. It should be safe to include it in GCC 14 as it 
doesn’t add any new logic beyond a new entry in arm-cpus.in.
Do you have commit rights to push it?


Hi Kyrylo,

Thanks for the approval.

Yes, I have commit right to push it.
The patch is committed as: 
https://gcc.gnu.org/g:6e249a9ad9d26fb01b147d33be9f9bfebca85c24

Thanks,
jasonwucj



Thanks,
Kyrill



Regards,
jasonwucj

Re: [PATCH 2/2] arm: Add cortex-m52 doc

[Chung-Ju Wu]

On 2024/01/08 22:32 UTC+8, Kyrylo Tkachov wrote:




-Original Message-
From: Chung-Ju Wu 
Sent: Monday, January 8, 2024 6:17 AM
To: gcc-patches ; Kyrylo Tkachov
; Richard Earnshaw 
Cc: jason...@anshingtek.com.tw
Subject: [PATCH 2/2] arm: Add cortex-m52 doc

Hi,

This is the patch to add cortex-m52 in the Arm-related options
sections of the gcc invoke.texi documentation.

Is it OK for trunk?


In the ChangeLog entry:
gcc/ChangeLog:

* doc/invoke.texi: Update docs.

Let's be more specific and specify something like
* doc/invoke.texi (Arm Options): Document Cortex-m52 options.

Ok with a better ChangeLog entry.


Hi Kyrylo,

Thanks for the suggestion and approval.
The patch is revised and committed as: 
https://gcc.gnu.org/g:43c4f982113076ad54c3405f865cc63b0a5ba5aa

Thanks,
jasonwucj



Thanks,
Kyrill


Regards,
jasonwucj

[PING^2] [PATCH 0/6] Contributing new target port: Andes 'nds32'.

[Chung-Ju Wu]

Hi, GCC global reviewers,

The nds32 port initial patch is still awaiting for
any global reviewer's approval.

Since there is no further comment in these days,
is it OK for trunk?

Thanks in advance. :)


Best regards,
jasonwucj


2013/8/13 Chung-Ju Wu :
> Hi, GCC Global Maintainers,
>
> The Andes nds32 port has been accepted by GCC SC [1]
> and the initial patch is posted on [2] but still needs
> global maintainer's approval.
>
[...]
>
> [1] http://gcc.gnu.org/ml/gcc/2013-07/msg00232.html
> [2] http://gcc.gnu.org/ml/gcc-patches/2013-07/msg01144.html
>

Re: [PATCH 1/6] Andes nds32: configure settings for nds32 target.

[Chung-Ju Wu]

On 7/24/13 11:46 PM, Chung-Ju Wu wrote:
> On 7/10/13 6:56 AM, Joseph S. Myers wrote:
>> On Mon, 8 Jul 2013, Chung-Ju Wu wrote:
>
> Thanks for the review comments.
> A revised patch is provided and here is a summary:
> 
>   1. Handle -march option within the compiler proper.
>  Simplify the handling of --with-arch in config.gcc.
>   2. The c-isr library is supported for all arch configuration.
>   3. Use tm_defines so that we can have only one t-mlibs used.
> 
> 

It has been a while since last v2 patch.
So I create a new v3 patch to resolve conflict with current trunk.

Is it OK to apply on the trunk?


Best regards,
jasonwucj

diff --git contrib/config-list.mk contrib/config-list.mk
index 9a141c2..08acc35 100644
--- contrib/config-list.mk
+++ contrib/config-list.mk
@@ -43,7 +43,9 @@ LIST = aarch64-elf aarch64-linux-gnu \
   mipsisa64-elfoabi mipsisa64r2el-elf mipsisa64sr71k-elf mipsisa64sb1-elf \
   mipsel-elf mips64-elf mips64vr-elf mips64orion-elf mips-rtems \
   mips-wrs-vxworks mipstx39-elf mmix-knuth-mmixware mn10300-elf moxie-elf \
-  moxie-uclinux moxie-rtems pdp11-aout picochip-elfOPT-enable-obsolete \
+  moxie-uclinux moxie-rtems \
+  nds32le-elf nds32be-elf \
+  pdp11-aout picochip-elfOPT-enable-obsolete \
   powerpc-darwin8 \
   powerpc-darwin7 powerpc64-darwin powerpc-freebsd6 powerpc-netbsd \
   powerpc-eabispe powerpc-eabisimaltivec powerpc-eabisim ppc-elf \
diff --git gcc/config.gcc gcc/config.gcc
index 36d5ae8..6ea8bba 100644
--- gcc/config.gcc
+++ gcc/config.gcc
@@ -418,6 +418,10 @@ mips*-*-*)
extra_headers="loongson.h"
extra_options="${extra_options} g.opt mips/mips-tables.opt"
;;
+nds32*)
+   cpu_type=nds32
+   extra_headers="nds32_intrinsic.h"
+   ;;
 picochip-*-*)
 cpu_type=picochip
 ;;
@@ -2030,6 +2034,18 @@ mn10300-*-*)
use_collect2=no
use_gcc_stdint=wrap
;;
+nds32le-*-*)
+   target_cpu_default="0"
+   tm_defines="${tm_defines}"
+   tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
+   tmake_file="nds32/t-mlibs"
+   ;;
+nds32be-*-*)
+   target_cpu_default="0|MASK_BIG_ENDIAN"
+   tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+   tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
+   tmake_file="nds32/t-mlibs"
+   ;;
 pdp11-*-*)
tm_file="${tm_file} newlib-stdint.h"
use_gcc_stdint=wrap
@@ -3645,6 +3661,39 @@ case "${target}" in
esac
;;
 
+   nds32*-*-*)
+   supported_defaults="arch nds32_lib"
+
+   # process --with-arch
+   case "${with_arch}" in
+   "" | v2 | v3 | v3m)
+   # OK
+   ;;
+   *)
+   echo "Cannot accept --with-arch=$with_arch, available 
values are: v2 v3 v3m" 1>&2
+   exit 1
+   ;;
+   esac
+
+   # process --with-nds32-lib
+   case "${with_nds32_lib}" in
+   "")
+   # the default library is newlib
+   with_nds32_lib=newlib
+   ;;
+   newlib)
+   # OK
+   ;;
+   mculib)
+   # OK
+   ;;
+   *)
+   echo "Cannot accept --with-nds32-lib=$with_nds32_lib, 
available values are: newlib mculib" 1>&2
+   exit 1
+   ;;
+   esac
+   ;;
+
powerpc*-*-* | rs6000-*-*)
supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 
tune_64"
 
diff --git libgcc/config.host libgcc/config.host
index 187391e..20f56d2 100644
--- libgcc/config.host
+++ libgcc/config.host
@@ -137,6 +137,9 @@ mips*-*-*)
cpu_type=mips
tmake_file=mips/t-mips
;;
+nds32*-*)
+   cpu_type=nds32
+   ;;
 powerpc*-*-*)
cpu_type=rs6000
;;
@@ -831,6 +834,29 @@ moxie-*-rtems*)
# Don't use default.
extra_parts=
;;
+nds32*-elf*)
+   # Basic makefile fragment and extra_parts for crt stuff.
+   # We also append c-isr library implementation.
+   tmake_file="${tmake_file} nds32/t-nds32 nds32/t-nds32-isr"
+   extra_parts="crtbegin1.o crtend1.o libnds32_isr.a"
+   # Append library definition makefile fragment according to 
--with-nds32-lib=X setting.
+   case "${with_nds32_lib}" in
+   "" | newlib)
+   # Append library definition makefile fragment t-nds32-newlib.
+   # Append 'soft-fp' software floating point make rule fragment 
pro

Re: [PATCH 3/6] Andes nds32: libgcc of nds32 porting.

[Chung-Ju Wu]

On 7/31/13 7:07 PM, Chung-Ju Wu wrote:
> On 7/25/13 12:41 AM, Chung-Ju Wu wrote:
> 
> According to Joseph's comment in this discussion thread:
>   http://gcc.gnu.org/ml/gcc-patches/2013-07/msg01372.html
> 
> Using LGPLv2.1+ with exception seems appropriate for sfp-machine.h.
> So I update our libgcc patch for nds32 port.
> 

It has been a while since last v2 patch.
I create a new v3 patch with zip file for current trunk.
(The plain text file is too large to be attached.)

Is it OK to apply on the trunk?


Best regards,
jasonwucj




3-nds32-libgcc.v3.patch.tar.gz
Description: GNU Zip compressed data

Re: [PATCH 4/6] Andes nds32: testsuite modifications for nds32 target.

[Chung-Ju Wu]

On 7/25/13 12:23 AM, Chung-Ju Wu wrote:
> 
> A revised patch is provided and here is a summary:
> 
>   1. The extend identifiers testcases are supposed to be tested.
>   2. Add preliminary nds32-specific testcases.
> 
> 

It has been a while since last v2 patch.
So I create a new v3 patch to resolve some conflicts
on testcases with current trunk.

The nds32 port is accepted by GCC SC and
there is no further comment to the patch.

Is it OK to apply on the trunk?


Best regards,
jasonwucj

diff --git gcc/testsuite/g++.dg/other/PR23205.C 
gcc/testsuite/g++.dg/other/PR23205.C
index e55710b..26a9dd5 100644
--- gcc/testsuite/g++.dg/other/PR23205.C
+++ gcc/testsuite/g++.dg/other/PR23205.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* 
hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* nds32*-*-* *-*-aix* 
alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */
 /* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types" } */
 
 const int foobar = 4;
diff --git gcc/testsuite/g++.dg/other/pr23205-2.C 
gcc/testsuite/g++.dg/other/pr23205-2.C
index 607e5a2..b25cb73 100644
--- gcc/testsuite/g++.dg/other/pr23205-2.C
+++ gcc/testsuite/g++.dg/other/pr23205-2.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* 
hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* nds32*-*-* *-*-aix* 
alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */
 /* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types 
-ftoplevel-reorder" } */
 
 const int foobar = 4;
diff --git gcc/testsuite/gcc.dg/20020312-2.c gcc/testsuite/gcc.dg/20020312-2.c
index 633da5b..6f5a953 100644
--- gcc/testsuite/gcc.dg/20020312-2.c
+++ gcc/testsuite/gcc.dg/20020312-2.c
@@ -52,6 +52,8 @@ extern void abort (void);
 /* No pic register.  */
 #elif defined(__moxie__)
 /* No pic register.  */
+#elif defined(__nds32__)
+/* No pic register.  */
 #elif defined(__hppa__)
 /* PIC register is %r27 or %r19, but is used even without -fpic.  */
 #elif defined(__pdp11__)
diff --git gcc/testsuite/gcc.dg/builtin-apply2.c 
gcc/testsuite/gcc.dg/builtin-apply2.c
index daaef47..70ab7b3 100644
--- gcc/testsuite/gcc.dg/builtin-apply2.c
+++ gcc/testsuite/gcc.dg/builtin-apply2.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args 
in registers." { "aarch64*-*-* avr-*-* " } { "*" } { "" } } */
+/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args 
in registers." { "aarch64*-*-* avr-*-* nds32*-*-*" } { "*" } { "" } } */
 /* { dg-skip-if "Variadic funcs use Base AAPCS.  Normal funcs use VFP 
variant." { "arm*-*-*" } { "-mfloat-abi=hard" } { "" } } */
 
 /* PR target/12503 */
diff --git gcc/testsuite/gcc.dg/lower-subreg-1.c 
gcc/testsuite/gcc.dg/lower-subreg-1.c
index 102ba22..12dcd10 100644
--- gcc/testsuite/gcc.dg/lower-subreg-1.c
+++ gcc/testsuite/gcc.dg/lower-subreg-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* 
sparc*-*-* spu-*-* tilegx-*-* } } } } } */
 /* { dg-options "-O -fdump-rtl-subreg1" } */
 /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */
+/* { dg-skip-if "nds32 target has special operations for 64-bit behavior" { 
nds32*-*-* }  { "*" } { "" } } */
 /* { dg-require-effective-target ilp32 } */
 
 long long test (long long a, long long b) { return a | b; }
diff --git gcc/testsuite/gcc.dg/sibcall-3.c gcc/testsuite/gcc.dg/sibcall-3.c
index c4460e2..e02a410 100644
--- gcc/testsuite/gcc.dg/sibcall-3.c
+++ gcc/testsuite/gcc.dg/sibcall-3.c
@@ -5,7 +5,7 @@
Copyright (C) 2002 Free Software Foundation Inc.
Contributed by Hans-Peter Nilsson*/
 
-/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* 
m32r-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || 
{ arm*-*-* && { ! arm32 } } } } } */
+/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* 
m32r-*-* mcore-*-* mn10300-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* 
xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
 /* -mlongcall disables sibcall patterns.  */
 /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
 /* { dg-options "-O2 -foptimize-sibling-calls" } */
diff --git gcc/testsuite/gcc.dg/sibcall-4.c gcc/testsuite/gcc.dg/sibcall-4.c
index 4f468f6..a66ed07 100644
--- gcc/testsuite/gcc.dg/sibcal

Re: [PATCH 5/6] Andes nds32: documentation for nds32 target.

[Chung-Ju Wu]

On 7/25/13 12:25 AM, Chung-Ju Wu wrote:
> On 7/12/13 1:35 AM, Chung-Ju Wu wrote:
>>
>> Fixed accordingly.
>>
>> Thanks for the review comments.  A revised patch is provided
>> and the issues you mentioned are fixed:
>>a. Describe nds32 built-in functions.
>>b. Use "@:" and "16--47"
>>
> 
> Because we have replaced -misa= with -march= option,
> we have another revised patch for documentation.
> 
> A revised patch is provided and here is a summary:
> 
>   1. Replace -misa= with -march= option.
> 
> 

It has been a while since last v2 patch.
So I create a new v3 patch to resolve some conflicts
on documentation with current trunk.

Is it OK to apply on the trunk?


Best regards,
jasonwucj


diff --git gcc/doc/extend.texi gcc/doc/extend.texi
index 151b7e9..25e8963 100644
--- gcc/doc/extend.texi
+++ gcc/doc/extend.texi
@@ -2502,6 +2502,12 @@ on data in the eight-bit data area.  Note the eight-bit 
data area is limited to
 You must use GAS and GLD from GNU binutils version 2.7 or later for
 this attribute to work correctly.
 
+@item exception
+@cindex exception handler functions
+Use this attribute on the NDS32 target to indicate that the specified function
+is an exception handler.  The compiler will generate corresponding sections
+for use in an exception handler.
+
 @item exception_handler
 @cindex exception handler functions on the Blackfin processor
 Use this attribute on the Blackfin to indicate that the specified function
@@ -2922,6 +2928,32 @@ void __attribute__ ((interrupt, use_shadow_register_set,
  use_debug_exception_return)) v7 ();
 @end smallexample
 
+On NDS32 target, this attribute is to indicate that the specified function
+is an interrupt handler.  The compiler will generate corresponding sections
+for use in an interrupt handler.  You can use the following attributes
+to modify the behavior:
+@table @code
+@item nested
+@cindex @code{nested} attribute
+This interrupt service routine is interruptible.
+@item not_nested
+@cindex @code{not_nested} attribute
+This interrupt service routine is not interruptible.
+@item nested_ready
+@cindex @code{nested_ready} attribute
+This interrupt service routine is interruptible after @code{PSW.GIE}
+(global interrupt enable) is set.  This allows interrupt service routine to
+finish some short critical code before enabling interrupts.
+@item save_all
+@cindex @code{save_all} attribute
+The system will help save all registers into stack before entering
+interrupt handler.
+@item partial_save
+@cindex @code{partial_save} attribute
+The system will help save caller registers into stack before entering
+interrupt handler.
+@end table
+
 On RL78, use @code{brk_interrupt} instead of @code{interrupt} for
 handlers intended to be used with the @code{BRK} opcode (i.e.@: those
 that must end with @code{RETB} instead of @code{RETI}).
@@ -3143,10 +3175,11 @@ and newer.
 
 @item naked
 @cindex function without a prologue/epilogue code
-Use this attribute on the ARM, AVR, MCORE, RL78, RX and SPU ports to indicate 
that
-the specified function does not need prologue/epilogue sequences generated by
-the compiler.  It is up to the programmer to provide these sequences. The
-only statements that can be safely included in naked functions are
+Use this attribute on the ARM, AVR, MCORE, NDS32, RL78, RX and SPU ports
+to indicate that the specified function does not need prologue/epilogue
+sequences generated by the compiler.
+It is up to the programmer to provide these sequences.
+The only statements that can be safely included in naked functions are
 @code{asm} statements that do not have operands.  All other statements,
 including declarations of local variables, @code{if} statements, and so
 forth, should be avoided.  Naked functions should be used to implement the
@@ -3491,6 +3524,21 @@ safe since the loaders there save EAX, EDX and ECX.  
(Lazy binding can be
 disabled with the linker or the loader if desired, to avoid the
 problem.)
 
+@item reset
+@cindex reset handler functions
+Use this attribute on the NDS32 target to indicate that the specified function
+is a reset handler.  The compiler will generate corresponding sections
+for use in a reset handler.  You can use the following attributes
+to provide extra exception handling:
+@table @code
+@item nmi
+@cindex @code{nmi} attribute
+Provide a user-defined function to handle NMI exception.
+@item warm
+@cindex @code{warm} attribute
+Provide a user-defined function to handle warm reset exception.
+@end table
+
 @item sseregparm
 @cindex @code{sseregparm} attribute
 On the Intel 386 with SSE support, the @code{sseregparm} attribute
@@ -8844,6 +8892,7 @@ instructions, but allow the compiler to schedule those 
calls.
 * MIPS Paired-Single Support::
 * MIPS Loongson Built-in Functions::
 * Other MIPS Built-in Functions::
+* NDS32 Built-in Functions::
 * picoChip Built-in Functions::
 * PowerPC Built-i

Re: [PATCH 6/6] Andes nds32: wwwdoc for nds32 target.

[Chung-Ju Wu]

On 7/8/13 7:05 PM, Chung-Ju Wu wrote:
> Hi,
> 
> This patch consists of webpage changes for describing a new 'nds32'
> target port and related information.
> 
> The following is a brief overview of changes:
> 
> htdocs/
> 2013-07-08  Chung-Ju Wu  
>   Shiva Chen  
> 
>   * backends.html: Add architecture characteristic key for nds32 target.
>   * readings.html: Add related information for nds32 target.
>   * gcc-4.9/changes.html: Add nds32 target support description.
> 

It has been a while since last patch.
I create a new v3 patch to resolve conflict with current trunk.

Is it OK to apply on the cvs wwwdoc trunk? :)


Best regards,
jasonwucj

Index: htdocs/backends.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/backends.html,v
retrieving revision 1.46
diff -u -r1.46 backends.html
--- htdocs/backends.html16 Jul 2012 21:19:20 -  1.46
+++ htdocs/backends.html8 Sep 2013 16:49:28 -
@@ -92,6 +92,7 @@
 mmix | HM  Q   Cq  p   b a e 
 mn10300  | ?? c  g  s
 ms1  |   S   F  B  p g bd
+nds32|   F C   pda  s
 pa   |   ? Q   CBD  qrm da e 
 pdp11|L   ICqrcp   e 
 rs6000   | Q   Cqr  da   
Index: htdocs/readings.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/readings.html,v
retrieving revision 1.231
diff -u -r1.231 readings.html
--- htdocs/readings.html1 Apr 2013 10:49:54 -   1.231
+++ htdocs/readings.html8 Sep 2013 16:49:28 -
@@ -68,6 +68,13 @@
Hardware Reference Manuals
  
 
+ andes (nds32)
+  Manufacturer: Various licenses of Andes Technology Corporation.
+  CPUs include: AndesCore families N7, N8, SN8, N9, N10, N12 and N13.
+  http://www.andestech.com/en/products/documentation.htm";>Andes 
Documentation
+  GDB includes a simulator for all CPUs.
+ 
+
  arc
   Manufacturer: ARC Cores (Argonaut)
  
Index: htdocs/gcc-4.9/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.9/changes.html,v
retrieving revision 1.26
diff -u -r1.26 changes.html
--- htdocs/gcc-4.9/changes.html 26 Aug 2013 14:16:31 -  1.26
+++ htdocs/gcc-4.9/changes.html 8 Sep 2013 16:49:28 -
@@ -228,6 +228,15 @@
   through -march=slm.
 
   
+
+NDS32
+  
+ A new port is added to support nds32 target,
+  the 32-bit architecture from Andes Technology Corporation.
+ The port provides initial support for the V2, V3, V3m
+  instruction set architectures.
+  
+
 RX
   
  The port now allows to specify the RX100, RX200, and RX600 processors

[PING^3] [PATCH 0/6] Contributing new target port: Andes 'nds32'.

[Chung-Ju Wu]

Hi, GCC Global Maintainers,

The nds32 port initial patch is still awaiting for
global maintainer's approval before it may be committed
into trunk.

All the issues of review comment have been addressed
in the new v3 patches:

[PATCH 1/6] Andes nds32: configure settings for nds32 target.
  http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00516.html
[PATCH 2/6] Andes nds32: machine description of nds32 porting.
  http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00517.html
  http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00518.html
  http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00519.html
[PATCH 3/6] Andes nds32: libgcc of nds32 porting.
  http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00520.html
[PATCH 4/6] Andes nds32: testsuite modifications for nds32 target.
  http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00521.html
[PATCH 5/6] Andes nds32: documentation for nds32 target.
  http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00522.html
[PATCH 6/6] Andes nds32: wwwdoc for nds32 target.
  http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00524.html

If there is no further comment, may I commit these nds32 patches into trunk?
So that other developers are able to get nds32 port via svn/git easily.

We and Andes Technology Corporation really appreciate it. :)


Best regards,
jasonwucj


On 8/25/13 11:28 PM, Chung-Ju Wu wrote:
> 2013/8/13 Chung-Ju Wu :
>> Hi, GCC Global Maintainers,
>>
>> The Andes nds32 port has been accepted by GCC SC [1]
>> and the initial patch is posted on [2] but still needs
>> global maintainer's approval.
>>
> [...]
>>
>> [1] http://gcc.gnu.org/ml/gcc/2013-07/msg00232.html
>> [2] http://gcc.gnu.org/ml/gcc-patches/2013-07/msg01144.html
>>

Re: [PATCH 6/6] Andes nds32: wwwdoc for nds32 target.

[Chung-Ju Wu]

2013/9/10 Gerald Pfeifer :
> On Mon, 9 Sep 2013, Chung-Ju Wu wrote:
>> Is it OK to apply on the cvs wwwdoc trunk? :)
>
> I would perhaps say:
>
>   "A new nds32 port supports the 32-bit architecture from Andes
>   Technology Corporation"
>
> or similar.
>
> If you prefer the current wording, that needs an extra "the",
> as in "to support the nds32 target".
>
> The patch is fine one of these changes.
>

Thanks for the comment and approval.

I take first option as you suggested.
Attach is the revised patch and I will commit it after
nds32 port implementation gets approved and committed. :)

>
> Once committed, can you also propose a new item for our main page?
> A new port definitely is worth one. :)
>
> Gerald

I'd happy to propose a new item at "News" block
on gcc main page as follows:

Index: htdocs/index.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v
retrieving revision 1.890
diff -u -r1.890 index.html
--- htdocs/index.html   13 Aug 2013 14:24:15 -  1.890
+++ htdocs/index.html   11 Sep 2013 14:08:10 -
@@ -53,6 +53,11 @@

 

+Andes nds32 support
+[2013-MM-DD]
+A port for nds32, the 32-bit architecture of AndesCore families,
+  has been contributed by Andes Technology Corporation.
+
 Twitter and Google+ accounts
 [2013-08-08]
 GCC and the GNU Toolchain Project now have accounts on


Once nds32 port implementation is approved and committed,
I will fill up the date in 2013-MM-DD and formally post a
patch mail on mailing list.

Thank you so much. :)


Best regards,
jasonwucj


6-nds32-wwwdoc.v3.revised.patch
Description: Binary data

Re: Ping^6: contribute Synopsys Designware ARC port

[Chung-Ju Wu]

2013/10/1 Diego Novillo :
> On Sat, Sep 28, 2013 at 9:54 AM, Joern Rennecke
>  wrote:
>> The main part of the port (everything but the testsuite) is still waiting
>> for review:
>
> I have been reviewing these patches (I've gone through 2), and so far
> I find nothing surprising in them.  I should be able to finish them
> today or tomorrow.  Joern, I assume that you'll be one of the
> maintainers for the port?  Anyone else?
>
> SC folks, could you appoint Joern (and any other volunteer that Joern
> suggests) as maintainers?
>
> Thanks.  Diego.

It seems that Joern has been appointed as port maintainer earlier:
  http://gcc.gnu.org/ml/gcc/2013-01/msg00094.html

And he also added himself in MAINTAINERS file already. :)


Best regards,
jasonwucj

Re: [PATCH 2/6] Andes nds32: machine description of nds32 porting (2).

[Chung-Ju Wu]

2013/10/6 Richard Sandiford :
> Chung-Ju Wu  writes:
>> On 10/2/13 1:31 AM, Richard Sandiford wrote:
>>> Chung-Ju Wu  writes:
>>>> +  /* Use $r15, if the value is NOT in the range of Is20,
>>>> + we must output "sethi + ori" directly since
>>>> + we may already passed the split stage.  */
>>>> +  return "sethi\t%0, hi20(%1)\;ori\t%0, %0, lo12(%1)";
>>>> +case 17:
>>>> +  return "#";
>>>
>>> I don't really understand the comment for case 16.  Returning "#"
>>> (like for case 17) forces a split even at the output stage.
>>>
>>> In this case it might not be worth forcing a split though, so I don't
>>> see any need to change the code.  I think the comment should be changed
>>> to give a different reason though.
>>>
>>
>> Sorry for the misleading comment.
>>
>> For case 17, we were trying to split large constant into two individual
>> rtx patterns into "sethi" + "addi" so that we can have chance to match
>> "addi" pattern with 16-bit instruction.
>>
>> But case 16 is different.
>> This case is only produced at prologue/epilogue phase, using a temporary
>> register $r15 to hold a large constant for adjusting stack pointer.
>> Since prologue/epilogue is after split1/split2 phase, we can only
>> output "sethi" + "ori" directly.
>> (The "addi" instruction with $r15 is a 32-bit instruction.)
>
> But this code is in the output template of the define_insn.  That code
> is only executed during final, after all passes have been run.  If the
> template returns "#", final will split the instruction itself, which is
> possible even at that late stage.  "#" doesn't have any effect on the
> passes themselves.
>
> (FWIW, there's also a split3 pass that runs after prologue/epilogue
> generation but before sched2.)
>
> However, ISTR there is/was a rule that prologue instructions shouldn't
> be split, since they'd lose their RTX_FRAME_RELATED_P bit or something.
> Maybe you hit an ICE because of that?
>

Ah... yes, you are right.  In the nds32_force_addi_stack_int(),
I move a large constant to a temp register for stack pointer adjustment:

+  /* $r15 is going to be temporary register to hold the value.  */
+  tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
+
+  /* Create one more instruction to move value
+ into the temporary register.  */
+  value_move_insn = emit_move_insn (tmp_reg, GEN_INT (full_value));
+
+  /* At prologue, we need to tell GCC that this is frame related insn,
+ so that we can consider this instruction to output debug information.
+ If full_value is NEGATIVE, it means this function
+ is invoked by expand_prologue.  */
+  if (full_value < 0)
+RTX_FRAME_RELATED_P (value_move_insn) = 1;
+
+  /* Create new 'add' rtx.  */
+  sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
+   stack_pointer_rtx,
+   tmp_reg);
+  /* Emit rtx into insn list and receive its transformed insn rtx.  */
+  sp_adjust_insn = emit_insn (sp_adjust_insn);
+
+  /* At prologue, we need to tell GCC that this is frame related insn,
+ so that we can consider this instruction to output debug information.
+ If full_value is NEGATIVE, it means this function
+ is invoked by expand_prologue.  */
+  if (full_value < 0)
+RTX_FRAME_RELATED_P (sp_adjust_insn) = 1;

If there is a rule to avoid spliting instructions with RTX_FRAME_RELATED_P,
I think it is the case why I hit an ICE of unrecognized insn for
'value_move_insn'.

It seems that my comment to case 16 is incorrect.
Thanks for clarifying it.

> Another way to handle this would be to have the movsi expander split
> large constant moves.  When can_create_pseudo_p (), the intermediate
> results can be stored in new registers, otherwise they should reuse
> operands[0].  Two advantages to doing it that way are that high parts
> can be shared before RA, and that calls to emit_move_insn from the
> prologue code will split the move automatically.  I think many ports
> do it that way (including MIPS FWIW).
>

Do you mean that I should split large constant by myself in movsi
(or starting from movsi) for both case 16 and case 17?

Thanks for the suggestion.  I'll try to implement it. :)


Best regards,
jasonwucj

Re: [PATCH 2/6] Andes nds32: machine description of nds32 porting (2).

[Chung-Ju Wu]

2013/10/6 Chung-Lin Tang :
> On 2013/10/6 下午 06:33, Richard Sandiford wrote:
>> Chung-Lin Tang  writes:
>>> On 2013/10/6 05:57 PM, Richard Sandiford wrote:
 Another way to handle this would be to have the movsi expander split
 large constant moves.  When can_create_pseudo_p (), the intermediate
 results can be stored in new registers, otherwise they should reuse
 operands[0].  Two advantages to doing it that way are that high parts
 can be shared before RA, and that calls to emit_move_insn from the
 prologue code will split the move automatically.  I think many ports
 do it that way (including MIPS FWIW).
>>>
>>> FWIW, most ports usually just handle such "large adjustment" cases in
>>> the prologue/epilogue code manually; either multiple SP-adjustments, or
>>> use of a temp register (better control of RTX_FRAME_RELATED_P anyways).
>>> You might be able to get it to work, but trying to rely on the splitter
>>> does not seem like best practice...
>>
>> To be clear, I wasn't talking about relying on the splitter in the
>> define_split sense.  I was saying that the move expanders could
>> split large constants.
>
>> MIPS prologue code does use emit_move_insn to move large constants,
>> which automatically produces a split form from the outset.  I don't
>> really agree that it's bad practice.
>
> I think that's mostly the same as what I meant by "manually"; it seems
> that there's lots of MIPS backend machinery starting from
> mips_legitimize_move(), so it's not really "automatic" ;)
>
> Chung-Lin
>

Hi, Chung-Lin,

Thanks for the hint. ^_^

I will follow Richard and your suggestion to split large constant
via movsi manually.  So that it will be automatically split whenever
emit_move_insn() is used. :)


Best regards,
jasonwucj

[PATCH v4, nds32] Andes nds32 port, machine description 3/3

[Chung-Ju Wu]

Hi, all,

This is v4 patch for Andes nds32 port on machine description part 3,
which includes other rtl patterns and settings.

gcc/
2013-10-25  Chung-Ju Wu  
Shiva Chen  

* config/nds32/constants.md: New file.
* config/nds32/constraints.md: New file.
* config/nds32/iterators.md: New file.
* config/nds32/nds32-doubleword.md: New file.
* config/nds32/nds32-intrinsic.md: New file.
* config/nds32/nds32_intrinsic.h: New file.
* config/nds32/nds32-modes.def: New file.
* config/nds32/nds32-multiple.md: New file.
* config/nds32/nds32.opt: New file.
* config/nds32/nds32-opts.h: New file.
* config/nds32/nds32-protos.h: New file.
* config/nds32/nds32-peephole2.md: New file.
* config/nds32/pipelines.md: New file.
* config/nds32/predicates.md: New file.
* config/nds32/t-mlibs: New file.


Best regards,
jasonwucj

RFA: Andes nds32 port v4 patch

[Chung-Ju Wu]

Hi, GCC global reviewers,

I would like to thank Joseph Myers's preliminary review and
Richard Sandiford's help for further technical review in these
three months:
  http://gcc.gnu.org/ml/gcc-patches/2013-07/msg01138.html
  http://gcc.gnu.org/ml/gcc-patches/2013-10/msg01180.html

Their comments clearly enhance nds32 port machine description design.
Now we have v4 patch for nds32 port in which all the issues have
been addressed:
  http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02153.html
  http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02154.html
  http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02156.html

Any advice or comment to improve the patch is much appreciated.
If there is no further comment, is this nds32 v4 patch OK for the trunk? :)


Best regards,
jasonwucj

[PATCH v4, nds32] Andes nds32 port, libgcc part

[Chung-Ju Wu]

Hi, all,

This is v4 patch for Andes nds32 port on libgcc part.

Thanks Joseph Myers's comments.  Now we remove the .file directive
from crtzero.S.  The rationale of this can be referred to:
  http://gcc.gnu.org/ml/gcc-patches/2008-07/msg00123.html

The diff is as follows and the patch file is attached.

diff --git a/libgcc/config/nds32/crtzero.S b/libgcc/config/nds32/crtzero.S
index 5ef0361..6509869 100644
--- a/libgcc/config/nds32/crtzero.S
+++ b/libgcc/config/nds32/crtzero.S
@@ -33,8 +33,6 @@
 !!
 
!!==

-   .file   "crtzero.S"
-
 
!!--
 !! Jump to start up code
 
!!--


libgcc/
2013-10-29  Chung-Ju Wu  
Shiva Chen  

* config/nds32 : New directory and files.


Best regards,
jasonwucj


3-nds32-libgcc.v4.patch.tar.gz
Description: GNU Zip compressed data

[PATCH v4, nds32] Andes nds32 port, documentation part

[Chung-Ju Wu]

This is v4 patch for Andes nds32 port on documentation part.

Thanks Joseph Myers's comments.  Now we use @deftypefn and @samp
to refine our documentation content.

The diff is as follows and the patch file is attached.

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index f0002a9..5f91813 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -12432,33 +12432,38 @@ once the handler returns.

 These built-in functions are available for the NDS32 target:

-@table @code
-@item void __builtin_nds32_isync (int *@var{addr})
+@deftypefn {Built-in Function} void __builtin_nds32_isync (int *@var{addr})
 Insert an ISYNC instruction into the instruction stream where
 @var{addr} is an instruction address for serialization.
+@end deftypefn

-@item void __builtin_nds32_isb (void)
+@deftypefn {Built-in Function} void __builtin_nds32_isb (void)
 Insert an ISB instruction into the instruction stream.
+@end deftypefn

-@item int __builtin_nds32_mfsr (int @var{sr})
+@deftypefn {Built-in Function} int __builtin_nds32_mfsr (int @var{sr})
 Return the content of a system register which is mapped by @var{sr}.
+@end deftypefn

-@item int __builtin_nds32_mfusr (int @var{usr})
+@deftypefn {Built-in Function} int __builtin_nds32_mfusr (int @var{usr})
 Return the content of a user space register which is mapped by @var{usr}.
+@end deftypefn

-@item void __builtin_nds32_mtsr (int @var{value}, int @var{sr})
+@deftypefn {Built-in Function} void __builtin_nds32_mtsr (int
@var{value}, int @var{sr})
 Move the @var{value} to a system register which is mapped by @var{sr}.
+@end deftypefn
-@item void __builtin_nds32_mtusr (int @var{value}, int @var{usr})
+@deftypefn {Built-in Function} void __builtin_nds32_mtusr (int
@var{value}, int @var{usr})
 Move the @var{value} to a user space register which is mapped by @var{usr}.
+@end deftypefn

-@item void __builtin_nds32_setgie_en (void)
+@deftypefn {Built-in Function} void __builtin_nds32_setgie_en (void)
 Enable global interrupt.
+@end deftypefn

-@item void __builtin_nds32_setgie_dis (void)
+@deftypefn {Built-in Function} void __builtin_nds32_setgie_dis (void)
 Disable global interrupt.
-
-@end table
+@end deftypefn

 @node picoChip Built-in Functions
 @subsection picoChip Built-in Functions
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 68af98e..cbc0644 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1864,7 +1864,7 @@ supported since version 4.7.2 and is the default
in 4.8.0 and newer.

 @item --with-nds32-lib=@var{library}
 Specifies that @var{library} setting is used for building @file{libgcc.a}.
-Currently, the valid @var{library} is 'newlib' or 'mculib'.
+Currently, the valid @var{library} is @samp{newlib} or @samp{mculib}.
 This option is only supported for the NDS32 target.

 @item --with-build-time-tools=@var{dir}


gcc/
2013-10-29  Chung-Ju Wu  
Shiva Chen  

* doc/invoke.texi (NDS32 options): Document nds32 specific options.
* doc/md.texi (NDS32 family): Document nds32 specific constraints.
* doc/install.texi (Cross-Compiler-Specific Options): Document
--with-nds32-lib for nds32 target.
* doc/extend.texi (Function Attributes): Document nds32 specific
attributes.


Best regards,
jasonwucj


5-nds32-documentation.v4.patch
Description: Binary data

Re: RFA: Andes nds32 port v4 patch

[Chung-Ju Wu]

2013/10/29 Joseph S. Myers :
> Since Richard looked at the machine description part of the port, I looked
> at the other pieces.  I'm happy with those pieces with the following minor
> changes:
>
> http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00520.html (libgcc): remove
> the .file directive from crtzero.S.  See
>  for why such
> directives are best avoided.
>

Thank you for the link.  Now I realize the rationale of
why it is better to remove the .file directive. :)

Modify it accordingly:
  http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02382.html

> http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00522.html (documentation):
> use @deftypefn rather than @table @code when documenting built-in
> functions.  In install.texi, say @samp{newlib} and @samp{mculib} instead
> of using '' quotes.
>

Thanks for the comment.  Now I modify it as you suggested:
  http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02384.html

> --
> Joseph S. Myers
> jos...@codesourcery.com

Thank you very much for the comments on libgcc and documentation parts.
Here I re-list the v4 patch of nds32 port:

  Machine Description --
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02153.html
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02154.html
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02156.html
  Libgcc and Documentation --
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02382.html
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg02384.html

Are those nds32 port patches OK to be committed?


Best regards,
jasonwucj

[PATCH] New port committed: Andes nds32.

[Chung-Ju Wu]

Hi, all,

Thanks for all who gave me suggestions, review comments,
and approval to this new nds32 port for GCC trunk.

The Andes nds32 port now is committed into trunk as Rev.204269:
  http://gcc.gnu.org/r204269

We also add items on wwwdoc for nds32 port contribution:
  htdocs/backends.html  -- Revision 1.48
  htdocs/index.html -- Revision 1.897
  htdocs/readings.html  -- Revision 1.233
  htdocs/gcc-4.9/changes.html -- Revision 1.31

We will keep maintaining nds32 port and the testsuite result
will be periodically published on appropriate mailing list.


Best regards,
jasonwucj

[PATCH, nds32] Committed: Adjust MULT performance cost.

[Chung-Ju Wu]

Hi, all,

The multiplication operation is low cost in nds32 target.
COSTS_N_INSNS(5) is too expensive for performance.
Adjust MULT cost to COSTS_N_INSNS(1).

Committed as Rev. 205478: http://gcc.gnu.org/r205478


Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 205477)
+++ gcc/ChangeLog   (working copy)
@@ -1,3 +1,8 @@
+2013-11-28  Chung-Ju Wu  
+
+   * config/nds32/nds32.c (nds32_rtx_costs): Adjust MULT cost if it is
+   not optimized for size.
+
 2013-11-28  Jakub Jelinek  

* cfgexpand.c (struct stack_vars_data): Add asan_base and asan_alignb

Index: gcc/config/nds32/nds32.c
===
--- gcc/config/nds32/nds32.c(revision 205477)
+++ gcc/config/nds32/nds32.c(working copy)
@@ -2471,7 +2471,7 @@
   break;

 case MULT:
-  *total = COSTS_N_INSNS (5);
+  *total = COSTS_N_INSNS (1);
   break;

 case DIV:


Best regards,
jasonwucj

Re: [PATCH, testsuite] Fix some testcases for nds32 target and provide new nds32 target specific tests

[Chung-Ju Wu]

Hi, Mike,

There is a pending testsuite patch for nds32 target:
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg01584.html

Is it OK for trunk? :)


Best regards,
jasonwucj


2013/11/14 Chung-Ju Wu :
>
> I would like to modify some testcases for nds32 target.
> Also I have some nds32 target specific tests which is
> suggested by Joseph earlier:
>   http://gcc.gnu.org/ml/gcc-patches/2013-07/msg00396.html
>
> The patch is attached and a ChangeLog is as below:
>
> gcc/testsuite/
> 2013-11-14  Chung-Ju Wu  
>
> * g++.dg/other/PR23205.C: Skip for nds32*-*-*.
> * g++.dg/other/pr23205-2.C: Skip for nds32*-*-*.
> * gcc.dg/20020312-2.c: Add __nds32__ case.
> * gcc.dg/builtin-apply2.c: Skip for nds32*-*-*.
> * gcc.dg/lower-subreg-1.c: Skip for nds32*-*-*.
> * gcc.dg/sibcall-3.c: Expected fail for nds32*-*-*.
> * gcc.dg/sibcall-4.c: Expected fail for nds32*-*-*.
> * gcc.dg/stack-usage-1.c (SIZE): Define case for __nds32__.
> * gcc.dg/torture/pr37868.c: Skip for nds32*-*-*.
> * gcc.dg/torture/stackalign/builtin-apply-2.c: Skip for nds32*-*-*.
> * gcc.dg/tree-ssa/20040204-1.c: Expected fail for nds32*-*-*.
> * gcc.dg/tree-ssa/forwprop-28.c: Skip for nds32*-*-*.
> * gcc.dg/tree-ssa/pr42585.c: Skip for nds32*-*-*.
> * gcc.dg/tree-ssa/sra-12.c: Skip for nds32*-*-*.
> * gcc.target/nds32: New nds32 specific directory and testcases.
> * lib/target-supports.exp (check_profiling_available): Check for
> nds32*-*-elf.
>
>
> Is this patch OK for the trunk?
>
>
> Best regards,
> jasonwucj

Re: [PATCH, testsuite] Fix some testcases for nds32 target and provide new nds32 target specific tests

[Chung-Ju Wu]

On 11/30/13, 9:07 AM, Mike Stump wrote:
> On Nov 28, 2013, at 2:03 AM, Chung-Ju Wu  wrote:
>> There is a pending testsuite patch for nds32 target:
>>http://gcc.gnu.org/ml/gcc-patches/2013-11/msg01584.html
>>
>> Is it OK for trunk? :)
> 
> Ok, but please remove:
> 
>   { target nds32*-*-* }
> 

Ah... I see.  Since I have following code fragment in nds32.exp:

  # Exit immediately if this isn't a nds32 target.
  if ![istarget nds32*-*-*] then {
return
  }

all the "{ target nds32*-*-* }" from gcc.target test cases are unnecessary.

Thanks.  Remove it accordingly.


> from the gcc.target test cases, it is not redundant with the .exp file.
> 
> A few oddities I will note, if you can improve them… that'd be nice:
> 
>> +/* { dg-skip-if "Variadic funcs arguments will push by caller for current 
>> nds32 porting." { nds32*-*-* } } */
> 
> This is a bit weird.  There isn't a notion of current, there isn't a notion 
> of porting.  Variadic funcs arguments are caller pushed?
> 

There are two approaches to deal with variadic function arguments
and I had a post on:
  http://gcc.gnu.org/ml/gcc-help/2013-03/msg00208.html

So far, in the nds32 port, we are using the approach like aarch64/avr does.
This test case is almost the same as gcc/testsuite/gcc.dg/builtin-apply2.c file.
Perhaps I should have used the following description, which seems much better:

+/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args 
in registers." { nds32*-*-* } "*" "" } */


>> +/* { dg-skip-if "nds32 target has special operations for 64-bit behavior" { 
>> nds32*-*-* }  { "*" } { "" } } */
> 
> This is a bit weird.
> 

Oops, you are right.
That is a legacy modification which is not
suitable for the nds32 port on trunk.
Thanks for the catch.  I will not commit that bit.

Thank you for the review and approval.
Attachment is the revised patch and I will apply it
tomorrow if there is no other comment. :)


Best regards,
jasonwucj




diff --git gcc/testsuite/g++.dg/other/PR23205.C 
gcc/testsuite/g++.dg/other/PR23205.C
index e55710b..26a9dd5 100644
--- gcc/testsuite/g++.dg/other/PR23205.C
+++ gcc/testsuite/g++.dg/other/PR23205.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* 
hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* nds32*-*-* *-*-aix* 
alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */
 /* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types" } */
 
 const int foobar = 4;
diff --git gcc/testsuite/g++.dg/other/pr23205-2.C 
gcc/testsuite/g++.dg/other/pr23205-2.C
index 607e5a2..b25cb73 100644
--- gcc/testsuite/g++.dg/other/pr23205-2.C
+++ gcc/testsuite/g++.dg/other/pr23205-2.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* 
hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* nds32*-*-* *-*-aix* 
alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */
 /* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types 
-ftoplevel-reorder" } */
 
 const int foobar = 4;
diff --git gcc/testsuite/gcc.dg/20020312-2.c gcc/testsuite/gcc.dg/20020312-2.c
index 2999100..7562a8d 100644
--- gcc/testsuite/gcc.dg/20020312-2.c
+++ gcc/testsuite/gcc.dg/20020312-2.c
@@ -52,6 +52,8 @@ extern void abort (void);
 /* No pic register.  */
 #elif defined(__moxie__)
 /* No pic register.  */
+#elif defined(__nds32__)
+/* No pic register.  */
 #elif defined(__hppa__)
 /* PIC register is %r27 or %r19, but is used even without -fpic.  */
 #elif defined(__pdp11__)
diff --git gcc/testsuite/gcc.dg/builtin-apply2.c 
gcc/testsuite/gcc.dg/builtin-apply2.c
index 869f337..3ae2adc 100644
--- gcc/testsuite/gcc.dg/builtin-apply2.c
+++ gcc/testsuite/gcc.dg/builtin-apply2.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args 
in registers." { "aarch64*-*-* avr-*-* " } { "*" } { "" } } */
+/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args 
in registers." { "aarch64*-*-* avr-*-* nds32*-*-*" } { "*" } { "" } } */
 /* { dg-skip-if "Variadic funcs use Base AAPCS.  Normal funcs use VFP 
variant." { arm*-*-* && arm_hf_eabi } { "*" } { "" } } */
 
 /* PR target/12503 */
diff --git gcc/testsuite/gcc.dg/sibcall-3.c gcc/testsuite/gcc.dg/sibcall-3.c
index c4460e2..e02a410 100644
--- gcc/testsuite/gcc.dg/sibcall-3.c
+++ gcc/testsuite/g

Re: [PATCH, testsuite] Fix some testcases for nds32 target and provide new nds32 target specific tests

[Chung-Ju Wu]

2013/12/3 Mike Stump :
> On Dec 2, 2013, at 5:02 AM, Chung-Ju Wu  wrote:
>> Perhaps I should have used the following description, which seems much 
>> better:
>>
>> +/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have 
>> args in registers." { nds32*-*-* } "*" "" } */
>
> Reads nicely, thanks.  Also, if I do a port, and this test case fails, and I 
> read that and those facts apply to my port, I can just effortlessly go that 
> direction.  To me, this is the best use of this information.  Secondary would 
> be if people wanted to do a target_supports, it would be more clear to the 
> untrained why it was done in the first place.

Thanks for the guidance.
I learned how to make a better description for a test case. :-)

And thanks for the approval,
the revised patch is now applied as Rev. 205625:
  http://gcc.gnu.org/r205625


Best regards,
jasonwucj

Re: [PATCH, nds32] Missing target_cpu_default in TARGET_DEFAULT_TARGET_FLAGS.

[Chung-Ju Wu]

2013/12/11 Monk Chiang :
> Hi,
>
> Recently I used --target=nds32be-elf to configure nds32 gcc,
> it seems that the big endian is not set as default.
>
[...]
>
> The following is the patch to fix this issue.  Tested on nds32be-elf.
>
> OK to apply?
>
> Index: common/config/nds32/nds32-common.c
> ===
> --- common/config/nds32/nds32-common.c  (revision 205880)
> +++ common/config/nds32/nds32-common.c  (working copy)
> @@ -93,7 +93,8 @@
>   TARGET_CMOV : Generate conditional move instruction.  */

Could you also extend the comment about adding TARGET_CPU_DEFAULT?
That would be great to let other developers realize why we need it. :)

>  #undef TARGET_DEFAULT_TARGET_FLAGS
>  #define TARGET_DEFAULT_TARGET_FLAGS\
> -  (MASK_GP_DIRECT  \
> +  (TARGET_CPU_DEFAULT  \
> +   | MASK_GP_DIRECT\
> | MASK_16_BIT   \
> | MASK_PERF_EXT \
> | MASK_CMOV)

> Index: ChangeLog
> ===
> --- ChangeLog   (revision 205880)
> +++ ChangeLog   (working copy)
> @@ -1,3 +1,8 @@
> +2013-12-11  Monk Chiang 

In ChangeLog formatting, there should be two spaces between 'Chiang' and '<'.

> +
> +   * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS):
> +   Redefine.
> +

Suggest using 'Consider TARGET_CPU_DEFAULT settings.'

>  2013-12-11  Bin Cheng  
>

OK with those changes.

Thank you for the patch fixing that issue. :)


Best regards,
jasonwucj

Re: [PATCH, nds32] Missing target_cpu_default in TARGET_DEFAULT_TARGET_FLAGS.

[Chung-Ju Wu]

2013/12/17 Monk Chiang :
>
> I add comment to describe why I adding TARGET_CPU_DEFAULT,
> and fix typo in ChangeLog fle.
>
> Thank you for your suggestion.
>
> Index: ChangeLog
> ===
> --- ChangeLog   (revision 206039)
> +++ ChangeLog   (working copy)
> @@ -1,3 +1,8 @@
> +2013-12-17  Monk Chiang  
> +
> +   * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS):
> +   Consider TARGET_CPU_DEFAULT settings.
> +
>  2013-12-16  Jakub Jelinek  
>
> * predict.h (PROB_LIKELY): Fix the value.
> Index: common/config/nds32/nds32-common.c
> ===
> --- common/config/nds32/nds32-common.c  (revision 206039)
> +++ common/config/nds32/nds32-common.c  (working copy)
> @@ -86,14 +86,23 @@
>
>  /* Run-time Target Specification.  */
>
> -/* Default enable
> +/* The default target flags consist of
> +   TARGET_CPU_DEFAULT and other MASK_XXX flags.
> +
> +   The value of TARGET_CPU_DEFAULT is set by
> +   the process of 'configure' and 'make' stage.
> +   Please check gcc/config.gcc for more implementation detail.
> +
> +   Other MASK_XXX flags are set individually.
> +   By default we enable
>   TARGET_GP_DIRECT: Generate gp-imply instruction.
>   TARGET_16_BIT   : Generate 16/32 bit mixed length instruction.
>   TARGET_PERF_EXT : Generate performance extention instrcution.
>   TARGET_CMOV : Generate conditional move instruction.  */
>  #undef TARGET_DEFAULT_TARGET_FLAGS
>  #define TARGET_DEFAULT_TARGET_FLAGS\
> -  (MASK_GP_DIRECT  \
> +  (TARGET_CPU_DEFAULT  \
> +   | MASK_GP_DIRECT\
> | MASK_16_BIT   \
> | MASK_PERF_EXT \
> | MASK_CMOV)
>
>
> Monk

Thanks for your revised patch. :)

Committed as Rev.206106:
  http://gcc.gnu.org/r206106


Best regards,
jasonwucj

[PATCH, nds32] Committed: Fix inaccurate alignment checking when passing BLKmode argument.

[Chung-Ju Wu]

Hi, all,

There is a problem in nds32.h to determine available register number
for passing BLKmode argument.  The original checking only refers to
NDS32_NEED_N_REGS_FOR_ARG macro but that is not sufficient to make
decision of using odd or even register number.  It is supposed to
further check the type alignment.

We define a new macro NDS32_MODE_TYPE_ALIGN and rewrite
NDS32_AVAILABLE_REGNUM_FOR_ARG definition.

The patch for nds32.c and nds32.h is as follow:


Index: gcc/config/nds32/nds32.h
===
--- gcc/config/nds32/nds32.h(revision 206139)
+++ gcc/config/nds32/nds32.h(working copy)
@@ -126,6 +126,11 @@
 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 
+/* Get alignment according to mode or type information.
+   When 'type' is nonnull, there is no need to look at 'mode'.  */
+#define NDS32_MODE_TYPE_ALIGN(mode, type) \
+  (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
+
 /* Round X up to the nearest double word.  */
 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 
@@ -142,12 +147,18 @@
 /* This macro is used to return the register number for passing argument.
We need to obey the following rules:
  1. If it is required MORE THAN one register,
-make sure the register number is a even value.
+we need to further check if it really needs to be
+aligned on double words.
+  a) If double word alignment is necessary,
+ the register number must be even value.
+  b) Otherwise, the register number can be odd or even value.
  2. If it is required ONLY one register,
 the register number can be odd or even value.  */
-#define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type) \
-  ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)\
-   ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)\
+#define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type)  \
+  ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
+   ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)  \
+  ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)  \
+  : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))\
: ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 
 /* This macro is to check if there are still available registers

Index: gcc/config/nds32/nds32.c
===
--- gcc/config/nds32/nds32.c(revision 206139)
+++ gcc/config/nds32/nds32.c(working copy)
@@ -1438,8 +1438,8 @@
 {
   unsigned int align;
 
-  /* When 'type' is nonnull, there is no need to look at 'mode'.  */
-  align = (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode));
+  /* Pick up the alignment according to the mode or type.  */
+  align = NDS32_MODE_TYPE_ALIGN (mode, type);
 
   return (align > PARM_BOUNDARY);
 }
@@ -1853,10 +1853,10 @@
   if (NDS32_ARG_PASS_IN_REG_P (cum->reg_offset, mode, type))
 {
   /* Pick up the next available register number.  */
-  return gen_rtx_REG (mode,
- NDS32_AVAILABLE_REGNUM_FOR_ARG (cum->reg_offset,
- mode,
- type));
+  unsigned int regno;
+
+  regno = NDS32_AVAILABLE_REGNUM_FOR_ARG (cum->reg_offset, mode, type);
+  return gen_rtx_REG (mode, regno);
     }
   else
 {


And the gcc/ChangeLog is as below:

+2013-12-20  Chung-Ju Wu  
+
+   * config/nds32/nds32.h (NDS32_MODE_TYPE_ALIGN): New macro.
+   (NDS32_AVAILABLE_REGNUM_FOR_ARG): Use more accurate alignment checking
+   to determine available register number.
+   * config/nds32/nds32.c (nds32_needs_double_word_align): Use new
+   macro NDS32_MODE_TYPE_ALIGN.
+   (nds32_function_arg): Refine code layout.
+
 2013-12-19  Jeff Law  

* doc/invoke.texi: (dump-rtl-ree): Fix typo and clarify ree


Bootstrapped and tested on nds32le-elf/nds32be-elf target.
Committed as Rev.206142:
  http://gcc.gnu.org/r206142


Best regards,
jasonwucj

Re: [Patch] PR55189 enable -Wreturn-type by default

[Chung-Ju Wu]

2013/12/21 Sylvestre Ledru :
> Hello
>
> Following this thread http://gcc.gnu.org/ml/gcc/2013-11/msg00260.html
> and this bug,
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55189
>
> I would like to propose the two following patches:
>
> I am activating -Wreturn-type by defaut and add the option -Wmissing-return
>
[snip]
>
> Index: gcc/ChangeLog
> ===
> --- gcc/ChangeLog   (révision 206154)
> +++ gcc/ChangeLog   (copie de travail)
> @@ -1,3 +1,11 @@
> +2013-12-20  Sylvestre Ledru  
> +
> +PR target/55189
> +* -Wreturn-type enabled by default.
> +   * Introduce back the option -Wmissing-return (enabled by -Wall)
> +   It was included by default with -Wreturn-type
> +   * Update all tests failing because of these changes.
> +
>  2013-12-20  Eric Botcazou  
> * config/arm/arm.c (arm_expand_prologue): In a nested APCS frame with

Hi, Sylvestre,

Sorry I have no right to approve this patch.
But I notice your ChangeLog formatting is not correct.

You can refer to other entries in ChangeLog to refine yours,
and then resubmit the patch for review. :)


Best regards,
jasonwucj

[PATCH, nds32] Add -mext-perf, -mext-perf2, and -mext-string options.

[Chung-Ju Wu]

Hi, all,

This is the patch to add more nds32-specific options.
With those options, the extension instructions are able to be generated.

Committed as Rev.254798: http://gcc.gnu.org/r254798

gcc/
* config/nds32/nds32.opt: Add mext-perf, mext-perf2, mext-string.
* config/nds32/nds32.opt: Refine the layout.
* config/nds32/nds32.c (TARGET_EXT_PERF, TARGET_EXT_PERF2,
TARGET_EXT_STRING): Support new options.
* config/nds32/nds32.h: Likewise.
* config/nds32/nds32.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/constraints.md: Likewise.
* common/config/nds32/nds32-common.c: Likewise.

In addition, I only modify the files under nds32 directory in this patch.
I will create other patches for doc/invoke.texi and wwwdoc to describe
these new options soon.


Best regards,
jasonwucj
>From 2347e6efe69c32388cec09af310ebb02573ca749 Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Thu, 9 Nov 2017 20:28:40 +0800
Subject: [PATCH 1/7] Add new -mext-perf, -mext-perf2, and -mext-string
 options.

---
 gcc/common/config/nds32/nds32-common.c | 12 
 gcc/config/nds32/constraints.md|  4 ++--
 gcc/config/nds32/nds32-predicates.c|  6 +++---
 gcc/config/nds32/nds32.c   | 16 ---
 gcc/config/nds32/nds32.h   |  8 ++--
 gcc/config/nds32/nds32.md  |  8 
 gcc/config/nds32/nds32.opt | 36 --
 7 files changed, 66 insertions(+), 24 deletions(-)

diff --git a/gcc/common/config/nds32/nds32-common.c 
b/gcc/common/config/nds32/nds32-common.c
index 13cada6..65268df 100644
--- a/gcc/common/config/nds32/nds32-common.c
+++ b/gcc/common/config/nds32/nds32-common.c
@@ -97,14 +97,18 @@ static const struct default_options 
nds32_option_optimization_table[] =
 
Other MASK_XXX flags are set individually.
By default we enable
- TARGET_16_BIT   : Generate 16/32 bit mixed length instruction.
- TARGET_PERF_EXT : Generate performance extention instrcution.
- TARGET_CMOV : Generate conditional move instruction.  */
+ TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
+ TARGET_EXT_PERF   : Generate performance extention instrcution.
+ TARGET_EXT_PERF2  : Generate performance extention version 2 instrcution.
+ TARGET_EXT_STRING : Generate string extention instrcution.
+ TARGET_CMOV   : Generate conditional move instruction.  */
 #undef TARGET_DEFAULT_TARGET_FLAGS
 #define TARGET_DEFAULT_TARGET_FLAGS\
   (TARGET_CPU_DEFAULT  \
| MASK_16_BIT   \
-   | MASK_PERF_EXT \
+   | MASK_EXT_PERF \
+   | MASK_EXT_PERF2\
+   | MASK_EXT_STRING   \
| MASK_CMOV)
 
 #undef TARGET_HANDLE_OPTION
diff --git a/gcc/config/nds32/constraints.md b/gcc/config/nds32/constraints.md
index a92269f..891063f 100644
--- a/gcc/config/nds32/constraints.md
+++ b/gcc/config/nds32/constraints.md
@@ -213,12 +213,12 @@
 (define_constraint "Ixls"
   "The immediate value 0x01"
   (and (match_code "const_int")
-   (match_test "TARGET_PERF_EXT && (ival == 0x1)")))
+   (match_test "TARGET_EXT_PERF && (ival == 0x1)")))
 
 (define_constraint "Ix11"
   "The immediate value 0x7ff"
   (and (match_code "const_int")
-   (match_test "TARGET_PERF_EXT && (ival == 0x7ff)")))
+   (match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))
 
 (define_constraint "Ibms"
   "The immediate value with power of 2"
diff --git a/gcc/config/nds32/nds32-predicates.c 
b/gcc/config/nds32/nds32-predicates.c
index cc8ae55..b6cff20 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -335,7 +335,7 @@ nds32_can_use_bclr_p (int ival)
   one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival));
 
   /* 'bclr' is a performance extension instruction.  */
-  return (TARGET_PERF_EXT && (one_bit_count == 1));
+  return (TARGET_EXT_PERF && (one_bit_count == 1));
 }
 
 /* Function to check if 'bset' instruction can be used with IVAL.  */
@@ -350,7 +350,7 @@ nds32_can_use_bset_p (int ival)
   one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
 
   /* 'bset' is a performance extension instruction.  */
-  return (TARGET_PERF_EXT && (one_bit_count == 1));
+  return (TARGET_EXT_PERF && (one_bit_count == 1));
 }
 
 /* Function to check if 'btgl' instruction can be used with IVAL.  */
@@ -365,7 +365,7 @@ nds32_can_use_btgl_p (int ival)
   one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
 
   /* 'btgl' is a performance extension instruction.  */
-  return (TARGET_PERF_E

[PATCH, nds32] Remove the useless constant UNSPEC_VOLATILE_FUNC_RETURN.

[Chung-Ju Wu]

Hi, all,

The constant UNSPEC_VOLATILE_FUNC_RETURN is now useless
in current nds32 implementation.  Remove it.

Committed as Rev.254799: http://gcc.gnu.org/r254799

gcc/
* config/nds32/constants.md (UNSPEC_VOLATILE_FUNC_RETURN): Remove.



Best regards,
jasonwucj
>From 3bc69293a88b0614789be8f49d2ef2c28a8a99fe Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Thu, 9 Nov 2017 22:58:40 +0800
Subject: [PATCH 3/7] The FUNC_RETURN is useless in the current implementation.

---
 gcc/config/nds32/constants.md | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/config/nds32/constants.md b/gcc/config/nds32/constants.md
index e6f4a03..b45b1f7 100644
--- a/gcc/config/nds32/constants.md
+++ b/gcc/config/nds32/constants.md
@@ -32,7 +32,6 @@
 
 ;; The unspec_volatile operation index.
 (define_c_enum "unspec_volatile_element" [
-  UNSPEC_VOLATILE_FUNC_RETURN
   UNSPEC_VOLATILE_ISYNC
   UNSPEC_VOLATILE_ISB
   UNSPEC_VOLATILE_MFSR
-- 
1.8.3.1

[PATCH, nds332] Provide more constraints for future use.

[Chung-Ju Wu]

Hi, all,

This patch is to prepare more constraints in nds32 implementation.
They will be used in the future patch.

Committed as Rev.254800: http://gcc.gnu.org/r254800

gcc/
* config/nds32/constraints.md: Provide more constraints.
* config/nds32/nds32.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Define R5_REG, R8_REG, and FRAME_POINTER_REG to
support constraints usage.


Best regards,
jasonwucj
>From a3a77c515c52201de592ec641affc28f7020414f Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Sat, 11 Nov 2017 10:30:28 +0800
Subject: [PATCH 4/7] Provide more constraints for future use.

---
 gcc/config/nds32/constraints.md | 52 +
 gcc/config/nds32/nds32.h| 15 +---
 2 files changed, 64 insertions(+), 3 deletions(-)

diff --git a/gcc/config/nds32/constraints.md b/gcc/config/nds32/constraints.md
index 891063f..565fc3b 100644
--- a/gcc/config/nds32/constraints.md
+++ b/gcc/config/nds32/constraints.md
@@ -41,9 +41,52 @@
 (define_register_constraint "t" "R15_TA_REG"
   "Temporary Assist register $ta (i.e. $r15)")
 
+(define_register_constraint "e" "R8_REG"
+  "Function Entry register $r8)")
+
 (define_register_constraint "k" "STACK_REG"
   "Stack register $sp")
 
+(define_register_constraint "v" "R5_REG"
+  "Register $r5")
+
+(define_register_constraint "x" "FRAME_POINTER_REG"
+  "Frame pointer register $fp")
+
+(define_constraint "Iv00"
+  "Constant value 0"
+  (and (match_code "const_int")
+   (match_test "ival == 0")))
+
+(define_constraint "Iv01"
+  "Constant value 1"
+  (and (match_code "const_int")
+   (match_test "ival == 1")))
+
+(define_constraint "Iv02"
+  "Constant value 2"
+  (and (match_code "const_int")
+   (match_test "ival == 2")))
+
+(define_constraint "Iv04"
+  "Constant value 4"
+  (and (match_code "const_int")
+   (match_test "ival == 4")))
+
+(define_constraint "Iv08"
+  "Constant value 8"
+  (and (match_code "const_int")
+   (match_test "ival == 8")))
+
+(define_constraint "Iu01"
+  "Unsigned immediate 1-bit value"
+  (and (match_code "const_int")
+   (match_test "ival == 1 || ival == 0")))
+
+(define_constraint "Iu02"
+  "Unsigned immediate 2-bit value"
+  (and (match_code "const_int")
+   (match_test "ival < (1 << 2) && ival >= 0")))
 
 (define_constraint "Iu03"
   "Unsigned immediate 3-bit value"
@@ -103,6 +146,11 @@
(match_test "ival < (1 << 9) && ival >= 0")))
 
 
+(define_constraint "Is08"
+  "Signed immediate 8-bit value"
+  (and (match_code "const_int")
+   (match_test "ival < (1 << 7) && ival >= -(1 << 7)")))
+
 (define_constraint "Is10"
   "Signed immediate 10-bit value"
   (and (match_code "const_int")
@@ -113,6 +161,10 @@
   (and (match_code "const_int")
(match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
 
+(define_constraint "Is14"
+  "Signed immediate 14-bit value"
+  (and (match_code "const_int")
+   (match_test "ival < (1 << 13) && ival >= -(1 << 13)")))
 
 (define_constraint "Is15"
   "Signed immediate 15-bit value"
diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
index fb37c41..6954eec 100644
--- a/gcc/config/nds32/nds32.h
+++ b/gcc/config/nds32/nds32.h
@@ -613,8 +613,11 @@ enum nds32_builtins
 enum reg_class
 {
   NO_REGS,
+  R5_REG,
+  R8_REG,
   R15_TA_REG,
   STACK_REG,
+  FRAME_POINTER_REG,
   LOW_REGS,
   MIDDLE_REGS,
   HIGH_REGS,
@@ -629,8 +632,11 @@ enum reg_class
 #define REG_CLASS_NAMES \
 {   \
   "NO_REGS",\
+  "R5_REG", \
+  "R8_REG", \
   "R15_TA_REG", \
   "STACK_REG",  \
+  "FRAME_POINTER_REG",  \
   "LOW_REGS",   \
   "MIDDLE_REGS",\
   "HIGH_REGS",  \
@@ -641,9 +647,12 @@ enum reg_class
 
 #define REG_CLASS_CONTENTS \
 {\
-  {0x, 0x}, /* NO_REGS :  */ \
-  {0x8000, 0x}, /* R15_TA_REG  : 15   */ \
-  {0x8000, 0x}, /* STACK_REG   : 31   */ \
+  {0x, 0x}, /* NO_REGS*/ \
+  {0x0020, 0x}, /* R5_REG: 5  */ \
+  {0x0100, 0x}, /* R8_REG: 8  */ \
+  {0x8000, 0x}, /* R15_TA_REG: 15 */ \
+  {0x8000, 0x}, /* STACK_REG : 31 */ \
+  {0x1000, 0x}, /* FRAME_POINTER_REG : 28 */ \
   {0x00ff, 0x}, /* LOW_REGS: 0-7  */ \
   {0x000f0fff, 0x}, /* MIDDLE_REGS : 0-11, 16-19  */ \
   {0xfff07000, 0x}, /* HIGH_REGS   : 12-14, 20-31 */ \
-- 
1.8.3.1

[PATCH, nds32] Add nds32 vector modes.

[Chung-Ju Wu]

Hi, all,

This is the preparation for future nds32 vector implementation.

Committed as Rev.254853: http://gcc.gnu.org/r254853

gcc/
* config/nds32/nds32-modes.def: Add vector mode V4QI V2HI V8QI V4HI
V2SI.
* config/nds32/iterators.md: Add vector mode iterators and attributes.


Best regards,
jasonwucj
>From 61acc7f622e563d6b46e45b26ba1f03dcb61dcb5 Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Sun, 12 Nov 2017 16:18:39 +0800
Subject: [PATCH 5/7] Add nds32 vector modes.

---
 gcc/config/nds32/iterators.md| 17 -
 gcc/config/nds32/nds32-modes.def |  4 +++-
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/gcc/config/nds32/iterators.md b/gcc/config/nds32/iterators.md
index 0a8f5ae..fce5ab6 100644
--- a/gcc/config/nds32/iterators.md
+++ b/gcc/config/nds32/iterators.md
@@ -26,12 +26,24 @@
 ;; A list of integer modes that are up to one word long.
 (define_mode_iterator QIHISI [QI HI SI])
 
+;; A list of integer modes for one word and double word.
+(define_mode_iterator SIDI [SI DI])
+
 ;; A list of integer modes that are up to one half-word long.
 (define_mode_iterator QIHI [QI HI])
 
 ;; A list of the modes that are up to double-word long.
 (define_mode_iterator DIDF [DI DF])
 
+;; A list of the modes that are up to one word long vector.
+(define_mode_iterator VQIHI [V4QI V2HI])
+
+;; A list of the modes that are up to one word long vector
+;; and scalar for varies mode.
+(define_mode_iterator VSHI [V2HI HI])
+(define_mode_iterator VSQIHI [V4QI V2HI QI HI])
+(define_mode_iterator VSQIHIDI [V4QI V2HI QI HI DI])
+(define_mode_iterator VQIHIDI [V4QI V2HI DI])
 
 ;;
 ;; Mode attributes.
@@ -39,8 +51,11 @@
 
 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
 
-(define_mode_attr byte [(QI "1") (HI "2") (SI "4")])
+(define_mode_attr byte [(QI "1") (HI "2") (SI "4") (V4QI "4") (V2HI "4")])
+
+(define_mode_attr bits [(V4QI "8") (QI "8") (V2HI "16") (HI "16") (DI "64")])
 
+(define_mode_attr VELT [(V4QI "QI") (V2HI "HI")])
 
 ;;
 ;; Code iterators.
diff --git a/gcc/config/nds32/nds32-modes.def b/gcc/config/nds32/nds32-modes.def
index 295a709..6e76dd2 100644
--- a/gcc/config/nds32/nds32-modes.def
+++ b/gcc/config/nds32/nds32-modes.def
@@ -18,4 +18,6 @@
along with GCC; see the file COPYING3.  If not see
<http://www.gnu.org/licenses/>.  */
 
-/* So far, there is no need to define any modes for nds32 target.  */
+/* Vector modes.  */
+VECTOR_MODES (INT, 4);/*V4QI V2HI */
+VECTOR_MODES (INT, 8);/*V8QI V4HI V2SI */
-- 
1.8.3.1

[PATCH, nds32] Reserve more register numbers for new registers in the future.

[Chung-Ju Wu]

Hi, all,

There will new registers in nds32 target for floating point
and special purpose.  This patch is prepared for such changes.
We modify the FIRST_PSEUDO_REGISTER number and corresponding
register content.

Committed as Rev.254854: http://gcc.gnu.org/r254854

gcc/
* config/nds32/nds32.h (FIRST_PSEUDO_REGISTER): Modify.
(FIXED_REGISTERS): Reserve more register numbers.
(CALL_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(REGISTER_NAMES): Likewise.


Best regards,
jasonwucj
>From 1eaf9ddc17a3728294f6802a6d6cb4e8b4222c20 Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Sun, 12 Nov 2017 19:55:11 +0800
Subject: [PATCH 6/7] Reserve more register numbers for new registers in the
 future.

---
 gcc/config/nds32/nds32.h | 157 +++
 1 file changed, 104 insertions(+), 53 deletions(-)

diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
index 6954eec..9bb31c8 100644
--- a/gcc/config/nds32/nds32.h
+++ b/gcc/config/nds32/nds32.h
@@ -530,7 +530,7 @@ enum nds32_builtins
from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers.  */
-#define FIRST_PSEUDO_REGISTER 34
+#define FIRST_PSEUDO_REGISTER 101
 
 /* An initializer that says which registers are used for fixed
purposes all throughout the compiled code and are therefore
@@ -546,19 +546,33 @@ enum nds32_builtins
 
reserved for assembler : $r15
reserved for other use : $r24, $r25, $r26, $r27 */
-#define FIXED_REGISTERS \
-{ /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
-  0,  0,  0,  0,  0,  0,  0,  0,\
-  /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
-  0,  0,  0,  0,  0,  0,  0,  1,\
-  /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
-  0,  0,  0,  0,  0,  0,  0,  0,\
-  /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
-  1,  1,  1,  1,  0,  1,  0,  1,\
-  /* ARG_POINTER:32 */  \
-  1,\
-  /* FRAME_POINTER:33 */\
-  1 \
+#define FIXED_REGISTERS \
+{ /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
+  0,   0,   0,   0,   0,   0,   0,   0, \
+  /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
+  0,   0,   0,   0,   0,   0,   0,   1, \
+  /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
+  0,   0,   0,   0,   0,   0,   0,   0, \
+  /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
+  1,   1,   1,   1,   0,   1,   0,   1, \
+  /* AP   FPReserved */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1 \
 }
 
 /* Identifies the registers that are not available for
@@ -567,33 +581,53 @@ enum nds32_builtins
 
0 : callee-save registers
1 : caller-save registers */
-#define CALL_USED_REGISTERS \
-{ /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
-  1,  1,  1,  1,  1,  1,  0,  0,\
-  /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
-  0,  0,  0,  0,  0,  0,  0,  1,\
-  /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
-  1,  1,  1,  1,  1,  1,  1,  1,\
-  /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
-  1,  1,  1,  1,  0,  1,  0,  1,\
-  /* ARG_POINTER:32 */  \
-  1,\
-  /* FRAME_POINTER:33 */\
-  1 \
+#define CALL_USED_REGISTERS \
+{ /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
+  1,   1,   1,   1,   1,   1,   0,   0, \
+  /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
+  0,   0,   0,   0,   0,   0,   0,   1, \
+  /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
+  1,   1,   1,   1,   0,   1,   0,   1, \
+  /* AP   FPReserved */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1,   1,   1,   1,   1,   1,   1, \
+  /* Reserved... */ \
+  1,   1, 

[PATCH, doc] NDS32: Add -mext-perf -mext-perf2 and -mext-string in the documentation

[Chung-Ju Wu]

Hi, all,

In this patch of nds32 port:
https://gcc.gnu.org/ml/gcc-patches/2017-11/msg01585.html

We add new options for NDS32 target.
So we need to update documentation as well.
The patch is attached and the plaintext ChangeLog is as follow:

gcc/ChangeLog

* doc/invoke.texi (NDS32 Options): Add -mext-perf, -mext-perf2 and
-mext-string options.


Committed as https://gcc.gnu.org/r256564

I will also cover these changes in the release notes at
htdocs/gcc-8/changes.html with another wwwdoc patch soon.

Best regards,
jasonwucj
>From 8b225b1b3f3b425ea180ba4a932e4201a95903c0 Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu 
Date: Fri, 10 Nov 2017 11:42:00 +0800
Subject: [PATCH] Add new nds32 options "-mext-perf", "-mext-perf2", and
 "-mext-string" in the documentation.

---
 gcc/doc/invoke.texi | 24 +---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c443c66..a9449a8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -941,7 +941,9 @@ Objective-C and Objective-C++ Dialects}.
 @gccoptlist{-mbig-endian  -mlittle-endian @gol
 -mreduced-regs  -mfull-regs @gol
 -mcmov  -mno-cmov @gol
--mperf-ext  -mno-perf-ext @gol
+-mext-perf  -mno-ext-perf @gol
+-mext-perf2  -mno-ext-perf2 @gol
+-mext-string  -mno-ext-string @gol
 -mv3push  -mno-v3push @gol
 -m16bit  -mno-16bit @gol
 -misr-vector-size=@var{num} @gol
@@ -21304,14 +21306,30 @@ Generate conditional move instructions.
 @opindex mno-cmov
 Do not generate conditional move instructions.
 
-@item -mperf-ext
+@item -mext-perf
 @opindex mperf-ext
 Generate performance extension instructions.
 
-@item -mno-perf-ext
+@item -mno-ext-perf
 @opindex mno-perf-ext
 Do not generate performance extension instructions.
 
+@item -mext-perf2
+@opindex mperf-ext
+Generate performance extension 2 instructions.
+
+@item -mno-ext-perf2
+@opindex mno-perf-ext
+Do not generate performance extension 2 instructions.
+
+@item -mext-string
+@opindex mperf-ext
+Generate string extension instructions.
+
+@item -mno-ext-string
+@opindex mno-perf-ext
+Do not generate string extension instructions.
+
 @item -mv3push
 @opindex mv3push
 Generate v3 push25/pop25 instructions.
-- 
1.8.3.1

[PATCH, wwwdocs] Update GCC 8 release notes for NDS32 port

[Chung-Ju Wu]

Hi, Gerald,

In previous patch we add new options for NDS32 port:
  https://gcc.gnu.org/ml/gcc-patches/2018-01/msg01397.html

So I think I need to update GCC 8 release notes as well.


Index: htdocs/gcc-8/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-8/changes.html,v
retrieving revision 1.30
diff -u -r1.30 changes.html
--- htdocs/gcc-8/changes.html   21 Jan 2018 20:01:31 -  1.30
+++ htdocs/gcc-8/changes.html   22 Jan 2018 06:28:56 -
@@ -348,7 +348,13 @@
 
 
 
-

+NDS32
+
+  
+New command-line options -mext-perf -mext-perf2 -mext-string
+have been added for performance extension instructions.
+  
+
 
 Nios II

 


Is this patch OK?


Best regards,
jasonwucj

Re: [PATCH, wwwdocs] Update GCC 8 release notes for NDS32 port

[Chung-Ju Wu]

Gerald Pfeifer on 2018/1/23 22:39 wrote:

On Tue, 23 Jan 2018, Chung-Ju Wu wrote:

+New command-line options -mext-perf -mext-perf2 -mext-string


Can you write this as

   "...-mext-perf, -mext-perf2, and
   -mext-string..."

please?

Approved with that change.



Thank you for the review. :)

I made the change and committed it as revision 1.33 of 
htdosc/gcc-8/changes.html.


Best regards,
jasonwucj



Gerald

[NDS32, committed] Add missing newline character into ASM_APP_ON macro.

[Chung-Ju Wu]

Hi, all,

For nds32 inline assembly code output, a newline character was missing.
The following commit is to fix the issue.


Committed as Rev.259642: https://gcc.gnu.org/r259642

gcc/
* config/nds32/nds32.h (ASM_APP_ON): Add missing newline character.


Best regards,
jasonwucj

[NDS32, committed] Fix print operand for cctl register.

[Chung-Ju Wu]

Hi, all,

There was an error in nds32_print_operand() to output
cctl register.  It would be better to set value earlier.
The following commit is to fix such issue.

Committed as Rev.259643: https://gcc.gnu.org/r259643

gcc/
* config/nds32/nds32.c (nds32_print_operand): Set op_value earlier.



Best regards,
jasonwucj

[NDS32, committed] Fix incorrect settings in sfp-machine.h and t-nds32-newlib for hard fp.

[Chung-Ju Wu]

Hi, all,

For nds32 NDS32_ABI_2FP_PLUS abi design,
some settings and compilation options are required to be adjusted
so that we can build correct libgcc.a library.

Committed as Rev.259645: https://gcc.gnu.org/r259645

libgcc/
* config/nds32/sfp-machine.h: Fix settings for NDS32_ABI_2FP_PLUS.
* config/nds32/t-nds32-newlib (HOST_LIBGCC2_CFLAGS): Use -fwrapv.


Best regards,
jasonwucj

[NDS32, committed] Split movdi/df if reigster number is illegal.

[Chung-Ju Wu]

Hi, all,

We have to split move_di/df pattern when hard register is odd
so that the wrong assembly code can be avoided.

Committed as Rev.259646: https://gcc.gnu.org/r259646

gcc/
* config/nds32/nds32-doubleword.md: New define_split pattern for
illegal register number.


Best regards,
jasonwucj

[NDS32, committed] Fix bug in bit-instruction checking functions.

[Chung-Ju Wu]

Hi, all,

In the implementation of nds32_can_use_bclr_p(), nds32_can_use_bset_p(),
and nds32_can_use_btgl_p(), we better use HOST_WIDE_INT type and GET_MODE_MASK()
so that the mask would be good for the bit-operation checking.


Committed as Rev.259647: https://gcc.gnu.org/r259647

gcc/
* config/nds32/nds32-predicates.c (nds32_can_use_bclr_p): Mask with
GET_MODE_MASK before any checking.
(nds32_can_use_bset_p): Likewise.
(nds32_can_use_btgl_p): Likewise.


Best regards,
jasonwucj

Re: [PATCH] Fix comment typo in ira.c

[Chung-Ju Wu]

2014-08-19 22:04 GMT+08:00 Vladimir Makarov :
> On 08/18/2014 10:51 AM, Kito Cheng wrote:
>> Hi Vladimir:
>>
>> Here is a tiny typo in comment, allono -> allocno.
>>
>> ChangLog
>> 2014-08-18  Kito Cheng  
>>
>> * ira.c: Fix typo in comment.
> Thanks, Kito.  Of course, the patch is ok.  You can commit it if it is
> not committed yet.
>

It seems that Kito has not got his svn write access yet.
I can help him to commit this patch.

Committed as Rev.214404.
  https://gcc.gnu.org/r214404


Best regards,
jasonwucj

Re: [PATCH] Remove CALLER_SAVE_PROFITABLE since nobody use it now

[Chung-Ju Wu]

2014-08-22 1:45 GMT+08:00 Joseph S. Myers :
> On Thu, 21 Aug 2014, Richard Earnshaw wrote:
>
>> On 19/08/14 15:24, Kito Cheng wrote:
>> > Hi Richard:
>> >> Hmm, I'm not sure about this.  It might not be used at present, but on:
>> >> AArch64, with more call-clobbered registers than call-saved registers, I
>> >> would expect this ought to be a win.  The fact that it isn't on today
>> >> may say more about the way it works than the concept that it's the wrong
>> >> thing to do in principle.
>> >
>> > In my view, calculate cost/profit should be done by register allocator 
>> > instead
>> > of a target hook/marco is more reasonable since register allocator can
>> > have more globe view to it, and IRA do it now.
>> >
>> > And as Joseph say, no code calling it, so I think it's time to remove it.
>> > thanks for your comment :)
>>
>> Objection withdrawn.
>
> Thanks.  The patch is OK.
>

Hi, Joseph,

Kito talked to me that he has signed FSF agreement
but has not got his svn write access yet.
So I help to commit this patch for him (Rev.214405).
  https://gcc.gnu.org/r214405

I think he needs to finish this form
https://sourceware.org/cgi-bin/pdw/ps_form.cgi
so that he can commit patches on his own in the future.
Could Kito list you as the one who approve his write access request?
Or could you suggest someone who may help with it? :)


Best regards,
jasonwucj


> --
> Joseph S. Myers
> jos...@codesourcery.com

Re: [PATCH 142/236] config/nds32: Use rtx_insn

[Chung-Ju Wu]

2014-08-07 1:22 GMT+08:00 David Malcolm :
> gcc/
> * config/nds32/nds32-protos.h (nds32_adjust_insn_length):
> Strengthen first param from rtx to rtx_insn *.
> * config/nds32/nds32.c (nds32_adjust_insn_length): Likewise for
> param "insn".
> ---
>  gcc/config/nds32/nds32-protos.h | 2 +-
>  gcc/config/nds32/nds32.c| 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h
> index 6d94027..ddcec9c 100644
> --- a/gcc/config/nds32/nds32-protos.h
> +++ b/gcc/config/nds32/nds32-protos.h
> @@ -92,7 +92,7 @@ extern int nds32_can_use_bitci_p (int);
>
>  /* Auxiliary function for 'Computing the Length of an Insn'.  */
>
> -extern int nds32_adjust_insn_length (rtx, int);
> +extern int nds32_adjust_insn_length (rtx_insn *, int);
>
>  /* Auxiliary functions for FP_AS_GP detection.  */
>
> diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
> index 47b1318..47e5ae4 100644
> --- a/gcc/config/nds32/nds32.c
> +++ b/gcc/config/nds32/nds32.c
> @@ -4412,7 +4412,7 @@ nds32_valid_stack_push_pop (rtx op, bool push_p)
> Modifies the length assigned to instruction INSN.
> LEN is the initially computed length of the insn.  */
>  int
> -nds32_adjust_insn_length (rtx insn, int length)
> +nds32_adjust_insn_length (rtx_insn *insn, int length)
>  {
>rtx src, dst;
>
> --

The changes in nds32 part are obvious to me.
I will check bootstrap and regression if there is any problem.

Thank you, David. :)


Best reagrds,
jasonwucj

[PATCH 01/18, nds32] Define PIC_OFFSET_TABLE_REGNUM to $gp register.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214849: https://gcc.gnu.org/r214849


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.h (PIC_OFFSET_TABLE_REGNUM): Define.


Best regards,
jasonwucj


0001-PATCH-01-Define-PIC_OFFSET_TABLE_REGNUM-to-gp-regist.patch
Description: Binary data

[PATCH 02/18, nds32] Refine the implementation and consider CFA restore information for stack push/pop multiple.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214851: https://gcc.gnu.org/r214851


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_gen_stack_push_multiple): Rename to ...
(nds32_emit_stack_push_multiple): ... this.
(nds32_gen_stack_pop_multiple): Rename to ...
(nds32_emit_stack_pop_multiple): ... this and consider CFA restore
information.


Best regards,
jasonwucj


0002-PATCH-02-Refine-the-implementation-and-consider-CFA-.patch
Description: Binary data

[PATCH 03/18, nds32] Refine the implementation and consider CFA restore information for stack v3push/v3pop.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214852: https://gcc.gnu.org/r214852


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_gen_stack_v3push): Rename to ...
(nds32_emit_stack_v3push): ... this.
(nds32_gen_stack_v3pop): Rename to ...
(nds32_emit_stack_v3pop): ... this and consider CFA restore
information.


Best regards,
jasonwucj


0003-PATCH-03-Refine-the-implementation-and-consider-CFA-.patch
Description: Binary data

[PATCH 04/18, nds32] In nds32_valid_stack_push_pop_p(), we look into OP rtx to see if we indeed save $fp/$gp/$lp registers.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214853: https://gcc.gnu.org/r214853


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32-predicates.c
(nds32_valid_stack_push_pop): Rename to ...
(nds32_valid_stack_push_pop_p): ... this.
* config/nds32/nds32-protos.h: Likewise.
* config/nds32/predicates.md: Likewise.


Best regards,
jasonwucj


0004-PATCH-04-In-nds32_valid_stack_push_pop_p-we-look-int.patch
Description: Binary data

[PATCH 05/18, nds32] Preparation in nds32.h of using registers to save varargs.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214854: https://gcc.gnu.org/r214854


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.h (machine_function): Add some fields for
variadic arguments implementation.


Best regards,
jasonwucj


0005-PATCH-05-Preparation-in-nds32.h-of-using-registers-t.patch
Description: Binary data

[PATCH 06/18, nds32] Add a function to indentify if FUNC is a interrupt service routine.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214855: https://gcc.gnu.org/r214855


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32-isr.c (nds32_isr_function_p): Define new function
to check if FUNC is an interrupt service routine.
* config/nds32/nds32-protos.h (nds32_isr_function_p): Declaration.


Best regards,
jasonwucj


0006-PATCH-06-Add-a-function-to-indentify-if-FUNC-is-a-in.patch
Description: Binary data

[PATCH 07/18, nds32] Consider varargs situation when creating stack operation assembly code.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214856: https://gcc.gnu.org/r214856


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32-md-auxiliary.c (nds32_output_stack_push):
Check rtx for varargs implementation.
(nds32_output_stack_pop): Likewise.
* config/nds32/nds32-protos.h: Have a rtx argument for
nds32_output_stack_push and nds32_output_stack_pop.
* config/nds32/nds32.md: Likewise.


Best regards,
jasonwucj


0007-PATCH-07-Consider-varargs-situation-when-creating-st.patch
Description: Binary data

[PATCH 08/18, nds32] We need to make sure it is NOT a variadic function so that some v3push/v3pop preparation can be applied.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214857: https://gcc.gnu.org/r214857


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_compute_stack_frame): Do not use
v3push/v3pop for variadic function.
* config/nds32/nds32.md (prologue, epilogue): Likewise.


Best regards,
jasonwucj


0008-PATCH-08-We-need-to-make-sure-it-is-NOT-a-variadic-f.patch
Description: Binary data

[PATCH 09/18, nds32] Remove unused variables.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214858: https://gcc.gnu.org/r214858


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_expand_prologue): Remove unused variables.
(nds32_expand_epilogue): Likewise.
(nds32_expand_prologue_v3push): Likewise.
(nds32_expand_epilogue_v3pop): Likewise.


Best regards,
jasonwucj


0009-PATCH-09-Remove-unused-variables.patch
Description: Binary data

[PATCH 10/18, nds32] Define and rename some GPR-specific stuff.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214859: https://gcc.gnu.org/r214859


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_function_arg): Define and rename some
GPR-specific stuff.
(nds32_function_arg_advance): Likewise.
(nds32_init_cumulative_args): Likewise.
* config/nds32/nds32.h (NDS32_MAX_GPR_REGS_FOR_ARGS): Define.
(NDS32_FIRST_GPR_REGNUM): Define.
(NDS32_LAST_GPR_REGNUM): Define.
(NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG): Define.
(NDS32_ARG_PASS_IN_REG_P): Use NDS32_MAX_GPR_REGS_FOR_ARGS.
(FUNCTION_ARG_REGNO_P): Use NDS32_MAX_GPR_REGS_FOR_ARGS.
(machine_function): Use GRP-specific stuff.


Best regards,
jasonwucj


0010-PATCH-10-Define-and-rename-some-GPR-specific-stuff.patch
Description: Binary data

[PATCH 11/18, nds32] Implement TARGET_SETUP_INCOMING_VARARGS target hook.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214861: https://gcc.gnu.org/r214861


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_setup_incoming_varargs): New
implementation for TARGET_SETUP_INCOMING_VARARGS.
(nds32_strict_argument_naming): Refine comment.
* config/nds32/nds32.h (TARGET_SOFT_FLOAT, TARGET_HARD_FLOAT):
Define for future implementation.


Best regards,
jasonwucj


0011-PATCH-11-Implement-TARGET_SETUP_INCOMING_VARARGS-tar.patch
Description: Binary data

[PATCH 12/18, nds32] Prepare necessary varargs information in compute_stack_frame().

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214862: https://gcc.gnu.org/r214862


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_compute_stack_frame): Prepare necessary
varargs information.


Best regards,
jasonwucj


0012-PATCH-12-Prepare-necessary-varargs-information-in-co.patch
Description: Binary data

[PATCH 13/18, nds32] Since argument pointer must be 8-byte alignment, our first parameter may require 4-byte offset if pushed varargs is not 8-byte aligned.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214863: https://gcc.gnu.org/r214863


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.h (FIRST_PARM_OFFSET): Set proper location
according to the value of crtl->args.pretend_args_size.


Best regards,
jasonwucj


0013-PATCH-13-Since-argument-pointer-must-be-8-byte-align.patch
Description: Binary data

[PATCH 14/18, nds32] Deal with nameless arguments in nds32_function_arg() and nds32_function_arg_advance().

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214865: https://gcc.gnu.org/r214865


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_function_arg): Deal with nameless
arguments.
(nds32_function_arg_advance): Deal with nameless arguments.
* config/nds32/nds32.h (NDS32_ARG_PASS_IN_REG_P): Split it into ...
(NDS32_ARG_ENTIRE_IN_GPR_REG_P): ... this one and ...
(NDS32_ARG_PARTIAL_IN_GPR_REG_P): ... this one.


Best regards,
jasonwucj


0014-PATCH-14-Deal-with-nameless-arguments-in-nds32_funct.patch
Description: Binary data

[PATCH 15/18, nds32] Since we are going to provide new heuristic for fp-as-gp optimization, we better not to set cfun->machine->fp_as_gp_p at prologue expanding.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214866: https://gcc.gnu.org/r214866


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_expand_prologue): Suppress fp-as-gp
optimization detection.


Best regards,
jasonwucj


0015-PATCH-15-Since-we-are-going-to-provide-new-heuristic.patch
Description: Binary data

[PATCH 16/18, nds32] Emit stack push instructions for varargs at prologue stage and emit stack adjustment instructions for varargs at epilogue stage.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214867: https://gcc.gnu.org/r214867


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_expand_prologue): Emit stack push
instructions for varargs implementation.
(nds32_expand_epilogue): Emit stack adjustment instructions for
varargs implementation.


Best regards,
jasonwucj


0016-PATCH-16-Emit-stack-push-instructions-for-varargs-at.patch
Description: Binary data

[PATCH 17/18, nds32] Provide TARGET_ARG_PARTIAL_BYTES so that we can have structure argument partially in registers and stack.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214868: https://gcc.gnu.org/r214868


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_arg_partial_bytes): New implementation
for TARGET_ARG_PARTIAL_BYTES.


Best regards,
jasonwucj


0017-PATCH-17-Provide-TARGET_ARG_PARTIAL_BYTES-so-that-we.patch
Description: Binary data

[PATCH 18/18, nds32] No need to take padding into consideration in Andes ABI2 because we can pass arguments in registers for variadic function.

[Chung-Ju Wu]

Hi, all,

Committed as Rev. 214869: https://gcc.gnu.org/r214869


gcc/ChangeLog

2014-09-03  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_must_pass_in_stack): New implementation
for TARGET_MUST_PASS_IN_STACK.


Best regards,
jasonwucj


0018-PATCH-18-No-need-to-take-padding-into-consideration-.patch
Description: Binary data

[PATCH 00/18, nds32] Committed: Fix incompatible ABI implementation for variadic function.

[Chung-Ju Wu]

Hi, all,

The variadic function ABI implmentation of current nds32 port on trunk
is incompatible to the past Andes toolchains.  Fixing it requires many
changes on the different files.  I split these changes into several
patches so that we can precisely describe the purpose of each
implementation in detail.

The following is a series of patches:

[01/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00293.html
[02/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00294.html
[03/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00295.html
[04/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00296.html
[05/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00297.html
[06/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00300.html
[07/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00301.html
[08/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00302.html
[09/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00304.html
[10/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00305.html
[11/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00306.html
[12/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00308.html
[13/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00309.html
[14/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00311.html
[15/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00312.html
[16/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00313.html
[17/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00314.html
[18/18] https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00315.html


Best regards,
jasonwucj

[PATCH, testsuite] Fix some testcases for nds32 target and provide new nds32 target specific tests

[Chung-Ju Wu]

Hi, Mike,

Recently the new nds32 port is approved and I committed it into trunk.
According to gcc testsuite report on:
  http://gcc.gnu.org/ml/gcc-testresults/2013-11/msg00751.html
  http://gcc.gnu.org/ml/gcc-testresults/2013-11/msg00752.html

I would like to modify some testcases for nds32 target.
Also I have some nds32 target specific tests which is
suggested by Joseph earlier:
  http://gcc.gnu.org/ml/gcc-patches/2013-07/msg00396.html

The patch is attached and a ChangeLog is as below:

gcc/testsuite/
2013-11-14  Chung-Ju Wu  

* g++.dg/other/PR23205.C: Skip for nds32*-*-*.
* g++.dg/other/pr23205-2.C: Skip for nds32*-*-*.
* gcc.dg/20020312-2.c: Add __nds32__ case.
* gcc.dg/builtin-apply2.c: Skip for nds32*-*-*.
* gcc.dg/lower-subreg-1.c: Skip for nds32*-*-*.
* gcc.dg/sibcall-3.c: Expected fail for nds32*-*-*.
* gcc.dg/sibcall-4.c: Expected fail for nds32*-*-*.
* gcc.dg/stack-usage-1.c (SIZE): Define case for __nds32__.
* gcc.dg/torture/pr37868.c: Skip for nds32*-*-*.
* gcc.dg/torture/stackalign/builtin-apply-2.c: Skip for nds32*-*-*.
* gcc.dg/tree-ssa/20040204-1.c: Expected fail for nds32*-*-*.
* gcc.dg/tree-ssa/forwprop-28.c: Skip for nds32*-*-*.
* gcc.dg/tree-ssa/pr42585.c: Skip for nds32*-*-*.
* gcc.dg/tree-ssa/sra-12.c: Skip for nds32*-*-*.
* gcc.target/nds32: New nds32 specific directory and testcases.
* lib/target-supports.exp (check_profiling_available): Check for
nds32*-*-elf.


Is this patch OK for the trunk?


Best regards,
jasonwucj


nds32-testsuite.patch
Description: Binary data

Re: wide-int, nds32

[Chung-Ju Wu]

2013/11/24 Mike Stump :
> Richi has asked the we break the wide-int patch so that the individual port 
> and front end maintainers can review their parts without have to go through 
> the entire patch.This patch covers the nds32 port.
>
> Ok?
>

OK.

The changes are straightforward on using wide-int interface.
Thanks for the patch! :-)


Best regards,
jasonwucj

Re: [PATCH] Don't call init_caller_save if LRA enabled

[Chung-Ju Wu]

2014-06-06 21:37 GMT+08:00 Vladimir Makarov :
> On 2014-06-04, 12:31 PM, Kito Cheng wrote:
>>
>> LRA generate caller-save register store/restore during split register,
>> not generate by caller-save.c:save_call_clobbered_regs, so initialize
>> this module by init_caller_save is meaningless if LRA enabled
>>
>> 2014-06-05  Kito Cheng  
>>
>>   * ira.c (ira): Don't call init_caller_save if LRA enabled
>>   since LRA use its own infrastructure to handle that.
>>
>>
>
> The patch is ok.  As I remember changelog entries should contain what is
> done but not why it is done.  But I guess this entry is ok too as it is
> still very brief.
>
> Kito, thanks for fixing it.  You can commit it into the trunk.
>
>

It seems that Kito hasn't got his commit right yet.
I can help commit this patch.

Committed as Rev. 211364
  http://gcc.gnu.org/r211364


Best regards,
jasonwucj

[PATCH 01/09, nds32] Committed: Add several new files for preparation of providing modules that are going to be separated from nds32.c source.

[Chung-Ju Wu]

Hi,

This patch is the preparation for subsquent patches of modules
implementation.  In addition to create several empty source files,
we also need to modify config.gcc and provide t-nds32 makefile fragment.

Committed as Rev.212280.
  https://gcc.gnu.org/r212280


Best regards,
jasonwucj

[PATCH 02/09, nds32] Committed: Move ISR impelentation to nds32-isr.c module.

[Chung-Ju Wu]

Hi,

There are many helper functions implemented in nds32.c to
deal with interrupt service routine code generation.
We move all of them into nds32-isr.c module.

Committed as Rev.212281.
  https://gcc.gnu.org/r212281


Best regards,
jasonwucj

[PATCH 03/09, nds32] Committed: Move builtin functions implementation to nds32-intrinsic.c module.

[Chung-Ju Wu]

Hi,

For supporting target specific builtin functions,
we use an individual nds32-intrinsic.c module to implement
essential and helpler functions.

Committed as Rev.212282.
  https://gcc.gnu.org/r212282


Best regards,
jasonwucj

Re: [PATCH 01/09, nds32] Committed: Add several new files for preparation of providing modules that are going to be separated from nds32.c source.

[Chung-Ju Wu]

2014-07-04 18:47 GMT+08:00 Chung-Ju Wu :
> Hi,
>
> This patch is the preparation for subsquent patches of modules
> implementation.  In addition to create several empty source files,
> we also need to modify config.gcc and provide t-nds32 makefile fragment.
>
> Committed as Rev.212280.
>   https://gcc.gnu.org/r212280
>

Sorry I forgot to attach patch in the previous mail.


Best regards,
jasonwucj


0001-PATCH-01-Add-several-new-files-for-preparation-of-pr.patch
Description: Binary data

Re: [PATCH 02/09, nds32] Committed: Move ISR impelentation to nds32-isr.c module.

[Chung-Ju Wu]

2014-07-04 18:48 GMT+08:00 Chung-Ju Wu :
> Hi,
>
> There are many helper functions implemented in nds32.c to
> deal with interrupt service routine code generation.
> We move all of them into nds32-isr.c module.
>
> Committed as Rev.212281.
>   https://gcc.gnu.org/r212281
>

Sorry I forgot to attach patch in the previous mail.


Best regards,
jasonwucj


0002-PATCH-02-Move-ISR-impelentation-to-nds32-isr.c-modul.patch
Description: Binary data

Re: [PATCH 03/09, nds32] Committed: Move builtin functions implementation to nds32-intrinsic.c module.

[Chung-Ju Wu]

2014-07-04 18:50 GMT+08:00 Chung-Ju Wu :
> Hi,
>
> For supporting target specific builtin functions,
> we use an individual nds32-intrinsic.c module to implement
> essential and helpler functions.
>
> Committed as Rev.212282.
>   https://gcc.gnu.org/r212282
>

Sorry I forgot to attach patch in the previous mail.


Best regards,
jasonwucj


0003-PATCH-03-Move-builtin-functions-implementation-to-nd.patch
Description: Binary data

[PATCH 04/09, nds32] Committed: Move some helper functions of predicates and constraints to nds32-predicates.c module.

[Chung-Ju Wu]

Hi,

Many external functions are used in predicates and constraints checking.
We move all of them into nds32-predicates.c module so that we
can easily maintain those implementation in the future.

Committed as Rev.212283.
  https://gcc.gnu.org/r212283


Best regards,
jasonwucj


0004-PATCH-04-Move-some-helper-functions-of-predicates-an.patch
Description: Binary data

[PATCH 05/09, nds32] Committed: Move cost calculation to nds32-cost.c module.

[Chung-Ju Wu]

Hi,

We provide a nds32-cost.c module to maintain some cost implementation
required by target hooks and macros.  Currently we only migrate
nds32_rtx_costs()
and nds32_address_cost() into the module.

Committed as Rev.212284.
  https://gcc.gnu.org/r212284


Best regards,
jasonwucj


0005-PATCH-05-Move-cost-calculation-to-nds32-cost.c-modul.patch
Description: Binary data

[PATCH 06/09, nds32] Committed: Preparation of nds32-pipelines-auxiliary.c module for future implementation.

[Chung-Ju Wu]

Hi,

The module is prepared for future implementation of pipeline models.
In this patch we only add a few comment to describe its purpose.

Committed as Rev.212285.
  https://gcc.gnu.org/r212285


Best regards,
jasonwucj


0006-PATCH-06-Preparation-of-nds32-pipelines-auxiliary.c-.patch
Description: Binary data

[PATCH 08/09, nds32] Committed: Move memory related implementation to nds32-memory-manipulation.c module.

[Chung-Ju Wu]

Hi,

The multiple load/store instructions are provided by nds32 target and
some memory access behaviors are able to utilize such instuctions.
We use nds32-memory-manipulation.c module to hold those memory related
implementation.

Committed as Rev.212287.
  https://gcc.gnu.org/r212287


Best regards,
jasonwucj


0008-PATCH-08-Move-memory-related-implementation-to-nds32.patch
Description: Binary data

[PATCH 09/09, nds32] Committed: Move fp-as-gp optimization to nds32-fp-as-gp.c module.

[Chung-Ju Wu]

Hi,

There is a target specific optimization, called fp-as-gp optimization,
in the nds32 port.  We are planning to make it as an individual pass.
By now we just move related implementation into nds32-fp-as-gp.c module.

Committed as Rev.212288.
  https://gcc.gnu.org/r212288


Best regards,
jasonwucj


0009-PATCH-09-Move-fp-as-gp-optimization-to-nds32-fp-as-g.patch
Description: Binary data

[PATCH 00/09, nds32] Provide individual modules as assistance to nds32.c implementation.

[Chung-Ju Wu]

Hi, all,

In the nds32 port, we are expecting the implementation in nds32.c
is going to gradually grow up.  For the sake of future maintenance,
we decide to provide individual modules and then migrate some
implementation from nds32.c into the modules.

The following is a series of patches:
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00293.html
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00295.html
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00296.html
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00298.html
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00299.html
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00300.html
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00301.html
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00302.html
  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00303.html

I would like to thank Kito, Monk, and Ling-Hua, to help me separate
the nds32.c content.  So I also list them as contributors in the ChangeLog.
Thank you all, and we are looking forward to have more patches to make
nds32 port better.


Best regards,
jasonwucj

[PATCH, nds32] Committed: Complete -march= option design.

[Chung-Ju Wu]

Hi, all,

When the help option --target-help is issued, the available items
for -march=X are supposed to be displayed automatically.
We need to complete -march= option design to perform such mechanism.


gcc/ChangeLog

2014-11-21  Chung-Ju Wu  

* config/nds32/nds32.opt (march): Add help message.


Committed as Rev. 217901: https://gcc.gnu.org/r217901


Best regards,
jasonwucj

Re: [PATCH, nds32] Committed: Complete -march= option design.

[Chung-Ju Wu]

2014-11-21 14:33 GMT+08:00 Chung-Ju Wu :
> Hi, all,
[snip]
>
> gcc/ChangeLog
>
> 2014-11-21  Chung-Ju Wu  
>
> * config/nds32/nds32.opt (march): Add help message.
>

Sorry for that I forgot to attach patch file in the previous mail.

Best regards,
jasonwucj


0001-Complete-march-option-design-so-that-it-can-display-.patch
Description: Binary data

[PATCH, nds32] Committed: Add missing RTX_FRAME_RELATED_P to set fp_adjust_insn rtx.

[Chung-Ju Wu]

Hi, all,

There is a wrong CFI info when frame pointer is needed.
The root cause is that we forgot to set fp_adjust_insn as
RTX_FRAME_RELATED_P rtx.

Fix this issue with following patch.


gcc/ChangeLog

2014-11-21  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_expand_prologue): Set fp_adjust_insn
as RTX_FRAME_RELATED_P rtx.


Committed as Rev. 217902: https://gcc.gnu.org/r217902


Best regards,
jasonwucj


0002-Add-missing-RTX_FRAME_RELATED_P-to-set-fp_adjust_ins.patch
Description: Binary data

[PATCH, nds32] Committed: Fix CFI info for variadic function arguments.

[Chung-Ju Wu]

Hi, all,

In nds32 ABI, the vararg arguments are pushed onto stack by callee.
However, those registers content are unnecessary to be restored.
We need to create an extra register note to inform gcc such information
so that it can generate correct CFI info for variadic function.


gcc/ChangeLog

2014-11-21  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_emit_stack_push_multiple): Add new
vaarg_p argument and create correct CFI info.
(nds32_expand_prologue): Pass true or false to
nds32_emit_stack_push_multiple function.


Committed as Rev. 217903: https://gcc.gnu.org/r217903


Best regards,
jasonwucj


0003-Fix-CFI-for-variadic-function-arguments.patch
Description: Binary data

[PATCH, nds32] Committed: Look into LO_SUM's operand to determine whether it is a valid address.

[Chung-Ju Wu]

Hi, all,

In the nds32_legitimate_address_p function, we should look into LO_SUM's
operand so that we can precisely identify if it is a valid address.
This can help to avoid extra move instruction and improve code generation.


gcc/ChangeLog

2014-11-21  Chung-Ju Wu  

* config/nds32/nds32.c (nds32_legitimate_address_p): For LO_SUM,
we need to look into its operand to determine whether it is a valid
address.


Committed as Rev. 217904: https://gcc.gnu.org/r217904


Best regards,
jasonwucj


0004-For-LO_SUM-rtx-we-need-to-look-into-its-operand-to-d.patch
Description: Binary data

Re: [PATCH, wwwdoc] Describe the changes of NDS32 port in GCC-5.0.

[Chung-Ju Wu]

2015-02-15 10:33 GMT+08:00 Chung-Ju Wu :
> Hi, all,
>
> There are some major changes on NDS32 port in GCC-5.0:
>   https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00316.html
>   https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00992.html
>   https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00993.html
>
> This patch is to describe them in changes.html.
>
> Although it is target-specific part, it is welcome for others to have
> review comments on its format, layout, and english words improvement.
>
> If there is no other comments about this patch, I will commit it into
> trunk next week. :)
>

Committed as revision 1.82 of htdocs/gcc-5/changes.html with minor adjustment.


Index: htdocs/gcc-5/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v
retrieving revision 1.81
diff -u -r1.81 changes.html
--- htdocs/gcc-5/changes.html   17 Feb 2015 22:55:14 -  1.81
+++ htdocs/gcc-5/changes.html   25 Feb 2015 05:50:42 -
@@ -626,6 +626,19 @@
   soft-float targets.
   

+NDS32
+  
+The variadic function ABI implementation is now compatible to the past
+Andes toolchains where caller uses registers to pass arguments and callee
+is in charge of pushing them into stack.
+The options -mforce-fp-as-gp,
-mforbid-fp-as-gp,
+and -mex9 have been removed since they are not
available yet in
+the nds32 port of GNU binutils package.
+New option -mcmodel=[small|medium|large] is provided to
+support varied code model on code generation.  The -mgp-direct
+option now becomes meaningless and can be discarded.
+  
+
 SH
   
 The compiler will now pass the appropriate --isa= option


>
> Best regards,
> jasonwucj
>

[PATCH, nds32] Committed: Rename some variables to explicitly represent general purpose register

[Chung-Ju Wu]

Hi, all,

This patch is just to rename some variables so that
one can easily tell that those variables are used to
describe general purpose registers.

No functionality changes.  Committed as Rev.221306:
  https://gcc.gnu.org/r221306


Best regards,
jasonwucj
diff --git a/gcc/config/nds32/nds32-md-auxiliary.c 
b/gcc/config/nds32/nds32-md-auxiliary.c
index 2f49277..0a3e773 100644
--- a/gcc/config/nds32/nds32-md-auxiliary.c
+++ b/gcc/config/nds32/nds32-md-auxiliary.c
@@ -604,8 +604,8 @@ nds32_output_stack_push (rtx par_rtx)
+ NDS32_MAX_GPR_REGS_FOR_ARGS
- 1;
   /* Pick up callee-saved first regno and last regno for further use.  */
-  int rb_callee_saved = cfun->machine->callee_saved_regs_first_regno;
-  int re_callee_saved = cfun->machine->callee_saved_regs_last_regno;
+  int rb_callee_saved = cfun->machine->callee_saved_first_gpr_regno;
+  int re_callee_saved = cfun->machine->callee_saved_last_gpr_regno;
 
   /* First we need to check if we are pushing argument registers not used
  for the named arguments.  If so, we have to create 'smw.adm' (push.s)
@@ -644,7 +644,7 @@ nds32_output_stack_push (rtx par_rtx)
  otherwise, generate 'push25 Re,0'.  */
   sp_adjust = cfun->machine->local_size
  + cfun->machine->out_args_size
- + cfun->machine->callee_saved_area_padding_bytes;
+ + cfun->machine->callee_saved_area_gpr_padding_bytes;
   if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
operands[1] = GEN_INT (sp_adjust);
@@ -712,8 +712,8 @@ nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED)
   /* The operands array which will be used in output_asm_insn().  */
   rtx operands[3];
   /* Pick up callee-saved first regno and last regno for further use.  */
-  int rb_callee_saved = cfun->machine->callee_saved_regs_first_regno;
-  int re_callee_saved = cfun->machine->callee_saved_regs_last_regno;
+  int rb_callee_saved = cfun->machine->callee_saved_first_gpr_regno;
+  int re_callee_saved = cfun->machine->callee_saved_last_gpr_regno;
 
   /* If we step here, we are going to do v3pop or multiple pop operation.  */
 
@@ -742,7 +742,7 @@ nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED)
  and then use 'pop25 Re,0'.  */
   sp_adjust = cfun->machine->local_size
  + cfun->machine->out_args_size
- + cfun->machine->callee_saved_area_padding_bytes;
+ + cfun->machine->callee_saved_area_gpr_padding_bytes;
   if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
  && !cfun->calls_alloca)
diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
index 1845bc2..b79e33e 100644
--- a/gcc/config/nds32/nds32.c
+++ b/gcc/config/nds32/nds32.c
@@ -224,12 +224,12 @@ nds32_compute_stack_frame (void)
   cfun->machine->lp_size = (df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0;
 
   /* Initially there is no padding bytes.  */
-  cfun->machine->callee_saved_area_padding_bytes = 0;
+  cfun->machine->callee_saved_area_gpr_padding_bytes = 0;
 
   /* Calculate the bytes of saving callee-saved registers on stack.  */
-  cfun->machine->callee_saved_regs_size = 0;
-  cfun->machine->callee_saved_regs_first_regno = SP_REGNUM;
-  cfun->machine->callee_saved_regs_last_regno  = SP_REGNUM;
+  cfun->machine->callee_saved_gpr_regs_size = 0;
+  cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM;
+  cfun->machine->callee_saved_last_gpr_regno  = SP_REGNUM;
   /* Currently, there is no need to check $r28~$r31
  because we will save them in another way.  */
   for (r = 0; r < 28; r++)
@@ -240,10 +240,10 @@ nds32_compute_stack_frame (void)
 (only need to set it once).
 If first regno == SP_REGNUM, we can tell that
 it is the first time to be here.  */
- if (cfun->machine->callee_saved_regs_first_regno == SP_REGNUM)
-   cfun->machine->callee_saved_regs_first_regno = r;
+ if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM)
+   cfun->machine->callee_saved_first_gpr_regno = r;
  /* Mark the last required callee-saved register.  */
- cfun->machine->callee_saved_regs_last_regno = r;
+ cfun->machine->callee_saved_last_gpr_regno = r;
}
 }
 
@@ -262,8 +262,8 @@ nds32_compute_stack_frame (void)
condition 3: There is no local_size, which means
 we do not need to adjust $sp.  */
   if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
-  || (cfun->machine->callee_saved_regs_first_regno == SP_REGNUM
- && cfun->machine->callee_saved_regs_last_regno == SP_REGNUM
+  || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM
+ && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM
  && !df_regs_ever_live_p (FP_REGNUM)
  && !df_regs_ever_live_p (LP_REGNUM)
 

[PATCH] Minor date fix in ChangeLog files.

[Chung-Ju Wu]

Hi, all,

I just happened to notice that there are some incorrect date
in ChangeLog files.  I guess this can be considered as obvious fix.

Committed it as Rev.219704: https://gcc.gnu.org/r219704

Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 219703)
+++ gcc/ChangeLog   (working copy)
@@ -286,7 +286,7 @@
cfganal.h, cfgbuild.h, cfgcleanup.h, lcm.h, cfgloopmanip.h,
builtins.def, and chkp-builtins.def.

-2014-01-15  David Edelsohn  
+2015-01-15  David Edelsohn  

* config/rs6000/default64.h (TARGET_DEFAULT) [LITTLE_ENDIAN]: Use
ISA 2.7 (POWER8).
@@ -988,7 +988,7 @@
Do not save lr in case of tail call.
* config/arm/thumb2.md (*thumb2_pop_single): New pattern.

-2015-01-13  Martin Uecker 
+2015-01-14  Martin Uecker 

* tree-vrp.c (check_array_ref): Emit more warnings
for warn_array_bounds >= 2.
@@ -1126,7 +1126,7 @@
(perform_symbolic_merge): This. Also fix computation of the range and
end of the symbolic number corresponding to the result of a bitwise OR.

-2014-01-13  Richard Biener  
+2015-01-13  Richard Biener  

PR tree-optimization/64568
* tree-ssa-forwprop.c (pass_forwprop::execute): Properly

Index: gcc/testsuite/ChangeLog
===
--- gcc/testsuite/ChangeLog (revision 219703)
+++ gcc/testsuite/ChangeLog (working copy)
@@ -489,7 +489,7 @@
PR tree-optimization/64404
* gcc.dg/vect/pr64404.c: New testcase.

-2014-01-13  Richard Biener  
+2015-01-13  Richard Biener  

PR tree-optimization/64568
* g++.dg/torture/pr64568.C: New testcase.


Best regards,
jasonwucj

Re: [PATCH, doc] NDS32: Describe -mcmodel= option instead of -mgp-direct in the documentation.

[Chung-Ju Wu]

2015-01-14 17:56 GMT+08:00 Chung-Ju Wu :
> Hi, all,
>
> In this patch of nds32 port:
>   https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00799.html
>
> Since we have a new option -mcmodel= as substitution for -mgp-direct,
> we need to update documentation about such change accordingly.
> The patch is attached and the plaintext ChangeLog is as follow.
>
> gcc/ChangeLog
>
> 2015-01-14  Chung-Ju Wu  
>
> * doc/invoke.texi (NDS32 Options): Add -mcmodel= option and
> remove -mgp-direct option.
>
>
> Although these changes are target-specific part, I think it would be better
> for others to have review comments, if any, on its format and layout.
>
> If there is no other comments about this patch, I will commit it into
> trunk after 24 hours.
>
>

Committed as Rev. 219706: https://gcc.gnu.org/r219706


> Best regards,
> jasonwucj

Re: [PATCH, doc] NDS32: Remove -mforce-fp-as-gp, -mforbid-fp-as-gp, and -mex9 options from documentation.

[Chung-Ju Wu]

2015-01-14 17:58 GMT+08:00 Chung-Ju Wu :
> Hi, all,
>
> In this patch of nds32 port:
>   https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00969.html
>
> Since we remove the implementation of -mforce-fp-as-gp, -mforbid-fp-as-gp,
> and -mex9 options, we need to update documentation as well.
> The patch is attached and the plaintext ChangeLog is as follow.
>
> gcc/ChangeLog
>
> 2015-01-14  Chung-Ju Wu  
>
> * doc/invoke.texi (NDS32 Options): Remove -mforce-fp-as-gp,
> -mforbid-fp-as-gp, and -mex9 options.
>
>
> Although these changes are target-specific part, I think it would be better
> for others to have review comments, if any, on its format and layout.
>
> If there is no other comments about this patch, I will commit it into
> trunk after 24 hours.
>

Committed as Rev. 219707: https://gcc.gnu.org/r219707


>
> Best regards,
> jasonwucj

PATCH, nds32] Committed: Fix wrong data flow when building nds32 target with --enable-checking=yes.

[Chung-Ju Wu]

Hi, all,

The nds32 target has two kinds of instructions for returning to the caller.
One is normal 'ret' instruction which takes $lp as return address;
and the other is 'pop25' instruction which perform registers pop and use $lp
as return address in a single step.

However, the current design of 'pop25' on trunk is incomplete.
We lost "return" rtx semantic in the pattern so that gcc will get wrong
data flow across pop25 if we configure it with --enable-checking=yes.

To fix this issue, we have dummy pattern 'pop25return' to tell gcc that
there is a return behavior after pop25 instruction.

This patch was committed last week before stage 4:
  https://gcc.gnu.org/r219710

gcc/ChangeLog


2015-01-16 Chung-Ju Wu 

* config/nds32/constants.md (UNSPEC_VOLATILE_POP25_RETURN): New.
* config/nds32/nds32.md (pop25return): New.
* config/nds32/nds32.c (nds32_expand_epilogue_v3pop): Emit
pop25return pattern.


Best regards,
jasonwucj


0007-Add-dummy-pattern-pop25return-to-tell-gcc-there-is-a.patch
Description: Binary data

[PATCH, nds32] Committed: Have shrink-wrapping optimization to be performed on nds32 target.

[Chung-Ju Wu]

Hi, all,

It is reported that the nds32 port on trunk cannot perform shrink-wrapping
optimization because there is missing named pattern "simple_return".
So we define that named pattern to fix the issue.

This patch was committed last week before stage 4:
  https://gcc.gnu.org/r219711


gcc/ChangeLog

2015-01-16  Chung-Ju Wu  

* config/nds32/nds32-protos.h (nds32_can_use_return_insn): New.
* config/nds32/nds32.md (unspec_volatile_func_return): Remove.
(return_internal): New.
(return): Define this named pattern.
(simple_return): Define this named pattern.
* config/nds32/nds32.c (nds32_expand_epilogue): Emit return_internal
pattern instead of unspec_volatile_func_return.
(nds32_expand_epilogue_v3pop): Likewise.
(nds32_can_use_return_insn): New function.


Best regards,
jasonwucj


0008-Use-simple_return-named-pattern-so-that-shirnk-wrapp.patch
Description: Binary data

[PATCH, nds32] Committed: Have sibling calls optmization to be performed on nds32 target.

[Chung-Ju Wu]

Hi, all,

It is reported that the nds32 port on trunk cannot perform sibling call
optimization because there are missing "sibcall" and "sibcall_value"
named patterns.  So we define those named patterns to fix the issue.

This patch was committed last week before stage 4:
  https://gcc.gnu.org/r219712


gcc/ChangeLog

2015-01-16  Chung-Ju Wu  

* config/nds32/nds32-protos.h (nds32_expand_epilogue): Change
prototype.
(nds32_expand_epilogue_v3pop): Likewise.
* config/nds32/nds32.md (sibcall): Define this for sibling call
optimization.
(sibcall_register): Likewise.
(sibcall_immediate): Likewise.
(sibcall_value): Likewise.
(sibcall_value_register): Likewise.
(sibcall_value_immediate): Likewise.
(sibcall_epilogue): Likewise.
(epilogue): Pass false to indicate this is not a sibcall epilogue.
* config/nds32/nds32.c (nds32_expand_epilogue): Consider sibcall case.
(nds32_expand_epilogue_v3pop): Likewise.

Best regards,
jasonwucj


0009-Implement-necessary-named-patterns-to-support-siblin.patch
Description: Binary data

Re: [PATCH, doc] NDS32: Describe -mcmodel= option instead of -mgp-direct in the documentation.

[Chung-Ju Wu]

2015-01-18 16:36 GMT+08:00 Gerald Pfeifer :
> On Wednesday 2015-01-14 17:56, Chung-Ju Wu wrote:
>> 2015-01-14  Chung-Ju Wu  
>>
>> * doc/invoke.texi (NDS32 Options): Add -mcmodel= option and
>> remove -mgp-direct option.
>>
>> Although these changes are target-specific part, I think it would be better
>> for others to have review comments, if any, on its format and layout.
>
> That's easier for us if you attach patches as text as opposed
> to Content-Type: application/octet-stream.
>
> Gerald

No problem.  If the content is small enough, next time I will have
patches as text so that others are able to do review easily.

Thanks for your suggestion. :)


Best regards,
jasonwucj

Re: [PATCH, doc] NDS32: Remove -mforce-fp-as-gp, -mforbid-fp-as-gp, and -mex9 options from documentation.

[Chung-Ju Wu]

2015-01-18 16:38 GMT+08:00 Gerald Pfeifer :
> On Wednesday 2015-01-14 17:58, Chung-Ju Wu wrote:
>> 2015-01-14  Chung-Ju Wu  
>>
>> * doc/invoke.texi (NDS32 Options): Remove -mforce-fp-as-gp,
>> -mforbid-fp-as-gp, and -mex9 options.
>
> Can you cover these, and similar changes, in the release notes
> at htdocs/gcc-5/changes.html, please?  (Cf. gcc.gnu.org/about.html
> for the web pages side of things.)
>
> Gerald

Thank for reminding me.

I am preparing such patch to describe nds32 port in the
release note of gcc5 changes.html, including the new options,
the options are removed, and ABI changes for variadic function:
  https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00316.html
  https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00992.html
  https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00993.html

I will post that patch for web page soon. :)


Best regards,
jasonwucj

[PATCH, wwwdoc] Describe the changes of NDS32 port in GCC-5.0.

[Chung-Ju Wu]

Hi, all,

There are some major changes on NDS32 port in GCC-5.0:
  https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00316.html
  https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00992.html
  https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00993.html

This patch is to describe them in changes.html.

Although it is target-specific part, it is welcome for others to have
review comments on its format, layout, and english words improvement.

If there is no other comments about this patch, I will commit it into
trunk next week. :)


Best regards,
jasonwucj

Index: htdocs/gcc-5/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v
retrieving revision 1.77
diff -u -r1.77 changes.html
--- htdocs/gcc-5/changes.html   2 Feb 2015 08:49:09 -   1.77
+++ htdocs/gcc-5/changes.html   5 Feb 2015 02:28:05 -
@@ -560,6 +560,19 @@
optimize the Linux kernel.
   
 
+NDS32
+  
+The variadic function ABI implementation is now compatible to the past
+Andes toolchains where caller uses registers to pass arguments and callee
+is in charge of pushing them into stack.
+The options -mforce-fp-as-gp, 
-mforbid-fp-as-gp,
+and -mex9 have been removed since they are not available yet 
in
+the nds32 port of binutils package.
+New option -mcmodel=small/medium/large is provided to
+support varied code model on code generation.  The -mgp-direct
+option now becomes meaningless and can be discarded.
+  
+
 SH
   
 The compiler will now pass the appropriate --isa= option

[PATCH] nds32: Backport PR70668 solution from mainline

[Chung-Ju Wu]

Hi, all,

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70668
https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01862.html

Thanks Stefan Reinauer to create this PR and
thanks Segher Boessenkool to fix the issue.

Now I backport the solution to gcc-6 and gcc-5 branches.
Committed as revision r244257 and r244258.
https://gcc.gnu.org/r244257
https://gcc.gnu.org/r244258


Best regards,
jasonwucj
Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 244256)
+++ gcc/ChangeLog   (working copy)
@@ -1,3 +1,12 @@
+2017-01-10  Chung-Ju Wu  
+
+   Backport from mainline
+   2016-04-28  Segher Boessenkool  
+
+   PR target/70668
+   * config/nds32/nds32.md (casesi): Don't access the operands array
+   out of bounds.
+
 2017-01-09  Andreas Tobler  
 
Backport from mainline
Index: gcc/config/nds32/nds32.md
===
--- gcc/config/nds32/nds32.md   (revision 244256)
+++ gcc/config/nds32/nds32.md   (working copy)
@@ -2289,11 +2289,9 @@
   emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
  operands[4]));
 
-  operands[5] = gen_reg_rtx (SImode);
-  /* Step C, D, E, and F, using another temporary register operands[5].  */
-  emit_jump_insn (gen_casesi_internal (operands[0],
-  operands[3],
-  operands[5]));
+  /* Step C, D, E, and F, using another temporary register.  */
+  rtx tmp = gen_reg_rtx (SImode);
+  emit_jump_insn (gen_casesi_internal (operands[0], operands[3], tmp));
   DONE;
 })
 
Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 244256)
+++ gcc/ChangeLog   (working copy)
@@ -1,3 +1,12 @@
+2017-01-10  Chung-Ju Wu  
+
+   Backport from mainline
+   2016-04-28  Segher Boessenkool  
+
+   PR target/70668
+   * config/nds32/nds32.md (casesi): Don't access the operands array
+   out of bounds.
+
 2017-01-09  Andreas Tobler  
 
Backport from mainline
Index: gcc/config/nds32/nds32.md
===
--- gcc/config/nds32/nds32.md   (revision 244256)
+++ gcc/config/nds32/nds32.md   (working copy)
@@ -2288,11 +2288,9 @@
   emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
  operands[4]));
 
-  operands[5] = gen_reg_rtx (SImode);
-  /* Step C, D, E, and F, using another temporary register operands[5].  */
-  emit_jump_insn (gen_casesi_internal (operands[0],
-  operands[3],
-  operands[5]));
+  /* Step C, D, E, and F, using another temporary register.  */
+  rtx tmp = gen_reg_rtx (SImode);
+  emit_jump_insn (gen_casesi_internal (operands[0], operands[3], tmp));
   DONE;
 })
 

[PATCH, nds32] Refine formatting and comments.

[Chung-Ju Wu]

Hi, all,

I noticed that some 8-spaces should be replaced with tab character.
Here is a patch to refine formatting and comments in nds32 port.
No functionality changes.

Committed as Rev.252874: http://gcc.gnu.org/r252874

gcc/
* config/nds32/nds32.c: Refine formatting and comments.
* config/nds32/nds32.h: Likewise.
* config/nds32/nds32.md: Likewise.
* config/nds32/nds32-cost.c: Likewise.
* config/nds32/nds32-isr.c: Likewise.
* config/nds32/nds32-md-auxiliary.c: Likewise.
* config/nds32/nds32-multiple.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.


Best regards,
jasonwucj
Index: gcc/config/nds32/nds32-cost.c
===
--- gcc/config/nds32/nds32-cost.c   (revision 252873)
+++ gcc/config/nds32/nds32-cost.c   (working copy)
@@ -99,7 +99,7 @@
 {
 case SET:
   /* For 'SET' rtx, we need to return false
- so that it can recursively calculate costs.  */
+so that it can recursively calculate costs.  */
   return false;
 
 case USE:
@@ -109,7 +109,7 @@
 
 case CONST_INT:
   /* All instructions involving constant operation
- need to be considered for cost evaluation.  */
+need to be considered for cost evaluation.  */
   if (outer_code == SET)
{
  /* (set X imm5s), use movi55, 2-byte cost.
@@ -202,17 +202,17 @@
 case POST_INC:
 case POST_DEC:
   /* We encourage that rtx contains
- POST_MODIFY/POST_INC/POST_DEC behavior.  */
+POST_MODIFY/POST_INC/POST_DEC behavior.  */
   return 0;
 
 case SYMBOL_REF:
   /* We can have gp-relative load/store for symbol_ref.
- Have it 4-byte cost.  */
+Have it 4-byte cost.  */
   return COSTS_N_INSNS (1);
 
 case CONST:
   /* It is supposed to be the pattern (const (plus symbol_ref const_int)).
- Have it 4-byte cost.  */
+Have it 4-byte cost.  */
   return COSTS_N_INSNS (1);
 
 case REG:
@@ -221,14 +221,14 @@
 
 case PLUS:
   /* We do not need to check if the address is a legitimate address,
- because this hook is never called with an invalid address.
- But we better check the range of
- const_int value for cost, if it exists.  */
+because this hook is never called with an invalid address.
+But we better check the range of
+const_int value for cost, if it exists.  */
   plus0 = XEXP (address, 0);
   plus1 = XEXP (address, 1);
 
   if (REG_P (plus0) && CONST_INT_P (plus1))
-{
+   {
  /* If it is possible to be lwi333/swi333 form,
 make it 2-byte cost.  */
  if (satisfies_constraint_Iu05 (plus1))
Index: gcc/config/nds32/nds32-isr.c
===
--- gcc/config/nds32/nds32-isr.c(revision 252873)
+++ gcc/config/nds32/nds32-isr.c(working copy)
@@ -171,20 +171,20 @@
   if (nds32_isr_vector_size == 4)
 {
   /* This block is for 4-byte vector size.
- Hardware $VID support is necessary and only one instruction
- is needed in vector section.  */
+Hardware $VID support is necessary and only one instruction
+is needed in vector section.  */
   fprintf (asm_out_file, "\tj\t%s ! jump to first level handler\n",
 first_level_handler_name);
 }
   else
 {
   /* This block is for 16-byte vector size.
- There is NO hardware $VID so that we need several instructions
- such as pushing GPRs and preparing software vid at vector section.
- For pushing GPRs, there are four variations for
- 16-byte vector content and we have to handle each combination.
- For preparing software vid, note that the vid need to
- be substracted vector_number_offset.  */
+There is NO hardware $VID so that we need several instructions
+such as pushing GPRs and preparing software vid at vector section.
+For pushing GPRs, there are four variations for
+16-byte vector content and we have to handle each combination.
+For preparing software vid, note that the vid need to
+be substracted vector_number_offset.  */
   if (TARGET_REDUCED_REGS)
{
  if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL)
@@ -449,12 +449,12 @@
   nds32_isr_vectors[0].category = NDS32_ISR_RESET;
 
   /* Prepare id_list and identify id value so that
- we can set total number of vectors.  */
+we can set total number of vectors.  */
   id_list = TREE_VALUE (reset);
   id = TREE_VALUE (id_list);
 
   /* The total vectors = interrupt + exception numbers + reset.
- There are 8 exception and 1 reset in nds32 architecture.  */
+There are 8 exception and 1 reset in nds32 architecture.  */
   nds32_isr_vectors[0].total_n_vectors = TR

[PATCH, nds32] Add OPT_fsched_pressure and OPT_fomit_frame_pointer in optimization table.

[Chung-Ju Wu]

Hi, all,

In the nds32 port, most of time we prefer reducing code size.
So we modify the nds32_option_optimization_table[] to apply
-fsched-pressure and -fomit-frame-pointer for specific
optimization level.

Committed as Rev.252876: https://gcc.gnu.org/r252876

gcc/
* common/config/nds32/nds32-common.c
(nds32_option_optimization_table): Refine formatting.
(nds32_option_optimization_table): Use -fsched-pressure and
-fomit-frame-pointer for specific optimization level.


Best regards,
jasonwucj
--- sandbox/src/gcc.svn/gcc/common/config/nds32/nds32-common.c  2017-09-06 
00:37:02.684366502 +0800
+++ gcc.710release.orig/gcc/common/config/nds32/nds32-common.c  2017-09-15 
22:11:41.441875438 +0800
@@ -74,12 +74,14 @@
 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
 static const struct default_options nds32_option_optimization_table[] =
 {
-  /* Enable -fomit-frame-pointer by default at -O1 or higher.  */
-  { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+  /* Enable -fsched-pressure by default at -O1 and above.  */
+  { OPT_LEVELS_1_PLUS,OPT_fsched_pressure, NULL, 1 },
+  /* Enable -fomit-frame-pointer by default at all optimization levels.  */
+  { OPT_LEVELS_ALL,   OPT_fomit_frame_pointer, NULL, 1 },
   /* Enable -mv3push by default at -Os, but it is useless under V2 ISA.  */
-  { OPT_LEVELS_SIZE,   OPT_mv3push, NULL, 1 },
+  { OPT_LEVELS_SIZE,  OPT_mv3push, NULL, 1 },
 
-  { OPT_LEVELS_NONE,   0,   NULL, 0 }
+  { OPT_LEVELS_NONE,  0,   NULL, 0 }
 };
 
 /*  */