[PATCH V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM

[juzhe . zhong]

From: Juzhe-Zhong 

Currently mode switching incorrect codegen for the following case:
void fn (void);

void f (void * in, void *out, int32_t x, int n, int m)
{
  for (int i = 0; i < n; i++) {
vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
fn ();
v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
__riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
  }
}

Before this patch:

Preheader: 
  ...
  csrwi vxrm,2
Loop Body:
  ... (no cswri vxrm,2)
  vaadd.vx
  ...
  vaadd.vx
  ...

This codegen is incorrect.

After this patch:

Preheader:
  ...
  csrwi vxrm,2
Loop Body:
  ...
  vaadd.vx
  ...
  csrwi vxrm,2
  ...
  vaadd.vx
  ...

cross-compile build PASS and regression PASS

Ok for trunk ?

gcc/ChangeLog:

* config/riscv/riscv.cc (global_state_unknown_p): New function.
(riscv_mode_after): Fix incorrect VXM.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vxrm-11.c: New test.
* gcc.target/riscv/rvv/base/vxrm-12.c: New test.

---
 gcc/config/riscv/riscv.cc | 29 ++-
 .../gcc.target/riscv/rvv/base/vxrm-11.c   | 20 +
 .../gcc.target/riscv/rvv/base/vxrm-12.c   | 18 
 3 files changed, 66 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 09fc9e5d95e..406c5469425 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7549,6 +7549,31 @@ riscv_mode_needed (int entity, rtx_insn *insn)
 }
 }
 
+/* Return true if the VXRM/FRM status of the INSN is unknown.  */
+static bool
+global_state_unknown_p (rtx_insn *insn, unsigned int regno)
+{
+  struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
+  df_ref ref;
+
+  /* Return true if there is a definition of VXRM.  */
+  for (ref = DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref))
+if (DF_REF_REGNO (ref) == regno)
+  return true;
+
+  /* A CALL function may contain an instruction that modifies the VXRM,
+ return true in this situation.  */
+  if (CALL_P (insn))
+return true;
+
+  /* Return true for all assembly since users may hardcode a assembly
+ like this: asm volatile ("csrwi vxrm, 0").  */
+  extract_insn (insn);
+  if (recog_data.is_asm)
+return true;
+  return false;
+}
+
 /* Return the mode that an insn results in.  */
 
 static int
@@ -7557,7 +7582,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn)
   switch (entity)
 {
 case RISCV_VXRM:
-  if (recog_memoized (insn) >= 0)
+  if (global_state_unknown_p (insn, VXRM_REGNUM))
+   return VXRM_MODE_NONE;
+  else if (recog_memoized (insn) >= 0)
return reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM),
PATTERN (insn))
 ? get_attr_vxrm_mode (insn)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
new file mode 100644
index 000..7f637a8b7f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void fn (void);
+
+void f (void * in, void *out, int32_t x, int n, int m)
+{
+  for (int i = 0; i < n; i++) {
+vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
+vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
+vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+fn ();
+v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+__riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
+  }
+}
+
+/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
new file mode 100644
index 000..c3ab509f106
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void f (void * in, void *out, int32_t x, int n, int m)
+{
+  for (int i = 0; i < n; i++) {
+vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
+vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
+vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+asm volatile ("csrwi\tvxrm,1");
+v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+__riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
+  }
+}
+
+/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */
-- 
2.36.3

Re: [COMMITTED 4/4] - Gimple range PHI analyzer and testcases

[Richard Biener via Gcc-patches]

On Wed, May 24, 2023 at 11:21 PM Andrew MacLeod via Gcc-patches
 wrote:
>
> This patch provide the framework for a gimple-range phi analyzer.
>
> Currently, the  primary purpose is to give better initial values for
> members of a "phi group"
>
> a PHI group is defined as a a group of PHI nodes whose arguments are all
> either members of the same PHI group, or one of 2 other values:
>   - An initializer, (typically a constant), but not necessarily,
>   - A modifier, which is always of the form:   member_ssa = member_ssa
> OP op2
>
> When the analyzer finds a group which matches this pattern, it tries to
> evaluate the modifier using the initial value and project a range for
> the entire group.
>
> This initial version is fairly simplistic.  It looks for 2 things:
>
> 1) if there is a relation between LHS and the other ssa_name in the
> modifier, then we can project a range. ie,
>  a_3 = a_2 + 1
> if there is a relation generated by the stmt which say a_3 > a_2, and
> the initial value is 0, we can project a range of [0, +INF] as the
> moifier will cause the value to always increase, and not wrap.
>
> Likewise, for a_3 = a_2 - 1,  we can project a range of [-INF, 0] based
> on the "<" relationship between a_3 and a_2.
>
> 2) If there is no relationship, then we use the initial range and
> "simulate" the modifier statement a set number of times looking to see
> if the value converges.
> Currently I have arbitrarily hard coded 10 attempts, but intend to
> change this down the road with a --param, as well as to perhaps
> influence it with any known values from SCEV regarding known iterations
> of the loop and possibly change it based on optimization levels.
>
> I also suspect something like one more than the number of bits in the
> type might help with any bitmasking tricks.
>
> Theres a lot of additinal things we can do to enhance this, but this
> framework provides a start.  These 2 initial evaluations fix 107822, and
> part of 107986.
>
>   There is about a 1.5% slowdown to VRP to invoke and utilize the
> analyzer in all 3 passes of VRP.  overall compile time is 0.06% slower.
>
> Bootstraps on x86_64-pc-linux-gnu  with no regressions.  Pushed.

Hm.  What I've noticed the last time looking at how ranger deals
with PHIs is that it diverts to SCEV analysis for all of them but
it could restrict itself to analyze PHIs in loop headers
(bb->loop_father->header == bb).  That only handles natural
loops of course but that was good enough for the old VRP implementation.
That might also help to keep the PHI anlyzer leaner by less entires.

I've only quickly looked at the PHI analyzer and I failed to understand
how you discover cycles.  I'm pointing you to the SCC value-numbering
cycle finding which you can find for example on the GCC 7 branch
(it's gone for quite some time) in tree-ssa-sccvn.c:DFS - that collects
strongly connected SSA components (it walks all uses, you probably
want to ignore virtuals).  SCEV also has its own cycle finding
(well, sort of) with the scev_dfs class and it restricts itself to
operations it handles (so it's more close to what you do).

I fear you're developing sth very ad-hoc here.

Richard.


> Andrew
>
>
>
>

Re: [PATCH] libgcc: Use initarray section type for .init_stack

[Andreas Krebbel via Gcc-patches]

On 3/20/23 07:33, Kewen.Lin wrote:
> Hi,
> 
> One of my workmates found there is a warning like:
> 
>   libgcc/config/rs6000/morestack.S:402: Warning: ignoring
> incorrect section type for .init_array.0
> 
> when compiling libgcc/config/rs6000/morestack.S.
> 
> Since commit r13-6545 touched that file recently, which was
> suspected to be responsible for this warning, I did some
> investigation and found this is a warning staying for a long
> time.  For section .init_stack*, it's preferred to use
> section type SHT_INIT_ARRAY.  So this patch is use
> "@init_array" to replace "@progbits".
> 
> Although the warning is trivial, Segher suggested me to
> post this to fix it, in order to avoid any possible
> misunderstanding/confusion on the warning.
> 
> As Alan confirmed, this doesn't require a premise check
> on if the existing binutils supports "@init_array" or not,
> "because if you want split-stack to work, you must link
> with gold, any version of binutils that has gold has an
> assembler that understands @init_array". (Thanks Alan!)
> 
> Bootstrapped and regtested on x86_64-redhat-linux
> and powerpc64{,le}-linux-gnu.
> 
> Is it ok for trunk when next stage 1 comes?
> 
> BR,
> Kewen
> -
> libgcc/ChangeLog:
> 
>   * config/i386/morestack.S: Use @init_array rather than
>   @progbits for section type of section .init_array.
>   * config/rs6000/morestack.S: Likewise.
>   * config/s390/morestack.S: Likewise.

s390 parts are ok. I did run a bootstrap and regression. Looks all good. Thanks!

Andreas

Re: [aarch64] Code-gen for vector initialization involving constants

[Richard Sandiford via Gcc-patches]

LGTM, just a couple of comment tweaks:

Prathamesh Kulkarni  writes:
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index d6fc94015fa..db7ca4c28c3 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -22332,6 +22332,46 @@ aarch64_unzip_vector_init (machine_mode mode, rtx 
> vals, bool even_p)
>return gen_rtx_PARALLEL (new_mode, vec);
>  }
>  
> +/* Return true if INSN is a scalar move.  */

s/INSN/SET/

> +
> +static bool
> +scalar_move_insn_p (rtx set)
> +{
> +  rtx src = SET_SRC (set);
> +  rtx dest = SET_DEST (set);
> +  return (is_a (GET_MODE (dest))
> +   && aarch64_mov_operand (src, GET_MODE (dest)));
> +}
> +
> +/* Similar to seq_cost, but ignore cost for scalar moves.  This function
> +   is called from aarch64_expand_vector_init.  */

Probably best to drop the second sentence.

OK with those changes, thanks (no need to retest).

Richard

Re: [PATCH V15] VECT: Add decrement IV iteration loop control by variable amount support

[juzhe.zh...@rivai.ai]

Bootstrap && Regression on X86 passed.

Ok for trunk ?


juzhe.zh...@rivai.ai
 
From: juzhe.zhong
Date: 2023-05-25 10:58
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V15] VECT: Add decrement IV iteration loop control by variable 
amount support
From: Ju-Zhe Zhong 
 
This patch is supporting decrement IV by following the flow designed by Richard:
 
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
 
(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rgc has 1 control, this step is the SSA name created for that control.
Otherwise the step is a fresh SSA name, as in your patch.
 
(3) vect_set_loop_controls_directly stores this step somewhere for later
use, probably in LOOP_VINFO.  Let's use "S" to refer to this stored step.
 
(4) After the vect_set_loop_controls_directly call above, and outside
the "if" statement that now contains vect_set_loop_controls_directly,
check whether rgc->controls.length () > 1.  If so, use
vect_adjust_loop_lens_control to set the controls based on S.
 
Then the only caller of vect_adjust_loop_lens_control is
vect_set_loop_condition_partial_vectors.  And the starting
step for vect_adjust_loop_lens_control is always S.
 
This patch has well tested for single-rgroup and multiple-rgroup (SLP) and
passed all testcase in RISC-V port.
 
Also, pass tests for multiple-rgroup (non-SLP) tested on vec_pack_trunk.
 
Fix bugs of V14 patch:
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c execution 
test
 
This patch passed all testcases listed above.
 
gcc/ChangeLog:
 
* tree-vect-loop-manip.cc (vect_set_loop_controls_directly): Add 
decrement IV support.
(vect_adjust_loop_lens_control): Ditto.
(vect_set_loop_condition_partial_vectors): Ditto.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): New variables.
* tree-vectorizer.h (LOOP_VINFO_USING_DECREMENTING_IV_P): New macro.
(LOOP_VINFO_DECREMENTING_IV_STEP): Ditto.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: New 
test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: New 
test.
 
---
.../rvv/autovec/partial/multiple_rgroup-3.c   | 288 ++
.../rvv/autovec/partial/multiple_rgroup-4.c   |  75 +
.../autovec/partial/multiple_rgroup_run-3.c   |  36 +++
.../autovec/partial/multiple_rgroup_run-4.c   |  15 +
gcc/tree-vect-loop-manip.cc   | 153 ++
gcc/tree-vect-loop.cc |  13 +
gcc/tree-vectorizer.h |  12 +
7 files changed, 592 insertions(+)
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
new file mode 100644
index 000..9579749c285
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
@@ -0,0 +1,288 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax" } */
+
+#include 
+
+void __attribute__ ((noinline, noclone))
+f0 (int8_t *__restrict x, int16_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i += 4, j += 8)
+{
+  x[i + 0] += 1;
+  x[i + 1] += 2;
+  x[i + 2] += 3;
+  x[i + 3] += 4;
+  y[j + 0] += 1;
+  y[j + 1] += 2;
+  y[j + 2] += 3;
+  y[j + 3] += 4;
+  y[j + 4] += 5;
+  y[j + 5] += 6;
+  y[j + 6] += 7;
+  y[j + 7] += 8;
+}
+}
+
+void __attribute__ ((optimize (0)))
+f0_init (int8_t *__restrict x, int8_t *__restrict x2, int16_t *__restrict y,
+ int16_t *__restrict y2, int n)
+{
+  for (int i = 0, j = 0; i < n; i += 4, j += 8)
+{
+  x[i + 0] = i % 120;
+  x[i + 1] = i % 78;
+  x[i + 2] = i % 55

RE: [PATCH] i386: Fix incorrect intrinsic signature for AVX512 s{lli|rai|rli}

[Hu, Lin1 via Gcc-patches]

OK, I update the change log and modify a part of format. The attached file is 
the new version.

-Original Message-
From: Hongtao Liu  
Sent: Thursday, May 25, 2023 11:40 AM
To: Hu, Lin1 
Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ; 
ubiz...@gmail.com
Subject: Re: [PATCH] i386: Fix incorrect intrinsic signature for AVX512 
s{lli|rai|rli}

On Thu, May 25, 2023 at 10:55 AM Hu, Lin1 via Gcc-patches
 wrote:
>
> Hi all,
>
> This patch aims to fix incorrect intrinsic signature for 
> _mm{512|256|}_s{lli|rai|rli}_epi*. And it has been tested on 
> x86_64-pc-linux-gnu. OK for trunk?
>
> BRs,
> Lin
>
> gcc/ChangeLog:
>
> PR target/109173
> PR target/109174
> * config/i386/avx512bwintrin.h (_mm512_srli_epi16): Change type from
> int to const int.
int to unsigned int or const int to const unsigned int.
Others LGTM.
> (_mm512_mask_srli_epi16): Ditto.
> (_mm512_slli_epi16): Ditto.
> (_mm512_mask_slli_epi16): Ditto.
> (_mm512_maskz_slli_epi16): Ditto.
> (_mm512_srai_epi16): Ditto.
> (_mm512_mask_srai_epi16): Ditto.
> (_mm512_maskz_srai_epi16): Ditto.
> * config/i386/avx512vlintrin.h (_mm256_mask_srli_epi32): Ditto.
> (_mm256_maskz_srli_epi32): Ditto.
> (_mm_mask_srli_epi32): Ditto.
> (_mm_maskz_srli_epi32): Ditto.
> (_mm256_mask_srli_epi64): Ditto.
> (_mm256_maskz_srli_epi64): Ditto.
> (_mm_mask_srli_epi64): Ditto.
> (_mm_maskz_srli_epi64): Ditto.
> (_mm256_mask_srai_epi32): Ditto.
> (_mm256_maskz_srai_epi32): Ditto.
> (_mm_mask_srai_epi32): Ditto.
> (_mm_maskz_srai_epi32): Ditto.
> (_mm256_srai_epi64): Ditto.
> (_mm256_mask_srai_epi64): Ditto.
> (_mm256_maskz_srai_epi64): Ditto.
> (_mm_srai_epi64): Ditto.
> (_mm_mask_srai_epi64): Ditto.
> (_mm_maskz_srai_epi64): Ditto.
> (_mm_mask_slli_epi32): Ditto.
> (_mm_maskz_slli_epi32): Ditto.
> (_mm_mask_slli_epi64): Ditto.
> (_mm_maskz_slli_epi64): Ditto.
> (_mm256_mask_slli_epi32): Ditto.
> (_mm256_maskz_slli_epi32): Ditto.
> (_mm256_mask_slli_epi64): Ditto.
> (_mm256_maskz_slli_epi64): Ditto.
> (_mm_mask_srai_epi16): Ditto.
> (_mm_maskz_srai_epi16): Ditto.
> (_mm256_srai_epi16): Ditto.
> (_mm256_mask_srai_epi16): Ditto.
> (_mm_mask_slli_epi16): Ditto.
> (_mm_maskz_slli_epi16): Ditto.
> (_mm256_mask_slli_epi16): Ditto.
> (_mm256_maskz_slli_epi16): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> PR target/109173
> PR target/109174
> * gcc.target/i386/pr109173-1.c: New test.
> * gcc.target/i386/pr109174-1.c: Ditto.
> ---
>  gcc/config/i386/avx512bwintrin.h   |  32 +++---
>  gcc/config/i386/avx512fintrin.h|  58 +++
>  gcc/config/i386/avx512vlbwintrin.h |  36 ---
>  gcc/config/i386/avx512vlintrin.h   | 112 +++--
>  gcc/testsuite/gcc.target/i386/pr109173-1.c |  57 +++
>  gcc/testsuite/gcc.target/i386/pr109174-1.c |  45 +
>  6 files changed, 236 insertions(+), 104 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr109173-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr109174-1.c
>
> diff --git a/gcc/config/i386/avx512bwintrin.h 
> b/gcc/config/i386/avx512bwintrin.h
> index 89790f7917b..791d4e35f32 100644
> --- a/gcc/config/i386/avx512bwintrin.h
> +++ b/gcc/config/i386/avx512bwintrin.h
> @@ -2880,7 +2880,7 @@ _mm512_maskz_dbsad_epu8 (__mmask32 __U, __m512i __A, 
> __m512i __B,
>
>  extern __inline __m512i
>  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm512_srli_epi16 (__m512i __A, const int __imm)
> +_mm512_srli_epi16 (__m512i __A, const unsigned int __imm)
>  {
>return (__m512i) __builtin_ia32_psrlwi512_mask ((__v32hi) __A, __imm,
>   (__v32hi)
> @@ -2891,7 +2891,7 @@ _mm512_srli_epi16 (__m512i __A, const int __imm)
>  extern __inline __m512i
>  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
>  _mm512_mask_srli_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
> -   const int __imm)
> +   const unsigned int __imm)
>  {
>return (__m512i) __builtin_ia32_psrlwi512_mask ((__v32hi) __A, __imm,
>   (__v32hi) __W,
> @@ -2910,7 +2910,7 @@ _mm512_maskz_srli_epi16 (__mmask32 __U, __m512i __A, 
> const int __imm)
>
>  extern __inline __m512i
>  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm512_slli_epi16 (__m512i __A, const int __B)
> +_mm512_slli_epi16 (__m512i __A, const unsigned int __B)
>  {
>return (__m512i) __builtin_ia32_psllwi512_mask ((__v32hi) __A, __B,
>   (__v32hi)
> @@ -2921,7 +2921,7 @@ _mm512_slli_epi16 (__m512i __A, const i

[PATCH] RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs

[juzhe . zhong]

From: Juzhe-Zhong 

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins.cc (register_frm): New function.
(DEF_RVV_FRM_ENUM): New macro.
(handle_pragma_vector): Add FRM enum
* config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro.
(RNE): Ditto.
(RTZ): Ditto.
(RDN): Ditto.
(RUP): Ditto.
(RMM): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/frm-1.c: New test.

---
 gcc/config/riscv/riscv-vector-builtins.cc | 14 
 gcc/config/riscv/riscv-vector-builtins.def| 12 +++
 .../gcc.target/riscv/rvv/base/frm-1.c | 35 +++
 3 files changed, 61 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
b/gcc/config/riscv/riscv-vector-builtins.cc
index f69f6c49c7e..9fea70709fd 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4031,6 +4031,19 @@ register_vxrm ()
   lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values);
 }
 
+/* Register the frm enum.  */
+static void
+register_frm ()
+{
+  auto_vec values;
+#define DEF_RVV_FRM_ENUM(NAME, VALUE)  
\
+  values.quick_push (string_int_pair ("FRM_" #NAME, VALUE));
+#include "riscv-vector-builtins.def"
+#undef DEF_RVV_FRM_ENUM
+
+  lang_hooks.types.simulate_enum_decl (input_location, "RVV_FRM", &values);
+}
+
 /* Implement #pragma riscv intrinsic vector.  */
 void
 handle_pragma_vector ()
@@ -4048,6 +4061,7 @@ handle_pragma_vector ()
 
   /* Define the enums.  */
   register_vxrm ();
+  register_frm ();
 
   /* Define the functions.  */
   function_table = new hash_table (1023);
diff --git a/gcc/config/riscv/riscv-vector-builtins.def 
b/gcc/config/riscv/riscv-vector-builtins.def
index 533853e09b1..61346e53d7b 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -94,6 +94,11 @@ along with GCC; see the file COPYING3.  If not see
 #define DEF_RVV_VXRM_ENUM(NAME, VALUE)
 #endif
 
+/* Define RVV_FRM rounding mode enum for floating-point intrinsics.  */
+#ifndef DEF_RVV_FRM_ENUM
+#define DEF_RVV_FRM_ENUM(NAME, VALUE)
+#endif
+
 /* SEW/LMUL = 64:
Only enable when TARGET_MIN_VLEN > 32.
Machine mode = VNx1BImode when TARGET_MIN_VLEN < 128.
@@ -674,6 +679,12 @@ DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE)
 DEF_RVV_VXRM_ENUM (RDN, VXRM_RDN)
 DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD)
 
+DEF_RVV_FRM_ENUM (RNE, FRM_RNE)
+DEF_RVV_FRM_ENUM (RTZ, FRM_RTZ)
+DEF_RVV_FRM_ENUM (RDN, FRM_RDN)
+DEF_RVV_FRM_ENUM (RUP, FRM_RUP)
+DEF_RVV_FRM_ENUM (RMM, FRM_RMM)
+
 #include "riscv-vector-type-indexer.gen.def"
 
 #undef DEF_RVV_PRED_TYPE
@@ -683,3 +694,4 @@ DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD)
 #undef DEF_RVV_BASE_TYPE
 #undef DEF_RVV_TYPE_INDEX
 #undef DEF_RVV_VXRM_ENUM
+#undef DEF_RVV_FRM_ENUM
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
new file mode 100644
index 000..f5635fb959e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t f0 ()
+{
+  return FRM_RNE;
+}
+
+size_t f1 ()
+{
+  return FRM_RTZ;
+}
+
+size_t f2 ()
+{
+  return FRM_RDN;
+}
+
+size_t f3 ()
+{
+  return FRM_RUP;
+}
+
+size_t f4 ()
+{
+  return FRM_RMM;
+}
+
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*1} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*2} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*3} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*4} 1} } */
-- 
2.36.3

Re: [COMMITTED 4/4] - Gimple range PHI analyzer and testcases

[Aldy Hernandez via Gcc-patches]

Some minor nits.


+// There can be only one running at a time.
+static phi_analyzer *phi_analysis_object = NULL;


Shouldn't this be phi_analyzer_object to be more consistent?  Similarly 
throughout.



+// Create a new phi_group with members BM, initialvalue INIT_VAL, modifier
+// statement MOD, and resolve values using query Q.
+// Calculate the range for the gropup if possible, otherwise set it to
+// VARYING.
+
+phi_group::phi_group (bitmap bm, tree init_val, edge e, gimple *mod,
+ range_query *q)


Could you document what this edge refers to?


+  // we dont expect a modifer and no inital value, so trap to have a look.
+  // perhaps they are dead cycles and we can just used UNDEFINED.


"We don't"...

"Perhaps..."

s/used/use


+// Return 0 if S is not a modifier statment for group members BM.
+// If it could be a modifier, return which operand position (1 or 2)
+// the phi member occurs in.
+unsigned
+phi_group::is_modifier_p (gimple *s, const bitmap bm)


"not" a modifier?  Or *is* a modifier?

s/statment/statement


+  // Look at the modifier for any relation


Missing final period.


+  for (unsigned x = 0; x< 10; x++)


Space before "<"


+  // Never converged, so bail for now. we could examine the pattern
+  // from m_initial to m_vr as an extension  Especially if we had a way
+  // to project the actual number of iterations (SCEV?)


s/we/We/

s/extension Especially/extension, especially/


+// IF the modifier statement has a relation K between the modifier and the


s/IF/If/


+  // If the type wraps, then relations dont tell us much.


s/dont/don't/


+//   m_tab.safe_grow_cleared (num_ssa_names + 100);


why is this commented out?


+ // Other non-ssa names that arent constants are not understood


s/arent/aren't/


+ // Try to create a group based on m_current. If a result comes back


Two spaces after period.


+  // If this dpoesn;t form a group, all members are instead simple phis.


doesn't


+// their arguemnts contain nothing but other PHI defintions, with at most


arguments
definitions


+// These are the APIs to start and stop a phi analyzerin a SCEV like manner.


analyzer

Thanks for working on this.
Aldy

[COMMITTED] ada: Accept aliased parameters in Exceptional_Cases

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Aliased parameters, just like parameters by-reference types, can safely
appear in consequences of Exceptional_Cases aspect.

gcc/ada/

* sem_res.adb (Resolve_Entity_Name): Allow aliased parameters; tune
error message.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_res.adb | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 4e49a0a1473..17228689364 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -8087,6 +8087,7 @@ package body Sem_Res is
   and then Within_Exceptional_Cases_Consequence (N)
   and then not Is_Attribute_Old (Parent (N))
   and then not Is_By_Reference_Type (Etype (E))
+  and then not Is_Aliased (E)
 then
if Ekind (E) = E_Out_Parameter then
   Error_Msg_N
@@ -8098,7 +8099,7 @@ package body Sem_Res is
"in consequence of Exceptional_Cases", N);
end if;
Error_Msg_N
- ("\only parameters of by-reference types are allowed", N);
+ ("\only parameters passed by reference are allowed", N);
 end if;
 
 --  Check for possible elaboration issues with respect to reads of
-- 
2.40.0

[COMMITTED] ada: Restrict use of formal parameters within exceptional cases

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Restrict references to formal parameters within the new SPARK aspect
Exceptional_Cases and allow occurrences of 'Old in this aspect.

gcc/ada/

* sem_attr.adb
(Analyze_Attribute_Old_Result): Allow uses of 'Old and 'Result within
the new aspect.
* sem_res.adb
(Within_Exceptional_Cases_Consequence): New utility routine.
(Resolve_Entity_Name): Restrict use of formal parameters within the
new aspect.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_attr.adb |  8 ++
 gcc/ada/sem_res.adb  | 61 
 2 files changed, 69 insertions(+)

diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb
index bc4e3cf019e..0cfc2da29dd 100644
--- a/gcc/ada/sem_attr.adb
+++ b/gcc/ada/sem_attr.adb
@@ -1423,6 +1423,14 @@ package body Sem_Attr is
 elsif Prag_Nam = Name_Contract_Cases then
Check_Placement_In_Contract_Cases (Prag);
 
+--  Attributes 'Old and 'Result are allowed to appear in
+--  consequence of aspect or pragma Exceptional_Cases. We already
+--  examined the exception_choice part of contract syntax, so we
+--  can accept all remaining occurrences within the pragma.
+
+elsif Prag_Nam = Name_Exceptional_Cases then
+   null;
+
 --  Attribute 'Result is allowed to appear in aspect or pragma
 --  [Refined_]Depends (SPARK RM 6.1.5(11)).
 
diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 3b7d821158c..4e49a0a1473 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -7832,6 +7832,11 @@ package body Sem_Res is
   --  Determine whether Expr is part of an N_Attribute_Reference
   --  expression.
 
+  function Within_Exceptional_Cases_Consequence
+(Expr : Node_Id)
+ return Boolean;
+  --  Determine whether Expr is part of an Exceptional_Cases consequence
+
   
   -- Is_Assignment_Or_Object_Expression --
   
@@ -7896,6 +7901,39 @@ package body Sem_Res is
  return False;
   end Is_Attribute_Expression;
 
+  --
+  -- Within_Exceptional_Cases_Consequence --
+  --
+
+  function Within_Exceptional_Cases_Consequence
+(Expr : Node_Id)
+ return Boolean
+  is
+ Context : Node_Id := Parent (Expr);
+  begin
+ while Present (Context) loop
+if Nkind (Context) = N_Pragma then
+
+   --  In Exceptional_Cases references to formal parameters are
+   --  only allowed within consequences, so it is enough to
+   --  recognize the pragma itself.
+
+   if Get_Pragma_Id (Context) = Pragma_Exceptional_Cases then
+  return True;
+   end if;
+
+--  Prevent the search from going too far
+
+elsif Is_Body_Or_Package_Declaration (Context) then
+   return False;
+end if;
+
+Context := Parent (Context);
+ end loop;
+
+ return False;
+  end Within_Exceptional_Cases_Consequence;
+
   --  Local variables
 
   E   : constant Entity_Id := Entity (N);
@@ -8040,6 +8078,29 @@ package body Sem_Res is
   & "(SPARK RM 7.1.3(10))", N);
 end if;
 
+--  Parameters of modes OUT or IN OUT of the subprogram shall not
+--  occur in the consequences of an exceptional contract unless
+--  they either are of a by-reference type or occur in the prefix
+--  of a reference to the 'Old attribute.
+
+if Ekind (E) in E_Out_Parameter | E_In_Out_Parameter
+  and then Within_Exceptional_Cases_Consequence (N)
+  and then not Is_Attribute_Old (Parent (N))
+  and then not Is_By_Reference_Type (Etype (E))
+then
+   if Ekind (E) = E_Out_Parameter then
+  Error_Msg_N
+("formal parameter of mode `OUT` cannot appear " &
+   "in consequence of Exceptional_Cases", N);
+   else
+  Error_Msg_N
+("formal parameter of mode `IN OUT` cannot appear " &
+   "in consequence of Exceptional_Cases", N);
+   end if;
+   Error_Msg_N
+ ("\only parameters of by-reference types are allowed", N);
+end if;
+
 --  Check for possible elaboration issues with respect to reads of
 --  variables. The act of renaming the variable is not considered a
 --  read as it simply establishes an alias.
-- 
2.40.0

[COMMITTED] ada: Fix SPARK context not restored when Load_Unit is failing

[Marc Poulhiès via Gcc-patches]

When Load_Unit fails to find the unit or encounters an error, the
Load_Fail procedure is called and an exception is raised, skipping the
restoration of the SPARK/Ghost context stored on procedure entry.

gcc/ada/

* rtsfind.adb (Load_RTU.Restore_SPARK_Context): New.
(Load_RTU): Use Restore_SPARK_Context on all exit paths.
* sem_ch6.adb (Analyze_Subprogram_Body_Helper): Initialize local
variable to Empty.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/rtsfind.adb | 41 ++---
 gcc/ada/sem_ch6.adb |  2 +-
 2 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/gcc/ada/rtsfind.adb b/gcc/ada/rtsfind.adb
index 4b8e89e213f..278797ff491 100644
--- a/gcc/ada/rtsfind.adb
+++ b/gcc/ada/rtsfind.adb
@@ -1023,6 +1023,13 @@ package body Rtsfind is
   U: RT_Unit_Table_Record renames RT_Unit_Table (U_Id);
   Priv_Par : constant Elist_Id := New_Elmt_List;
   Lib_Unit : Node_Id;
+  Saved_GM  : constant Ghost_Mode_Type := Ghost_Mode;
+  Saved_IGR : constant Node_Id := Ignored_Ghost_Region;
+  Saved_ISMP : constant Boolean:=
+ Ignore_SPARK_Mode_Pragmas_In_Instance;
+  Saved_SM  : constant SPARK_Mode_Type := SPARK_Mode;
+  Saved_SMP : constant Node_Id := SPARK_Mode_Pragma;
+  --  Save Ghost and SPARK mode-related data to restore on exit
 
   procedure Save_Private_Visibility;
   --  If the current unit is the body of child unit or the spec of a
@@ -1034,6 +1041,9 @@ package body Rtsfind is
   procedure Restore_Private_Visibility;
   --  Restore the visibility of ancestors after compiling RTU
 
+  procedure Restore_SPARK_Context;
+  --  Restore Ghost and SPARK mode-related data saved on procedure entry
+
   
   -- Restore_Private_Visibility --
   
@@ -1075,15 +1085,16 @@ package body Rtsfind is
  end loop;
   end Save_Private_Visibility;
 
-  --  Local variables
+  ---
+  -- Restore_SPARK_Context --
+  ---
 
-  Saved_GM  : constant Ghost_Mode_Type := Ghost_Mode;
-  Saved_IGR : constant Node_Id := Ignored_Ghost_Region;
-  Saved_ISMP : constant Boolean:=
- Ignore_SPARK_Mode_Pragmas_In_Instance;
-  Saved_SM  : constant SPARK_Mode_Type := SPARK_Mode;
-  Saved_SMP : constant Node_Id := SPARK_Mode_Pragma;
-  --  Save Ghost and SPARK mode-related data to restore on exit
+  procedure Restore_SPARK_Context is
+  begin
+ Ignore_SPARK_Mode_Pragmas_In_Instance := Saved_ISMP;
+ Restore_Ghost_Region (Saved_GM, Saved_IGR);
+ Restore_SPARK_Mode   (Saved_SM, Saved_SMP);
+  end Restore_SPARK_Context;
 
--  Start of processing for Load_RTU
 
@@ -1195,9 +1206,17 @@ package body Rtsfind is
  Set_Is_Potentially_Use_Visible (U.Entity, True);
   end if;
 
-  Ignore_SPARK_Mode_Pragmas_In_Instance := Saved_ISMP;
-  Restore_Ghost_Region (Saved_GM, Saved_IGR);
-  Restore_SPARK_Mode   (Saved_SM, Saved_SMP);
+  Restore_SPARK_Context;
+
+   exception
+  --  The Load_Fail procedure that is called when the result of Load_Unit
+  --  is not satisfactory raises an exception. As the compiler is able to
+  --  recover in some cases (i.e. when RE_Not_Available is raised), we need
+  --  to restore the SPARK/Ghost context correctly.
+
+  when others =>
+ Restore_SPARK_Context;
+ raise;
end Load_RTU;
 

diff --git a/gcc/ada/sem_ch6.adb b/gcc/ada/sem_ch6.adb
index 992688cf092..48b363e077c 100644
--- a/gcc/ada/sem_ch6.adb
+++ b/gcc/ada/sem_ch6.adb
@@ -2277,7 +2277,7 @@ package body Sem_Ch6 is
   Mask_Types : Elist_Id  := No_Elist;
   Prot_Typ   : Entity_Id := Empty;
   Spec_Decl  : Node_Id   := Empty;
-  Spec_Id: Entity_Id;
+  Spec_Id: Entity_Id := Empty;
 
   Last_Real_Spec_Entity : Entity_Id := Empty;
   --  When we analyze a separate spec, the entity chain ends up containing
-- 
2.40.0

[COMMITTED] ada: Minor fixes in description of scope depth

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

In particular, the scope depth of library units is 1 instead of 0.

gcc/ada/

* einfo.ads (Scope_Depth): Fix circular definition.
(Scope_Depth_Value): Fix value for library units.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/einfo.ads | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/einfo.ads b/gcc/ada/einfo.ads
index 78a1534c749..b39cffd172c 100644
--- a/gcc/ada/einfo.ads
+++ b/gcc/ada/einfo.ads
@@ -4324,14 +4324,14 @@ package Einfo is
 --   concurrent types, private types and entries, and also to record types,
 --   i.e. to any entity that can appear on the scope stack. Yields the
 --   scope depth value, which for those entities other than records is
---   simply the scope depth value, for record entities, it is the
---   Scope_Depth of the record scope.
+--   simply the Scope_Depth_Value, and for record entities, is the
+--   Scope_Depth of the record's scope.
 
 --Scope_Depth_Value
 --   Defined in program units, blocks, loops, return statements,
 --   concurrent types, private types and entries.
 --   Indicates the number of scopes that statically enclose the declaration
---   of the unit or type. Library units have a depth of zero. Note that
+--   of the unit or type. Library units have a depth of one. Note that
 --   record types can act as scopes but do NOT have this field set (see
 --   Scope_Depth above). Queries should normally be via Scope_Depth,
 --   and not call Scope_Depth_Value directly.
-- 
2.40.0

[COMMITTED] ada: Tune warning about assignment just before a raise statement

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Tune warning about a possibly ineffective assignment to a formal
parameter that happens just before a raise statement.

The warning is now emitted for parameters of all by-copy types and not
just of scalar types (this gives more warnings), but is suppressed for
aliased parameters (this removes some spurious warnings).

gcc/ada/

* sem_ch11.adb (Analyze_Raise_Expression): Tune warning condition.
* libgnat/g-dirope.ads (Open): Remove a potentially inaccurate comment.
* libgnat/g-dirope.adb (Open): Remove a potentially useless assignment;
the Dir output parameter should be assigned a null value anyway by the
preceding call to Free.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/libgnat/g-dirope.adb | 1 -
 gcc/ada/libgnat/g-dirope.ads | 3 +--
 gcc/ada/sem_ch11.adb | 7 ---
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/gcc/ada/libgnat/g-dirope.adb b/gcc/ada/libgnat/g-dirope.adb
index 127f6ba8e80..3cebc9fe4a7 100644
--- a/gcc/ada/libgnat/g-dirope.adb
+++ b/gcc/ada/libgnat/g-dirope.adb
@@ -636,7 +636,6 @@ package body GNAT.Directory_Operations is
 
   if not Is_Open (Dir) then
  Free (Dir);
- Dir := Null_Dir;
  raise Directory_Error;
   end if;
end Open;
diff --git a/gcc/ada/libgnat/g-dirope.ads b/gcc/ada/libgnat/g-dirope.ads
index a3a8e4635f0..cdb99ff3267 100644
--- a/gcc/ada/libgnat/g-dirope.ads
+++ b/gcc/ada/libgnat/g-dirope.ads
@@ -210,8 +210,7 @@ package GNAT.Directory_Operations is
procedure Open (Dir : out Dir_Type; Dir_Name : Dir_Name_Str);
--  Opens the directory named by Dir_Name and returns a Dir_Type value
--  that refers to this directory, and is positioned at the first entry.
-   --  Raises Directory_Error if Dir_Name cannot be accessed. In that case
-   --  Dir will be set to Null_Dir.
+   --  Raises Directory_Error if Dir_Name cannot be accessed.
 
procedure Close (Dir : in out Dir_Type);
--  Closes the directory stream referred to by Dir. After calling Close
diff --git a/gcc/ada/sem_ch11.adb b/gcc/ada/sem_ch11.adb
index 547d682..73eca7a603e 100644
--- a/gcc/ada/sem_ch11.adb
+++ b/gcc/ada/sem_ch11.adb
@@ -543,11 +543,12 @@ package body Sem_Ch11 is
 if Present (P) and then Nkind (P) = N_Assignment_Statement then
L := Name (P);
 
-   --  Give warning for assignment to scalar formal
+   --  Give warning for assignment to by-copy formal
 
-   if Is_Scalar_Type (Etype (L))
- and then Is_Entity_Name (L)
+   if Is_Entity_Name (L)
  and then Is_Formal (Entity (L))
+ and then Is_By_Copy_Type (Etype (L))
+ and then not Is_Aliased (Entity (L))
 
  --  Do this only for parameters to the current subprogram.
  --  This avoids some false positives for the nested case.
-- 
2.40.0

[COMMITTED] ada: Fix obsolete comment in Sinfo.Utils

[Marc Poulhiès via Gcc-patches]

From: Bob Duff 

...caused by moving code here from Atree.

gcc/ada/

* sinfo-utils.adb: Update comment to refer to
New_Node_Debugging_Output.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sinfo-utils.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/sinfo-utils.adb b/gcc/ada/sinfo-utils.adb
index 02ed69d7136..b0cc2d3b418 100644
--- a/gcc/ada/sinfo-utils.adb
+++ b/gcc/ada/sinfo-utils.adb
@@ -50,7 +50,7 @@ package body Sinfo.Utils is
 
--  Either way, gnat1 will stop when node 12345 is created, or certain other
--  interesting operations are performed, such as Rewrite. To see exactly
-   --  which operations, search for "pragma Debug" below.
+   --  which operations, search for "New_Node_Debugging_Output" in Atree.
 
--  The second method is much faster if the amount of Ada code being
--  compiled is large.
-- 
2.40.0

[COMMITTED] ada: Reduce span of variable

[Marc Poulhiès via Gcc-patches]

From: Ronan Desplanques 

This patch does not change the behavior of the compiler, but is
intended to improve readability. It seizes an opportunity to move
a variable declaration to a smaller scope, so that it's clearer
that the variable is not used outside of that scope.

gcc/ada/

* sem_ch3.adb (Replace_Type): Reduce span of variable.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch3.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb
index a0783195b8b..c8af679b404 100644
--- a/gcc/ada/sem_ch3.adb
+++ b/gcc/ada/sem_ch3.adb
@@ -15901,7 +15901,6 @@ package body Sem_Ch3 is
 
   procedure Replace_Type (Id, New_Id : Entity_Id) is
  Id_Type  : constant Entity_Id := Etype (Id);
- Acc_Type : Entity_Id;
  Par  : constant Node_Id := Parent (Derived_Type);
 
   begin
@@ -15913,6 +15912,7 @@ package body Sem_Ch3 is
 
  if Ekind (Id_Type) = E_Anonymous_Access_Type then
 declare
+   Acc_Type  : Entity_Id;
Desig_Typ : Entity_Id := Designated_Type (Id_Type);
 
 begin
-- 
2.40.0

[COMMITTED] ada: Fix error message for Aggregate aspect

[Marc Poulhiès via Gcc-patches]

The error message was wrongly using % instead of & in the format string,
causing the displayed message to refer to incorrect names in some cases.

gcc/ada/

* sem_ch13.adb (Check_Aspect_At_Freeze_Point): fix format string,
use existing local Ident.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch13.adb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/sem_ch13.adb b/gcc/ada/sem_ch13.adb
index 6f9fe738ddd..593e6f8c169 100644
--- a/gcc/ada/sem_ch13.adb
+++ b/gcc/ada/sem_ch13.adb
@@ -11224,8 +11224,8 @@ package body Sem_Ch13 is
  when Aspect_Aggregate =>
 if Is_Array_Type (Entity (ASN)) then
Error_Msg_N
- ("aspect% can only be applied to non-array type",
-  Identifier (ASN));
+ ("aspect& can only be applied to non-array type",
+  Ident);
 end if;
 Resolve_Aspect_Aggregate (Entity (ASN), Expression (ASN));
 return;
-- 
2.40.0

[COMMITTED] ada: Handle controlling access parameters in DTWs

[Marc Poulhiès via Gcc-patches]

From: Ronan Desplanques 

This patch improves the way controlling access parameters are
handled in dispatch table wrappers. The constructions of both the
specifications and the bodies of wrappers are modified.

gcc/ada/

* freeze.adb (Build_DTW_Body): Add appropriate type conversions for
controlling access parameters.
* sem_util.adb (Build_Overriding_Spec): Fix designated types in
controlling access parameters.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/freeze.adb   | 7 ++-
 gcc/ada/sem_util.adb | 7 +--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/gcc/ada/freeze.adb b/gcc/ada/freeze.adb
index 6014f71e661..1a1eace600b 100644
--- a/gcc/ada/freeze.adb
+++ b/gcc/ada/freeze.adb
@@ -1555,7 +1555,6 @@ package body Freeze is
  Par_Prim : Entity_Id;
  Wrapped_Subp : Entity_Id) return Node_Id
   is
- Par_Typ: constant Entity_Id := Find_Dispatching_Type (Par_Prim);
  Actuals: constant List_Id   := Empty_List;
  Call   : Node_Id;
  Formal : Entity_Id := First_Formal (Par_Prim);
@@ -1571,12 +1570,10 @@ package body Freeze is
 --  If the controlling argument is inherited, add conversion to
 --  parent type for the call.
 
-if Etype (Formal) = Par_Typ
-  and then Is_Controlling_Formal (Formal)
-then
+if Is_Controlling_Formal (Formal) then
Append_To (Actuals,
  Make_Type_Conversion (Loc,
-   New_Occurrence_Of (Par_Typ, Loc),
+   New_Occurrence_Of (Etype (Formal), Loc),
New_Occurrence_Of (New_Formal, Loc)));
 else
Append_To (Actuals, New_Occurrence_Of (New_Formal, Loc));
diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index b28f2899894..2e2fb911c38 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -2234,9 +2234,12 @@ package body Sem_Util is
and then Entity (Formal_Type) = Par_Typ
  then
 Rewrite (Formal_Type, New_Occurrence_Of (Typ, Loc));
- end if;
 
- --  Nothing needs to be done for access parameters
+ elsif Nkind (Formal_Type) = N_Access_Definition
+   and then Entity (Subtype_Mark (Formal_Type)) = Par_Typ
+ then
+Rewrite (Subtype_Mark (Formal_Type), New_Occurrence_Of (Typ, Loc));
+ end if;
 
  Next (Formal_Spec);
   end loop;
-- 
2.40.0

[COMMITTED] ada: Fix incorrect handling of Aggregate aspect

[Marc Poulhiès via Gcc-patches]

This change fixes 2 incorrect handlings of the aspect.
The arguments are now correctly resolved and the aspect is rejected on
non array types.

gcc/ada/

* sem_ch13.adb (Analyze_One_Aspect): Mark Aggregate aspect as
needing delayed resolution and reject the aspect on non-array
type.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch13.adb | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/sem_ch13.adb b/gcc/ada/sem_ch13.adb
index d40c70f6ee4..a3819725181 100644
--- a/gcc/ada/sem_ch13.adb
+++ b/gcc/ada/sem_ch13.adb
@@ -2908,10 +2908,10 @@ package body Sem_Ch13 is
 end case;
 
 if Delay_Required
-
and then (A_Id = Aspect_Stable_Properties
   or else A_Id = Aspect_Designated_Storage_Model
-  or else A_Id = Aspect_Storage_Model_Type)
+  or else A_Id = Aspect_Storage_Model_Type
+  or else A_Id = Aspect_Aggregate)
--  ??? It seems like we should do this for all aspects, not
--  just these, but that causes as-yet-undiagnosed regressions.
 
@@ -4203,6 +4203,12 @@ package body Sem_Ch13 is
   Aitem := Empty;
 
when Aspect_Aggregate =>
+  if Is_Array_Type (E) then
+ Error_Msg_N
+   ("aspect% can only be applied to non-array type", Id);
+ goto Continue;
+  end if;
+
   Validate_Aspect_Aggregate (Expr);
   Record_Rep_Item (E, Aspect);
   goto Continue;
-- 
2.40.0

[COMMITTED] ada: Add missing supportive code for recently added SPARK aspects

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Fix minor inconsistencies with the recently added SPARK aspects
Exceptional_Cases and Subprogram_Variant, whose implementation is based
on Contract_Cases.

gcc/ada/

* aspects.ads
(Implementation_Defined_Aspect): Recently added aspects are
implementation-defined, just like Contract_Cases.
* sem_prag.ads
(Aspect_Specifying_Pragma): Recently added aspects have corresponding
pragmas, just like Contract_Cases.
(Pragma_Significant_To_Subprograms): Recently added aspects are
significant to subprograms, just like Contract_Cases.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/aspects.ads  |  2 ++
 gcc/ada/sem_prag.ads | 46 
 2 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/gcc/ada/aspects.ads b/gcc/ada/aspects.ads
index 6670b64ca49..5771967 100644
--- a/gcc/ada/aspects.ads
+++ b/gcc/ada/aspects.ads
@@ -270,6 +270,7 @@ package Aspects is
   Aspect_Dimension_System   => True,
   Aspect_Effective_Reads=> True,
   Aspect_Effective_Writes   => True,
+  Aspect_Exceptional_Cases  => True,
   Aspect_Extensions_Visible => True,
   Aspect_Favor_Top_Level=> True,
   Aspect_Ghost  => True,
@@ -292,6 +293,7 @@ package Aspects is
   Aspect_Shared => True,
   Aspect_Simple_Storage_Pool=> True,
   Aspect_Simple_Storage_Pool_Type   => True,
+  Aspect_Subprogram_Variant => True,
   Aspect_Suppress_Debug_Info=> True,
   Aspect_Suppress_Initialization=> True,
   Aspect_Thread_Local_Storage   => True,
diff --git a/gcc/ada/sem_prag.ads b/gcc/ada/sem_prag.ads
index 993ff7a986b..cbeb815ee0e 100644
--- a/gcc/ada/sem_prag.ads
+++ b/gcc/ada/sem_prag.ads
@@ -59,6 +59,7 @@ package Sem_Prag is
   Pragma_Effective_Reads  => True,
   Pragma_Effective_Writes => True,
   Pragma_Elaborate_Body   => True,
+  Pragma_Exceptional_Cases=> True,
   Pragma_Export   => True,
   Pragma_Extensions_Visible   => True,
   Pragma_Favor_Top_Level  => True,
@@ -109,6 +110,7 @@ package Sem_Prag is
   Pragma_Simple_Storage_Pool_Type => True,
   Pragma_SPARK_Mode   => True,
   Pragma_Storage_Size => True,
+  Pragma_Subprogram_Variant   => True,
   Pragma_Suppress => True,
   Pragma_Suppress_Debug_Info  => True,
   Pragma_Suppress_Initialization  => True,
@@ -208,27 +210,29 @@ package Sem_Prag is
--  of subprogram bodies.
 
Pragma_Significant_To_Subprograms : constant array (Pragma_Id) of Boolean :=
- (Pragma_Contract_Cases=> True,
-  Pragma_Depends   => True,
-  Pragma_Ghost => True,
-  Pragma_Global=> True,
-  Pragma_Inline=> True,
-  Pragma_Inline_Always => True,
-  Pragma_Post  => True,
-  Pragma_Post_Class=> True,
-  Pragma_Postcondition => True,
-  Pragma_Pre   => True,
-  Pragma_Pre_Class => True,
-  Pragma_Precondition  => True,
-  Pragma_Pure  => True,
-  Pragma_Pure_Function => True,
-  Pragma_Refined_Depends   => True,
-  Pragma_Refined_Global=> True,
-  Pragma_Refined_Post  => True,
-  Pragma_Refined_State => True,
-  Pragma_Volatile  => True,
-  Pragma_Volatile_Function => True,
-  others   => False);
+ (Pragma_Contract_Cases => True,
+  Pragma_Depends=> True,
+  Pragma_Exceptional_Cases  => True,
+  Pragma_Ghost  => True,
+  Pragma_Global => True,
+  Pragma_Inline => True,
+  Pragma_Inline_Always  => True,
+  Pragma_Post   => True,
+  Pragma_Post_Class => True,
+  Pragma_Postcondition  => True,
+  Pragma_Pre=> True,
+  Pragma_Pre_Class  => True,
+  Pragma_Precondition   => True,
+  Pragma_Pure   => True,
+  Pragma_Pure_Function  => True,
+  Pragma_Refined_Depends=> True,
+  Pragma_Refined_Global => True,
+  Pragma_Refined_Post   => True,
+  Pragma_Refined_State  => True,
+  Pragma_Subprogram_Variant => True,
+  Pragma_Volatile   => True,
+  Pragma_Volatile_Function  => True,
+  others=> False);
 
-
-- Subprograms --
-- 
2.40.0

[COMMITTED] ada: Fix internal error on declare-expression in post-condition

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

It comes from an incorrect node sharing in the expanded tree.

gcc/ada/

* sem_ch3.adb (Find_Type_Of_Object): Copy the object definition when
building the subtype declaration in the case of a spec expression.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch3.adb | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb
index 1ed590ba519..9e32dea5c02 100644
--- a/gcc/ada/sem_ch3.adb
+++ b/gcc/ada/sem_ch3.adb
@@ -18423,19 +18423,21 @@ package body Sem_Ch3 is
 Analyze (Subtype_Mark (Obj_Def));
 
 declare
-   Base_T : constant Entity_Id := Entity (Subtype_Mark (Obj_Def));
-   Decl   : constant Node_Id :=
+   Base_T  : constant Entity_Id := Entity (Subtype_Mark (Obj_Def));
+   New_Def : constant Node_Id   := New_Copy_Tree (Obj_Def);
+   Decl: constant Node_Id   :=
  Make_Subtype_Declaration (Sloc (P),
Defining_Identifier => T,
-   Subtype_Indication  => Relocate_Node (Obj_Def));
+   Subtype_Indication  => New_Def);
+
 begin
Set_Etype  (T, Base_T);
Mutate_Ekind  (T, Subtype_Kind (Ekind (Base_T)));
-   Set_Parent (T, Obj_Def);
+   Set_Parent (T, Decl);
Set_Scope (T, Current_Scope);
 
if Ekind (T) = E_Array_Subtype then
-  Constrain_Array (T, Obj_Def, Related_Nod, T, 'P');
+  Constrain_Array (T, New_Def, Related_Nod, T, 'P');
 
elsif Ekind (T) = E_Record_Subtype then
   Set_First_Entity (T, First_Entity (Base_T));
-- 
2.40.0

[COMMITTED] ada: Enrich documentation of subprogram

[Marc Poulhiès via Gcc-patches]

From: Ronan Desplanques 

This patch adds documentation to the subprogram Replace_Type in
Sem_Ch3. In particular, references to relevant parts of the Ada
reference manual are added.

gcc/ada/

* sem_ch3.adb (Replace_Type): Add more documentation.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch3.adb | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb
index 0bddfa84463..db2bbb5ee8e 100644
--- a/gcc/ada/sem_ch3.adb
+++ b/gcc/ada/sem_ch3.adb
@@ -15849,7 +15849,11 @@ package body Sem_Ch3 is
   --  derived type.
 
   procedure Replace_Type (Id, New_Id : Entity_Id);
-  --  When the type is an anonymous access type, create a new access type
+  --  Set the Etype of New_Id to the appropriate subtype determined from
+  --  the Etype of Id, following (RM 3.4 (18, 19, 20, 21)). Id is either
+  --  the parent type's primitive subprogram or one of its formals, and
+  --  New_Id is the corresponding entity for the derived type. When the
+  --  Etype of Id is an anonymous access type, create a new access type
   --  designating the derived type.
 
   procedure Set_Derived_Name;
-- 
2.40.0

[COMMITTED] ada: Add Entry_Cancel_Parameter to E_Label

[Marc Poulhiès via Gcc-patches]

From: Bob Duff 

...and other (minor) changes.

gcc/ada/

* gen_il-gen-gen_entities.adb (E_Label): Add
Entry_Cancel_Parameter. This is necessary because
Analyze_Implicit_Label_Declaration set the Ekind to E_Label.
Without this change, this field would fail the vanishing-fields
check in Atree (which is currently commented out).
* einfo.ads (Entry_Cancel_Parameter): Document for E_Label.
* sem_eval.adb (Why_Not_Static): Protect against previous errors
(no need to explain why something is not static if it's already
illegal for other reasons).
* sem_util.ads (Enter_Name): Fix misleading comment.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/einfo.ads   | 3 +++
 gcc/ada/gen_il-gen-gen_entities.adb | 1 +
 gcc/ada/sem_eval.adb| 2 +-
 gcc/ada/sem_util.ads| 6 --
 4 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/einfo.ads b/gcc/ada/einfo.ads
index b39cffd172c..7dc2bd178cc 100644
--- a/gcc/ada/einfo.ads
+++ b/gcc/ada/einfo.ads
@@ -1131,6 +1131,8 @@ package Einfo is
 --   object for task entry calls and a Communications_Block object
 --   in the case of protected entry calls. In both cases the objects
 --   are declared in outer scopes to this block.
+--   This is also defined in labels, because we temporarily set the
+--   Ekind of an E_Block to E_Label in Analyze_Implicit_Label_Declaration.
 
 --Entry_Component
 --   Defined in formal parameters (in, in out and out parameters). Used
@@ -5660,6 +5662,7 @@ package Einfo is
--  E_Label
--Renamed_Object $$$
--Renamed_Entity $$$
+   --Entry_Cancel_Parameter
--Enclosing_Scope
--Reachable
 
diff --git a/gcc/ada/gen_il-gen-gen_entities.adb 
b/gcc/ada/gen_il-gen-gen_entities.adb
index ebc0f204b03..67efc5d0f9a 100644
--- a/gcc/ada/gen_il-gen-gen_entities.adb
+++ b/gcc/ada/gen_il-gen-gen_entities.adb
@@ -1224,6 +1224,7 @@ begin -- Gen_IL.Gen.Gen_Entities
--  implicit label declaration, not the occurrence of the label itself,
--  which is simply a direct name referring to the label.
(Sm (Enclosing_Scope, Node_Id),
+Sm (Entry_Cancel_Parameter, Node_Id),
 Sm (Reachable, Flag),
 Sm (Renamed_Or_Alias, Node_Id)));
 
diff --git a/gcc/ada/sem_eval.adb b/gcc/ada/sem_eval.adb
index e54f4a637e2..905e7ff55b7 100644
--- a/gcc/ada/sem_eval.adb
+++ b/gcc/ada/sem_eval.adb
@@ -7611,7 +7611,7 @@ package body Sem_Eval is
Error_Msg_NE
  ("!& is not a static subtype (RM 4.9(26))", N, E);
 
-else
+elsif E /= Any_Id then
Error_Msg_NE
  ("!& is not static constant or named number "
   & "(RM 4.9(5))", N, E);
diff --git a/gcc/ada/sem_util.ads b/gcc/ada/sem_util.ads
index 4028d370823..4962c62fa7d 100644
--- a/gcc/ada/sem_util.ads
+++ b/gcc/ada/sem_util.ads
@@ -809,8 +809,10 @@ package Sem_Util is
procedure Enter_Name (Def_Id : Entity_Id);
--  Insert new name in symbol table of current scope with check for
--  duplications (error message is issued if a conflict is found).
-   --  Note: Enter_Name is not used for overloadable entities, instead these
-   --  are entered using Sem_Ch6.Enter_Overloaded_Entity.
+   --  Note: Enter_Name is not used for most overloadable entities, instead
+   --  they are entered using Sem_Ch6.Enter_Overloaded_Entity. However,
+   --  this is used for SOME overloadable entities, such as enumeration
+   --  literals and certain operator symbols.
 
function Entity_Of (N : Node_Id) return Entity_Id;
--  Obtain the entity of arbitrary node N. If N is a renaming, return the
-- 
2.40.0

[COMMITTED] ada: Fix crash during function return analysis

[Marc Poulhiès via Gcc-patches]

The compiler would crash when checking type relation between the
function's return type and the type of the expression used in the return
statement. It would not work if the function's return type is an access
type and the expression is not.

gcc/ada/

* sem_ch6.adb (Analyze_Function_Return): Add missing
Is_Access_Type check before accessing the Designated_Type field.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch6.adb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/ada/sem_ch6.adb b/gcc/ada/sem_ch6.adb
index 7c90747f293..6df1c8dedd3 100644
--- a/gcc/ada/sem_ch6.adb
+++ b/gcc/ada/sem_ch6.adb
@@ -847,6 +847,7 @@ package body Sem_Ch6 is
   and then Serious_Errors_Detected = 0
   and then Is_Access_Type (R_Type)
   and then Nkind (Expr) not in N_Null | N_Raise_Expression
+  and then Is_Access_Type (Etype (Expr))
   and then Is_Interface (Designated_Type (R_Type))
   and then Is_Progenitor (Designated_Type (R_Type),
   Designated_Type (Etype (Expr)))
-- 
2.40.0

[COMMITTED] ada: Set Is_Not_Self_Hidden flag in more cases

[Marc Poulhiès via Gcc-patches]

From: Bob Duff 

More work-in-progress for changing E_Void checks to the flag.

gcc/ada/

* sem_ch9.adb (Analyze_Protected_Type_Declaration): Set the flag
for protected types.
(Analyze_Single_Protected_Declaration): Likewise, for singleton
protected objects.
(Analyze_Task_Type_Declaration): Set the flag for task types.
(Analyze_Single_Task_Declaration): Likewise, for singleton task
objects.
* sem_ch10.adb (Decorate_Type): Set the flag for types treated as
incomplete.
(Build_Shadow_Entity): Set the flag for shadow entities.
(Decorate_State): Set the flag for an abstract state.
(Build_Limited_Views): Set the flag for limited view of package.
* sem_attr.adb (Check_Not_Incomplete_Type): Disable the check when
this is a current instance.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_attr.adb | 2 +-
 gcc/ada/sem_ch10.adb | 8 ++--
 gcc/ada/sem_ch9.adb  | 4 
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb
index 0cfc2da29dd..efea03670c3 100644
--- a/gcc/ada/sem_attr.adb
+++ b/gcc/ada/sem_attr.adb
@@ -2517,7 +2517,7 @@ package body Sem_Attr is
or else In_Spec_Expression
  then
 return;
- else
+ elsif not Is_Current_Instance (P) then
 Check_Fully_Declared (P_Type, P);
  end if;
   end Check_Not_Incomplete_Type;
diff --git a/gcc/ada/sem_ch10.adb b/gcc/ada/sem_ch10.adb
index c9bbd773424..a6cbe466b75 100644
--- a/gcc/ada/sem_ch10.adb
+++ b/gcc/ada/sem_ch10.adb
@@ -3306,6 +3306,7 @@ package body Sem_Ch10 is
   --  incomplete type, and carries the corresponding attributes.
 
   Mutate_Ekind   (Ent, E_Incomplete_Type);
+  Set_Is_Not_Self_Hidden (Ent);
   Set_Etype  (Ent, Ent);
   Set_Full_View  (Ent, Empty);
   Set_Is_First_Subtype   (Ent);
@@ -5989,7 +5990,8 @@ package body Sem_Ch10 is
 Mutate_Ekind (Shadow, Ekind (Ent));
  end if;
 
- Set_Is_Internal   (Shadow);
+ Set_Is_Not_Self_Hidden (Shadow);
+ Set_Is_Internal (Shadow);
  Set_From_Limited_With (Shadow);
 
  --  Add the new shadow entity to the limited view of the package
@@ -6056,6 +6058,7 @@ package body Sem_Ch10 is
   procedure Decorate_State (Ent : Entity_Id; Scop : Entity_Id) is
   begin
  Mutate_Ekind(Ent, E_Abstract_State);
+ Set_Is_Not_Self_Hidden  (Ent);
  Set_Etype   (Ent, Standard_Void_Type);
  Set_Scope   (Ent, Scop);
  Set_Encapsulating_State (Ent, Empty);
@@ -6416,11 +6419,12 @@ package body Sem_Ch10 is
 raise Program_Error;
   end case;
 
-  --  The withed unit may not be analyzed, but the with calause itself
+  --  The withed unit may not be analyzed, but the with clause itself
   --  must be minimally decorated. This ensures that the checks on unused
   --  with clauses also process limieted withs.
 
   Mutate_Ekind (Pack, E_Package);
+  Set_Is_Not_Self_Hidden (Pack);
   Set_Etype (Pack, Standard_Void_Type);
 
   if Is_Entity_Name (Nam) then
diff --git a/gcc/ada/sem_ch9.adb b/gcc/ada/sem_ch9.adb
index 90b0ff08540..a15e37b7ce7 100644
--- a/gcc/ada/sem_ch9.adb
+++ b/gcc/ada/sem_ch9.adb
@@ -2067,6 +2067,7 @@ package body Sem_Ch9 is
   end if;
 
   Mutate_Ekind   (T, E_Protected_Type);
+  Set_Is_Not_Self_Hidden (T);
   Set_Is_First_Subtype   (T);
   Reinit_Size_Align  (T);
   Set_Etype  (T, T);
@@ -2901,6 +2902,7 @@ package body Sem_Ch9 is
 
   Enter_Name (Obj_Id);
   Mutate_Ekind   (Obj_Id, E_Variable);
+  Set_Is_Not_Self_Hidden (Obj_Id);
   Set_Etype  (Obj_Id, Typ);
   Set_SPARK_Pragma   (Obj_Id, SPARK_Mode_Pragma);
   Set_SPARK_Pragma_Inherited (Obj_Id);
@@ -2987,6 +2989,7 @@ package body Sem_Ch9 is
 
   Enter_Name (Obj_Id);
   Mutate_Ekind   (Obj_Id, E_Variable);
+  Set_Is_Not_Self_Hidden (Obj_Id);
   Set_Etype  (Obj_Id, Typ);
   Set_SPARK_Pragma   (Obj_Id, SPARK_Mode_Pragma);
   Set_SPARK_Pragma_Inherited (Obj_Id);
@@ -3265,6 +3268,7 @@ package body Sem_Ch9 is
   end if;
 
   Mutate_Ekind   (T, E_Task_Type);
+  Set_Is_Not_Self_Hidden (T);
   Set_Is_First_Subtype   (T, True);
   Set_Has_Task   (T, True);
   Reinit_Size_Align  (T);
-- 
2.40.0

[COMMITTED] ada: Fix comments for recently added SPARK aspects

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Implementation of contract Subprogram_Variant and Exceptional_Cases was
based on the existing code for Contract_Cases, i.e. on the existing
occurrences of Aspect_Contract_Cases, Name_Contract_Cases and
Pragma_Contract_Cases. However, occurrences of "Contract_Cases" itself
in the comments were not updated.

gcc/ada/

* contracts.adb
(Add_Pre_Post_Condition): Mention new aspects in the comment.
* contracts.ads
(Add_Contract_Item): Likewise.
(Analyze_Subprogram_Body_Stub_Contract): Likewise.
* sem_prag.adb
(Contract_Freeze_Error): Likewise.
(Ensure_Aggregate_Form): Likewise.
* sem_prag.ads
(Find_Related_Declaration_Or_Body): Likewise.
* sinfo.ads
(Is_Generic_Contract_Pragma): Likewise.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/contracts.adb |  2 ++
 gcc/ada/contracts.ads |  4 
 gcc/ada/sem_prag.adb  | 18 +-
 gcc/ada/sem_prag.ads  |  2 ++
 gcc/ada/sinfo.ads |  2 ++
 5 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/gcc/ada/contracts.adb b/gcc/ada/contracts.adb
index c85df0fccc8..e2df8b96a65 100644
--- a/gcc/ada/contracts.adb
+++ b/gcc/ada/contracts.adb
@@ -223,11 +223,13 @@ package body Contracts is
   --Attach_Handler
   --Contract_Cases
   --Depends
+  --Exceptional_Cases
   --Extensions_Visible
   --Global
   --Interrupt_Handler
   --Postcondition
   --Precondition
+  --Subprogram_Variant
   --Test_Case
   --Volatile_Function
 
diff --git a/gcc/ada/contracts.ads b/gcc/ada/contracts.ads
index a53565fe003..0625b9fc029 100644
--- a/gcc/ada/contracts.ads
+++ b/gcc/ada/contracts.ads
@@ -45,6 +45,7 @@ package Contracts is
--Depends
--Effective_Reads
--Effective_Writes
+   --Exceptional_Cases
--Extensions_Visible
--Global
--Initial_Condition
@@ -58,6 +59,7 @@ package Contracts is
--Refined_Global
--Refined_Post
--Refined_States
+   --Subprogram_Variant
--Test_Case
--Volatile_Function
 
@@ -173,12 +175,14 @@ package Contracts is
--
--Contract_Cases
--Depends
+   --Exceptional_Cases
--Global
--Postcondition
--Precondition
--Refined_Depends
--Refined_Global
--Refined_Post
+   --Subprogram_Variant
--Test_Case
 
procedure Analyze_Task_Contract (Task_Id : Entity_Id);
diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb
index 40636f21fc7..d66e5612135 100644
--- a/gcc/ada/sem_prag.adb
+++ b/gcc/ada/sem_prag.adb
@@ -225,10 +225,10 @@ package body Sem_Prag is
procedure Contract_Freeze_Error
  (Contract_Id : Entity_Id;
   Freeze_Id   : Entity_Id);
-   --  Subsidiary to the analysis of pragmas Contract_Cases, Part_Of, Post, and
-   --  Pre. Emit a freezing-related error message where Freeze_Id is the entity
-   --  of a body which caused contract freezing and Contract_Id denotes the
-   --  entity of the affected contstruct.
+   --  Subsidiary to the analysis of pragmas Contract_Cases, Exceptional_Cases,
+   --  Part_Of, Post, Pre and Subprogram_Variant. Emit a freezing-related error
+   --  message where Freeze_Id is the entity of a body which caused contract
+   --  freezing and Contract_Id denotes the entity of the affected contstruct.
 
procedure Duplication_Error (Prag : Node_Id; Prev : Node_Id);
--  Subsidiary to all Find_Related_xxx routines. Emit an error on pragma
@@ -4515,11 +4515,11 @@ package body Sem_Prag is
 
   procedure Ensure_Aggregate_Form (Arg : Node_Id);
   --  Subsidiary routine to the processing of pragmas Abstract_State,
-  --  Contract_Cases, Depends, Global, Initializes, Refined_Depends,
-  --  Refined_Global, Refined_State and Subprogram_Variant. Transform
-  --  argument Arg into an aggregate if not one already. N_Null is never
-  --  transformed. Arg may denote an aspect specification or a pragma
-  --  argument association.
+  --  Contract_Cases, Depends, Exceptional_Cases, Global, Initializes,
+  --  Refined_Depends, Refined_Global, Refined_State and
+  --  Subprogram_Variant. Transform argument Arg into an aggregate if not
+  --  one already. N_Null is never transformed. Arg may denote an aspect
+  --  specification or a pragma argument association.
 
   procedure Error_Pragma (Msg : String);
   pragma No_Return (Error_Pragma);
diff --git a/gcc/ada/sem_prag.ads b/gcc/ada/sem_prag.ads
index cbeb815ee0e..49c1d0b4892 100644
--- a/gcc/ada/sem_prag.ads
+++ b/gcc/ada/sem_prag.ads
@@ -447,6 +447,7 @@ package Sem_Prag is
--  Subsidiary to the analysis of pragmas
--Contract_Cases
--Depends
+   --Exceptional_Cases
--Extensions_Visible
--Global
--Initializes
@@ -463,6 +464,7 @@ package Sem_Prag is
--Refined_Global
-

[COMMITTED] ada: Prevent search of calls in preconditions from going too far

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

When determining whether a call to protected function appears within
a pragma expression we can safely stop at the subprogram body.

Cleanup related to recently added support for a new SPARK aspects,
whose implementation was based on Contract_Cases.

gcc/ada/

* sem_util.adb (Check_Internal_Protected_Use): Add standard protection
against search going too far.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 5 +
 1 file changed, 5 insertions(+)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 2e2fb911c38..bfe1b9fc74d 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -3501,6 +3501,11 @@ package body Sem_Util is
 ("internal call cannot appear in default for formal of "
  & "protected operation", N);
   return;
+
+   --  Prevent the search from going too far
+
+   elsif Is_Body_Or_Package_Declaration (P) then
+  exit;
end if;
 
P := Parent (P);
-- 
2.40.0

[COMMITTED] ada: Small tweak to implementation of by-copy semantics for storage models

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

Get_Actual_Subtype can be used to access the Actual_Designated_Subtype of
explicit dereferences with a storage model. As a side effect, this also
handles the case where the prefix of the dereference is a formal parameter.

gcc/ada/

* exp_ch6.adb (Add_Simple_Call_By_Copy_Code): Use Get_Actual_Subtype
to retrieve the actual subtype for all actuals and do it in only one
place for all unconstrained composite formal types.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch6.adb | 29 -
 1 file changed, 4 insertions(+), 25 deletions(-)

diff --git a/gcc/ada/exp_ch6.adb b/gcc/ada/exp_ch6.adb
index fce10d5e946..b2408140bef 100644
--- a/gcc/ada/exp_ch6.adb
+++ b/gcc/ada/exp_ch6.adb
@@ -1969,21 +1969,12 @@ package body Exp_Ch6 is
 F_Typ := Non_Limited_View (F_Typ);
  end if;
 
- --  Use the actual designated subtype for a dereference, if any
-
- if Nkind (Actual) = N_Explicit_Dereference
-   and then Present (Actual_Designated_Subtype (Actual))
- then
-Indic :=
-  New_Occurrence_Of (Actual_Designated_Subtype (Actual), Loc);
-
  --  Use formal type for temp, unless formal type is an unconstrained
- --  array, in which case we don't have to worry about bounds checks,
- --  and we use the actual type, since that has appropriate bounds.
-
- elsif Is_Array_Type (F_Typ) and then not Is_Constrained (F_Typ) then
-Indic := New_Occurrence_Of (Etype (Actual), Loc);
+ --  composite, in which case we don't have to worry about checks and
+ --  we can use the actual type, since that has appropriate bounds.
 
+ if Is_Composite_Type (F_Typ) and then not Is_Constrained (F_Typ) then
+Indic := New_Occurrence_Of (Get_Actual_Subtype (Actual), Loc);
  else
 Indic := New_Occurrence_Of (F_Typ, Loc);
  end if;
@@ -1999,21 +1990,9 @@ package body Exp_Ch6 is
  --  with the input parameter unless we have an OUT formal or
  --  this is an initialization call.
 
- --  If the formal is an out parameter with discriminants, the
- --  discriminants must be captured even if the rest of the object
- --  is in principle uninitialized, because the discriminants may
- --  be read by the called subprogram.
-
  if Ekind (Formal) = E_Out_Parameter then
 Incod := Empty;
 
-if Has_Discriminants (F_Typ)
-  and then (Nkind (Actual) /= N_Explicit_Dereference
- or else No (Actual_Designated_Subtype (Actual)))
-then
-   Indic := New_Occurrence_Of (Etype (Actual), Loc);
-end if;
-
  elsif Inside_Init_Proc then
 
 --  Skip using the actual as the expression in Decl if we are in
-- 
2.40.0

[COMMITTED] ada: Tune handling of attributes Old in contract Exceptional_Cases

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Contract Exceptional_Cases allows formal parameters to appear *in*
prefixes of attributes Old, but the code only allowed them to appear
*as* prefixes of those attributes.

For example, we now accetp expressions like "X.all'Old" that were
previously rejected.

gcc/ada/

* sem_res.adb (Resolve_Entity_Name): Tune handling of formal parameters
in contract Exceptional_Cases.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_res.adb | 32 ++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 17228689364..9161218a32b 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -7832,6 +7832,9 @@ package body Sem_Res is
   --  Determine whether Expr is part of an N_Attribute_Reference
   --  expression.
 
+  function In_Attribute_Old (Expr : Node_Id) return Boolean;
+  --  Determine whether Expr is in attribute Old
+
   function Within_Exceptional_Cases_Consequence
 (Expr : Node_Id)
  return Boolean;
@@ -7878,6 +7881,31 @@ package body Sem_Res is
  end if;
   end Is_Assignment_Or_Object_Expression;
 
+  --
+  -- In_Attribute_Old --
+  --
+
+  function In_Attribute_Old (Expr : Node_Id) return Boolean is
+ N : Node_Id := Expr;
+  begin
+ while Present (N) loop
+if Nkind (N) = N_Attribute_Reference
+  and then Attribute_Name (N) = Name_Old
+then
+   return True;
+
+--  Prevent the search from going too far
+
+elsif Is_Body_Or_Package_Declaration (N) then
+   return False;
+end if;
+
+N := Parent (N);
+ end loop;
+
+ return False;
+  end In_Attribute_Old;
+
   -
   -- Is_Attribute_Expression --
   -
@@ -8080,12 +8108,12 @@ package body Sem_Res is
 
 --  Parameters of modes OUT or IN OUT of the subprogram shall not
 --  occur in the consequences of an exceptional contract unless
---  they either are of a by-reference type or occur in the prefix
+--  they are either passed by reference or occur in the prefix
 --  of a reference to the 'Old attribute.
 
 if Ekind (E) in E_Out_Parameter | E_In_Out_Parameter
   and then Within_Exceptional_Cases_Consequence (N)
-  and then not Is_Attribute_Old (Parent (N))
+  and then not In_Attribute_Old (N)
   and then not Is_By_Reference_Type (Etype (E))
   and then not Is_Aliased (E)
 then
-- 
2.40.0

[COMMITTED] ada: Remove unused initial value of a local variable

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Cleanup related to improved handling of expression functions in
GNATprove; semantics is unaffected.

gcc/ada/

* sem_ch6.adb (Analyze_Return_Type): Remove unused initial value.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch6.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/sem_ch6.adb b/gcc/ada/sem_ch6.adb
index 135d8ab7f0b..7c90747f293 100644
--- a/gcc/ada/sem_ch6.adb
+++ b/gcc/ada/sem_ch6.adb
@@ -2046,7 +2046,7 @@ package body Sem_Ch6 is
 
procedure Analyze_Return_Type (N : Node_Id) is
   Designator : constant Entity_Id := Defining_Entity (N);
-  Typ: Entity_Id := Empty;
+  Typ: Entity_Id;
 
begin
   --  Normal case where result definition does not indicate an error
-- 
2.40.0

[COMMITTED] ada: Maximize use of existing constant

[Marc Poulhiès via Gcc-patches]

From: Ronan Desplanques 

This patch does not change the behavior of the compiler and is
intended as a readability improvement.

gcc/ada/

* sem_ch3.adb (Replace_Type): Use existing constant wherever
possible.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch3.adb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb
index c8af679b404..0bddfa84463 100644
--- a/gcc/ada/sem_ch3.adb
+++ b/gcc/ada/sem_ch3.adb
@@ -15994,7 +15994,7 @@ package body Sem_Ch3 is
 --  of the parent, and we can also use it rather than its base,
 --  which can lead to more efficient code.
 
-if Etype (Id) = Parent_Type then
+if Id_Type = Parent_Type then
if Is_Scalar_Type (Parent_Type)
  and then
Subtypes_Statically_Compatible (Parent_Type, Derived_Type)
@@ -16019,7 +16019,7 @@ package body Sem_Ch3 is
 end if;
 
  else
-Set_Etype (New_Id, Etype (Id));
+Set_Etype (New_Id, Id_Type);
  end if;
   end Replace_Type;
 
-- 
2.40.0

[COMMITTED] ada: Clean up copying of node trees

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Before calling routine In_Entity_Map we checked if the entity map is
present; inside this routine we checked this again.

Code cleanup; semantics is unaffected.

gcc/ada/

* sem_util.adb (Update_New_Entities): Remove redundant check for entity
map being present.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index bfe1b9fc74d..8b536ec4e42 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -23858,9 +23858,7 @@ package body Sem_Util is
 --  ??? Is there a better way of distinguishing those?
 
 while Present (Old_Id) and then Present (New_Id) loop
-   if not (Present (Entity_Map)
-and then In_Entity_Map (Old_Id, Entity_Map))
-   then
+   if not In_Entity_Map (Old_Id, Entity_Map) then
   Update_Semantic_Fields (New_Id);
end if;
 
-- 
2.40.0

[COMMITTED] ada: Deconstruct a no longer used parameter of New_Copy_Tree

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Parameter Scopes_In_EWA_OK of New_Copy_Tree was introduced in 2018 to
deal with expressions-with-actions (EWA) in the build-in-place
machinery. However, after changes made in 2022 it is no longer used by
any caller.

Cleanup related to handling of expression functions in GNATprove;
semantics is unaffected.

gcc/ada/

* sem_util.ads (New_Copy_Tree): Remove Scopes_In_EWA_OK from spec;
adapt comment.
* sem_util.adb (New_Copy_Tree): Remove Scopes_In_EWA_OK from body;
adapt code.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 16 ++--
 gcc/ada/sem_util.ads | 13 -
 2 files changed, 10 insertions(+), 19 deletions(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 8b536ec4e42..b83c75939c7 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -23067,11 +23067,10 @@ package body Sem_Util is
---
 
function New_Copy_Tree
- (Source   : Node_Id;
-  Map  : Elist_Id   := No_Elist;
-  New_Sloc : Source_Ptr := No_Location;
-  New_Scope: Entity_Id  := Empty;
-  Scopes_In_EWA_OK : Boolean:= False) return Node_Id
+ (Source: Node_Id;
+  Map   : Elist_Id   := No_Elist;
+  New_Sloc  : Source_Ptr := No_Location;
+  New_Scope : Entity_Id  := Empty) return Node_Id
is
   --  This routine performs low-level tree manipulations and needs access
   --  to the internals of the tree.
@@ -24030,12 +24029,9 @@ package body Sem_Util is
 return;
 
  --  Nothing to do when the entity is defined in a scoping construct
- --  within an N_Expression_With_Actions node, unless the caller has
- --  requested their replication.
+ --  within an N_Expression_With_Actions node.
 
- --  ??? should this restriction be eliminated?
-
- elsif EWA_Inner_Scope_Level > 0 and then not Scopes_In_EWA_OK then
+ elsif EWA_Inner_Scope_Level > 0 then
 return;
 
  --  Nothing to do when the entity does not denote a construct that
diff --git a/gcc/ada/sem_util.ads b/gcc/ada/sem_util.ads
index 4962c62fa7d..185cf2ceabd 100644
--- a/gcc/ada/sem_util.ads
+++ b/gcc/ada/sem_util.ads
@@ -2630,11 +2630,10 @@ package Sem_Util is
--  names to facilitate debugging the tree copy.
 
function New_Copy_Tree
- (Source   : Node_Id;
-  Map  : Elist_Id   := No_Elist;
-  New_Sloc : Source_Ptr := No_Location;
-  New_Scope: Entity_Id  := Empty;
-  Scopes_In_EWA_OK : Boolean:= False) return Node_Id;
+ (Source: Node_Id;
+  Map   : Elist_Id   := No_Elist;
+  New_Sloc  : Source_Ptr := No_Location;
+  New_Scope : Entity_Id  := Empty) return Node_Id;
--  Perform a deep copy of the subtree rooted at Source. Entities, itypes,
--  and nodes are handled separately as follows:
--
@@ -2704,10 +2703,6 @@ package Sem_Util is
--
--  Parameter New_Scope may be used to specify a new scope for all copied
--  entities and itypes.
-   --
-   --  Parameter Scopes_In_EWA_OK may be used to force the replication of both
-   --  scoping entities and non-scoping entities found within expression with
-   --  actions nodes.
 
function New_External_Entity
  (Kind : Entity_Kind;
-- 
2.40.0

[COMMITTED] ada: Remove redundant guards from calls to Move_Aspects

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Routine Move_Aspects does nothing if its From parameter has no aspects.
There is no need to check this at the call sites.

Code cleanup related to changes in handling of expressions functions in
GNATprove; semantics is unaffected.

gcc/ada/

* par-ch7.adb (P_Package): Remove redundant guard from call to
Move_Aspects.
* par-ch9.adb (P_Task): Likewise.
* sem_ch6.adb (Analyze_Expression_Function, Is_Inline_Pragma): Likewise.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/par-ch7.adb | 4 +---
 gcc/ada/par-ch9.adb | 4 +---
 gcc/ada/sem_ch6.adb | 8 ++--
 3 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/gcc/ada/par-ch7.adb b/gcc/ada/par-ch7.adb
index e8a765bbac1..fc96ce89f6c 100644
--- a/gcc/ada/par-ch7.adb
+++ b/gcc/ada/par-ch7.adb
@@ -162,9 +162,7 @@ package body Ch7 is
 
 --  Move the aspect specifications to the body node
 
-if Has_Aspects (Dummy_Node) then
-   Move_Aspects (From => Dummy_Node, To => Package_Node);
-end if;
+Move_Aspects (From => Dummy_Node, To => Package_Node);
 
 Parse_Decls_Begin_End (Package_Node);
  end if;
diff --git a/gcc/ada/par-ch9.adb b/gcc/ada/par-ch9.adb
index 752b28bd092..d6526de0b36 100644
--- a/gcc/ada/par-ch9.adb
+++ b/gcc/ada/par-ch9.adb
@@ -140,9 +140,7 @@ package body Ch9 is
 
 --  Move the aspect specifications to the body node
 
-if Has_Aspects (Dummy_Node) then
-   Move_Aspects (From => Dummy_Node, To => Task_Node);
-end if;
+Move_Aspects (From => Dummy_Node, To => Task_Node);
 
 Parse_Decls_Begin_End (Task_Node);
 
diff --git a/gcc/ada/sem_ch6.adb b/gcc/ada/sem_ch6.adb
index 48b363e077c..135d8ab7f0b 100644
--- a/gcc/ada/sem_ch6.adb
+++ b/gcc/ada/sem_ch6.adb
@@ -390,9 +390,7 @@ package body Sem_Ch6 is
  --  function to the proper body when the expression function acts
  --  as a completion.
 
- if Has_Aspects (N) then
-Move_Aspects (N, To => New_Body);
- end if;
+ Move_Aspects (N, To => New_Body);
 
  Relocate_Pragmas_To_Body (New_Body);
 
@@ -2875,9 +2873,7 @@ package body Sem_Ch6 is
 
   --  Move aspects to the new spec
 
-  if Has_Aspects (N) then
- Move_Aspects (N, To => Decl);
-  end if;
+  Move_Aspects (N, To => Decl);
 
   Insert_Before (N, Decl);
   Analyze (Decl);
-- 
2.40.0

[COMMITTED] ada: Decouple size of addresses and pointers from size of memory space

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

This decouples the size of the types representing addresses and pointers,
which is Standard'Address_Size, from the size of the memory space, which
is System.Memory_Size (more precisely log2 of it).  They are tied through
the definition of System.Address:

  type Address is mod Memory_Size;

so Standard'Address_Size >= log2 (System.Memory_Size) necessarily, but the
equality does not hold on platforms where addresses and pointers contain
additional bits of metadata.

gcc/ada/

* libgnat/a-ststio.adb (Set_Mode): Test System.Memory_Size.
* libgnat/g-debuti.ads (Address_64): Likewise.
* libgnat/i-c.ads: Add with clause for System.
(ptrdiff_t): Define based on the size of memory space.
(size_t): Likewise.
* libgnat/s-crtl.ads (size_t): Likewise.
(ssize_t): Likewise.
* libgnat/s-memory.ads (size_t): Likewise.
* libgnat/s-parame.ads (Size_Type): Likewise.
* libgnat/s-parame__hpux.ads (Size_Type): Likewise.
* libgnat/s-parame__posix2008.ads (Size_Type): Likewise.
* libgnat/s-parame__vxworks.ads (Size_Type): Likewise.
* libgnat/s-putima.adb (Signed_Address): Likewise.
(Unsigned_Address): Likewise.
* libgnat/s-stoele.ads (Storage_Offset): Likewise.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/libgnat/a-ststio.adb| 4 +++-
 gcc/ada/libgnat/g-debuti.ads| 4 ++--
 gcc/ada/libgnat/i-c.ads | 6 +++---
 gcc/ada/libgnat/s-crtl.ads  | 5 ++---
 gcc/ada/libgnat/s-memory.ads| 2 +-
 gcc/ada/libgnat/s-parame.ads| 4 +---
 gcc/ada/libgnat/s-parame__hpux.ads  | 4 +---
 gcc/ada/libgnat/s-parame__posix2008.ads | 4 +---
 gcc/ada/libgnat/s-parame__vxworks.ads   | 4 +---
 gcc/ada/libgnat/s-putima.adb| 5 ++---
 gcc/ada/libgnat/s-stoele.ads| 7 +--
 11 files changed, 18 insertions(+), 31 deletions(-)

diff --git a/gcc/ada/libgnat/a-ststio.adb b/gcc/ada/libgnat/a-ststio.adb
index 2cb9d974bbd..ab46f483b0e 100644
--- a/gcc/ada/libgnat/a-ststio.adb
+++ b/gcc/ada/libgnat/a-ststio.adb
@@ -367,11 +367,13 @@ package body Ada.Streams.Stream_IO is
   FIO.Append_Set (AP (File));
 
   if File.Mode = FCB.Append_File then
- if Standard'Address_Size = 64 then
+ pragma Warnings (Off, "condition is always *");
+ if Memory_Size = 2**64 then
 File.Index := Count (ftell64 (File.Stream)) + 1;
  else
 File.Index := Count (ftell (File.Stream)) + 1;
  end if;
+ pragma Warnings (On);
   end if;
 
   File.Last_Op := Op_Other;
diff --git a/gcc/ada/libgnat/g-debuti.ads b/gcc/ada/libgnat/g-debuti.ads
index b989cd4bdfb..51a1b7708e6 100644
--- a/gcc/ada/libgnat/g-debuti.ads
+++ b/gcc/ada/libgnat/g-debuti.ads
@@ -39,8 +39,8 @@ with System;
 package GNAT.Debug_Utilities is
pragma Pure;
 
-   Address_64 : constant Boolean := Standard'Address_Size = 64;
-   --  Set true if 64 bit addresses (assumes only 32 and 64 are possible)
+   Address_64 : constant Boolean := System.Memory_Size = 2**64;
+   --  Set true if 64-bit addresses (assumes only 32 and 64 are possible)
 
Address_Image_Length : constant := 13 + 10 * Boolean'Pos (Address_64);
--  Length of string returned by Image function for an address
diff --git a/gcc/ada/libgnat/i-c.ads b/gcc/ada/libgnat/i-c.ads
index 70139023dc3..70af56a7836 100644
--- a/gcc/ada/libgnat/i-c.ads
+++ b/gcc/ada/libgnat/i-c.ads
@@ -24,6 +24,7 @@ pragma Assertion_Policy (Pre=> Ignore,
  Contract_Cases => Ignore,
  Ghost  => Ignore);
 
+with System;
 with System.Parameters;
 
 package Interfaces.C
@@ -82,10 +83,9 @@ is
--  a non-private system.address type.
 
type ptrdiff_t is
- range -(2 ** (System.Parameters.ptr_bits - Integer'(1))) ..
-   +(2 ** (System.Parameters.ptr_bits - Integer'(1)) - 1);
+ range -System.Memory_Size / 2 .. System.Memory_Size / 2 - 1;
 
-   type size_t is mod 2 ** System.Parameters.ptr_bits;
+   type size_t is mod System.Memory_Size;
 
--  Boolean type
 
diff --git a/gcc/ada/libgnat/s-crtl.ads b/gcc/ada/libgnat/s-crtl.ads
index 4b6fc769afa..c3a3b6481db 100644
--- a/gcc/ada/libgnat/s-crtl.ads
+++ b/gcc/ada/libgnat/s-crtl.ads
@@ -55,10 +55,9 @@ package System.CRTL is
 
subtype off_t is Long_Integer;
 
-   type size_t is mod 2 ** Standard'Address_Size;
+   type size_t is mod System.Memory_Size;
 
-   type ssize_t is range -(2 ** (Standard'Address_Size - 1))
-  .. +(2 ** (Standard'Address_Size - 1)) - 1;
+   type ssize_t is range -Memory_Size / 2 .. Memory_Size / 2 - 1;
 
type int64 is new Long_Long_Integer;
--  Note: we use Long_Long_Integer'First instead of -2 ** 63 to allow this
diff --git a/gcc/ada/libgnat/s-memory.ads b/gcc/ada/libgnat/s-memory.ads
index dc431b766f8..4f6dd3d2856 100644
--- a/gcc/ada/libgnat/s-memory.ads
+++ b/gcc/ada/lib

[COMMITTED] ada: Add size clause to System.Address

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

Standard'Address_Size is the value provided by the code generator for the
size of pointers, and it is set as the default size of every thin pointer
by the front-end.  Now it is documented in the GNAT RM as having the value
of System.Address'Size, which is indeed the case on (correctly configured)
platforms where pointers contain exactly the number of bits that are needed
to address the memory space.

However, on platforms where pointers contain additional bits of metadata,
it has a larger value and the documented relation does not hold, which also
means that unchecked conversions between System.Address and pointers are
seen as potentially problematic.  In order to fix the discrepancy on these
platforms, this change adds the obvious size clause to System.Address, which
is confirming on all the other (correctly configured) platforms.

gcc/ada/

* libgnat/system-aix.ads (Address): Likewise.
* libgnat/system-darwin-arm.ads (Address): Likewise.
* libgnat/system-darwin-ppc.ads (Address): Likewise.
* libgnat/system-darwin-x86.ads (Address): Likewise.
* libgnat/system-djgpp.ads (Address): Likewise.
* libgnat/system-dragonfly-x86_64.ads (Address): Likewise.
* libgnat/system-freebsd.ads (Address): Likewise.
* libgnat/system-hpux-ia64.ads (Address): Likewise.
* libgnat/system-hpux.ads (Address): Likewise.
* libgnat/system-linux-alpha.ads (Address): Likewise.
* libgnat/system-linux-arm.ads (Address): Likewise.
* libgnat/system-linux-hppa.ads (Address): Likewise.
* libgnat/system-linux-ia64.ads (Address): Likewise.
* libgnat/system-linux-m68k.ads (Address): Likewise.
* libgnat/system-linux-mips.ads (Address): Likewise.
* libgnat/system-linux-ppc.ads (Address): Likewise.
* libgnat/system-linux-riscv.ads (Address): Likewise.
* libgnat/system-linux-s390.ads (Address): Likewise.
* libgnat/system-linux-sh4.ads (Address): Likewise.
* libgnat/system-linux-sparc.ads (Address): Likewise.
* libgnat/system-linux-x86.ads (Address): Likewise.
* libgnat/system-lynxos178-ppc.ads (Address): Likewise.
* libgnat/system-lynxos178-x86.ads (Address): Likewise.
* libgnat/system-mingw.ads (Address): Likewise.
* libgnat/system-qnx-arm.ads (Address): Likewise.
* libgnat/system-rtems.ads (Address): Likewise.
* libgnat/system-solaris-sparc.ads (Address): Likewise.
* libgnat/system-solaris-x86.ads (Address): Likewise.
* libgnat/system-vxworks-ppc-kernel.ads (Address): Likewise.
* libgnat/system-vxworks-ppc-rtp-smp.ads (Address): Likewise.
* libgnat/system-vxworks-ppc-rtp.ads (Address): Likewise.
* libgnat/system-vxworks7-aarch64-rtp-smp.ads (Address): Likewise.
* libgnat/system-vxworks7-aarch64.ads (Address): Likewise.
* libgnat/system-vxworks7-arm-rtp-smp.ads (Address): Likewise.
* libgnat/system-vxworks7-arm.ads (Address): Likewise.
* libgnat/system-vxworks7-ppc-kernel.ads (Address): Likewise.
* libgnat/system-vxworks7-ppc-rtp-smp.ads (Address): Likewise.
* libgnat/system-vxworks7-ppc64-kernel.ads (Address): Likewise.
* libgnat/system-vxworks7-ppc64-rtp-smp.ads (Address): Likewise.
* libgnat/system-vxworks7-x86-kernel.ads (Address): Likewise.
* libgnat/system-vxworks7-x86-rtp-smp.ads (Address): Likewise.
* libgnat/system-vxworks7-x86_64-kernel.ads (Address): Likewise.
* libgnat/system-vxworks7-x86_64-rtp-smp.ads (Address): Likewise.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/libgnat/system-aix.ads  | 2 ++
 gcc/ada/libgnat/system-darwin-arm.ads   | 2 ++
 gcc/ada/libgnat/system-darwin-ppc.ads   | 2 ++
 gcc/ada/libgnat/system-darwin-x86.ads   | 2 ++
 gcc/ada/libgnat/system-djgpp.ads| 2 ++
 gcc/ada/libgnat/system-dragonfly-x86_64.ads | 2 ++
 gcc/ada/libgnat/system-freebsd.ads  | 2 ++
 gcc/ada/libgnat/system-hpux-ia64.ads| 2 ++
 gcc/ada/libgnat/system-hpux.ads | 2 ++
 gcc/ada/libgnat/system-linux-alpha.ads  | 2 ++
 gcc/ada/libgnat/system-linux-arm.ads| 2 ++
 gcc/ada/libgnat/system-linux-hppa.ads   | 2 ++
 gcc/ada/libgnat/system-linux-ia64.ads   | 2 ++
 gcc/ada/libgnat/system-linux-m68k.ads   | 2 ++
 gcc/ada/libgnat/system-linux-mips.ads   | 2 ++
 gcc/ada/libgnat/system-linux-ppc.ads| 2 ++
 gcc/ada/libgnat/system-linux-riscv.ads  | 2 ++
 gcc/ada/libgnat/system-linux-s390.ads   | 2 ++
 gcc/ada/libgnat/system-linux-sh4.ads| 2 ++
 gcc/ada/libgnat/system-linux-sparc.ads  | 2 ++
 gcc/ada/libgnat/system-linux-x86.ads| 2 ++
 gcc/ada/libgnat/system-lynxos178-ppc.ads| 2 ++
 

[COMMITTED] ada: Fix copy-paste mistake in analysis of Exceptional_Cases

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Trivial mistakes in copied code.

gcc/ada/

* sem_prag.adb (Analyze_Pragma): Fix references to Exceptional_Cases in
code copied from handling of Subprogram_Variant.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_prag.adb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb
index 963c6dea238..40636f21fc7 100644
--- a/gcc/ada/sem_prag.adb
+++ b/gcc/ada/sem_prag.adb
@@ -16688,7 +16688,7 @@ package body Sem_Prag is
 Ensure_Aggregate_Form (Get_Argument (N, Spec_Id));
 
 --  Chain the pragma on the contract for further processing by
---  Analyze_Subprogram_Variant_In_Decl_Part.
+--  Analyze_Exceptional_Cases_In_Decl_Part.
 
 Add_Contract_Item (N, Defining_Entity (Subp_Decl));
 
@@ -16698,13 +16698,13 @@ package body Sem_Prag is
 if Nkind (Subp_Decl) in N_Subprogram_Body
   | N_Subprogram_Body_Stub
 then
-   --  The legality checks of pragma Subprogram_Variant are
+   --  The legality checks of pragma Exceptional_Cases are
--  affected by the SPARK mode in effect and the volatility
--  of the context. Analyze all pragmas in a specific order.
 
Analyze_If_Present (Pragma_SPARK_Mode);
Analyze_If_Present (Pragma_Volatile_Function);
-   Analyze_Subprogram_Variant_In_Decl_Part (N);
+   Analyze_Exceptional_Cases_In_Decl_Part (N);
 end if;
  end Exceptional_Cases;
 
-- 
2.40.0

[COMMITTED] ada: Switch from E_Void to Is_Not_Self_Hidden

[Marc Poulhiès via Gcc-patches]

From: Bob Duff 

We had previously used Ekind = E_Void to indicate that a declaration is
self-hidden. We now use the Is_Not_Self_Hidden flag instead. This allows
us to avoid many "vanishing fields", which are (possibly-latent) bugs,
and we now enable the assertions in Atree that detect such bugs.

gcc/ada/

* atree.adb (Check_Vanishing_Fields): Fix bug in the "blah type
only" cases. Remove the special cases for E_Void. Misc cleanup.
(Mutate_Nkind): Disallow mutating to the same kind.
(Mutate_Ekind): Disallow mutating to E_Void.
(From E_Void is still OK -- entities start out as E_Void by
default.) Fix bug in statistics gathering -- was setting the wrong
count. Enable Check_Vanishing_Fields for entities.
* sem_ch8.adb (Is_Self_Hidden): New function.
(Find_Direct_Name): Call Is_Self_Hidden to use the new
Is_Not_Self_Hidden flag to determine whether a declaration is
hidden from all visibility by itself. This replaces the old method
of checking E_Void.
(Find_Expanded_Name): Likewise.
(Find_Selected_Component): Likewise.
* sem_util.adb (Enter_Name): Remove setting of Ekind to E_Void.
* sem_ch3.adb: Set the Is_Not_Self_Hidden flag in appropriate
places. Comment fixes.
(Inherit_Component): Remove setting of Ekind to E_Void.
* sem_ch9.adb
(Analyze_Protected_Type_Declaration): Update comment. Skip Itypes,
which should not be turned into components.
* atree.ads (Mutate_Nkind): Document error case.
(Mutate_Ekind): Remove comments apologizing for E_Void mutations.
Document error cases.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/atree.adb| 36 +++
 gcc/ada/atree.ads| 15 +++--
 gcc/ada/sem_ch3.adb  | 50 +---
 gcc/ada/sem_ch8.adb  | 34 ++
 gcc/ada/sem_ch9.adb  | 10 +
 gcc/ada/sem_util.adb |  6 +-
 6 files changed, 71 insertions(+), 80 deletions(-)

diff --git a/gcc/ada/atree.adb b/gcc/ada/atree.adb
index ef19a80b6e7..f1e4e2ca8bb 100644
--- a/gcc/ada/atree.adb
+++ b/gcc/ada/atree.adb
@@ -25,10 +25,10 @@
 
 with Ada.Unchecked_Conversion;
 with Aspects;use Aspects;
-with Debug;  use Debug;
 with Namet;  use Namet;
 with Nlists; use Nlists;
 with Opt;use Opt;
+with Osint;
 with Output; use Output;
 with Sinfo.Utils;use Sinfo.Utils;
 with System.Storage_Elements;
@@ -975,8 +975,6 @@ package body Atree is
   end loop;
end Check_Vanishing_Fields;
 
-   Check_Vanishing_Fields_Failed : Boolean := False;
-
procedure Check_Vanishing_Fields
  (Old_N : Entity_Id; New_Kind : Entity_Kind)
is
@@ -1012,16 +1010,9 @@ package body Atree is
  when others => return False; -- ignore the exception
   end Same_Node_To_Fetch_From;
 
-   begin
-  --  Disable these checks in the case of converting to or from E_Void,
-  --  because we have many cases where we convert something to E_Void and
-  --  then back (or then to something else), and Reinit_Field_To_Zero
-  --  wouldn't work because we expect the fields to retain their values.
-
-  if New_Kind = E_Void or else Old_Kind = E_Void then
- return;
-  end if;
+   --  Start of processing for Check_Vanishing_Fields
 
+   begin
   for J in Entity_Field_Table (Old_Kind)'Range loop
  declare
 F : constant Entity_Field := Entity_Field_Table (Old_Kind) (J);
@@ -1030,8 +1021,9 @@ package body Atree is
null; -- no check in this case
 elsif not Field_Checking.Field_Present (New_Kind, F) then
if not Field_Is_Initial_Zero (Old_N, F) then
-  Check_Vanishing_Fields_Failed := True;
   Write_Str ("# ");
+  Write_Str (Osint.Get_First_Main_File_Name);
+  Write_Str (": ");
   Write_Str (Old_Kind'Img);
   Write_Str (" --> ");
   Write_Str (New_Kind'Img);
@@ -1048,14 +1040,11 @@ package body Atree is
   Write_Str ("...mutating node ");
   Write_Int (Nat (Old_N));
   Write_Line ("");
+  raise Program_Error;
end if;
 end if;
  end;
   end loop;
-
-  if Check_Vanishing_Fields_Failed then
- raise Program_Error;
-  end if;
end Check_Vanishing_Fields;
 
Nkind_Offset : constant Field_Offset := Field_Descriptors (F_Nkind).Offset;
@@ -1080,6 +1069,8 @@ package body Atree is
   All_Node_Offsets : Node_Offsets.Table_Type renames
 Node_Offsets.Table (Node_Offsets.First .. Node_Offsets.Last);
begin
+  pragma Assert (Nkind (N) /= Val);
+
   pragma Debug (Check_Vanishing_Fields (N, Val));
 
   --  Grow the slots if necessary
@@ -1131,23 +1122,20 @@ pa

[COMMITTED] ada: Crash on empty aggregate using the Ada 2022 notation

[Marc Poulhiès via Gcc-patches]

From: Javier Miranda 

The compiler crashes processing an empty aggregate initializing
a component of a discriminated record type using the Ada 2022
notation (that is, []).

gcc/ada/

* exp_aggr.adb (Build_Record_Aggr_Code): Protect access to
aggregate components when the aggregate is empty.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_aggr.adb | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb
index f3ad8a9e1ae..de4d5a785fc 100644
--- a/gcc/ada/exp_aggr.adb
+++ b/gcc/ada/exp_aggr.adb
@@ -4061,7 +4061,9 @@ package body Exp_Aggr is
 Decl  : Node_Id;
 
  begin
-if Nkind (First (Choices (Assoc))) = N_Others_Choice
+if Present (Assoc)
+  and then
+Nkind (First (Choices (Assoc))) = N_Others_Choice
 then
Decl :=
  Build_Actual_Subtype_Of_Component
-- 
2.40.0

[COMMITTED] ada: Fix (again) incorrect handling of Aggregate aspect

[Marc Poulhiès via Gcc-patches]

Previous fix stopped the processing of the Aggregate aspect early,
skipping the call to Record_Rep_Item, making later call to
Resolve_Container_Aggregate fail.

Also, the previous fix would not handle correctly the case where the
type is private and the check for non-array type can only be done at the
freeze point with the full type.

Adapt the resolving of the aspect when the input is not correct and the
parameters can't be resolved.

gcc/ada/

* sem_ch13.adb (Analyze_One_Aspect): Call Record_Rep_Item.
(Check_Aspect_At_Freeze_Point): Check the aspect is specified on
non-array type only...
(Analyze_One_Aspect): ... instead of doing it too early here.
* sem_aggr.adb (Resolve_Container_Aggregate): Do nothing in case
the parameters failed to resolve.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_aggr.adb |  9 +++--
 gcc/ada/sem_ch13.adb | 12 +++-
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/gcc/ada/sem_aggr.adb b/gcc/ada/sem_aggr.adb
index f1511b70648..33c44c42a24 100644
--- a/gcc/ada/sem_aggr.adb
+++ b/gcc/ada/sem_aggr.adb
@@ -3160,6 +3160,7 @@ package body Sem_Aggr is
 
   if Present (Add_Unnamed_Subp)
 and then No (New_Indexed_Subp)
+and then Etype (Add_Unnamed_Subp) /= Any_Type
   then
  declare
 Elmt_Type : constant Entity_Id :=
@@ -3203,7 +3204,9 @@ package body Sem_Aggr is
 end if;
  end;
 
-  elsif Present (Add_Named_Subp) then
+  elsif Present (Add_Named_Subp)
+and then Etype (Add_Named_Subp) /= Any_Type
+  then
  declare
 --  Retrieves types of container, key, and element from the
 --  specified insertion procedure.
@@ -3245,7 +3248,9 @@ package body Sem_Aggr is
 end loop;
  end;
 
-  elsif Present (Assign_Indexed_Subp) then
+  elsif Present (Assign_Indexed_Subp)
+and then Etype (Assign_Indexed_Subp) /= Any_Type
+  then
  --  Indexed Aggregate. Positional or indexed component
  --  can be present, but not both. Choices must be static
  --  values or ranges with static bounds.
diff --git a/gcc/ada/sem_ch13.adb b/gcc/ada/sem_ch13.adb
index a3819725181..6f9fe738ddd 100644
--- a/gcc/ada/sem_ch13.adb
+++ b/gcc/ada/sem_ch13.adb
@@ -4203,11 +4203,8 @@ package body Sem_Ch13 is
   Aitem := Empty;
 
when Aspect_Aggregate =>
-  if Is_Array_Type (E) then
- Error_Msg_N
-   ("aspect% can only be applied to non-array type", Id);
- goto Continue;
-  end if;
+  --  We will be checking that the aspect is not specified on a
+  --  non-array type in Check_Aspect_At_Freeze_Point
 
   Validate_Aspect_Aggregate (Expr);
   Record_Rep_Item (E, Aspect);
@@ -11225,6 +11222,11 @@ package body Sem_Ch13 is
 return;
 
  when Aspect_Aggregate =>
+if Is_Array_Type (Entity (ASN)) then
+   Error_Msg_N
+ ("aspect% can only be applied to non-array type",
+  Identifier (ASN));
+end if;
 Resolve_Aspect_Aggregate (Entity (ASN), Expression (ASN));
 return;
 
-- 
2.40.0

[COMMITTED] ada: Avoid duplicated streaming subprograms

[Marc Poulhiès via Gcc-patches]

From: Steve Baird 

In some common cases, a reference to Some_Type'Some_Streaming_Attribute
causes the needed subprogram to be generated "on demand". If there are
multiple such references (e.g., two calls to Some_Type'Write) then we
want to avoid generating multiple essentially-identical subprograms.
This change implies that a generated streaming subprogram may now have
multiple call sites, so we can no longer use the source position information
from the (one and only) call site. If an exception is raised during a
streaming operation, this can make a difference in the reported raise location.

gcc/ada/

* exp_attr.adb
(Cached_Streaming_Ops): A new package, providing maps to save
previously-generated Read/Write/Input/Output procedures.
(Expand_N_Attribute_Reference): When a new subprogram is generated
for a Read/Write/Input/Output attribute reference, record that
type/subp pair in the appropriate Cached_Streaming_Ops map.
(Find_Stream_Subprogram): Check the appropriate
Cached_Streaming_Ops map to see if an appropriate subprogram has
already been generated. If so, then return it. The appropriateness
test includes a call to a new nested subprogram,
In_Available_Context.
* exp_strm.ads, exp_strm.adb: Do not pass in a Loc parameter (or a
source-location-bearing Nod parameter) to the 16 procedures
provided for building streaming-related subprograms. Use the
source location of the type instead.
* exp_dist.adb, exp_ch3.adb: Adapt to Exp_Strm spec changes. For
these calls the source location of the type was already being
used.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_attr.adb | 279 +--
 gcc/ada/exp_ch3.adb  |   8 +-
 gcc/ada/exp_dist.adb |  10 +-
 gcc/ada/exp_strm.adb | 100 
 gcc/ada/exp_strm.ads |  39 ++
 5 files changed, 286 insertions(+), 150 deletions(-)

diff --git a/gcc/ada/exp_attr.adb b/gcc/ada/exp_attr.adb
index a5791adf7dd..7235a164e0a 100644
--- a/gcc/ada/exp_attr.adb
+++ b/gcc/ada/exp_attr.adb
@@ -77,8 +77,55 @@ with Uname;  use Uname;
 with Urealp; use Urealp;
 with Validsw;use Validsw;
 
+with GNAT.HTable;
+
 package body Exp_Attr is
 
+   package Cached_Streaming_Ops is
+
+  Map_Size : constant := 63;
+  subtype Header_Num is Integer range 0 .. Map_Size - 1;
+
+  function Streaming_Op_Hash (Id : Entity_Id) return Header_Num is
+(Header_Num (Id mod Map_Size));
+
+  --  Cache used to avoid building duplicate subprograms for a single
+  --  type/streaming-attribute pair.
+
+  package Read_Map is new GNAT.HTable.Simple_HTable
+(Header_Num => Header_Num,
+ Key=> Entity_Id,
+ Element=> Entity_Id,
+ No_Element => Empty,
+ Hash   => Streaming_Op_Hash,
+ Equal  => "=");
+
+  package Write_Map is new GNAT.HTable.Simple_HTable
+(Header_Num => Header_Num,
+ Key=> Entity_Id,
+ Element=> Entity_Id,
+ No_Element => Empty,
+ Hash   => Streaming_Op_Hash,
+ Equal  => "=");
+
+  package Input_Map is new GNAT.HTable.Simple_HTable
+(Header_Num => Header_Num,
+ Key=> Entity_Id,
+ Element=> Entity_Id,
+ No_Element => Empty,
+ Hash   => Streaming_Op_Hash,
+ Equal  => "=");
+
+  package Output_Map is new GNAT.HTable.Simple_HTable
+(Header_Num => Header_Num,
+ Key=> Entity_Id,
+ Element=> Entity_Id,
+ No_Element => Empty,
+ Hash   => Streaming_Op_Hash,
+ Equal  => "=");
+
+   end Cached_Streaming_Ops;
+
---
-- Local Subprograms --
---
@@ -210,13 +257,15 @@ package body Exp_Attr is
--  is not a floating-point type.
 
function Find_Stream_Subprogram
- (Typ : Entity_Id;
-  Nam : TSS_Name_Type) return Entity_Id;
+ (Typ  : Entity_Id;
+  Nam  : TSS_Name_Type;
+  Attr_Ref : Node_Id) return Entity_Id;
--  Returns the stream-oriented subprogram attribute for Typ. For tagged
--  types, the corresponding primitive operation is looked up, else the
--  appropriate TSS from the type itself, or from its closest ancestor
--  defining it, is returned. In both cases, inheritance of representation
-   --  aspects is thus taken into account.
+   --  aspects is thus taken into account. Attr_Ref is used to identify the
+   --  point from which the function result will be referenced.
 
function Full_Base (T : Entity_Id) return Entity_Id;
--  The stream functions need to examine the underlying representation of
@@ -4115,18 +4164,19 @@ package body Exp_Attr is
   ---
 
   when Attribute_Input => Input : declare
- P_Type : constant Entity_Id := Entity (Pr

[COMMITTED] ada: Use procedural variant of Next_Index where possible

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Code cleanup; semantics is unaffected.

gcc/ada/

* einfo-utils.adb (Write_Entity_Info): Use procedural Next_Index.
* sem_aggr.adb (Collect_Aggr_Bounds): Reuse local constant.
(Resolve_Null_Array_Aggregate): Use procedural Next_Index.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/einfo-utils.adb | 2 +-
 gcc/ada/sem_aggr.adb| 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/ada/einfo-utils.adb b/gcc/ada/einfo-utils.adb
index fa28a9e0100..d1db66ff697 100644
--- a/gcc/ada/einfo-utils.adb
+++ b/gcc/ada/einfo-utils.adb
@@ -3171,7 +3171,7 @@ package body Einfo.Utils is
Index := First_Index (Id);
while Present (Index) loop
   Write_Attribute (" ", Etype (Index));
-  Index := Next_Index (Index);
+  Next_Index (Index);
end loop;
 
Write_Eol;
diff --git a/gcc/ada/sem_aggr.adb b/gcc/ada/sem_aggr.adb
index 33c44c42a24..d9520ca8f4b 100644
--- a/gcc/ada/sem_aggr.adb
+++ b/gcc/ada/sem_aggr.adb
@@ -464,8 +464,8 @@ package body Sem_Aggr is
  This_Range : constant Node_Id := Aggregate_Bounds (N);
  --  The aggregate range node of this specific sub-aggregate
 
- This_Low  : constant Node_Id := Low_Bound  (Aggregate_Bounds (N));
- This_High : constant Node_Id := High_Bound (Aggregate_Bounds (N));
+ This_Low  : constant Node_Id := Low_Bound  (This_Range);
+ This_High : constant Node_Id := High_Bound (This_Range);
  --  The aggregate bounds of this specific sub-aggregate
 
  Assoc : Node_Id;
@@ -4175,7 +4175,7 @@ package body Sem_Aggr is
  Append (Make_Range (Loc, New_Copy_Tree (Lo), Hi), Constr);
  Analyze_And_Resolve (Last (Constr), Etype (Index));
 
- Index := Next_Index (Index);
+ Next_Index (Index);
   end loop;
 
   Set_Compile_Time_Known_Aggregate (N);
-- 
2.40.0

[COMMITTED] ada: Simplify copying of node lists

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

When creating a copy of a node list we called Copy_Entity for entities
and Copy_Separate_Tree for other nodes. This was unnecessary, because
the Copy_Separate_Tree when called on entities will just do Copy_Entity.

Code cleanup; semantics is unaffected.

gcc/ada/

* atree.adb (Copy_List): Call Copy_Separate_Tree for both entities and
other nodes.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/atree.adb | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/gcc/ada/atree.adb b/gcc/ada/atree.adb
index 1c5b93727cd..ef19a80b6e7 100644
--- a/gcc/ada/atree.adb
+++ b/gcc/ada/atree.adb
@@ -1396,12 +1396,7 @@ package body Atree is
 
 E := First (List);
 while Present (E) loop
-   if Is_Entity (E) then
-  Append (Copy_Entity (E), NL);
-   else
-  Append (Copy_Separate_Tree (E), NL);
-   end if;
-
+   Append (Copy_Separate_Tree (E), NL);
Next (E);
 end loop;
 
-- 
2.40.0

[COMMITTED] ada: Expect Exceptional_Cases as a context for attribute Old

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

When determining whether attribute Old is evaluated conditionally, we
must also expect it to appear in the recently added contract
Exceptional_Cases.

gcc/ada/

* sem_util.adb (Determining_Expressions): Fix style; fix layout and
ordering of pragma names; expect pragma Exceptional_Cases.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 6b5abc92c96..aabd01747fc 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -30651,9 +30651,9 @@ package body Sem_Util is
(Expr : Node_Id; Expr_Trailer : Node_Id := Empty)
return Determining_Expression_List
  is
-Par   : Node_Id := Expr;
-Trailer   : Node_Id := Expr_Trailer;
-Next_Element  : Determining_Expr;
+Par  : Node_Id := Expr;
+Trailer  : Node_Id := Expr_Trailer;
+Next_Element : Determining_Expr;
  begin
 --  We want to stop climbing up the tree when we reach the
 --  postcondition expression. An aspect_specification is
@@ -30761,9 +30761,13 @@ package body Sem_Util is
 else
pragma Assert
  (Get_Pragma_Id (Pragma_Name (Par)) in
-Pragma_Post | Pragma_Postcondition
-| Pragma_Post_Class | Pragma_Refined_Post
-| Pragma_Check | Pragma_Contract_Cases);
+Pragma_Check
+  | Pragma_Contract_Cases
+  | Pragma_Exceptional_Cases
+  | Pragma_Post
+  | Pragma_Postcondition
+  | Pragma_Post_Class
+  | Pragma_Refined_Post);
 
return (1 .. 0 => <>); -- recursion terminates here
 end if;
-- 
2.40.0

[COMMITTED] ada: Fix copying of quantified expressions

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

While visiting the AST as part of routine New_Copy_Tree we maintain
an EWA_Level variable in a stack-like fashion. This worked fine for
expression with actions nodes but not for quantified expressions.

gcc/ada/

* sem_util.adb (Visit_Node): Decrement EWA_Level with the same condition
as when it was incremented.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index b83c75939c7..c9aa76707a5 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -24383,7 +24383,10 @@ package body Sem_Util is
  then
 EWA_Inner_Scope_Level := EWA_Inner_Scope_Level - 1;
 
- elsif Nkind (N) = N_Expression_With_Actions then
+ elsif Nkind (N) = N_Expression_With_Actions
+   or else
+ (Nkind (N) = N_Quantified_Expression and then Expander_Active)
+ then
 EWA_Level := EWA_Level - 1;
  end if;
   end Visit_Node;
-- 
2.40.0

[COMMITTED] ada: Missing warning on null-excluding array aggregate component

[Marc Poulhiès via Gcc-patches]

From: Javier Miranda 

The compiler does not report warnings on the initialization
of arrays of null-excluding access type components by means
of iterated component association, when the expression
initializing each component is either a conditional
expression or a case expression that may initialize
some component with a null value.

gcc/ada/

* sem_aggr.adb
(Warn_On_Null_Component_Association): New subprogram.
(Empty_Range): Adding missing support for iterated component
association node.
(Resolve_Array_Aggregate): Report warning on iterated component
association that may initialize some component of an array of
null-excluding access type components with a null value.
* exp_ch4.adb
(Expand_N_Expression_With_Actions): Add missing type check since
the subtype of the EWA node and the subtype of the expression
may differ.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch4.adb  |   5 ++
 gcc/ada/sem_aggr.adb | 163 ++-
 2 files changed, 165 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/exp_ch4.adb b/gcc/ada/exp_ch4.adb
index c7727904df2..48692c06f01 100644
--- a/gcc/ada/exp_ch4.adb
+++ b/gcc/ada/exp_ch4.adb
@@ -5728,6 +5728,11 @@ package body Exp_Ch4 is
   --  the usual forced evaluation to encapsulate potential aliasing.
 
   else
+ --  A check is also needed since the subtype of the EWA node and the
+ --  subtype of the expression may differ (for example, the EWA node
+ --  may have a null-excluding access subtype).
+
+ Apply_Constraint_Check (Expression (N), Etype (N));
  Force_Evaluation (Expression (N));
   end if;
 
diff --git a/gcc/ada/sem_aggr.adb b/gcc/ada/sem_aggr.adb
index d9520ca8f4b..e7643277460 100644
--- a/gcc/ada/sem_aggr.adb
+++ b/gcc/ada/sem_aggr.adb
@@ -1340,6 +1340,12 @@ package body Sem_Aggr is
  Index_Typ : Entity_Id);
   --  For AI12-061
 
+  procedure Warn_On_Null_Component_Association (Expr : Node_Id);
+  --  Expr is either a conditional expression or a case expression of an
+  --  iterated component association initializing the aggregate N with
+  --  components that can never be null. Report warning on associations
+  --  that may initialize some component with a null value.
+
   -
   -- Add --
   -
@@ -1877,6 +1883,132 @@ package body Sem_Aggr is
  End_Scope;
   end Resolve_Iterated_Component_Association;
 
+  
+  -- Warn_On_Null_Component_Association --
+  
+
+  procedure Warn_On_Null_Component_Association (Expr : Node_Id) is
+ Comp_Typ : constant Entity_Id := Component_Type (Etype (N));
+
+ procedure Check_Case_Expr (N : Node_Id);
+ --  Check if a case expression may initialize some component with a
+ --  null value.
+
+ procedure Check_Cond_Expr (N : Node_Id);
+ --  Check if a conditional expression may initialize some component
+ --  with a null value.
+
+ procedure Check_Expr (Expr : Node_Id);
+ --  Check if an expression may initialize some component with a
+ --  null value.
+
+ procedure Warn_On_Null_Expression_And_Rewrite (Null_Expr : Node_Id);
+ --  Report warning on known null expression and replace the expression
+ --  by a raise constraint error node.
+
+ -
+ -- Check_Case_Expr --
+ -
+
+ procedure Check_Case_Expr (N : Node_Id) is
+Alt_Node : Node_Id := First (Alternatives (N));
+
+ begin
+while Present (Alt_Node) loop
+   Check_Expr (Expression (Alt_Node));
+   Next (Alt_Node);
+end loop;
+ end Check_Case_Expr;
+
+ -
+ -- Check_Cond_Expr --
+ -
+
+ procedure Check_Cond_Expr (N : Node_Id) is
+If_Expr   : Node_Id := N;
+Then_Expr : Node_Id;
+Else_Expr : Node_Id;
+
+ begin
+Then_Expr := Next (First (Expressions (If_Expr)));
+Else_Expr := Next (Then_Expr);
+
+Check_Expr (Then_Expr);
+
+--  Process elsif parts (if any)
+
+while Nkind (Else_Expr) = N_If_Expression loop
+   If_Expr   := Else_Expr;
+   Then_Expr := Next (First (Expressions (If_Expr)));
+   Else_Expr := Next (Then_Expr);
+
+   Check_Expr (Then_Expr);
+end loop;
+
+if Known_Null (Else_Expr) then
+   Warn_On_Null_Expression_And_Rewrite (Else_Expr);
+end if;
+ end Check_Cond_Expr;
+
+ 
+ -- Check_Expr --
+ 
+
+ procedure Check_Expr (Expr : Node_Id) is
+

[COMMITTED] ada: Enable Support_Atomic_Primitives on VxWorks 7 PPC

[Marc Poulhiès via Gcc-patches]

From: Johannes Kliemann 

gcc/ada/

* libgnat/system-vxworks7-ppc-kernel.ads: Enable
Support_Atomic_Primitives.
* libgnat/system-vxworks7-ppc-rtp-smp.ads: Likewise.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/libgnat/system-vxworks7-ppc-kernel.ads  | 2 +-
 gcc/ada/libgnat/system-vxworks7-ppc-rtp-smp.ads | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/libgnat/system-vxworks7-ppc-kernel.ads 
b/gcc/ada/libgnat/system-vxworks7-ppc-kernel.ads
index 573abe7aa99..bbf6d983a67 100644
--- a/gcc/ada/libgnat/system-vxworks7-ppc-kernel.ads
+++ b/gcc/ada/libgnat/system-vxworks7-ppc-kernel.ads
@@ -148,7 +148,7 @@ private
Stack_Check_Probes: constant Boolean := True;
Stack_Check_Limits: constant Boolean := False;
Support_Aggregates: constant Boolean := True;
-   Support_Atomic_Primitives : constant Boolean := False;
+   Support_Atomic_Primitives : constant Boolean := True;
Support_Composite_Assign  : constant Boolean := True;
Support_Composite_Compare : constant Boolean := True;
Support_Long_Shifts   : constant Boolean := True;
diff --git a/gcc/ada/libgnat/system-vxworks7-ppc-rtp-smp.ads 
b/gcc/ada/libgnat/system-vxworks7-ppc-rtp-smp.ads
index cc25943f063..de1e10d07e4 100644
--- a/gcc/ada/libgnat/system-vxworks7-ppc-rtp-smp.ads
+++ b/gcc/ada/libgnat/system-vxworks7-ppc-rtp-smp.ads
@@ -153,7 +153,7 @@ private
Stack_Check_Probes: constant Boolean := True;
Stack_Check_Limits: constant Boolean := False;
Support_Aggregates: constant Boolean := True;
-   Support_Atomic_Primitives : constant Boolean := False;
+   Support_Atomic_Primitives : constant Boolean := True;
Support_Composite_Assign  : constant Boolean := True;
Support_Composite_Compare : constant Boolean := True;
Support_Long_Shifts   : constant Boolean := True;
-- 
2.40.0

[COMMITTED] ada: Minor adjustments to Standard_Address

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

Standard_Address is an internal entity that is meant to be a clone of
System.Address built at compilation startup.  It needs to be seen as a
bona-fide address by the code generator.  For the sake of completeness,
it is also given its modulus, although this does not matter in practice.

gcc/ada/

* cstand.adb (Create_Standard): Set the Is_Descendant_Of_Address
flag on Standard_Address.
* freeze.adb (Freeze_Entity): Copy the modulus of System.Address
onto Standard_Address.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/cstand.adb |  2 ++
 gcc/ada/freeze.adb | 18 ++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/gcc/ada/cstand.adb b/gcc/ada/cstand.adb
index fbd5888b198..d4a420deda9 100644
--- a/gcc/ada/cstand.adb
+++ b/gcc/ada/cstand.adb
@@ -1370,9 +1370,11 @@ package body CStand is
 
   --  Standard_Address is not user visible, but is used internally. It is
   --  an unsigned type mod 2**System_Address_Size with System.Address size.
+  --  We flag it as Is_Descendant_Of_Address for code generation purposes.
 
   Standard_Address := New_Standard_Entity ("standard_address");
   Build_Unsigned_Integer_Type (Standard_Address, System_Address_Size);
+  Set_Is_Descendant_Of_Address (Standard_Address);
 
   --  Note: universal integer and universal real are constructed as fully
   --  formed signed numeric types, with parameters corresponding to the
diff --git a/gcc/ada/freeze.adb b/gcc/ada/freeze.adb
index 1a1eace600b..5d3413c1505 100644
--- a/gcc/ada/freeze.adb
+++ b/gcc/ada/freeze.adb
@@ -7284,10 +7284,20 @@ package body Freeze is
  elsif Is_Integer_Type (E) then
 Adjust_Esize_For_Alignment (E);
 
-if Is_Modular_Integer_Type (E)
-  and then Warn_On_Suspicious_Modulus_Value
-then
-   Check_Suspicious_Modulus (E);
+if Is_Modular_Integer_Type (E) then
+   --  Standard_Address has been built with the assumption that its
+   --  modulus was System_Address_Size, but this is not a universal
+   --  property and may need to be corrected.
+
+   if Is_RTE (E, RE_Address) then
+  Set_Modulus (Standard_Address, Modulus (E));
+  Set_Intval
+(High_Bound (Scalar_Range (Standard_Address)),
+ Modulus (E) - 1);
+
+   elsif Warn_On_Suspicious_Modulus_Value then
+  Check_Suspicious_Modulus (E);
+   end if;
 end if;
 
  --  The pool applies to named and anonymous access types, but not
-- 
2.40.0

[COMMITTED] ada: Require successful build of xsnamest

[Marc Poulhiès via Gcc-patches]

From: Tom Tromey 

While experimenting, I introduced a compilation error into xsnamest.
This took a little while to track down because, while the error was in
the log, the build did not stop.  This patch changes Make-generated.in
to require a successful build of this program.

gcc/ada/

* Make-generated.in (ada/stamp-snames): Check result of
gnatmake.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/Make-generated.in | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/Make-generated.in b/gcc/ada/Make-generated.in
index 948fc508a56..95c2a1df352 100644
--- a/gcc/ada/Make-generated.in
+++ b/gcc/ada/Make-generated.in
@@ -46,7 +46,7 @@ ada/stamp-snames : ada/snames.ads-tmpl ada/snames.adb-tmpl 
ada/snames.h-tmpl ada
-$(MKDIR) ada/bldtools/snamest
$(RM) $(addprefix ada/bldtools/snamest/,$(notdir $^))
$(CP) $^ ada/bldtools/snamest
-   cd ada/bldtools/snamest; gnatmake -q xsnamest ; ./xsnamest
+   cd ada/bldtools/snamest && gnatmake -q xsnamest && ./xsnamest
$(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.ns 
ada/snames.ads
$(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.nb 
ada/snames.adb
$(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.nh ada/snames.h
-- 
2.40.0

Re: [PATCH] LoongArch: Fix the problem of structure parameter passing in C++. This structure has empty structure members and less than three floating point members.

[Jonathan Wakely via Gcc-patches]

On Wed, 24 May 2023 at 21:15, Jason Merrill  wrote:

> On Wed, May 24, 2023 at 5:00 AM Jonathan Wakely via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
>
>> On Wed, 24 May 2023 at 09:41, Xi Ruoyao  wrote:
>>
>> > Wang Lei raised some concerns about Itanium C++ ABI, so let's ask a C++
>> > expert here...
>> >
>> > Jonathan: AFAIK the standard and the Itanium ABI treats an empty class
>> > as size 1
>>
>> Only as a complete object, not as a subobject.
>>
>
> Also as a data member subobject.
>
>
>> > in order to guarantee unique address, so for the following:
>> >
>> > class Empty {};
>> > class Test { Empty empty; double a, b; };
>>
>> There is no need to have a unique address here, so Test::empty and Test::a
>> have the same address. It's a potentially-overlapping subobject.
>>
>> For the Itanium ABI, sizeof(Test) == 2 * sizeof(double).
>>
>
> That would be true if Test::empty were marked [[no_unique_address]], but
> without that attribute, sizeof(Test) is actually 3 * sizeof(double).
>

Doh, yes.


>
>
>> > When we pass "Test" via registers, we may only allocate the registers
>> > for Test::a and Test::b, and complete ignore Test::empty because there
>> > is no addresses of registers.  Is this correct or not?
>>
>> I think that's a decision for the loongarch psABI. In principle, there's
>> no
>> reason a register has to be used to pass Test::empty, since you can't read
>> from it or write to it.
>>
>
> Agreed.  The Itanium C++ ABI has nothing to say about how registers are
> allocated for parameter passing; this is a matter for the psABI.
>
> And there is no need for a psABI to allocate a register for Test::empty
> because it contains no data.
>
> In the x86_64 psABI, Test above is passed in memory because of its size
> ("the size of the aggregate exceeds two eightbytes...").  But
>
> struct Test2 { Empty empty; double a; };
>
> is passed in a single floating-point register; the Test2::empty subobject
> is not passed anywhere, because its eightbyte is classified as NO_CLASS,
> because there is no actual data there.
>
> I know nothing about the LoongArch psABI, but going out of your way to
> assign a register to an empty class seems like a mistake.
>
> > On Wed, 2023-05-24 at 14:45 +0800, Xi Ruoyao via Gcc-patches wrote:
>> > > On Wed, 2023-05-24 at 14:04 +0800, Lulu Cheng wrote:
>> > > > An empty struct type that is not non-trivial for the purposes of
>> > > > calls
>> > > > will be treated as though it were the following C type:
>> > > >
>> > > > struct {
>> > > >   char c;
>> > > > };
>> > > >
>> > > > Before this patch was added, a structure parameter containing an
>> > > > empty structure and
>> > > > less than three floating-point members was passed through one or two
>> > > > floating-point
>> > > > registers, while nested empty structures are ignored. Which did not
>> > > > conform to the
>> > > > calling convention.
>> > >
>> > > No, it's a deliberate decision I've made in
>> > > https://gcc.gnu.org/r12-8294.  And we already agreed "the ABI needs
>> to
>> > > be updated" when we applied r12-8294, but I've never improved my
>> > > English
>> > > skill to revise the ABI myself :(.
>> > >
>> > > We are also using the same "de-facto" ABI throwing away the empty
>> > > struct
>> > > for Clang++ (https://reviews.llvm.org/D132285).  So we should update
>> > > the
>> > > spec here, instead of changing every implementation.
>> > >
>> > > The C++ standard treats the empty struct as size 1 for ensuring the
>> > > semantics of pointer comparison operations.  When we pass it through
>> > > the
>> > > registers, there is no need to really consider the empty field because
>> > > there is no pointers to registers.
>> > >
>> >
>> >
>>
>>

Re: [PATCH] Fix type error of 'switch (SUBREG_BYTE (op)).'

[Jin Ma via Gcc-patches]

> > On 5/17/23 03:03, Jin Ma wrote:
> >> For example:
> >> (define_insn "mov_lowpart_sidi2"
> >>[(set (match_operand:SI0 "register_operand" "=r")
> >>  (subreg:SI (match_operand:DI 1 "register_operand" " r") 0))]
> >>"TARGET_64BIT"
> >>"mov\t%0,%1")
> >> 
> >> (define_insn "mov_highpart_sidi2"
> >>[(set (match_operand:SI0 "register_operand" "=r")
> >>  (subreg:SI (match_operand:DI 1 "register_operand" " r") 1))]
> >>"TARGET_64BIT"
> >>"movh\t%0,%1")
> >> 
> >> When defining the above patterns, the generated file insn-recog.cc will
> >> appear 'switch (SUBREG_BYTE (op))', but since the return value of
> >> SUBREG_BYTE is poly_uint16_pod, the following error will occur:
> >> "error: switch quantity not an integer".
> >> 
> >> gcc/ChangeLog:
> >> 
> >>  * genrecog.cc (print_nonbool_test): Fix type error of
> >>  'switch (SUBREG_BYTE (op))'.
> > Thanks.  Installed.
> 
> We shouldn't add to_constant just because it's a convenient
> way of getting rid of errors :)  There has to be a good reason
> in principle why the value is known at compile time.
> 
> So I think this should be reverted.  Nothing guarantees that
> SUBREG_BYTEs are constant on AArch64 and RISC-V.  And for SVE
> it's common for them not to be.
> 
> If we want to support the above, I think we need to make the
> generator use known_eq instead.
> 
> The patterns don't look right though.  An SI subreg of a DI
> can't have a SUBREG_BYTE of 1.  And the lowpart SUBREG_BYTE
> depends on endianness.  So I think a better way of writing
> the lowpart pattern above is to use subreg_lowpart_operator
> (which riscv already has).
> 
> The high part can't be done using subregs though.
> 
> Thanks,
> Richard

I'm trying to understand what you mean. The return value of
the SUBREG_BYTE is poly_uint16_pod. When the value of the
NUM_POLY_INT_COEFFS is 2, using to_constant () to convert
to a constant may lose coeffs[1], right?

I agree with this, we can revert this first, but this problem
always exists, and it seems that we need to find other suitable
ways to solve this error.

Thanks,
Jin

[PATCH] RISC-V: In pipeline scheduling, insns should not be fusion in different BB blocks.

[Jin Ma via Gcc-patches]

When the last insn1 of BB1 and the first insn2 of BB2 are fusion, insn2 will
clear all dependencies in the function chain_to_prev_insn, resulting in insn2
may mov to any BB, and the program calculation result is wrong.

gcc/ChangeLog:

* sched-deps.cc (sched_macro_fuse_insns): Insns should not be fusion
in different BB blocks
---
 gcc/sched-deps.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/sched-deps.cc b/gcc/sched-deps.cc
index 2aa6623ad2e..998fe930804 100644
--- a/gcc/sched-deps.cc
+++ b/gcc/sched-deps.cc
@@ -2833,7 +2833,7 @@ sched_macro_fuse_insns (rtx_insn *insn)
  compile time complexity.  */
   if (DEBUG_INSN_P (insn))
 return;
-  prev = prev_nonnote_nondebug_insn (insn);
+  prev = prev_nonnote_nondebug_insn_bb (insn);
   if (!prev)
 return;
 
-- 
2.17.1

RE: [PATCH] i386: Fix incorrect intrinsic signature for AVX512 s{lli|rai|rli}

[Liu, Hongtao via Gcc-patches]

> -Original Message-
> From: Hu, Lin1 
> Sent: Thursday, May 25, 2023 3:52 PM
> To: Hongtao Liu 
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ;
> ubiz...@gmail.com
> Subject: RE: [PATCH] i386: Fix incorrect intrinsic signature for AVX512
> s{lli|rai|rli}
> 
> OK, I update the change log and modify a part of format. The attached file is
> the new version.
LGTM.
> 
> -Original Message-
> From: Hongtao Liu 
> Sent: Thursday, May 25, 2023 11:40 AM
> To: Hu, Lin1 
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ;
> ubiz...@gmail.com
> Subject: Re: [PATCH] i386: Fix incorrect intrinsic signature for AVX512
> s{lli|rai|rli}
> 
> On Thu, May 25, 2023 at 10:55 AM Hu, Lin1 via Gcc-patches
>  wrote:
> >
> > Hi all,
> >
> > This patch aims to fix incorrect intrinsic signature for
> _mm{512|256|}_s{lli|rai|rli}_epi*. And it has been tested on x86_64-pc-
> linux-gnu. OK for trunk?
> >
> > BRs,
> > Lin
> >
> > gcc/ChangeLog:
> >
> > PR target/109173
> > PR target/109174
> > * config/i386/avx512bwintrin.h (_mm512_srli_epi16): Change type
> from
> > int to const int.
> int to unsigned int or const int to const unsigned int.
> Others LGTM.
> > (_mm512_mask_srli_epi16): Ditto.
> > (_mm512_slli_epi16): Ditto.
> > (_mm512_mask_slli_epi16): Ditto.
> > (_mm512_maskz_slli_epi16): Ditto.
> > (_mm512_srai_epi16): Ditto.
> > (_mm512_mask_srai_epi16): Ditto.
> > (_mm512_maskz_srai_epi16): Ditto.
> > * config/i386/avx512vlintrin.h (_mm256_mask_srli_epi32): Ditto.
> > (_mm256_maskz_srli_epi32): Ditto.
> > (_mm_mask_srli_epi32): Ditto.
> > (_mm_maskz_srli_epi32): Ditto.
> > (_mm256_mask_srli_epi64): Ditto.
> > (_mm256_maskz_srli_epi64): Ditto.
> > (_mm_mask_srli_epi64): Ditto.
> > (_mm_maskz_srli_epi64): Ditto.
> > (_mm256_mask_srai_epi32): Ditto.
> > (_mm256_maskz_srai_epi32): Ditto.
> > (_mm_mask_srai_epi32): Ditto.
> > (_mm_maskz_srai_epi32): Ditto.
> > (_mm256_srai_epi64): Ditto.
> > (_mm256_mask_srai_epi64): Ditto.
> > (_mm256_maskz_srai_epi64): Ditto.
> > (_mm_srai_epi64): Ditto.
> > (_mm_mask_srai_epi64): Ditto.
> > (_mm_maskz_srai_epi64): Ditto.
> > (_mm_mask_slli_epi32): Ditto.
> > (_mm_maskz_slli_epi32): Ditto.
> > (_mm_mask_slli_epi64): Ditto.
> > (_mm_maskz_slli_epi64): Ditto.
> > (_mm256_mask_slli_epi32): Ditto.
> > (_mm256_maskz_slli_epi32): Ditto.
> > (_mm256_mask_slli_epi64): Ditto.
> > (_mm256_maskz_slli_epi64): Ditto.
> > (_mm_mask_srai_epi16): Ditto.
> > (_mm_maskz_srai_epi16): Ditto.
> > (_mm256_srai_epi16): Ditto.
> > (_mm256_mask_srai_epi16): Ditto.
> > (_mm_mask_slli_epi16): Ditto.
> > (_mm_maskz_slli_epi16): Ditto.
> > (_mm256_mask_slli_epi16): Ditto.
> > (_mm256_maskz_slli_epi16): Ditto.
> >
> > gcc/testsuite/ChangeLog:
> >
> > PR target/109173
> > PR target/109174
> > * gcc.target/i386/pr109173-1.c: New test.
> > * gcc.target/i386/pr109174-1.c: Ditto.
> > ---
> >  gcc/config/i386/avx512bwintrin.h   |  32 +++---
> >  gcc/config/i386/avx512fintrin.h|  58 +++
> >  gcc/config/i386/avx512vlbwintrin.h |  36 ---
> >  gcc/config/i386/avx512vlintrin.h   | 112 +++--
> >  gcc/testsuite/gcc.target/i386/pr109173-1.c |  57 +++
> >  gcc/testsuite/gcc.target/i386/pr109174-1.c |  45 +
> >  6 files changed, 236 insertions(+), 104 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/i386/pr109173-1.c
> >  create mode 100644 gcc/testsuite/gcc.target/i386/pr109174-1.c
> >
> > diff --git a/gcc/config/i386/avx512bwintrin.h
> b/gcc/config/i386/avx512bwintrin.h
> > index 89790f7917b..791d4e35f32 100644
> > --- a/gcc/config/i386/avx512bwintrin.h
> > +++ b/gcc/config/i386/avx512bwintrin.h
> > @@ -2880,7 +2880,7 @@ _mm512_maskz_dbsad_epu8 (__mmask32 __U,
> __m512i __A, __m512i __B,
> >
> >  extern __inline __m512i
> >  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> > -_mm512_srli_epi16 (__m512i __A, const int __imm)
> > +_mm512_srli_epi16 (__m512i __A, const unsigned int __imm)
> >  {
> >return (__m512i) __builtin_ia32_psrlwi512_mask ((__v32hi) __A, __imm,
> >   (__v32hi)
> > @@ -2891,7 +2891,7 @@ _mm512_srli_epi16 (__m512i __A, const int
> __imm)
> >  extern __inline __m512i
> >  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> >  _mm512_mask_srli_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
> > -   const int __imm)
> > +   const unsigned int __imm)
> >  {
> >return (__m512i) __builtin_ia32_psrlwi512_mask ((__v32hi) __A, __imm,
> >   (__v32hi) __W,
> > @@ -2910,7 +2

RE: [PATCH] aarch64: Implement vector FP absolute compare intrinsics with builtins

[Kyrylo Tkachov via Gcc-patches]

> -Original Message-
> From: Kyrylo Tkachov
> Sent: Thursday, May 18, 2023 12:14 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford 
> Subject: [PATCH] aarch64: Implement vector FP absolute compare intrinsics
> with builtins
> 
> Hi all,
> 
> While optimising some vector math library code with intrinsics we stumbled
> upon the issue in the testcase.
> The compiler should be generating a FACGT instruction but instead we
> generate:
> foo(__Float32x4_t, __Float32x4_t, __Float32x4_t):
> fabsv0.4s, v0.4s
> adrpx0, .LC0
> ldr q31, [x0, #:lo12:.LC0]
> fcmgt   v0.4s, v0.4s, v31.4s
> ret
> 
> This is because the vcagtq_f32 intrinsic is open-coded in arm_neon.h as
> return vabsq_f32 (__a) > vabsq_f32 (__b)
> thus relying on the optimisers to merge it back together. But since one of the
> arms of the comparison
> is a vector constant the combine pass optimises the abs into it and tries
> matching:
> (set (reg:V4SI 101)
> (neg:V4SI (gt:V4SI (reg:V4SF 100)
> (const_vector:V4SF [
> (const_double:SF 1.0e+2 [0x0.c8p+7]) repeated x4
> ]
> and
> (set (reg:V4SI 101)
> (neg:V4SI (gt:V4SI (abs:V4SF (reg:V4SF 104))
> (reg:V4SF 103
> 
> instead of what we want:
> (insn 13 9 14 2 (set (reg/i:V4SI 32 v0)
> (neg:V4SI (gt:V4SI (abs:V4SF (reg:V4SF 98))
> (abs:V4SF (reg:V4SF 96)
> 
> I don't really see a good way around that with our current implementation of
> these intrinsics.
> Therefore this patch reimplements these intrinsics with aarch64 builtins that
> generate the RTL for these
> instructions directly. Apparently we already had them defined in aarch64-
> simd-builtins.def and have been
> using them for the fp16 case already.
> I realise that this approach is against the general principle of expressing
> intrinsics in the higher-level constructs,
> so I'm willing to listen to counter-arguments.
> That said, the FACGT/FACGE instructions are as fast as the non-ABS
> comparison instructions on all microarchitectures that I know of
> so it should always be a win to have them in the merged form rather than
> split the fabs step separately or try to hoist it.
> And the testcase does come from real library code that we're trying to
> optimise.
> With this patch for the testcase we generate:
> foo:
> adrpx0, .LC0
> ldr q31, [x0, #:lo12:.LC0]
> facgt   v0.4s, v0.4s, v31.4s
> ret
> 
> Bootstrapped and tested on aarch64-none-linux-gnu.
> I'll hold off on committing this to give folks a few days to comment, but will
> push by the end of next week if there are no objections.

Pushed to trunk.
Thanks,
Kyrill

> 
> Thanks,
> Kyrill
> 
> gcc/ChangeLog:
> 
>   * config/aarch64/arm_neon.h (vcage_f64): Reimplement with
> builtins.
>   (vcage_f32): Likewise.
>   (vcages_f32): Likewise.
>   (vcageq_f32): Likewise.
>   (vcaged_f64): Likewise.
>   (vcageq_f64): Likewise.
>   (vcagts_f32): Likewise.
>   (vcagt_f32): Likewise.
>   (vcagt_f64): Likewise.
>   (vcagtq_f32): Likewise.
>   (vcagtd_f64): Likewise.
>   (vcagtq_f64): Likewise.
>   (vcale_f32): Likewise.
>   (vcale_f64): Likewise.
>   (vcaled_f64): Likewise.
>   (vcales_f32): Likewise.
>   (vcaleq_f32): Likewise.
>   (vcaleq_f64): Likewise.
>   (vcalt_f32): Likewise.
>   (vcalt_f64): Likewise.
>   (vcaltd_f64): Likewise.
>   (vcaltq_f32): Likewise.
>   (vcaltq_f64): Likewise.
>   (vcalts_f32): Likewise.
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.target/aarch64/simd/facgt_constpool_1.c: New test.

[PATCH] tree-optimization/109791 - expand &x + off for niter compute

[Richard Biener via Gcc-patches]

The following makes expand_simple_operations expand POINTER_PLUS_EXPRs
with variable offset when the base is invariant.  That will allow
to simplify address differences to offset differences in some cases.
Note the patch doesn't follow the variable off chain as I don't have
a testcase showing that's beneficial.

Bootstrapped and tested on x86_64-unknown-linux-gnu.

I'm going to push this when the last patch in the series tests OK
and the testcase from PR109791 then can be added.

PR tree-optimization/109791
* tree-ssa-loop-niter.cc (expand_simple_operations): Expand &x + off.
---
 gcc/tree-ssa-loop-niter.cc | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/gcc/tree-ssa-loop-niter.cc b/gcc/tree-ssa-loop-niter.cc
index 5d398b67e68..159fdc8fb85 100644
--- a/gcc/tree-ssa-loop-niter.cc
+++ b/gcc/tree-ssa-loop-niter.cc
@@ -2817,12 +2817,17 @@ expand_simple_operations (tree expr, tree stop, 
hash_map &cache)
return expr;
   /* Fallthru.  */
 case POINTER_PLUS_EXPR:
-  /* And increments and decrements by a constant are simple.  */
+  /* And increments and decrements by a constant are simple.
+Also expand increments from an invariant base (but do not follow
+a variable offset).  */
   e1 = gimple_assign_rhs2 (stmt);
-  if (!is_gimple_min_invariant (e1))
+  if (is_gimple_min_invariant (e1))
+   ee = expand_simple_operations (e, stop, cache);
+  else if (is_gimple_min_invariant (e))
+   ee = e;
+  else
return expr;
 
-  ee = expand_simple_operations (e, stop, cache);
   return fold_build2 (code, TREE_TYPE (expr), ee, e1);
 
 default:
-- 
2.35.3

Re: [PATCH V15] VECT: Add decrement IV iteration loop control by variable amount support

[Richard Sandiford via Gcc-patches]

Thanks, this looks functionally correct to me.  And I agree it handles
the cases that previously needed multiplication.

But I think it regresses code quality when no multiplication was needed.
We can now generate duplicate IVs.  Perhaps ivopts would remove the
duplicates, but it might be hard, because of the variable steps.

For example, we would generate duplicate IVs for non-SLP code that
operates on multiple vector sizes.  (Can't remembrer what the status
of unpack/truncate patterns is on RVV.)  But it also shows up for SLP.
E.g., I would expect duplicate IVs for:

uint16_t x[100];
uint32_t y[200];

void f() {
  for (int i = 0; i < 100; i += 2) {
x[i + 0] += 1;
x[i + 1] += 2;
y[i + 0] += 1;
y[i + 1] += 2;
  }
}

So I think the call to vect_set_loop_controls_directly does still
need to be inside an "if".  But the "if" condition should be based
on whether the IV step is different.  As discussed yesterday, the
IV step is different if nitems_per_iter, aka:

  max_nscalars_per_iter * factor

is different.

Because of that, I think I was wrong to suggest storing the IV in
loop_vinfo.  It should probably be stored in rgroup_controls instead.

Then we could have a structure like this:

  rgroup_controls *rgc;
  rgroup_controls *iv_rgc = nullptr;
  ...
  FOR_EACH_VEC_ELT (*controls, i, rgc)
if (!rgc->controls.is_empty ())
  {
...
if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
|| !iv_rgc
|| (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
!= rgc->max_nscalars_per_iter * rgc->factor))
  {
/* See whether zero-based IV would ever generate all-false masks
   or zero length before wrapping around.  */
bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, rgc);

/* Set up all controls for this group.  */
test_ctrl = vect_set_loop_controls_directly (loop, loop_vinfo,
 &preheader_seq,
 &header_seq,
 loop_cond_gsi, rgc,
 niters, niters_skip,
 might_wrap_p);

iv_rgc = rgc;
  }

if (LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
&& rgc->controls.length () > 1)
  {
...your code, using the iv in iv_rgc...;
  }
  }

Some other comments:

> diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc
> index ff6159e08d5..f9d92ced982 100644
> --- a/gcc/tree-vect-loop-manip.cc
> +++ b/gcc/tree-vect-loop-manip.cc
> @@ -468,6 +468,38 @@ vect_set_loop_controls_directly (class loop *loop, 
> loop_vec_info loop_vinfo,
>gimple_stmt_iterator incr_gsi;
>bool insert_after;
>standard_iv_increment_position (loop, &incr_gsi, &insert_after);
> +  if (LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo))
> +{
> +  /* single rgroup:

Instead of "single rgroup", how about:

  /* Create an IV that counts down from niters_total and whose step
 is the (variable) amount processed in the current iteration:

But please keep the example below as well.

> +  ...
> +  _10 = (unsigned long) count_12(D);
> +  ...
> +  # ivtmp_9 = PHI 
> +  _36 = MIN_EXPR ;
> +  ...
> +  vect__4.8_28 = .LEN_LOAD (_17, 32B, _36, 0);
> +  ...
> +  ivtmp_35 = ivtmp_9 - _36;
> +  ...
> +  if (ivtmp_35 != 0)
> +goto ; [83.33%]
> +  else
> +goto ; [16.67%]
> +  */
> +  nitems_total = gimple_convert (preheader_seq, iv_type, nitems_total);
> +  tree step = rgc->controls.length () == 1 ? rgc->controls[0]
> +: make_ssa_name (iv_type);
> +  /* Create decrement IV.  */
> +  create_iv (nitems_total, MINUS_EXPR, step, NULL_TREE, loop, &incr_gsi,
> +  insert_after, &index_before_incr, &index_after_incr);
> +  gimple_seq_add_stmt (header_seq, gimple_build_assign (step, MIN_EXPR,
> + index_before_incr,
> + nitems_step));
> +  LOOP_VINFO_DECREMENTING_IV_STEP (loop_vinfo) = step;
> +  return index_after_incr;
> +}
> +
> +  /* Create increment IV.  */
>create_iv (build_int_cst (iv_type, 0), PLUS_EXPR, nitems_step, NULL_TREE,
>loop, &incr_gsi, insert_after, &index_before_incr,
>&index_after_incr);
> @@ -683,6 +715,63 @@ vect_set_loop_controls_directly (class loop *loop, 
> loop_vec_info loop_vinfo,
>return next_ctrl;
>  }
>  
> +/* Try to use adjust loop lens for multiple-rgroups.

This is no longer "try", since the function always does something.

How about:

/* Populate DEST_RGM->controls, given that they should add up to STEP.

> +
> + _36 = MIN

[PATCH] RISC-V: Add autovec sign/zero extension and truncation.

[Robin Dapp via Gcc-patches]

Hi,

this patch implements the autovec expanders for sign and zero extension
patterns as well as the accompanying truncations.  In order to use them
additional mode_attr iterators as well as vectorizer hooks are required.
Using these hooks we can e.g. vectorize with VNx4QImode as base mode
and extend VNx4SI to VNx4DI.  They are still going to be expanded in the
future.

vf4 and vf8 truncations are emulated by truncating two and three times
respectively.

The patch also adds tests and changes some expectations for already
existing ones.

Combine does not yet handle binary operations of two widened operands
as we are missing the necessary split/rewrite patterns.  These will be
added at a later time.

Co-authored-by: Juzhe Zhong 

riscv.exp testsuite is unchanged.  zero-scratch-regs-3.c seems
to FAIL in vcondu but that already happens on trunk.

Regards
 Robin

gcc/ChangeLog:

* config/riscv/autovec.md (2): New
expander.
(2): Dito.
(2): Dito.
(trunc2): Dito.
(trunc2): Dito.
(trunc2): Dito.
* config/riscv/riscv-protos.h (riscv_v_ext_mode_p): Declare.
(vectorize_related_mode): Define.
(autovectorize_vector_modes): Define.
* config/riscv/riscv-v.cc (vectorize_related_mode): Implement
hook.
(autovectorize_vector_modes): Implement hook.
* config/riscv/riscv.cc (riscv_v_ext_tuple_mode_p): Export.
(riscv_autovectorize_vector_modes): Implement target hook.
(riscv_vectorize_related_mode): Implement target hook.
(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define.
(TARGET_VECTORIZE_RELATED_MODE): Define.
* config/riscv/vector-iterators.md: Add lowercase versions of
mode_attr iterators.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adjust
expectation.
* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64d-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64f-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64x-2.c: Dito.
* gcc.target/riscv/rvv/rvv.exp: Add new conversion tests.
* gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Do not vectorize.
* gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Dito.
* gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Dito.
* gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Dito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Dito.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-template.h: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-template.h: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-template.h: New test.
---
 gcc/config/riscv/autovec.md   | 104 ++
 gcc/config/riscv/riscv-protos.h   |   5 +
 gcc/config/riscv/riscv-v.cc   |  83 ++
 gcc/config/riscv/riscv.cc |  31 +-
 gcc/config/riscv/vector-iterators.md  |  33 +-
 .../riscv/rvv/autovec/binop/shift-rv32gcv.c   |   1 -
 .../riscv/rvv/autovec/binop/shift-rv64gcv.c   |   5 +-
 .../riscv/rvv/autovec/binop/vdiv-run.c|   4 +-
 .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c|   7 +-
 .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c|   7 +-
 .../riscv/rvv/autovec/binop/vdiv-template.h   |   5 +-
 .../riscv/rvv/autovec/binop/vrem-rv32gcv.c|   7 +-
 .../riscv/rvv/autovec/binop/vrem-rv64gcv.c|   7 +-
 .../riscv/rvv/autovec/conversions/vncvt-run.c |  35 ++
 .../rvv/autovec/conversions/vncvt-rv32gcv.c   |   6 +
 .../rvv/autovec/conversions/vncvt-rv64gcv.c   |   6 +
 .../rvv/autovec/conversions/vncvt-template.h  |  19 
 .../riscv/rvv/autovec/conversions/vsext-run.c | 

Re: [PATCH] Fix type error of 'switch (SUBREG_BYTE (op)).'

[Richard Sandiford via Gcc-patches]

"Jin Ma"  writes:
>> > On 5/17/23 03:03, Jin Ma wrote:
>> >> For example:
>> >> (define_insn "mov_lowpart_sidi2"
>> >>[(set (match_operand:SI0 "register_operand" "=r")
>> >>  (subreg:SI (match_operand:DI 1 "register_operand" " r") 0))]
>> >>"TARGET_64BIT"
>> >>"mov\t%0,%1")
>> >> 
>> >> (define_insn "mov_highpart_sidi2"
>> >>[(set (match_operand:SI0 "register_operand" "=r")
>> >>  (subreg:SI (match_operand:DI 1 "register_operand" " r") 1))]
>> >>"TARGET_64BIT"
>> >>"movh\t%0,%1")
>> >> 
>> >> When defining the above patterns, the generated file insn-recog.cc will
>> >> appear 'switch (SUBREG_BYTE (op))', but since the return value of
>> >> SUBREG_BYTE is poly_uint16_pod, the following error will occur:
>> >> "error: switch quantity not an integer".
>> >> 
>> >> gcc/ChangeLog:
>> >> 
>> >>  * genrecog.cc (print_nonbool_test): Fix type error of
>> >>  'switch (SUBREG_BYTE (op))'.
>> > Thanks.  Installed.
>> 
>> We shouldn't add to_constant just because it's a convenient
>> way of getting rid of errors :)  There has to be a good reason
>> in principle why the value is known at compile time.
>> 
>> So I think this should be reverted.  Nothing guarantees that
>> SUBREG_BYTEs are constant on AArch64 and RISC-V.  And for SVE
>> it's common for them not to be.
>> 
>> If we want to support the above, I think we need to make the
>> generator use known_eq instead.
>> 
>> The patterns don't look right though.  An SI subreg of a DI
>> can't have a SUBREG_BYTE of 1.  And the lowpart SUBREG_BYTE
>> depends on endianness.  So I think a better way of writing
>> the lowpart pattern above is to use subreg_lowpart_operator
>> (which riscv already has).
>> 
>> The high part can't be done using subregs though.
>> 
>> Thanks,
>> Richard
>
> I'm trying to understand what you mean. The return value of
> the SUBREG_BYTE is poly_uint16_pod. When the value of the
> NUM_POLY_INT_COEFFS is 2, using to_constant () to convert
> to a constant may lose coeffs[1], right?

to_constant will abort compilation if coeffs[1] is nonzero.
So we should only use it in contexts where coeffs[1] is already
known to be zero.

We don't know coeffs[1] is already zero here.  The purpose of the
switch statement is to test the value, which is currently unknown.

We handle (subreg ... 0) correctly when all subregs have byte 0.
In that case we use an "if" statement and use known_eq to test
the SUBREG_BYTE.  The problem only occurs when there are multiple
possible SUBREG_BYTEs at the same decision point.

I agree that it would make sense to support this, probably by
emitting a chain of known_eq "if" statements.

But before we do that, I think we should check whether there
is a legitimate use case.  Like I say, the patterns above don't
look correct to me.

Thanks,
Richard

Re: [PATCH] RISC-V: In pipeline scheduling, insns should not be fusion in different BB blocks.

[Richard Sandiford via Gcc-patches]

Jin Ma  writes:
> When the last insn1 of BB1 and the first insn2 of BB2 are fusion, insn2 will
> clear all dependencies in the function chain_to_prev_insn, resulting in insn2
> may mov to any BB, and the program calculation result is wrong.
>
> gcc/ChangeLog:
>
>   * sched-deps.cc (sched_macro_fuse_insns): Insns should not be fusion
>   in different BB blocks
> ---
>  gcc/sched-deps.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/sched-deps.cc b/gcc/sched-deps.cc
> index 2aa6623ad2e..998fe930804 100644
> --- a/gcc/sched-deps.cc
> +++ b/gcc/sched-deps.cc
> @@ -2833,7 +2833,7 @@ sched_macro_fuse_insns (rtx_insn *insn)
>   compile time complexity.  */
>if (DEBUG_INSN_P (insn))
>  return;
> -  prev = prev_nonnote_nondebug_insn (insn);
> +  prev = prev_nonnote_nondebug_insn_bb (insn);
>if (!prev)
>  return;

Huh, kind-of impressed we managed to go so long without hitting this.

The patch is OK, thanks (and for branches too if necessary).

Richard

Re: [PATCH] RISC-V: Add autovec sign/zero extension and truncation.

[juzhe.zh...@rivai.ai]

Hi, Robin.

>>+extern bool riscv_v_ext_mode_p (machine_mode mode);
No, we don't need it as global extern.

>> +  if (riscv_v_ext_mode_p (vector_mode)
>>+  && multiple_p (BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul),
>>+  GET_MODE_SIZE (element_mode), &min_units))

use riscv_v_ext_vector_mode_p  instead since riscv_v_ext_mode_p includes tuple 
modes.
You should not use tuple modes in related_mode. Tuple modes will be used in 
array mode target hook and
used by vec_load_lanes/vec_store_lanes.

Otherwise LGTM since I have reviewed twice already.
Wait for kito's final approval.

Thanks.


juzhe.zh...@rivai.ai
 
From: Robin Dapp
Date: 2023-05-25 17:03
To: gcc-patches; Kito Cheng; palmer; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add autovec sign/zero extension and truncation.
Hi,
 
this patch implements the autovec expanders for sign and zero extension
patterns as well as the accompanying truncations.  In order to use them
additional mode_attr iterators as well as vectorizer hooks are required.
Using these hooks we can e.g. vectorize with VNx4QImode as base mode
and extend VNx4SI to VNx4DI.  They are still going to be expanded in the
future.
 
vf4 and vf8 truncations are emulated by truncating two and three times
respectively.
 
The patch also adds tests and changes some expectations for already
existing ones.
 
Combine does not yet handle binary operations of two widened operands
as we are missing the necessary split/rewrite patterns.  These will be
added at a later time.
 
Co-authored-by: Juzhe Zhong 
 
riscv.exp testsuite is unchanged.  zero-scratch-regs-3.c seems
to FAIL in vcondu but that already happens on trunk.
 
Regards
Robin
 
gcc/ChangeLog:
 
* config/riscv/autovec.md (2): New
expander.
(2): Dito.
(2): Dito.
(trunc2): Dito.
(trunc2): Dito.
(trunc2): Dito.
* config/riscv/riscv-protos.h (riscv_v_ext_mode_p): Declare.
(vectorize_related_mode): Define.
(autovectorize_vector_modes): Define.
* config/riscv/riscv-v.cc (vectorize_related_mode): Implement
hook.
(autovectorize_vector_modes): Implement hook.
* config/riscv/riscv.cc (riscv_v_ext_tuple_mode_p): Export.
(riscv_autovectorize_vector_modes): Implement target hook.
(riscv_vectorize_related_mode): Implement target hook.
(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define.
(TARGET_VECTORIZE_RELATED_MODE): Define.
* config/riscv/vector-iterators.md: Add lowercase versions of
mode_attr iterators.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adjust
expectation.
* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64d-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64f-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64x-2.c: Dito.
* gcc.target/riscv/rvv/rvv.exp: Add new conversion tests.
* gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Do not vectorize.
* gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Dito.
* gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Dito.
* gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Dito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Dito.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-template.h: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-template.h: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-template.h: New test.
---
gcc/config/riscv/autovec.md   | 104 ++
gcc/config/riscv/riscv-protos.h   |   5 +
gcc/config/riscv/riscv-v.cc   |  83 ++
gcc/config/riscv/riscv.cc |  31 +-
gcc/config/riscv/vector-iterators.md  |  33 +-
.../riscv/rvv/autovec/binop/shift-rv32gcv.c   |   1 -
.../riscv/rvv/autovec/binop/shift-rv64gcv.c   |   5 +-
.../riscv/rvv/autovec/binop/vdiv-run.c|   4 +-
.../riscv/rvv/autovec/binop/vdiv-rv32gcv.c|   7 +-
.../riscv/rvv/autovec/binop/vdiv-rv64gcv.c|   7 +-
.../riscv/rvv/autovec/binop/vdiv-

[PATCH] Add scalar_storage_order support to C++

[naveenh--- via Gcc-patches]

From: Naveen H S 

This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type similar. The code is similar to how it is handled in the C front-end.

2021-04-03  Andrew Pinski   

gcc/ChangeLog:

* c-family/c-attribs.cc (handle_scalar_storage_order_attribute):
Do not reject the C++ cases.
* cp/class.cc (layout_nonempty_base_or_field): Fix the type of
arrays in C++.
* cp/call.cc (reference_binding): Treat reversed field similar as
packed fields.
(build_temp): Likewise.
(convert_like_internal): Emit error code for non binding reversed
endian field.
* cp/cp-tree.h (clk_implicit_rval) : Add clk_reversed.
* cp/cp-tree.c (lvalue_kind) : Handle reverse storage ordered operands.

gcc/testsuite/ChangeLog:

* c-c++-common/sso/dump.h: Move from gcc.dg/sso to c-c++-common/sso.
* c-c++-common/sso/init1.h: Likewise.
* c-c++-common/sso/init13.h: Likewise.
* c-c++-common/sso/init2.h: Likewise.
* c-c++-common/sso/init3.h: Likewise.
* c-c++-common/sso/init4.h: Likewise.
* c-c++-common/sso/init5.h: Likewise.
* c-c++-common/sso/init6.h: Likewise.
* c-c++-common/sso/init7.h: Likewise.
* c-c++-common/sso/init8.h: Likewise.
* c-c++-common/sso/init9.h: Likewise.
* c-c++-common/sso/p1.c: Likewise.
* c-c++-common/sso/p13.c: Likewise.
* c-c++-common/sso/p2.c: Likewise.
* c-c++-common/sso/p3.c: Likewise.
* c-c++-common/sso/p4.c: Likewise.
* c-c++-common/sso/p5.c: Likewise.
* c-c++-common/sso/p6.c: Likewise.
* c-c++-common/sso/p7.c: Likewise.
* c-c++-common/sso/p8.c: Likewise.
* c-c++-common/sso/p9.c: Likewise.
* c-c++-common/sso/q1.c: Likewise.
* c-c++-common/sso/q13.c: Likewise.
* c-c++-common/sso/q2.c: Likewise.
* c-c++-common/sso/q3.c: Likewise.
* c-c++-common/sso/q4.c: Likewise.
* c-c++-common/sso/q5.c: Likewise.
* c-c++-common/sso/q6.c: Likewise.
* c-c++-common/sso/q7.c: Likewise.
* c-c++-common/sso/q8.c: Likewise.
* c-c++-common/sso/q9.c: Likewise.
* c-c++-common/sso/r3.c: Likewise.
* c-c++-common/sso/r5.c: Likewise.
* c-c++-common/sso/r6.c: Likewise.
* c-c++-common/sso/r7.c: Likewise.
* c-c++-common/sso/r8.c: Likewise.
* c-c++-common/sso/s3.c: Likewise.
* c-c++-common/sso/s5.c: Likewise.
* c-c++-common/sso/s6.c: Likewise.
* c-c++-common/sso/s7.c: Likewise.
* c-c++-common/sso/s8.c: Likewise.
* c-c++-common/sso/t1.c: Likewise.
* c-c++-common/sso/t13.c: Likewise.
* c-c++-common/sso/t2.c: Likewise.
* c-c++-common/sso/t3.c: Likewise.
* c-c++-common/sso/t4.c: Likewise.
* c-c++-common/sso/t5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* c-c++-common/sso/t7.c: Likewise.
* c-c++-common/sso/t8.c: Likewise.
* c-c++-common/sso/t9.c: Likewise.
* c-c++-common/sso/u5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* g++.dg/sso/sso.exp: New file.
* g++.dg/sso/auto-1.C: New file.
* g++.dg/sso/auto-2.C: New file.
* g++.dg/sso/auto-3.C: New file.
* g++.dg/sso/template-reference-1.C: New file.
* g++.dg/sso/template-reference-2.C: New file.
* g++.dg/sso/template-reference-3.C: New file.
* g++.dg/sso/template-reference-4.C: New file.
* g++.dg/sso-1.C: Modified.

Co-authored-by: Naveen H S 
---
 gcc/c-family/c-attribs.cc |  2 +-
 gcc/cp/call.cc| 17 ++-
 gcc/cp/class.cc   | 22 ++
 gcc/cp/cp-tree.h  |  3 +-
 gcc/cp/tree.cc|  5 ++-
 .../{gcc.dg => c-c++-common}/sso/dump.h   |  0
 .../{gcc.dg => c-c++-common}/sso/init1.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init13.h |  0
 .../{gcc.dg => c-c++-common}/sso/init2.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init3.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init4.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init5.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init6.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init7.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init8.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init9.h  |  0
 .../{gcc.dg => c-c++-common}/sso/p1.c |  0
 .../{gcc.dg => c-c++-common}/sso/p13.c|  1 +
 .../{gcc.dg => c-c++-common}/sso/p2.c |  0
 .../{gcc.dg => c-c++-common}/sso/p3.c |  0
 .../{gcc.dg => c-c++-common}/sso/p4.c |  0
 .../{gcc.dg => c-c++-common}/sso/p5.c |  0
 .../{gcc.dg => 

[PATCH] Add scalar_storage_order support to C++

[naveenh--- via Gcc-patches]

From: Naveen H S 

This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type similar. The code is similar to how it is handled in the C front-end.

2021-04-03  Andrew Pinski   

gcc/ChangeLog:

* c-family/c-attribs.cc (handle_scalar_storage_order_attribute):
Do not reject the C++ cases.
* cp/class.cc (layout_nonempty_base_or_field): Fix the type of
arrays in C++.
* cp/call.cc (reference_binding): Treat reversed field similar as
packed fields.
(build_temp): Likewise.
(convert_like_internal): Emit error code for non binding reversed
endian field.
* cp/cp-tree.h (clk_implicit_rval) : Add clk_reversed.
* cp/cp-tree.c (lvalue_kind) : Handle reverse storage ordered operands.

gcc/testsuite/ChangeLog:

* c-c++-common/sso/dump.h: Move from gcc.dg/sso to c-c++-common/sso.
* c-c++-common/sso/init1.h: Likewise.
* c-c++-common/sso/init13.h: Likewise.
* c-c++-common/sso/init2.h: Likewise.
* c-c++-common/sso/init3.h: Likewise.
* c-c++-common/sso/init4.h: Likewise.
* c-c++-common/sso/init5.h: Likewise.
* c-c++-common/sso/init6.h: Likewise.
* c-c++-common/sso/init7.h: Likewise.
* c-c++-common/sso/init8.h: Likewise.
* c-c++-common/sso/init9.h: Likewise.
* c-c++-common/sso/p1.c: Likewise.
* c-c++-common/sso/p13.c: Likewise.
* c-c++-common/sso/p2.c: Likewise.
* c-c++-common/sso/p3.c: Likewise.
* c-c++-common/sso/p4.c: Likewise.
* c-c++-common/sso/p5.c: Likewise.
* c-c++-common/sso/p6.c: Likewise.
* c-c++-common/sso/p7.c: Likewise.
* c-c++-common/sso/p8.c: Likewise.
* c-c++-common/sso/p9.c: Likewise.
* c-c++-common/sso/q1.c: Likewise.
* c-c++-common/sso/q13.c: Likewise.
* c-c++-common/sso/q2.c: Likewise.
* c-c++-common/sso/q3.c: Likewise.
* c-c++-common/sso/q4.c: Likewise.
* c-c++-common/sso/q5.c: Likewise.
* c-c++-common/sso/q6.c: Likewise.
* c-c++-common/sso/q7.c: Likewise.
* c-c++-common/sso/q8.c: Likewise.
* c-c++-common/sso/q9.c: Likewise.
* c-c++-common/sso/r3.c: Likewise.
* c-c++-common/sso/r5.c: Likewise.
* c-c++-common/sso/r6.c: Likewise.
* c-c++-common/sso/r7.c: Likewise.
* c-c++-common/sso/r8.c: Likewise.
* c-c++-common/sso/s3.c: Likewise.
* c-c++-common/sso/s5.c: Likewise.
* c-c++-common/sso/s6.c: Likewise.
* c-c++-common/sso/s7.c: Likewise.
* c-c++-common/sso/s8.c: Likewise.
* c-c++-common/sso/t1.c: Likewise.
* c-c++-common/sso/t13.c: Likewise.
* c-c++-common/sso/t2.c: Likewise.
* c-c++-common/sso/t3.c: Likewise.
* c-c++-common/sso/t4.c: Likewise.
* c-c++-common/sso/t5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* c-c++-common/sso/t7.c: Likewise.
* c-c++-common/sso/t8.c: Likewise.
* c-c++-common/sso/t9.c: Likewise.
* c-c++-common/sso/u5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* g++.dg/sso/sso.exp: New file.
* g++.dg/sso/auto-1.C: New file.
* g++.dg/sso/auto-2.C: New file.
* g++.dg/sso/auto-3.C: New file.
* g++.dg/sso/template-reference-1.C: New file.
* g++.dg/sso/template-reference-2.C: New file.
* g++.dg/sso/template-reference-3.C: New file.
* g++.dg/sso/template-reference-4.C: New file.
* g++.dg/sso-1.C: Modified.

Co-authored-by: Naveen H S 
---
 gcc/c-family/c-attribs.cc |  2 +-
 gcc/cp/call.cc| 17 ++-
 gcc/cp/class.cc   | 22 ++
 gcc/cp/cp-tree.h  |  3 +-
 gcc/cp/tree.cc|  5 ++-
 .../{gcc.dg => c-c++-common}/sso/dump.h   |  0
 .../{gcc.dg => c-c++-common}/sso/init1.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init13.h |  0
 .../{gcc.dg => c-c++-common}/sso/init2.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init3.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init4.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init5.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init6.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init7.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init8.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init9.h  |  0
 .../{gcc.dg => c-c++-common}/sso/p1.c |  0
 .../{gcc.dg => c-c++-common}/sso/p13.c|  1 +
 .../{gcc.dg => c-c++-common}/sso/p2.c |  0
 .../{gcc.dg => c-c++-common}/sso/p3.c |  0
 .../{gcc.dg => c-c++-common}/sso/p4.c |  0
 .../{gcc.dg => c-c++-common}/sso/p5.c |  0
 .../{gcc.dg => 

[PATCH] Add scalar_storage_order support to C++

[naveenh--- via Gcc-patches]

From: Naveen H S 

This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type similar. The code is similar to how it is handled in the C front-end.

2021-04-03  Andrew Pinski   

gcc/ChangeLog:

* c-family/c-attribs.cc (handle_scalar_storage_order_attribute):
Do not reject the C++ cases.
* cp/class.cc (layout_nonempty_base_or_field): Fix the type of
arrays in C++.
* cp/call.cc (reference_binding): Treat reversed field similar as
packed fields.
(build_temp): Likewise.
(convert_like_internal): Emit error code for non binding reversed
endian field.
* cp/cp-tree.h (clk_implicit_rval) : Add clk_reversed.
* cp/cp-tree.c (lvalue_kind) : Handle reverse storage ordered operands.

gcc/testsuite/ChangeLog:

* c-c++-common/sso/dump.h: Move from gcc.dg/sso to c-c++-common/sso.
* c-c++-common/sso/init1.h: Likewise.
* c-c++-common/sso/init13.h: Likewise.
* c-c++-common/sso/init2.h: Likewise.
* c-c++-common/sso/init3.h: Likewise.
* c-c++-common/sso/init4.h: Likewise.
* c-c++-common/sso/init5.h: Likewise.
* c-c++-common/sso/init6.h: Likewise.
* c-c++-common/sso/init7.h: Likewise.
* c-c++-common/sso/init8.h: Likewise.
* c-c++-common/sso/init9.h: Likewise.
* c-c++-common/sso/p1.c: Likewise.
* c-c++-common/sso/p13.c: Likewise.
* c-c++-common/sso/p2.c: Likewise.
* c-c++-common/sso/p3.c: Likewise.
* c-c++-common/sso/p4.c: Likewise.
* c-c++-common/sso/p5.c: Likewise.
* c-c++-common/sso/p6.c: Likewise.
* c-c++-common/sso/p7.c: Likewise.
* c-c++-common/sso/p8.c: Likewise.
* c-c++-common/sso/p9.c: Likewise.
* c-c++-common/sso/q1.c: Likewise.
* c-c++-common/sso/q13.c: Likewise.
* c-c++-common/sso/q2.c: Likewise.
* c-c++-common/sso/q3.c: Likewise.
* c-c++-common/sso/q4.c: Likewise.
* c-c++-common/sso/q5.c: Likewise.
* c-c++-common/sso/q6.c: Likewise.
* c-c++-common/sso/q7.c: Likewise.
* c-c++-common/sso/q8.c: Likewise.
* c-c++-common/sso/q9.c: Likewise.
* c-c++-common/sso/r3.c: Likewise.
* c-c++-common/sso/r5.c: Likewise.
* c-c++-common/sso/r6.c: Likewise.
* c-c++-common/sso/r7.c: Likewise.
* c-c++-common/sso/r8.c: Likewise.
* c-c++-common/sso/s3.c: Likewise.
* c-c++-common/sso/s5.c: Likewise.
* c-c++-common/sso/s6.c: Likewise.
* c-c++-common/sso/s7.c: Likewise.
* c-c++-common/sso/s8.c: Likewise.
* c-c++-common/sso/t1.c: Likewise.
* c-c++-common/sso/t13.c: Likewise.
* c-c++-common/sso/t2.c: Likewise.
* c-c++-common/sso/t3.c: Likewise.
* c-c++-common/sso/t4.c: Likewise.
* c-c++-common/sso/t5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* c-c++-common/sso/t7.c: Likewise.
* c-c++-common/sso/t8.c: Likewise.
* c-c++-common/sso/t9.c: Likewise.
* c-c++-common/sso/u5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* g++.dg/sso/sso.exp: New file.
* g++.dg/sso/auto-1.C: New file.
* g++.dg/sso/auto-2.C: New file.
* g++.dg/sso/auto-3.C: New file.
* g++.dg/sso/template-reference-1.C: New file.
* g++.dg/sso/template-reference-2.C: New file.
* g++.dg/sso/template-reference-3.C: New file.
* g++.dg/sso/template-reference-4.C: New file.
* g++.dg/sso-1.C: Modified.

Co-authored-by: Naveen H S 
---
 gcc/c-family/c-attribs.cc |  2 +-
 gcc/cp/call.cc| 17 ++-
 gcc/cp/class.cc   | 22 ++
 gcc/cp/cp-tree.h  |  3 +-
 gcc/cp/tree.cc|  5 ++-
 .../{gcc.dg => c-c++-common}/sso/dump.h   |  0
 .../{gcc.dg => c-c++-common}/sso/init1.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init13.h |  0
 .../{gcc.dg => c-c++-common}/sso/init2.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init3.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init4.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init5.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init6.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init7.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init8.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init9.h  |  0
 .../{gcc.dg => c-c++-common}/sso/p1.c |  0
 .../{gcc.dg => c-c++-common}/sso/p13.c|  1 +
 .../{gcc.dg => c-c++-common}/sso/p2.c |  0
 .../{gcc.dg => c-c++-common}/sso/p3.c |  0
 .../{gcc.dg => c-c++-common}/sso/p4.c |  0
 .../{gcc.dg => c-c++-common}/sso/p5.c |  0
 .../{gcc.dg => 

[PATCH] Add scalar_storage_order support to C++

[naveenh--- via Gcc-patches]

From: Naveen H S 

This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type similar. The code is similar to how it is handled in the C front-end.

2021-04-03  Andrew Pinski   

gcc/ChangeLog:

* c-family/c-attribs.cc (handle_scalar_storage_order_attribute):
Do not reject the C++ cases.
* cp/class.cc (layout_nonempty_base_or_field): Fix the type of
arrays in C++.
* cp/call.cc (reference_binding): Treat reversed field similar as
packed fields.
(build_temp): Likewise.
(convert_like_internal): Emit error code for non binding reversed
endian field.
* cp/cp-tree.h (clk_implicit_rval) : Add clk_reversed.
* cp/cp-tree.c (lvalue_kind) : Handle reverse storage ordered operands.

gcc/testsuite/ChangeLog:

* c-c++-common/sso/dump.h: Move from gcc.dg/sso to c-c++-common/sso.
* c-c++-common/sso/init1.h: Likewise.
* c-c++-common/sso/init13.h: Likewise.
* c-c++-common/sso/init2.h: Likewise.
* c-c++-common/sso/init3.h: Likewise.
* c-c++-common/sso/init4.h: Likewise.
* c-c++-common/sso/init5.h: Likewise.
* c-c++-common/sso/init6.h: Likewise.
* c-c++-common/sso/init7.h: Likewise.
* c-c++-common/sso/init8.h: Likewise.
* c-c++-common/sso/init9.h: Likewise.
* c-c++-common/sso/p1.c: Likewise.
* c-c++-common/sso/p13.c: Likewise.
* c-c++-common/sso/p2.c: Likewise.
* c-c++-common/sso/p3.c: Likewise.
* c-c++-common/sso/p4.c: Likewise.
* c-c++-common/sso/p5.c: Likewise.
* c-c++-common/sso/p6.c: Likewise.
* c-c++-common/sso/p7.c: Likewise.
* c-c++-common/sso/p8.c: Likewise.
* c-c++-common/sso/p9.c: Likewise.
* c-c++-common/sso/q1.c: Likewise.
* c-c++-common/sso/q13.c: Likewise.
* c-c++-common/sso/q2.c: Likewise.
* c-c++-common/sso/q3.c: Likewise.
* c-c++-common/sso/q4.c: Likewise.
* c-c++-common/sso/q5.c: Likewise.
* c-c++-common/sso/q6.c: Likewise.
* c-c++-common/sso/q7.c: Likewise.
* c-c++-common/sso/q8.c: Likewise.
* c-c++-common/sso/q9.c: Likewise.
* c-c++-common/sso/r3.c: Likewise.
* c-c++-common/sso/r5.c: Likewise.
* c-c++-common/sso/r6.c: Likewise.
* c-c++-common/sso/r7.c: Likewise.
* c-c++-common/sso/r8.c: Likewise.
* c-c++-common/sso/s3.c: Likewise.
* c-c++-common/sso/s5.c: Likewise.
* c-c++-common/sso/s6.c: Likewise.
* c-c++-common/sso/s7.c: Likewise.
* c-c++-common/sso/s8.c: Likewise.
* c-c++-common/sso/t1.c: Likewise.
* c-c++-common/sso/t13.c: Likewise.
* c-c++-common/sso/t2.c: Likewise.
* c-c++-common/sso/t3.c: Likewise.
* c-c++-common/sso/t4.c: Likewise.
* c-c++-common/sso/t5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* c-c++-common/sso/t7.c: Likewise.
* c-c++-common/sso/t8.c: Likewise.
* c-c++-common/sso/t9.c: Likewise.
* c-c++-common/sso/u5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* g++.dg/sso/sso.exp: New file.
* g++.dg/sso/auto-1.C: New file.
* g++.dg/sso/auto-2.C: New file.
* g++.dg/sso/auto-3.C: New file.
* g++.dg/sso/template-reference-1.C: New file.
* g++.dg/sso/template-reference-2.C: New file.
* g++.dg/sso/template-reference-3.C: New file.
* g++.dg/sso/template-reference-4.C: New file.
* g++.dg/sso-1.C: Modified.
---
 gcc/c-family/c-attribs.cc |  2 +-
 gcc/cp/call.cc| 17 ++-
 gcc/cp/class.cc   | 22 ++
 gcc/cp/cp-tree.h  |  3 +-
 gcc/cp/tree.cc|  5 ++-
 .../{gcc.dg => c-c++-common}/sso/dump.h   |  0
 .../{gcc.dg => c-c++-common}/sso/init1.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init13.h |  0
 .../{gcc.dg => c-c++-common}/sso/init2.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init3.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init4.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init5.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init6.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init7.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init8.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init9.h  |  0
 .../{gcc.dg => c-c++-common}/sso/p1.c |  0
 .../{gcc.dg => c-c++-common}/sso/p13.c|  1 +
 .../{gcc.dg => c-c++-common}/sso/p2.c |  0
 .../{gcc.dg => c-c++-common}/sso/p3.c |  0
 .../{gcc.dg => c-c++-common}/sso/p4.c |  0
 .../{gcc.dg => c-c++-common}/sso/p5.c |  0
 .../{gcc.dg => c-c++-common}/sso/p6.c   

[PATCH] Add scalar_storage_order support to C++

[naveenh--- via Gcc-patches]

From: Naveen H S 

This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type similar. The code is similar to how it is handled in the C front-end.

2021-04-03  Andrew Pinski   

Co-authored-by: Naveen H S 

gcc/ChangeLog:

* c-family/c-attribs.cc (handle_scalar_storage_order_attribute):
Do not reject the C++ cases.
* cp/class.cc (layout_nonempty_base_or_field): Fix the type of
arrays in C++.
* cp/call.cc (reference_binding): Treat reversed field similar as
packed fields.
(build_temp): Likewise.
(convert_like_internal): Emit error code for non binding reversed
endian field.
* cp/cp-tree.h (clk_implicit_rval) : Add clk_reversed.
* cp/cp-tree.c (lvalue_kind) : Handle reverse storage ordered operands.

gcc/testsuite/ChangeLog:

* c-c++-common/sso/dump.h: Move from gcc.dg/sso to c-c++-common/sso.
* c-c++-common/sso/init1.h: Likewise.
* c-c++-common/sso/init13.h: Likewise.
* c-c++-common/sso/init2.h: Likewise.
* c-c++-common/sso/init3.h: Likewise.
* c-c++-common/sso/init4.h: Likewise.
* c-c++-common/sso/init5.h: Likewise.
* c-c++-common/sso/init6.h: Likewise.
* c-c++-common/sso/init7.h: Likewise.
* c-c++-common/sso/init8.h: Likewise.
* c-c++-common/sso/init9.h: Likewise.
* c-c++-common/sso/p1.c: Likewise.
* c-c++-common/sso/p13.c: Likewise.
* c-c++-common/sso/p2.c: Likewise.
* c-c++-common/sso/p3.c: Likewise.
* c-c++-common/sso/p4.c: Likewise.
* c-c++-common/sso/p5.c: Likewise.
* c-c++-common/sso/p6.c: Likewise.
* c-c++-common/sso/p7.c: Likewise.
* c-c++-common/sso/p8.c: Likewise.
* c-c++-common/sso/p9.c: Likewise.
* c-c++-common/sso/q1.c: Likewise.
* c-c++-common/sso/q13.c: Likewise.
* c-c++-common/sso/q2.c: Likewise.
* c-c++-common/sso/q3.c: Likewise.
* c-c++-common/sso/q4.c: Likewise.
* c-c++-common/sso/q5.c: Likewise.
* c-c++-common/sso/q6.c: Likewise.
* c-c++-common/sso/q7.c: Likewise.
* c-c++-common/sso/q8.c: Likewise.
* c-c++-common/sso/q9.c: Likewise.
* c-c++-common/sso/r3.c: Likewise.
* c-c++-common/sso/r5.c: Likewise.
* c-c++-common/sso/r6.c: Likewise.
* c-c++-common/sso/r7.c: Likewise.
* c-c++-common/sso/r8.c: Likewise.
* c-c++-common/sso/s3.c: Likewise.
* c-c++-common/sso/s5.c: Likewise.
* c-c++-common/sso/s6.c: Likewise.
* c-c++-common/sso/s7.c: Likewise.
* c-c++-common/sso/s8.c: Likewise.
* c-c++-common/sso/t1.c: Likewise.
* c-c++-common/sso/t13.c: Likewise.
* c-c++-common/sso/t2.c: Likewise.
* c-c++-common/sso/t3.c: Likewise.
* c-c++-common/sso/t4.c: Likewise.
* c-c++-common/sso/t5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* c-c++-common/sso/t7.c: Likewise.
* c-c++-common/sso/t8.c: Likewise.
* c-c++-common/sso/t9.c: Likewise.
* c-c++-common/sso/u5.c: Likewise.
* c-c++-common/sso/t6.c: Likewise.
* g++.dg/sso/sso.exp: New file.
* g++.dg/sso/auto-1.C: New file.
* g++.dg/sso/auto-2.C: New file.
* g++.dg/sso/auto-3.C: New file.
* g++.dg/sso/template-reference-1.C: New file.
* g++.dg/sso/template-reference-2.C: New file.
* g++.dg/sso/template-reference-3.C: New file.
* g++.dg/sso/template-reference-4.C: New file.
* g++.dg/sso-1.C: Modified.
---
 gcc/c-family/c-attribs.cc |  2 +-
 gcc/cp/call.cc| 17 ++-
 gcc/cp/class.cc   | 22 ++
 gcc/cp/cp-tree.h  |  3 +-
 gcc/cp/tree.cc|  5 ++-
 .../{gcc.dg => c-c++-common}/sso/dump.h   |  0
 .../{gcc.dg => c-c++-common}/sso/init1.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init13.h |  0
 .../{gcc.dg => c-c++-common}/sso/init2.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init3.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init4.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init5.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init6.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init7.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init8.h  |  0
 .../{gcc.dg => c-c++-common}/sso/init9.h  |  0
 .../{gcc.dg => c-c++-common}/sso/p1.c |  0
 .../{gcc.dg => c-c++-common}/sso/p13.c|  1 +
 .../{gcc.dg => c-c++-common}/sso/p2.c |  0
 .../{gcc.dg => c-c++-common}/sso/p3.c |  0
 .../{gcc.dg => c-c++-common}/sso/p4.c |  0
 .../{gcc.dg => c-c++-common}/sso/p5.c |  0
 .../{gcc.dg => 

Re: [PATCH] RISC-V: Add autovec sign/zero extension and truncation.

[Robin Dapp via Gcc-patches]

Hi Juzhe,

> use riscv_v_ext_vector_mode_p  instead since riscv_v_ext_mode_p includes 
> tuple modes.
> You should not use tuple modes in related_mode. Tuple modes will be used in 
> array mode target hook and
> used by vec_load_lanes/vec_store_lanes.

Ah, thanks for catching this.  Yes, vector_mode_p is what I intended
obviously.

Regards
 Robin

Re: Re: [PATCH V15] VECT: Add decrement IV iteration loop control by variable amount support

[juzhe.zh...@rivai.ai]

Hi， Richard. Thanks for the comments.

>> if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
>> || !iv_rgc
>> || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>> != rgc->max_nscalars_per_iter * rgc->factor))
>>   {
  >>   /* See whether zero-based IV would ever generate all-false masks
   >> or zero length before wrapping around.  */
   >>  bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, 
rgc);
 
   >>  /* Set up all controls for this group.  */
 >>test_ctrl = vect_set_loop_controls_directly (loop, loop_vinfo,
>>  &preheader_seq,
>>  &header_seq,
>>  loop_cond_gsi, rgc,
>>  niters, niters_skip,
>>  might_wrap_p);
 
   >>  iv_rgc = rgc;
  >> }


Could you tell me why you add:
(iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>> != rgc->max_nscalars_per_iter * rgc->factor) ?

When I have this in the condition, ICE for fail to generate IR:
loop_len_76 = MIN_EXPR ;
  loop_len_66 = MIN_EXPR ;
  loop_len_66 = MIN_EXPR ;
  loop_len_65 = MIN_EXPR <0, 4>;

  _103 = -loop_len_65;

  loop_len_64 = MIN_EXPR <_103, 4>;
  loop_len_63 = _103 - loop_len_64;

When I remove it, it works.

Should I remove it?

Thanks.


juzhe.zh...@rivai.ai
 
From: Richard Sandiford
Date: 2023-05-25 17:02
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V15] VECT: Add decrement IV iteration loop control by 
variable amount support
Thanks, this looks functionally correct to me.  And I agree it handles
the cases that previously needed multiplication.
 
But I think it regresses code quality when no multiplication was needed.
We can now generate duplicate IVs.  Perhaps ivopts would remove the
duplicates, but it might be hard, because of the variable steps.
 
For example, we would generate duplicate IVs for non-SLP code that
operates on multiple vector sizes.  (Can't remembrer what the status
of unpack/truncate patterns is on RVV.)  But it also shows up for SLP.
E.g., I would expect duplicate IVs for:
 
uint16_t x[100];
uint32_t y[200];
 
void f() {
  for (int i = 0; i < 100; i += 2) {
x[i + 0] += 1;
x[i + 1] += 2;
y[i + 0] += 1;
y[i + 1] += 2;
  }
}
 
So I think the call to vect_set_loop_controls_directly does still
need to be inside an "if".  But the "if" condition should be based
on whether the IV step is different.  As discussed yesterday, the
IV step is different if nitems_per_iter, aka:
 
  max_nscalars_per_iter * factor
 
is different.
 
Because of that, I think I was wrong to suggest storing the IV in
loop_vinfo.  It should probably be stored in rgroup_controls instead.
 
Then we could have a structure like this:
 
  rgroup_controls *rgc;
  rgroup_controls *iv_rgc = nullptr;
  ...
  FOR_EACH_VEC_ELT (*controls, i, rgc)
if (!rgc->controls.is_empty ())
  {
...
if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
|| !iv_rgc
|| (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
!= rgc->max_nscalars_per_iter * rgc->factor))
  {
/* See whether zero-based IV would ever generate all-false masks
   or zero length before wrapping around.  */
bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, rgc);
 
/* Set up all controls for this group.  */
test_ctrl = vect_set_loop_controls_directly (loop, loop_vinfo,
 &preheader_seq,
 &header_seq,
 loop_cond_gsi, rgc,
 niters, niters_skip,
 might_wrap_p);
 
iv_rgc = rgc;
  }
 
if (LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
&& rgc->controls.length () > 1)
  {
...your code, using the iv in iv_rgc...;
  }
  }
 
Some other comments:
 
> diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc
> index ff6159e08d5..f9d92ced982 100644
> --- a/gcc/tree-vect-loop-manip.cc
> +++ b/gcc/tree-vect-loop-manip.cc
> @@ -468,6 +468,38 @@ vect_set_loop_controls_directly (class loop *loop, 
> loop_vec_info loop_vinfo,
>gimple_stmt_iterator incr_gsi;
>bool insert_after;
>standard_iv_increment_position (loop, &incr_gsi, &insert_after);
> +  if (LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo))
> +{
> +  /* single rgroup:
 
Instead of "single rgroup", how about:
 
  /* Create an IV that counts down from niters_total and whose step
is the (variable) amount processed in the current iteration:
But please keep the example below as well.
 
> + ...
> + _10 = (unsigned long) count_12(D);
> + ...
> + # ivtmp_9 = PHI 
> + _3

Re: [aarch64] Code-gen for vector initialization involving constants

[Prathamesh Kulkarni via Gcc-patches]

On Thu, 25 May 2023 at 13:04, Richard Sandiford
 wrote:
>
> LGTM, just a couple of comment tweaks:
>
> Prathamesh Kulkarni  writes:
> > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> > index d6fc94015fa..db7ca4c28c3 100644
> > --- a/gcc/config/aarch64/aarch64.cc
> > +++ b/gcc/config/aarch64/aarch64.cc
> > @@ -22332,6 +22332,46 @@ aarch64_unzip_vector_init (machine_mode mode, rtx 
> > vals, bool even_p)
> >return gen_rtx_PARALLEL (new_mode, vec);
> >  }
> >
> > +/* Return true if INSN is a scalar move.  */
>
> s/INSN/SET/
>
> > +
> > +static bool
> > +scalar_move_insn_p (rtx set)
> > +{
> > +  rtx src = SET_SRC (set);
> > +  rtx dest = SET_DEST (set);
> > +  return (is_a (GET_MODE (dest))
> > +   && aarch64_mov_operand (src, GET_MODE (dest)));
> > +}
> > +
> > +/* Similar to seq_cost, but ignore cost for scalar moves.  This function
> > +   is called from aarch64_expand_vector_init.  */
>
> Probably best to drop the second sentence.
>
> OK with those changes, thanks (no need to retest).
Thanks, committed as ea9154dbc8fc86d4c617503ca5e6f02fed3a6a56.

Thanks,
Prathamesh
>
> Richard

Re: [PATCH 1/3] OpenMP: C support for imperfectly-nested loops

[Jakub Jelinek via Gcc-patches]

On Fri, Apr 28, 2023 at 05:22:52PM -0600, Sandra Loosemore wrote:
> OpenMP 5.0 removed the restriction that multiple collapsed loops must
> be perfectly nested, allowing "intervening code" (including nested
> BLOCKs) before or after each nested loop.  In GCC this code is moved
> into the inner loop body by the respective front ends.
> 
> This patch changes the C front end to use recursive descent parsing
> on nested loops within an "omp for" construct, rather than an iterative
> approach, in order to preserve proper nesting of compound statements.
> 
> gcc/c/ChangeLog
>   * c-parser.cc (struct c_parser): Add omp_for_parse_state field.
>   (struct omp_for_parse_data): New.
>   (c_parser_compound_statement_nostart): Special-case nested
>   OMP loops and blocks in intervening code.
>   (c_parser_while_statement): Reject in intervening code.
>   (c_parser_do_statement): Likewise.
>   (c_parser_for_statement): Likewise.
>   (c_parser_postfix_expression_after_primary): Reject calls to OMP
>   runtime routines in intervening code.
>   (c_parser_pragma): Reject OMP pragmas in intervening code.
>   (c_parser_omp_loop_nest): New, split from c_parser_omp_for_loop.
>   (c_parser_omp_for_loop): Rewrite to use recursive descent and
>   generalize handling for intervening code.
> 
> gcc/ChangeLog
>   * omp-api.h: New file.

Why?  Just add those to omp-general.h.

>   * omp-general.cc (omp_runtime_api_procname): New.
>   (omp_runtime_api_call): Moved here from omp-low.cc, and make
>   non-static.
>   * omp-general.h: Include omp-api.h.
>   * omp-low.cc (omp_runtime_api_call): Delete this copy.
> 
> gcc/testsuite/ChangeLog
>   * c-c++-common/goacc/collapse-1.c: Adjust expected error messages.
>   * c-c++-common/goacc/tile-2.c: Likewise.
>   * c-c++-common/gomp/imperfect1.c: New.
>   * c-c++-common/gomp/imperfect2.c: New.
>   * c-c++-common/gomp/imperfect3.c: New.
>   * c-c++-common/gomp/imperfect4.c: New.
>   * c-c++-common/gomp/imperfect5.c: New.
>   * gcc.dg/gomp/collapse-1.c: Adjust expected error messages.
> 
> libgomp/ChangeLog
>   * testsuite/libgomp.c-c++-common/imperfect1.c: New.
>   * testsuite/libgomp.c-c++-common/imperfect2.c: New.
>   * testsuite/libgomp.c-c++-common/imperfect3.c: New.
>   * testsuite/libgomp.c-c++-common/imperfect4.c: New.
>   * testsuite/libgomp.c-c++-common/imperfect5.c: New.
>   * testsuite/libgomp.c-c++-common/imperfect6.c: New.
>   * testsuite/libgomp.c-c++-common/offload-imperfect1.c: New.
>   * testsuite/libgomp.c-c++-common/offload-imperfect2.c: New.
>   * testsuite/libgomp.c-c++-common/offload-imperfect3.c: New.
>   * testsuite/libgomp.c-c++-common/offload-imperfect4.c: New.

If the 3 patches are going to be committed separately (which I think is a
good idea), then the *c-c++-common* tests are a problem, because the tests
will then fail after the C FE part is committed before the C++ FE part is
committed.
For the new tests there are 2 options, one is commit them in the C patch
with /* { dg-do run { target c } } */ instead of just
/* { dg-do run } */ etc. and then in the second patch remove those
" { target c }" parts, or commit them in the second patch only.
For the existing tests with adjustments, do the { target c } vs.
{ target c++ } games and tweak in the second patch.

The offload-imperfect* tests should be called target-imperfect* I think,
for consistency with other tests.

In the gcc/testsuite/c-c++-common/gomp/ tests I miss some coverage for
the boundary cases what is and isn't intervening code.
Before your changes, we were allowing multiple levels of {}s,
so
#pragma omp for ordered(2)
for (int i = 0; i < 64; i++)
  {
{
  {
for (int j = 0; j < 64; j++)
  ;
  }
}
  }
which is valid in 5.0 (but should be tested in the testsuite), but also
empty statements, which when reading the 5.1/5.2 spec don't actually seem to
be valid.
#pragma omp for ordered(2)
for (int i = 0; i < 64; i++)
  {
;
;
;
for (int j = 0; j < 64; j++)
  ;
;
  }
because even the empty statement is I think intervening code according to
the grammar.

Another thing I don't really see covered in the testsuite nor in the code
is if some variable declared in intervening code is then used in the inner
loop's init/cond/incr expressions.  I mean something like:
#pragma omp for collapse(2)
for (int i = 0; i < 64; i++)
  {
int v = (i + 4) * 2;
for (int j = v; j < 64; j++)
  ;
  }
That just ICEs with your patch, we should diagnose it as invalid.
In the canonical loop form requirements the standard requires that the
expressions are loop invariant with the exceptions of specific cases
allowed for non-rectangular loops.  So, above I'm sure that is violated.
Another case would be
#pragma omp for collapse(2)
for (int i = 0; i < 64; i++)
  {
int v = (i + 4);
for (int j = v; j < 64; j++)
  ;
  }
but here it i

Re: [PATCH] [x86] reenable dword MOVE_MAX for better memmove inlining

[Alexandre Oliva via Gcc-patches]

--text follows this line--
On May 24, 2023, Richard Biener  wrote:

> gimple_fold_builtin_memory_op tries to expand the call to a single
> load plus a single store so we can handle overlaps by first loading
> everything to registers and then storing:

*nod*, that's why I figured we could afford to go back to allowing
DImode (with -m32) or TImode (with -m64) even without vector modes: we'd
just use a pair of registers, a single insn, even though not a single
hardware instruction.

> using DImode on i?86 without SSE means we eventually perform two
> loads and two stores which means we need two registers available.

*nod*.  But the alternative is to issue an out-of-line call to memmove,
which would clobber more than 2 registers.  ISTM that inlining such
calls is better, whether optimizing for speed or size.

> So I think if we want to expand this further at the GIMPLE level we
> should still honor MOVE_MAX but eventually emit multiple loads/stores
> honoring the MOVE_MAX_PIECES set of constraints there and avoid
> expanding to sequences where we cannot interleave the loads/stores
> (aka for the memmove case).

But...  don't we already?  If I'm reading the code right, we'll already
issue gimple code to load the whole block into a temporary and then
store it, but current MOVE_MAX won't let us go past 4 bytes on SSE-less
x86.

-- 
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
   Free Software Activist   GNU Toolchain Engineer
Disinformation flourishes because many people care deeply about injustice
but very few check the facts.  Ask me about 

Re: [PATCH] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*

[Alexandre Oliva via Gcc-patches]

On May 25, 2023, "Kewen.Lin"  wrote:

> Thanks for fixing, I tested this on ppc64le and ppc64 {-m64,-m32}
> well.

Thanks!

> I think this is for PR101169, could you add it as PR marker?

Nice, will do!

>> -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } 
>> } } */
>> +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target ilp32 } 
>> } } */

> So both lp64 and ilp32 have the same count, could we merge it and
> remove the selectors?

We could, but...  I thought I wouldn't, since they were different
before, and they're likely to diverge again in the future.  I thought
that combining them might suggest that they ought to be the same, when
we already know that this is not the case.

I'll prepare an alternate patch that combines them.

-- 
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
   Free Software Activist   GNU Toolchain Engineer
Disinformation flourishes because many people care deeply about injustice
but very few check the facts.  Ask me about 

[PATCH v2] RISC-V: Implement autovec abs, vneg, vnot.

[Robin Dapp via Gcc-patches]

Hi,

this patch implements abs2, vneg2 and vnot2 expanders
for integer vector registers and adds tests for them.

v2 is rebased against Juzhe's latest refactoring.

Regards
 Robin

gcc/ChangeLog:

* config/riscv/autovec.md (2): Add vneg/vnot.
(abs2): Add.
* config/riscv/riscv-protos.h (emit_vlmax_masked_insn): Declare.
* config/riscv/riscv-v.cc (emit_vlmax_masked_insn): New
function.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Add unop tests.
* gcc.target/riscv/rvv/autovec/unop/abs-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/abs-template.h: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-template.h: New test.
* gcc.target/riscv/rvv/autovec/unop/vnot-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vnot-template.h: New test.
---
 gcc/config/riscv/autovec.md   | 45 ++-
 gcc/config/riscv/riscv-protos.h   |  1 +
 gcc/config/riscv/riscv-v.cc   | 16 +++
 .../riscv/rvv/autovec/unop/abs-run.c  | 29 
 .../riscv/rvv/autovec/unop/abs-rv32gcv.c  |  7 +++
 .../riscv/rvv/autovec/unop/abs-rv64gcv.c  |  7 +++
 .../riscv/rvv/autovec/unop/abs-template.h | 26 +++
 .../riscv/rvv/autovec/unop/vneg-run.c | 29 
 .../riscv/rvv/autovec/unop/vneg-rv32gcv.c |  6 +++
 .../riscv/rvv/autovec/unop/vneg-rv64gcv.c |  6 +++
 .../riscv/rvv/autovec/unop/vneg-template.h| 18 
 .../riscv/rvv/autovec/unop/vnot-run.c | 43 ++
 .../riscv/rvv/autovec/unop/vnot-rv32gcv.c |  6 +++
 .../riscv/rvv/autovec/unop/vnot-rv64gcv.c |  6 +++
 .../riscv/rvv/autovec/unop/vnot-template.h| 22 +
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp|  2 +
 16 files changed, 268 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-template.h

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 7fe4d94de39..8d26f16d5dc 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -145,7 +145,7 @@ (define_expand "3"
 })
 
 ;; -
-;;  [INT] Binary shifts by scalar.
+;;  [INT] Binary shifts by vector.
 ;; -
 ;; Includes:
 ;; - vsll.vv/vsra.vv/vsrl.vv
@@ -373,3 +373,46 @@ (define_expand "vcondu"
 DONE;
   }
 )
+
+;; =
+;; == Unary arithmetic
+;; =
+
+;; 
---
+;;  [INT] Unary operations
+;; 
---
+;; Includes:
+;; - vneg.v/vnot.v
+;; 
---
+(define_expand "2"
+  [(set (match_operand:VI 0 "register_operand")
+(any_int_unop:VI
+ (match_operand:VI 1 "register_operand")))]
+  "TARGET_VECTOR"
+{
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
+  DONE;
+})
+
+;; 
---
+;; - ABS expansion to vmslt and vneg
+;; 
---
+
+(define_expand "abs2"
+  [(set (match_operand:VI 0 "register_operand"

[ping] RE: [PATCH] stor-layout, aarch64: Express SRA intrinsics with RTL codes

[Kyrylo Tkachov via Gcc-patches]

Ping.
Thanks,
Kyrill

> -Original Message-
> From: Gcc-patches  bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Thursday, May 18, 2023 4:19 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] stor-layout, aarch64: Express SRA intrinsics with RTL codes
> 
> Hi all,
> 
> This patch expresses the intrinsics for the SRA and RSRA instructions with
> standard RTL codes rather than relying on UNSPECs.
> These instructions perform a vector shift right plus accumulate with an
> optional rounding constant addition for the RSRA variant.
> There are a number of interesting points:
> 
> * The scalar-in-SIMD-registers variant for DImode SRA e.g. ssra d0, d1, #N
> is left using the UNSPECs. Expressing it as a DImode plus+shift led to all
> kinds of trouble as it started matching the existing define_insns for
> "add x0, x0, asr #N" instructions and adding the SRA form as an extra
> alternative required a significant amount of deduplication of iterators and
> things still didn't work out well. I decided not to tackle that case in
> this patch. It can be attempted later.
> 
> * For the RSRA variants that add a rounding constant (1 << (shift-1)) the
> addition is notionally performed in a wider mode than the input types so that
> overflow is handled properly. In RTL this can be represented with an
> appropriate
> extend operation followed by a truncate back to the original modes.
> However for 128-bit input modes such as V4SI we don't have appropriate
> modes
> defined for this widening i.e. we'd need a V4DI mode to represent the
> intermediate widened result.  This patch defines such modes for
> V16HI,V8SI,V4DI,V2TI. These will come handy in the future too as we have
> more Advanced SIMD instruction that have similar intermediate widening
> semantics.
> 
> * The above new modes led to a problem with stor-layout.cc. The new modes
> only
> exist for the sake of the RTL optimisers understanding the semantics of the
> instruction but are not indended to be moved to and from register or
> memory,
> assigned to types, used as TYPE_MODE or participate in auto-vectorisation.
> This is expressed in aarch64 by aarch64_classify_vector_mode returning zero
> for these new modes. However, the code in stor-
> layout.cc:
> explicitly doesn't check this when picking a TYPE_MODE due to modes being
> made
> potentially available later through target switching (PR38240).
> This led to these modes being picked as TYPE_MODE for declarations such as:
> typedef int16_t vnx8hi __attribute__((vector_size (32))) when 256-bit
> fixed-length SVE modes are available and vector_type_mode later struggling
> to rectify this.
> This issue is addressed with the new target hook
> TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P that is intended to
> check if a
> vector mode can be used in any legal target attribute configuration of the
> port, as opposed to the existing TARGET_VECTOR_MODE_SUPPORTED_P that
> checks
> only the initial target configuration. This allows a simple adjustment in
> stor-layout.cc that still disqualifies these limited modes early on while
> allowing consideration of modes that can be turned on in the future with
> target attributes.
> 
> Bootstrapped and tested on aarch64-none-linux-gnu.
> Ok for the non-aarch64 parts?
> 
> Thanks,
> Kyrill
> 
> gcc/ChangeLog:
> 
>   * config/aarch64/aarch64-modes.def (V16HI, V8SI, V4DI, V2TI): New
> modes.
>   * config/aarch64/aarch64-protos.h (aarch64_const_vec_rnd_cst_p):
>   Declare prototype.
>   (aarch64_const_vec_rsra_rnd_imm_p): Likewise.
>   * config/aarch64/aarch64-simd.md (*aarch64_simd_sra):
> Rename to...
>   (aarch64_sra_n_insn): ... This.
>   (aarch64_rsra_n_insn): New define_insn.
>   (aarch64_sra_n): New define_expand.
>   (aarch64_rsra_n): Likewise.
>   (aarch64_sra_n): Rename to...
>   (aarch64_sra_ndi): ... This.
>   * config/aarch64/aarch64.cc (aarch64_classify_vector_mode): Add
>   any_target_p argument.
>   (aarch64_extract_vec_duplicate_wide_int): Define.
>   (aarch64_const_vec_rsra_rnd_imm_p): Likewise.
>   (aarch64_const_vec_rnd_cst_p): Likewise.
>   (aarch64_vector_mode_supported_any_target_p): Likewise.
>   (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
>   * config/aarch64/iterators.md (UNSPEC_SRSRA, UNSPEC_URSRA):
> Delete.
>   (VSRA): Adjust for the above.
>   (sur): Likewise.
>   (V2XWIDE): New mode_attr.
>   (vec_or_offset): Likewise.
>   (SHIFTEXTEND): Likewise.
>   * config/aarch64/predicates.md (aarch64_simd_rsra_rnd_imm_vec):
> New
>   predicate.
>   * doc/tm.texi (TARGET_VECTOR_MODE_SUPPORTED_P): Adjust
> description to
>   clarify that it applies to current target options.
>   (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Document.
>   * doc/tm.texi.in: Regenerate.
>   * stor-layout.cc (mode_for_vector): Check
>   vector_mode_supported_any_target_p when iterating through vector
> 

Re: [PATCH V15] VECT: Add decrement IV iteration loop control by variable amount support

[Richard Sandiford via Gcc-patches]

"juzhe.zh...@rivai.ai"  writes:
> Hi， Richard. Thanks for the comments.
>
>>> if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
>>> || !iv_rgc
>>> || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>>> != rgc->max_nscalars_per_iter * rgc->factor))
>>>   {
>   >>   /* See whether zero-based IV would ever generate all-false 
> masks
>>> or zero length before wrapping around.  */
>>>  bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, 
> rgc);
>  
>>>  /* Set up all controls for this group.  */
>  >>test_ctrl = vect_set_loop_controls_directly (loop, loop_vinfo,
> >>  &preheader_seq,
> >>  &header_seq,
> >>  loop_cond_gsi, 
> rgc,
> >>  niters, 
> niters_skip,
> >>  might_wrap_p);
>  
>>>  iv_rgc = rgc;
>   >> }
>
>
> Could you tell me why you add:
> (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>>> != rgc->max_nscalars_per_iter * rgc->factor) ?

The patch creates IVs with the following step:

  gimple_seq_add_stmt (header_seq, gimple_build_assign (step, MIN_EXPR,
index_before_incr,
nitems_step));

If nitems_step is the same for two IVs, those IVs will always be equal.

So having multiple IVs with the same nitems_step is redundant.

nitems_step is calculated as follows:

  unsigned int nitems_per_iter = rgc->max_nscalars_per_iter * rgc->factor;
  ...
  poly_uint64 vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo);
  ...

  if (nitems_per_iter != 1)
{
  ...
  tree iv_factor = build_int_cst (iv_type, nitems_per_iter);
  ...
  nitems_step = gimple_build (preheader_seq, MULT_EXPR, iv_type,
  nitems_step, iv_factor);
  ...
}

so nitems_per_step is equal to:

  rgc->max_nscalars_per_iter * rgc->factor * VF

VF is fixed for a loop, so nitems_step is equal for two different
rgroup_controls if:

  rgc->max_nscalars_per_iter * rgc->factor

is the same for those rgroup_controls.

Please try the example I posted earlier today. I think you'll see that,
without the:

  (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
   != rgc->max_nscalars_per_iter * rgc->factor)

you'll have two IVs with the same step (because their MIN_EXPRs have
the same bound).

Thanks,
Richard

Re: [PATCH 2/3] OpenMP: C++ support for imperfectly-nested loops

[Jakub Jelinek via Gcc-patches]

On Fri, Apr 28, 2023 at 05:22:53PM -0600, Sandra Loosemore wrote:
> OpenMP 5.0 removed the restriction that multiple collapsed loops must
> be perfectly nested, allowing "intervening code" (including nested
> BLOCKs) before or after each nested loop.  In GCC this code is moved
> into the inner loop body by the respective front ends.
> 
> This patch changes the C++ front end to use recursive descent parsing
> on nested loops within an "omp for" construct, rather than an
> iterative approach, in order to preserve proper nesting of compound
> statements.  Preserving cleanups (destructors) for class objects
> declared in intervening code and loop initializers complicates moving
> the former into the body of the loop; this is handled by parsing the
> entire construct before reassembling any of it.

What I wrote about the C patch applies mostly about this patch too,
so I won't review it in detail until the review comments are handled
in both, just would like to note that while C (so far) only supports
#pragma syntax for OpenMP, C++ also supports the attribute syntax
(see e.g. g++.dg/gomp/attrs-*.C testcases).
So, e.g. the no OpenMP constructs in intervening code restriction
applies also to the attribute syntax and needs to be tested for it.
It might work without too many changes because the attribute syntax
is handled by rewriting it essentially into pragma syntax and letting
the parser parse it like that.
Of course, it will matter more for the tile/unroll patch when used together
your patch, when it will need to allow the task generating constructs for
the moreloops cases.

> libgomp/ChangeLog
>   * testsuite/libgomp.c++/imperfect-class-1.C : New.
>   * testsuite/libgomp.c++/imperfect-class-2.C : New.
>   * testsuite/libgomp.c++/imperfect-class-3.C : New.
>   * testsuite/libgomp.c++/imperfect-destructor.C : New.
>   * testsuite/libgomp.c++/imperfect-template-1.C : New.
>   * testsuite/libgomp.c++/imperfect-template-2.C : New.
>   * testsuite/libgomp.c++/imperfect-template-3.C : New.

Formatting, there shouldn't be space before : in ChangeLog entries.

Jakub

[committed] arc: Make TLS Local Dynamic work like Global Dynamic model

[Claudiu Zissulescu via Gcc-patches]

Current ARC's TLS Local Dynamic model is using two anchors to access
data, namely `.tdata` and `.tbss`. This implementation is unnecessary
complicated. However, the TLS Local Dynamic model has better results
using Global Dynamic model and anchors.

gcc/ChangeLog;

* config/arc/arc.cc (arc_call_tls_get_addr): Simplify access using
TLS Local Dynamic.

Signed-off-by: Claudiu Zissulescu 
---
 gcc/config/arc/arc.cc | 24 +---
 1 file changed, 1 insertion(+), 23 deletions(-)

diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index dd012ffa975..fef8a504f77 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -6257,8 +6257,6 @@ arc_call_tls_get_addr (rtx ti)
   return ret;
 }
 
-#define DTPOFF_ZERO_SYM ".tdata"
-
 /* Return a legitimized address for ADDR,
which is a SYMBOL_REF with tls_model MODEL.  */
 
@@ -6267,37 +6265,17 @@ arc_legitimize_tls_address (rtx addr, enum tls_model 
model)
 {
   rtx tmp;
 
-  if (!flag_pic && model == TLS_MODEL_LOCAL_DYNAMIC)
-model = TLS_MODEL_LOCAL_EXEC;
-
-
   /* The TP pointer needs to be set.  */
   gcc_assert (arc_tp_regno != -1);
 
   switch (model)
 {
 case TLS_MODEL_GLOBAL_DYNAMIC:
+case TLS_MODEL_LOCAL_DYNAMIC:
   tmp = gen_reg_rtx (Pmode);
   emit_move_insn (tmp, arc_unspec_offset (addr, UNSPEC_TLS_GD));
   return arc_call_tls_get_addr (tmp);
 
-case TLS_MODEL_LOCAL_DYNAMIC:
-  rtx base;
-  tree decl;
-  const char *base_name;
-
-  decl = SYMBOL_REF_DECL (addr);
-  base_name = DTPOFF_ZERO_SYM;
-  if (decl && bss_initializer_p (decl))
-   base_name = ".tbss";
-
-  base = gen_rtx_SYMBOL_REF (Pmode, base_name);
-  tmp = gen_reg_rtx (Pmode);
-  emit_move_insn (tmp, arc_unspec_offset (base, UNSPEC_TLS_GD));
-  base = arc_call_tls_get_addr (tmp);
-  return gen_rtx_PLUS (Pmode, force_reg (Pmode, base),
-  arc_unspec_offset (addr, UNSPEC_TLS_OFF));
-
 case TLS_MODEL_INITIAL_EXEC:
   addr = arc_unspec_offset (addr, UNSPEC_TLS_IE);
   addr = copy_to_mode_reg (Pmode, gen_const_mem (Pmode, addr));
-- 
2.30.2

Re: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]

[Alex Coplan via Gcc-patches]

Hi Kyrill,

On 23/05/2023 11:14, Kyrylo Tkachov wrote:
> Hi Alex,
> diff --git a/gcc/testsuite/gcc.target/arm/pr109800.c 
> b/gcc/testsuite/gcc.target/arm/pr109800.c
> new file mode 100644
> index 000..71d1ede13dd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/pr109800.c
> @@ -0,0 +1,3 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 
> -mbig-endian -mpure-code" } */
> +double f() { return 5.0; }
> 
> ... The arm testsuite options are kinda hard to get right with all the 
> effective targets and multilibs and such hardcoded abi and march options tend 
> to break in some target.
> I suggest you put this testcase in gcc.target/arm/pure-code and add a 
> dg-skip-if to skip the test if the multilib options specify a different 
> float-abi.

How about this instead:

diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c 
b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
new file mode 100644
index 000..d797b790232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 
-mbig-endian -mpure-code" } */
+double f() { return 5.0; }

Full v2 patch attached.

Thanks,
Alex
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index cbfc4543531..40c4d848238 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -7555,7 +7555,7 @@ (define_expand "movdf"
   && !arm_const_double_rtx (operands[1])
   && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1])))
 {
-  rtx clobreg = gen_reg_rtx (DFmode);
+  rtx clobreg = gen_reg_rtx (DImode);
   emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1],
   clobreg));
   DONE;
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 60e7ba35d8b..03514acc94f 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -2138,7 +2138,7 @@ (define_insn "get_fpscr"
 (define_insn_and_split "no_literal_pool_df_immediate"
   [(set (match_operand:DF 0 "s_register_operand" "=w")
(match_operand:DF 1 "const_double_operand" "F"))
-   (clobber (match_operand:DF 2 "s_register_operand" "=r"))]
+   (clobber (match_operand:DI 2 "s_register_operand" "=r"))]
   "arm_disable_literal_pool
&& TARGET_VFP_BASE
&& !arm_const_double_rtx (operands[1])
@@ -2153,8 +2153,9 @@ (define_insn_and_split "no_literal_pool_df_immediate"
   unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32);
   ival |= (zext_hwi (buf[1 - order], 32) << 32);
   rtx cst = gen_int_mode (ival, DImode);
-  emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst);
-  emit_move_insn (operands[0], operands[2]);
+  emit_move_insn (operands[2], cst);
+  emit_move_insn (operands[0],
+ simplify_gen_subreg (DFmode, operands[2], DImode, 0));
   DONE;
 }
 )
diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c 
b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
new file mode 100644
index 000..d797b790232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 
-mbig-endian -mpure-code" } */
+double f() { return 5.0; }

Re: Re: [PATCH V15] VECT: Add decrement IV iteration loop control by variable amount support

[juzhe.zh...@rivai.ai]

Yeah. I see. Removing it will cause testcase run fail.
Now I found the issue, since you want to store the step in the iv_rgroup.

After I tried, the IR looks correct but create ICE:
0x18c8d41 process_bb
../../../riscv-gcc/gcc/tree-ssa-sccvn.cc:7933
0x18cb6d9 do_rpo_vn_1
../../../riscv-gcc/gcc/tree-ssa-sccvn.cc:8544
0x18cbd35 do_rpo_vn(function*, edge_def*, bitmap_head*, bool, bool, vn_lookup_ki
../../../riscv-gcc/gcc/tree-ssa-sccvn.cc:8646
0x19d42d2 execute
../../../riscv-gcc/gcc/tree-vectorizer.cc:1385

This is the IR:

loop_len_76 = MIN_EXPR ;

  loop_len_66 = MIN_EXPR ;   -> store the step in rgroup instead 
of LOOP_VINFO
  _103 = loop_len_66;  >reuse the MIN VALUE

  loop_len_66 = MIN_EXPR ;

  _104 = _103 - loop_len_66;  ->use MIN - loop_len_66

  loop_len_65 = MIN_EXPR <_104, 4>;
  _105 = _104 - loop_len_65;
  loop_len_64 = MIN_EXPR <_105, 4>;
  loop_len_63 = _105 - loop_len_64;

Since previously I store the "MIN_EXPR ;" in the LOOP_VINFO, not 
the rgroup.

So previously is correct and no ICE:

  loop_len_76 = MIN_EXPR ;

 _103 = MIN_EXPR ;-> Step store in the LOOP_VINFO (S)

  loop_len_66 = MIN_EXPR <_103, 4>; 

  _104 = _103 - loop_len_66;  ->  use MIN - loop_len_66

  loop_len_65 = MIN_EXPR <_104, 4>;
  _105 = _104 - loop_len_65;
  loop_len_64 = MIN_EXPR <_105, 4>;
  loop_len_63 = _105 - loop_len_64;

Could you help me with this ?
Thanks.


juzhe.zh...@rivai.ai
 
From: Richard Sandiford
Date: 2023-05-25 18:19
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V15] VECT: Add decrement IV iteration loop control by 
variable amount support
"juzhe.zh...@rivai.ai"  writes:
> Hi， Richard. Thanks for the comments.
>
>>> if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
>>> || !iv_rgc
>>> || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>>> != rgc->max_nscalars_per_iter * rgc->factor))
>>>   {
>   >>   /* See whether zero-based IV would ever generate all-false 
> masks
>>> or zero length before wrapping around.  */
>>>  bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, 
> rgc);
>  
>>>  /* Set up all controls for this group.  */
>  >>test_ctrl = vect_set_loop_controls_directly (loop, loop_vinfo,
> >>  &preheader_seq,
> >>  &header_seq,
> >>  loop_cond_gsi, 
> rgc,
> >>  niters, 
> niters_skip,
> >>  might_wrap_p);
>  
>>>  iv_rgc = rgc;
>   >> }
>
>
> Could you tell me why you add:
> (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>>> != rgc->max_nscalars_per_iter * rgc->factor) ?
 
The patch creates IVs with the following step:
 
  gimple_seq_add_stmt (header_seq, gimple_build_assign (step, MIN_EXPR,
index_before_incr,
nitems_step));
 
If nitems_step is the same for two IVs, those IVs will always be equal.
 
So having multiple IVs with the same nitems_step is redundant.
 
nitems_step is calculated as follows:
 
  unsigned int nitems_per_iter = rgc->max_nscalars_per_iter * rgc->factor;
  ...
  poly_uint64 vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo);
  ...
 
  if (nitems_per_iter != 1)
{
  ...
  tree iv_factor = build_int_cst (iv_type, nitems_per_iter);
  ...
  nitems_step = gimple_build (preheader_seq, MULT_EXPR, iv_type,
  nitems_step, iv_factor);
  ...
}
 
so nitems_per_step is equal to:
 
  rgc->max_nscalars_per_iter * rgc->factor * VF
 
VF is fixed for a loop, so nitems_step is equal for two different
rgroup_controls if:
 
  rgc->max_nscalars_per_iter * rgc->factor
 
is the same for those rgroup_controls.
 
Please try the example I posted earlier today. I think you'll see that,
without the:
 
  (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
   != rgc->max_nscalars_per_iter * rgc->factor)
 
you'll have two IVs with the same step (because their MIN_EXPRs have
the same bound).
 
Thanks,
Richard
 

Re: [PATCH] doc: clarify semantics of vector bitwise shifts

[Richard Biener via Gcc-patches]

On Thu, May 25, 2023 at 8:50 AM Richard Biener
 wrote:
>
> On Wed, May 24, 2023 at 8:36 PM Alexander Monakov  wrote:
> >
> >
> > On Wed, 24 May 2023, Richard Biener via Gcc-patches wrote:
> >
> > > I’d have to check the ISAs what they actually do here - it of course 
> > > depends
> > > on RTL semantics as well but as you say those are not strictly defined 
> > > here
> > > either.

Btw, it was just noted on IRC that VSX (and maybe altivec as well)
does not adhere to this and use
just 3 bits from the shift operand for bytes and 4 for half-words.

> > Plus, we can add the following executable test to the testsuite:
>
> Yeah, that's probably a good idea.  I think your documentation change
> with the added sentence about the truncation is OK.  Note we have
>
> /* Shift operations for shift and rotate.
>Shift means logical shift if done on an
>unsigned type, arithmetic shift if done on a signed type.
>The second operand is the number of bits to
>shift by; it need not be the same type as the first operand and result.
>Note that the result is undefined if the second operand is larger
>than or equal to the first operand's type size.
>
>The first operand of a shift can have either an integer or a
>(non-integer) fixed-point type.  We follow the ISO/IEC TR 18037:2004
>semantics for the latter.
>
>Rotates are defined for integer types only.  */
> DEFTREECODE (LSHIFT_EXPR, "lshift_expr", tcc_binary, 2)
>
> in tree.def which implies short << 24 is undefined behavior (similar
> wording in generic.texi).  The rtl docs say nothing about behavior
> but I think the semantics should carry over.  That works for x86
> even for scalar instructions working on GPRs (masking is applied
> but fixed to 5 or 6 bits even for QImode or HImode shifts).
>
> Note that when we make these shifts well-defined there's
> also arithmetic on signed types smaller than int (which again
> doesn't exist in C) where overflow invokes undefined behavior
> in the middle-end.  Unless we want to change that as well
> this is somewhat inconsistent then.
>
> There's also the issue that C 'int' is defined by INT_TYPE_SIZE
> and thus target dependent which makes what is undefined and
> what not target dependent.
>
> Richard.
>
> > #include 
> >
> > #define CHECK(TYPE, WIDTH, OP, COUNT, INVERT) \
> > { \
> > typedef TYPE vec __attribute__((vector_size(WIDTH))); \
> >   \
> > static volatile vec zero; \
> > vec tmp = (zero-2) OP (COUNT);\
> > vec ref = INVERT zero;\
> > if (__builtin_memcmp(&tmp, &ref, sizeof tmp)) \
> > __builtin_abort();\
> > }
> >
> > int main(void)
> > {
> > CHECK( uint8_t, 16, <<, 8,  )
> > CHECK( uint8_t, 16, <<, 31, )
> > CHECK( uint8_t, 16, >>, 8,  )
> > CHECK( uint8_t, 16, >>, 31, )
> > CHECK(  int8_t, 16, <<, 8,  )
> > CHECK(  int8_t, 16, <<, 31, )
> > CHECK(  int8_t, 16, >>, 8,  ~)
> > CHECK(  int8_t, 16, >>, 31, ~)
> > CHECK(uint16_t, 16, <<, 16, )
> > CHECK(uint16_t, 16, <<, 31, )
> > CHECK(uint16_t, 16, >>, 16, )
> > CHECK(uint16_t, 16, >>, 31, )
> > CHECK( int16_t, 16, <<, 16, )
> > CHECK( int16_t, 16, <<, 31, )
> > CHECK( int16_t, 16, >>, 16, ~)
> > CHECK( int16_t, 16, >>, 31, ~)
> > // Per-lane-variable shifts:
> > CHECK( uint8_t, 16, <<, zero+8,  )
> > CHECK( uint8_t, 16, <<, zero+31, )
> > CHECK( uint8_t, 16, >>, zero+8,  )
> > CHECK( uint8_t, 16, >>, zero+31, )
> > CHECK(  int8_t, 16, <<, zero+8,  )
> > CHECK(  int8_t, 16, <<, zero+31, )
> > CHECK(  int8_t, 16, >>, zero+8,  ~)
> > CHECK(  int8_t, 16, >>, zero+31, ~)
> > CHECK(uint16_t, 16, <<, zero+16, )
> > CHECK(uint16_t, 16, <<, zero+31, )
> > CHECK(uint16_t, 16, >>, zero+16, )
> > CHECK(uint16_t, 16, >>, zero+31, )
> > CHECK( int16_t, 16, <<, zero+16, )
> > CHECK( int16_t, 16, <<, zero+31, )
> > CHECK( int16_t, 16, >>, zero+16, ~)
> > CHECK( int16_t, 16, >>, zero+31, ~)
> >
> > // Repeat for WIDTH=32 and WIDTH=64
> > }
> >
> > Alexander

RE: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]

[Kyrylo Tkachov via Gcc-patches]

> -Original Message-
> From: Alex Coplan 
> Sent: Thursday, May 25, 2023 11:26 AM
> To: Kyrylo Tkachov 
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
> 
> Subject: Re: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]
> 
> Hi Kyrill,
> 
> On 23/05/2023 11:14, Kyrylo Tkachov wrote:
> > Hi Alex,
> > diff --git a/gcc/testsuite/gcc.target/arm/pr109800.c
> b/gcc/testsuite/gcc.target/arm/pr109800.c
> > new file mode 100644
> > index 000..71d1ede13dd
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/arm/pr109800.c
> > @@ -0,0 +1,3 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-
> d16 -mbig-endian -mpure-code" } */
> > +double f() { return 5.0; }
> >
> > ... The arm testsuite options are kinda hard to get right with all the 
> > effective
> targets and multilibs and such hardcoded abi and march options tend to
> break in some target.
> > I suggest you put this testcase in gcc.target/arm/pure-code and add a dg-
> skip-if to skip the test if the multilib options specify a different 
> float-abi.
> 
> How about this instead:
> 
> diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
> b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
> new file mode 100644
> index 000..d797b790232
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_hard_ok } */
> +/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -
> mbig-endian -mpure-code" } */
> +double f() { return 5.0; }
> 
> Full v2 patch attached.

Thanks, looks better but I think you'll still want to have a dg-skip-if to 
avoid explicit -mfloat-abi=soft and -mfloat-abi=softfp in the multilib options. 
You can grep in that test directory for examples
Kyrill

> 
> Thanks,
> Alex

Re: [PATCH v2] RISC-V: Implement autovec abs, vneg, vnot.

[juzhe.zh...@rivai.ai]

+(define_expand "abs2"
+  [(set (match_operand:VI 0 "register_operand")
+(match_operand:VI 1 "register_operand"))]
+  "TARGET_VECTOR"
+{
+  rtx zero = gen_const_vec_duplicate (mode, GEN_INT (0));
+  machine_mode mask_mode = riscv_vector::get_mask_mode (mode).require ();
+  rtx mask = gen_reg_rtx (mask_mode);
+  riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero);
+
+  /* For masking we need two more operands than a regular unop, the mask
+ itself and the maskoff operand.  */
+  rtx ops[] = {operands[0], mask, operands[1], operands[1]};
+  riscv_vector::emit_vlmax_masked_insn (code_for_pred (NEG, mode),
+ riscv_vector::RVV_UNOP + 2, ops);
+  DONE;
+})

+/* This function emits a masked instruction.  */
+void
+emit_vlmax_masked_insn (unsigned icode, int op_num, rtx *ops)
+{
+  machine_mode dest_mode = GET_MODE (ops[0]);
+  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
+  insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true,
+/*FULLY_UNMASKED_P*/ false,
+/*USE_REAL_MERGE_P*/ true,
+/*HAS_AVL_P*/ true,
+/*VLMAX_P*/ true, dest_mode, mask_mode);
+  e.set_policy (TAIL_ANY);
+  e.set_policy (MASK_ANY);
+  e.emit_insn ((enum insn_code) icode, ops);
+}

I think it's logically incorrect.  For ABS, you want:

operands[0] = operads[1] > 0 ? operands[1] :  (-operands[1])
So you should do this following sequence:

vmslt v0,v1,0
vneg v1,v1v0.t (should use Mask undisturbed)

Here I see you set:
e.set_policy (MASK_ANY); which is incorrect.
You should use e.set_policy (MASK_UNDISTURBED); instead.

Your testcases fail to catch this issue (you should create a testcase to catch 
this bug with this patch implementation.)

Besides, 
riscv_vector::RVV_UNOP + 2, ops);

You should not use RVV_UNOP+2. Instead, you should add an enum call RVV_UNOP_MU 
and replace it.

Thanks.


juzhe.zh...@rivai.ai
 
From: Robin Dapp
Date: 2023-05-25 18:08
To: gcc-patches; Kito Cheng; palmer; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH v2] RISC-V: Implement autovec abs, vneg, vnot.
Hi,
 
this patch implements abs2, vneg2 and vnot2 expanders
for integer vector registers and adds tests for them.
 
v2 is rebased against Juzhe's latest refactoring.
 
Regards
Robin
 
gcc/ChangeLog:
 
* config/riscv/autovec.md (2): Add vneg/vnot.
(abs2): Add.
* config/riscv/riscv-protos.h (emit_vlmax_masked_insn): Declare.
* config/riscv/riscv-v.cc (emit_vlmax_masked_insn): New
function.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/rvv.exp: Add unop tests.
* gcc.target/riscv/rvv/autovec/unop/abs-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/abs-template.h: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-template.h: New test.
* gcc.target/riscv/rvv/autovec/unop/vnot-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vnot-template.h: New test.
---
gcc/config/riscv/autovec.md   | 45 ++-
gcc/config/riscv/riscv-protos.h   |  1 +
gcc/config/riscv/riscv-v.cc   | 16 +++
.../riscv/rvv/autovec/unop/abs-run.c  | 29 
.../riscv/rvv/autovec/unop/abs-rv32gcv.c  |  7 +++
.../riscv/rvv/autovec/unop/abs-rv64gcv.c  |  7 +++
.../riscv/rvv/autovec/unop/abs-template.h | 26 +++
.../riscv/rvv/autovec/unop/vneg-run.c | 29 
.../riscv/rvv/autovec/unop/vneg-rv32gcv.c |  6 +++
.../riscv/rvv/autovec/unop/vneg-rv64gcv.c |  6 +++
.../riscv/rvv/autovec/unop/vneg-template.h| 18 
.../riscv/rvv/autovec/unop/vnot-run.c | 43 ++
.../riscv/rvv/autovec/unop/vnot-rv32gcv.c |  6 +++
.../riscv/rvv/autovec/unop/vnot-rv64gcv.c |  6 +++
.../riscv/rvv/autovec/unop/vnot-template.h| 22 +
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp|  2 +
16 files changed, 268 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
create m

Re: [PATCH] [x86] reenable dword MOVE_MAX for better memmove inlining

[Richard Biener via Gcc-patches]

On Thu, May 25, 2023 at 12:01 PM Alexandre Oliva  wrote:
>
> --text follows this line--
> On May 24, 2023, Richard Biener  wrote:
>
> > gimple_fold_builtin_memory_op tries to expand the call to a single
> > load plus a single store so we can handle overlaps by first loading
> > everything to registers and then storing:
>
> *nod*, that's why I figured we could afford to go back to allowing
> DImode (with -m32) or TImode (with -m64) even without vector modes: we'd
> just use a pair of registers, a single insn, even though not a single
> hardware instruction.
>
> > using DImode on i?86 without SSE means we eventually perform two
> > loads and two stores which means we need two registers available.
>
> *nod*.  But the alternative is to issue an out-of-line call to memmove,
> which would clobber more than 2 registers.  ISTM that inlining such
> calls is better, whether optimizing for speed or size.
>
> > So I think if we want to expand this further at the GIMPLE level we
> > should still honor MOVE_MAX but eventually emit multiple loads/stores
> > honoring the MOVE_MAX_PIECES set of constraints there and avoid
> > expanding to sequences where we cannot interleave the loads/stores
> > (aka for the memmove case).
>
> But...  don't we already?  If I'm reading the code right, we'll already
> issue gimple code to load the whole block into a temporary and then
> store it, but current MOVE_MAX won't let us go past 4 bytes on SSE-less
> x86.

I mean we could do what RTL expansion would do later and do
by-pieces, thus emit multiple loads/stores but not n loads and then
n stores but interleaved.

Richard.

>
> --
> Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
>Free Software Activist   GNU Toolchain Engineer
> Disinformation flourishes because many people care deeply about injustice
> but very few check the facts.  Ask me about 

[PATCH] target/109955 - handle pattern generated COND_EXPR without vcond

[Richard Biener via Gcc-patches]

The following properly handles pattern matching generated COND_EXPRs
which can still have embedded compares in vectorizable_condition
which will always code generate the masked vector variant.  We
were requiring vcond with embedded comparisons instead of also
allowing (as code generated) split compare and VEC_COND_EXPR.

This fixes some of the fallout when removing vcond{,u,eq} expanders
from the x86 backend.

Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.

PR target/109955
* tree-vect-stmts.cc (vectorizable_condition): For
embedded comparisons also handle the case when the target
only provides vec_cmp and vcond_mask.
---
 gcc/tree-vect-stmts.cc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 127b987cd62..bd3b07a3aa1 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -10836,7 +10836,12 @@ vectorizable_condition (vec_info *vinfo,
   if (reduction_type == EXTRACT_LAST_REDUCTION)
/* Count one reduction-like operation per vector.  */
kind = vec_to_scalar;
-  else if (!expand_vec_cond_expr_p (vectype, comp_vectype, cond_code))
+  else if (!expand_vec_cond_expr_p (vectype, comp_vectype, cond_code)
+  && (masked
+  || (!expand_vec_cmp_expr_p (comp_vectype, vec_cmp_type,
+  cond_code)
+  || !expand_vec_cond_expr_p (vectype, vec_cmp_type,
+  ERROR_MARK
return false;
 
   if (slp_node
-- 
2.35.3

Re: Re: [PATCH V15] VECT: Add decrement IV iteration loop control by variable amount support

[Richard Biener via Gcc-patches]

On Thu, 25 May 2023, juzhe.zh...@rivai.ai wrote:

> Yeah. I see. Removing it will cause testcase run fail.
> Now I found the issue, since you want to store the step in the iv_rgroup.
> 
> After I tried, the IR looks correct but create ICE:
> 0x18c8d41 process_bb
> ../../../riscv-gcc/gcc/tree-ssa-sccvn.cc:7933
> 0x18cb6d9 do_rpo_vn_1
> ../../../riscv-gcc/gcc/tree-ssa-sccvn.cc:8544
> 0x18cbd35 do_rpo_vn(function*, edge_def*, bitmap_head*, bool, bool, 
> vn_lookup_ki
> ../../../riscv-gcc/gcc/tree-ssa-sccvn.cc:8646
> 0x19d42d2 execute
> ../../../riscv-gcc/gcc/tree-vectorizer.cc:1385
> 
> This is the IR:
> 
> loop_len_76 = MIN_EXPR ;
> 
>   loop_len_66 = MIN_EXPR ;   -> store the step in rgroup 
> instead of LOOP_VINFO
>   _103 = loop_len_66;  >reuse the MIN VALUE
> 
>   loop_len_66 = MIN_EXPR ;

you have two defs of loop_len_66, that's not allowed

> 
>   _104 = _103 - loop_len_66;  ->use MIN - loop_len_66
> 
>   loop_len_65 = MIN_EXPR <_104, 4>;
>   _105 = _104 - loop_len_65;
>   loop_len_64 = MIN_EXPR <_105, 4>;
>   loop_len_63 = _105 - loop_len_64;
> 
> Since previously I store the "MIN_EXPR ;" in the LOOP_VINFO, 
> not the rgroup.
> 
> So previously is correct and no ICE:
> 
>   loop_len_76 = MIN_EXPR ;
> 
>  _103 = MIN_EXPR ;-> Step store in the LOOP_VINFO (S)
> 
>   loop_len_66 = MIN_EXPR <_103, 4>; 
> 
>   _104 = _103 - loop_len_66;  ->  use MIN - loop_len_66
> 
>   loop_len_65 = MIN_EXPR <_104, 4>;
>   _105 = _104 - loop_len_65;
>   loop_len_64 = MIN_EXPR <_105, 4>;
>   loop_len_63 = _105 - loop_len_64;
> 
> Could you help me with this ?
> Thanks.
> 
> 
> juzhe.zh...@rivai.ai
>  
> From: Richard Sandiford
> Date: 2023-05-25 18:19
> To: juzhe.zhong\@rivai.ai
> CC: gcc-patches; rguenther
> Subject: Re: [PATCH V15] VECT: Add decrement IV iteration loop control by 
> variable amount support
> "juzhe.zh...@rivai.ai"  writes:
> > Hi? Richard. Thanks for the comments.
> >
> >>> if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
> >>> || !iv_rgc
> >>> || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
> >>> != rgc->max_nscalars_per_iter * rgc->factor))
> >>>   {
> >   >>   /* See whether zero-based IV would ever generate all-false 
> > masks
> >>> or zero length before wrapping around.  */
> >>>  bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, 
> > rgc);
> >  
> >>>  /* Set up all controls for this group.  */
> >  >>test_ctrl = vect_set_loop_controls_directly (loop, 
> > loop_vinfo,
> > >>  &preheader_seq,
> > >>  &header_seq,
> > >>  loop_cond_gsi, 
> > rgc,
> > >>  niters, 
> > niters_skip,
> > >>  might_wrap_p);
> >  
> >>>  iv_rgc = rgc;
> >   >> }
> >
> >
> > Could you tell me why you add:
> > (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
> >>> != rgc->max_nscalars_per_iter * rgc->factor) ?
>  
> The patch creates IVs with the following step:
>  
>   gimple_seq_add_stmt (header_seq, gimple_build_assign (step, MIN_EXPR,
> index_before_incr,
> nitems_step));
>  
> If nitems_step is the same for two IVs, those IVs will always be equal.
>  
> So having multiple IVs with the same nitems_step is redundant.
>  
> nitems_step is calculated as follows:
>  
>   unsigned int nitems_per_iter = rgc->max_nscalars_per_iter * rgc->factor;
>   ...
>   poly_uint64 vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo);
>   ...
>  
>   if (nitems_per_iter != 1)
> {
>   ...
>   tree iv_factor = build_int_cst (iv_type, nitems_per_iter);
>   ...
>   nitems_step = gimple_build (preheader_seq, MULT_EXPR, iv_type,
>   nitems_step, iv_factor);
>   ...
> }
>  
> so nitems_per_step is equal to:
>  
>   rgc->max_nscalars_per_iter * rgc->factor * VF
>  
> VF is fixed for a loop, so nitems_step is equal for two different
> rgroup_controls if:
>  
>   rgc->max_nscalars_per_iter * rgc->factor
>  
> is the same for those rgroup_controls.
>  
> Please try the example I posted earlier today. I think you'll see that,
> without the:
>  
>   (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>!= rgc->max_nscalars_per_iter * rgc->factor)
>  
> you'll have two IVs with the same step (because their MIN_EXPRs have
> the same bound).
>  
> Thanks,
> Richard
>  
> 

-- 
Richard Biener 
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)

Re: [PATCH] [x86] reenable dword MOVE_MAX for better memmove inlining

[Alexandre Oliva via Gcc-patches]

On May 25, 2023, Richard Biener  wrote:

> I mean we could do what RTL expansion would do later and do
> by-pieces, thus emit multiple loads/stores but not n loads and then
> n stores but interleaved.

That wouldn't help e.g. gcc.dg/memcpy-6.c's fold_move_8, because
MOVE_MAX and MOVE_MAX_PIECES currently limits inline expansion to 4
bytes on x86 without SSE, both in gimple and RTL, and interleaved loads
and stores wouldn't help with memmove.  We can't fix that by changing
code that uses MOVE_MAX and/or MOVE_MAX_PIECES, when these limits are
set too low.

I'm also concerned that doing more such expansion in gimple folding
would be reversed in later gimple passes.  That's good in that it would
enable efficient rtl movmem/cpymem instruction selection, but it's not
clear to me that there would generally be benefits to such early
open-coding in gimple.

-- 
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
   Free Software Activist   GNU Toolchain Engineer
Disinformation flourishes because many people care deeply about injustice
but very few check the facts.  Ask me about 

Re: [PATCH] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*

[Segher Boessenkool]

Hi!

On Thu, May 25, 2023 at 07:05:55AM -0300, Alexandre Oliva wrote:
> On May 25, 2023, "Kewen.Lin"  wrote:
> > So both lp64 and ilp32 have the same count, could we merge it and
> > remove the selectors?
> 
> We could, but...  I thought I wouldn't, since they were different
> before, and they're likely to diverge again in the future.  I thought
> that combining them might suggest that they ought to be the same, when
> we already know that this is not the case.
> 
> I'll prepare an alternate patch that combines them.

Fwiw, updating the insn counts blindly like this has very small value on
the one hand, and negative value on the other.  In total, negative
value.

If it is not possible to keep these tests up-to-date easily the test
should be improved.  If tests regressed otoh we should ***not*** paper
over that with patches like this, but investigate what happened instead:
such regressions are *real*.

So which is it here?  I am assuming it is a not-to-well written testcase
without all the necessary noipa attrs, and/or putting more than one
thing to test per function directly.  Insn counts then shift easily if
the compiler decides to factor (CSE etc.) your code differently, but
that is a testcase artifact then, not something we want to adjust counts
for all of the time.

It is feasible to do these insn count things only for trivial tiny
snippets.  Everything bigger will regress all of the time, no one will
look at it properly, and instead people will just do blind "update
counts" patches like this :-/  *Good* insn count tests are quite
valuable, but harder to write.  But maintenance costs noticably bigger
than zero for a testcase are not good, how many testcases do we run in
the testsuite?

So, can we fix the underlying problem here please?

Thanks,


Segher

Re: [PATCH] [x86] reenable dword MOVE_MAX for better memmove inlining

[Richard Biener via Gcc-patches]

On Thu, May 25, 2023 at 1:10 PM Alexandre Oliva  wrote:
>
> On May 25, 2023, Richard Biener  wrote:
>
> > I mean we could do what RTL expansion would do later and do
> > by-pieces, thus emit multiple loads/stores but not n loads and then
> > n stores but interleaved.
>
> That wouldn't help e.g. gcc.dg/memcpy-6.c's fold_move_8, because
> MOVE_MAX and MOVE_MAX_PIECES currently limits inline expansion to 4
> bytes on x86 without SSE, both in gimple and RTL, and interleaved loads
> and stores wouldn't help with memmove.  We can't fix that by changing
> code that uses MOVE_MAX and/or MOVE_MAX_PIECES, when these limits are
> set too low.
>
> I'm also concerned that doing more such expansion in gimple folding
> would be reversed in later gimple passes.  That's good in that it would
> enable efficient rtl movmem/cpymem instruction selection, but it's not
> clear to me that there would generally be benefits to such early
> open-coding in gimple.

Btw, there was a short period where the MOVE_MAX limit was restricted
but that had fallout and we've reverted since then.

Richard.

> --
> Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
>Free Software Activist   GNU Toolchain Engineer
> Disinformation flourishes because many people care deeply about injustice
> but very few check the facts.  Ask me about 

[PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support

[juzhe . zhong]

From: Ju-Zhe Zhong 

This patch is supporting decrement IV by following the flow designed by Richard:

(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.

(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rgc has 1 control, this step is the SSA name created for that control.
Otherwise the step is a fresh SSA name, as in your patch.

(3) vect_set_loop_controls_directly stores this step somewhere for later
use, probably in LOOP_VINFO.  Let's use "S" to refer to this stored step.

(4) After the vect_set_loop_controls_directly call above, and outside
the "if" statement that now contains vect_set_loop_controls_directly,
check whether rgc->controls.length () > 1.  If so, use
vect_adjust_loop_lens_control to set the controls based on S.

Then the only caller of vect_adjust_loop_lens_control is
vect_set_loop_condition_partial_vectors.  And the starting
step for vect_adjust_loop_lens_control is always S.

This patch has well tested for single-rgroup and multiple-rgroup (SLP) and
passed all testcase in RISC-V port.

gcc/ChangeLog:

* tree-vect-loop-manip.cc (vect_adjust_loop_lens_control): New function.
(vect_set_loop_controls_directly): Add decrement IV support.
(vect_set_loop_condition_partial_vectors): Ditto.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): New variable.
* tree-vectorizer.h (LOOP_VINFO_USING_DECREMENTING_IV_P): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: New 
test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: New 
test.

---
 .../rvv/autovec/partial/multiple_rgroup-3.c   | 288 ++
 .../rvv/autovec/partial/multiple_rgroup-4.c   |  75 +
 .../autovec/partial/multiple_rgroup_run-3.c   |  36 +++
 .../autovec/partial/multiple_rgroup_run-4.c   |  15 +
 gcc/tree-vect-loop-manip.cc   | 135 +++-
 gcc/tree-vect-loop.cc |  12 +
 gcc/tree-vectorizer.h |   8 +
 7 files changed, 557 insertions(+), 12 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
new file mode 100644
index 000..9579749c285
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
@@ -0,0 +1,288 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax" } */
+
+#include 
+
+void __attribute__ ((noinline, noclone))
+f0 (int8_t *__restrict x, int16_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i += 4, j += 8)
+{
+  x[i + 0] += 1;
+  x[i + 1] += 2;
+  x[i + 2] += 3;
+  x[i + 3] += 4;
+  y[j + 0] += 1;
+  y[j + 1] += 2;
+  y[j + 2] += 3;
+  y[j + 3] += 4;
+  y[j + 4] += 5;
+  y[j + 5] += 6;
+  y[j + 6] += 7;
+  y[j + 7] += 8;
+}
+}
+
+void __attribute__ ((optimize (0)))
+f0_init (int8_t *__restrict x, int8_t *__restrict x2, int16_t *__restrict y,
+int16_t *__restrict y2, int n)
+{
+  for (int i = 0, j = 0; i < n; i += 4, j += 8)
+{
+  x[i + 0] = i % 120;
+  x[i + 1] = i % 78;
+  x[i + 2] = i % 55;
+  x[i + 3] = i % 27;
+  y[j + 0] = j % 33;
+  y[j + 1] = j % 44;
+  y[j + 2] = j % 66;
+  y[j + 3] = j % 88;
+  y[j + 4] = j % 99;
+  y[j + 5] = j % 39;
+  y[j + 6] = j % 49;
+  y[j + 7] = j % 101;
+
+  x2[i + 0] = i % 120;
+  x2[i + 1] = i % 78;
+  x2[i + 2] = i % 55;
+  x2[i + 3] = i % 27;
+  y2[j + 0] = j % 33;
+  y2[j + 1] = j % 44;
+  y2[j + 2] = j % 66;
+  y2[j + 3] = j % 88;
+  y2[j + 4] = j % 99;
+  y2[j + 5] = j % 39;
+  y2[j + 6] = j % 49;
+  y2[j + 7] = j % 101;
+}
+}
+
+void __attribute__ ((optimize (0)))
+f0_golden (int8_t *__restrict x, int16_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i += 4, j += 8)
+{
+  x[i + 0] += 1;
+  x[i + 1] += 2;
+  x[i + 2] += 3;
+  x[i + 3] += 4;
+  y[j + 0] += 1;
+  y[j + 1] += 2;
+  y[j + 2] += 3;
+  y[j + 3] += 4;
+  y[j + 4] += 5;
+  y[j + 5] += 6;
+  y[j + 6] += 7;
+  y[j + 7] += 8;
+}
+}
+
+void __attribute__ ((optimize (0)))
+f0_check (int8_t *__restrict x, int8_t *__restrict x2, int16_t *

Re: Re: [PATCH V15] VECT: Add decrement IV iteration loop control by variable amount support

[钟居哲]

Thank you so much for your patience.
Could you take a look at V16 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619652.html 
whether it is ok for trunk ?

Thanks.


juzhe.zh...@rivai.ai
 
From: Richard Sandiford
Date: 2023-05-25 18:19
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V15] VECT: Add decrement IV iteration loop control by 
variable amount support
"juzhe.zh...@rivai.ai"  writes:
> Hi， Richard. Thanks for the comments.
>
>>> if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
>>> || !iv_rgc
>>> || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>>> != rgc->max_nscalars_per_iter * rgc->factor))
>>>   {
>   >>   /* See whether zero-based IV would ever generate all-false 
> masks
>>> or zero length before wrapping around.  */
>>>  bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, 
> rgc);
>  
>>>  /* Set up all controls for this group.  */
>  >>test_ctrl = vect_set_loop_controls_directly (loop, loop_vinfo,
> >>  &preheader_seq,
> >>  &header_seq,
> >>  loop_cond_gsi, 
> rgc,
> >>  niters, 
> niters_skip,
> >>  might_wrap_p);
>  
>>>  iv_rgc = rgc;
>   >> }
>
>
> Could you tell me why you add:
> (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>>> != rgc->max_nscalars_per_iter * rgc->factor) ?
 
The patch creates IVs with the following step:
 
  gimple_seq_add_stmt (header_seq, gimple_build_assign (step, MIN_EXPR,
index_before_incr,
nitems_step));
 
If nitems_step is the same for two IVs, those IVs will always be equal.
 
So having multiple IVs with the same nitems_step is redundant.
 
nitems_step is calculated as follows:
 
  unsigned int nitems_per_iter = rgc->max_nscalars_per_iter * rgc->factor;
  ...
  poly_uint64 vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo);
  ...
 
  if (nitems_per_iter != 1)
{
  ...
  tree iv_factor = build_int_cst (iv_type, nitems_per_iter);
  ...
  nitems_step = gimple_build (preheader_seq, MULT_EXPR, iv_type,
  nitems_step, iv_factor);
  ...
}
 
so nitems_per_step is equal to:
 
  rgc->max_nscalars_per_iter * rgc->factor * VF
 
VF is fixed for a loop, so nitems_step is equal for two different
rgroup_controls if:
 
  rgc->max_nscalars_per_iter * rgc->factor
 
is the same for those rgroup_controls.
 
Please try the example I posted earlier today. I think you'll see that,
without the:
 
  (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
   != rgc->max_nscalars_per_iter * rgc->factor)
 
you'll have two IVs with the same step (because their MIN_EXPRs have
the same bound).
 
Thanks,
Richard
 

RE: [PATCH] RISC-V: Add autovec sign/zero extension and truncation.

[Li, Pan2 via Gcc-patches]

The zero-scratch-regs-3.c comes from below PATCH. 

https://gcc.gnu.org/pipermail/gcc-patches/2023-April/615494.html

Hi Yanzhang,

Could you please help to double check the issue reported by Robin? Aka: " 
zero-scratch-regs-3.c seems to FAIL in vcondu but that already happens on 
trunk."

Thanks a lot.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Robin Dapp via Gcc-patches
Sent: Thursday, May 25, 2023 5:03 PM
To: gcc-patches ; Kito Cheng ; 
palmer ; juzhe.zh...@rivai.ai; jeffreyalaw 

Cc: rdapp@gmail.com
Subject: [PATCH] RISC-V: Add autovec sign/zero extension and truncation.

Hi,

this patch implements the autovec expanders for sign and zero extension 
patterns as well as the accompanying truncations.  In order to use them 
additional mode_attr iterators as well as vectorizer hooks are required.
Using these hooks we can e.g. vectorize with VNx4QImode as base mode and extend 
VNx4SI to VNx4DI.  They are still going to be expanded in the future.

vf4 and vf8 truncations are emulated by truncating two and three times 
respectively.

The patch also adds tests and changes some expectations for already existing 
ones.

Combine does not yet handle binary operations of two widened operands as we are 
missing the necessary split/rewrite patterns.  These will be added at a later 
time.

Co-authored-by: Juzhe Zhong 

riscv.exp testsuite is unchanged.  zero-scratch-regs-3.c seems to FAIL in 
vcondu but that already happens on trunk.

Regards
 Robin

gcc/ChangeLog:

* config/riscv/autovec.md (2): New
expander.
(2): Dito.
(2): Dito.
(trunc2): Dito.
(trunc2): Dito.
(trunc2): Dito.
* config/riscv/riscv-protos.h (riscv_v_ext_mode_p): Declare.
(vectorize_related_mode): Define.
(autovectorize_vector_modes): Define.
* config/riscv/riscv-v.cc (vectorize_related_mode): Implement
hook.
(autovectorize_vector_modes): Implement hook.
* config/riscv/riscv.cc (riscv_v_ext_tuple_mode_p): Export.
(riscv_autovectorize_vector_modes): Implement target hook.
(riscv_vectorize_related_mode): Implement target hook.
(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define.
(TARGET_VECTORIZE_RELATED_MODE): Define.
* config/riscv/vector-iterators.md: Add lowercase versions of
mode_attr iterators.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adjust
expectation.
* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64d-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64f-2.c: Dito.
* gcc.target/riscv/rvv/autovec/zve64x-2.c: Dito.
* gcc.target/riscv/rvv/rvv.exp: Add new conversion tests.
* gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Do not vectorize.
* gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Dito.
* gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Dito.
* gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Dito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Dito.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-template.h: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vsext-template.h: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vzext-template.h: New test.
---
 gcc/config/riscv/autovec.md   | 104 ++
 gcc/config/riscv/riscv-protos.h   |   5 +
 gcc/config/riscv/riscv-v.cc   |  83 ++
 gcc/config/riscv/riscv.cc |  31 +-
 gcc/config/riscv/vector-iterators.md  |  33 +-
 .../riscv/rvv/autovec/binop/shift-rv32gcv.c   |   1 -
 .../riscv/rvv/autovec/binop/shift-rv64gcv.c   |   

[PATCH 1/1] arm: merge MVE_5 and MVE_6 iterators

[Christophe Lyon via Gcc-patches]

MVE_5 and MVE_6 iterators are the same: this patch replaces MVE_6 with
MVE_5 everywhere in mve.md and removes MVE_6 from iterators.md.

2023-05-25  Christophe Lyon 

gcc/
* config/arm/iterators.md (MVE_6): Remove.
* config/arm/mve.md: Replace MVE_6 with MVE_5.
---
 gcc/config/arm/iterators.md |  1 -
 gcc/config/arm/mve.md   | 68 ++---
 2 files changed, 34 insertions(+), 35 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 597c1dae640..9e77af55d60 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -272,7 +272,6 @@
 (define_mode_iterator MVE_3 [V16QI V8HI])
 (define_mode_iterator MVE_2 [V16QI V8HI V4SI])
 (define_mode_iterator MVE_5 [V8HI V4SI])
-(define_mode_iterator MVE_6 [V8HI V4SI])
 (define_mode_iterator MVE_7 [V16BI V8BI V4BI V2QI])
 (define_mode_iterator MVE_7_HI [HI V16BI V8BI V4BI V2QI])
 (define_mode_iterator MVE_V8HF [V8HF])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 9e3570c5264..74909ce47e1 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -3732,9 +3732,9 @@
 ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
 ;;
 (define_insn "mve_vldrhq_gather_offset_"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
-   (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us")
-  (match_operand:MVE_6 2 "s_register_operand" "w")]
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
+   (unspec:MVE_5 [(match_operand: 1 "memory_operand" "Us")
+  (match_operand:MVE_5 2 "s_register_operand" "w")]
VLDRHGOQ))
   ]
   "TARGET_HAVE_MVE"
@@ -3755,9 +3755,9 @@
 ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
 ;;
 (define_insn "mve_vldrhq_gather_offset_z_"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
-   (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us")
-  (match_operand:MVE_6 2 "s_register_operand" "w")
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
+   (unspec:MVE_5 [(match_operand: 1 "memory_operand" "Us")
+  (match_operand:MVE_5 2 "s_register_operand" "w")
   (match_operand: 3 "vpr_register_operand" "Up")
]VLDRHGOQ))
   ]
@@ -3780,9 +3780,9 @@
 ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
 ;;
 (define_insn "mve_vldrhq_gather_shifted_offset_"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
-   (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us")
-  (match_operand:MVE_6 2 "s_register_operand" "w")]
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
+   (unspec:MVE_5 [(match_operand: 1 "memory_operand" "Us")
+  (match_operand:MVE_5 2 "s_register_operand" "w")]
VLDRHGSOQ))
   ]
   "TARGET_HAVE_MVE"
@@ -3803,9 +3803,9 @@
 ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
 ;;
 (define_insn "mve_vldrhq_gather_shifted_offset_z_"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
-   (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us")
-  (match_operand:MVE_6 2 "s_register_operand" "w")
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
+   (unspec:MVE_5 [(match_operand: 1 "memory_operand" "Us")
+  (match_operand:MVE_5 2 "s_register_operand" "w")
   (match_operand: 3 "vpr_register_operand" "Up")
]VLDRHGSOQ))
   ]
@@ -3828,8 +3828,8 @@
 ;; [vldrhq_s, vldrhq_u]
 ;;
 (define_insn "mve_vldrhq_"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
-   (unspec:MVE_6 [(match_operand: 1 "mve_memory_operand" "Ux")]
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=w")
+   (unspec:MVE_5 [(match_operand: 1 "mve_memory_operand" "Ux")]
 VLDRHQ))
   ]
   "TARGET_HAVE_MVE"
@@ -3870,8 +3870,8 @@
 ;; [vldrhq_z_s vldrhq_z_u]
 ;;
 (define_insn "mve_vldrhq_z_"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
-   (unspec:MVE_6 [(match_operand: 1 "mve_memory_operand" "Ux")
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=w")
+   (unspec:MVE_5 [(match_operand: 1 "mve_memory_operand" "Ux")
(match_operand: 2 "vpr_register_operand" "Up")]
 VLDRHQ))
   ]
@@ -4449,7 +4449,7 @@
 (define_insn "mve_vstrhq_p_"
   [(set (match_operand: 0 "mve_memory_operand" "=Ux")
(unspec:
-[(match_operand:MVE_6 1 "s_register_operand" "w")
+[(match_operand:MVE_5 1 "s_register_operand" "w")
  (match_operand: 2 "vpr_register_operand" "Up")
  (match_dup 0)]
 VSTRHQ))
@@ -4470,8 +4470,8 @@
 ;;
 (define_expand "mve_vstrhq_scatter_offset_p_"
   [(match_operand: 0 "mve_scatter_memory")
-   (match_operand:MVE_6 1 "s_register_operand")
-   (match_operand:MVE_6 2 "s_register_operand")
+   (match_operand:MVE_5 1 "s_register_operand")
+   (match_operand:MVE_5 2 "s_register_operand")
(match_operand: 3 "vpr_r

RE: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]

[Kyrylo Tkachov via Gcc-patches]

> -Original Message-
> From: Gcc-patches  bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Thursday, May 25, 2023 11:48 AM
> To: Alex Coplan 
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
> 
> Subject: RE: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]
> 
> 
> 
> > -Original Message-
> > From: Alex Coplan 
> > Sent: Thursday, May 25, 2023 11:26 AM
> > To: Kyrylo Tkachov 
> > Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> > ; Ramana Radhakrishnan
> > 
> > Subject: Re: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]
> >
> > Hi Kyrill,
> >
> > On 23/05/2023 11:14, Kyrylo Tkachov wrote:
> > > Hi Alex,
> > > diff --git a/gcc/testsuite/gcc.target/arm/pr109800.c
> > b/gcc/testsuite/gcc.target/arm/pr109800.c
> > > new file mode 100644
> > > index 000..71d1ede13dd
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/arm/pr109800.c
> > > @@ -0,0 +1,3 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-
> > d16 -mbig-endian -mpure-code" } */
> > > +double f() { return 5.0; }
> > >
> > > ... The arm testsuite options are kinda hard to get right with all the
> effective
> > targets and multilibs and such hardcoded abi and march options tend to
> > break in some target.
> > > I suggest you put this testcase in gcc.target/arm/pure-code and add a dg-
> > skip-if to skip the test if the multilib options specify a different 
> > float-abi.
> >
> > How about this instead:
> >
> > diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
> > b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
> > new file mode 100644
> > index 000..d797b790232
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
> > @@ -0,0 +1,4 @@
> > +/* { dg-do compile } */
> > +/* { dg-require-effective-target arm_hard_ok } */
> > +/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-
> d16 -
> > mbig-endian -mpure-code" } */
> > +double f() { return 5.0; }
> >
> > Full v2 patch attached.
> 
> Thanks, looks better but I think you'll still want to have a dg-skip-if to 
> avoid
> explicit -mfloat-abi=soft and -mfloat-abi=softfp in the multilib options. You
> can grep in that test directory for examples

Actually, as discussed offline this patch is okay as it has the arm_hard_ok 
check.
Thanks,
Kyrill

> Kyrill
> 
> >
> > Thanks,
> > Alex

Re: [PATCH v2] RISC-V: Implement autovec abs, vneg, vnot.

[Robin Dapp via Gcc-patches]

> I think it's logically incorrect.  For ABS, you want:
> 
> operands[0] = operads[1] > 0 ? operands[1] :  (-operands[1])
> So you should do this following sequence:
> 
> vmslt v0,v1,0
> vneg v1,v1v0.t (should use Mask undisturbed)

Yes, this is the emitted sequence, but the vsetvli mask is indeed
wrong.  Just got lucky there.  Or what else did you mean with
logically incorrect?

> Here I see you set:
> e.set_policy (MASK_ANY); which is incorrect.
> You should use e.set_policy (MASK_UNDISTURBED); instead.> 
> Your testcases fail to catch this issue (you should create a testcase
> to catch this bug with this patch implementation.)

Added a regex to look for "ta,mu".

> You should not use RVV_UNOP+2. Instead, you should add an enum call
> RVV_UNOP_MU and replace it.

I was a bit weary of adding yet another, would rather have that
unified somehow, but well ;) Another time.  Adjusted locally.

[PATCH 2/2] cprop_hardreg: Enable propagation of the stack pointer if possible.

[Manolis Tsamis]

Propagation of the stack pointer in cprop_hardreg is currenty forbidden
in all cases, due to maybe_mode_change returning NULL. Relax this
restriction and allow propagation when no mode change is requested.

gcc/ChangeLog:

* regcprop.cc (maybe_mode_change): Enable stack pointer propagation.

Signed-off-by: Manolis Tsamis 
---

 gcc/regcprop.cc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/regcprop.cc b/gcc/regcprop.cc
index f426f4fedcd..6cbfadb181f 100644
--- a/gcc/regcprop.cc
+++ b/gcc/regcprop.cc
@@ -422,7 +422,12 @@ maybe_mode_change (machine_mode orig_mode, machine_mode 
copy_mode,
 
  It's unclear if we need to do the same for other special registers.  */
   if (regno == STACK_POINTER_REGNUM)
-return NULL_RTX;
+{
+  if (orig_mode == new_mode)
+   return stack_pointer_rtx;
+  else
+   return NULL_RTX;
+}
 
   if (orig_mode == new_mode)
 return gen_raw_REG (new_mode, regno);
-- 
2.34.1

[PATCH 0/2] RISC-V: New pass to optimize calculation of offsets for memory operations.

[Manolis Tsamis]

This pass tries to optimize memory offset calculations by moving them
from add immediate instructions to the memory loads/stores.
For example it can transform this:

  addi t4,sp,16
  add  t2,a6,t4
  shl  t3,t2,1
  ld   a2,0(t3)
  addi a2,1
  sd   a2,8(t2)

into the following (one instruction less):

  add  t2,a6,sp
  shl  t3,t2,1
  ld   a2,32(t3)
  addi a2,1
  sd   a2,24(t2)

Although there are places where this is done already, this pass is more
powerful and can handle the more difficult cases that are currently not
optimized. Also, it runs late enough and can optimize away unnecessary
stack pointer calculations.

The first patch in the series contains the implementation of this pass
while the second is a minor change that enables cprop_hardreg's
propgation of the stack pointer, because this pass depends on cprop
to do the propagation of optimized operations. If preferred I can split
this into two different patches (in which cases some of the testcases
included will fail temporarily).



Manolis Tsamis (2):
  Implementation of new RISCV optimizations pass: fold-mem-offsets.
  cprop_hardreg: Enable propagation of the stack pointer if possible.

 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-fold-mem-offsets.cc| 637 ++
 gcc/config/riscv/riscv-passes.def |   1 +
 gcc/config/riscv/riscv-protos.h   |   1 +
 gcc/config/riscv/riscv.opt|   4 +
 gcc/config/riscv/t-riscv  |   4 +
 gcc/doc/invoke.texi   |   8 +
 gcc/regcprop.cc   |   7 +-
 .../gcc.target/riscv/fold-mem-offsets-1.c |  16 +
 .../gcc.target/riscv/fold-mem-offsets-2.c |  24 +
 .../gcc.target/riscv/fold-mem-offsets-3.c |  17 +
 11 files changed, 719 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/riscv/riscv-fold-mem-offsets.cc
 create mode 100644 gcc/testsuite/gcc.target/riscv/fold-mem-offsets-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/fold-mem-offsets-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/fold-mem-offsets-3.c

-- 
2.34.1

[PATCH 1/2] Implementation of new RISCV optimizations pass: fold-mem-offsets.

[Manolis Tsamis]

Implementation of the new RISC-V optimization pass for memory offset
calculations, documentation and testcases.

gcc/ChangeLog:

* config.gcc: Add riscv-fold-mem-offsets.o to extra_objs.
* config/riscv/riscv-passes.def (INSERT_PASS_AFTER): Schedule a new
pass.
* config/riscv/riscv-protos.h (make_pass_fold_mem_offsets): Declare.
* config/riscv/riscv.opt: New options.
* config/riscv/t-riscv: New build rule.
* doc/invoke.texi: Document new option.
* config/riscv/riscv-fold-mem-offsets.cc: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/fold-mem-offsets-1.c: New test.
* gcc.target/riscv/fold-mem-offsets-2.c: New test.
* gcc.target/riscv/fold-mem-offsets-3.c: New test.

Signed-off-by: Manolis Tsamis 
---

 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-fold-mem-offsets.cc| 637 ++
 gcc/config/riscv/riscv-passes.def |   1 +
 gcc/config/riscv/riscv-protos.h   |   1 +
 gcc/config/riscv/riscv.opt|   4 +
 gcc/config/riscv/t-riscv  |   4 +
 gcc/doc/invoke.texi   |   8 +
 .../gcc.target/riscv/fold-mem-offsets-1.c |  16 +
 .../gcc.target/riscv/fold-mem-offsets-2.c |  24 +
 .../gcc.target/riscv/fold-mem-offsets-3.c |  17 +
 10 files changed, 713 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv-fold-mem-offsets.cc
 create mode 100644 gcc/testsuite/gcc.target/riscv/fold-mem-offsets-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/fold-mem-offsets-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/fold-mem-offsets-3.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index d88071773c9..5dffd21b4c8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -529,7 +529,7 @@ pru-*-*)
;;
 riscv*)
cpu_type=riscv
-   extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
+   extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-fold-mem-offsets.o riscv-selftests.o riscv-v.o 
riscv-vsetvl.o"
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o"
d_target_objs="riscv-d.o"
diff --git a/gcc/config/riscv/riscv-fold-mem-offsets.cc 
b/gcc/config/riscv/riscv-fold-mem-offsets.cc
new file mode 100644
index 000..81325bb3beb
--- /dev/null
+++ b/gcc/config/riscv/riscv-fold-mem-offsets.cc
@@ -0,0 +1,637 @@
+/* Fold memory offsets pass for RISC-V.
+   Copyright (C) 2022 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#define IN_TARGET_CODE 1
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "rtl.h"
+#include "tree.h"
+#include "expr.h"
+#include "backend.h"
+#include "regs.h"
+#include "target.h"
+#include "memmodel.h"
+#include "emit-rtl.h"
+#include "insn-config.h"
+#include "recog.h"
+#include "predict.h"
+#include "df.h"
+#include "tree-pass.h"
+#include "cfgrtl.h"
+
+/* This pass tries to optimize memory offset calculations by moving them
+   from add immediate instructions to the memory loads/stores.
+   For example it can transform this:
+
+ addi t4,sp,16
+ add  t2,a6,t4
+ shl  t3,t2,1
+ ld   a2,0(t3)
+ addi a2,1
+ sd   a2,8(t2)
+
+   into the following (one instruction less):
+
+ add  t2,a6,sp
+ shl  t3,t2,1
+ ld   a2,32(t3)
+ addi a2,1
+ sd   a2,24(t2)
+
+   Usually, the code generated from the previous passes tries to have the
+   offsets in the memory instructions but this pass is still beneficial
+   because:
+
+- There are cases where add instructions are added in a late rtl pass
+  and the rest of the pipeline cannot eliminate them.  Specifically,
+  arrays and structs allocated on the stack can result in multiple
+  unnecessary add instructions that cannot be eliminated easily
+  otherwise.
+
+- The existing mechanisms that move offsets to memory instructions
+  usually apply only to specific patterns or have other limitations.
+  This pass is very generic and can fold offsets through complex
+  calculations with multiple memory uses and partially overlapping
+  calculations.  As a result 

Re: [PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support

[Richard Sandiford via Gcc-patches]

This looks good to me.  Just a couple of very minor cosmetic things:

juzhe.zh...@rivai.ai writes:
> @@ -753,17 +846,35 @@ vect_set_loop_condition_partial_vectors (class loop 
> *loop,
> continue;
> }
>  
> - /* See whether zero-based IV would ever generate all-false masks
> -or zero length before wrapping around.  */
> - bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, rgc);
> -
> - /* Set up all controls for this group.  */
> - test_ctrl = vect_set_loop_controls_directly (loop, loop_vinfo,
> -  &preheader_seq,
> -  &header_seq,
> -  loop_cond_gsi, rgc,
> -  niters, niters_skip,
> -  might_wrap_p);
> + if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo) || !iv_rgc
> + || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
> + != rgc->max_nscalars_per_iter * rgc->factor))

Coding style is to put each subcondition on a separate line when the
whole condition doesn't fit on a single line.  So:

if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
|| !iv_rgc
|| (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
!= rgc->max_nscalars_per_iter * rgc->factor))

> @@ -2725,6 +2726,17 @@ start_over:
>&& !vect_verify_loop_lens (loop_vinfo))
>  LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) = false;
>  
> +  /* If we're vectorizing an loop that uses length "controls" and

s/an loop/a loop/(Sorry for not noticing earlier.)

OK for trunk from my POV with those changes; no need to repost unless
your policies require it.  Please give Richi a chance to comment too
though.

Thanks for your patience with the review process.  The final result
seems pretty clean to me.

Richard

Re: [PATCH v4] libgfortran: Replace mutex with rwlock

[Zhu, Lipeng via Gcc-patches]

On 1/1/1970 8:00 AM, Thomas Koenig wrote:

Hi Lipeng,


May I know any comment or concern on this patch, thanks for your time :)



Thanks for your patience in getting this reviewed.

A few remarks / questions.

Which strategy is used in this implementation, read-preferring or 
write-preferring?  And if read-
preferring is used, is there a danger of deadlock if people do unreasonable 
things?
Maybe you could explain that, also in a comment in the code >
Can you add some sort of torture test case(s) which does a lot of 
opening/closing/reading/writing,
possibly with asynchronous I/O and/or pthreads, to catch possible problems?  If 
there is a system
dependency or some race condition, chances are that regression testers will 
catch this.


Hi Thomas,

Thanks for your time for the review.
Sure, I will add test case according to your suggestions and update the 
comment based on the implementation of "read-preferring" strategy.


Thanks,
Lipeng Zhu


With this, the libgfortran parts are OK, unless somebody else has more 
comments, so give this a couple
of days.  I cannot approve the libgcc parts, that would be somebody else 
(Jakub?)

Best regards

Thomas

[PATCH V17] VECT: Add decrement IV iteration loop control by variable amount support

[juzhe . zhong]

From: Ju-Zhe Zhong 

Fix format for Richard.

This patch is supporting decrement IV by following the flow designed by Richard:

(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.

(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rgc has 1 control, this step is the SSA name created for that control.
Otherwise the step is a fresh SSA name, as in your patch.

(3) vect_set_loop_controls_directly stores this step somewhere for later
use, probably in LOOP_VINFO.  Let's use "S" to refer to this stored step.

(4) After the vect_set_loop_controls_directly call above, and outside
the "if" statement that now contains vect_set_loop_controls_directly,
check whether rgc->controls.length () > 1.  If so, use
vect_adjust_loop_lens_control to set the controls based on S.

Then the only caller of vect_adjust_loop_lens_control is
vect_set_loop_condition_partial_vectors.  And the starting
step for vect_adjust_loop_lens_control is always S.

This patch has well tested for single-rgroup and multiple-rgroup (SLP) and
passed all testcase in RISC-V port.

gcc/ChangeLog:

* tree-vect-loop-manip.cc (vect_adjust_loop_lens_control): New function.
(vect_set_loop_controls_directly): Add decrement IV support.
(vect_set_loop_condition_partial_vectors): Ditto.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): New variable.
* tree-vectorizer.h (LOOP_VINFO_USING_DECREMENTING_IV_P): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: New 
test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: New 
test.

---
 .../rvv/autovec/partial/multiple_rgroup-3.c   | 288 ++
 .../rvv/autovec/partial/multiple_rgroup-4.c   |  75 +
 .../autovec/partial/multiple_rgroup_run-3.c   |  36 +++
 .../autovec/partial/multiple_rgroup_run-4.c   |  15 +
 gcc/tree-vect-loop-manip.cc   | 136 -
 gcc/tree-vect-loop.cc |  12 +
 gcc/tree-vectorizer.h |   8 +
 7 files changed, 558 insertions(+), 12 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
new file mode 100644
index 000..9579749c285
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
@@ -0,0 +1,288 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax" } */
+
+#include 
+
+void __attribute__ ((noinline, noclone))
+f0 (int8_t *__restrict x, int16_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i += 4, j += 8)
+{
+  x[i + 0] += 1;
+  x[i + 1] += 2;
+  x[i + 2] += 3;
+  x[i + 3] += 4;
+  y[j + 0] += 1;
+  y[j + 1] += 2;
+  y[j + 2] += 3;
+  y[j + 3] += 4;
+  y[j + 4] += 5;
+  y[j + 5] += 6;
+  y[j + 6] += 7;
+  y[j + 7] += 8;
+}
+}
+
+void __attribute__ ((optimize (0)))
+f0_init (int8_t *__restrict x, int8_t *__restrict x2, int16_t *__restrict y,
+int16_t *__restrict y2, int n)
+{
+  for (int i = 0, j = 0; i < n; i += 4, j += 8)
+{
+  x[i + 0] = i % 120;
+  x[i + 1] = i % 78;
+  x[i + 2] = i % 55;
+  x[i + 3] = i % 27;
+  y[j + 0] = j % 33;
+  y[j + 1] = j % 44;
+  y[j + 2] = j % 66;
+  y[j + 3] = j % 88;
+  y[j + 4] = j % 99;
+  y[j + 5] = j % 39;
+  y[j + 6] = j % 49;
+  y[j + 7] = j % 101;
+
+  x2[i + 0] = i % 120;
+  x2[i + 1] = i % 78;
+  x2[i + 2] = i % 55;
+  x2[i + 3] = i % 27;
+  y2[j + 0] = j % 33;
+  y2[j + 1] = j % 44;
+  y2[j + 2] = j % 66;
+  y2[j + 3] = j % 88;
+  y2[j + 4] = j % 99;
+  y2[j + 5] = j % 39;
+  y2[j + 6] = j % 49;
+  y2[j + 7] = j % 101;
+}
+}
+
+void __attribute__ ((optimize (0)))
+f0_golden (int8_t *__restrict x, int16_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i += 4, j += 8)
+{
+  x[i + 0] += 1;
+  x[i + 1] += 2;
+  x[i + 2] += 3;
+  x[i + 3] += 4;
+  y[j + 0] += 1;
+  y[j + 1] += 2;
+  y[j + 2] += 3;
+  y[j + 3] += 4;
+  y[j + 4] += 5;
+  y[j + 5] += 6;
+  y[j + 6] += 7;
+  y[j + 7] += 8;
+}
+}
+
+void __attribute__ ((optimize (0)))
+f0_check (int8_t *__restrict x, int8_t

Re: Re: [PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support

[钟居哲]

Thanks Richard so much.
I have sent V17 patch for commit (fix format as you suggested).
You don't need to reply that.

I am waiting for Richi's final approval.

Thanks.


juzhe.zh...@rivai.ai
 
From: Richard Sandiford
Date: 2023-05-25 20:36
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V16] VECT: Add decrement IV iteration loop control by 
variable amount support
This looks good to me.  Just a couple of very minor cosmetic things:
 
juzhe.zh...@rivai.ai writes:
> @@ -753,17 +846,35 @@ vect_set_loop_condition_partial_vectors (class loop 
> *loop,
>continue;
>}
>  
> - /* See whether zero-based IV would ever generate all-false masks
> -or zero length before wrapping around.  */
> - bool might_wrap_p = vect_rgroup_iv_might_wrap_p (loop_vinfo, rgc);
> -
> - /* Set up all controls for this group.  */
> - test_ctrl = vect_set_loop_controls_directly (loop, loop_vinfo,
> -  &preheader_seq,
> -  &header_seq,
> -  loop_cond_gsi, rgc,
> -  niters, niters_skip,
> -  might_wrap_p);
> + if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo) || !iv_rgc
> + || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
> + != rgc->max_nscalars_per_iter * rgc->factor))
 
Coding style is to put each subcondition on a separate line when the
whole condition doesn't fit on a single line.  So:
 
if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
|| !iv_rgc
|| (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
!= rgc->max_nscalars_per_iter * rgc->factor))
 
> @@ -2725,6 +2726,17 @@ start_over:
>&& !vect_verify_loop_lens (loop_vinfo))
>  LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) = false;
>  
> +  /* If we're vectorizing an loop that uses length "controls" and
 
s/an loop/a loop/(Sorry for not noticing earlier.)
 
OK for trunk from my POV with those changes; no need to repost unless
your policies require it.  Please give Richi a chance to comment too
though.
 
Thanks for your patience with the review process.  The final result
seems pretty clean to me.
 
Richard
 

[PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

[Pan Li via Gcc-patches]

From: Pan Li 

This patch would like to add new sub extension (aka ZVFHMIN) to the
-march= option. To make it simple, only the sub extension itself is
involved in this patch, and the underlying FP16 related RVV intrinsic
API depends on the TARGET_ZVFHMIN.

You can locate more information about ZVFHMIN from below spec doc.

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point

Signed-off-by: Pan Li 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/predef-26.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc|  3 ++
 gcc/config/riscv/riscv-opts.h  |  6 ++-
 gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++
 4 files changed, 63 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c2ec74b9d92..72f2f8f2753 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
+  {"zvfhmin", "f"},
 
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
@@ -216,6 +217,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+  {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
 
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2a16402265a..f34ca993689 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -200,9 +200,11 @@ enum riscv_entity
 
 #define MASK_ZFHMIN   (1 << 0)
 #define MASK_ZFH  (1 << 1)
+#define MASK_ZVFHMIN  (1 << 2)
 
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
+#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
 
 #define MASK_ZMMUL  (1 << 0)
 #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c 
b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 000..8f8da1ecd65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c 
b/gcc/testsuite/gcc.target/riscv/predef-26.c
new file mode 100644
index 000..285f64bd6c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zvfhmin)
+#error "__riscv_zvfhmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_zfh)
+#error "__riscv_zfh"
+#endif
+
+#if defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+  return 0;
+}
-- 
2.34.1