Re: [PATCH, rs6000] Fix PR target/80246, DFP builtins using the wrong types
On Mär 30 2017, Peter Bergner wrote:
> Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c
> ===
> --- gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (revision 246539)
> +++ gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (working copy)
> @@ -1,6 +1,4 @@
> /* { dg-do compile { target { powerpc*-*-linux* } } } */
> -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
> -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
> /* { dg-require-effective-target powerpc_vsx_ok } */
> /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
> "-mcpu=power7" } } */
> /* { dg-options "-mcpu=power7 -O2" } */
> @@ -10,11 +8,13 @@
> /* { dg-final { scan-assembler-times "diex " 1} } */
> /* { dg-final { scan-assembler-times "dscli " 2} } */
> /* { dg-final { scan-assembler-times "dscri " 2} } */
> +/* { dg-final { scan-assembler-times "std "1} } */
> +/* { dg-final { scan-assembler-times "ld " 1} } */
Fails with -m32.
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
Re: [PATCH] [PATCH, rs6000] Fix pr79941 (v2)
On Mär 09 2017, Will Schmidt wrote:
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
> new file mode 100644
> index 000..4bb6185
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
> @@ -0,0 +1,61 @@
> +/* PR target/79941 */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-mvsx -O2 -save-temps" } */
FAIL: gcc.target/powerpc/fold-vec-mule-misc.c execution test
$ ./fold-vec-mule-misc.exe
Illegal instruction
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
Re: [PATCH, rs6000] Fix PR target/80246, DFP builtins using the wrong types
On Mär 30 2017, Peter Bergner wrote:
> Index: gcc/testsuite/gcc.target/powerpc/pr80246.c
> ===
> --- gcc/testsuite/gcc.target/powerpc/pr80246.c(nonexistent)
> +++ gcc/testsuite/gcc.target/powerpc/pr80246.c(working copy)
> @@ -0,0 +1,35 @@
> +/* { dg-do compile { target { powerpc*-*-linux* } } } */
> +/* { dg-require-effective-target dfp } */
> +/* { dg-options "-O2" } */
> +/* { dg-final { scan-assembler-times "dxex " 1 } } */
> +/* { dg-final { scan-assembler-times "dxexq " 1 } } */
> +/* { dg-final { scan-assembler-times "diex " 1 } } */
> +/* { dg-final { scan-assembler-times "diexq " 1 } } */
> +/* { dg-final { scan-assembler-not "bl __builtin" } } */
> +/* { dg-final { scan-assembler-not "drintn" } } */
> +/* { dg-final { scan-assembler-not "dctfix" } } */
> +/* { dg-final { scan-assembler-not "dcffix" } } */
> +
> +long long
> +do_xex (_Decimal64 arg)
> +{
> + return __builtin_dxex (arg);
> +}
> +
> +long long
> +do_xexq (_Decimal128 arg)
> +{
> + return __builtin_dxexq (arg);
> +}
> +
> +_Decimal64
> +do_iex (long long exp, _Decimal64 arg)
> +{
> + return __builtin_diex (exp, arg);
> +}
> +
> +_Decimal128
> +do_iexq (long long exp, _Decimal128 arg)
> +{
> + return __builtin_diexq (exp, arg);
> +}
FAIL: gcc.target/powerpc/pr80246.c (test for excess errors)
Excess errors:
/daten/gcc/gcc-20170401/gcc/testsuite/gcc.target/powerpc/pr80246.c:18:10:
error: Builtin function __builtin_dxex requires the -mhard-dfp option
/daten/gcc/gcc-20170401/gcc/testsuite/gcc.target/powerpc/pr80246.c:24:10:
error: Builtin function __builtin_dxexq requires the -mhard-dfp option
/daten/gcc/gcc-20170401/gcc/testsuite/gcc.target/powerpc/pr80246.c:30:10:
error: Builtin function __builtin_diex requires the -mhard-dfp option
/daten/gcc/gcc-20170401/gcc/testsuite/gcc.target/powerpc/pr80246.c:36:10:
error: Builtin function __builtin_diexq requires the -mhard-dfp option
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
Re: [PATCH] [PATCH, rs6000] Fix pr79941 (v2)
On Sun, Apr 02, 2017 at 09:26:24AM +0200, Andreas Schwab wrote:
> > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
> > b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
> > new file mode 100644
> > index 000..4bb6185
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
> > @@ -0,0 +1,61 @@
> > +/* PR target/79941 */
> > +
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target powerpc_vsx_ok } */
> > +/* { dg-options "-mvsx -O2 -save-temps" } */
>
> FAIL: gcc.target/powerpc/fold-vec-mule-misc.c execution test
>
> $ ./fold-vec-mule-misc.exe
> Illegal instruction
It should test vsx_hw, not just vsx_ok. I'll handle it (and the other
problem you found). Thanks, and sorry for not spotting the problems!
Segher
Re: [v3 PATCH] Implement std::is_aggregate.
On 2 April 2017 at 08:35, Jakub Jelinek wrote: >> + remove_cv_t<_Tp> >> + )> > > Any reason for the wrapping? No, it's just a result of a nocturnal copy-paste-job of the existing code for has_unique_object_representations. > Also, shouldn't there be also: > > /// is_aggregate_v > template > _GLIBCXX17_INLINE constexpr bool is_aggregate_v = > is_aggregate<_Tp>::value; > > somewhere with appropriate guards (or within the same ones)? Yes, well spotted. I will add that. > I'm surprised tests for the is_*_v variable templates are only in > experimental/type_traits/value.cc when they are now apparently > part of C++17. Perhaps 20_util/variable_templates_for_traits.cc ?
Re: [v3 PATCH] Implement std::is_aggregate.
On Sun, Apr 02, 2017 at 12:24:16PM +0300, Ville Voutilainen wrote: > On 2 April 2017 at 08:35, Jakub Jelinek wrote: > >> + remove_cv_t<_Tp> > >> + )> > > > > Any reason for the wrapping? > > No, it's just a result of a nocturnal copy-paste-job of the existing > code for has_unique_object_representations. > > > Also, shouldn't there be also: > > > > /// is_aggregate_v > > template > > _GLIBCXX17_INLINE constexpr bool is_aggregate_v = > > is_aggregate<_Tp>::value; > > > > somewhere with appropriate guards (or within the same ones)? > > Yes, well spotted. I will add that. > > > I'm surprised tests for the is_*_v variable templates are only in > > experimental/type_traits/value.cc when they are now apparently > > part of C++17. > > Perhaps 20_util/variable_templates_for_traits.cc ? Whatever you/Jonathan and/or Paolo agree on, libstdc++ isn't my area of expertise. Jakub
Re: [v3 PATCH] Implement std::is_aggregate.
On 2 April 2017 at 14:08, Jakub Jelinek wrote:
> On Sun, Apr 02, 2017 at 12:24:16PM +0300, Ville Voutilainen wrote:
>> On 2 April 2017 at 08:35, Jakub Jelinek wrote:
>> >> + remove_cv_t<_Tp>
>> >> + )>
>> >
>> > Any reason for the wrapping?
>>
>> No, it's just a result of a nocturnal copy-paste-job of the existing
>> code for has_unique_object_representations.
>>
>> > Also, shouldn't there be also:
>> >
>> > /// is_aggregate_v
>> > template
>> > _GLIBCXX17_INLINE constexpr bool is_aggregate_v =
>> > is_aggregate<_Tp>::value;
>> >
>> > somewhere with appropriate guards (or within the same ones)?
>>
>> Yes, well spotted. I will add that.
Thus:
2017-04-02 Ville Voutilainen
Implement std::is_aggregate.
* include/std/type_traits (is_aggregate, is_aggregate_v): New.
* testsuite/20_util/is_aggregate/requirements/explicit_instantiation.cc:
New.
* testsuite/20_util/is_aggregate/requirements/typedefs.cc: Likewise.
* testsuite/20_util/is_aggregate/value.cc: Likewise.
diff --git a/libstdc++-v3/include/std/type_traits
b/libstdc++-v3/include/std/type_traits
index 6707caa..a5e7048 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -3062,6 +3062,25 @@ template
#endif
#undef _GLIBCXX_NO_BUILTIN_HAS_UNIQ_OBJ_REP
+#ifdef __has_builtin
+# if !__has_builtin(__is_aggregate)
+// Try not to break non-GNU compilers that don't support the built-in:
+# define _GLIBCXX_NO_BUILTIN_IS_AGGREGATE 1
+# endif
+#endif
+
+#ifndef _GLIBCXX_NO_BUILTIN_IS_AGGREGATE
+#define __cpp_lib_is_aggregate 201703
+ /// is_aggregate
+ template
+struct is_aggregate
+: bool_constant<__is_aggregate(remove_cv_t<_Tp>)> { };
+ /// is_aggregate_v
+ template
+inline constexpr bool is_aggregate_v = is_aggregate<_Tp>::value;
+#endif
+#undef _GLIBCXX_NO_BUILTIN_IS_AGGREGATE
+
#endif // C++17
_GLIBCXX_END_NAMESPACE_VERSION
diff --git
a/libstdc++-v3/testsuite/20_util/is_aggregate/requirements/explicit_instantiation.cc
b/libstdc++-v3/testsuite/20_util/is_aggregate/requirements/explicit_instantiation.cc
new file mode 100644
index 000..4c189cd
--- /dev/null
+++
b/libstdc++-v3/testsuite/20_util/is_aggregate/requirements/explicit_instantiation.cc
@@ -0,0 +1,29 @@
+// { dg-options "-std=gnu++1z" }
+// { dg-do compile { target c++1z } }
+
+// Copyright (C) 2017 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+//
Re: [PATCH] [PATCH, rs6000] Fix pr79941 (v2)
On Sun, Apr 02, 2017 at 09:26:24AM +0200, Andreas Schwab wrote:
> > +/* PR target/79941 */
> > +
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target powerpc_vsx_ok } */
> > +/* { dg-options "-mvsx -O2 -save-temps" } */
>
> FAIL: gcc.target/powerpc/fold-vec-mule-misc.c execution test
>
> $ ./fold-vec-mule-misc.exe
> Illegal instruction
I cannot get this one to fail, unless I explicitly use -mcpu=power8 or
similar (which will not run on a power7, direct move insns do not yet
exist on power7).
What is different about your setup? (What *is* your setup?)
Segher
Re: [PATCH] [PATCH, rs6000] Fix pr79941 (v2)
On Apr 02 2017, Segher Boessenkool wrote:
> On Sun, Apr 02, 2017 at 09:26:24AM +0200, Andreas Schwab wrote:
>> > +/* PR target/79941 */
>> > +
>> > +/* { dg-do run } */
>> > +/* { dg-require-effective-target powerpc_vsx_ok } */
>> > +/* { dg-options "-mvsx -O2 -save-temps" } */
>>
>> FAIL: gcc.target/powerpc/fold-vec-mule-misc.c execution test
>>
>> $ ./fold-vec-mule-misc.exe
>> Illegal instruction
>
> I cannot get this one to fail, unless I explicitly use -mcpu=power8 or
> similar (which will not run on a power7, direct move insns do not yet
> exist on power7).
>
> What is different about your setup? (What *is* your setup?)
http://gcc.gnu.org/ml/gcc-testresults/2017-04/msg00126.html
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
Re: [PATCH] [PATCH, rs6000] Fix pr79941 (v2)
On Sun, Apr 02, 2017 at 03:45:05PM +0200, Andreas Schwab wrote:
> > On Sun, Apr 02, 2017 at 09:26:24AM +0200, Andreas Schwab wrote:
> >> > +/* PR target/79941 */
> >> > +
> >> > +/* { dg-do run } */
> >> > +/* { dg-require-effective-target powerpc_vsx_ok } */
> >> > +/* { dg-options "-mvsx -O2 -save-temps" } */
> >>
> >> FAIL: gcc.target/powerpc/fold-vec-mule-misc.c execution test
> >>
> >> $ ./fold-vec-mule-misc.exe
> >> Illegal instruction
> >
> > I cannot get this one to fail, unless I explicitly use -mcpu=power8 or
> > similar (which will not run on a power7, direct move insns do not yet
> > exist on power7).
> >
> > What is different about your setup? (What *is* your setup?)
>
> http://gcc.gnu.org/ml/gcc-testresults/2017-04/msg00126.html
That only says it is powerpc64-linux. I don't see these problems there
(or anywhere else).
The testcase should not run on anything older than a Power7. Is your
system something older? Why does powerpc_vsx_ok return true then, ugh.
Segher
Re: [PATCH, rs6000] Fix PR target/80246, DFP builtins using the wrong types
On 4/2/17 2:29 AM, Andreas Schwab wrote:
>> +/* { dg-require-effective-target dfp } */
[snip]
> FAIL: gcc.target/powerpc/pr80246.c (test for excess errors)
> Excess errors:
> /daten/gcc/gcc-20170401/gcc/testsuite/gcc.target/powerpc/pr80246.c:18:10:
> error: Builtin function __builtin_dxex requires the -mhard-dfp option
What configure options are you using? I would have expected this the
dg-require-effective-target to disable this test if you don't have
-mhard-dfp.
Peter
Re: [PATCH] [PATCH, rs6000] Fix pr79941 (v2)
On Apr 02 2017, Segher Boessenkool wrote: > Why does powerpc_vsx_ok return true then, ugh. Because the assembler is new enough. That's all it checks. Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 "And now for something completely different."
Re: [PATCH, rs6000] Fix PR target/80246, DFP builtins using the wrong types
On Apr 02 2017, Peter Bergner wrote:
> On 4/2/17 2:29 AM, Andreas Schwab wrote:
>>> +/* { dg-require-effective-target dfp } */
> [snip]
>> FAIL: gcc.target/powerpc/pr80246.c (test for excess errors)
>> Excess errors:
>> /daten/gcc/gcc-20170401/gcc/testsuite/gcc.target/powerpc/pr80246.c:18:10:
>> error: Builtin function __builtin_dxex requires the -mhard-dfp option
>
> What configure options are you using?
http://gcc.gnu.org/ml/gcc-testresults/2017-04/msg00126.html
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
[PATCH, i386]: Fix PR 80250, ICE for __builtin_ia32_vp4dpwssds_mask builtin
Hello!
Attached patch rewrites totally wrong IMOD4 move patterns. Insn
pattern didn't even have constraints, split pattern didn't allow
constant zero in its operand predicate, so no wonder compilation
failed on const_0.
2017-04-02 Uros Bizjak
PR target/80250
* config/i386/sse.md (mov): Remove insn pattern.
(mov): New expander.
(*mov_internal): New insn and split pattern.
Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
Index: config/i386/sse.md
===
--- config/i386/sse.md (revision 246636)
+++ config/i386/sse.md (working copy)
@@ -19707,25 +19707,39 @@
(define_mode_attr imod4_narrow
[(V64SF "V16SF") (V64SI "V16SI")])
-(define_insn "mov"
+(define_expand "mov"
[(set (match_operand:IMOD4 0 "nonimmediate_operand")
- (match_operand:IMOD4 1 "general_operand"))]
+ (match_operand:IMOD4 1 "vector_move_operand"))]
"TARGET_AVX512F"
- "#")
+{
+ ix86_expand_vector_move (mode, operands);
+ DONE;
+})
-(define_split
- [(set (match_operand:IMOD4 0 "register_operand")
- (match_operand:IMOD4 1 "nonimmediate_operand"))]
- "TARGET_AVX512F && reload_completed"
- [(set (subreg: (match_dup 0) 0)
- (subreg: (match_dup 1) 0))
- (set (subreg: (match_dup 0) 64)
- (subreg: (match_dup 1) 64))
- (set (subreg: (match_dup 0) 128)
- (subreg: (match_dup 1) 128))
- (set (subreg: (match_dup 0) 192)
- (subreg: (match_dup 1) 192))])
+(define_insn_and_split "*mov_internal"
+ [(set (match_operand:IMOD4 0 "nonimmediate_operand" "=v,v ,m")
+ (match_operand:IMOD4 1 "vector_move_operand" " C,vm,v"))]
+ "TARGET_AVX512F
+ && (register_operand (operands[0], mode)
+ || register_operand (operands[1], mode))"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx op0, op1;
+ int i;
+ for (i = 0; i < 4; i++)
+{
+ op0 = simplify_subreg
+(mode, operands[0], mode, i * 64);
+ op1 = simplify_subreg
+(mode, operands[1], mode, i * 64);
+ emit_move_insn (op0, op1);
+}
+ DONE;
+})
+
(define_insn "avx5124fmaddps_4fmaddps"
[(set (match_operand:V16SF 0 "register_operand" "=v")
(unspec:V16SF
Re: [PATCH] On x86 allow if-conversion of more than one insn as long as there is at most one cmov (PR tree-optimization/79390)
On Sat, Apr 1, 2017 at 2:20 PM, Jakub Jelinek wrote: > Hi! > > As discussed in the PR, in the following testcase we don't if-convert > with the generic (and many other) tuning, because we default to > --param max-rtl-if-conversion-insns=1 in most of the tunings. > The problem we have is with multiple cmov instructions, but in the > testcase there is just one cmov and the other insn is turned into a SSE > max insn, which is fine. > > This patch stops artificially lowering that param, and for one_if_conv_insn > tuning it instead rejects the if-conversion if the resulting sequence has > multiple cmov instructions. The hook is passed if_info too, so it can > in the future do better heuristics based on predictability of the edges, > how far the uses of the cmov result are (I assume cmov major problem is > latency, right?) etc. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > 2017-04-01 Jakub Jelinek > > PR tree-optimization/79390 > * target.h (struct noce_if_info): Declare. > * targhooks.h (default_noce_conversion_profitable_p): Declare. > * target.def (noce_conversion_profitable_p): New target hook. > * ifcvt.h (struct noce_if_info): New type, moved from ... > * ifcvt.c (struct noce_if_info): ... here. > (noce_conversion_profitable_p): Renamed to ... > (default_noce_conversion_profitable_p): ... this. No longer > static nor inline. > (noce_try_store_flag_constants, noce_try_addcc, > noce_try_store_flag_mask, noce_try_cmove, noce_try_cmove_arith, > noce_convert_multiple_sets): Use targetm.noce_conversion_profitable_p > instead of noce_conversion_profitable_p. > * config/i386/i386.c: Include ifcvt.h. > (ix86_option_override_internal): Don't override > PARAM_MAX_RTL_IF_CONVERSION_INSNS default. > (ix86_noce_conversion_profitable_p): New function. > (TARGET_NOCE_CONVERSION_PROFITABLE_P): Redefine. > * config/i386/x86-tune.def (X86_TUNE_ONE_IF_CONV_INSN): Adjust > comment. > * doc/tm.texi.in (TARGET_NOCE_CONVERSION_PROFITABLE_P): Add. > * doc/tm.texi: Regenerated. > > * gcc.target/i386/pr79390.c: New test. > * gcc.dg/ifcvt-4.c: Use -mtune-ctrl=^one_if_conv_insn for i?86/x86_64. x86 part LGTM. Hopefully, this infrastructure will allow us to fix (or it already fixes) PR 56309 [1]. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56309 Thanks, Uros.
Re: [PATCH, rs6000] Fix PR target/80246, DFP builtins using the wrong types
On Sun, Apr 02, 2017 at 09:48:36AM -0500, Peter Bergner wrote:
> On 4/2/17 2:29 AM, Andreas Schwab wrote:
> >> +/* { dg-require-effective-target dfp } */
> [snip]
> > FAIL: gcc.target/powerpc/pr80246.c (test for excess errors)
> > Excess errors:
> > /daten/gcc/gcc-20170401/gcc/testsuite/gcc.target/powerpc/pr80246.c:18:10:
> > error: Builtin function __builtin_dxex requires the -mhard-dfp option
>
> What configure options are you using? I would have expected this the
> dg-require-effective-target to disable this test if you don't have
> -mhard-dfp.
This should test hard_dfp instead of dfp. I also have a fix for the
dfp-builtin-1.c problem. Still pondering what to do about the last one,
fold-vec-mule-misc.c: vsx_ok is pretty useless, or confusingly named at
least.
Segher
[PATCH, i386]: Add missing DONE to movdi_to_sse.
2017-04-02 Uros Bizjak
* config/i386/sse.md (movdi_to_sse): Add missing DONE.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline.
Uros.
Index: config/i386/sse.md
===
--- config/i386/sse.md (revision 246637)
+++ config/i386/sse.md (working copy)
@@ -1141,6 +1141,7 @@
}
else
gcc_unreachable ();
+ DONE;
})
(define_split
Re: [v3 PATCH] PR libstdc++/79141
On 2 April 2017 at 02:45, Ville Voutilainen wrote: > Tested on Linux-x64. For what it's worth, here's a saner changelog that uses the signatures that were originally in place. The patch passes the full testsuite on Linux-PPC64 without regressions. 2017-04-02 Ville Voutilainen PR libstdc++/79141 * include/bits/stl_pair.h (__wrap_nonesuch): New. (operator=(typename conditional< __and_, is_copy_assignable<_T2>>::value, const pair&, const __nonesuch&>::type)): Change __nonesuch to __wrap_nonesuch. (operator=(typename conditional< __not_<__and_, is_copy_assignable<_T2>>>::value, const pair&, const __nonesuch&>::type)): Likewise. (operator=(typename conditional< __and_, is_move_assignable<_T2>>::value, pair&&, __nonesuch&&>::type)): Likewise. * testsuite/20_util/pair/79141.cc: New.
New German PO file for 'gcc' (version 7.1-b20170226)
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Re: [CHKP] Fix for PR79990
Hi,
Here is the patch that roughly follows your idea.
Some comments:
- There are more cases than array_ref overflow. We need to take care
of component_ref and both underflows/overflows are possible
- I could not make it work with "0" as a fake address, because then
catching lower bounds violation is getting hard at O2 and above. E.g.
consider this:
0x004005f8 <+8>: bndmk 0x7(%rax),%bnd0
0x004005fd <+13>:mov$0x400734,%edi
=> 0x00400602 <+18>:bndcl 0xfffc,%bnd0
(gdb) p $bnd0
$1 = {lbound = 0x0, ubound = 0x7} : size 8
0x0040060b <+27>:callq 0x400500
- bndcu is removed as not necessary and underflowed access is not
caught. I used another fake value for lower bound address, which is
2^(bitness - 1)
- hard-reg-3-[1,2]* tests fail with ICE right now because of PR80270.
I will mark them as XFAIL if the patch is approved and the mentioned
bug is not fixed
diff --git a/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-lbv.c
b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-lbv.c
new file mode 100644
index 000..319e1ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-lbv.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-shouldfail "bounds violation" } */
+/* { dg-options "-fcheck-pointer-bounds -mmpx" } */
+
+
+#define SHOULDFAIL
+
+#include "mpx-check.h"
+
+typedef int v16 __attribute__((vector_size(16)));
+
+int foo(int i) {
+ register v16 u asm("xmm0");
+ return u[i];
+}
+
+int mpx_test (int argc, const char **argv)
+{
+ printf ("%d\n", foo (-1));
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-nov.c
b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-nov.c
new file mode 100644
index 000..3c6d39a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-nov.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-fcheck-pointer-bounds -mmpx" } */
+
+#include "mpx-check.h"
+
+typedef int v16 __attribute__((vector_size(16)));
+
+int foo (int i) {
+ register v16 u asm ("xmm0");
+ return u[i];
+}
+
+int mpx_test (int argc, const char **argv)
+{
+ printf ("%d\n", foo (3));
+ printf ("%d\n", foo (0));
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-ubv.c
b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-ubv.c
new file mode 100644
index 000..7fe76c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-2-ubv.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-shouldfail "bounds violation" } */
+/* { dg-options "-fcheck-pointer-bounds -mmpx" } */
+
+
+#define SHOULDFAIL
+
+#include "mpx-check.h"
+
+typedef int v16 __attribute__((vector_size(16)));
+
+int foo (int i) {
+ register v16 u asm ("xmm0");
+ return u[i];
+}
+
+int mpx_test (int argc, const char **argv)
+{
+ printf ("%d\n", foo (5));
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-lbv.c
b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-lbv.c
new file mode 100644
index 000..7e4451f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-lbv.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-shouldfail "bounds violation" } */
+/* { dg-options "-fcheck-pointer-bounds -mmpx" } */
+
+
+#define SHOULDFAIL
+
+#include "mpx-check.h"
+
+typedef int v8 __attribute__ ((vector_size (8)));
+
+struct S1
+{
+ v8 s1f;
+};
+
+struct S2
+{
+ struct S1 s2f1;
+ v8 s2f2;
+};
+
+int foo_s2f1 (int i)
+{
+ register struct S2 b asm ("xmm0");
+ return b.s2f1.s1f[i];
+}
+
+int mpx_test (int argc, const char **argv)
+{
+ printf ("%d\n", foo_s2f1 (-1));
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-nov.c
b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-nov.c
new file mode 100644
index 000..73bd7fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-nov.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-options "-fcheck-pointer-bounds -mmpx" } */
+
+
+#include "mpx-check.h"
+
+typedef int v8 __attribute__ ((vector_size (8)));
+
+struct S1
+{
+ v8 s1f;
+};
+
+struct S2
+{
+ struct S1 s2f1;
+ v8 s2f2;
+};
+
+int foo_s2f1 (int i)
+{
+ register struct S2 b asm ("xmm0");
+ return b.s2f1.s1f[i];
+}
+
+int mpx_test (int argc, const char **argv)
+{
+ printf ("%d\n", foo_s2f1 (0));
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-ubv.c
b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-ubv.c
new file mode 100644
index 000..166b6b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mpx/hard-reg-3-1-ubv.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-shouldfail "bounds violation" } */
+/* { dg-options "-fcheck-pointer-bounds -mmpx" } */
+
+
+#define SHOULDFAIL
+
+#include "mpx-check.h"
+
+typedef int v8 __attribute__ ((vector_size (8)));
+
+struct S1
+{
+ v8 s1f;
+};
+
+struct S2
+{
+ struct S1 s2f1;
+ v8 s2f2;
+};
+
+int foo_s2f1 (int i)
+{
+ register struct S2 b asm ("xmm0");
+ return b.s2f1.s1f[i];
+}
+
+int mpx_test (int argc, const char **argv)
+{
+ printf ("%d\n", foo_s2f
[Committed] Add a few testcases
Hi,
While working on an out of tree optimization pass, I ran into a few
failures which was not represented by the testsuite so I am adding
them now.
Committed after a bootstrap/test on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
testsuite/ChangeLog:
* gcc.c-torture/compile/nested-3.c: New testcase.
* gcc.c-torture/execute/20170401-1.c: New testcase.
* gcc.c-torture/execute/20170401-2.c: New testcase.
Index: gcc.c-torture/compile/nested-3.c
===
--- gcc.c-torture/compile/nested-3.c(nonexistent)
+++ gcc.c-torture/compile/nested-3.c(working copy)
@@ -0,0 +1,18 @@
+struct a
+{
+ int t;
+ int t1;
+};
+
+int f(int i, int j)
+{
+ struct a *t;
+ struct a t1 = {i, j};
+ t = &t1;
+ auto int g(void) __attribute__((noinline));
+ int g(void)
+ {
+return t->t + t->t1;
+ }
+ return g();
+}
Index: gcc.c-torture/execute/20170401-1.c
===
--- gcc.c-torture/execute/20170401-1.c (nonexistent)
+++ gcc.c-torture/execute/20170401-1.c (working copy)
@@ -0,0 +1,53 @@
+/* PR45070 */
+extern void abort(void);
+
+struct packed_ushort {
+unsigned short ucs;
+} __attribute__((packed));
+
+struct source {
+int pos, length;
+};
+
+static int flag;
+
+static void __attribute__((noinline)) fetch(struct source *p)
+{
+p->length = 128;
+}
+
+static struct packed_ushort __attribute__((noinline)) next(struct source *p)
+{
+struct packed_ushort rv;
+
+if (p->pos >= p->length) {
+ if (flag) {
+ flag = 0;
+ fetch(p);
+ return next(p);
+ }
+ flag = 1;
+ rv.ucs = 0x;
+ return rv;
+}
+rv.ucs = 0;
+return rv;
+}
+
+int main(void)
+{
+struct source s;
+int i;
+
+s.pos = 0;
+s.length = 0;
+flag = 0;
+
+for (i = 0; i < 16; i++) {
+ struct packed_ushort rv = next(&s);
+ if ((i == 0 && rv.ucs != 0x)
+ || (i > 0 && rv.ucs != 0))
+ abort();
+}
+return 0;
+}
Index: gcc.c-torture/execute/20170401-2.c
===
--- gcc.c-torture/execute/20170401-2.c (nonexistent)
+++ gcc.c-torture/execute/20170401-2.c (working copy)
@@ -0,0 +1,29 @@
+void adjust_xy (short *, short *);
+
+struct adjust_template
+{
+ short kx_x;
+ short kx_y;
+};
+
+static struct adjust_template adjust = {1, 1};
+
+main ()
+{
+ short x = 1, y = 1;
+
+ adjust_xy (&x, &y);
+
+ if (x != 2)
+abort ();
+
+ exit (0);
+}
+
+void
+adjust_xy (x, y)
+ short *x;
+ short *y;
+{
+ *x = adjust.kx_x * *x + adjust.kx_y * *y;
+}
