[gcc r15-3136] rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:6e68c3df1540c5bafbb47343698bf4e270333fdb

commit r15-3136-g6e68c3df1540c5bafbb47343698bf4e270333fdb
Author: Peter Bergner 
Date:   Fri Aug 23 11:45:40 2024 -0500

rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

Our power8 swap optimization pass has some special handling for optimizing
swaps of TImode variables.  The test case reported in bugzilla uses a call
to  __atomic_compare_exchange, which introduces a variable of PTImode and
that does not get the same treatment as TImode leading to wrong code
generation.  The simple fix is to treat PTImode identically to TImode.

2024-08-23  Peter Bergner  

gcc/
PR target/116415
* config/rs6000/rs6000.h (TI_OR_PTI_MODE): New define.
* config/rs6000/rs6000-p8swap.cc (rs6000_analyze_swaps): Use it to
handle PTImode identically to TImode.

gcc/testsuite/
PR target/116415
* gcc.target/powerpc/pr116415.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-p8swap.cc  |  8 +++---
 gcc/config/rs6000/rs6000.h  |  2 ++
 gcc/testsuite/gcc.target/powerpc/pr116415.c | 42 +
 3 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-p8swap.cc 
b/gcc/config/rs6000/rs6000-p8swap.cc
index 639f477d7822..05fb76057f93 100644
--- a/gcc/config/rs6000/rs6000-p8swap.cc
+++ b/gcc/config/rs6000/rs6000-p8swap.cc
@@ -2469,10 +2469,10 @@ rs6000_analyze_swaps (function *fun)
mode = V4SImode;
}
 
- if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || mode == TImode)
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || TI_OR_PTI_MODE (mode))
{
  insn_entry[uid].is_relevant = 1;
- if (mode == TImode || mode == V1TImode
+ if (TI_OR_PTI_MODE (mode) || mode == V1TImode
  || FLOAT128_VECTOR_P (mode))
insn_entry[uid].is_128_int = 1;
  if (DF_REF_INSN_INFO (mention))
@@ -2497,10 +2497,10 @@ rs6000_analyze_swaps (function *fun)
  && ALTIVEC_OR_VSX_VECTOR_MODE (GET_MODE (SET_DEST (insn
mode = GET_MODE (SET_DEST (insn));
 
- if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || mode == TImode)
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || TI_OR_PTI_MODE (mode))
{
  insn_entry[uid].is_relevant = 1;
- if (mode == TImode || mode == V1TImode
+ if (TI_OR_PTI_MODE (mode) || mode == V1TImode
  || FLOAT128_VECTOR_P (mode))
insn_entry[uid].is_128_int = 1;
  if (DF_REF_INSN_INFO (mention))
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 703be908d944..d460eb065448 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -986,6 +986,8 @@ enum data_align { align_abi, align_opt, align_both };
   (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE)
\
|| (MODE) == V2DImode || (MODE) == V1TImode)
 
+#define TI_OR_PTI_MODE(mode) ((mode) == TImode || (mode) == PTImode)
+
 /* Post-reload, we can't use any new AltiVec registers, as we already
emitted the vrsave mask.  */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr116415.c 
b/gcc/testsuite/gcc.target/powerpc/pr116415.c
new file mode 100644
index ..08cc282e2c27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr116415.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* PR 116415: Verify our Power8 swap optimization pass doesn't incorrectly swap
+   PTImode values.  They should be handled identically to TImode values.  */
+
+#include 
+#include 
+#include 
+
+typedef union {
+  struct {
+uint64_t a;
+uint64_t b;
+  } t;
+  __uint128_t data;
+} Value;
+Value value, next;
+
+void
+bug (Value *val, Value *nxt)
+{
+  for (;;) {
+nxt->t.a = val->t.a + 1;
+nxt->t.b = val->t.b + 2;
+if (__atomic_compare_exchange (&val->data, &val->data, &nxt->data,
+  0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE))
+  break;
+  }
+}
+
+int
+main (void)
+{
+  bug (&value, &next);
+  printf ("%lu %lu\n", value.t.a, value.t.b);
+  if (value.t.a != 1 || value.t.b != 2)
+abort ();
+  return 0;
+}

[gcc/ibm/heads/gcc-12-branch] (21 commits) ibm: Merge up to top of releases/gcc-12

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-12-branch' was updated to point to:

 95d8973a6f8... ibm: Merge up to top of releases/gcc-12

It previously pointed to:

 3409c8aae4b... ibm: Merge up to top of releases/gcc-12

Diff:

Summary of changes (added commits):
---

  95d8973... ibm: Merge up to top of releases/gcc-12
  5f699cb... AVR: target/98762 - Handle partial clobber in movqi output. (*)
  ca6eea0... rs6000: Fix wrong RTL patterns for vector merge high/low sh (*)
  13f0528... rs6000: Fix wrong RTL patterns for vector merge high/low ch (*)
  c99573f... Daily bump. (*)
  4351caf... Daily bump. (*)
  5330558... AVR: target/88236, target/115726 - Fix __memx code generati (*)
  1d6c409... Daily bump. (*)
  1a837bc... Daily bump. (*)
  ae5bf1a... Daily bump. (*)
  96ef336... rs6000: Fix wrong RTL patterns for vector merge high/low wo (*)
  aba7335... Daily bump. (*)
  95ca5f4... [libstdc++] [testsuite] defer to check_vect_support* [PR115 (*)
  25cb136... Add support for -mcpu=grace (*)
  4f8dc81... Daily bump. (*)
  809d911... Daily bump. (*)
  4b69afd... libstdc++: Remove confusing text from status tables for rel (*)
  814b8cc... Daily bump. (*)
  0fd6ae9... rs6000: Don't clobber return value when eh_return called [P (*)
  f4affb9... Daily bump. (*)
  723716c... Daily bump. (*)

(*) This commit already exists in another branch.
Because the reference `refs/vendors/ibm/heads/gcc-12-branch' matches
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[gcc(refs/vendors/ibm/heads/gcc-12-branch)] ibm: Merge up to top of releases/gcc-12

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:95d8973a6f8fb29dee98b12f2d90f836620410b3

commit 95d8973a6f8fb29dee98b12f2d90f836620410b3
Merge: 3409c8aae4b 5f699cb08ee
Author: Peter Bergner 
Date:   Wed Jul 3 09:07:00 2024 -0500

ibm: Merge up to top of releases/gcc-12

2024-07-03  Peter Bergner  

Merge up to releases/gcc-12 5f699cb08eed44a903393f601009e9c6d0b59c59

Diff:

 gcc/ChangeLog  |  77 +++
 gcc/ChangeLog.ibm  |   4 +
 gcc/DATESTAMP  |   2 +-
 gcc/config/aarch64/aarch64-cores.def   |   1 +
 gcc/config/aarch64/aarch64-tune.md |   2 +-
 gcc/config/avr/avr.cc  |  35 +++-
 gcc/config/avr/avr.md  |  18 +-
 gcc/config/rs6000/altivec.md   | 222 +++--
 gcc/config/rs6000/rs6000-logue.cc  |   7 +-
 gcc/config/rs6000/rs6000.cc|  24 +--
 gcc/config/rs6000/rs6000.md|  15 ++
 gcc/config/rs6000/vsx.md   |  28 +--
 gcc/doc/invoke.texi|   4 +-
 gcc/testsuite/ChangeLog|  28 +++
 gcc/testsuite/g++.target/powerpc/pr106069.C| 119 +++
 .../gcc.target/avr/torture/pr88236-pr115726.c  | 115 +++
 gcc/testsuite/gcc.target/avr/torture/pr98762.c |  19 ++
 gcc/testsuite/gcc.target/powerpc/pr106069-1.c  |  39 
 gcc/testsuite/gcc.target/powerpc/pr106069-2.c  |  37 
 gcc/testsuite/gcc.target/powerpc/pr114846.c|  20 ++
 gcc/testsuite/gcc.target/powerpc/pr115355.c|  37 
 libstdc++-v3/ChangeLog |  23 +++
 libstdc++-v3/doc/html/manual/status.html   |  24 +--
 libstdc++-v3/doc/xml/manual/status_cxx1998.xml |   3 +-
 libstdc++-v3/doc/xml/manual/status_cxx2011.xml |   3 +-
 libstdc++-v3/doc/xml/manual/status_cxx2014.xml |   3 +-
 libstdc++-v3/doc/xml/manual/status_cxx2017.xml |   3 +-
 libstdc++-v3/doc/xml/manual/status_cxx2020.xml |   3 +-
 libstdc++-v3/doc/xml/manual/status_cxx2023.xml |   3 +-
 libstdc++-v3/doc/xml/manual/status_cxxtr1.xml  |   3 +-
 libstdc++-v3/doc/xml/manual/status_cxxtr24733.xml  |   3 +-
 .../experimental/simd/pr115454_find_last_set.cc|   1 -
 32 files changed, 791 insertions(+), 134 deletions(-)

diff --cc gcc/ChangeLog.ibm
index a07d18e2326,000..c7932696714
mode 100644,00..100644
--- a/gcc/ChangeLog.ibm
+++ b/gcc/ChangeLog.ibm
@@@ -1,51 -1,0 +1,55 @@@
++2024-07-03  Peter Bergner  
++
++  Merge up to releases/gcc-12 5f699cb08eed44a903393f601009e9c6d0b59c59
++
 +2024-06-22  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 218adac0fce6135fcb5c0c56911272687f05872b
 +
 +2024-05-29  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 342f577d8ea60c3473a6c1e66ef038b96f99f9d2
 +
 +2024-01-26  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 52dde3e8af9fac2e9c11ce5dfdad1f19546bbb64
 +
 +2023-11-21  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 a285310c50a868d27f63fc0297e56dd5d31a924b
 +
 +2023-09-14  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 6ca605af5995abf3d4013e7e146754509b8faddb
 +
 +2023-07-31  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 79ebcd30bda2cd00bf442a28717ec50ae0a8cd1d
 +
 +2023-04-11  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 908d9c7e6ed4be95d39b7b01056dda365f379947
 +
 +2023-03-27  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 4f41c4ff250709219a7c3eba27a62f8a4689412b
 +
 +2022-11-04  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 33561e870dc48966e8c7ede46e95032279a15423
 +
 +2022-10-17  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 fe7d74313736b8e1c30812bc49419f419bdf1c53
 +
 +2022-09-16  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 05cfd7b0677502d06a50ea6ff05d4445e194e3b9
 +
 +2022-08-19  Peter Bergner  
 +
 +  Merge up to releases/gcc-12 2d29d7b240d9ca87cbee5d90c846694125d293af
 +
 +2022-06-15  Peter Bergner  
 +
 +  Create ibm/gcc-12-branch which follows the releases/gcc-12 branch.

[gcc/ibm/heads/gcc-14-branch] (70 commits) ibm: Merge up to top of releases/gcc-14

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-14-branch' was updated to point to:

 a9332cff81c... ibm: Merge up to top of releases/gcc-14

It previously pointed to:

 96b284e64a7... ibm: Create the ibm/gcc-14-branch

Diff:

Summary of changes (added commits):
---

  a9332cf... ibm: Merge up to top of releases/gcc-14
  0f71e52... Daily bump. (*)
  6e1fb1f... Revert "Delete MALLOC_ABI_ALIGNMENT define from pa32-linux. (*)
  acde9f8... hppa: Fix ICE caused by mismatched predicate and constraint (*)
  3389a23... preprocessor: Create the parser before handling command-lin (*)
  5574450... AVR: target/98762 - Handle partial clobber in movqi output. (*)
  052f78d... rs6000: Fix wrong RTL patterns for vector merge high/low sh (*)
  0e495e8... rs6000: Fix wrong RTL patterns for vector merge high/low ch (*)
  88bfbab... Daily bump. (*)
  8eb4695... aarch64: Fix typo in aarch64-ldp-fusion.cc:combine_reg_note (*)
  5db1392... Daily bump. (*)
  7249b3c... AVR: target/88236, target/115726 - Fix __memx code generati (*)
  37bbd2c... c: Fix ICE related to incomplete structures in C23 [PR11493 (*)
  78bd4b1... Daily bump. (*)
  603b344... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
  9f14748... Fortran: fix passing of optional dummy as actual to optiona (*)
  b31e190... Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR1 (*)
  4fe3fff... Daily bump. (*)
  47cbc76... Daily bump. (*)
  e6b115b... c++: decltype of capture proxy of ref [PR115504] (*)
  a00a8d4... c++: alias CTAD and copy deduction guide [PR115198] (*)
  33a9c4d... c++: using non-dep array var of unknown bound [PR115358] (*)
  d5e352a... libstdc++: Fix std::format for chrono::duration with unsign (*)
  ef8b60d... rs6000: Fix wrong RTL patterns for vector merge high/low wo (*)
  15d304d... Daily bump. (*)
  a8b77a6... libstdc++: Replace viewcvs links in docs with cgit links (*)
  b70af0b... [libstdc++] [testsuite] defer to check_vect_support* [PR115 (*)
  c2878a9... aarch64: Add support for -mcpu=grace (*)
  6e6f10c... tree-ssa-pre.c/115214(ICE in find_or_generate_expression, a (*)
  f9cc628... Daily bump. (*)
  532357b... Daily bump. (*)
  f91d9b3... libstdc++: Remove confusing text from status tables for rel (*)
  b383719... Fix PR c/115587, uninitialized variable in c_parser_omp_loo (*)
  4bf93fc... SPARC: fix internal error with -mv8plus on 64-bit Linux (*)
  b7157f3... c-family: Add Warning property to Wnrvo option [PR115624] (*)
  faf5994... Daily bump. (*)
  2b5e8f9... rs6000: Don't clobber return value when eh_return called [P (*)
  1a2329d... Daily bump. (*)
  1735b86... Daily bump. (*)
  70d9d92... Daily bump. (*)
  9421f02... AArch64: Fix cpu features initialization [PR115342] (*)
  a851931... libstdc++: Fix test on x86_64 and non-simd targets (*)
  a16f47f... Build: Set gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips (*)
  272e8c9... tree-optimization/115278 - fix DSE in if-conversion wrt vol (*)
  65e2586... tree-optimization/115508 - fix ICE with SLP scheduling and  (*)
  85d32e6... Avoid SLP_REPRESENTATIVE access for VEC_PERM in SLP schedul (*)
  30fca2c... Daily bump. (*)
  e77f314... libstdc++: Fix find_last_set(simd_mask) to ignore padding b (*)
  d26fa1c... vshuf-mem.C: Make -march=z14 depend on s390_vxe (*)
  b4e4997... testsuite: Add -Wno-psabi to vshuf-mem.C test (*)
  166c9f9... IBM Z: Fix ICE in expand_perm_as_replicate (*)
  f79e909... bitint: Fix up lowering of COMPLEX_EXPR [PR115544] (*)
  74a58c3... diagnostics: Fix add_misspelling_candidates [PR115440] (*)
  946f26e... Daily bump. (*)
  6f6103c... Daily bump. (*)
  789f055... Daily bump. (*)
  9226487... c-family: Fix -Warray-compare warning ICE [PR115290] (*)
  5be6d9d... c++: Fix up floating point conversion rank comparison for _ (*)
  20cda2e... c++: undeclared identifier in requires-clause [PR99678] (*)
  4df8640... c++: ICE w/ ambig and non-strictly-viable cands [PR115239] (*)
  9583f78... c++: visibility wrt concept-id as targ [PR115283] (*)
  0ed63e3... s390: testsuite: Fix ifcvt-one-insn-bool.c (*)
  8f124e6... s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR1095 (*)
  13a09f3... Daily bump. (*)
  a4f8e9e... Daily bump. (*)
  3fe255f... riscv: Allocate enough space to strcpy() string (*)
  6b2fc15... Daily bump. (*)
  75251f5... libstdc++: Fix declaration of posix_memalign for freestandi (*)
  b740c09... Daily bump. (*)
  8bd6e40... Daily bump. (*)

(*) This commit already exists in another branch.
Because the reference `refs/vendors/ibm/heads/gcc-14-branch' matches
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[gcc/ibm/heads/gcc-13-branch] (83 commits) ibm: Merge up to top of releases/gcc-13

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-13-branch' was updated to point to:

 b7341a9059d... ibm: Merge up to top of releases/gcc-13

It previously pointed to:

 c3db5f495a1... ibm: Merge up to top of releases/gcc-13

Diff:

Summary of changes (added commits):
---

  b7341a9... ibm: Merge up to top of releases/gcc-13
  a26c560... Daily bump. (*)
  ecd6ebe... hppa: Fix ICE caused by mismatched predicate and constraint (*)
  ba9fef4... AVR: target/98762 - Handle partial clobber in movqi output. (*)
  bab38d9... rs6000: Fix wrong RTL patterns for vector merge high/low sh (*)
  ffdd377... rs6000: Fix wrong RTL patterns for vector merge high/low ch (*)
  2dd3934... Daily bump. (*)
  b4abe8f... Daily bump. (*)
  743575b... AVR: target/88236, target/115726 - Fix __memx code generati (*)
  461c846... Daily bump. (*)
  5a4ea0b... Daily bump. (*)
  ae1f6eb... Daily bump. (*)
  84cae12... libstdc++: Replace viewcvs links in docs with cgit links (*)
  4b64a10... libstdc++: Fix std::format for chrono::duration with unsign (*)
  361bfce... rs6000: Fix wrong RTL patterns for vector merge high/low wo (*)
  e65b1a1... Daily bump. (*)
  5aa9ed0... AArch64: Fix strict-align cpymem/setmem [PR103100] (*)
  c93a9bb... aarch64: Fix +nocrypto handling (*)
  3de1c49... [libstdc++] [testsuite] defer to check_vect_support* [PR115 (*)
  952ea32... Add support for -mcpu=grace (*)
  d081007... Daily bump. (*)
  563aa24... Daily bump. (*)
  bc6e4bd... libstdc++: Remove confusing text from status tables for rel (*)
  2cb5a44... Daily bump. (*)
  dd54ed4... rs6000: Don't clobber return value when eh_return called [P (*)
  db36cf4... Daily bump. (*)
  464c4af... Daily bump. (*)
  df9c225... Daily bump. (*)
  c335e34... libstdc++: Fix test on x86_64 and non-simd targets (*)
  fbd088a... libstdc++: Fix find_last_set(simd_mask) to ignore padding b (*)
  701de95... Daily bump. (*)
  e216eb1... diagnostics: Fix add_misspelling_candidates [PR115440] (*)
  abde654... Daily bump. (*)
  0530884... Fortran: fix ALLOCATE with SOURCE=, zero-length character [ (*)
  41ea263... Daily bump. (*)
  3ff2339... Daily bump. (*)
  be14e6c... c-family: Fix -Warray-compare warning ICE [PR115290] (*)
  6d0a0c5... c++: Fix up floating point conversion rank comparison for _ (*)
  a62db39... Daily bump. (*)
  663be6b... Daily bump. (*)
  072e71f... Daily bump. (*)
  24dbdd2... libstdc++: Fix declaration of posix_memalign for freestandi (*)
  7da2f89... Daily bump. (*)
  341342d... Daily bump. (*)
  113a104... arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR11 (*)
  dfab685... testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115 (*)
  bf3ffb4... arm: Zero/Sign extends for CMSE security on Armv8-M.baselin (*)
  3f5d0ca... Daily bump. (*)
  6eb0e93... Fix building JIT with musl libc [PR115442] (*)
  ef21690... libstdc++: Fix simd conversion for -fno-signed-char f (*)
  0efc270... libstdc++: Avoid MMX return types from __builtin_shufflevec (*)
  26113c2... libstdc++: Use __builtin_shufflevector for simd split and c (*)
  7813d94... c: Fix up pointer types to may_alias structures [PR114493] (*)
  865d60a... fold-const: Fix up CLZ handling in tree_call_nonnegative_wa (*)
  f9db8b0... builtins: Force SAVE_EXPR for __builtin_{add,sub,mul}_overf (*)
  308ca60... invoke.texi: Clarify -march=lujiazui (*)
  50b5019... rs6000: Fix up PCH in --enable-host-pie builds [PR115324] (*)
  8deaab6... combine: Fix up simplify_compare_const [PR115092] (*)
  f2ef3ac... Daily bump. (*)
  ef494b1... Fix crash on access-to-incomplete type (*)
  02025fb... Add testcase for PR ada/114398 (*)
  e54d909... ada: Storage_Error in indirect call to function returning l (*)
  7067b7e... Daily bump. (*)
  cd8dc16... Daily bump. (*)
  e11fb72... Daily bump. (*)
  e4f85ea... Disable FMADD in chains for Zen4 and generic (*)
  3cf6c1f... Daily bump. (*)
  c0f2293... Daily bump. (*)
  16fe81c... Daily bump. (*)
  38360ba... Daily bump. (*)
  ed06ca8... alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] (*)
  218246b... Daily bump. (*)
  6634ff0... Daily bump. (*)
  c57d73f... AVR: tree-optimization/115307 - Work around isinf bloat fro (*)
  b45d728... AVR: target/115317 - Make isinf(-Inf) return -1. (*)
  3687dcf... libstdc++: Replace link to gcc-4.3.2 docs in manual [PR1152 (*)
  acdf0f7... Daily bump. (*)
  2602b71... vect: Tighten vect_determine_precisions_from_range [PR11328 (*)
  0836216... vect: Fix access size alignment assumption [PR115192] (*)
  173f876... i386: Fix ix86_option override after change [PR 113719] (*)
  d0fb9d2... Daily bump. (*)
  3be8fa7... MIPS16: Mark $2/$3 as clobbered if GP is used (*)
  2618cda... Daily bump. (*)

(*) This commit already exists in another branch.
Because the reference `refs/vendors/ibm/heads/gcc-13-branch' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/vendors/ibm/heads/gcc-13-branch)] ibm: Merge up to top of releases/gcc-13

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:b7341a9059d7a4ff8fcbffd7b968209a732d0163

commit b7341a9059d7a4ff8fcbffd7b968209a732d0163
Merge: c3db5f495a1 a26c560d3f6
Author: Peter Bergner 
Date:   Wed Jul 3 22:36:49 2024 -0500

ibm: Merge up to top of releases/gcc-13

2024-07-03  Peter Bergner  

Merge up to releases/gcc-13 a26c560d3f679d5237dd5191869e845740b94759

Diff:

 gcc/ChangeLog  | 333 +
 gcc/ChangeLog.ibm  |   4 +
 gcc/DATESTAMP  |   2 +-
 gcc/ada/ChangeLog  |  13 +
 gcc/ada/exp_ch6.adb|  11 +-
 gcc/ada/exp_util.adb   |   6 +
 gcc/ada/sem_ch6.adb|  12 +-
 gcc/builtins.cc|  16 +-
 gcc/c-family/ChangeLog |  10 +
 gcc/c-family/c-warn.cc |  13 +-
 gcc/c/ChangeLog|  10 +
 gcc/c/c-decl.cc|  15 +
 gcc/combine.cc |   6 +-
 gcc/common/config/aarch64/aarch64-common.cc|  35 ++-
 gcc/config/aarch64/aarch64-c.cc|   2 +-
 gcc/config/aarch64/aarch64-cores.def   |   2 +
 gcc/config/aarch64/aarch64-tune.md |   2 +-
 gcc/config/aarch64/aarch64.cc  |  52 ++--
 gcc/config/aarch64/aarch64.h   |  10 +-
 gcc/config/aarch64/aarch64.md  |   4 +-
 gcc/config/alpha/alpha.md  |  21 +-
 gcc/config/alpha/constraints.md|   2 +-
 gcc/config/arm/arm.cc  |  76 -
 gcc/config/avr/avr.cc  |  35 ++-
 gcc/config/avr/avr.md  |  34 ++-
 gcc/config/i386/i386-options.cc|  10 +-
 gcc/config/i386/x86-tune.def   |   2 +-
 gcc/config/mips/mips.cc|  11 +-
 gcc/config/pa/pa.md|  18 --
 gcc/config/rs6000/altivec.md   | 222 ++
 gcc/config/rs6000/rs6000-builtin.cc|   2 +-
 gcc/config/rs6000/rs6000-c.cc  |  62 ++--
 gcc/config/rs6000/rs6000-gen-builtins.cc   |  72 ++---
 gcc/config/rs6000/rs6000-logue.cc  |   7 +-
 gcc/config/rs6000/rs6000.cc|  24 +-
 gcc/config/rs6000/rs6000.md|  15 +
 gcc/config/rs6000/vsx.md   |  28 +-
 gcc/cp/ChangeLog   |  11 +
 gcc/cp/typeck.cc   |   3 +
 gcc/doc/invoke.texi|  10 +-
 gcc/fold-const.cc  |  18 +-
 gcc/fortran/ChangeLog  |  10 +
 gcc/fortran/trans-stmt.cc  |   3 +-
 gcc/jit/ChangeLog  |   9 +
 gcc/jit/jit-recording.cc   |   1 +
 gcc/opts-common.cc |   6 +-
 gcc/testsuite/ChangeLog| 188 
 gcc/testsuite/c-c++-common/Warray-compare-3.c  |  13 +
 gcc/testsuite/g++.dg/cpp1z/pr115440.C  |   8 +
 gcc/testsuite/g++.dg/cpp23/ext-floating18.C|  26 ++
 gcc/testsuite/g++.target/powerpc/pr106069.C| 119 
 gcc/testsuite/gcc.c-torture/execute/pr108789.c |  39 +++
 gcc/testsuite/gcc.dg/pr114493-1.c  |  19 ++
 gcc/testsuite/gcc.dg/pr114493-2.c  |  26 ++
 gcc/testsuite/gcc.dg/pr114902.c|  23 ++
 gcc/testsuite/gcc.dg/pr115092.c|  16 +
 gcc/testsuite/gcc.dg/vect/pr113281-1.c |  17 ++
 gcc/testsuite/gcc.dg/vect/pr113281-2.c |  50 
 gcc/testsuite/gcc.dg/vect/pr113281-3.c |  39 +++
 gcc/testsuite/gcc.dg/vect/pr113281-4.c |  55 
 gcc/testsuite/gcc.dg/vect/pr113281-5.c |  66 
 gcc/testsuite/gcc.dg/vect/pr115192.c   |  28 ++
 gcc/testsuite/gcc.target/aarch64/options_set_27.c  |   9 +
 gcc/testsuite/gcc.target/aarch64/options_set_4.c   |   2 +-
 gcc/testsuite/gcc.target/alpha/pr115297.c  |  13 +
 gcc/testsuite/gcc.target/arm/cmse/extend-return.c  |  62 +++-
 .../gcc.target/avr/torture/pr115307-isinf.c|  21 ++
 .../gcc.target/avr/torture/pr115317-isinf.c|  55 
 .../gcc.target/avr/torture/pr88236-pr115726.c  | 115 +++
 gcc/testsuite/gcc.target/avr/torture/pr98762.c |  19 ++
 gcc/testsuite/gcc.target/powerpc/pr106069-1.c  |  39 +++
 gcc/testsuite/gcc.target/powerpc/pr106069-2.c  |  37 +++
 gcc/testsuite/gcc.target/powerpc/pr114846.c|  20 ++
 gcc/testsuite/gcc.target/powerpc/pr115355.c|  37 +++
 .../gfortran.dg/allocate_with_source_32.f9

[gcc r15-2080] rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:a05c3d23d1e1c8d2971b123804fc7a61a3561adb

commit r15-2080-ga05c3d23d1e1c8d2971b123804fc7a61a3561adb
Author: Peter Bergner 
Date:   Wed Jun 19 16:07:29 2024 -0500

rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759]

We currently only emit the ROP-protect hash* insns for Power10, where the
insns were added to the architecture.  We want to emit them for earlier
cpus (where they operate as NOPs), so that if those older binaries are
ever executed on a Power10, then they'll be protected from ROP attacks.
Binutils accepts hashst and hashchk back to Power8, so change GCC to emit
them for Power8 and later.  This matches clang's behavior.

2024-06-19  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Use 
TARGET_POWER8.
(rs6000_emit_prologue): Likewise.
* config/rs6000/rs6000.md (hashchk): Likewise.
(hashst): Likewise.
Fix whitespace.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-2.c: New test.
* lib/target-supports.exp (rop_ok): Use
check_effective_target_has_arch_pwr8.

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc |  6 +++---
 gcc/config/rs6000/rs6000.md   |  6 +++---
 gcc/testsuite/gcc.target/powerpc/pr114759-2.c | 17 +
 gcc/testsuite/lib/target-supports.exp |  2 +-
 4 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 193e2122c0f9..48f406330714 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -716,7 +716,7 @@ rs6000_stack_info (void)
   info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
   info->rop_hash_size = 0;
 
-  if (TARGET_POWER10
+  if (TARGET_POWER8
   && info->calls_p
   && DEFAULT_ABI == ABI_ELFv2
   && rs6000_rop_protect)
@@ -3272,7 +3272,7 @@ rs6000_emit_prologue (void)
   /* NOTE: The hashst isn't needed if we're going to do a sibcall,
  but there's no way to know that here.  Harmless except for
  performance, of course.  */
-  if (TARGET_POWER10 && rs6000_rop_protect && info->rop_hash_size != 0)
+  if (TARGET_POWER8 && rs6000_rop_protect && info->rop_hash_size != 0)
 {
   gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
@@ -5051,7 +5051,7 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type)
 
   /* The ROP hash check must occur after the stack pointer is restored
  (since the hash involves r1), and is not performed for a sibcall.  */
-  if (TARGET_POWER10
+  if (TARGET_POWER8
   && rs6000_rop_protect
   && info->rop_hash_size != 0
   && epilogue_type != EPILOGUE_TYPE_SIBCALL)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 276a5c9cf2d3..679aac5a10d5 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15808,9 +15808,9 @@
 
 (define_insn "hashst"
   [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
-(unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
+   (unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
UNSPEC_HASHST))]
-  "TARGET_POWER10 && rs6000_rop_protect"
+  "TARGET_POWER8 && rs6000_rop_protect"
 {
   static char templ[32];
   const char *p = rs6000_privileged ? "p" : "";
@@ -15823,7 +15823,7 @@
   [(unspec_volatile [(match_operand:DI 0 "int_reg_operand" "r")
 (match_operand:DI 1 "simple_offsettable_mem_operand" "m")]
UNSPEC_HASHCHK)]
-  "TARGET_POWER10 && rs6000_rop_protect"
+  "TARGET_POWER8 && rs6000_rop_protect"
 {
   static char templ[32];
   const char *p = rs6000_privileged ? "p" : "";
diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-2.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-2.c
new file mode 100644
index ..3881ebd416e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mrop-protect" } */
+/* { dg-require-effective-target rop_ok } Only enable on supported ABIs.  */
+
+/* Verify we generate ROP-protect hash insns when compiling for Power8.  */
+
+extern void foo (void);
+
+int
+bar (void)
+{
+  foo ();
+  return 5;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index f001c28072f6..daa0c75d2bc3 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7452,7 +7452,7 @@ proc check_effective_target_powerpc_elfv2 { } {
 # Return 1 if this is a PowerPC target supporting -mrop-protect
 
 proc check_effective_

[gcc r15-2081] rs6000: Error on CPUs and ABIs that don't support the ROP protection insns [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:6f2bab9b5d1ce1914c748b7dcd8638dafaa98df7

commit r15-2081-g6f2bab9b5d1ce1914c748b7dcd8638dafaa98df7
Author: Peter Bergner 
Date:   Mon Jul 15 16:57:32 2024 -0500

rs6000: Error on CPUs and ABIs that don't support the ROP protection insns 
[PR114759]

We currently silently ignore the -mrop-protect option for old CPUs we don't
support with the ROP hash insns, but we throw an error for unsupported ABIs.
This patch treats unsupported CPUs and ABIs similarly by throwing an error
both both.  This matches clang behavior and allows us to simplify our tests
in the code that generates our prologue and epilogue code.

2024-06-26  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000.cc (rs6000_option_override_internal): 
Disallow
CPUs and ABIs that do no support the ROP protection insns.
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Remove now
unneeded tests.
(rs6000_emit_prologue): Likewise.
Remove unneeded gcc_assert.
(rs6000_emit_epilogue): Likewise.
* config/rs6000/rs6000.md: Likewise.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-3.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 22 ++
 gcc/config/rs6000/rs6000.cc   | 12 
 gcc/config/rs6000/rs6000.md   |  4 ++--
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c | 19 +++
 4 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 48f406330714..edc0d6c8f520 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -716,17 +716,11 @@ rs6000_stack_info (void)
   info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
   info->rop_hash_size = 0;
 
-  if (TARGET_POWER8
-  && info->calls_p
-  && DEFAULT_ABI == ABI_ELFv2
-  && rs6000_rop_protect)
+  /* If we want ROP protection and this function makes a call, indicate
+ we need to create a stack slot to save the hashed return address in.  */
+  if (rs6000_rop_protect
+  && info->calls_p)
 info->rop_hash_size = 8;
-  else if (rs6000_rop_protect && DEFAULT_ABI != ABI_ELFv2)
-{
-  /* We can't check this in rs6000_option_override_internal since
-DEFAULT_ABI isn't established yet.  */
-  error ("%qs requires the ELFv2 ABI", "-mrop-protect");
-}
 
   /* Determine if we need to save the condition code registers.  */
   if (save_reg_p (CR2_REGNO)
@@ -3272,9 +3266,8 @@ rs6000_emit_prologue (void)
   /* NOTE: The hashst isn't needed if we're going to do a sibcall,
  but there's no way to know that here.  Harmless except for
  performance, of course.  */
-  if (TARGET_POWER8 && rs6000_rop_protect && info->rop_hash_size != 0)
+  if (info->rop_hash_size)
 {
-  gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx addr = gen_rtx_PLUS (Pmode, stack_ptr,
   GEN_INT (info->rop_hash_save_offset));
@@ -5051,12 +5044,9 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type)
 
   /* The ROP hash check must occur after the stack pointer is restored
  (since the hash involves r1), and is not performed for a sibcall.  */
-  if (TARGET_POWER8
-  && rs6000_rop_protect
-  && info->rop_hash_size != 0
+  if (info->rop_hash_size
   && epilogue_type != EPILOGUE_TYPE_SIBCALL)
 {
-  gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx addr = gen_rtx_PLUS (Pmode, stack_ptr,
   GEN_INT (info->rop_hash_save_offset));
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 195f2af9062e..d4eec5c472f8 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4844,6 +4844,18 @@ rs6000_option_override_internal (bool global_init_p)
}
 }
 
+  /* We only support ROP protection on certain targets.  */
+  if (rs6000_rop_protect)
+{
+  /* Disallow CPU targets we don't support.  */
+  if (!TARGET_POWER8)
+   error ("%<-mrop-protect%> requires %<-mcpu=power8%> or later");
+
+  /* Disallow ABI targets we don't support.  */
+  if (DEFAULT_ABI != ABI_ELFv2)
+   error ("%<-mrop-protect%> requires the ELFv2 ABI");
+}
+
   /* Initialize all of the registers.  */
   rs6000_init_hard_regno_mode_ok (global_init_p);
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 679aac5a10d5..45a4a8cfb907 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15810,7 +15810,7 @@
   [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
(unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
  

[gcc r15-2144] rs6000: Fix .machine cpu selection w/ altivec [PR97367]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:6962835bca3e6bef0f6ceae84a7814138b08b8a5

commit r15-2144-g6962835bca3e6bef0f6ceae84a7814138b08b8a5
Author: René Rebe 
Date:   Fri Jul 12 21:17:08 2024 +

rs6000: Fix .machine cpu selection w/ altivec [PR97367]

There are various non-IBM CPUs with altivec, so we cannot use that
flag to determine which .machine cpu to use, so ignore it.
Emit an additional ".machine altivec" if Altivec is enabled so
that the assembler doesn't require an explicit -maltivec option
to assemble any Altivec instructions for those targets where
the ".machine cpu" is insufficient to enable Altivec.  For example,
-mcpu=G5 emits a ".machine power4".

2024-07-18  René Rebe  
Peter Bergner  

gcc/
PR target/97367
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Do not 
consider
OPTION_MASK_ALTIVEC.
(emit_asm_machine): For Altivec compiles, emit a ".machine altivec".

gcc/testsuite/
PR target/97367
* gcc.target/powerpc/pr97367.c: New test.

Signed-off-by: René Rebe 

Diff:
---
 gcc/config/rs6000/rs6000.cc|  5 -
 gcc/testsuite/gcc.target/powerpc/pr97367.c | 13 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2c0a7fc8cefa..5ed64b1e6866 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5896,7 +5896,8 @@ rs6000_machine_from_flags (void)
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
-  flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | 
OPTION_MASK_ISEL);
+  flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
+| OPTION_MASK_ALTIVEC);
 
   if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
 return "power10";
@@ -5921,6 +5922,8 @@ void
 emit_asm_machine (void)
 {
   fprintf (asm_out_file, "\t.machine %s\n", rs6000_machine);
+  if (TARGET_ALTIVEC)
+fprintf (asm_out_file, "\t.machine altivec\n");
 }
 #endif
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97367.c 
b/gcc/testsuite/gcc.target/powerpc/pr97367.c
new file mode 100644
index ..ef269a5f9134
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97367.c
@@ -0,0 +1,13 @@
+/* PR target/97367 */
+/* { dg-options "-mdejagnu-cpu=G5" } */
+
+/* Verify we emit a ".machine power4" and ".machine altivec" rather
+   than a ".machine power7".  */
+
+int dummy (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.machine power4\M} } } */
+/* { dg-final { scan-assembler {\.machine altivec\M} } } */

[gcc r15-2155] rs6000: Catch unsupported ABI errors when using -mrop-protect [PR114759, PR115988]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:b2f47a5c1d5204131660ea0372a08e692df8844e

commit r15-2155-gb2f47a5c1d5204131660ea0372a08e692df8844e
Author: Peter Bergner 
Date:   Thu Jul 18 18:01:46 2024 -0500

rs6000: Catch unsupported ABI errors when using -mrop-protect 
[PR114759,PR115988]

2024-07-18  Peter Bergner  

gcc/testsuite/
PR target/114759
PR target/115988
* gcc.target/powerpc/pr114759-3.c: Catch unsupported ABI errors.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-3.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
index 6770a9aec3b5..e2f1d42e111f 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
@@ -2,7 +2,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -mdejagnu-cpu=power7 -mrop-protect" } */
 
-/* Verify we emit an error if we use -mrop-protect with an unsupported cpu.  */
+/* Verify we emit an error if we use -mrop-protect with an unsupported cpu
+   or ABI.  */
 
 extern void foo (void);
 
@@ -17,3 +18,4 @@ bar (void)
in the final line (which is all that dg-error inspects). Hence, we have
to tell dg-error to ignore the line number.  */
 /* { dg-error "'-mrop-protect' requires '-mcpu=power8'" "PR114759" { target 
*-*-* } 0 } */
+/* { dg-error "'-mrop-protect' requires the ELFv2 ABI" "PR114759" { target { ! 
rop_ok } } 0 } */

[gcc r14-10476] rs6000: Fix .machine cpu selection w/ altivec [PR97367]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:1205104bbef40abe3baa5965a676f3b0f68971dd

commit r14-10476-g1205104bbef40abe3baa5965a676f3b0f68971dd
Author: René Rebe 
Date:   Fri Jul 12 21:17:08 2024 +

rs6000: Fix .machine cpu selection w/ altivec [PR97367]

There are various non-IBM CPUs with altivec, so we cannot use that
flag to determine which .machine cpu to use, so ignore it.
Emit an additional ".machine altivec" if Altivec is enabled so
that the assembler doesn't require an explicit -maltivec option
to assemble any Altivec instructions for those targets where
the ".machine cpu" is insufficient to enable Altivec.  For example,
-mcpu=G5 emits a ".machine power4".

2024-07-18  René Rebe  
Peter Bergner  

gcc/
PR target/97367
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Do not 
consider
OPTION_MASK_ALTIVEC.
(emit_asm_machine): For Altivec compiles, emit a ".machine altivec".

gcc/testsuite/
PR target/97367
* gcc.target/powerpc/pr97367.c: New test.

Signed-off-by: René Rebe 
(cherry picked from commit 6962835bca3e6bef0f6ceae84a7814138b08b8a5)

Diff:
---
 gcc/config/rs6000/rs6000.cc|  5 -
 gcc/testsuite/gcc.target/powerpc/pr97367.c | 13 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 11cb622fe1f1..7b80c98cfd83 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5869,7 +5869,8 @@ rs6000_machine_from_flags (void)
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
-  flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | 
OPTION_MASK_ISEL);
+  flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
+| OPTION_MASK_ALTIVEC);
 
   if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
 return "power10";
@@ -5894,6 +5895,8 @@ void
 emit_asm_machine (void)
 {
   fprintf (asm_out_file, "\t.machine %s\n", rs6000_machine);
+  if (TARGET_ALTIVEC)
+fprintf (asm_out_file, "\t.machine altivec\n");
 }
 #endif
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97367.c 
b/gcc/testsuite/gcc.target/powerpc/pr97367.c
new file mode 100644
index ..ef269a5f9134
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97367.c
@@ -0,0 +1,13 @@
+/* PR target/97367 */
+/* { dg-options "-mdejagnu-cpu=G5" } */
+
+/* Verify we emit a ".machine power4" and ".machine altivec" rather
+   than a ".machine power7".  */
+
+int dummy (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.machine power4\M} } } */
+/* { dg-final { scan-assembler {\.machine altivec\M} } } */

[gcc r13-8925] rs6000: Fix .machine cpu selection w/ altivec [PR97367]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:44fe2c06a156a63f7ae359fd5dd3ce98afa3e92a

commit r13-8925-g44fe2c06a156a63f7ae359fd5dd3ce98afa3e92a
Author: René Rebe 
Date:   Fri Jul 12 21:17:08 2024 +

rs6000: Fix .machine cpu selection w/ altivec [PR97367]

There are various non-IBM CPUs with altivec, so we cannot use that
flag to determine which .machine cpu to use, so ignore it.
Emit an additional ".machine altivec" if Altivec is enabled so
that the assembler doesn't require an explicit -maltivec option
to assemble any Altivec instructions for those targets where
the ".machine cpu" is insufficient to enable Altivec.  For example,
-mcpu=G5 emits a ".machine power4".

2024-07-18  René Rebe  
Peter Bergner  

gcc/
PR target/97367
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Do not 
consider
OPTION_MASK_ALTIVEC.
(emit_asm_machine): For Altivec compiles, emit a ".machine altivec".

gcc/testsuite/
PR target/97367
* gcc.target/powerpc/pr97367.c: New test.

Signed-off-by: René Rebe 
(cherry picked from commit 6962835bca3e6bef0f6ceae84a7814138b08b8a5)

Diff:
---
 gcc/config/rs6000/rs6000.cc|  5 -
 gcc/testsuite/gcc.target/powerpc/pr97367.c | 13 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 76eb89ad5298..29475ffcb7f0 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5894,7 +5894,8 @@ rs6000_machine_from_flags (void)
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
-  flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | 
OPTION_MASK_ISEL);
+  flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
+| OPTION_MASK_ALTIVEC);
 
   if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
 return "power10";
@@ -5919,6 +5920,8 @@ void
 emit_asm_machine (void)
 {
   fprintf (asm_out_file, "\t.machine %s\n", rs6000_machine);
+  if (TARGET_ALTIVEC)
+fprintf (asm_out_file, "\t.machine altivec\n");
 }
 #endif
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97367.c 
b/gcc/testsuite/gcc.target/powerpc/pr97367.c
new file mode 100644
index ..ef269a5f9134
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97367.c
@@ -0,0 +1,13 @@
+/* PR target/97367 */
+/* { dg-options "-mdejagnu-cpu=G5" } */
+
+/* Verify we emit a ".machine power4" and ".machine altivec" rather
+   than a ".machine power7".  */
+
+int dummy (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.machine power4\M} } } */
+/* { dg-final { scan-assembler {\.machine altivec\M} } } */

[gcc r12-10628] rs6000: Fix .machine cpu selection w/ altivec [PR97367]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:319b57fb02b52ba9036c00dda36ff28d8274e13d

commit r12-10628-g319b57fb02b52ba9036c00dda36ff28d8274e13d
Author: René Rebe 
Date:   Fri Jul 12 21:17:08 2024 +

rs6000: Fix .machine cpu selection w/ altivec [PR97367]

There are various non-IBM CPUs with altivec, so we cannot use that
flag to determine which .machine cpu to use, so ignore it.
Emit an additional ".machine altivec" if Altivec is enabled so
that the assembler doesn't require an explicit -maltivec option
to assemble any Altivec instructions for those targets where
the ".machine cpu" is insufficient to enable Altivec.  For example,
-mcpu=G5 emits a ".machine power4".

2024-07-18  René Rebe  
Peter Bergner  

gcc/
PR target/97367
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Do not 
consider
OPTION_MASK_ALTIVEC.
(emit_asm_machine): For Altivec compiles, emit a ".machine altivec".

gcc/testsuite/
PR target/97367
* gcc.target/powerpc/pr97367.c: New test.

Signed-off-by: René Rebe 
(cherry picked from commit 6962835bca3e6bef0f6ceae84a7814138b08b8a5)

Diff:
---
 gcc/config/rs6000/rs6000.cc|  5 -
 gcc/testsuite/gcc.target/powerpc/pr97367.c | 13 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 34be43c9f84c..03893b2cf8bd 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5813,7 +5813,8 @@ rs6000_machine_from_flags (void)
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
-  flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | 
OPTION_MASK_ISEL);
+  flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
+| OPTION_MASK_ALTIVEC);
 
   if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
 return "power10";
@@ -5838,6 +5839,8 @@ void
 emit_asm_machine (void)
 {
   fprintf (asm_out_file, "\t.machine %s\n", rs6000_machine);
+  if (TARGET_ALTIVEC)
+fprintf (asm_out_file, "\t.machine altivec\n");
 }
 #endif
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97367.c 
b/gcc/testsuite/gcc.target/powerpc/pr97367.c
new file mode 100644
index ..ef269a5f9134
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97367.c
@@ -0,0 +1,13 @@
+/* PR target/97367 */
+/* { dg-options "-mdejagnu-cpu=G5" } */
+
+/* Verify we emit a ".machine power4" and ".machine altivec" rather
+   than a ".machine power7".  */
+
+int dummy (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.machine power4\M} } } */
+/* { dg-final { scan-assembler {\.machine altivec\M} } } */

[gcc r14-10490] rs6000: Update ELFv2 stack frame comment showing the correct ROP save location

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:c33532c59752723a4f7dfc305545b34c61281380

commit r14-10490-gc33532c59752723a4f7dfc305545b34c61281380
Author: Peter Bergner 
Date:   Fri Jun 7 16:03:08 2024 -0500

rs6000: Update ELFv2 stack frame comment showing the correct ROP save 
location

The ELFv2 stack frame layout comment in rs6000-logue.cc shows the ROP
hash save slot in the wrong location.  Update the comment to show the
correct ROP hash save location in the frame.

2024-06-07  Peter Bergner  

gcc/
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Update comment.

(cherry picked from commit e91cf26a954a5c1bf431e36f3a1e69f94e9fa4fe)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index bd5d56ba002c..d61a25a51264 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -591,21 +591,21 @@ rs6000_savres_strategy (rs6000_stack_t *info,
+---+
| Parameter save area (+padding*) (P)   |  32
+---+
-   | Optional ROP hash slot (R)|  32+P
+   | Alloca space (A)  |  32+P
+---+
-   | Alloca space (A)  |  32+P+R
+   | Local variable space (L)  |  32+P+A
+---+
-   | Local variable space (L)  |  32+P+R+A
+   | Optional ROP hash slot (R)|  32+P+A+L
+---+
-   | Save area for AltiVec registers (W)   |  32+P+R+A+L
+   | Save area for AltiVec registers (W)   |  32+P+A+L+R
+---+
-   | AltiVec alignment padding (Y) |  32+P+R+A+L+W
+   | AltiVec alignment padding (Y) |  32+P+A+L+R+W
+---+
-   | Save area for GP registers (G)|  32+P+R+A+L+W+Y
+   | Save area for GP registers (G)|  32+P+A+L+R+W+Y
+---+
-   | Save area for FP registers (F)|  32+P+R+A+L+W+Y+G
+   | Save area for FP registers (F)|  32+P+A+L+R+W+Y+G
+---+
-   old SP->| back chain to caller's caller |  32+P+R+A+L+W+Y+G+F
+   old SP->| back chain to caller's caller |  32+P+A+L+R+W+Y+G+F
+---+
 
  * If the alloca area is present, the parameter save area is

[gcc r14-10491] rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:33ebeb2435d68ae0546b29394e99e00647943fa9

commit r14-10491-g33ebeb2435d68ae0546b29394e99e00647943fa9
Author: Peter Bergner 
Date:   Fri Jun 14 14:36:20 2024 -0500

rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

We currently only compute the offset for the ROP hash save location in
the stack frame for Altivec compiles.  For non-Altivec compiles when we
emit ROP mitigation instructions, we use a default offset of zero which
corresponds to the backchain save location which will get clobbered on
any call.  The fix is to compute the ROP hash save location for all
compiles.

2024-06-14  Peter Bergner  

gcc/
PR target/115389
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute
rop_hash_save_offset for non-Altivec compiles.

gcc/testsuite
PR target/115389
* gcc.target/powerpc/pr115389.c: New test.

(cherry picked from commit c70eea0dba5f223d49c80cfb3e80e87b74330aac)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc   |  9 -
 gcc/testsuite/gcc.target/powerpc/pr115389.c | 17 +
 2 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index d61a25a51264..193e2122c0f9 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -817,17 +817,16 @@ rs6000_stack_info (void)
  gcc_assert (info->altivec_size == 0
  || info->altivec_save_offset % 16 == 0);
 
- /* Adjust for AltiVec case.  */
- info->ehrd_offset = info->altivec_save_offset - ehrd_size;
-
  /* Adjust for ROP protection.  */
  info->rop_hash_save_offset
= info->altivec_save_offset - info->rop_hash_size;
- info->ehrd_offset -= info->rop_hash_size;
}
   else
-   info->ehrd_offset = info->gp_save_offset - ehrd_size;
+ /* Adjust for ROP protection.  */
+ info->rop_hash_save_offset
+   = info->gp_save_offset - info->rop_hash_size;
 
+  info->ehrd_offset = info->rop_hash_save_offset - ehrd_size;
   info->ehcr_offset = info->ehrd_offset - ehcr_size;
   info->cr_save_offset = reg_size; /* first word when 64-bit.  */
   info->lr_save_offset = 2*reg_size;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115389.c 
b/gcc/testsuite/gcc.target/powerpc/pr115389.c
new file mode 100644
index ..a091ee8a1be0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr115389.c
@@ -0,0 +1,17 @@
+/* PR target/115389 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mrop-protect -mno-vsx -mno-altivec 
-mabi=no-altivec -save-temps" } */
+/* { dg-require-effective-target rop_ok } */
+
+/* Verify we do not emit invalid offsets for our ROP insns.  */
+
+extern void foo (void);
+long
+bar (void)
+{
+  foo ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */

[gcc r14-10492] rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:e2d746e5ab73b0b1f1a8104101c09b1f4ab3fa25

commit r14-10492-ge2d746e5ab73b0b1f1a8104101c09b1f4ab3fa25
Author: Peter Bergner 
Date:   Wed Jun 19 16:07:29 2024 -0500

rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759]

We currently only emit the ROP-protect hash* insns for Power10, where the
insns were added to the architecture.  We want to emit them for earlier
cpus (where they operate as NOPs), so that if those older binaries are
ever executed on a Power10, then they'll be protected from ROP attacks.
Binutils accepts hashst and hashchk back to Power8, so change GCC to emit
them for Power8 and later.  This matches clang's behavior.

2024-06-19  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Use 
TARGET_POWER8.
(rs6000_emit_prologue): Likewise.
* config/rs6000/rs6000.md (hashchk): Likewise.
(hashst): Likewise.
Fix whitespace.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-2.c: New test.
* lib/target-supports.exp (rop_ok): Use
check_effective_target_has_arch_pwr8.

(cherry picked from commit a05c3d23d1e1c8d2971b123804fc7a61a3561adb)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc |  6 +++---
 gcc/config/rs6000/rs6000.md   |  6 +++---
 gcc/testsuite/gcc.target/powerpc/pr114759-2.c | 17 +
 gcc/testsuite/lib/target-supports.exp |  2 +-
 4 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 193e2122c0f9..48f406330714 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -716,7 +716,7 @@ rs6000_stack_info (void)
   info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
   info->rop_hash_size = 0;
 
-  if (TARGET_POWER10
+  if (TARGET_POWER8
   && info->calls_p
   && DEFAULT_ABI == ABI_ELFv2
   && rs6000_rop_protect)
@@ -3272,7 +3272,7 @@ rs6000_emit_prologue (void)
   /* NOTE: The hashst isn't needed if we're going to do a sibcall,
  but there's no way to know that here.  Harmless except for
  performance, of course.  */
-  if (TARGET_POWER10 && rs6000_rop_protect && info->rop_hash_size != 0)
+  if (TARGET_POWER8 && rs6000_rop_protect && info->rop_hash_size != 0)
 {
   gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
@@ -5051,7 +5051,7 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type)
 
   /* The ROP hash check must occur after the stack pointer is restored
  (since the hash involves r1), and is not performed for a sibcall.  */
-  if (TARGET_POWER10
+  if (TARGET_POWER8
   && rs6000_rop_protect
   && info->rop_hash_size != 0
   && epilogue_type != EPILOGUE_TYPE_SIBCALL)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d4120c3b9ce5..43bde9ab9e19 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15815,9 +15815,9 @@
 
 (define_insn "hashst"
   [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
-(unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
+   (unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
UNSPEC_HASHST))]
-  "TARGET_POWER10 && rs6000_rop_protect"
+  "TARGET_POWER8 && rs6000_rop_protect"
 {
   static char templ[32];
   const char *p = rs6000_privileged ? "p" : "";
@@ -15830,7 +15830,7 @@
   [(unspec_volatile [(match_operand:DI 0 "int_reg_operand" "r")
 (match_operand:DI 1 "simple_offsettable_mem_operand" "m")]
UNSPEC_HASHCHK)]
-  "TARGET_POWER10 && rs6000_rop_protect"
+  "TARGET_POWER8 && rs6000_rop_protect"
 {
   static char templ[32];
   const char *p = rs6000_privileged ? "p" : "";
diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-2.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-2.c
new file mode 100644
index ..3881ebd416e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mrop-protect" } */
+/* { dg-require-effective-target rop_ok } Only enable on supported ABIs.  */
+
+/* Verify we generate ROP-protect hash insns when compiling for Power8.  */
+
+extern void foo (void);
+
+int
+bar (void)
+{
+  foo ();
+  return 5;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index fb9191d6e73b..d8b5a06a4224 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7393,7 +7393,7 @@ proc check_effective_target_powerpc_elfv2 { } {
 # Return 

[gcc r14-10494] rs6000: Catch unsupported ABI errors when using -mrop-protect [PR114759, PR115988]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:bd535b46aaffe637b2eeb634e56ee6e9efa511bf

commit r14-10494-gbd535b46aaffe637b2eeb634e56ee6e9efa511bf
Author: Peter Bergner 
Date:   Thu Jul 18 18:01:46 2024 -0500

rs6000: Catch unsupported ABI errors when using -mrop-protect 
[PR114759,PR115988]

2024-07-18  Peter Bergner  

gcc/testsuite/
PR target/114759
PR target/115988
* gcc.target/powerpc/pr114759-3.c: Catch unsupported ABI errors.

(cherry picked from commit b2f47a5c1d5204131660ea0372a08e692df8844e)

Diff:
---
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-3.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
index 6770a9aec3b5..e2f1d42e111f 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
@@ -2,7 +2,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -mdejagnu-cpu=power7 -mrop-protect" } */
 
-/* Verify we emit an error if we use -mrop-protect with an unsupported cpu.  */
+/* Verify we emit an error if we use -mrop-protect with an unsupported cpu
+   or ABI.  */
 
 extern void foo (void);
 
@@ -17,3 +18,4 @@ bar (void)
in the final line (which is all that dg-error inspects). Hence, we have
to tell dg-error to ignore the line number.  */
 /* { dg-error "'-mrop-protect' requires '-mcpu=power8'" "PR114759" { target 
*-*-* } 0 } */
+/* { dg-error "'-mrop-protect' requires the ELFv2 ABI" "PR114759" { target { ! 
rop_ok } } 0 } */

[gcc r14-10493] rs6000: Error on CPUs and ABIs that don't support the ROP protection insns [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:35e5c2d2e4af20d143ee1a4f8f4f2bd8b24c4af1

commit r14-10493-g35e5c2d2e4af20d143ee1a4f8f4f2bd8b24c4af1
Author: Peter Bergner 
Date:   Mon Jul 15 16:57:32 2024 -0500

rs6000: Error on CPUs and ABIs that don't support the ROP protection insns 
[PR114759]

We currently silently ignore the -mrop-protect option for old CPUs we don't
support with the ROP hash insns, but we throw an error for unsupported ABIs.
This patch treats unsupported CPUs and ABIs similarly by throwing an error
both both.  This matches clang behavior and allows us to simplify our tests
in the code that generates our prologue and epilogue code.

2024-06-26  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000.cc (rs6000_option_override_internal): 
Disallow
CPUs and ABIs that do no support the ROP protection insns.
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Remove now
unneeded tests.
(rs6000_emit_prologue): Likewise.
Remove unneeded gcc_assert.
(rs6000_emit_epilogue): Likewise.
* config/rs6000/rs6000.md: Likewise.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-3.c: New test.

(cherry picked from commit 6f2bab9b5d1ce1914c748b7dcd8638dafaa98df7)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 22 ++
 gcc/config/rs6000/rs6000.cc   | 12 
 gcc/config/rs6000/rs6000.md   |  4 ++--
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c | 19 +++
 4 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 48f406330714..edc0d6c8f520 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -716,17 +716,11 @@ rs6000_stack_info (void)
   info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
   info->rop_hash_size = 0;
 
-  if (TARGET_POWER8
-  && info->calls_p
-  && DEFAULT_ABI == ABI_ELFv2
-  && rs6000_rop_protect)
+  /* If we want ROP protection and this function makes a call, indicate
+ we need to create a stack slot to save the hashed return address in.  */
+  if (rs6000_rop_protect
+  && info->calls_p)
 info->rop_hash_size = 8;
-  else if (rs6000_rop_protect && DEFAULT_ABI != ABI_ELFv2)
-{
-  /* We can't check this in rs6000_option_override_internal since
-DEFAULT_ABI isn't established yet.  */
-  error ("%qs requires the ELFv2 ABI", "-mrop-protect");
-}
 
   /* Determine if we need to save the condition code registers.  */
   if (save_reg_p (CR2_REGNO)
@@ -3272,9 +3266,8 @@ rs6000_emit_prologue (void)
   /* NOTE: The hashst isn't needed if we're going to do a sibcall,
  but there's no way to know that here.  Harmless except for
  performance, of course.  */
-  if (TARGET_POWER8 && rs6000_rop_protect && info->rop_hash_size != 0)
+  if (info->rop_hash_size)
 {
-  gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx addr = gen_rtx_PLUS (Pmode, stack_ptr,
   GEN_INT (info->rop_hash_save_offset));
@@ -5051,12 +5044,9 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type)
 
   /* The ROP hash check must occur after the stack pointer is restored
  (since the hash involves r1), and is not performed for a sibcall.  */
-  if (TARGET_POWER8
-  && rs6000_rop_protect
-  && info->rop_hash_size != 0
+  if (info->rop_hash_size
   && epilogue_type != EPILOGUE_TYPE_SIBCALL)
 {
-  gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx addr = gen_rtx_PLUS (Pmode, stack_ptr,
   GEN_INT (info->rop_hash_save_offset));
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7b80c98cfd83..2e686acac6a0 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4825,6 +4825,18 @@ rs6000_option_override_internal (bool global_init_p)
}
 }
 
+  /* We only support ROP protection on certain targets.  */
+  if (rs6000_rop_protect)
+{
+  /* Disallow CPU targets we don't support.  */
+  if (!TARGET_POWER8)
+   error ("%<-mrop-protect%> requires %<-mcpu=power8%> or later");
+
+  /* Disallow ABI targets we don't support.  */
+  if (DEFAULT_ABI != ABI_ELFv2)
+   error ("%<-mrop-protect%> requires the ELFv2 ABI");
+}
+
   /* Initialize all of the registers.  */
   rs6000_init_hard_regno_mode_ok (global_init_p);
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 43bde9ab9e19..39c75af5c877 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15817,7 +15817,7 @@
   [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")

[gcc r13-8938] rs6000: Update ELFv2 stack frame comment showing the correct ROP save location

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:9bbdec4d94f9120b75d03a610e0338bb05ee40f7

commit r13-8938-g9bbdec4d94f9120b75d03a610e0338bb05ee40f7
Author: Peter Bergner 
Date:   Fri Jun 7 16:03:08 2024 -0500

rs6000: Update ELFv2 stack frame comment showing the correct ROP save 
location

The ELFv2 stack frame layout comment in rs6000-logue.cc shows the ROP
hash save slot in the wrong location.  Update the comment to show the
correct ROP hash save location in the frame.

2024-06-07  Peter Bergner  

gcc/
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Update comment.

(cherry picked from commit e91cf26a954a5c1bf431e36f3a1e69f94e9fa4fe)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index baadbbd692e1..ddd46ae459ae 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -591,21 +591,21 @@ rs6000_savres_strategy (rs6000_stack_t *info,
+---+
| Parameter save area (+padding*) (P)   |  32
+---+
-   | Optional ROP hash slot (R)|  32+P
+   | Alloca space (A)  |  32+P
+---+
-   | Alloca space (A)  |  32+P+R
+   | Local variable space (L)  |  32+P+A
+---+
-   | Local variable space (L)  |  32+P+R+A
+   | Optional ROP hash slot (R)|  32+P+A+L
+---+
-   | Save area for AltiVec registers (W)   |  32+P+R+A+L
+   | Save area for AltiVec registers (W)   |  32+P+A+L+R
+---+
-   | AltiVec alignment padding (Y) |  32+P+R+A+L+W
+   | AltiVec alignment padding (Y) |  32+P+A+L+R+W
+---+
-   | Save area for GP registers (G)|  32+P+R+A+L+W+Y
+   | Save area for GP registers (G)|  32+P+A+L+R+W+Y
+---+
-   | Save area for FP registers (F)|  32+P+R+A+L+W+Y+G
+   | Save area for FP registers (F)|  32+P+A+L+R+W+Y+G
+---+
-   old SP->| back chain to caller's caller |  32+P+R+A+L+W+Y+G+F
+   old SP->| back chain to caller's caller |  32+P+A+L+R+W+Y+G+F
+---+
 
  * If the alloca area is present, the parameter save area is

[gcc r13-8939] rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:bc51e5abcd9cf9a4f74384f2df7c0c8c5ae07c1c

commit r13-8939-gbc51e5abcd9cf9a4f74384f2df7c0c8c5ae07c1c
Author: Peter Bergner 
Date:   Fri Jun 14 14:36:20 2024 -0500

rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

We currently only compute the offset for the ROP hash save location in
the stack frame for Altivec compiles.  For non-Altivec compiles when we
emit ROP mitigation instructions, we use a default offset of zero which
corresponds to the backchain save location which will get clobbered on
any call.  The fix is to compute the ROP hash save location for all
compiles.

2024-06-14  Peter Bergner  

gcc/
PR target/115389
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute
rop_hash_save_offset for non-Altivec compiles.

gcc/testsuite
PR target/115389
* gcc.target/powerpc/pr115389.c: New test.

(cherry picked from commit c70eea0dba5f223d49c80cfb3e80e87b74330aac)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc   |  9 -
 gcc/testsuite/gcc.target/powerpc/pr115389.c | 17 +
 2 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index ddd46ae459ae..d38b90b61070 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -817,17 +817,16 @@ rs6000_stack_info (void)
  gcc_assert (info->altivec_size == 0
  || info->altivec_save_offset % 16 == 0);
 
- /* Adjust for AltiVec case.  */
- info->ehrd_offset = info->altivec_save_offset - ehrd_size;
-
  /* Adjust for ROP protection.  */
  info->rop_hash_save_offset
= info->altivec_save_offset - info->rop_hash_size;
- info->ehrd_offset -= info->rop_hash_size;
}
   else
-   info->ehrd_offset = info->gp_save_offset - ehrd_size;
+ /* Adjust for ROP protection.  */
+ info->rop_hash_save_offset
+   = info->gp_save_offset - info->rop_hash_size;
 
+  info->ehrd_offset = info->rop_hash_save_offset - ehrd_size;
   info->ehcr_offset = info->ehrd_offset - ehcr_size;
   info->cr_save_offset = reg_size; /* first word when 64-bit.  */
   info->lr_save_offset = 2*reg_size;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115389.c 
b/gcc/testsuite/gcc.target/powerpc/pr115389.c
new file mode 100644
index ..a091ee8a1be0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr115389.c
@@ -0,0 +1,17 @@
+/* PR target/115389 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mrop-protect -mno-vsx -mno-altivec 
-mabi=no-altivec -save-temps" } */
+/* { dg-require-effective-target rop_ok } */
+
+/* Verify we do not emit invalid offsets for our ROP insns.  */
+
+extern void foo (void);
+long
+bar (void)
+{
+  foo ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */

[gcc r13-8942] rs6000: Catch unsupported ABI errors when using -mrop-protect [PR114759, PR115988]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:9a4603d323d890dfab6d27ede17dc904abdccd9b

commit r13-8942-g9a4603d323d890dfab6d27ede17dc904abdccd9b
Author: Peter Bergner 
Date:   Thu Jul 18 18:01:46 2024 -0500

rs6000: Catch unsupported ABI errors when using -mrop-protect 
[PR114759,PR115988]

2024-07-18  Peter Bergner  

gcc/testsuite/
PR target/114759
PR target/115988
* gcc.target/powerpc/pr114759-3.c: Catch unsupported ABI errors.

(cherry picked from commit b2f47a5c1d5204131660ea0372a08e692df8844e)

Diff:
---
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-3.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
index 6770a9aec3b5..e2f1d42e111f 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
@@ -2,7 +2,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -mdejagnu-cpu=power7 -mrop-protect" } */
 
-/* Verify we emit an error if we use -mrop-protect with an unsupported cpu.  */
+/* Verify we emit an error if we use -mrop-protect with an unsupported cpu
+   or ABI.  */
 
 extern void foo (void);
 
@@ -17,3 +18,4 @@ bar (void)
in the final line (which is all that dg-error inspects). Hence, we have
to tell dg-error to ignore the line number.  */
 /* { dg-error "'-mrop-protect' requires '-mcpu=power8'" "PR114759" { target 
*-*-* } 0 } */
+/* { dg-error "'-mrop-protect' requires the ELFv2 ABI" "PR114759" { target { ! 
rop_ok } } 0 } */

[gcc r13-8940] rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:77fd352a47137d79e6b7a480503ce4368f13c3e5

commit r13-8940-g77fd352a47137d79e6b7a480503ce4368f13c3e5
Author: Peter Bergner 
Date:   Wed Jun 19 16:07:29 2024 -0500

rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759]

We currently only emit the ROP-protect hash* insns for Power10, where the
insns were added to the architecture.  We want to emit them for earlier
cpus (where they operate as NOPs), so that if those older binaries are
ever executed on a Power10, then they'll be protected from ROP attacks.
Binutils accepts hashst and hashchk back to Power8, so change GCC to emit
them for Power8 and later.  This matches clang's behavior.

2024-06-19  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Use 
TARGET_POWER8.
(rs6000_emit_prologue): Likewise.
* config/rs6000/rs6000.md (hashchk): Likewise.
(hashst): Likewise.
Fix whitespace.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-2.c: New test.
* lib/target-supports.exp (rop_ok): Use
check_effective_target_has_arch_pwr8.

(cherry picked from commit a05c3d23d1e1c8d2971b123804fc7a61a3561adb)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc |  6 +++---
 gcc/config/rs6000/rs6000.md   |  6 +++---
 gcc/testsuite/gcc.target/powerpc/pr114759-2.c | 17 +
 gcc/testsuite/lib/target-supports.exp |  2 +-
 4 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index d38b90b61070..9e6b4ca5533f 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -716,7 +716,7 @@ rs6000_stack_info (void)
   info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
   info->rop_hash_size = 0;
 
-  if (TARGET_POWER10
+  if (TARGET_POWER8
   && info->calls_p
   && DEFAULT_ABI == ABI_ELFv2
   && rs6000_rop_protect)
@@ -3275,7 +3275,7 @@ rs6000_emit_prologue (void)
   /* NOTE: The hashst isn't needed if we're going to do a sibcall,
  but there's no way to know that here.  Harmless except for
  performance, of course.  */
-  if (TARGET_POWER10 && rs6000_rop_protect && info->rop_hash_size != 0)
+  if (TARGET_POWER8 && rs6000_rop_protect && info->rop_hash_size != 0)
 {
   gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
@@ -5054,7 +5054,7 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type)
 
   /* The ROP hash check must occur after the stack pointer is restored
  (since the hash involves r1), and is not performed for a sibcall.  */
-  if (TARGET_POWER10
+  if (TARGET_POWER8
   && rs6000_rop_protect
   && info->rop_hash_size != 0
   && epilogue_type != EPILOGUE_TYPE_SIBCALL)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8d8118197da7..79aaf490837f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15665,9 +15665,9 @@
 
 (define_insn "hashst"
   [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
-(unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
+   (unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
UNSPEC_HASHST))]
-  "TARGET_POWER10 && rs6000_rop_protect"
+  "TARGET_POWER8 && rs6000_rop_protect"
 {
   static char templ[32];
   const char *p = rs6000_privileged ? "p" : "";
@@ -15680,7 +15680,7 @@
   [(unspec_volatile [(match_operand:DI 0 "int_reg_operand" "r")
 (match_operand:DI 1 "simple_offsettable_mem_operand" "m")]
UNSPEC_HASHCHK)]
-  "TARGET_POWER10 && rs6000_rop_protect"
+  "TARGET_POWER8 && rs6000_rop_protect"
 {
   static char templ[32];
   const char *p = rs6000_privileged ? "p" : "";
diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-2.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-2.c
new file mode 100644
index ..3881ebd416e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mrop-protect" } */
+/* { dg-require-effective-target rop_ok } Only enable on supported ABIs.  */
+
+/* Verify we generate ROP-protect hash insns when compiling for Power8.  */
+
+extern void foo (void);
+
+int
+bar (void)
+{
+  foo ();
+  return 5;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index be8ddc8e0f85..c81313ea7177 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6919,7 +6919,7 @@ proc check_effective_target_powerpc_elfv2 { } {
 # Return 1

[gcc r13-8941] rs6000: Error on CPUs and ABIs that don't support the ROP protection insns [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:63b1b3e23c3c589c2859d481705dc706cbff35a1

commit r13-8941-g63b1b3e23c3c589c2859d481705dc706cbff35a1
Author: Peter Bergner 
Date:   Mon Jul 15 16:57:32 2024 -0500

rs6000: Error on CPUs and ABIs that don't support the ROP protection insns 
[PR114759]

We currently silently ignore the -mrop-protect option for old CPUs we don't
support with the ROP hash insns, but we throw an error for unsupported ABIs.
This patch treats unsupported CPUs and ABIs similarly by throwing an error
both both.  This matches clang behavior and allows us to simplify our tests
in the code that generates our prologue and epilogue code.

2024-06-26  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000.cc (rs6000_option_override_internal): 
Disallow
CPUs and ABIs that do no support the ROP protection insns.
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Remove now
unneeded tests.
(rs6000_emit_prologue): Likewise.
Remove unneeded gcc_assert.
(rs6000_emit_epilogue): Likewise.
* config/rs6000/rs6000.md: Likewise.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-3.c: New test.

(cherry picked from commit 6f2bab9b5d1ce1914c748b7dcd8638dafaa98df7)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 22 ++
 gcc/config/rs6000/rs6000.cc   | 12 
 gcc/config/rs6000/rs6000.md   |  4 ++--
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c | 19 +++
 4 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 9e6b4ca5533f..208404e68640 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -716,17 +716,11 @@ rs6000_stack_info (void)
   info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
   info->rop_hash_size = 0;
 
-  if (TARGET_POWER8
-  && info->calls_p
-  && DEFAULT_ABI == ABI_ELFv2
-  && rs6000_rop_protect)
+  /* If we want ROP protection and this function makes a call, indicate
+ we need to create a stack slot to save the hashed return address in.  */
+  if (rs6000_rop_protect
+  && info->calls_p)
 info->rop_hash_size = 8;
-  else if (rs6000_rop_protect && DEFAULT_ABI != ABI_ELFv2)
-{
-  /* We can't check this in rs6000_option_override_internal since
-DEFAULT_ABI isn't established yet.  */
-  error ("%qs requires the ELFv2 ABI", "-mrop-protect");
-}
 
   /* Determine if we need to save the condition code registers.  */
   if (save_reg_p (CR2_REGNO)
@@ -3275,9 +3269,8 @@ rs6000_emit_prologue (void)
   /* NOTE: The hashst isn't needed if we're going to do a sibcall,
  but there's no way to know that here.  Harmless except for
  performance, of course.  */
-  if (TARGET_POWER8 && rs6000_rop_protect && info->rop_hash_size != 0)
+  if (info->rop_hash_size)
 {
-  gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx addr = gen_rtx_PLUS (Pmode, stack_ptr,
   GEN_INT (info->rop_hash_save_offset));
@@ -5054,12 +5047,9 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type)
 
   /* The ROP hash check must occur after the stack pointer is restored
  (since the hash involves r1), and is not performed for a sibcall.  */
-  if (TARGET_POWER8
-  && rs6000_rop_protect
-  && info->rop_hash_size != 0
+  if (info->rop_hash_size
   && epilogue_type != EPILOGUE_TYPE_SIBCALL)
 {
-  gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx addr = gen_rtx_PLUS (Pmode, stack_ptr,
   GEN_INT (info->rop_hash_save_offset));
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 29475ffcb7f0..2b876c90e6fa 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4850,6 +4850,18 @@ rs6000_option_override_internal (bool global_init_p)
}
 }
 
+  /* We only support ROP protection on certain targets.  */
+  if (rs6000_rop_protect)
+{
+  /* Disallow CPU targets we don't support.  */
+  if (!TARGET_POWER8)
+   error ("%<-mrop-protect%> requires %<-mcpu=power8%> or later");
+
+  /* Disallow ABI targets we don't support.  */
+  if (DEFAULT_ABI != ABI_ELFv2)
+   error ("%<-mrop-protect%> requires the ELFv2 ABI");
+}
+
   /* Initialize all of the registers.  */
   rs6000_init_hard_regno_mode_ok (global_init_p);
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 79aaf490837f..7e6fcc45a204 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15667,7 +15667,7 @@
   [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
 

[gcc r12-10638] rs6000: Update ELFv2 stack frame comment showing the correct ROP save location

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:2647b9e052eafbbec1094558167be9a24e2d8221

commit r12-10638-g2647b9e052eafbbec1094558167be9a24e2d8221
Author: Peter Bergner 
Date:   Fri Jun 7 16:03:08 2024 -0500

rs6000: Update ELFv2 stack frame comment showing the correct ROP save 
location

The ELFv2 stack frame layout comment in rs6000-logue.cc shows the ROP
hash save slot in the wrong location.  Update the comment to show the
correct ROP hash save location in the frame.

2024-06-07  Peter Bergner  

gcc/
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Update comment.

(cherry picked from commit e91cf26a954a5c1bf431e36f3a1e69f94e9fa4fe)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 33077b72611c..270f41573757 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -595,21 +595,21 @@ rs6000_savres_strategy (rs6000_stack_t *info,
+---+
| Parameter save area (+padding*) (P)   |  32
+---+
-   | Optional ROP hash slot (R)|  32+P
+   | Alloca space (A)  |  32+P
+---+
-   | Alloca space (A)  |  32+P+R
+   | Local variable space (L)  |  32+P+A
+---+
-   | Local variable space (L)  |  32+P+R+A
+   | Optional ROP hash slot (R)|  32+P+A+L
+---+
-   | Save area for AltiVec registers (W)   |  32+P+R+A+L
+   | Save area for AltiVec registers (W)   |  32+P+A+L+R
+---+
-   | AltiVec alignment padding (Y) |  32+P+R+A+L+W
+   | AltiVec alignment padding (Y) |  32+P+A+L+R+W
+---+
-   | Save area for GP registers (G)|  32+P+R+A+L+W+Y
+   | Save area for GP registers (G)|  32+P+A+L+R+W+Y
+---+
-   | Save area for FP registers (F)|  32+P+R+A+L+W+Y+G
+   | Save area for FP registers (F)|  32+P+A+L+R+W+Y+G
+---+
-   old SP->| back chain to caller's caller |  32+P+R+A+L+W+Y+G+F
+   old SP->| back chain to caller's caller |  32+P+A+L+R+W+Y+G+F
+---+
 
  * If the alloca area is present, the parameter save area is

[gcc r12-10639] rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:60e513cd47aadd8f139079f8388b14930e6e0913

commit r12-10639-g60e513cd47aadd8f139079f8388b14930e6e0913
Author: Peter Bergner 
Date:   Fri Jun 14 14:36:20 2024 -0500

rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

We currently only compute the offset for the ROP hash save location in
the stack frame for Altivec compiles.  For non-Altivec compiles when we
emit ROP mitigation instructions, we use a default offset of zero which
corresponds to the backchain save location which will get clobbered on
any call.  The fix is to compute the ROP hash save location for all
compiles.

2024-06-14  Peter Bergner  

gcc/
PR target/115389
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute
rop_hash_save_offset for non-Altivec compiles.

gcc/testsuite
PR target/115389
* gcc.target/powerpc/pr115389.c: New test.

(cherry picked from commit c70eea0dba5f223d49c80cfb3e80e87b74330aac)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc   |  9 -
 gcc/testsuite/gcc.target/powerpc/pr115389.c | 17 +
 2 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 270f41573757..3894bd23d179 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -821,17 +821,16 @@ rs6000_stack_info (void)
  gcc_assert (info->altivec_size == 0
  || info->altivec_save_offset % 16 == 0);
 
- /* Adjust for AltiVec case.  */
- info->ehrd_offset = info->altivec_save_offset - ehrd_size;
-
  /* Adjust for ROP protection.  */
  info->rop_hash_save_offset
= info->altivec_save_offset - info->rop_hash_size;
- info->ehrd_offset -= info->rop_hash_size;
}
   else
-   info->ehrd_offset = info->gp_save_offset - ehrd_size;
+ /* Adjust for ROP protection.  */
+ info->rop_hash_save_offset
+   = info->gp_save_offset - info->rop_hash_size;
 
+  info->ehrd_offset = info->rop_hash_save_offset - ehrd_size;
   info->ehcr_offset = info->ehrd_offset - ehcr_size;
   info->cr_save_offset = reg_size; /* first word when 64-bit.  */
   info->lr_save_offset = 2*reg_size;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115389.c 
b/gcc/testsuite/gcc.target/powerpc/pr115389.c
new file mode 100644
index ..a091ee8a1be0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr115389.c
@@ -0,0 +1,17 @@
+/* PR target/115389 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mrop-protect -mno-vsx -mno-altivec 
-mabi=no-altivec -save-temps" } */
+/* { dg-require-effective-target rop_ok } */
+
+/* Verify we do not emit invalid offsets for our ROP insns.  */
+
+extern void foo (void);
+long
+bar (void)
+{
+  foo ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */

[gcc r12-10641] rs6000: Error on CPUs and ABIs that don't support the ROP protection insns [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:25cf4d2a2200903fe868f8cbd9d24f35768041c1

commit r12-10641-g25cf4d2a2200903fe868f8cbd9d24f35768041c1
Author: Peter Bergner 
Date:   Mon Jul 15 16:57:32 2024 -0500

rs6000: Error on CPUs and ABIs that don't support the ROP protection insns 
[PR114759]

We currently silently ignore the -mrop-protect option for old CPUs we don't
support with the ROP hash insns, but we throw an error for unsupported ABIs.
This patch treats unsupported CPUs and ABIs similarly by throwing an error
both both.  This matches clang behavior and allows us to simplify our tests
in the code that generates our prologue and epilogue code.

2024-06-26  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000.cc (rs6000_option_override_internal): 
Disallow
CPUs and ABIs that do no support the ROP protection insns.
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Remove now
unneeded tests.
(rs6000_emit_prologue): Likewise.
Remove unneeded gcc_assert.
(rs6000_emit_epilogue): Likewise.
* config/rs6000/rs6000.md: Likewise.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-3.c: New test.

(cherry picked from commit 6f2bab9b5d1ce1914c748b7dcd8638dafaa98df7)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 22 ++
 gcc/config/rs6000/rs6000.cc   | 12 
 gcc/config/rs6000/rs6000.md   |  4 ++--
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c | 19 +++
 4 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 9817ce78639a..d891d43c074e 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -720,17 +720,11 @@ rs6000_stack_info (void)
   info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
   info->rop_hash_size = 0;
 
-  if (TARGET_POWER8
-  && info->calls_p
-  && DEFAULT_ABI == ABI_ELFv2
-  && rs6000_rop_protect)
+  /* If we want ROP protection and this function makes a call, indicate
+ we need to create a stack slot to save the hashed return address in.  */
+  if (rs6000_rop_protect
+  && info->calls_p)
 info->rop_hash_size = 8;
-  else if (rs6000_rop_protect && DEFAULT_ABI != ABI_ELFv2)
-{
-  /* We can't check this in rs6000_option_override_internal since
-DEFAULT_ABI isn't established yet.  */
-  error ("%qs requires the ELFv2 ABI", "-mrop-protect");
-}
 
   /* Determine if we need to save the condition code registers.  */
   if (save_reg_p (CR2_REGNO)
@@ -3279,9 +3273,8 @@ rs6000_emit_prologue (void)
   /* NOTE: The hashst isn't needed if we're going to do a sibcall,
  but there's no way to know that here.  Harmless except for
  performance, of course.  */
-  if (TARGET_POWER8 && rs6000_rop_protect && info->rop_hash_size != 0)
+  if (info->rop_hash_size)
 {
-  gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx addr = gen_rtx_PLUS (Pmode, stack_ptr,
   GEN_INT (info->rop_hash_save_offset));
@@ -5026,12 +5019,9 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type)
 
   /* The ROP hash check must occur after the stack pointer is restored
  (since the hash involves r1), and is not performed for a sibcall.  */
-  if (TARGET_POWER8
-  && rs6000_rop_protect
-  && info->rop_hash_size != 0
+  if (info->rop_hash_size
   && epilogue_type != EPILOGUE_TYPE_SIBCALL)
 {
-  gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
   rtx addr = gen_rtx_PLUS (Pmode, stack_ptr,
   GEN_INT (info->rop_hash_save_offset));
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 03893b2cf8bd..cf0d089d06ba 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4888,6 +4888,18 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_print_builtin_options (stderr, 0, "builtin mask",
  rs6000_builtin_mask);
 
+  /* We only support ROP protection on certain targets.  */
+  if (rs6000_rop_protect)
+{
+  /* Disallow CPU targets we don't support.  */
+  if (!TARGET_POWER8)
+   error ("%<-mrop-protect%> requires %<-mcpu=power8%> or later");
+
+  /* Disallow ABI targets we don't support.  */
+  if (DEFAULT_ABI != ABI_ELFv2)
+   error ("%<-mrop-protect%> requires the ELFv2 ABI");
+}
+
   /* Initialize all of the registers.  */
   rs6000_init_hard_regno_mode_ok (global_init_p);
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d1ae5be96d44..b0614868f942 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs600

[gcc r12-10640] rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:aa293f40770bae5e94f33d4700f2f0ce9eff712b

commit r12-10640-gaa293f40770bae5e94f33d4700f2f0ce9eff712b
Author: Peter Bergner 
Date:   Wed Jun 19 16:07:29 2024 -0500

rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759]

We currently only emit the ROP-protect hash* insns for Power10, where the
insns were added to the architecture.  We want to emit them for earlier
cpus (where they operate as NOPs), so that if those older binaries are
ever executed on a Power10, then they'll be protected from ROP attacks.
Binutils accepts hashst and hashchk back to Power8, so change GCC to emit
them for Power8 and later.  This matches clang's behavior.

2024-06-19  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Use 
TARGET_POWER8.
(rs6000_emit_prologue): Likewise.
* config/rs6000/rs6000.md (hashchk): Likewise.
(hashst): Likewise.
Fix whitespace.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-2.c: New test.
* lib/target-supports.exp (rop_ok): Use
check_effective_target_has_arch_pwr8.

(cherry picked from commit a05c3d23d1e1c8d2971b123804fc7a61a3561adb)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc |  6 +++---
 gcc/config/rs6000/rs6000.md   |  6 +++---
 gcc/testsuite/gcc.target/powerpc/pr114759-2.c | 17 +
 gcc/testsuite/lib/target-supports.exp |  2 +-
 4 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 3894bd23d179..9817ce78639a 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -720,7 +720,7 @@ rs6000_stack_info (void)
   info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
   info->rop_hash_size = 0;
 
-  if (TARGET_POWER10
+  if (TARGET_POWER8
   && info->calls_p
   && DEFAULT_ABI == ABI_ELFv2
   && rs6000_rop_protect)
@@ -3279,7 +3279,7 @@ rs6000_emit_prologue (void)
   /* NOTE: The hashst isn't needed if we're going to do a sibcall,
  but there's no way to know that here.  Harmless except for
  performance, of course.  */
-  if (TARGET_POWER10 && rs6000_rop_protect && info->rop_hash_size != 0)
+  if (TARGET_POWER8 && rs6000_rop_protect && info->rop_hash_size != 0)
 {
   gcc_assert (DEFAULT_ABI == ABI_ELFv2);
   rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
@@ -5026,7 +5026,7 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type)
 
   /* The ROP hash check must occur after the stack pointer is restored
  (since the hash involves r1), and is not performed for a sibcall.  */
-  if (TARGET_POWER10
+  if (TARGET_POWER8
   && rs6000_rop_protect
   && info->rop_hash_size != 0
   && epilogue_type != EPILOGUE_TYPE_SIBCALL)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c38bebde185b..d1ae5be96d44 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15557,9 +15557,9 @@
 
 (define_insn "hashst"
   [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
-(unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
+   (unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
UNSPEC_HASHST))]
-  "TARGET_POWER10 && rs6000_rop_protect"
+  "TARGET_POWER8 && rs6000_rop_protect"
 {
   static char templ[32];
   const char *p = rs6000_privileged ? "p" : "";
@@ -15572,7 +15572,7 @@
   [(unspec_volatile [(match_operand:DI 0 "int_reg_operand" "r")
 (match_operand:DI 1 "simple_offsettable_mem_operand" "m")]
UNSPEC_HASHCHK)]
-  "TARGET_POWER10 && rs6000_rop_protect"
+  "TARGET_POWER8 && rs6000_rop_protect"
 {
   static char templ[32];
   const char *p = rs6000_privileged ? "p" : "";
diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-2.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-2.c
new file mode 100644
index ..3881ebd416e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mrop-protect" } */
+/* { dg-require-effective-target rop_ok } Only enable on supported ABIs.  */
+
+/* Verify we generate ROP-protect hash insns when compiling for Power8.  */
+
+extern void foo (void);
+
+int
+bar (void)
+{
+  foo ();
+  return 5;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 64216dfbdb26..ee2fa5ed8a61 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6752,7 +6752,7 @@ proc check_effective_target_powerpc_elfv2 { } {
 # Return 

[gcc r12-10642] rs6000: Catch unsupported ABI errors when using -mrop-protect [PR114759, PR115988]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:f7bebf4c07dffaa75c77152e8004aa0ccbf6eeac

commit r12-10642-gf7bebf4c07dffaa75c77152e8004aa0ccbf6eeac
Author: Peter Bergner 
Date:   Thu Jul 18 18:01:46 2024 -0500

rs6000: Catch unsupported ABI errors when using -mrop-protect 
[PR114759,PR115988]

2024-07-18  Peter Bergner  

gcc/testsuite/
PR target/114759
PR target/115988
* gcc.target/powerpc/pr114759-3.c: Catch unsupported ABI errors.

(cherry picked from commit b2f47a5c1d5204131660ea0372a08e692df8844e)

Diff:
---
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-3.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
index 6770a9aec3b5..e2f1d42e111f 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-3.c
@@ -2,7 +2,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -mdejagnu-cpu=power7 -mrop-protect" } */
 
-/* Verify we emit an error if we use -mrop-protect with an unsupported cpu.  */
+/* Verify we emit an error if we use -mrop-protect with an unsupported cpu
+   or ABI.  */
 
 extern void foo (void);
 
@@ -17,3 +18,4 @@ bar (void)
in the final line (which is all that dg-error inspects). Hence, we have
to tell dg-error to ignore the line number.  */
 /* { dg-error "'-mrop-protect' requires '-mcpu=power8'" "PR114759" { target 
*-*-* } 0 } */
+/* { dg-error "'-mrop-protect' requires the ELFv2 ABI" "PR114759" { target { ! 
rop_ok } } 0 } */

[gcc r14-9884] rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:7924e352523b37155ed9d76dc426701de9d11a22

commit r14-9884-g7924e352523b37155ed9d76dc426701de9d11a22
Author: Peter Bergner 
Date:   Tue Apr 9 15:24:39 2024 -0500

rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR 
[PR101865]

This is a cleanup patch in preparation to fixing the real bug in PR101865.
TARGET_DIRECT_MOVE is redundant with TARGET_P8_VECTOR, so alias it to that.
Also replace all usages of OPTION_MASK_DIRECT_MOVE with 
OPTION_MASK_P8_VECTOR
and delete the now dead mask.

2024-04-09  Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete 
redundant
OPTION_MASK_DIRECT_MOVE usage.  Delete TARGET_DIRECT_MOVE dead code.
(rs6000_opt_masks): Neuter the "direct-move" option.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete useless
comment.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
OPTION_MASK_DIRECT_MOVE.
(OTHER_VSX_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 14 +-
 gcc/config/rs6000/rs6000-cpus.def |  3 ---
 gcc/config/rs6000/rs6000.cc   | 14 +++---
 gcc/config/rs6000/rs6000.h|  2 ++
 gcc/config/rs6000/rs6000.opt  |  2 +-
 5 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ce0b14a8d37..647f20de7f2 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -429,19 +429,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned on in the following condition:
- 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
-explicitly disabled.
-Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
-have been turned on explicitly.
- Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned off in any of the following conditions:
- 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
-   disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
-   enabled.
- 2. TARGET_VSX is off.  */
-  if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
+  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 28249600318..45dd5a85901 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -49,7 +49,6 @@
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_QUAD_MEMORY  \
 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
@@ -90,7 +89,6 @@
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
 | OPTION_MASK_FLOAT128_KEYWORD \
 | OPTION_MASK_P8_VECTOR\
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_FLOAT128_HW  \
@@ -118,7 +116,6 @@
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_DLMZB\
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6ba9df4f02e..c241371147c 1

[gcc r14-9949] rs6000: Add OPTION_MASK_POWER8 [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:aa57af93ba22865be747f926e4e5f219e7f8758a

commit r14-9949-gaa57af93ba22865be747f926e4e5f219e7f8758a
Author: Will Schmidt 
Date:   Fri Apr 12 14:55:16 2024 -0500

rs6000: Add OPTION_MASK_POWER8 [PR101865]

The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional upon
TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the
-mno-altivec or -mno-vsx options are used.  The solution here is to create
a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of
Altivec or VSX enablement.

Unfortunately, the only way to create an OPTION_MASK_* mask is to create
a new option, which we have done here, but marked it as WarnRemoved since
we do not want users using it.  For stage1, we will look into how we can
create ISA mask flags for use in the compiler without the need for explicit
options.

2024-04-12  Will Schmidt  
Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER8.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
OPTION_MASK_POWER8.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add 
OPTION_MASK_POWER8.
(ISA_2_7_MASKS_SERVER): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
* config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
* config/rs6000/rs6000.md (define_attr "isa"): Add p8.
(define_attr "enabled"): Handle it.
(define_insn "prefetch"): Use TARGET_POWER8.
* config/rs6000/rs6000.opt (mpower8-internal): New.

gcc/testsuite/
PR target/101865
* gcc.target/powerpc/predefine-p7-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec.c: New test.
* gcc.target/powerpc/predefine-p8-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test.
* gcc.target/powerpc/predefine-p9-novsx.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc|   2 +-
 gcc/config/rs6000/rs6000-c.cc  |   2 +-
 gcc/config/rs6000/rs6000-cpus.def  |   2 +
 gcc/config/rs6000/rs6000.cc|   7 +-
 gcc/config/rs6000/rs6000.h |   2 +-
 gcc/config/rs6000/rs6000.md|   8 +-
 gcc/config/rs6000/rs6000.opt   |   4 +
 .../gcc.target/powerpc/predefine-p7-novsx.c|  22 +
 .../powerpc/predefine-p8-noaltivec-novsx.c |  26 ++
 .../gcc.target/powerpc/predefine-p8-noaltivec.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-novsx.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-pragma-vsx.c   | 101 +
 .../gcc.target/powerpc/predefine-p9-novsx.c|  26 ++
 13 files changed, 245 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index e7d6204074c..320affd79e3 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -165,7 +165,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P7_64:
   return TARGET_POPCNTD && TARGET_POWERPC64;
 case ENB_P8:
-  return TARGET_DIRECT_MOVE;
+  return TARGET_POWER8;
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 647f20de7f2..bd493ab87c5 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -429,7 +429,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+  if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 45dd5a85901..6ee678e69c3 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \

[gcc r13-8672] rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:d42105742841e73ca867b6da0c5ca6ad4d86fed6

commit r13-8672-gd42105742841e73ca867b6da0c5ca6ad4d86fed6
Author: Peter Bergner 
Date:   Tue Apr 9 15:24:39 2024 -0500

rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR 
[PR101865]

This is a cleanup patch in preparation to fixing the real bug in PR101865.
TARGET_DIRECT_MOVE is redundant with TARGET_P8_VECTOR, so alias it to that.
Also replace all usages of OPTION_MASK_DIRECT_MOVE with 
OPTION_MASK_P8_VECTOR
and delete the now dead mask.

2024-04-09  Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete 
redundant
OPTION_MASK_DIRECT_MOVE usage.  Delete TARGET_DIRECT_MOVE dead code.
(rs6000_opt_masks): Neuter the "direct-move" option.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete useless
comment.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
OPTION_MASK_DIRECT_MOVE.
(OTHER_P8_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.

(cherry picked from commit 7924e352523b37155ed9d76dc426701de9d11a22)

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 14 +-
 gcc/config/rs6000/rs6000-cpus.def |  3 ---
 gcc/config/rs6000/rs6000.cc   | 14 +++---
 gcc/config/rs6000/rs6000.h|  2 ++
 gcc/config/rs6000/rs6000.opt  |  2 +-
 5 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 8555174d36e..2bedc0fc938 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -429,19 +429,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned on in the following condition:
- 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
-explicitly disabled.
-Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
-have been turned on explicitly.
- Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned off in any of the following conditions:
- 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
-   disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
-   enabled.
- 2. TARGET_VSX is off.  */
-  if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
+  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 4f350da378c..4f8d07b9a0d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -49,7 +49,6 @@
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_QUAD_MEMORY  \
 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
@@ -93,7 +92,6 @@
 /* Flags that need to be turned off if -mno-power8-vector.  */
 #define OTHER_P8_VECTOR_MASKS  (OTHER_P9_VECTOR_MASKS  \
 | OPTION_MASK_P9_VECTOR\
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_CRYPTO)
 
 /* Flags that need to be turned off if -mno-vsx.  */
@@ -124,7 +122,6 @@
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_DLMZB\
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e5ceff3a61b..4d8740202b7 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ 

[gcc r13-8673] rs6000: Add OPTION_MASK_POWER8 [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:0ae9252f7b52151209b36d8a1cefc49f1b23fa46

commit r13-8673-g0ae9252f7b52151209b36d8a1cefc49f1b23fa46
Author: Will Schmidt 
Date:   Fri Apr 12 14:55:16 2024 -0500

rs6000: Add OPTION_MASK_POWER8 [PR101865]

The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional upon
TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the
-mno-altivec or -mno-vsx options are used.  The solution here is to create
a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of
Altivec or VSX enablement.

Unfortunately, the only way to create an OPTION_MASK_* mask is to create
a new option, which we have done here, but marked it as WarnRemoved since
we do not want users using it.  For stage1, we will look into how we can
create ISA mask flags for use in the compiler without the need for explicit
options.

2024-04-12  Will Schmidt  
Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER8.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
OPTION_MASK_POWER8.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add 
OPTION_MASK_POWER8.
(ISA_2_7_MASKS_SERVER): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
* config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
* config/rs6000/rs6000.md (define_attr "isa"): Add p8.
(define_attr "enabled"): Handle it.
(define_insn "prefetch"): Use TARGET_POWER8.
* config/rs6000/rs6000.opt (mpower8-internal): New.

gcc/testsuite/
PR target/101865
* gcc.target/powerpc/predefine-p7-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec.c: New test.
* gcc.target/powerpc/predefine-p8-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test.
* gcc.target/powerpc/predefine-p9-novsx.c: New test.

(cherry picked from commit aa57af93ba22865be747f926e4e5f219e7f8758a)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc|   2 +-
 gcc/config/rs6000/rs6000-c.cc  |   2 +-
 gcc/config/rs6000/rs6000-cpus.def  |   2 +
 gcc/config/rs6000/rs6000.cc|   7 +-
 gcc/config/rs6000/rs6000.h |   2 +-
 gcc/config/rs6000/rs6000.md|   8 +-
 gcc/config/rs6000/rs6000.opt   |   4 +
 .../gcc.target/powerpc/predefine-p7-novsx.c|  22 +
 .../powerpc/predefine-p8-noaltivec-novsx.c |  26 ++
 .../gcc.target/powerpc/predefine-p8-noaltivec.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-novsx.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-pragma-vsx.c   | 101 +
 .../gcc.target/powerpc/predefine-p9-novsx.c|  26 ++
 13 files changed, 245 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 2b4412e0403..5b17132a101 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -165,7 +165,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P7_64:
   return TARGET_POPCNTD && TARGET_POWERPC64;
 case ENB_P8:
-  return TARGET_DIRECT_MOVE;
+  return TARGET_POWER8;
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 2bedc0fc938..a931efd2409 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -429,7 +429,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+  if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 4f8d07b9a0d..641ad09a3ba 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_VECTOR 

[gcc r12-10408] rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:135402288a1b1b082d2e71ff2ee5c63b7dafed9f

commit r12-10408-g135402288a1b1b082d2e71ff2ee5c63b7dafed9f
Author: Peter Bergner 
Date:   Tue Apr 9 15:24:39 2024 -0500

rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR 
[PR101865]

This is a cleanup patch in preparation to fixing the real bug in PR101865.
TARGET_DIRECT_MOVE is redundant with TARGET_P8_VECTOR, so alias it to that.
Also replace all usages of OPTION_MASK_DIRECT_MOVE with 
OPTION_MASK_P8_VECTOR
and delete the now dead mask.

2024-04-09  Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete 
redundant
OPTION_MASK_DIRECT_MOVE usage.  Delete TARGET_DIRECT_MOVE dead code.
(rs6000_opt_masks): Neuter the "direct-move" option.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete useless
comment.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
OPTION_MASK_DIRECT_MOVE.
(OTHER_P8_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.

(cherry picked from commit 7924e352523b37155ed9d76dc426701de9d11a22)

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 14 +-
 gcc/config/rs6000/rs6000-cpus.def |  3 ---
 gcc/config/rs6000/rs6000.cc   | 14 +++---
 gcc/config/rs6000/rs6000.h|  2 ++
 gcc/config/rs6000/rs6000.opt  |  2 +-
 5 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index fa0c93e1841..cc848478a20 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -432,19 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned on in the following condition:
- 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
-explicitly disabled.
-Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
-have been turned on explicitly.
- Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned off in any of the following conditions:
- 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
-   disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
-   enabled.
- 2. TARGET_VSX is off.  */
-  if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
+  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 963947f6939..7dc8679ac9d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -49,7 +49,6 @@
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_QUAD_MEMORY  \
 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
@@ -94,7 +93,6 @@
 /* Flags that need to be turned off if -mno-power8-vector.  */
 #define OTHER_P8_VECTOR_MASKS  (OTHER_P9_VECTOR_MASKS  \
 | OPTION_MASK_P9_VECTOR\
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_CRYPTO)
 
 /* Flags that need to be turned off if -mno-vsx.  */
@@ -125,7 +123,6 @@
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_DLMZB\
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 70406c21c1c..34c533dba31 100644
--- a/gcc/config/rs6000/rs6000.cc
+++

[gcc r12-10409] rs6000: Add OPTION_MASK_POWER8 [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:04ca18ff5e2592ac88a5b72248332f519a17184b

commit r12-10409-g04ca18ff5e2592ac88a5b72248332f519a17184b
Author: Will Schmidt 
Date:   Fri Apr 12 14:55:16 2024 -0500

rs6000: Add OPTION_MASK_POWER8 [PR101865]

The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional upon
TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the
-mno-altivec or -mno-vsx options are used.  The solution here is to create
a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of
Altivec or VSX enablement.

Unfortunately, the only way to create an OPTION_MASK_* mask is to create
a new option, which we have done here, but marked it as WarnRemoved since
we do not want users using it.  For stage1, we will look into how we can
create ISA mask flags for use in the compiler without the need for explicit
options.

2024-04-12  Will Schmidt  
Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER8.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
OPTION_MASK_POWER8.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add 
OPTION_MASK_POWER8.
(ISA_2_7_MASKS_SERVER): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
* config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
* config/rs6000/rs6000.md (define_attr "isa"): Add p8.
(define_attr "enabled"): Handle it.
(define_insn "prefetch"): Use TARGET_POWER8.
* config/rs6000/rs6000.opt (mpower8-internal): New.

gcc/testsuite/
PR target/101865
* gcc.target/powerpc/predefine-p7-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec.c: New test.
* gcc.target/powerpc/predefine-p8-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test.
* gcc.target/powerpc/predefine-p9-novsx.c: New test.

(cherry picked from commit aa57af93ba22865be747f926e4e5f219e7f8758a)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc|   2 +-
 gcc/config/rs6000/rs6000-c.cc  |   2 +-
 gcc/config/rs6000/rs6000-cpus.def  |   2 +
 gcc/config/rs6000/rs6000.cc|   7 +-
 gcc/config/rs6000/rs6000.h |   2 +-
 gcc/config/rs6000/rs6000.md|   8 +-
 gcc/config/rs6000/rs6000.opt   |   4 +
 .../gcc.target/powerpc/predefine-p7-novsx.c|  22 +
 .../powerpc/predefine-p8-noaltivec-novsx.c |  26 ++
 .../gcc.target/powerpc/predefine-p8-noaltivec.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-novsx.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-pragma-vsx.c   | 101 +
 .../gcc.target/powerpc/predefine-p9-novsx.c|  26 ++
 13 files changed, 245 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 39a07a27c86..ff5830532d2 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -168,7 +168,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P7_64:
   return TARGET_POPCNTD && TARGET_POWERPC64;
 case ENB_P8:
-  return TARGET_DIRECT_MOVE;
+  return TARGET_POWER8;
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index cc848478a20..77d8de70e7a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -432,7 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+  if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 7dc8679ac9d..a052914b246 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_VECTOR

[gcc r11-11412] rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:26d48b6d3e2d07583f25f0769d0c005864760aee

commit r11-11412-g26d48b6d3e2d07583f25f0769d0c005864760aee
Author: Peter Bergner 
Date:   Tue Apr 9 15:24:39 2024 -0500

rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR 
[PR101865]

This is a cleanup patch in preparation to fixing the real bug in PR101865.
TARGET_DIRECT_MOVE is redundant with TARGET_P8_VECTOR, so alias it to that.
Also replace all usages of OPTION_MASK_DIRECT_MOVE with 
OPTION_MASK_P8_VECTOR
and delete the now dead mask.

2024-04-09  Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete 
redundant
OPTION_MASK_DIRECT_MOVE usage.  Delete TARGET_DIRECT_MOVE dead code.
(rs6000_opt_masks): Neuter the "direct-move" option.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete useless
comment.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
OPTION_MASK_DIRECT_MOVE.
(OTHER_P8_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.

(cherry picked from commit 7924e352523b37155ed9d76dc426701de9d11a22)

Diff:
---
 gcc/config/rs6000/rs6000-c.c  | 14 +-
 gcc/config/rs6000/rs6000-cpus.def |  3 ---
 gcc/config/rs6000/rs6000.c| 14 +++---
 gcc/config/rs6000/rs6000.h|  2 ++
 gcc/config/rs6000/rs6000.opt  |  2 +-
 5 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index afcb5bb6e39..1e3117899bb 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -432,19 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned on in the following condition:
- 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
-explicitly disabled.
-Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
-have been turned on explicitly.
- Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned off in any of the following conditions:
- 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
-   disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
-   enabled.
- 2. TARGET_VSX is off.  */
-  if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
+  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 907e1469736..518897df935 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -49,7 +49,6 @@
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_QUAD_MEMORY  \
 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
@@ -94,7 +93,6 @@
 /* Flags that need to be turned off if -mno-power8-vector.  */
 #define OTHER_P8_VECTOR_MASKS  (OTHER_P9_VECTOR_MASKS  \
 | OPTION_MASK_P9_VECTOR\
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_CRYPTO)
 
 /* Flags that need to be turned off if -mno-vsx.  */
@@ -125,7 +123,6 @@
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_DLMZB\
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 3e5281c0f05..4864c959a6e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/co

[gcc r11-11413] rs6000: Add OPTION_MASK_POWER8 [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:f8f02fd0bfeeb733a044a120b394eeac48de318a

commit r11-11413-gf8f02fd0bfeeb733a044a120b394eeac48de318a
Author: Peter Bergner 
Date:   Thu May 2 18:07:05 2024 -0500

rs6000: Add OPTION_MASK_POWER8 [PR101865]

The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional upon
TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the
-mno-altivec or -mno-vsx options are used.  The solution here is to create
a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of
Altivec or VSX enablement.

Unfortunately, the only way to create an OPTION_MASK_* mask is to create
a new option, which we have done here, but marked it as WarnRemoved since
we do not want users using it.  For stage1, we will look into how we can
create ISA mask flags for use in the compiler without the need for explicit
options.

2024-04-12  Will Schmidt  
Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Use
OPTION_MASK_POWER8.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add 
OPTION_MASK_POWER8.
(ISA_2_7_MASKS_SERVER): Likewise.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Update
comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
* config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
* config/rs6000/rs6000.md (define_attr "isa"): Add p8.
(define_attr "enabled"): Handle it.
(define_insn "prefetch"): Use TARGET_POWER8.
* config/rs6000/rs6000.opt (mpower8-internal): New.

gcc/testsuite/
PR target/101865
* gcc.target/powerpc/predefine-p7-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec.c: New test.
* gcc.target/powerpc/predefine-p8-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test.
* gcc.target/powerpc/predefine-p9-novsx.c: New test.

(cherry picked from commit aa57af93ba22865be747f926e4e5f219e7f8758a)

Diff:
---
 gcc/config/rs6000/rs6000-c.c   |   2 +-
 gcc/config/rs6000/rs6000-cpus.def  |   2 +
 gcc/config/rs6000/rs6000.c |   7 +-
 gcc/config/rs6000/rs6000.h |   2 +-
 gcc/config/rs6000/rs6000.md|   8 +-
 gcc/config/rs6000/rs6000.opt   |   4 +
 .../gcc.target/powerpc/predefine-p7-novsx.c|  22 +
 .../powerpc/predefine-p8-noaltivec-novsx.c |  26 ++
 .../gcc.target/powerpc/predefine-p8-noaltivec.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-novsx.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-pragma-vsx.c   | 101 +
 .../gcc.target/powerpc/predefine-p9-novsx.c|  26 ++
 12 files changed, 244 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 1e3117899bb..60cbb1118ec 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -432,7 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+  if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 518897df935..6a1acbd3136 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
fusion here, instead set it in rs6000.c if we are tuning for a power8
system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
@@ -137,6 +138,7 @@
 | OPTION_MASK_MODULO   \
 | OPTION_MASK_MULHW\
 | OPTION_MASK_NO_UPDATE\
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_FUSION\
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_P9_MINMAX

[gcc r15-2896] rs6000: ROP - Do not disable shrink-wrapping for leaf functions [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:0451bc503da9c858e9f1ddfb8faec367c2e032c8

commit r15-2896-g0451bc503da9c858e9f1ddfb8faec367c2e032c8
Author: Peter Bergner 
Date:   Tue Jun 18 17:42:45 2024 -0500

rs6000: ROP - Do not disable shrink-wrapping for leaf functions [PR114759]

Only disable shrink-wrapping when using -mrop-protect when we know we
will be emitting the ROP-protect hash instructions (ie, non-leaf functions).

2024-06-17  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000.cc (rs6000_override_options_after_change): 
Move
the disabling of shrink-wrapping from here
* config/rs6000/rs6000-logue.cc (rs6000_emit_prologue): ...to here.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-1.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc |  5 +
 gcc/config/rs6000/rs6000.cc   |  4 
 gcc/testsuite/gcc.target/powerpc/pr114759-1.c | 16 
 3 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index edc0d6c8f520..fdb6414f486f 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -3012,6 +3012,11 @@ rs6000_emit_prologue (void)
&& (lookup_attribute ("no_split_stack",
  DECL_ATTRIBUTES (cfun->decl))
== NULL));
+  /* If we are inserting ROP-protect hash instructions, disable shrink-wrap
+ until the bug where the hashst insn is emitted in the wrong location
+ is fixed.  See PR101324 for details.  */
+  if (info->rop_hash_size)
+flag_shrink_wrap = 0;
 
   frame_pointer_needed_indeed
 = frame_pointer_needed && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0bcc6a2d0ab6..f2bd9edea8a1 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3431,10 +3431,6 @@ rs6000_override_options_after_change (void)
   else if (!OPTION_SET_P (flag_cunroll_grow_size))
 flag_cunroll_grow_size = flag_peel_loops || optimize >= 3;
 
-  /* If we are inserting ROP-protect instructions, disable shrink wrap.  */
-  if (rs6000_rop_protect)
-flag_shrink_wrap = 0;
-
   /* One of the late-combine passes runs after register allocation
  and can match define_insn_and_splits that were previously used
  only before register allocation.  Some of those define_insn_and_splits
diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-1.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-1.c
new file mode 100644
index ..579e08e920f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mrop-protect 
-fdump-rtl-pro_and_epilogue" } */
+/* { dg-require-effective-target rop_ok } Only enable on supported ABIs. */
+
+/* Verify we still attempt shrink-wrapping when using -mrop-protect
+   and there are no function calls.  */
+
+long
+foo (long arg)
+{
+  if (arg)
+asm ("" ::: "r20");
+  return 0;
+}
+
+/* { dg-final { scan-rtl-dump-times "Performing shrink-wrapping" 1 
"pro_and_epilogue" } } */

[gcc/ibm/heads/gcc-14-branch] (210 commits) ibm: Merge up to top of releases/gcc-14

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-14-branch' was updated to point to:

 7ea4c6f44d3... ibm: Merge up to top of releases/gcc-14

It previously pointed to:

 a9332cff81c... ibm: Merge up to top of releases/gcc-14

Diff:

Summary of changes (added commits):
---

  7ea4c6f... ibm: Merge up to top of releases/gcc-14
  63c51e0... c++/coroutines: fix passing *this to promise type, again [P (*)
  d9bd361... [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests (*)
  8c98f06... RISC-V: Make full-vec-move1.c test robust for optimization (*)
  7268985... Daily bump. (*)
  e903ada... s390: Fix high-level builtins vec_gfmsum{,_accum}_128 (*)
  5a63e19... Daily bump. (*)
  7d9bb37... Add -mcpu=power11 support. (*)
  f688431... Daily bump. (*)
  6bfd78c... Daily bump. (*)
  534ffe7... Daily bump. (*)
  6f1e687... Daily bump. (*)
  b0dd13e... i386: Fix up __builtin_ia32_b{extr{,i}_u{32,64},zhi_{s,d}i} (*)
  897cd79... Daily bump. (*)
  9ca1d7a... AVR: target/116295 - Fix unrecognizable insn with __flash r (*)
  a9255df... Daily bump. (*)
  49e8eee... Daily bump. (*)
  b1102f7... c++: alias and non-type template parm [PR116223] (*)
  987fc81... c++: parse error with -std=c++14 -fconcepts [PR116071] (*)
  ba26c47... hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b))  (*)
  f2b5ca6... wide-int: Fix up mul_internal overflow checking [PR116224] (*)
  3fe5720... libquadmath: Fix up libquadmath/math/sqrtq.c compilation in (*)
  cad2693... fortran: Fix up pasto in gfc_get_array_descr_info (*)
  ba45573... sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR1 (*)
  c5ef3b9... Daily bump. (*)
  de73898... compiler: panic arguments are empty interface type (*)
  2405d29... libgomp: Remove bogus warnings from privatized-ref-2.f90. (*)
  9906a98... Fortran: Suppress bogus used uninitialized warnings [PR1088 (*)
  daced76... Update gcc fr.po (*)
  eccf707... RISC-V: xtheadmemidx: Fix mode test for pre/post-modify add (*)
  5103ee7... Daily bump. (*)
  80a64e6... Daily bump. (*)
  c386665... libstdc++: Fix __cpp_lib_chrono for old std::string ABI (*)
  99eb84f... Daily bump. (*)
  21e2d27... Update gcc .po files (*)
  14fa2b2... forwprop: Don't add uses to dce list if debug statement [PR (*)
  a295076... Refine constraint "Bk" to define_special_memory_constraint. (*)
  30f4fa3... i386: Add non-optimize prefetchi intrins (*)
  79d32ba... LoongArch: Remove gawk extension from a generator script. (*)
  81db685... c++: generic lambda in default template argument [PR88313] (*)
  37e54ff... c++: alias of alias tmpl with dependent attrs [PR115897] (*)
  59e3934... libstdc++: fix uses of explicit object parameter [PR116038] (*)
  241f710... c++: normalizing ttp constraints [PR115656] (*)
  e548a88... c++: missing SFINAE during alias CTAD [PR115296] (*)
  1287b4a... c++: prev declared hidden tmpl friend inst [PR112288] (*)
  fb8da40... Daily bump. (*)
  c637241... libstdc++: Add [[nodiscard]] to some std::locale functions (*)
  c79e73e... libstdc++: Add missing constexpr to __atomic_impl::__clear_ (*)
  8d52ae3... libstdc++: Initialize base in test allocator's constructor (*)
  d8e5645... libstdc++: Fix std::tr2::dynamic_bitset shift operations [P (*)
  a78480c... libstdc++: Remove std::basic_format_args default constructo (*)
  85d07df... libstdc++: Make std::basic_format_context non-copyable [PR1 (*)
  7d269e3... libstdc++: Make std::any_cast ill-formed (LWG 3305) (*)
  095be59... libstdc++: Define __cpp_lib_ranges in  (*)
  11b5ad5... libstdc++: Use direct-initialization for std::vector' (*)
  5fcdb36... libstdc++: Use __glibcxx_ranges_as_const to guard P2278R4 c (*)
  a1e1665... libstdc++: Use reserved form of [[__likely__]] in  (*)
  9ba75a6... libstdc++: Fix  and  for -std=gnu++14 -fc (*)
  ce84aba... libstdc++: Fix std::vector for -std=gnu++14 -fconcept (*)
  973097d... i386: Fix up *_vinsert= 4 constant ele (*)
  187eec8... Fix Xcode 16 build break with NULL != nullptr (*)
  0abce41... RISC-V: Split vwadd.wx and vwsub.wx and add helpers. (*)
  937713a... RISC-V: Do not allow v0 as dest when merging [PR115068]. (*)
  3a7e796... RISC-V: Add -X to link spec (*)
  92003fa... RISC-V: Fix parsing of Zic* extensions (*)
  68ef0c3... RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar (*)
  c38dbfc... RISC-V: Fix missing boolean_expression in zmmul extension (*)
  4db3875... RISC-V: Bugfix vec_extract v mode iterator restriction mism (*)
  87346ed... RISC-V: Bugfix vec_extract vls mode iterator restriction mi (*)
  c32995c... [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_ (*)
  2d7dda8... RISC-V: Use tu policy for first-element vec_set [PR115725]. (*)
  b218c42... [RISC-V] add implied extension repeatly until stable (*)
  a2a2916... Daily bump. (*)
  493035c... eh: ICE with std::initializer_list and ASan [PR115865] (*)
  747c4b5... Do not use caller-saved registers for COMDAT functions (*)
  c314867... c++: ICE with __has_unique_object_representations [PR115476 (*)
  a4c9ade... i386: PR targe

[gcc/ibm/heads/gcc-13-branch] (553 commits) ibm: Merge up to top of releases/gcc-13

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-13-branch' was updated to point to:

 c3db5f495a1... ibm: Merge up to top of releases/gcc-13

It previously pointed to:

 efb4bfb219d... ibm: Merge up to top of releases/gcc-13

Diff:

Summary of changes (added commits):
---

  c3db5f4... ibm: Merge up to top of releases/gcc-13
  ebca600... Daily bump. (*)
  fd91953... libstdc++: Fix up 19_diagnostics/stacktrace/hash.cc on 13 b (*)
  3185cfe... Fortran: Fix SHAPE for zero-size arrays (*)
  67434fe... libstdc++: Guard use of sized deallocation [PR114940] (*)
  d7f9f23... Daily bump. (*)
  b954f15... Daily bump. (*)
  513d050... Daily bump. (*)
  91c7ec5... Daily bump. (*)
  53cdaa7... c++: unroll pragma in templates [PR111529] (*)
  5f14578... c++: array of PMF [PR113598] (*)
  cf76815... Daily bump. (*)
  6f8933c... Daily bump. (*)
  75d394c... testsuite: Verify r0-r3 are extended with CMSE (*)
  f0b88ec... Fortran: fix issues with class(*) assignment [PR114827] (*)
  2ebf3af... Fortran: fix reallocation on assignment of polymorphic vari (*)
  53bc98f... strlen: Fix up !si->full_string_p handling in count_nonzero (*)
  35ac28b... ubsan: Use right address space for MEM_REF created for bool (*)
  a841964... Daily bump. (*)
  9433e30... libstdc++: testsuite: Enhance codecvt_unicode with tests fo (*)
  bd5e672... libstdc++: Fix handling of surrogate CP in codecvt [PR10897 (*)
  0a9df2c... c++: Fix std dialect hint for std::to_address [PR107800] (*)
  5ed32d0... Fortran: fix dependency checks for inquiry refs [PR115039] (*)
  c827f46... testsuite: Adjust pr113359-2_*.c with unsigned long long [P (*)
  3f6a425... PHIOPT: Don't transform minmax if middle bb contains a phi  (*)
  d6cf49e... match: Disable `(type)zero_one_valuep*CST` for 1bit signed  (*)
  bde5894... Bump BASE-VER. (*)
  b71f1de... Update ChangeLog and version files for release (*)
  a021b58... Daily bump. (*)
  4416023... Daily bump. (*)
  94509b6... Daily bump. (*)
  162c441... [committed] Fix RISC-V missing stack tie (*)
  5b5342e... Daily bump. (*)
  851aa3b... Daily bump. (*)
  1db45e8... ipa: Compare jump functions in ICF (PR 113907) (*)
  10bf53a... ICF&SRA: Make ICF and SRA agree on padding (*)
  7dca716... libstdc++: Fix typo in std::stacktrace::max_size [PR115063] (*)
  71e941b... libstdc++: Fix infinite loop in std::binomial_distribution  (*)
  b9e2a32... libstdc++: Adjust expected locale-dependent date formats in (*)
  ebc61a9... libstdc++: Fix typo in Doxygen comment (*)
  bce15a5... libstdc++: Fix run_doxygen for Doxygen 1.10 man page format (*)
  47cac09... c++: build_extra_args recapturing local specs [PR114303] (*)
  12ee04d... Daily bump. (*)
  d3659e2... c++: constexpr union member access folding [PR114709] (*)
  2e353c6... Manually add ChangeLog entries for various commits from 202 (*)
  d629308... rtl-optimization/54052 - RTL SSA PHI insertion compile-time (*)
  6d1801f... Daily bump. (*)
  b7a2697... diagnostics: fix corrupt json/SARIF on stderr [PR114348] (*)
  2a6f99a... Fix ICE in -fdiagnostics-generate-patch [PR112684] (*)
  230f672... diagnostics: fix ICE on sarif output when source file is un (*)
  96f7a36... analyzer: fix ICE and false positive with -Wanalyzer-deref- (*)
  810d35a... analyzer: fix ICE due to type mismatch when replaying call  (*)
  ed02610... analyzer: fix -Wanalyzer-deref-before-check false positive  (*)
  67d104f... analyzer: fix -Wanalyzer-va-arg-type-mismatch false +ve on  (*)
  2c688f6... analyzer: fix skipping of debug stmts [PR113253] (*)
  0593151... analyzer: fix defaults in compound assignments from non-zer (*)
  132eb1a... analyzer: casting all zeroes should give all zeroes [PR1133 (*)
  994477c... analyzer: fix deref-before-check false positives due to inl (*)
  a1cb188... analyzer: fix ICE for 2 bits before the start of base regio (*)
  b8c772c... jit: dump string literal initializers correctly (*)
  44968a0... testsuite, analyzer: add test case [PR108171] (*)
  a0b13d0... analyzer: fix ICE on zero-sized arrays [PR110882] (*)
  0df1ee0... analyzer: fix ICE on division of tainted floating-point val (*)
  60dcb71... jit.exp: handle dwarf version mismatch in jit-check-debug-i (*)
  b38472f... jit: avoid using __vector in testcase [PR110466] (*)
  e0c5290... testsuite: Add more allocation size tests for conjured sval (*)
  ccf8d3e... analyzer: Fix allocation size false positive on conjured sv (*)
  89feb35... analyzer: add caching to globals with initializers [PR11011 (*)
  e30211c... [PR114415][scheduler]: Fixing wrong code generation (*)
  421311a... Fix range-ops operator_addr. (*)
  fefdb9f... Daily bump. (*)
  6f7674a... testsuite: Fix up vector-subaccess-1.C test for ia32 [PR892 (*)
  adba85b... AVR: target/114981 - Support __builtin_powi[l] / __powidf2. (*)
  44d84db... reassoc: Fix up optimize_range_tests_to_bit_test [PR114965] (*)
  cad27df... expansion: Use __trunchfbf2 calls rather than __extendhfbf2 (*)
  d1ec7bc... tree-inline: Remove .ASAN_MARK calls when inlining function 

[gcc(refs/vendors/ibm/heads/gcc-13-branch)] ibm: Merge up to top of releases/gcc-13

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:c3db5f495a1543fb22f725be910dc46249a15e57

commit c3db5f495a1543fb22f725be910dc46249a15e57
Merge: efb4bfb219d ebca6006f44
Author: Peter Bergner 
Date:   Wed May 29 10:48:31 2024 -0500

ibm: Merge up to top of releases/gcc-13

2024-05-29  Peter Bergner  

Merge up to releases/gcc-13 ebca6006f44408b8084868da6613f185b810db74

Diff:

 ChangeLog  |   15 +
 Makefile.in|   30 +
 Makefile.tpl   |   24 +
 c++tools/ChangeLog |4 +
 config/ChangeLog   |4 +
 contrib/ChangeLog  |   13 +
 contrib/dg-extract-results.sh  |   17 +-
 contrib/header-tools/ChangeLog |4 +
 contrib/reghunt/ChangeLog  |4 +
 contrib/regression/ChangeLog   |4 +
 fixincludes/ChangeLog  |4 +
 gcc/BASE-VER   |2 +-
 gcc/ChangeLog  | 1964 ++
 gcc/ChangeLog.ibm  |4 +
 gcc/DATESTAMP  |2 +-
 gcc/ada/ChangeLog  |   50 +
 gcc/ada/exp_attr.adb   |   63 +-
 gcc/ada/exp_ch4.adb|2 -
 gcc/ada/exp_ch7.adb|   13 +
 gcc/ada/exp_util.adb   |   15 +-
 gcc/ada/sem_aggr.adb   |9 +-
 gcc/ada/sem_ch13.adb   |   12 +-
 gcc/ada/sem_res.adb|   14 +-
 gcc/analyzer/ChangeLog |  148 +
 gcc/analyzer/call-summary.cc   |   12 +
 gcc/analyzer/checker-event.cc  |   40 -
 gcc/analyzer/constraint-manager.cc |  131 +
 gcc/analyzer/constraint-manager.h  |1 +
 gcc/analyzer/engine.cc |7 +
 gcc/analyzer/inlining-iterator.h   |   40 +
 gcc/analyzer/kf.cc |   22 +
 gcc/analyzer/region-model-manager.cc   |9 +-
 gcc/analyzer/region-model.cc   |  110 +-
 gcc/analyzer/region.cc |   77 +-
 gcc/analyzer/region.h  |   14 +-
 gcc/analyzer/sm-malloc.cc  |   40 +
 gcc/analyzer/sm-taint.cc   |6 +
 gcc/analyzer/state-purge.cc|9 +
 gcc/analyzer/store.cc  |   11 +-
 gcc/analyzer/store.h   |   10 +-
 gcc/analyzer/supergraph.cc |4 +
 gcc/analyzer/varargs.cc|   38 +-
 gcc/asan.cc|   52 +-
 gcc/attribs.cc |   17 +-
 gcc/bb-reorder.cc  |3 +-
 gcc/bitmap.cc  |2 +-
 gcc/c-family/ChangeLog |   49 +
 gcc/c-family/c-attribs.cc  |   32 +-
 gcc/c-family/c-common.cc   |8 +-
 gcc/c-family/c-lex.cc  |   32 +-
 gcc/c-family/c-pch.cc  |5 +-
 gcc/c/ChangeLog|   14 +
 gcc/c/c-decl.cc|7 +-
 gcc/calls.cc   |7 +-
 gcc/cfgexpand.cc   |   32 +-
 gcc/cfgrtl.cc  |   27 +-
 gcc/cfgrtl.h   |1 +
 gcc/cgraph.cc  |   10 +-
 gcc/cgraph.h   |   15 +-
 gcc/cgraphunit.cc  |2 +
 gcc/combine.cc |   12 +-
 gcc/common.opt |2 +-
 gcc/common/config/avr/avr-common.cc|6 -
 gcc/common/config/i386/i386-common.cc  |2 +-
 gcc/config.gcc |1 +
 gcc/config.in  |   21 +-
 gcc/config/aarch64/aarch64-arches.def  |2 +-
 gcc/config/aarch64/aarch64-builtins.cc |2 +-
 gcc/config/aarch64/aarch64-cores.def   |2 +-
 gcc/config/aarch64/aarch64.cc  |   31 +-
 gcc/config/aarch64/aarch64.md  |   35 +-
 gcc/config/aarch64/iterators.md|3 +
 gcc/config/aarch64/t-aarch64-rtems |   42 +
 gcc/config/alpha/alpha.cc  |3 +-
 gcc/config/arc/arc.cc  |   

[gcc/ibm/heads/gcc-12-branch] (363 commits) ibm: Merge up to top of releases/gcc-12

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-12-branch' was updated to point to:

 92786addfe0... ibm: Merge up to top of releases/gcc-12

It previously pointed to:

 9f2e51a88fb... ibm: Merge up to top of releases/gcc-12

Diff:

Summary of changes (added commits):
---

  92786ad... ibm: Merge up to top of releases/gcc-12
  342f577... Daily bump. (*)
  da9b7a5... ubsan: Use right address space for MEM_REF created for bool (*)
  e0b2c4f... Fortran: Fix SHAPE for zero-size arrays (*)
  72f6b7e... ipa: Compare jump functions in ICF (PR 113907) (*)
  3bb534d... Daily bump. (*)
  4507501... Daily bump. (*)
  0bd259a... Daily bump. (*)
  e11d3dd... Daily bump. (*)
  ba57a52... c++: __is_constructible ref binding [PR100667] (*)
  6a5dcdb... c++: fix PR111529 backport (*)
  1982783... c++: unroll pragma in templates [PR111529] (*)
  419b5e1... c++: array of PMF [PR113598] (*)
  7076c56... c++: binding reference to comma expr [PR114561] (*)
  a1ff317... Daily bump. (*)
  df19155... Daily bump. (*)
  d9c8940... testsuite: Verify r0-r3 are extended with CMSE (*)
  13ced60... Daily bump. (*)
  113ddbe... Daily bump. (*)
  2f0c2cc... Daily bump. (*)
  1ba6e8b... Daily bump. (*)
  65e5547... middle-end/110176 - wrong zext (bool) <= (int) 4294967295u  (*)
  47e6bff... tree-optimization/111039 - abnormals and bit test merging (*)
  5db4b54... tree-optimization/112281 - loop distribution and zero depen (*)
  dbb5273... tree-optimization/112495 - alias versioning and address spa (*)
  4a71557... tree-optimization/112505 - bit-precision induction vectoriz (*)
  1f41e8e... debug/112718 - reset all type units with -ffat-lto-objects (*)
  9bad5cf... tree-optimization/112793 - SLP of constant/external code-ge (*)
  2d650c0... tree-optimization/114027 - fix testcase (*)
  6661a7c... tree-optimization/114027 - conditional reduction chain (*)
  c1b2185... tree-optimization/114375 - disallow SLP discovery of permut (*)
  a7b1d81... tree-optimization/114231 - use patterns for BB SLP discover (*)
  46b2e98... middle-end/114734 - wrong code with expand_call_mem_ref (*)
  42a0393... lto/114655 - -flto=4 at link time doesn't override -flto=au (*)
  56415e3... gcov-profile/114715 - missing coverage for switch (*)
  b656e65... Daily bump. (*)
  2183e5b... ipa: Self-DCE of uses of removed call LHSs (PR 108007) (*)
  4419198... ipa: Force args obtined through pass-through maps to the ex (*)
  de66146... Daily bump. (*)
  2beef72... Daily bump. (*)
  c5c3a4a... Fix range-ops operator_addr. (*)
  f7db003... Daily bump. (*)
  587596d... Objective-C, NeXT, v2: Correct a regression in code-gen. (*)
  3349a6c... Daily bump. (*)
  ffa41c6... testsuite: Fix up vector-subaccess-1.C test for ia32 [PR892 (*)
  f5c7306... Fix PR 110386: backprop vs ABSU_EXPR (*)
  58d11bf... testsuite: fix Wmismatched-new-delete-8.C with -m32 (*)
  16319f8... warn-access: Fix handling of unnamed types [PR109804] (*)
  39d56b9... Fix PR 111331: wrong code for `a > 28 ? MIN : 29` (*)
  d88fe82... Fold: Fix up merge_truthop_with_opposite_arm for NaNs [PR95 (*)
  0ab30fb... libstdc++: Fix conversion of simd to vector builtin (*)
  79aa696... libstdc++: Silence irrelevant warnings in  (*)
  7abc861... libstdc++: Fix -Wsystem-headers warnings in tests (*)
  c0c1207... libstdc++: Update  synopsis test for C++11 and late (*)
  2d174d4... libstdc++: Fix -Wsystem-headers warnings (*)
  14876f3... libstdc++: Improve doxygen docs for  (*)
  0a9cfae... libstdc++: Improve doxygen docs for some of  (*)
  0d128f5... libstdc++: Improve doxygen docs for algorithms and more (*)
  54de91d... libstdc++: Improve doxygen docs for std::allocator (*)
  e1800b8... libstdc++: Improve doxygen docs for  (*)
  f0db5df... libstdc++: Improve doxygen docs for  (*)
  914a226... libstdc++: Stop defining C++0x compat symbols for versioned (*)
  f8ab9b7... libstdc++: Add macros for the inline namespace std::_V2 (*)
  d9f006d... libstdc++: Disable Doxygen GROUP_NESTED_COMPOUNDS config op (*)
  f3d4e25... libstdc++: Simplify fs::path construction using variable te (*)
  57eb035... libstdc++: Update std::pointer_traits to match new LWG 3545 (*)
  1bb467f... libstdc++: Simplify detection idiom using concepts (*)
  51e9dcc... libstdc++: Improve doxygen docs for std::pointer_traits (*)
  c6f80dc... libstdc++: use grep -E instead of egrep in scripts (*)
  5c156f5... libstdc++: Fix allocator propagation in regex algorithms [P (*)
  e35b26c... libstdc++: Define std::basic_stringbuf::view() for old std: (*)
  0135f93... libstdc++: Add autoconf checks for mkdir, chmod, chdir, and (*)
  a389921... libstdc++: Explicitly default some copy ctors and assignmen (*)
  dc0964f... libstdc++: Add static_assert to std::integer_sequence [PR11 (*)
  15c5170... libstdc++: Remove non-void static assertions in variant's s (*)
  c285c1b... libstdc++: Fix exception thrown by std::shared_lock::unlock (*)
  6f5dcea... libstdc++: Fix conditions for using memcmp in std::lexicogr (*)
  8ec265c... libstdc++: Do not use memmove 

[gcc r15-1115] rs6000: Update ELFv2 stack frame comment showing the correct ROP save location

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:e91cf26a954a5c1bf431e36f3a1e69f94e9fa4fe

commit r15-1115-ge91cf26a954a5c1bf431e36f3a1e69f94e9fa4fe
Author: Peter Bergner 
Date:   Fri Jun 7 16:03:08 2024 -0500

rs6000: Update ELFv2 stack frame comment showing the correct ROP save 
location

The ELFv2 stack frame layout comment in rs6000-logue.cc shows the ROP
hash save slot in the wrong location.  Update the comment to show the
correct ROP hash save location in the frame.

2024-06-07  Peter Bergner  

gcc/
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Update comment.

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index bd5d56ba002..d61a25a5126 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -591,21 +591,21 @@ rs6000_savres_strategy (rs6000_stack_t *info,
+---+
| Parameter save area (+padding*) (P)   |  32
+---+
-   | Optional ROP hash slot (R)|  32+P
+   | Alloca space (A)  |  32+P
+---+
-   | Alloca space (A)  |  32+P+R
+   | Local variable space (L)  |  32+P+A
+---+
-   | Local variable space (L)  |  32+P+R+A
+   | Optional ROP hash slot (R)|  32+P+A+L
+---+
-   | Save area for AltiVec registers (W)   |  32+P+R+A+L
+   | Save area for AltiVec registers (W)   |  32+P+A+L+R
+---+
-   | AltiVec alignment padding (Y) |  32+P+R+A+L+W
+   | AltiVec alignment padding (Y) |  32+P+A+L+R+W
+---+
-   | Save area for GP registers (G)|  32+P+R+A+L+W+Y
+   | Save area for GP registers (G)|  32+P+A+L+R+W+Y
+---+
-   | Save area for FP registers (F)|  32+P+R+A+L+W+Y+G
+   | Save area for FP registers (F)|  32+P+A+L+R+W+Y+G
+---+
-   old SP->| back chain to caller's caller |  32+P+R+A+L+W+Y+G+F
+   old SP->| back chain to caller's caller |  32+P+A+L+R+W+Y+G+F
+---+
 
  * If the alloca area is present, the parameter save area is

[gcc] Created branch 'ibm/heads/gcc-14-branch' in namespace 'refs/vendors'

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-14-branch' was created in namespace 'refs/vendors' 
pointing to:

 7593dae69ba0... arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR11

[gcc(refs/vendors/ibm/heads/gcc-14-branch)] ibm: Create the ibm/gcc-14-branch

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:96b284e64a7f1c3bfce4e5434c407799bbfbcd98

commit 96b284e64a7f1c3bfce4e5434c407799bbfbcd98
Author: Peter Bergner 
Date:   Wed Jun 12 11:19:31 2024 -0500

ibm: Create the ibm/gcc-14-branch

2024-06-12  Peter Bergner  

Create ibm/gcc-14-branch which follows the releases/gcc-14 branch.

Diff:
---
 gcc/ChangeLog.ibm | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/ChangeLog.ibm b/gcc/ChangeLog.ibm
new file mode 100644
index ..3ebc8710b3b7
--- /dev/null
+++ b/gcc/ChangeLog.ibm
@@ -0,0 +1,3 @@
+2024-06-12  Peter Bergner  
+
+   Create ibm/gcc-14-branch which follows the releases/gcc-14 branch.

[gcc r15-1232] rs6000: Fix pr66144-3.c test to accept multiple equivalent insns. [PR115262]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:ae8103a3a13ac412b9ca33222594cb507ceac9f7

commit r15-1232-gae8103a3a13ac412b9ca33222594cb507ceac9f7
Author: Peter Bergner 
Date:   Wed Jun 12 21:05:34 2024 -0500

rs6000: Fix pr66144-3.c test to accept multiple equivalent insns. [PR115262]

Jeff's commit r15-831-g05daf617ea22e1 changed the instruction we expected
for this test case into an equivalent instruction.  Modify the test case
so it will accept any of three instructions we could get depending on the
options used.

2024-06-12  Peter Bergner  

gcc/testsuite/
PR testsuite/115262
* gcc.target/powerpc/pr66144-3.c (dg-do): Compile for all targets.
(dg-options): Add -fno-unroll-loops and remove -mvsx.
(scan-assembler): Change from this...
(scan-assembler-times): ...to this.  Tweak regex to accept multiple
allowable instructions.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/pr66144-3.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr66144-3.c 
b/gcc/testsuite/gcc.target/powerpc/pr66144-3.c
index 4c93b2a7a3da..14ecb809edc2 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr66144-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr66144-3.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { powerpc64*-*-* } } } */
-/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize" } */
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fno-unroll-loops" 
} */
 /* { dg-require-effective-target powerpc_vsx } */
 
 /* Verify that we can optimize a vector conditional move, where one of the arms
@@ -20,7 +20,7 @@ test (void)
 a[i] = (b[i] == c[i]) ? -1 : a[i];
 }
 
-/* { dg-final { scan-assembler {\mvcmpequw\M} } } */
-/* { dg-final { scan-assembler {\mxxsel\M}} } */
+/* { dg-final { scan-assembler-times {\mvcmpequw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\m(?:xxsel|xxlor|vor)\M} 1 } } */
 /* { dg-final { scan-assembler-not {\mvspltisw\M} } } */
 /* { dg-final { scan-assembler-not {\mxxlorc\M}   } } */

[gcc r15-1377] rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:c70eea0dba5f223d49c80cfb3e80e87b74330aac

commit r15-1377-gc70eea0dba5f223d49c80cfb3e80e87b74330aac
Author: Peter Bergner 
Date:   Fri Jun 14 14:36:20 2024 -0500

rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

We currently only compute the offset for the ROP hash save location in
the stack frame for Altivec compiles.  For non-Altivec compiles when we
emit ROP mitigation instructions, we use a default offset of zero which
corresponds to the backchain save location which will get clobbered on
any call.  The fix is to compute the ROP hash save location for all
compiles.

2024-06-14  Peter Bergner  

gcc/
PR target/115389
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute
rop_hash_save_offset for non-Altivec compiles.

gcc/testsuite
PR target/115389
* gcc.target/powerpc/pr115389.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc   |  9 -
 gcc/testsuite/gcc.target/powerpc/pr115389.c | 17 +
 2 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index d61a25a51264..193e2122c0f9 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -817,17 +817,16 @@ rs6000_stack_info (void)
  gcc_assert (info->altivec_size == 0
  || info->altivec_save_offset % 16 == 0);
 
- /* Adjust for AltiVec case.  */
- info->ehrd_offset = info->altivec_save_offset - ehrd_size;
-
  /* Adjust for ROP protection.  */
  info->rop_hash_save_offset
= info->altivec_save_offset - info->rop_hash_size;
- info->ehrd_offset -= info->rop_hash_size;
}
   else
-   info->ehrd_offset = info->gp_save_offset - ehrd_size;
+ /* Adjust for ROP protection.  */
+ info->rop_hash_save_offset
+   = info->gp_save_offset - info->rop_hash_size;
 
+  info->ehrd_offset = info->rop_hash_save_offset - ehrd_size;
   info->ehcr_offset = info->ehrd_offset - ehcr_size;
   info->cr_save_offset = reg_size; /* first word when 64-bit.  */
   info->lr_save_offset = 2*reg_size;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115389.c 
b/gcc/testsuite/gcc.target/powerpc/pr115389.c
new file mode 100644
index ..a091ee8a1be0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr115389.c
@@ -0,0 +1,17 @@
+/* PR target/115389 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mrop-protect -mno-vsx -mno-altivec 
-mabi=no-altivec -save-temps" } */
+/* { dg-require-effective-target rop_ok } */
+
+/* Verify we do not emit invalid offsets for our ROP insns.  */
+
+extern void foo (void);
+long
+bar (void)
+{
+  foo ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */

[gcc/ibm/heads/gcc-12-branch] (99 commits) ibm: Merge up to top of releases/gcc-12

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-12-branch' was updated to point to:

 3409c8aae4b... ibm: Merge up to top of releases/gcc-12

It previously pointed to:

 92786addfe0... ibm: Merge up to top of releases/gcc-12

Diff:

Summary of changes (added commits):
---

  3409c8a... ibm: Merge up to top of releases/gcc-12
  218adac... Daily bump. (*)
  169d4d1... libstdc++: Fix test on x86_64 and non-simd targets (*)
  8b5bdeb... libstdc++: Fix find_last_set(simd_mask) to ignore padding b (*)
  cdbff5f... Daily bump. (*)
  b9569e7... libstdc++: Fix simd conversion for -fno-signed-char f (*)
  f79b273... libstdc++: Avoid MMX return types from __builtin_shufflevec (*)
  fb06754... libstdc++: Use __builtin_shufflevector for simd split and c (*)
  c60dd0e... diagnostics: Fix add_misspelling_candidates [PR115440] (*)
  8f612e6... c-family: Fix -Warray-compare warning ICE [PR115290] (*)
  98794d9... Bump BASE-VER. (*)
  2bada4b... Update ChangeLog and version files for release (*)
  fac4fbd... Daily bump. (*)
  9c0c31d... Daily bump. (*)
  b87418f... Daily bump. (*)
  ea0aa97... libstdc++: Fix declaration of posix_memalign for freestandi (*)
  caa4702... Daily bump. (*)
  26640a5... Daily bump. (*)
  573a5f3... Daily bump. (*)
  5319283... Daily bump. (*)
  6693b1f... Daily bump. (*)
  448dd00... arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR11 (*)
  33663c0... cfgrtl: Fix MEM_EXPR update in duplicate_insn_chain [PR1149 (*)
  959cef9... [PR111497][LRA]: Copy substituted equivalence (*)
  844ff32... middle-end/40635 - SSA update losing PHI arg loations (*)
  1edc6a7... rtl-optimization/54052 - RTL SSA PHI insertion compile-time (*)
  3d9e4ee... testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115 (*)
  55c1687... arm: Zero/Sign extends for CMSE security on Armv8-M.baselin (*)
  f38ffe3... Daily bump. (*)
  a995fde... Include safe-ctype.h after C++ standard headers, to avoid o (*)
  8f11ed1... libcc1: fix  include (*)
  d30afaa... PHIOPT: Don't transform minmax if middle bb contains a phi  (*)
  870e389... libstdc++: Fix fwrite error parameter (*)
  3837f95... libstdc++: Define __cpp_lib_constexpr_algorithms in  [ (*)
  80d0f82... libstdc++: Reverse arguments in constraint for std::optiona (*)
  c394e29... libstdc++: Destroy allocators in re-inserted container node (*)
  d4126b3... c: Fix up pointer types to may_alias structures [PR114493] (*)
  b065824... fold-const: Fix up CLZ handling in tree_call_nonnegative_wa (*)
  91a3712... builtins: Force SAVE_EXPR for __builtin_{add,sub,mul}_overf (*)
  bda8c28... rs6000: Fix up PCH in --enable-host-pie builds [PR115324] (*)
  840bc67... combine: Fix up simplify_compare_const [PR115092] (*)
  25bd98d... tree-inline: Remove .ASAN_MARK calls when inlining function (*)
  bf13440... gimple-ssa-sprintf: Use [0, 1] range for %lc with (wint_t)  (*)
  cc96dc5... openmp: Copy DECL_LANG_SPECIFIC and DECL_LANG_FLAG_? to tre (*)
  7d06735... rtlanal: Fix set_noop_p for volatile loads or stores [PR114 (*)
  b3ef00f... internal-fn: Temporarily disable flag_trapv during .{ADD,SU (*)
  bb21a7d... attribs: Don't crash on NULL TREE_TYPE in diag_attr_exclusi (*)
  e9b960e... c++: Fix bogus warnings about ignored annotations [PR114691 (*)
  082fe43... asan, v3: Fix up handling of > 32 byte aligned variables wi (*)
  b3b7176... c++: Fix up maybe_warn_for_constant_evaluated calls [PR1145 (*)
  f8a3279... vect: Don't clear base_misaligned in update_epilogue_loop_v (*)
  f33e8ee... c++: Fix ICE with weird copy assignment operator [PR114572] (*)
  42afabb... fold-const: Handle NON_LVALUE_EXPR in native_encode_initial (*)
  9987fe6... libquadmath: Don't assume the storage for __float128 argume (*)
  81c300b... icf: Reset SSA_NAME_{PTR,RANGE}_INFO in successfully merged (*)
  9f48459... aarch64: Fix TImode __sync_*_compare_and_exchange expansion (*)
  b294d46... bb-reorder: Fix -freorder-blocks-and-partition ICEs on aarc (*)
  9299722... i386: Fix ICEs with SUBREGs from vector etc. constants to X (*)
  c2cd5ee... c: Handle scoped attributes in __has*attribute and scoped a (*)
  fda7a89... attribs: Don't canonicalize lookup_scoped_attribute_spec ar (*)
  e697601... ggc-common: Fix save PCH assertion (*)
  f5758e8... tree-ssa-strlen: Fix up handle_store [PR113603] (*)
  ba38543... docs: Fix 2 typos (*)
  bc51282... i386: Add -masm=intel profiling support [PR113122] (*)
  170c2bb... cfgexpand: Workaround CSE of ADDR_EXPRs in VAR_DECL partiti (*)
  3f0d1e5... libgomp: Fix up FLOCK fallback handling [PR113192] (*)
  ca8ad80... c-family: copy attribute diagnostic fixes [PR113262] (*)
  d73137a... tree-optimization/111070 - fix ICE with recent ifcombine fi (*)
  cc835f4... Daily bump. (*)
  12a3ba2... Fix crash on access-to-incomplete type (*)
  481a766... Daily bump. (*)
  6e35fb3... Daily bump. (*)
  4745c29... Daily bump. (*)
  5d52558... Disable FMADD in chains for Zen4 and generic (*)
  208c8dc... Daily bump. (*)
  a741bb3... Daily bump. (*)
  a7edd18... Daily bump. (*

[gcc] Created branch 'ibm/heads/mmaplus' in namespace 'refs/vendors'

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/mmaplus' was created in namespace 'refs/vendors' pointing 
to:

 bf11ecbb02b5... testsuite: Add test directive checking removal of link_erro

[gcc r12-10790] rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:eeb72f26ea7e70baadf2e3b9e89e8f7055fec0a9

commit r12-10790-geeb72f26ea7e70baadf2e3b9e89e8f7055fec0a9
Author: Peter Bergner 
Date:   Fri Aug 23 11:45:40 2024 -0500

rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

Our power8 swap optimization pass has some special handling for optimizing
swaps of TImode variables.  The test case reported in bugzilla uses a call
to  __atomic_compare_exchange, which introduces a variable of PTImode and
that does not get the same treatment as TImode leading to wrong code
generation.  The simple fix is to treat PTImode identically to TImode.

2024-08-23  Peter Bergner  

gcc/
PR target/116415
* config/rs6000/rs6000.h (TI_OR_PTI_MODE): New define.
* config/rs6000/rs6000-p8swap.cc (rs6000_analyze_swaps): Use it to
handle PTImode identically to TImode.

gcc/testsuite/
PR target/116415
* gcc.target/powerpc/pr116415.c: New test.

(cherry picked from commit 6e68c3df1540c5bafbb47343698bf4e270333fdb)

Diff:
---
 gcc/config/rs6000/rs6000-p8swap.cc  |  8 +++---
 gcc/config/rs6000/rs6000.h  |  2 ++
 gcc/testsuite/gcc.target/powerpc/pr116415.c | 42 +
 3 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-p8swap.cc 
b/gcc/config/rs6000/rs6000-p8swap.cc
index 62f5ca5bff4a..e97a32b4c236 100644
--- a/gcc/config/rs6000/rs6000-p8swap.cc
+++ b/gcc/config/rs6000/rs6000-p8swap.cc
@@ -2467,10 +2467,10 @@ rs6000_analyze_swaps (function *fun)
mode = V4SImode;
}
 
- if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || mode == TImode)
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || TI_OR_PTI_MODE (mode))
{
  insn_entry[uid].is_relevant = 1;
- if (mode == TImode || mode == V1TImode
+ if (TI_OR_PTI_MODE (mode) || mode == V1TImode
  || FLOAT128_VECTOR_P (mode))
insn_entry[uid].is_128_int = 1;
  if (DF_REF_INSN_INFO (mention))
@@ -2495,10 +2495,10 @@ rs6000_analyze_swaps (function *fun)
  && ALTIVEC_OR_VSX_VECTOR_MODE (GET_MODE (SET_DEST (insn
mode = GET_MODE (SET_DEST (insn));
 
- if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || mode == TImode)
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || TI_OR_PTI_MODE (mode))
{
  insn_entry[uid].is_relevant = 1;
- if (mode == TImode || mode == V1TImode
+ if (TI_OR_PTI_MODE (mode) || mode == V1TImode
  || FLOAT128_VECTOR_P (mode))
insn_entry[uid].is_128_int = 1;
  if (DF_REF_INSN_INFO (mention))
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 5588a4bae027..48ba4df1da5c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1051,6 +1051,8 @@ enum data_align { align_abi, align_opt, align_both };
   (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE)
\
|| (MODE) == V2DImode || (MODE) == V1TImode)
 
+#define TI_OR_PTI_MODE(mode) ((mode) == TImode || (mode) == PTImode)
+
 /* Post-reload, we can't use any new AltiVec registers, as we already
emitted the vrsave mask.  */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr116415.c 
b/gcc/testsuite/gcc.target/powerpc/pr116415.c
new file mode 100644
index ..08cc282e2c27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr116415.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* PR 116415: Verify our Power8 swap optimization pass doesn't incorrectly swap
+   PTImode values.  They should be handled identically to TImode values.  */
+
+#include 
+#include 
+#include 
+
+typedef union {
+  struct {
+uint64_t a;
+uint64_t b;
+  } t;
+  __uint128_t data;
+} Value;
+Value value, next;
+
+void
+bug (Value *val, Value *nxt)
+{
+  for (;;) {
+nxt->t.a = val->t.a + 1;
+nxt->t.b = val->t.b + 2;
+if (__atomic_compare_exchange (&val->data, &val->data, &nxt->data,
+  0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE))
+  break;
+  }
+}
+
+int
+main (void)
+{
+  bug (&value, &next);
+  printf ("%lu %lu\n", value.t.a, value.t.b);
+  if (value.t.a != 1 || value.t.b != 2)
+abort ();
+  return 0;
+}

[gcc r13-9154] rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:507ed9118b29d7a5a2b751876bec9a1f5009de01

commit r13-9154-g507ed9118b29d7a5a2b751876bec9a1f5009de01
Author: Peter Bergner 
Date:   Fri Aug 23 11:45:40 2024 -0500

rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

Our power8 swap optimization pass has some special handling for optimizing
swaps of TImode variables.  The test case reported in bugzilla uses a call
to  __atomic_compare_exchange, which introduces a variable of PTImode and
that does not get the same treatment as TImode leading to wrong code
generation.  The simple fix is to treat PTImode identically to TImode.

2024-08-23  Peter Bergner  

gcc/
PR target/116415
* config/rs6000/rs6000.h (TI_OR_PTI_MODE): New define.
* config/rs6000/rs6000-p8swap.cc (rs6000_analyze_swaps): Use it to
handle PTImode identically to TImode.

gcc/testsuite/
PR target/116415
* gcc.target/powerpc/pr116415.c: New test.

(cherry picked from commit 6e68c3df1540c5bafbb47343698bf4e270333fdb)

Diff:
---
 gcc/config/rs6000/rs6000-p8swap.cc  |  8 +++---
 gcc/config/rs6000/rs6000.h  |  2 ++
 gcc/testsuite/gcc.target/powerpc/pr116415.c | 42 +
 3 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-p8swap.cc 
b/gcc/config/rs6000/rs6000-p8swap.cc
index 0388b9bd7366..ca03b0205206 100644
--- a/gcc/config/rs6000/rs6000-p8swap.cc
+++ b/gcc/config/rs6000/rs6000-p8swap.cc
@@ -2469,10 +2469,10 @@ rs6000_analyze_swaps (function *fun)
mode = V4SImode;
}
 
- if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || mode == TImode)
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || TI_OR_PTI_MODE (mode))
{
  insn_entry[uid].is_relevant = 1;
- if (mode == TImode || mode == V1TImode
+ if (TI_OR_PTI_MODE (mode) || mode == V1TImode
  || FLOAT128_VECTOR_P (mode))
insn_entry[uid].is_128_int = 1;
  if (DF_REF_INSN_INFO (mention))
@@ -2497,10 +2497,10 @@ rs6000_analyze_swaps (function *fun)
  && ALTIVEC_OR_VSX_VECTOR_MODE (GET_MODE (SET_DEST (insn
mode = GET_MODE (SET_DEST (insn));
 
- if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || mode == TImode)
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || TI_OR_PTI_MODE (mode))
{
  insn_entry[uid].is_relevant = 1;
- if (mode == TImode || mode == V1TImode
+ if (TI_OR_PTI_MODE (mode) || mode == V1TImode
  || FLOAT128_VECTOR_P (mode))
insn_entry[uid].is_128_int = 1;
  if (DF_REF_INSN_INFO (mention))
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9f02025b0c8d..b8edba43d538 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1008,6 +1008,8 @@ enum data_align { align_abi, align_opt, align_both };
   (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE)
\
|| (MODE) == V2DImode || (MODE) == V1TImode)
 
+#define TI_OR_PTI_MODE(mode) ((mode) == TImode || (mode) == PTImode)
+
 /* Post-reload, we can't use any new AltiVec registers, as we already
emitted the vrsave mask.  */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr116415.c 
b/gcc/testsuite/gcc.target/powerpc/pr116415.c
new file mode 100644
index ..08cc282e2c27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr116415.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* PR 116415: Verify our Power8 swap optimization pass doesn't incorrectly swap
+   PTImode values.  They should be handled identically to TImode values.  */
+
+#include 
+#include 
+#include 
+
+typedef union {
+  struct {
+uint64_t a;
+uint64_t b;
+  } t;
+  __uint128_t data;
+} Value;
+Value value, next;
+
+void
+bug (Value *val, Value *nxt)
+{
+  for (;;) {
+nxt->t.a = val->t.a + 1;
+nxt->t.b = val->t.b + 2;
+if (__atomic_compare_exchange (&val->data, &val->data, &nxt->data,
+  0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE))
+  break;
+  }
+}
+
+int
+main (void)
+{
+  bug (&value, &next);
+  printf ("%lu %lu\n", value.t.a, value.t.b);
+  if (value.t.a != 1 || value.t.b != 2)
+abort ();
+  return 0;
+}

[gcc r14-10849] rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:ab74b2d86471cdb5b8a327e734630f1288125d9e

commit r14-10849-gab74b2d86471cdb5b8a327e734630f1288125d9e
Author: Peter Bergner 
Date:   Fri Aug 23 11:45:40 2024 -0500

rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

Our power8 swap optimization pass has some special handling for optimizing
swaps of TImode variables.  The test case reported in bugzilla uses a call
to  __atomic_compare_exchange, which introduces a variable of PTImode and
that does not get the same treatment as TImode leading to wrong code
generation.  The simple fix is to treat PTImode identically to TImode.

2024-08-23  Peter Bergner  

gcc/
PR target/116415
* config/rs6000/rs6000.h (TI_OR_PTI_MODE): New define.
* config/rs6000/rs6000-p8swap.cc (rs6000_analyze_swaps): Use it to
handle PTImode identically to TImode.

gcc/testsuite/
PR target/116415
* gcc.target/powerpc/pr116415.c: New test.

(cherry picked from commit 6e68c3df1540c5bafbb47343698bf4e270333fdb)

Diff:
---
 gcc/config/rs6000/rs6000-p8swap.cc  |  8 +++---
 gcc/config/rs6000/rs6000.h  |  2 ++
 gcc/testsuite/gcc.target/powerpc/pr116415.c | 42 +
 3 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-p8swap.cc 
b/gcc/config/rs6000/rs6000-p8swap.cc
index 639f477d7822..05fb76057f93 100644
--- a/gcc/config/rs6000/rs6000-p8swap.cc
+++ b/gcc/config/rs6000/rs6000-p8swap.cc
@@ -2469,10 +2469,10 @@ rs6000_analyze_swaps (function *fun)
mode = V4SImode;
}
 
- if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || mode == TImode)
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || TI_OR_PTI_MODE (mode))
{
  insn_entry[uid].is_relevant = 1;
- if (mode == TImode || mode == V1TImode
+ if (TI_OR_PTI_MODE (mode) || mode == V1TImode
  || FLOAT128_VECTOR_P (mode))
insn_entry[uid].is_128_int = 1;
  if (DF_REF_INSN_INFO (mention))
@@ -2497,10 +2497,10 @@ rs6000_analyze_swaps (function *fun)
  && ALTIVEC_OR_VSX_VECTOR_MODE (GET_MODE (SET_DEST (insn
mode = GET_MODE (SET_DEST (insn));
 
- if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || mode == TImode)
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || TI_OR_PTI_MODE (mode))
{
  insn_entry[uid].is_relevant = 1;
- if (mode == TImode || mode == V1TImode
+ if (TI_OR_PTI_MODE (mode) || mode == V1TImode
  || FLOAT128_VECTOR_P (mode))
insn_entry[uid].is_128_int = 1;
  if (DF_REF_INSN_INFO (mention))
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 197922fbb847..9b5cf321876b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1005,6 +1005,8 @@ enum data_align { align_abi, align_opt, align_both };
   (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE)
\
|| (MODE) == V2DImode || (MODE) == V1TImode)
 
+#define TI_OR_PTI_MODE(mode) ((mode) == TImode || (mode) == PTImode)
+
 /* Post-reload, we can't use any new AltiVec registers, as we already
emitted the vrsave mask.  */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr116415.c 
b/gcc/testsuite/gcc.target/powerpc/pr116415.c
new file mode 100644
index ..08cc282e2c27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr116415.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* PR 116415: Verify our Power8 swap optimization pass doesn't incorrectly swap
+   PTImode values.  They should be handled identically to TImode values.  */
+
+#include 
+#include 
+#include 
+
+typedef union {
+  struct {
+uint64_t a;
+uint64_t b;
+  } t;
+  __uint128_t data;
+} Value;
+Value value, next;
+
+void
+bug (Value *val, Value *nxt)
+{
+  for (;;) {
+nxt->t.a = val->t.a + 1;
+nxt->t.b = val->t.b + 2;
+if (__atomic_compare_exchange (&val->data, &val->data, &nxt->data,
+  0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE))
+  break;
+  }
+}
+
+int
+main (void)
+{
+  bug (&value, &next);
+  printf ("%lu %lu\n", value.t.a, value.t.b);
+  if (value.t.a != 1 || value.t.b != 2)
+abort ();
+  return 0;
+}

[gcc r15-4962] testsuite: Fix up gcc.target/powerpc/safe-indirect-jump-3.c test [PR117444]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:f185a89fc4b6e6f5ae5475cd7c723b3acf39976b

commit r15-4962-gf185a89fc4b6e6f5ae5475cd7c723b3acf39976b
Author: Peter Bergner 
Date:   Tue Nov 5 10:30:46 2024 -0600

testsuite: Fix up gcc.target/powerpc/safe-indirect-jump-3.c test [PR117444]

The test safe-indirect-jump-3.c FAILs on powerpc64le-linux with the change
in jump table generation behavior with commit r15-4756-g06bc3a734e8890,
since it is compiled without optimization and expects jump tables to be
generated.  Add an explicit -fjump-tables to dg-options to get the old
behavior back.

2024-11-05  Peter Bergner  

gcc/testsuite/
PR testsuite/117444
* gcc.target/powerpc/safe-indirect-jump-3.c: Add -fjump-tables to
dg-options.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c 
b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
index 87881fb18fc5..f5a7100a9ff8 100644
--- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mno-speculate-indirect-jumps" } */
+/* { dg-options "-fjump-tables -mno-speculate-indirect-jumps" } */
 /* { dg-warning "'-mno-speculate-indirect-jumps' is deprecated" "" { target 
*-*-* } 0 } */
 
 /* Test for deliberate misprediction of jump tables.  */

[gcc r14-10860] rs6000: ROP - Do not disable shrink-wrapping for leaf functions [PR114759]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:b4d4b86aebe1314a145732150d59a7b9ba066032

commit r14-10860-gb4d4b86aebe1314a145732150d59a7b9ba066032
Author: Peter Bergner 
Date:   Tue Jun 18 17:42:45 2024 -0500

rs6000: ROP - Do not disable shrink-wrapping for leaf functions [PR114759]

Only disable shrink-wrapping when using -mrop-protect when we know we
will be emitting the ROP-protect hash instructions (ie, non-leaf functions).

2024-06-17  Peter Bergner  

gcc/
PR target/114759
* config/rs6000/rs6000.cc (rs6000_override_options_after_change): 
Move
the disabling of shrink-wrapping from here
* config/rs6000/rs6000-logue.cc (rs6000_emit_prologue): ...to here.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-1.c: New test.

(cherry picked from commit 0451bc503da9c858e9f1ddfb8faec367c2e032c8)

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc |  5 +
 gcc/config/rs6000/rs6000.cc   |  4 
 gcc/testsuite/gcc.target/powerpc/pr114759-1.c | 16 
 3 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index edc0d6c8f520..fdb6414f486f 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -3012,6 +3012,11 @@ rs6000_emit_prologue (void)
&& (lookup_attribute ("no_split_stack",
  DECL_ATTRIBUTES (cfun->decl))
== NULL));
+  /* If we are inserting ROP-protect hash instructions, disable shrink-wrap
+ until the bug where the hashst insn is emitted in the wrong location
+ is fixed.  See PR101324 for details.  */
+  if (info->rop_hash_size)
+flag_shrink_wrap = 0;
 
   frame_pointer_needed_indeed
 = frame_pointer_needed && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 5fd31bf8242c..80f03809ff68 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3424,10 +3424,6 @@ rs6000_override_options_after_change (void)
 }
   else if (!OPTION_SET_P (flag_cunroll_grow_size))
 flag_cunroll_grow_size = flag_peel_loops || optimize >= 3;
-
-  /* If we are inserting ROP-protect instructions, disable shrink wrap.  */
-  if (rs6000_rop_protect)
-flag_shrink_wrap = 0;
 }
 
 #ifdef TARGET_USES_LINUX64_OPT
diff --git a/gcc/testsuite/gcc.target/powerpc/pr114759-1.c 
b/gcc/testsuite/gcc.target/powerpc/pr114759-1.c
new file mode 100644
index ..579e08e920f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr114759-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mrop-protect 
-fdump-rtl-pro_and_epilogue" } */
+/* { dg-require-effective-target rop_ok } Only enable on supported ABIs. */
+
+/* Verify we still attempt shrink-wrapping when using -mrop-protect
+   and there are no function calls.  */
+
+long
+foo (long arg)
+{
+  if (arg)
+asm ("" ::: "r20");
+  return 0;
+}
+
+/* { dg-final { scan-rtl-dump-times "Performing shrink-wrapping" 1 
"pro_and_epilogue" } } */

[gcc r15-7432] rs6000: Add cast to avoid pointer to integer comparison warning [PR117674]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:c9b8a8fc55168ba9ec5432fc7b86621074e1b887

commit r15-7432-gc9b8a8fc55168ba9ec5432fc7b86621074e1b887
Author: Peter Bergner 
Date:   Fri Feb 7 13:39:42 2025 -0600

rs6000: Add cast to avoid pointer to integer comparison warning [PR117674]

2025-02-07  Peter Bergner  

libgcc/
PR target/117674
* config/rs6000/linux-unwind.h (ppc_backchain_fallback): Add cast to
avoid comparison between pointer and integer warning.

Diff:
---
 libgcc/config/rs6000/linux-unwind.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libgcc/config/rs6000/linux-unwind.h 
b/libgcc/config/rs6000/linux-unwind.h
index 97a9fbd2d1ae..6fd3c908ae84 100644
--- a/libgcc/config/rs6000/linux-unwind.h
+++ b/libgcc/config/rs6000/linux-unwind.h
@@ -395,7 +395,7 @@ ppc_backchain_fallback (struct _Unwind_Context *context, 
void *a)
   current = context->cfa;
 
   /* If the trace CFA is not the context CFA the backtrace is done.  */
-  if (arg == NULL || arg->cfa != current)
+  if (arg == NULL || arg->cfa != (_Unwind_Word) current)
return;
 
   /* Start with next address.  */

[gcc/ibm/heads/mmaplus] (1192 commits) Update ChangeLog.*

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/mmaplus' was updated to point to:

 b0534a239f4e... Update ChangeLog.*

It previously pointed to:

 3b2b644646c7... Update ChangeLog.*

Diff:

!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
---

  3b2b644... Update ChangeLog.*
  6c83dae... Set default name to power8 if no --with-cpu.
  752de69... Update ChangeLog.*
  90229e4... Revert changes
  b8e0f4b... RFC2677-Add xvrlw support.
  f482ec2... RFC2686-Add paddis support.
  727669f... RFC2655-Add saturating subtract built-ins.
  1a52c13... RFC2656-Support load/store vector with right length.
  8ab7dac... RFC2653-PowerPC: Add support for 1,024 bit DMR registers.
  0c9e8a5... RFC2653-Add dense math test for new instruction names.
  8d4c490... RFC2653-PowerPC: Switch to dense math names for all MMA ope
  178b44c... RFC2653-Add support for dense math registers.
  9b13df3... RFC2653-Add wD constraint.
  10ef210... Use vector pair load/store for memcpy with -mcpu=future
  6bde233... Add -mcpu=future tuning support.
  66d13f6... Add support for -mcpu=future
  a6ea141... Update tests to work with architecture flags changes.
  16e412e... Change TARGET_MODULO to TARGET_POWER9
  d07b089... Change TARGET_POPCNTD to TARGET_POWER7
  9158ccc... Change TARGET_CMPB to TARGET_POWER6
  6559400... Change TARGET_FPRND to TARGET_POWER5X
  1eabe29... Change TARGET_POPCNTB to TARGET_POWER5
  5f1bebd... Do not allow -mvsx to boost processor to power7.
  e2771ea... Use architecture flags for defining _ARCH_PWR macros.
  ae489dc... Add rs6000 architecture masks.
  79518d7... Add ChangeLog.dmf and update REVISION.


Summary of changes (added commits):
---

  b0534a2... Update ChangeLog.*
  57af3f6... Set default name to power8 if no --with-cpu.
  93f4f03... Update ChangeLog.*
  789030a... Revert changes
  12dc932... RFC2677-Add xvrlw support.
  aa6348c... RFC2686-Add paddis support.
  92ab335... RFC2655-Add saturating subtract built-ins.
  6f039c1... RFC2656-Support load/store vector with right length.
  cfffa0f... RFC2653-PowerPC: Add support for 1,024 bit DMR registers.
  8ae1c5a... RFC2653-Add dense math test for new instruction names.
  e9de88c... RFC2653-PowerPC: Switch to dense math names for all MMA ope
  e3507bc... RFC2653-Add support for dense math registers.
  af1a752... RFC2653-Add wD constraint.
  898e330... Use vector pair load/store for memcpy with -mcpu=future
  7b173d3... Add -mcpu=future tuning support.
  99ed71c... Add support for -mcpu=future
  4a8a2d0... Update tests to work with architecture flags changes.
  e493980... Change TARGET_MODULO to TARGET_POWER9
  f986a60... Change TARGET_POPCNTD to TARGET_POWER7
  9a17bb6... Change TARGET_CMPB to TARGET_POWER6
  25d8c27... Change TARGET_FPRND to TARGET_POWER5X
  c535ab0... Change TARGET_POPCNTB to TARGET_POWER5
  8b38dc4... Do not allow -mvsx to boost processor to power7.
  9597f84... Use architecture flags for defining _ARCH_PWR macros.
  f596a73... Add rs6000 architecture masks.
  899fe7e... Add ChangeLog.dmf and update REVISION.
  5e718a7... PR117350: Keep assembler name for abstract decls for autofd (*)
  74cee43... Daily bump. (*)
  44e71c8... libstdc++: Add -fno-assume-sane-operators-new-delete to tes (*)
  94f98f6... Fortran: fix minor front-end memleaks (*)
  4a23528... aarch64: Update error message check for __builtin_launder c (*)
  1a0d480... aarch64: Fix fp8_scalar_1.c's stacktest1 (*)
  746629e... selftest: invoke "diff" when ASSERT_STREQ fails (*)
  b4d4e22... testsuite: rename plugins from .c to .cc (*)
  e2db825... csky: use quotes when referring to cpus and archs [PR90160] (*)
  3e2a1b2... [PATCH] testsuite:RISC-V:Modify the char string. (*)
  eff7e72... Fortran: passing inquiry ref of complex array to assumed ra (*)
  5134bad... c: avoid double-negative in warning message [PR94370] (*)
  67458ea... loop-prefetch: fix wording of warning [PR80760] (*)
  08bb92d... plugin: add missing colon in error message [PR93746] (*)
  098a41c... gdbhooks: Handle references to vec* in VecPrinter (*)
  a22dfe2... RISC-V: Refactor the testcases for RVV gather/scatter (*)
  1802669... RISC-V: Fix incorrect optimization options passing to gathe (*)
  1729147... improve std::deque::_M_reallocate_map (*)
  ae7c047... ada: Do not use ATTR_ADDR_EXPR for 'Unrestricted_Access (*)
  84d8a38... ada: Add minimal support for address clause/aspect on contr (*)
  936f9f1... ada: Clean up previous change (*)
  e14ec56... ada: Minor adjustments to error message for RM B.1(24) (*)
  38b977c... ada: Refactor code of Check_Ambiguous_Call and Valid_Conver (*)
  fed7c5c... ada: Relocate implementation of Write_Error_Summary (*)
  9b33f74... ada: Relocate implementation of Set_Msg_Insertion_Column (*)
  9fb54f4... ada: Remove Warn_Runtime_Raise attribute from Error_Msg_Obj (*)
  8d0bb80... ada: Refactor checking redundant messages (*)
  ba0c6d0... ada: Remove Current_Node from Errout (*)
  2364e96... ad

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2653-Add support for dense math registers.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:e3507bcba8da515736267a70c3dfb5fac05463c4

commit e3507bcba8da515736267a70c3dfb5fac05463c4
Author: Michael Meissner 
Date:   Tue Oct 22 16:56:10 2024 -0400

RFC2653-Add support for dense math registers.

The MMA subsystem added the notion of accumulator registers as an optional
feature of ISA 3.1 (power10).  In ISA 3.1, these accumulators overlapped 
with
the VSX registers 0..31, but logically the accumulator registers were 
separate
from the FPR registers.  In ISA 3.1, it was anticipated that in future 
systems,
the accumulator registers may no overlap with the FPR registers.  This patch
adds the support for dense math registers as separate registers.

This particular patch does not change the MMA support to use the 
accumulators
within the dense math registers.  This patch just adds the basic support for
having separate DMRs.  The next patch will switch the MMA support to use the
accumulators if -mcpu=future is used.

For testing purposes, I added an undocumented option '-mdense-math' to 
enable
or disable the dense math support.

This patch adds a new constraint (wD).  If MMA is selected but dense math is
not selected (i.e. -mcpu=power10), the wD constraint will allow access to
accumulators that overlap with VSX registers 0..31.  If both MMA and dense 
math
are selected (i.e. -mcpu=future), the wD constraint will only allow dense 
math
registers.

This patch modifies the existing %A output modifier.  If MMA is selected but
dense math is not selected, then %A output modifier converts the VSX 
register
number to the accumulator number, by dividing it by 4.  If both MMA and 
dense
math are selected, then %A will map the separate DMR registers into 0..7.

The intention is that user code using extended asm can be modified to run on
both MMA without dense math and MMA with dense math:

1)  If possible, don't use extended asm, but instead use the MMA 
built-in
functions;

2)  If you do need to write extended asm, change the d constraints
targetting accumulators should now use wD;

3)  Only use the built-in zero, assemble and disassemble functions 
create
move data between vector quad types and dense math accumulators.
I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the
extended asm code.  The reason is these instructions assume there 
is a
1-to-1 correspondence between 4 adjacent FPR registers and an
accumulator that overlaps with those instructions.  With 
accumulators
now being separate registers, there no longer is a 1-to-1
correspondence.

It is possible that the mangling for DMRs and the GDB register numbers may
produce other changes in the future.

gcc/

2024-10-22   Michael Meissner  

* config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec.
(movxo): Add comments about dense math registers.
(movxo_nodm): Rename from movxo and restrict the usage to machines
without dense math registers.
(movxo_dm): New insn for movxo support for machines with dense math
registers.
(mma_): Restrict usage to machines without dense math 
registers.
(mma_xxsetaccz): Add a define_expand wrapper, and add support for 
dense
math registers.
(mma_dmsetaccz): New insn.
* config/rs6000/predicates.md (dmr_operand): New predicate.
(accumulator_operand): Add support for dense math registers.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): 
Do
not issue a de-prime instruction when disassembling a vector quad 
on a
system with dense math registers.
* config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): 
Define
__DENSE_MATH__ if we have dense math registers.
* config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE.
(enum rs6000_reload_reg_type): Add RELOAD_REG_DMR.
(LAST_RELOAD_REG_CLASS): Add support for DMR registers and the wD
constraint.
(reload_reg_map): Likewise.
(rs6000_reg_names): Likewise.
(alt_reg_names): Likewise.
(rs6000_hard_regno_nregs_internal): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_secondary_reload_memory): Add support for DMR registers.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(print_operand): Make %A handle both FP

[gcc(refs/vendors/ibm/heads/mmaplus)] Revert changes

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:789030a88dc752b80277f1868d94cb8e4e82d481

commit 789030a88dc752b80277f1868d94cb8e4e82d481
Author: Michael Meissner 
Date:   Tue Oct 22 17:51:04 2024 -0400

Revert changes

Diff:
---
 gcc/config/rs6000/altivec.md   | 14 
 gcc/config/rs6000/constraints.md   | 10 ---
 gcc/config/rs6000/predicates.md| 52 +---
 gcc/config/rs6000/rs6000.cc| 25 --
 gcc/config/rs6000/rs6000.h |  7 --
 gcc/config/rs6000/rs6000.md| 96 +++---
 gcc/testsuite/gcc.target/powerpc/prefixed-addis.c  | 24 --
 .../gcc.target/powerpc/vector-rotate-left.c| 34 
 8 files changed, 14 insertions(+), 248 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index c76b1eeefe35..b6a778ef6179 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,20 +1982,6 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; -mcpu=future adds a vector rotate left word variant.  There is no vector
-;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
-;; altivec_vrl and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*xvrlw"
-  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
-   (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
-(match_operand:V4SI 2 "register_operand" "v,wa")))]
-  "TARGET_XVRLW"
-  "@
-   vrlw %0,%1,%2
-   xvrlw %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 (define_insn "altivec_vrl"
   [(set (match_operand:VI2 0 "register_operand" "=v")
 (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 4d8d21fd6bbb..277a30a82458 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,16 +222,6 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
-(define_constraint "eU"
-  "@internal integer constant that can be loaded with paddis"
-  (and (match_code "const_int")
-   (match_operand 0 "paddis_operand")))
-
-(define_constraint "eV"
-  "@internal integer constant that can be loaded with paddis + paddi"
-  (and (match_code "const_int")
-   (match_operand 0 "paddis_paddi_operand")))
-
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index f8e7df5e7f5b..2797c3cf619b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,53 +369,6 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
-;; Return 1 if op is a 64-bit constant that uses the paddis instruction
-(define_predicate "paddis_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-return false;
-
-  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
-  if ((value & HOST_WIDE_INT_C(0x)) != 0)
-return false;
-
-  return true;
-})
-
-;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
-;; addi/addis/paddi instruction combination.
-(define_predicate "paddis_paddi_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-return false;
-
-  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
-  if ((value & HOST_WIDE_INT_C(0x)) == 0)
-return false;
-
-  return true;
-})
-
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1160,10 +1113,7 @@
   (if_then_else (match_code "const_int")
 (match_test "satisfies_constraint_I (op)
 || satisfies_constraint_L (op)
-|| satisfies_constraint_eI (op)
-|| satisfies_constraint_eU (op)
-|| satisfies_constraint_eV (op)")
-
+|| satisfies_constraint_eI (op)")
 (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/conf

[gcc(refs/vendors/ibm/heads/mmaplus)] Do not allow -mvsx to boost processor to power7.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:8b38dc4e1d3d1794cdc9436f5ad392c8d5442912

commit 8b38dc4e1d3d1794cdc9436f5ad392c8d5442912
Author: Michael Meissner 
Date:   Tue Oct 22 16:42:11 2024 -0400

Do not allow -mvsx to boost processor to power7.

This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7.  The user must now use -mcpu=power7 or 
higher.
This means if the user does -mvsx and the default processor does not have 
VSX
support, it will be an error.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 1 file changed, 79 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4f1f30408714..30cdf9480f1c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3694,7 +3695,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3963,59 +3963,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target a

[gcc(refs/vendors/ibm/heads/mmaplus)] Change TARGET_POPCNTD to TARGET_POWER7

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:f986a6097fcffd83d871946d8c479d0ee398baea

commit f986a6097fcffd83d871946d8c479d0ee398baea
Author: Michael Meissner 
Date:   Tue Oct 22 16:50:48 2024 -0400

Change TARGET_POPCNTD to TARGET_POWER7

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTD to TARGET_POWER7.  The POPCNTD instruction was added in 
power7
(ISA 2.06).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

* config/rs6000/dfp.md (floatdidd2): Change TARGET_POPCNTD to
TARGET_POWER7.
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* config/rs6000/rs6000-string.cc (expand_block_compare_gpr): 
Likewise.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_popcount): Likewise.
* config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz2): Likewise.
(popcntd2): Likewise.
(lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_"): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-string.cc  |  4 ++--
 gcc/config/rs6000/rs6000.cc |  6 +++---
 gcc/config/rs6000/rs6000.h  | 16 
 gcc/config/rs6000/rs6000.md | 24 
 6 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd3..b8189390d410 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..dae43b672ea7 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P6_64:
   return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POPCNTD;
+  return TARGET_POWER7;
 case ENB_P7_64:
-  return TARGET_POPCNTD && TARGET_POWERPC64;
+  return TARGET_POWER7 && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index de618da9b5dc..de66d3a5f9a9 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes, 
unsigned int base_align,
 bool
 expand_block_compare (rtx operands[])
 {
-  /* TARGET_POPCNTD is already guarded at expand cmpmemsi.  */
-  gcc_assert (TARGET_POPCNTD);
+  /* TARGET_POWER7 is already guarded at expand cmpmemsi.  */
+  gcc_assert (TARGET_POWER7);
 
   /* For P8, this case is complicated to handle because the subtract
  with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d27c089c9e34..a04da188df93 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1998,7 +1998,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
  if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
 
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
 
  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -22389,7 +22389,7 @@ rs6000_rtx

[gcc(refs/vendors/ibm/heads/mmaplus)] Use vector pair load/store for memcpy with -mcpu=future

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:898e330bd7d50a0cb630d3b206561e4d54877a2b

commit 898e330bd7d50a0cb630d3b206561e4d54877a2b
Author: Michael Meissner 
Date:   Tue Oct 22 16:54:35 2024 -0400

Use vector pair load/store for memcpy with -mcpu=future

In the development for the power10 processor, GCC did not enable using the 
load
vector pair and store vector pair instructions when optimizing things like
memory copy.  This patch enables using those instructions if -mcpu=future is
used.

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable 
using
load vector pair and store vector pair instructions for memory copy
operations.
(POWERPC_MASKS): Make the bit for enabling using load vector pair 
and
store vector pair operations set and reset when the PowerPC 
processor is
changed.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 4c5865218815..2ce8d13aa169 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -80,7 +80,8 @@
 
 #define POWER11_MASKS_SERVER   ISA_3_1_MASKS_SERVER
 
-#define FUTURE_MASKS_SERVERPOWER11_MASKS_SERVER
+#define FUTURE_MASKS_SERVER(POWER11_MASKS_SERVER   \
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -110,6 +111,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2656-Support load/store vector with right length.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:6f039c1f5c4b0b7bfc765c355a9a1b9152500a56

commit 6f039c1f5c4b0b7bfc765c355a9a1b9152500a56
Author: Michael Meissner 
Date:   Tue Oct 22 16:59:43 2024 -0400

RFC2656-Support load/store vector with right length.

This patch adds support for new instructions that may be added to the 
PowerPC
architecture in the future to enhance the load and store vector with length
instructions.

The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to 
use
since the count for the number of bytes must be in the top 8 bits of the GPR
register, instead of the bottom 8 bits.  This meant that code generating 
these
instructions typically had to do a shift left by 56 bits to get the count 
into
the right position.  In a future version of the PowerPC architecture, new
variants of these instructions might be added that expect the count to be in
the bottom 8 bits of the GPR register.  These patches add this support to 
GCC
if the user uses the -mcpu=future option.

I discovered that the code in rs6000-string.cc to generate ISA 3.1 
lxvl/stxvl
future lxvll/stxvll instructions would generate these instructions on 
32-bit.
However the patterns for these instructions is only done on 64-bit systems. 
 So
I added a check for 64-bit support before generating the instructions.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-10-22   Michael Meissner  

gcc/

* config/rs6000/rs6000-string.cc (expand_block_move): Do not 
generate
lxvl and stxvl on 32-bit.
* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl 
with
the shift count automaticaly used in the insn.
(lxvrl): New insn for -mcpu=future.
(lxvrll): Likewise.
(stxvl): If -mcpu=future, generate the stxvl with the shift count
automaticaly used in the insn.
(stxvrl): New insn for -mcpu=future.
(stxvrll): Likewise.

gcc/testsuite/

* gcc.target/powerpc/lxvrl.c: New test.
* lib/target-supports.exp 
(check_effective_target_powerpc_future_ok):
New effective target.

Diff:
---
 gcc/config/rs6000/rs6000-string.cc   |   1 +
 gcc/config/rs6000/vsx.md | 122 +--
 gcc/testsuite/gcc.target/powerpc/lxvrl.c |  32 
 gcc/testsuite/lib/target-supports.exp|  12 +++
 4 files changed, 146 insertions(+), 21 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index de66d3a5f9a9..82ec028ebfc3 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2786,6 +2786,7 @@ expand_block_move (rtx operands[], bool might_overlap)
 
   if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
  && TARGET_BLOCK_OPS_VECTOR_PAIR
+ && TARGET_POWERPC64
  && bytes >= 32
  && (align >= 256 || !STRICT_ALIGNMENT))
{
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f4f7113f5fe8..43c10a1b0970 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5710,20 +5710,32 @@
   DONE;
 })
 
-;; Load VSX Vector with Length
+;; Load VSX Vector with Length.  If we have lxvrl, we don't have to do an
+;; explicit shift left into a pseudo.
 (define_expand "lxvl"
-  [(set (match_dup 3)
-(ashift:DI (match_operand:DI 2 "register_operand")
-   (const_int 56)))
-   (set (match_operand:V16QI 0 "vsx_register_operand")
-   (unspec:V16QI
-[(match_operand:DI 1 "gpc_reg_operand")
-  (mem:V16QI (match_dup 1))
- (match_dup 3)]
-UNSPEC_LXVL))]
+  [(use (match_operand:V16QI 0 "vsx_register_operand"))
+   (use (match_operand:DI 1 "gpc_reg_operand"))
+   (use (match_operand:DI 2 "gpc_reg_operand"))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  operands[3] = gen_reg_rtx (DImode);
+  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
+  rtx len;
+
+  if (TARGET_FUTURE)
+len = shift_len;
+  else
+{
+  len = gen_reg_rtx (DImode);
+  emit_insn (gen_rtx_SET (len, shift_len));
+}
+
+  rtx dest = operands[0];
+  rtx addr = operands[1];
+  rtx mem = gen_rtx_MEM (V16QImode, addr);
+  rtvec rv = gen_rtvec (3, addr, mem, len);
+  rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
+  emit_insn (gen_rtx_SET (dest, lxvl));
+  DONE;
 })
 
 (define_insn "*lxvl"
@@ -5747,6 +5759,34 @@
   "lxvll %x0,%1,%2"
   [(set_attr "type" "vecload")])
 
+;; For lxvrl and lxvrll, use the combiner to eliminate the shift.  The
+;; define_expand for lxvl will already incorporate the shift in generating the
+;; insn.  The lxvll buitl-in function required the user to have already done
+;; the shift.  Defining lxvrll this way, will optimize cases where the user has
+;; done the shift immediately before

[gcc(refs/vendors/ibm/heads/mmaplus)] Update tests to work with architecture flags changes.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:4a8a2d079162111f3cfbf7c5147e5554f97a5113

commit 4a8a2d079162111f3cfbf7c5147e5554f97a5113
Author: Michael Meissner 
Date:   Tue Oct 22 16:52:24 2024 -0400

Update tests to work with architecture flags changes.

Two tests used -mvsx to raise the processor level to at least power7.  These
tests were rewritten to add cpu=power7 support.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 38 +++--
 gcc/testsuite/gcc.target/powerpc/pr115688.c |  3 +-
 2 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index feef76db4618..5e2ecf34f249 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_fprs } */
 /* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include 
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;

[gcc(refs/vendors/ibm/heads/mmaplus)] Use architecture flags for defining _ARCH_PWR macros.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:9597f840febcc4820270023c5d843e5a0a051587

commit 9597f840febcc4820270023c5d843e5a0a051587
Author: Michael Meissner 
Date:   Tue Oct 22 16:41:09 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11, which are no 
longer
in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER4): New macro.
(TARGET_POWER5): Likewise.
(TARGET_POWER5X): Likewise.
(TARGET_POWER6): Likewise.
(TARGET_POWER7): Likewise.
(TARGET_POWER8): Likewise.
(TARGET_POWER9): Likewise.
(TARGET_POWER10): Likewise.
(TARGET_POWER11): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 27 +++
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h| 20 
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 52 insertions(+), 38 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 7e3a7c423dc4..2053cdc3a99d 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,23 +420,25 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefin

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2653-Add wD constraint.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:af1a75250d8b9e9c2170c579e6127368e22d2282

commit af1a75250d8b9e9c2170c579e6127368e22d2282
Author: Michael Meissner 
Date:   Tue Oct 22 16:55:18 2024 -0400

RFC2653-Add wD constraint.

This patch adds a new constraint ('wD') that matches the accumulator 
registers
that overlap with VSX registers 0..31 on power10.  Future patches will add 
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.

2024-10-22   Michael Meissner  

* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/mma.md (mma_): Prepare for alternate 
accumulator
registers.  Use wD constraint instead of 'd' constraint.  Use
accumulator_operand instead of fpr_reg_operand.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
   "TARGET_MMA"
   " %A0"
@@ -523,7 +523,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
@@ -532,8 +532,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
@@ -542,7 +542,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
@@ -551,8 +551,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
@@ -561,7 +561,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -574,8 +574,8 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
(match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -588,7 +588,7 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -601,8 +601,8 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
   

[gcc(refs/vendors/ibm/heads/mmaplus)] Change TARGET_MODULO to TARGET_POWER9

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:e493980945dc9b1e6b52fb6a02dfd05d97d9c4fc

commit e493980945dc9b1e6b52fb6a02dfd05d97d9c4fc
Author: Michael Meissner 
Date:   Tue Oct 22 16:51:43 2024 -0400

Change TARGET_MODULO to TARGET_POWER9

As part of the architecture flags patches, this patch changes the use of
TARGET_MODULO to TARGET_POWER9.  The modulo instructions were added in 
power9 (ISA
3.0).  Note, I did not change the uses of TARGET_MODULO where it was 
explicitly
generating different code if the machine had a modulo instruction.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER9 instead of TARGET_MODULO.
* config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
 gcc/config/rs6000/rs6000.h  | 6 +++---
 gcc/config/rs6000/rs6000.md | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index dae43b672ea7..b6093b3cb64c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index df6b7adbb6c4..9ce1d028521e 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -461,9 +461,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID   (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD  TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD  TARGET_POWER9
 
 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.  
*/
 #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9640e4a5d938..cd71d6afa005 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
  (const_int 1)
 
  (and (eq_attr "isa" "p9v")

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:e9de88cf40fd3e61cb824384e1b1780d39f89ebe

commit e9de88cf40fd3e61cb824384e1b1780d39f89ebe
Author: Michael Meissner 
Date:   Tue Oct 22 16:57:05 2024 -0400

RFC2653-PowerPC: Switch to dense math names for all MMA operations.

This patch changes the assembler instruction names for MMA instructions from
the original name used in power10 to the new name when used with the dense 
math
system.  I.e. xvf64gerpp becomes dmxvf64gerpp.  The assembler will emit the
same bits for either spelling.

For the non-prefixed MMA instructions, we add a 'dm' prefix in front of the
instruction.  However, the prefixed instructions have a 'pm' prefix, and we 
add
the 'dm' prefix afterwards.  To prevent having two sets of parallel int
attributes, we remove the "pm" prefix from the instruction string in the
attributes, and add it later, both in the insn name and in the output 
template.

2024-10-22   Michael Meissner  

gcc/

* config/rs6000/mma.md (vvi4i4i8): Change the instruction to not 
have a
"pm" prefix.
(avvi4i4i8): Likewise.
(vvi4i4i2): Likewise.
(avvi4i4i2): Likewise.
(vvi4i4): Likewise.
(avvi4i4): Likewise.
(pvi4i2): Likewise.
(apvi4i2): Likewise.
(vvi4i4i4): Likewise.
(avvi4i4i4): Likewise.
(mma_): Add support for running on DMF systems, generating the 
dense
math instruction and using the dense math accumulators.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_pm): Add support for running on DMF systems, 
generating
the dense math instruction and using the dense math accumulators.
Rename the insn with a 'pm' prefix and add either 'pm' or 'pmdm'
prefixes based on whether we have the original MMA specification or 
if
we have dense math support.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.

Diff:
---
 gcc/config/rs6000/mma.md | 157 +++
 1 file changed, 104 insertions(+), 53 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index ae6e7e9695be..2e04eb653fa6 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -225,44 +225,47 @@
 (UNSPEC_MMA_XVF64GERNP "xvf64gernp")
 (UNSPEC_MMA_XVF64GERNN "xvf64gernn")])
 
-(define_int_attr vvi4i4i8  [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")])
+;; The "pm" prefix is not in these expansions, so that we can generate
+;; pmdmxvi4ger8 on systems with dense math registers and xvi4ger8 on systems
+;; without dense math registers.
+(define_int_attr vvi4i4i8  [(UNSPEC_MMA_PMXVI4GER8 "xvi4ger8")])
 
-(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP   
"pmxvi4ger8pp")])
+(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP   "xvi4ger8pp")])
 
-(define_int_attr vvi4i4i2  [(UNSPEC_MMA_PMXVI16GER2"pmxvi16ger2")
-(UNSPEC_MMA_PMXVI16GER2S   "pmxvi16ger2s")
-(UNSPEC_MMA_PMXVF16GER2"pmxvf16ger2")
-(UNSPEC_MMA_PMXVBF16GER2   
"pmxvbf16ger2")])
+(define_int_attr vvi4i4i2  [(UNSPEC_MMA_PMXVI16GER2"xvi16ger2")
+(UNSPEC_MMA_PMXVI16GER2S   "xvi16ger2s")
+(UNSPEC_MMA_PMXVF16GER2"xvf16ger2")
+(UNSPEC_MMA_PMXVBF16GER2   "xvbf16ger2")])
 
-(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP  "pmxvi16ger2pp")
-(UNSPEC_MMA_PMXVI16GER2SPP 
"pmxvi16ger2spp")
-(UNSPEC_MMA_PMXVF16GER2PP  "pmxvf16ger2pp")
-(UNSPEC_MMA_PMXVF16GER2PN  "pmxvf16ger2pn")
-(UNSPEC_MMA_PMXVF16GER2NP  "pmxvf16ger2np")
-(UNSPEC_MMA_PMXVF16GER2NN  "pmxvf16ger2nn")
-(UNSPEC_MMA_PMXVBF16GER2PP 
"pmxvbf16ger2pp")
-(UNSPEC_MMA_PMXVBF16GER2PN 
"pmxvbf16ger2pn")
-(UNSPEC_MMA_PMXVBF16GER2NP 
"pmxvbf16ger2np")
-(UNSPEC_MMA_PMXVBF16GER2NN 
"pmxvbf16ger2nn")])
+(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP  "xvi16ger2pp")
+(UNSPEC_MMA_PMXVI16GER2SPP "xvi16ger2spp")
+(UNSPEC_MMA_PMXVF16GER2PP  "xvf16ger2pp")
+(UNSPEC_MMA_PMXVF16GER2PN  "xvf

[gcc(refs/vendors/ibm/heads/mmaplus)] Add rs6000 architecture masks.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:f596a7323701b001d9bbf1a8f3cf06b6d75669e0

commit f596a7323701b001d9bbf1a8f3cf06b6d75669e0
Author: Michael Meissner 
Date:   Tue Oct 22 16:40:13 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

This patch also changes the target_clones support to use an architecture 
mask
instead of isa bits.

This patch also switches the handling of .machine to use architecture masks 
if
they exist (power4 through power11).  All of the other PowerPCs will 
continue to
use the existing code for setting the .machine option.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument, 
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks 
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead 
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  48 +
 gcc/config/rs6000/rs6000.cc   | 215 +++---
 gcc/config/rs6000/rs6000.h|  24 +
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 259 insertions(+), 36 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..e5b6e9581331
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,48 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the optio

[gcc(refs/vendors/ibm/heads/mmaplus)] Add -mcpu=future tuning support.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:7b173d32ded5d88d6f4973b167c6304b60453492

commit 7b173d32ded5d88d6f4973b167c6304b60453492
Author: Michael Meissner 
Date:   Tue Oct 22 16:53:40 2024 -0400

Add -mcpu=future tuning support.

This patch makes -mtune=future use the same tuning decision as 
-mtune=power11.

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/power10.md (all reservations): Add future as an
alterntive to power10 and power11.

Diff:
---
 gcc/config/rs6000/power10.md | 144 +--
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 2310c4603457..e42b057dc45b 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@
-;; Scheduling description for the IBM Power10 and Power11 processors.
+;; Scheduling description for the IBM Power10, Power11, and Future processors.
 ;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
   (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +178,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle latency for updat

[gcc(refs/vendors/ibm/heads/mmaplus)] Add support for -mcpu=future

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:99ed71cbb0b2d61153e2bac086e226d85db219fa

commit 99ed71cbb0b2d61153e2bac086e226d85db219fa
Author: Michael Meissner 
Date:   Tue Oct 22 16:53:04 2024 -0400

Add support for -mcpu=future

This patch adds the support that can be used in developing GCC support for
future PowerPC processors.

2024-10-22  Michael Meissner  

* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for 
-mcpu=future.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-arch.def: Add future cpu.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
-mcpu=future, define _ARCH_FUTURE.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(future cpu): Define.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power10_cost): Update comment.
(get_arch_flags): Add support for future processor.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
(TARGET_POWER11): New macro.
* config/rs6000/rs6000.md (cpu attribute): Likewise.

Diff:
---
 gcc/config.gcc  |  4 ++--
 gcc/config/rs6000/aix71.h   |  1 +
 gcc/config/rs6000/aix72.h   |  1 +
 gcc/config/rs6000/aix73.h   |  1 +
 gcc/config/rs6000/driver-rs6000.cc  |  2 ++
 gcc/config/rs6000/rs6000-arch.def   |  1 +
 gcc/config/rs6000/rs6000-c.cc   |  2 ++
 gcc/config/rs6000/rs6000-cpus.def   |  3 +++
 gcc/config/rs6000/rs6000-opts.h |  1 +
 gcc/config/rs6000/rs6000-tables.opt | 11 +++
 gcc/config/rs6000/rs6000.cc | 34 ++
 gcc/config/rs6000/rs6000.h  |  2 ++
 gcc/config/rs6000/rs6000.md |  2 +-
 13 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 12018d2193ca..53e4890b7e15 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -536,7 +536,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h 
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5615,7 +5615,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
-   "" | common | native \
+   "" | common | native | future \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 4350dcd89524..505986b33d63 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b48..242ca94bd065 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662d..2bd6b4bb3c4f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -

[gcc(refs/vendors/ibm/heads/mmaplus)] Change TARGET_POPCNTB to TARGET_POWER5

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:c535ab073031bb3c9e512c635bcbc0c099e59485

commit c535ab073031bb3c9e512c635bcbc0c099e59485
Author: Michael Meissner 
Date:   Tue Oct 22 16:48:20 2024 -0400

Change TARGET_POPCNTB to TARGET_POWER5

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTB to TARGET_POWER5.  The POPCNTB instruction was added in ISA 
2.02
(power5).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER5 instead of TARGET_POPCNTB.
* config/rs6000/rs6000.h (TARGET_EXTRA_BUILTINS): Use TARGET_POWER5
instead of TARGET_POPCNTB.  Eliminate TARGET_CMPB and TARGET_POPCNTD
tests since TARGET_POWER5 will always be true for those tests.
(TARGET_FRE): Use TARGET_POWER5 instead of TARGET_POPCNTB.
(TARGET_FRSQRTES): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount): Use TARGET_POWER5 instead of TARGET_POPCNTB.  Drop
test for TARGET_POPCNTD (i.e power7), since TARGET_POPCNTB will 
always
be set if TARGET_POPCNTD is set.
(popcntb2): Use TARGET_POWER5 instead of TARGET_POPCNTB.
(parity2): Likewise.
(parity2_cmpb): Remove TARGET_POPCNTB test, since it will 
always
be true when TARGET_CMPB (i.e. power6) is set.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000.h  |  8 +++-
 gcc/config/rs6000/rs6000.md | 10 +-
 3 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index a180677eba2b..95a562ee2638 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -545,9 +545,7 @@ extern int rs6000_vector_align[];
 
 #define TARGET_EXTRA_BUILTINS  (TARGET_POWERPC64\
 || TARGET_PPC_GPOPT /* 970/power4 */\
-|| TARGET_POPCNTB   /* ISA 2.02 */  \
-|| TARGET_CMPB  /* ISA 2.05 */  \
-|| TARGET_POPCNTD   /* ISA 2.06 */  \
+|| TARGET_POWER5/* ISA 2.02 & above */ \
 || TARGET_ALTIVEC   \
 || TARGET_VSX   \
 || TARGET_HARD_FLOAT)
@@ -561,9 +559,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRE (TARGET_HARD_FLOAT \
-&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
+&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
 
-#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \
+#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \
 && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 95be36d5a726..ab62db7a2717 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -379,7 +379,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p5")
- (match_test "TARGET_POPCNTB"))
+ (match_test "TARGET_POWER5"))
  (const_int 1)
 
  (and (eq_attr "isa" "p6")
@@ -2510,7 +2510,7 @@
 (define_expand "popcount2"
   [(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
-  "TARGET_POPCNTB || TARGET_POPCNTD"
+  "TARGET_POWER5"
 {
   rs6000_emit_popcount (operands[0], operands[1]);
   DONE;
@@ -2520,7 +2520,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNS

[gcc(refs/vendors/ibm/heads/mmaplus)] Change TARGET_CMPB to TARGET_POWER6

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:9a17bb6964e3b15bc596d8f06d38e125fbb8948d

commit 9a17bb6964e3b15bc596d8f06d38e125fbb8948d
Author: Michael Meissner 
Date:   Tue Oct 22 16:49:52 2024 -0400

Change TARGET_CMPB to TARGET_POWER6

As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER6.  The CMPB instruction was added in power6 
(ISA
2.05).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.h (TARGET_FCFID): Merge tests for popcntb, 
cmpb,
and popcntd into a single test for TARGET_POWER5.
(TARGET_LFIWAX): Use TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Likewise.
(cmpb): Likewise.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  6 ++
 gcc/config/rs6000/rs6000.md | 16 
 3 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 95a562ee2638..69a1355407f3 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -448,13 +448,11 @@ extern int rs6000_vector_align[];
Enable 32-bit fcfid's on any of the switches for newer ISA machines.  */
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
-|| TARGET_POPCNTB  /* ISA 2.02 */  \
-|| TARGET_CMPB /* ISA 2.05 */  \
-|| TARGET_POPCNTD) /* ISA 2.06 */
+|| TARGET_POWER5)  /* ISA 2.02 and above */ \
 
 #define TARGET_FCTIDZ  TARGET_FCFID
 #define TARGET_STFIWX  TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX  TARGET_CMPB
+#define TARGET_LFIWAX  TARGET_POWER6
 #define TARGET_LFIWZX  TARGET_POPCNTD
 #define TARGET_FCFIDS  TARGET_POPCNTD
 #define TARGET_FCFIDU  TARGET_POPCNTD
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 97535f912b83..0a57e50682b9 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -383,7 +383,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p6")
- (match_test "TARGET_CMPB"))
+ (match_test "TARGET_POWER6"))
  (const_int 1)
 
  (and (eq_attr "isa" "p7")
@@ -2544,7 +2544,7 @@
 (define_insn "parity2_cmpb"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] 
UNSPEC_PARITY))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "prty %0,%1"
   [(set_attr "type" "popcnt")])
 
@@ -2597,7 +2597,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
 (match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "cmpb %0,%1,%2"
   [(set_attr "type" "cmp")])
 
@@ -5415,7 +5415,7 @@
&& ((TARGET_PPC_GFXOPT
 && !HONOR_NANS (mode)
 && !HONOR_SIGNED_ZEROS (mode))
-   || TARGET_CMPB
+   || TARGET_POWER6
|| VECTOR_UNIT_VSX_P (mode))"
 {
   /* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5436,7 +5436,7 @@
   if (!gpc_reg_operand (operands[2], mode))
 operands[2] = copy_to_mode_reg (mode, operands[2]);
 
-  if (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))
+  if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode))
 {
   emit_insn (gen_copysign3_fcpsg

[gcc(refs/vendors/ibm/heads/mmaplus)] Change TARGET_FPRND to TARGET_POWER5X

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:25d8c2792e5e8ebf00b6d6a9295ad9e051895c6c

commit 25d8c2792e5e8ebf00b6d6a9295ad9e051895c6c
Author: Michael Meissner 
Date:   Tue Oct 22 16:48:59 2024 -0400

Change TARGET_FPRND to TARGET_POWER5X

As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER5X.  The FPRND instruction was added in power5+.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

* config/rs6000/rs6000.cc (report_architecture_mismatch): Use
TARGET_POWER5X instead of TARGET_FPRND.
* config/rs6000/rs6000.md (fmod3): Use TARGET_POWER5X instead 
of
TARGET_FPRND.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(btrunc2): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/config/rs6000/rs6000.md | 14 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 30cdf9480f1c..d27c089c9e34 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -25344,7 +25344,7 @@ report_architecture_mismatch (void)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POPCNTB)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ab62db7a2717..97535f912b83 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -6689,7 +6689,7 @@
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
friz %0,%1
@@ -6817,7 +6817,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6827,7 +6827,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6837,7 +6837,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6848,7 +6848,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
 UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_attr "type" "fp")])

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2686-Add paddis support.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:aa6348c986600150bc32069cf1e07a608f378068

commit aa6348c986600150bc32069cf1e07a608f378068
Author: Michael Meissner 
Date:   Tue Oct 22 17:01:20 2024 -0400

RFC2686-Add paddis support.

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/constraints.md (eU): New constraint.
(eV): Likewise.
* config/rs6000/predicates.md (paddis_operand): New predicate.
(paddis_paddi_operand): Likewise.
(add_operand): Add paddis support.
* config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis 
support.
(num_insns_constant_multi): Likewise.
(print_operand): Add %B for paddis support.
* config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
(SIGNED_INTEGER_32BIT_P): Likewise.
* config/rs6000/rs6000.md (isa attribute): Add paddis support.
(enabled attribute); Likewise.
(add3): Likewise.
(adddi3 splitter): New splitter for paddis.
(movdi_internal64): Add paddis support.
(movdi splitter): New splitter for paddis.

gcc/testsuite/

* gcc.target/powerpc/prefixed-addis.c: New test.

Diff:
---
 gcc/config/rs6000/constraints.md  | 10 +++
 gcc/config/rs6000/predicates.md   | 52 +++-
 gcc/config/rs6000/rs6000.cc   | 25 ++
 gcc/config/rs6000/rs6000.h|  4 +
 gcc/config/rs6000/rs6000.md   | 96 ---
 gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 ++
 6 files changed, 197 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 277a30a82458..4d8d21fd6bbb 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,6 +222,16 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
+(define_constraint "eU"
+  "@internal integer constant that can be loaded with paddis"
+  (and (match_code "const_int")
+   (match_operand 0 "paddis_operand")))
+
+(define_constraint "eV"
+  "@internal integer constant that can be loaded with paddis + paddi"
+  (and (match_code "const_int")
+   (match_operand 0 "paddis_paddi_operand")))
+
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 2797c3cf619b..f8e7df5e7f5b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,6 +369,53 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
+;; Return 1 if op is a 64-bit constant that uses the paddis instruction
+(define_predicate "paddis_operand"
+  (match_code "const_int")
+{
+  if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+  /* If addi, addis, or paddi can handle the number, don't return true.  */
+  HOST_WIDE_INT value = INTVAL (op);
+  if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+  /* If the number is too large for padds, return false.  */
+  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
+  if ((value & HOST_WIDE_INT_C(0x)) != 0)
+return false;
+
+  return true;
+})
+
+;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
+;; addi/addis/paddi instruction combination.
+(define_predicate "paddis_paddi_operand"
+  (match_code "const_int")
+{
+  if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+  /* If addi, addis, or paddi can handle the number, don't return true.  */
+  HOST_WIDE_INT value = INTVAL (op);
+  if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+  /* If the number is too large for padds, return false.  */
+  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
+  if ((value & HOST_WIDE_INT_C(0x)) == 0)
+return false;
+
+  return true;
+})
+
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1113,7 +1160,10 @@
   (if_then_else (match_code "const_int")
 (match_test "satisfies_constraint_I (op)
 || satisfies_constraint_L (op)
-|| satisfies_constraint_eI (op)")
+|| satisfies_constraint_eI (op)
+|| satisfies_constraint_eU (op)
+|| satisfies_constraint_eV (op)")
+
 (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e9b97b61679b..f78b5ec58637 100644
--- a/gcc/con

[gcc(refs/vendors/ibm/heads/mmaplus)] Set default name to power8 if no --with-cpu.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:57af3f6b604772d371328520b972755fed590704

commit 57af3f6b604772d371328520b972755fed590704
Author: Michael Meissner 
Date:   Wed Nov 6 16:52:07 2024 -0500

Set default name to power8 if no --with-cpu.

2024-11-06  Michael Meissner  

gcc/

* config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu 
name.

Diff:
---
 gcc/config/rs6000/default64.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index 10e3dec78aca..afa6542e040c 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -21,6 +21,7 @@ along with GCC; see the file COPYING3.  If not see
 #define RS6000_CPU(NAME, CPU, FLAGS)
 #include "rs6000-cpus.def"
 #undef RS6000_CPU
+#undef TARGET_CPU_DEFAULT
 
 #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
 #undef TARGET_DEFAULT
@@ -28,10 +29,20 @@ along with GCC; see the file COPYING3.  If not see
| MASK_LITTLE_ENDIAN)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower8"
+#define TARGET_CPU_DEFAULT "power8"
+
 #else
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower4"
+
+#if (TARGET_DEFAULT & MASK_POWERPC64)
+#define TARGET_CPU_DEFAULT "powerpc64"
+
+#else
+#define TARGET_CPU_DEFAULT "powerpc"
+#endif
+
 #endif

[gcc(refs/vendors/ibm/heads/mmaplus)] Add ChangeLog.dmf and update REVISION.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:899fe7e3026fef4d0a4e9fdc517bdaea67e156e8

commit 899fe7e3026fef4d0a4e9fdc517bdaea67e156e8
Author: Michael Meissner 
Date:   Tue Oct 22 16:38:02 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-10-22  Michael Meissner  

gcc/

* ChangeLog.mmaplus: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.mmaplus | 8 
 gcc/REVISION  | 1 +
 2 files changed, 9 insertions(+)

diff --git a/gcc/ChangeLog.mmaplus b/gcc/ChangeLog.mmaplus
new file mode 100644
index ..0872229a6baf
--- /dev/null
+++ b/gcc/ChangeLog.mmaplus
@@ -0,0 +1,8 @@
+Add ChangeLog.dmf and update REVISION.
+
+2024-10-22  Michael Meissner  
+
+gcc/
+
+   * ChangeLog.mmaplus: New file for branch.
+   * REVISION: Update.
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..2fe62cd77cb5
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+ibm/mmaplus branch

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2655-Add saturating subtract built-ins.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:92ab335ad4356e4c383a77fb2ab24bf60aefc44c

commit 92ab335ad4356e4c383a77fb2ab24bf60aefc44c
Author: Michael Meissner 
Date:   Tue Oct 22 17:00:35 2024 -0400

RFC2655-Add saturating subtract built-ins.

This patch adds support for a saturating subtract built-in function that 
may be
added to a future PowerPC processor.  Note, if it is added, the name of the
built-in function may change before GCC 13 is released.  If the name 
changes,
we will submit a patch changing the name.

I also added support for providing dense math built-in functions, even 
though
at present, we have not added any new built-in functions for dense math.  
It is
likely we will want to add new dense math built-in functions as the dense 
math
support is fleshed out.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-10-22   Michael Meissner  

gcc/

* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add 
support
for flagging invalid use of future built-in functions.
(rs6000_builtin_is_supported): Add support for future built-in
functions.
* config/rs6000/rs6000-builtins.def 
(__builtin_saturate_subtract32): New
built-in function for -mcpu=future.
(__builtin_saturate_subtract64): Likewise.
* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add 
stanzas
for -mcpu=future built-ins.
(stanza_map): Likewise.
(enable_string): Likewise.
(struct attrinfo): Likewise.
(parse_bif_attrs): Likewise.
(write_decls): Likewise.
* config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
built-in insn declarations.
(sat_sub3_dot): Likewise.
(sat_sub3_dot2): Likewise.
* doc/extend.texi (Future PowerPC built-ins): New section.

gcc/testsuite/

* gcc.target/powerpc/subfus-1.c: New test.
* gcc.target/powerpc/subfus-2.c: Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc | 17 
 gcc/config/rs6000/rs6000-builtins.def   | 10 +
 gcc/config/rs6000/rs6000-gen-builtins.cc| 35 ++---
 gcc/config/rs6000/rs6000.md | 60 +
 gcc/doc/extend.texi | 24 
 gcc/testsuite/gcc.target/powerpc/subfus-1.c | 32 +++
 gcc/testsuite/gcc.target/powerpc/subfus-2.c | 32 +++
 7 files changed, 205 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 8e4335e9b44f..a5f33eb9da18 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,6 +139,17 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
 case ENB_MMA:
   error ("%qs requires the %qs option", name, "-mmma");
   break;
+case ENB_FUTURE:
+  error ("%qs requires the %qs option", name, "-mcpu=future");
+  break;
+case ENB_FUTURE_64:
+  error ("%qs requires the %qs option and either the %qs or %qs option",
+name, "-mcpu=future", "-m64", "-mpowerpc64");
+  break;
+case ENB_DM:
+  error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
+"-mdense-math");
+  break;
 default:
 case ENB_ALWAYS:
   gcc_unreachable ();
@@ -194,6 +205,12 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
   return TARGET_HTM;
 case ENB_MMA:
   return TARGET_MMA;
+case ENB_FUTURE:
+  return TARGET_FUTURE;
+case ENB_FUTURE_64:
+  return TARGET_FUTURE && TARGET_POWERPC64;
+case ENB_DM:
+  return TARGET_DENSE_MATH;
 default:
   gcc_unreachable ();
 }
diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index 69046fd22442..84de393bc597 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -137,6 +137,8 @@
 ;   endian   Needs special handling for endianness
 ;   ibmldRestrict usage to the case when TFmode is IBM-128
 ;   ibm128   Restrict usage to the case where __ibm128 is supported or if ibmld
+;   future   Restrict usage to future instructions
+;   dm   Restrict usage to dense math
 ;
 ; Each attribute corresponds to extra processing required when
 ; the built-in is expanded.  All such special processing should
@@ -3933,3 +3935,11 @@
 
   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
 STXVP nothing {mma,pair}
+
+[future]
+  const signed int __builtin_saturate_subtract32 (signed int, signed int);
+  SAT_SUBSI sat_subsi3 {}
+
+[future-64]
+  const signed long __builtin_saturate_subtract64 (signed long,  signed long);
+  SAT_SUBDI sat_subdi3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc 
b/gcc/conf

[gcc(refs/vendors/ibm/heads/mmaplus)] Update ChangeLog.*

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:b0534a239f4e7cd1e7e19b16eeca2d6dba49b57a

commit b0534a239f4e7cd1e7e19b16eeca2d6dba49b57a
Author: Michael Meissner 
Date:   Wed Nov 6 16:54:27 2024 -0500

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.mmaplus | 13 +
 1 file changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.mmaplus b/gcc/ChangeLog.mmaplus
index 9664bf85d2b8..0ab6b3e7b1f0 100644
--- a/gcc/ChangeLog.mmaplus
+++ b/gcc/ChangeLog.mmaplus
@@ -1,3 +1,16 @@
+ Branch mmaplus, patch #22 
+
+Set default name to power8 if no --with-cpu.
+
+2024-11-06  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name.
+
+ Branch mmaplus, patch #21 was reverted 

+ Branch mmaplus, patch #21 was reverted 

+
  Branch mmaplus, patch #19 
 
 RFC2655-Add saturating subtract built-ins.

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2677-Add xvrlw support.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:12dc932b4ea19c1e6bb6d5dff6c4f6ea9f3f5e09

commit 12dc932b4ea19c1e6bb6d5dff6c4f6ea9f3f5e09
Author: Michael Meissner 
Date:   Tue Oct 22 17:02:33 2024 -0400

RFC2677-Add xvrlw support.

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/altivec.md (xvrlw): New insn.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.

gcc/testsuite/

* gcc.target/powerpc/vector-rotate-left.c: New test.

Diff:
---
 gcc/config/rs6000/altivec.md   | 14 +
 gcc/config/rs6000/rs6000.h |  3 ++
 .../gcc.target/powerpc/vector-rotate-left.c| 34 ++
 3 files changed, 51 insertions(+)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index b6a778ef6179..c76b1eeefe35 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,6 +1982,20 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; -mcpu=future adds a vector rotate left word variant.  There is no vector
+;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*xvrlw"
+  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+   (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+(match_operand:V4SI 2 "register_operand" "v,wa")))]
+  "TARGET_XVRLW"
+  "@
+   vrlw %0,%1,%2
+   xvrlw %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "altivec_vrl"
   [(set (match_operand:VI2 0 "register_operand" "=v")
 (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8bed27c821ce..fd61edd26970 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -587,6 +587,9 @@ extern int rs6000_vector_align[];
 /* Whether we have PADDIS support.  */
 #define TARGET_PADDIS  TARGET_FUTURE
 
+/* Whether we have XVRLW support.  */
+#define TARGET_XVRLW   TARGET_FUTURE
+
 /* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c 
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
new file mode 100644
index ..5a5f37755077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the xvrl (vector word rotate left using VSX registers insead of
+   Altivec registers is generated.  */
+
+#include 
+
+typedef vector unsigned int  v4si_t;
+
+v4si_t
+rotl_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x << n) | (x >> (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotr_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x >> n) | (x << (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotl_v4si_vector (v4si_t x, v4si_t y)
+{
+  __asm__ (" # %x0" : "+f" (x));   /* xvrlw.  */
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvrlw\M} 3  } } */

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2653-Add dense math test for new instruction names.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:8ae1c5a877c240fcec1c0217e687e316394103d3

commit 8ae1c5a877c240fcec1c0217e687e316394103d3
Author: Michael Meissner 
Date:   Tue Oct 22 16:57:52 2024 -0400

RFC2653-Add dense math test for new instruction names.

2024-10-22   Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/dm-double-test.c: New test.
* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
target test.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/dm-double-test.c | 194 ++
 gcc/testsuite/lib/target-supports.exp |  23 +++
 2 files changed, 217 insertions(+)

diff --git a/gcc/testsuite/gcc.target/powerpc/dm-double-test.c 
b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
new file mode 100644
index ..66c197795856
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
@@ -0,0 +1,194 @@
+/* Test derived from mma-double-1.c, modified for dense math.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_dense_math_ok } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+#include 
+#include 
+#include 
+
+typedef unsigned char vec_t __attribute__ ((vector_size (16)));
+typedef double v4sf_t __attribute__ ((vector_size (16)));
+#define SAVE_ACC(ACC, ldc, J)  \
+ __builtin_mma_disassemble_acc (result, ACC); \
+ rowC = (v4sf_t *) &CO[0*ldc+J]; \
+  rowC[0] += result[0]; \
+  rowC = (v4sf_t *) &CO[1*ldc+J]; \
+  rowC[0] += result[1]; \
+  rowC = (v4sf_t *) &CO[2*ldc+J]; \
+  rowC[0] += result[2]; \
+  rowC = (v4sf_t *) &CO[3*ldc+J]; \
+ rowC[0] += result[3];
+
+void
+DM (int m, int n, int k, double *A, double *B, double *C)
+{
+  __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;
+  v4sf_t result[4];
+  v4sf_t *rowC;
+  for (int l = 0; l < n; l += 4)
+{
+  double *CO;
+  double *AO;
+  AO = A;
+  CO = C;
+  C += m * 4;
+  for (int j = 0; j < m; j += 16)
+   {
+ double *BO = B;
+ __builtin_mma_xxsetaccz (&acc0);
+ __builtin_mma_xxsetaccz (&acc1);
+ __builtin_mma_xxsetaccz (&acc2);
+ __builtin_mma_xxsetaccz (&acc3);
+ __builtin_mma_xxsetaccz (&acc4);
+ __builtin_mma_xxsetaccz (&acc5);
+ __builtin_mma_xxsetaccz (&acc6);
+ __builtin_mma_xxsetaccz (&acc7);
+ unsigned long i;
+
+ for (i = 0; i < k; i++)
+   {
+ vec_t *rowA = (vec_t *) & AO[i * 16];
+ __vector_pair rowB;
+ vec_t *rb = (vec_t *) & BO[i * 4];
+ __builtin_mma_assemble_pair (&rowB, rb[1], rb[0]);
+ __builtin_mma_xvf64gerpp (&acc0, rowB, rowA[0]);
+ __builtin_mma_xvf64gerpp (&acc1, rowB, rowA[1]);
+ __builtin_mma_xvf64gerpp (&acc2, rowB, rowA[2]);
+ __builtin_mma_xvf64gerpp (&acc3, rowB, rowA[3]);
+ __builtin_mma_xvf64gerpp (&acc4, rowB, rowA[4]);
+ __builtin_mma_xvf64gerpp (&acc5, rowB, rowA[5]);
+ __builtin_mma_xvf64gerpp (&acc6, rowB, rowA[6]);
+ __builtin_mma_xvf64gerpp (&acc7, rowB, rowA[7]);
+   }
+ SAVE_ACC (&acc0, m, 0);
+ SAVE_ACC (&acc2, m, 4);
+ SAVE_ACC (&acc1, m, 2);
+ SAVE_ACC (&acc3, m, 6);
+ SAVE_ACC (&acc4, m, 8);
+ SAVE_ACC (&acc6, m, 12);
+ SAVE_ACC (&acc5, m, 10);
+ SAVE_ACC (&acc7, m, 14);
+ AO += k * 16;
+ BO += k * 4;
+ CO += 16;
+   }
+  B += k * 4;
+}
+}
+
+void
+init (double *matrix, int row, int column)
+{
+  for (int j = 0; j < column; j++)
+{
+  for (int i = 0; i < row; i++)
+   {
+ matrix[j * row + i] = (i * 16 + 2 + j) / 0.123;
+   }
+}
+}
+
+void
+init0 (double *matrix, double *matrix1, int row, int column)
+{
+  for (int j = 0; j < column; j++)
+for (int i = 0; i < row; i++)
+  matrix[j * row + i] = matrix1[j * row + i] = 0;
+}
+
+
+void
+print (const char *name, const double *matrix, int row, int column)
+{
+  printf ("Matrix %s has %d rows and %d columns:\n", name, row, column);
+  for (int i = 0; i < row; i++)
+{
+  for (int j = 0; j < column; j++)
+   {
+ printf ("%f ", matrix[j * row + i]);
+   }
+  printf ("\n");
+}
+  printf ("\n");
+}
+
+int
+main (int argc, char *argv[])
+{
+  int rowsA, colsB, common;
+  int i, j, k;
+  int ret = 0;
+
+  for (int t = 16; t <= 128; t += 16)
+{
+  for (int t1 = 4; t1 <= 16; t1 += 4)
+   {
+ rowsA = t;
+ colsB = t1;
+ common = 1;
+ /* printf ("Running test for rows = %d,cols = %d\n", t, t1); */
+ double A[rowsA * common];
+ double B[common * colsB];
+ double C[rowsA * colsB];
+ double D[rowsA * colsB];
+
+
+ init (A, rowsA, common);
+ init (B, common, colsB);
+ init0 (C, D, rowsA, colsB);
+ DM (rowsA, colsB, common, A, B

[gcc(refs/vendors/ibm/heads/mmaplus)] Update ChangeLog.*

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:93f4f03f35b1c37ee6618d7907e90b66c0bc0c88

commit 93f4f03f35b1c37ee6618d7907e90b66c0bc0c88
Author: Michael Meissner 
Date:   Tue Oct 22 17:55:58 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.mmaplus | 814 ++
 1 file changed, 814 insertions(+)

diff --git a/gcc/ChangeLog.mmaplus b/gcc/ChangeLog.mmaplus
index 0872229a6baf..9664bf85d2b8 100644
--- a/gcc/ChangeLog.mmaplus
+++ b/gcc/ChangeLog.mmaplus
@@ -1,3 +1,817 @@
+ Branch mmaplus, patch #19 
+
+RFC2655-Add saturating subtract built-ins.
+
+This patch adds support for a saturating subtract built-in function that may be
+added to a future PowerPC processor.  Note, if it is added, the name of the
+built-in function may change before GCC 13 is released.  If the name changes,
+we will submit a patch changing the name.
+
+I also added support for providing dense math built-in functions, even though
+at present, we have not added any new built-in functions for dense math.  It is
+likely we will want to add new dense math built-in functions as the dense math
+support is fleshed out.
+
+The patches have been tested on both little and big endian systems.  Can I 
check
+it into the master branch?
+
+2024-10-22   Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support
+   for flagging invalid use of future built-in functions.
+   (rs6000_builtin_is_supported): Add support for future built-in
+   functions.
+   * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New
+   built-in function for -mcpu=future.
+   (__builtin_saturate_subtract64): Likewise.
+   * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas
+   for -mcpu=future built-ins.
+   (stanza_map): Likewise.
+   (enable_string): Likewise.
+   (struct attrinfo): Likewise.
+   (parse_bif_attrs): Likewise.
+   (write_decls): Likewise.
+   * config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
+   built-in insn declarations.
+   (sat_sub3_dot): Likewise.
+   (sat_sub3_dot2): Likewise.
+   * doc/extend.texi (Future PowerPC built-ins): New section.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/subfus-1.c: New test.
+   * gcc.target/powerpc/subfus-2.c: Likewise.
+
+ Branch mmaplus, patch #18 
+
+RFC2656-Support load/store vector with right length.
+
+This patch adds support for new instructions that may be added to the PowerPC
+architecture in the future to enhance the load and store vector with length
+instructions.
+
+The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use
+since the count for the number of bytes must be in the top 8 bits of the GPR
+register, instead of the bottom 8 bits.  This meant that code generating these
+instructions typically had to do a shift left by 56 bits to get the count into
+the right position.  In a future version of the PowerPC architecture, new
+variants of these instructions might be added that expect the count to be in
+the bottom 8 bits of the GPR register.  These patches add this support to GCC
+if the user uses the -mcpu=future option.
+
+I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl
+future lxvll/stxvll instructions would generate these instructions on 32-bit.
+However the patterns for these instructions is only done on 64-bit systems.  So
+I added a check for 64-bit support before generating the instructions.
+
+The patches have been tested on both little and big endian systems.  Can I 
check
+it into the master branch?
+
+2024-10-22   Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-string.cc (expand_block_move): Do not generate
+   lxvl and stxvl on 32-bit.
+   * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with
+   the shift count automaticaly used in the insn.
+   (lxvrl): New insn for -mcpu=future.
+   (lxvrll): Likewise.
+   (stxvl): If -mcpu=future, generate the stxvl with the shift count
+   automaticaly used in the insn.
+   (stxvrl): New insn for -mcpu=future.
+   (stxvrll): Likewise.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/lxvrl.c: New test.
+   * lib/target-supports.exp (check_effective_target_powerpc_future_ok):
+   New effective target.
+
+ Branch mmaplus, patch #17 
+
+RFC2653-PowerPC: Add support for 1,024 bit DMR registers.
+
+This patch is a prelimianry patch to add the full 1,024 bit dense math register
+(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of the
+DMR register.
+
+This patch only adds the new 1,024 bit register support.  It does not add
+support for any instructions that need 1,024 bit registers instead of 512 bit
+registers.
+
+I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
+registers.  Th

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:cfffa0fc9c76e930d507a549527ede03862f81ad

commit cfffa0fc9c76e930d507a549527ede03862f81ad
Author: Michael Meissner 
Date:   Tue Oct 22 16:58:33 2024 -0400

RFC2653-PowerPC: Add support for 1,024 bit DMR registers.

This patch is a prelimianry patch to add the full 1,024 bit dense math 
register
(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of 
the
DMR register.

This patch only adds the new 1,024 bit register support.  It does not add
support for any instructions that need 1,024 bit registers instead of 512 
bit
registers.

I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
registers.  The 'wD' constraint added in previous patches is used for these
registers.  I added support to do load and store of DMRs via the VSX 
registers,
since there are no load/store dense math instructions.  I added the new 
keyword
'__dmr' to create 1,024 bit types that can be loaded into DMRs.  At 
present, I
don't have aliases for __dmr512 and __dmr1024 that we've discussed 
internally.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-10-22   Michael Meissner  

gcc/

* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(movtdo): New define_expand and define_insn_and_split to implement 
1,024
bit DMR registers.
(movtdo_insert512_upper): New insn.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr_to_memory): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
support.
(rs6000_init_builtins): Add support for __dmr keyword.
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add 
support
for TDOmode.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-modes.def (TDOmode): New mode.
* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
support for TDOmode.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_hard_regno_mode_ok): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Add support for TDOmode.  Setup 
reload
hooks for DMR mode.
(reg_offset_addressing_ok_p): Add support for TDOmode.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(rs6000_mangle_type): Add mangling for __dmr type.
(rs6000_dmr_register_move_cost): Add support for TDOmode.
(rs6000_split_multireg_move): Likewise.
(rs6000_invalid_conversion): Likewise.
* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
(enum rs6000_builtin_type_index): Add DMR type nodes.
(dmr_type_node): Likewise.
(ptr_dmr_type_node): Likewise.

gcc/testsuite/

* gcc.target/powerpc/dm-1024bit.c: New test.

Diff:
---
 gcc/config/rs6000/mma.md  | 154 ++
 gcc/config/rs6000/rs6000-builtin.cc   |  17 +++
 gcc/config/rs6000/rs6000-call.cc  |  10 +-
 gcc/config/rs6000/rs6000-modes.def|   4 +
 gcc/config/rs6000/rs6000.cc   | 101 -
 gcc/config/rs6000/rs6000.h|   6 +-
 gcc/testsuite/gcc.target/powerpc/dm-1024bit.c |  63 +++
 7 files changed, 321 insertions(+), 34 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 2e04eb653fa6..8461499e1c3d 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -92,6 +92,11 @@
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
UNSPEC_MMA_DMSETDMRZ
+   UNSPEC_DM_INSERT512_UPPER
+   UNSPEC_DM_INSERT512_LOWER
+   UNSPEC_DM_EXTRACT512
+   UNSPEC_DMR_RELOAD_FROM_MEMORY
+   UNSPEC_DMR_RELOAD_TO_MEMORY
   ])
 
 (define_c_enum "unspecv"
@@ -793,3 +798,152 @@
 }
   [(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
+
+;; TDOmode (__dmr keyword for 1,024 bit registers).
+(define_expand "movtdo"
+  [(set (match_operand:TDO 0 "nonimmediate_operand")
+   (match_operand:TDO 1 "input_operand"))]
+  "TARGET_MMA_DENSE_MATH"
+{
+  rs6000_emit_move (operands[0], operands[1], TDOmode);
+  DONE;
+})
+
+(define_insn_and_split "*movtdo"
+  [(set (match_operand:TDO

[gcc r13-9344] rs6000: Fix ICE for invalid constants in built-in functions

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:2c42f598b4365fac40bbc32a795e42b87962c874

commit r13-9344-g2c42f598b4365fac40bbc32a795e42b87962c874
Author: Peter Bergner 
Date:   Thu Jan 16 10:53:27 2025 -0600

rs6000: Fix ICE for invalid constants in built-in functions

For invalid constant operand values used in built-in functions, return
const0_rtx to signify an error occurred during expansion.

2025-01-16  Peter Bergner  

gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
const0_rtx when there is an error.

gcc/testsuite/
* gcc.target/powerpc/mma-builtin-error.c: New test.

(cherry picked from commit 0696af74b3392e2178215607337b116d1bb53e34)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc  |  8 
 gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c | 11 +++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 3ed3930067dc..12bd3cec0d5c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3552,7 +3552,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
error ("argument %d must be a literal between 0 and %d,"
   " inclusive",
   bifaddr->restr_opnd[i], p);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3569,7 +3569,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   " inclusive",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3586,7 +3586,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   "between %d and %d, inclusive",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3602,7 +3602,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   "literal %d",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c 
b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
new file mode 100644
index ..a87a15709255
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+typedef unsigned char vec_t __attribute__((vector_size(16)));
+
+void
+foo (__vector_quad *dst, vec_t vec0, vec_t vec1) /* { dg-error "argument 5 
must be a literal between 0 and 15, inclusive" } */
+{
+  __builtin_mma_pmxvi8ger4 (dst, vec0, vec1, 15, 15, -1);
+}

[gcc r13-9343] rs6000: Fix loop limit for built-in constant checking

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:a54c3a72defe4bd7c33f20fc3d51496e160a8aa7

commit r13-9343-ga54c3a72defe4bd7c33f20fc3d51496e160a8aa7
Author: Peter Bergner 
Date:   Thu Jan 16 10:49:45 2025 -0600

rs6000: Fix loop limit for built-in constant checking

The loop checking for built-in constant operand restrictions was missing
some operands due to the loop limit being too small.  Fixing that exposed
a testsuite failure which is caused by a typo in the pmxvi4ger8pp definition
where we had made the PMASK field too small.

2025-01-16  Peter Bergner  

gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use 
correct
array size for the loop limit.
* config/rs6000/rs6000-builtins.def: Fix field size for PMASK 
operand.

(cherry picked from commit 1a2d63a78f99b7fdc2eff5bf9065682d5bbbaaca)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc   | 2 +-
 gcc/config/rs6000/rs6000-builtins.def | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 0cb6e742c6b2..3ed3930067dc 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3534,7 +3534,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
 }
 
   /* Check for restricted constant arguments.  */
-  for (int i = 0; i < 2; i++)
+  for (size_t i = 0; i < ARRAY_SIZE (bifaddr->restr); i++)
 {
   switch (bifaddr->restr[i])
{
diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index f3dcb739245b..8f1a9efbc3d0 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3862,11 +3862,11 @@
 PMXVI4GER8_INTERNAL mma_pmxvi4ger8 {mma}
 
   void __builtin_mma_pmxvi4ger8pp (v512 *, vuc, vuc, const int<4>, \
-   const int<4>, const int<4>);
+   const int<4>, const int<8>);
 PMXVI4GER8PP nothing {mma,quad,mmaint}
 
   v512 __builtin_mma_pmxvi4ger8pp_internal (v512, vuc, vuc, const int<4>, \
-const int<4>, const int<4>);
+const int<4>, const int<8>);
 PMXVI4GER8PP_INTERNAL mma_pmxvi4ger8pp {mma,quad}
 
   void __builtin_mma_pmxvi8ger4 (v512 *, vuc, vuc, const int<4>, \

[gcc r12-10929] rs6000: Fix loop limit for built-in constant checking

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:4e508cbb938a8936bc6aefd7823b55107aa4a7f9

commit r12-10929-g4e508cbb938a8936bc6aefd7823b55107aa4a7f9
Author: Peter Bergner 
Date:   Thu Jan 16 10:49:45 2025 -0600

rs6000: Fix loop limit for built-in constant checking

The loop checking for built-in constant operand restrictions was missing
some operands due to the loop limit being too small.  Fixing that exposed
a testsuite failure which is caused by a typo in the pmxvi4ger8pp definition
where we had made the PMASK field too small.

2025-01-16  Peter Bergner  

gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use 
correct
array size for the loop limit.
* config/rs6000/rs6000-builtins.def: Fix field size for PMASK 
operand.

(cherry picked from commit 1a2d63a78f99b7fdc2eff5bf9065682d5bbbaaca)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc   | 2 +-
 gcc/config/rs6000/rs6000-builtins.def | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index f01f3aded362..d467db29e8e3 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3584,7 +3584,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
 }
 
   /* Check for restricted constant arguments.  */
-  for (int i = 0; i < 2; i++)
+  for (size_t i = 0; i < ARRAY_SIZE (bifaddr->restr); i++)
 {
   switch (bifaddr->restr[i])
{
diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index d2c0565dc623..eca7ad2f5fae 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3861,11 +3861,11 @@
 PMXVI4GER8_INTERNAL mma_pmxvi4ger8 {mma}
 
   void __builtin_mma_pmxvi4ger8pp (v512 *, vuc, vuc, const int<4>, \
-   const int<4>, const int<4>);
+   const int<4>, const int<8>);
 PMXVI4GER8PP nothing {mma,quad,mmaint}
 
   v512 __builtin_mma_pmxvi4ger8pp_internal (v512, vuc, vuc, const int<4>, \
-const int<4>, const int<4>);
+const int<4>, const int<8>);
 PMXVI4GER8PP_INTERNAL mma_pmxvi4ger8pp {mma,quad}
 
   void __builtin_mma_pmxvi8ger4 (v512 *, vuc, vuc, const int<4>, \

[gcc r12-10930] rs6000: Fix ICE for invalid constants in built-in functions

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:4dbace39f1149984e6b85574d4665ce18240db8e

commit r12-10930-g4dbace39f1149984e6b85574d4665ce18240db8e
Author: Peter Bergner 
Date:   Thu Jan 16 10:53:27 2025 -0600

rs6000: Fix ICE for invalid constants in built-in functions

For invalid constant operand values used in built-in functions, return
const0_rtx to signify an error occurred during expansion.

2025-01-16  Peter Bergner  

gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
const0_rtx when there is an error.

gcc/testsuite/
* gcc.target/powerpc/mma-builtin-error.c: New test.

(cherry picked from commit 0696af74b3392e2178215607337b116d1bb53e34)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc  |  8 
 gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c | 11 +++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index d467db29e8e3..a1549fe2a15f 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3602,7 +3602,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
error ("argument %d must be a literal between 0 and %d,"
   " inclusive",
   bifaddr->restr_opnd[i], p);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3619,7 +3619,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   " inclusive",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3636,7 +3636,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   "between %d and %d, inclusive",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3652,7 +3652,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   "literal %d",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c 
b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
new file mode 100644
index ..a87a15709255
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+typedef unsigned char vec_t __attribute__((vector_size(16)));
+
+void
+foo (__vector_quad *dst, vec_t vec0, vec_t vec1) /* { dg-error "argument 5 
must be a literal between 0 and 15, inclusive" } */
+{
+  __builtin_mma_pmxvi8ger4 (dst, vec0, vec1, 15, 15, -1);
+}

[gcc r14-11241] rs6000: Fix loop limit for built-in constant checking

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:68df37647bdce7fc85c5f0f25629027800a4fcb5

commit r14-11241-g68df37647bdce7fc85c5f0f25629027800a4fcb5
Author: Peter Bergner 
Date:   Thu Jan 16 10:49:45 2025 -0600

rs6000: Fix loop limit for built-in constant checking

The loop checking for built-in constant operand restrictions was missing
some operands due to the loop limit being too small.  Fixing that exposed
a testsuite failure which is caused by a typo in the pmxvi4ger8pp definition
where we had made the PMASK field too small.

2025-01-16  Peter Bergner  

gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use 
correct
array size for the loop limit.
* config/rs6000/rs6000-builtins.def: Fix field size for PMASK 
operand.

(cherry picked from commit 1a2d63a78f99b7fdc2eff5bf9065682d5bbbaaca)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc   | 2 +-
 gcc/config/rs6000/rs6000-builtins.def | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index d8b18b2b8ce9..ce66fb3e3d57 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3548,7 +3548,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
 }
 
   /* Check for restricted constant arguments.  */
-  for (int i = 0; i < 2; i++)
+  for (size_t i = 0; i < ARRAY_SIZE (bifaddr->restr); i++)
 {
   switch (bifaddr->restr[i])
{
diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index 3bc7fed69568..80f5fbb9e823 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3885,11 +3885,11 @@
 PMXVI4GER8_INTERNAL mma_pmxvi4ger8 {mma}
 
   void __builtin_mma_pmxvi4ger8pp (v512 *, vuc, vuc, const int<4>, \
-   const int<4>, const int<4>);
+   const int<4>, const int<8>);
 PMXVI4GER8PP nothing {mma,quad,mmaint}
 
   v512 __builtin_mma_pmxvi4ger8pp_internal (v512, vuc, vuc, const int<4>, \
-const int<4>, const int<4>);
+const int<4>, const int<8>);
 PMXVI4GER8PP_INTERNAL mma_pmxvi4ger8pp {mma,quad}
 
   void __builtin_mma_pmxvi8ger4 (v512 *, vuc, vuc, const int<4>, \

[gcc r14-11242] rs6000: Fix ICE for invalid constants in built-in functions

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:a1acb1c0edec1e04b20b3e7d561a04098dfd47b6

commit r14-11242-ga1acb1c0edec1e04b20b3e7d561a04098dfd47b6
Author: Peter Bergner 
Date:   Thu Jan 16 10:53:27 2025 -0600

rs6000: Fix ICE for invalid constants in built-in functions

For invalid constant operand values used in built-in functions, return
const0_rtx to signify an error occurred during expansion.

2025-01-16  Peter Bergner  

gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
const0_rtx when there is an error.

gcc/testsuite/
* gcc.target/powerpc/mma-builtin-error.c: New test.

(cherry picked from commit 0696af74b3392e2178215607337b116d1bb53e34)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc  |  8 
 gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c | 11 +++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index ce66fb3e3d57..72278367bdb3 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3566,7 +3566,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
error ("argument %d must be a literal between 0 and %d,"
   " inclusive",
   bifaddr->restr_opnd[i], p);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3583,7 +3583,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   " inclusive",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3600,7 +3600,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   "between %d and %d, inclusive",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3616,7 +3616,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   "literal %d",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c 
b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
new file mode 100644
index ..a87a15709255
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+typedef unsigned char vec_t __attribute__((vector_size(16)));
+
+void
+foo (__vector_quad *dst, vec_t vec0, vec_t vec1) /* { dg-error "argument 5 
must be a literal between 0 and 15, inclusive" } */
+{
+  __builtin_mma_pmxvi8ger4 (dst, vec0, vec1, 15, 15, -1);
+}

[gcc r15-6883] rs6000: Add clobber and guard for vsx_stxvd2x4_le_const [PR116030]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:f12bb6c26b86c616e4de8c542804cb5b5c9ebdc6

commit r15-6883-gf12bb6c26b86c616e4de8c542804cb5b5c9ebdc6
Author: Jiufu Guo 
Date:   Mon Jan 13 18:16:16 2025 -0600

rs6000: Add clobber and guard for vsx_stxvd2x4_le_const [PR116030]

Previously, vsx_stxvd2x4_le_const_ was introduced for 'split1' pass,
so it is guarded by "can_create_pseudo_p ()".  While it would be possible
to match the pattern of this insn during/after RA, this insn could be
updated to make it work for split pass after RA.

And this insn would not be the best choice if the address has alignment like
"&(-16)", so "!altivec_indexed_or_indirect_operand" is added to guard this 
insn.

2025-01-13  Jiufu Guo  

gcc/
PR target/116030
* config/rs6000/vsx.md (vsx_stxvd2x4_le_const_): Add clobber
and guard with !altivec_indexed_or_indirect_operand.

gcc/testsuite/
PR target/116030
* gcc.target/powerpc/pr116030.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md| 10 ++
 gcc/testsuite/gcc.target/powerpc/pr116030.c | 22 ++
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d4e0190484a0..dd3573b80868 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3453,12 +3453,13 @@
 
 (define_insn_and_split "vsx_stxvd2x4_le_const_"
   [(set (match_operand:VSX_W 0 "memory_operand" "=Z")
-   (match_operand:VSX_W 1 "immediate_operand" "W"))]
+   (match_operand:VSX_W 1 "immediate_operand" "W"))
+   (clobber (match_scratch:VSX_W 2 "=wa"))]
   "!BYTES_BIG_ENDIAN
&& VECTOR_MEM_VSX_P (mode)
&& !TARGET_P9_VECTOR
-   && const_vec_duplicate_p (operands[1])
-   && can_create_pseudo_p ()"
+   && !altivec_indexed_or_indirect_operand (operands[0], mode)
+   && const_vec_duplicate_p (operands[1])"
   "#"
   "&& 1"
   [(set (match_dup 2)
@@ -3471,7 +3472,8 @@
 {
   /* Here all the constants must be loaded without memory.  */
   gcc_assert (easy_altivec_constant (operands[1], mode));
-  operands[2] = gen_reg_rtx (mode);
+  if (GET_CODE (operands[2]) == SCRATCH)
+operands[2] = gen_reg_rtx (mode);
 }
   [(set_attr "type" "vecstore")
(set_attr "length" "8")])
diff --git a/gcc/testsuite/gcc.target/powerpc/pr116030.c 
b/gcc/testsuite/gcc.target/powerpc/pr116030.c
new file mode 100644
index ..da27106a5a75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr116030.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power8 -Os -fno-forward-propagate 
-ftrivial-auto-var-init=zero" } */
+/* { dg-require-effective-target dfp } */
+
+/* Verify we do not ICE on the tests below.  */
+
+/* { dg-final { scan-assembler-not "rldicr" { target { le } } } } */
+/* { dg-final { scan-assembler-not "stxvd2x" { target { le } } } } */
+
+union U128
+{
+  _Decimal128 d;
+  unsigned long long int u[2];
+};
+
+union U128
+foo ()
+{
+  volatile union U128 u128;
+  u128.d = 0.99e+39DL;
+  return u128;
+}

[gcc r15-6959] rs6000: Fix loop limit for built-in constant checking

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:1a2d63a78f99b7fdc2eff5bf9065682d5bbbaaca

commit r15-6959-g1a2d63a78f99b7fdc2eff5bf9065682d5bbbaaca
Author: Peter Bergner 
Date:   Thu Jan 16 10:49:45 2025 -0600

rs6000: Fix loop limit for built-in constant checking

The loop checking for built-in constant operand restrictions was missing
some operands due to the loop limit being too small.  Fixing that exposed
a testsuite failure which is caused by a typo in the pmxvi4ger8pp definition
where we had made the PMASK field too small.

2025-01-16  Peter Bergner  

gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use 
correct
array size for the loop limit.
* config/rs6000/rs6000-builtins.def: Fix field size for PMASK 
operand.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc   | 2 +-
 gcc/config/rs6000/rs6000-builtins.def | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index bdf2fa0b680b..0251a240b1a1 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3441,7 +3441,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
 }
 
   /* Check for restricted constant arguments.  */
-  for (int i = 0; i < 2; i++)
+  for (size_t i = 0; i < ARRAY_SIZE (bifaddr->restr); i++)
 {
   switch (bifaddr->restr[i])
{
diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index 320049d8b0ab..3ca63739d317 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3687,11 +3687,11 @@
 PMXVI4GER8_INTERNAL mma_pmxvi4ger8 {mma}
 
   void __builtin_mma_pmxvi4ger8pp (v512 *, vuc, vuc, const int<4>, \
-   const int<4>, const int<4>);
+   const int<4>, const int<8>);
 PMXVI4GER8PP nothing {mma,quad,mmaint}
 
   v512 __builtin_mma_pmxvi4ger8pp_internal (v512, vuc, vuc, const int<4>, \
-const int<4>, const int<4>);
+const int<4>, const int<8>);
 PMXVI4GER8PP_INTERNAL mma_pmxvi4ger8pp {mma,quad}
 
   void __builtin_mma_pmxvi8ger4 (v512 *, vuc, vuc, const int<4>, \

[gcc r15-6960] rs6000: Fix ICE for invalid constants in built-in functions

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:0696af74b3392e2178215607337b116d1bb53e34

commit r15-6960-g0696af74b3392e2178215607337b116d1bb53e34
Author: Peter Bergner 
Date:   Thu Jan 16 10:53:27 2025 -0600

rs6000: Fix ICE for invalid constants in built-in functions

For invalid constant operand values used in built-in functions, return
const0_rtx to signify an error occurred during expansion.

2025-01-16  Peter Bergner  

gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
const0_rtx when there is an error.

gcc/testsuite/
* gcc.target/powerpc/mma-builtin-error.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc  |  8 
 gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c | 11 +++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 0251a240b1a1..111802381acb 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3459,7 +3459,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
error ("argument %d must be a literal between 0 and %d,"
   " inclusive",
   bifaddr->restr_opnd[i], p);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3476,7 +3476,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   " inclusive",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3493,7 +3493,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   "between %d and %d, inclusive",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
@@ -3509,7 +3509,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* 
subtarget */,
   "literal %d",
   bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
   bifaddr->restr_val2[i]);
-   return CONST0_RTX (mode[0]);
+   return const0_rtx;
  }
break;
  }
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c 
b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
new file mode 100644
index ..a87a15709255
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+typedef unsigned char vec_t __attribute__((vector_size(16)));
+
+void
+foo (__vector_quad *dst, vec_t vec0, vec_t vec1) /* { dg-error "argument 5 
must be a literal between 0 and 15, inclusive" } */
+{
+  __builtin_mma_pmxvi8ger4 (dst, vec0, vec1, 15, 15, -1);
+}

[gcc r15-9188] rs6000: Add Cobol support to traceback table [PR119308]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:c669ab0a866697577fec0c8c2e662640c4be4c94

commit r15-9188-gc669ab0a866697577fec0c8c2e662640c4be4c94
Author: Peter Bergner 
Date:   Thu Apr 3 10:52:29 2025 -0500

rs6000: Add Cobol support to traceback table [PR119308]

The AIX traceback table documentation states the tbtab "lang" field for
Cobol should be set to 7.  Use it.

2025-04-03  Peter Bergner  

gcc/
PR target/119308
* config/rs6000/rs6000-logue.cc (rs6000_output_function_epilogue):
Handle GCC COBOL for the tbtab lang field.

Diff:
---
 gcc/config/rs6000/rs6000-logue.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/rs6000/rs6000-logue.cc 
b/gcc/config/rs6000/rs6000-logue.cc
index 52f44b114b06..5377ad6cee62 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -5351,6 +5351,8 @@ rs6000_output_function_epilogue (FILE *file)
i = 1;
   else if (! strcmp (language_string, "GNU Ada"))
i = 3;
+  else if (! strcmp (language_string, "GCC COBOL"))
+   i = 7;
   else if (! strcmp (language_string, "GNU Modula-2"))
i = 8;
   else if (lang_GNU_CXX ()

[gcc r15-9538] testsuite: Replace altivec vector attribute with generic equivalent [PR112822]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:17c5ad25811a92c45083a0ad0b9c7e0d944c9521

commit r15-9538-g17c5ad25811a92c45083a0ad0b9c7e0d944c9521
Author: Peter Bergner 
Date:   Wed Apr 16 21:48:59 2025 +

testsuite: Replace altivec vector attribute with generic equivalent 
[PR112822]

Usage of the altivec vector attribute requires use of the -maltivec option.
Replace with a generic equivalent which allows building the test case on
multiple other targets and non-altivec ppc cpus, but still diagnoses the
ICE on unfixed compilers.

2025-04-16  Peter Bergner  

gcc/testsuite/
PR tree-optimization/112822
* g++.dg/pr112822.C: Replace altivec vector attribute with a generic
vector attribute.

Diff:
---
 gcc/testsuite/g++.dg/pr112822.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/pr112822.C b/gcc/testsuite/g++.dg/pr112822.C
index a8557522467d..f88bd833c92d 100644
--- a/gcc/testsuite/g++.dg/pr112822.C
+++ b/gcc/testsuite/g++.dg/pr112822.C
@@ -89,7 +89,7 @@ template  struct cg { 
typedef aj cn; };
 namespace ai {
 template  cj cp;
 template  void cl(bu *cr, cj cs) { ct(cr, cs); }
-typedef __attribute__((altivec(vector__))) double co;
+typedef double co __attribute__ ((vector_size (16)));
 void ct(double *cr, co cs) { *(co *)cr = cs; }
 struct cq {
   co q;

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:453484d9b339d29b44323734f838bb8b301b085f

commit 453484d9b339d29b44323734f838bb8b301b085f
Author: Michael Meissner 
Date:   Tue Oct 22 16:58:33 2024 -0400

RFC2653-PowerPC: Add support for 1,024 bit DMR registers.

This patch is a prelimianry patch to add the full 1,024 bit dense math 
register
(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of 
the
DMR register.

This patch only adds the new 1,024 bit register support.  It does not add
support for any instructions that need 1,024 bit registers instead of 512 
bit
registers.

I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
registers.  The 'wD' constraint added in previous patches is used for these
registers.  I added support to do load and store of DMRs via the VSX 
registers,
since there are no load/store dense math instructions.  I added the new 
keyword
'__dmr' to create 1,024 bit types that can be loaded into DMRs.  At 
present, I
don't have aliases for __dmr512 and __dmr1024 that we've discussed 
internally.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-10-22   Michael Meissner  

gcc/

* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(movtdo): New define_expand and define_insn_and_split to implement 
1,024
bit DMR registers.
(movtdo_insert512_upper): New insn.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr_to_memory): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
support.
(rs6000_init_builtins): Add support for __dmr keyword.
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add 
support
for TDOmode.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-modes.def (TDOmode): New mode.
* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
support for TDOmode.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_hard_regno_mode_ok): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Add support for TDOmode.  Setup 
reload
hooks for DMR mode.
(reg_offset_addressing_ok_p): Add support for TDOmode.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(rs6000_mangle_type): Add mangling for __dmr type.
(rs6000_dmr_register_move_cost): Add support for TDOmode.
(rs6000_split_multireg_move): Likewise.
(rs6000_invalid_conversion): Likewise.
* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
(enum rs6000_builtin_type_index): Add DMR type nodes.
(dmr_type_node): Likewise.
(ptr_dmr_type_node): Likewise.

gcc/testsuite/

* gcc.target/powerpc/dm-1024bit.c: New test.

Diff:
---
 gcc/config/rs6000/mma.md  | 154 ++
 gcc/config/rs6000/rs6000-builtin.cc   |  17 +++
 gcc/config/rs6000/rs6000-call.cc  |  10 +-
 gcc/config/rs6000/rs6000-modes.def|   4 +
 gcc/config/rs6000/rs6000.cc   | 101 -
 gcc/config/rs6000/rs6000.h|   6 +-
 gcc/testsuite/gcc.target/powerpc/dm-1024bit.c |  63 +++
 7 files changed, 321 insertions(+), 34 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 31040ab1d5ba..6acd37d4e87f 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -92,6 +92,11 @@
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
UNSPEC_MMA_DMSETDMRZ
+   UNSPEC_DM_INSERT512_UPPER
+   UNSPEC_DM_INSERT512_LOWER
+   UNSPEC_DM_EXTRACT512
+   UNSPEC_DMR_RELOAD_FROM_MEMORY
+   UNSPEC_DMR_RELOAD_TO_MEMORY
   ])
 
 (define_c_enum "unspecv"
@@ -793,3 +798,152 @@
 }
   [(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
+
+;; TDOmode (__dmr keyword for 1,024 bit registers).
+(define_expand "movtdo"
+  [(set (match_operand:TDO 0 "nonimmediate_operand")
+   (match_operand:TDO 1 "input_operand"))]
+  "TARGET_MMA_DENSE_MATH"
+{
+  rs6000_emit_move (operands[0], operands[1], TDOmode);
+  DONE;
+})
+
+(define_insn_and_split "*movtdo"
+  [(set (match_operand:TDO

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2677-Add xvrlw support.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:904961a355ecae12ce801a7475b439d5e8ef1479

commit 904961a355ecae12ce801a7475b439d5e8ef1479
Author: Michael Meissner 
Date:   Tue Oct 22 17:02:33 2024 -0400

RFC2677-Add xvrlw support.

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/altivec.md (xvrlw): New insn.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.

gcc/testsuite/

* gcc.target/powerpc/vector-rotate-left.c: New test.

Diff:
---
 gcc/config/rs6000/altivec.md   | 14 +
 gcc/config/rs6000/rs6000.h |  3 ++
 .../gcc.target/powerpc/vector-rotate-left.c| 34 ++
 3 files changed, 51 insertions(+)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7edc288a6565..d158cf479d60 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,6 +1982,20 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; -mcpu=future adds a vector rotate left word variant.  There is no vector
+;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*xvrlw"
+  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+   (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+(match_operand:V4SI 2 "register_operand" "v,wa")))]
+  "TARGET_XVRLW"
+  "@
+   vrlw %0,%1,%2
+   xvrlw %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "altivec_vrl"
   [(set (match_operand:VI2 0 "register_operand" "=v")
 (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3cac81a0bd95..9f4edf668454 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -587,6 +587,9 @@ extern int rs6000_vector_align[];
 /* Whether we have PADDIS support.  */
 #define TARGET_PADDIS  TARGET_FUTURE
 
+/* Whether we have XVRLW support.  */
+#define TARGET_XVRLW   TARGET_FUTURE
+
 /* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c 
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
new file mode 100644
index ..5a5f37755077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the xvrl (vector word rotate left using VSX registers insead of
+   Altivec registers is generated.  */
+
+#include 
+
+typedef vector unsigned int  v4si_t;
+
+v4si_t
+rotl_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x << n) | (x >> (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotr_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x >> n) | (x << (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotl_v4si_vector (v4si_t x, v4si_t y)
+{
+  __asm__ (" # %x0" : "+f" (x));   /* xvrlw.  */
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvrlw\M} 3  } } */

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2686-Add paddis support.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:83a5d8b95e312f0c19998719dbe048d67fce3415

commit 83a5d8b95e312f0c19998719dbe048d67fce3415
Author: Michael Meissner 
Date:   Tue Oct 22 17:01:20 2024 -0400

RFC2686-Add paddis support.

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/constraints.md (eU): New constraint.
(eV): Likewise.
* config/rs6000/predicates.md (paddis_operand): New predicate.
(paddis_paddi_operand): Likewise.
(add_operand): Add paddis support.
* config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis 
support.
(num_insns_constant_multi): Likewise.
(print_operand): Add %B for paddis support.
* config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
(SIGNED_INTEGER_32BIT_P): Likewise.
* config/rs6000/rs6000.md (isa attribute): Add paddis support.
(enabled attribute); Likewise.
(add3): Likewise.
(adddi3 splitter): New splitter for paddis.
(movdi_internal64): Add paddis support.
(movdi splitter): New splitter for paddis.

gcc/testsuite/

* gcc.target/powerpc/prefixed-addis.c: New test.

Diff:
---
 gcc/config/rs6000/constraints.md  | 10 +++
 gcc/config/rs6000/predicates.md   | 52 +++-
 gcc/config/rs6000/rs6000.cc   | 25 ++
 gcc/config/rs6000/rs6000.h|  4 +
 gcc/config/rs6000/rs6000.md   | 96 ---
 gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 ++
 6 files changed, 197 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 3da9ed086810..5440becb6e6c 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,6 +222,16 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
+(define_constraint "eU"
+  "@internal integer constant that can be loaded with paddis"
+  (and (match_code "const_int")
+   (match_operand 0 "paddis_operand")))
+
+(define_constraint "eV"
+  "@internal integer constant that can be loaded with paddis + paddi"
+  (and (match_code "const_int")
+   (match_operand 0 "paddis_paddi_operand")))
+
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index c95b4336f062..c206860e4927 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,6 +369,53 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
+;; Return 1 if op is a 64-bit constant that uses the paddis instruction
+(define_predicate "paddis_operand"
+  (match_code "const_int")
+{
+  if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+  /* If addi, addis, or paddi can handle the number, don't return true.  */
+  HOST_WIDE_INT value = INTVAL (op);
+  if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+  /* If the number is too large for padds, return false.  */
+  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
+  if ((value & HOST_WIDE_INT_C(0x)) != 0)
+return false;
+
+  return true;
+})
+
+;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
+;; addi/addis/paddi instruction combination.
+(define_predicate "paddis_paddi_operand"
+  (match_code "const_int")
+{
+  if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+  /* If addi, addis, or paddi can handle the number, don't return true.  */
+  HOST_WIDE_INT value = INTVAL (op);
+  if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+  /* If the number is too large for padds, return false.  */
+  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
+  if ((value & HOST_WIDE_INT_C(0x)) == 0)
+return false;
+
+  return true;
+})
+
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1113,7 +1160,10 @@
   (if_then_else (match_code "const_int")
 (match_test "satisfies_constraint_I (op)
 || satisfies_constraint_L (op)
-|| satisfies_constraint_eI (op)")
+|| satisfies_constraint_eI (op)
+|| satisfies_constraint_eU (op)
+|| satisfies_constraint_eV (op)")
+
 (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7ac45d287d0b..650d39895aef 100644
--- a/gcc/con

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2655-Add saturating subtract built-ins.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:56e6cba06a8f626faff300ffef89017977c27928

commit 56e6cba06a8f626faff300ffef89017977c27928
Author: Michael Meissner 
Date:   Tue Oct 22 17:00:35 2024 -0400

RFC2655-Add saturating subtract built-ins.

This patch adds support for a saturating subtract built-in function that 
may be
added to a future PowerPC processor.  Note, if it is added, the name of the
built-in function may change before GCC 13 is released.  If the name 
changes,
we will submit a patch changing the name.

I also added support for providing dense math built-in functions, even 
though
at present, we have not added any new built-in functions for dense math.  
It is
likely we will want to add new dense math built-in functions as the dense 
math
support is fleshed out.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-10-22   Michael Meissner  

gcc/

* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add 
support
for flagging invalid use of future built-in functions.
(rs6000_builtin_is_supported): Add support for future built-in
functions.
* config/rs6000/rs6000-builtins.def 
(__builtin_saturate_subtract32): New
built-in function for -mcpu=future.
(__builtin_saturate_subtract64): Likewise.
* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add 
stanzas
for -mcpu=future built-ins.
(stanza_map): Likewise.
(enable_string): Likewise.
(struct attrinfo): Likewise.
(parse_bif_attrs): Likewise.
(write_decls): Likewise.
* config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
built-in insn declarations.
(sat_sub3_dot): Likewise.
(sat_sub3_dot2): Likewise.
* doc/extend.texi (Future PowerPC built-ins): New section.

gcc/testsuite/

* gcc.target/powerpc/subfus-1.c: New test.
* gcc.target/powerpc/subfus-2.c: Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc | 17 
 gcc/config/rs6000/rs6000-builtins.def   | 10 +
 gcc/config/rs6000/rs6000-gen-builtins.cc| 35 ++---
 gcc/config/rs6000/rs6000.md | 60 +
 gcc/doc/extend.texi | 24 
 gcc/testsuite/gcc.target/powerpc/subfus-1.c | 32 +++
 gcc/testsuite/gcc.target/powerpc/subfus-2.c | 32 +++
 7 files changed, 205 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index ea8755b3ef8a..1885b1f636f3 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,6 +139,17 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
 case ENB_MMA:
   error ("%qs requires the %qs option", name, "-mmma");
   break;
+case ENB_FUTURE:
+  error ("%qs requires the %qs option", name, "-mcpu=future");
+  break;
+case ENB_FUTURE_64:
+  error ("%qs requires the %qs option and either the %qs or %qs option",
+name, "-mcpu=future", "-m64", "-mpowerpc64");
+  break;
+case ENB_DM:
+  error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
+"-mdense-math");
+  break;
 default:
 case ENB_ALWAYS:
   gcc_unreachable ();
@@ -194,6 +205,12 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
   return TARGET_HTM;
 case ENB_MMA:
   return TARGET_MMA;
+case ENB_FUTURE:
+  return TARGET_FUTURE;
+case ENB_FUTURE_64:
+  return TARGET_FUTURE && TARGET_POWERPC64;
+case ENB_DM:
+  return TARGET_DENSE_MATH;
 default:
   gcc_unreachable ();
 }
diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index 555d7d589506..eef5f41f7615 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -137,6 +137,8 @@
 ;   endian   Needs special handling for endianness
 ;   ibmldRestrict usage to the case when TFmode is IBM-128
 ;   ibm128   Restrict usage to the case where __ibm128 is supported or if ibmld
+;   future   Restrict usage to future instructions
+;   dm   Restrict usage to dense math
 ;
 ; Each attribute corresponds to extra processing required when
 ; the built-in is expanded.  All such special processing should
@@ -3924,3 +3926,11 @@
 
   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
 STXVP nothing {mma,pair}
+
+[future]
+  const signed int __builtin_saturate_subtract32 (signed int, signed int);
+  SAT_SUBSI sat_subsi3 {}
+
+[future-64]
+  const signed long __builtin_saturate_subtract64 (signed long,  signed long);
+  SAT_SUBDI sat_subdi3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc 
b/gcc/conf

[gcc(refs/vendors/ibm/heads/mmaplus)] Use vector pair load/store for memcpy with -mcpu=future

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:805a9d9c81d277706cc3a5e3270767d5f101aae6

commit 805a9d9c81d277706cc3a5e3270767d5f101aae6
Author: Michael Meissner 
Date:   Tue Oct 22 16:54:35 2024 -0400

Use vector pair load/store for memcpy with -mcpu=future

In the development for the power10 processor, GCC did not enable using the 
load
vector pair and store vector pair instructions when optimizing things like
memory copy.  This patch enables using those instructions if -mcpu=future is
used.

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable 
using
load vector pair and store vector pair instructions for memory copy
operations.
(POWERPC_MASKS): Make the bit for enabling using load vector pair 
and
store vector pair operations set and reset when the PowerPC 
processor is
changed.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 51d5c39bad5f..23ca24b71b34 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -80,7 +80,8 @@
 
 #define POWER11_MASKS_SERVER   ISA_3_1_MASKS_SERVER
 
-#define FUTURE_MASKS_SERVERPOWER11_MASKS_SERVER
+#define FUTURE_MASKS_SERVER(POWER11_MASKS_SERVER   \
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -110,6 +111,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2656-Support load/store vector with right length.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:8a4e2eb426c73182fc91e5faef8f4d0f0a3f6122

commit 8a4e2eb426c73182fc91e5faef8f4d0f0a3f6122
Author: Michael Meissner 
Date:   Tue Oct 22 16:59:43 2024 -0400

RFC2656-Support load/store vector with right length.

This patch adds support for new instructions that may be added to the 
PowerPC
architecture in the future to enhance the load and store vector with length
instructions.

The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to 
use
since the count for the number of bytes must be in the top 8 bits of the GPR
register, instead of the bottom 8 bits.  This meant that code generating 
these
instructions typically had to do a shift left by 56 bits to get the count 
into
the right position.  In a future version of the PowerPC architecture, new
variants of these instructions might be added that expect the count to be in
the bottom 8 bits of the GPR register.  These patches add this support to 
GCC
if the user uses the -mcpu=future option.

I discovered that the code in rs6000-string.cc to generate ISA 3.1 
lxvl/stxvl
future lxvll/stxvll instructions would generate these instructions on 
32-bit.
However the patterns for these instructions is only done on 64-bit systems. 
 So
I added a check for 64-bit support before generating the instructions.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-10-22   Michael Meissner  

gcc/

* config/rs6000/rs6000-string.cc (expand_block_move): Do not 
generate
lxvl and stxvl on 32-bit.
* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl 
with
the shift count automaticaly used in the insn.
(lxvrl): New insn for -mcpu=future.
(lxvrll): Likewise.
(stxvl): If -mcpu=future, generate the stxvl with the shift count
automaticaly used in the insn.
(stxvrl): New insn for -mcpu=future.
(stxvrll): Likewise.

gcc/testsuite/

* gcc.target/powerpc/lxvrl.c: New test.
* lib/target-supports.exp 
(check_effective_target_powerpc_future_ok):
New effective target.

Diff:
---
 gcc/config/rs6000/rs6000-string.cc   |   1 +
 gcc/config/rs6000/vsx.md | 122 +--
 gcc/testsuite/gcc.target/powerpc/lxvrl.c |  32 
 gcc/testsuite/lib/target-supports.exp|  12 +++
 4 files changed, 146 insertions(+), 21 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index aefd417ccaa0..60ca58c7dfe7 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2786,6 +2786,7 @@ expand_block_move (rtx operands[], bool might_overlap)
 
   if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
  && TARGET_BLOCK_OPS_VECTOR_PAIR
+ && TARGET_POWERPC64
  && bytes >= 32
  && (align >= 256 || !STRICT_ALIGNMENT))
{
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index dd3573b80868..89523cf4a0e5 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5712,20 +5712,32 @@
   DONE;
 })
 
-;; Load VSX Vector with Length
+;; Load VSX Vector with Length.  If we have lxvrl, we don't have to do an
+;; explicit shift left into a pseudo.
 (define_expand "lxvl"
-  [(set (match_dup 3)
-(ashift:DI (match_operand:DI 2 "register_operand")
-   (const_int 56)))
-   (set (match_operand:V16QI 0 "vsx_register_operand")
-   (unspec:V16QI
-[(match_operand:DI 1 "gpc_reg_operand")
-  (mem:V16QI (match_dup 1))
- (match_dup 3)]
-UNSPEC_LXVL))]
+  [(use (match_operand:V16QI 0 "vsx_register_operand"))
+   (use (match_operand:DI 1 "gpc_reg_operand"))
+   (use (match_operand:DI 2 "gpc_reg_operand"))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  operands[3] = gen_reg_rtx (DImode);
+  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
+  rtx len;
+
+  if (TARGET_FUTURE)
+len = shift_len;
+  else
+{
+  len = gen_reg_rtx (DImode);
+  emit_insn (gen_rtx_SET (len, shift_len));
+}
+
+  rtx dest = operands[0];
+  rtx addr = operands[1];
+  rtx mem = gen_rtx_MEM (V16QImode, addr);
+  rtvec rv = gen_rtvec (3, addr, mem, len);
+  rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
+  emit_insn (gen_rtx_SET (dest, lxvl));
+  DONE;
 })
 
 (define_insn "*lxvl"
@@ -5749,6 +5761,34 @@
   "lxvll %x0,%1,%2"
   [(set_attr "type" "vecload")])
 
+;; For lxvrl and lxvrll, use the combiner to eliminate the shift.  The
+;; define_expand for lxvl will already incorporate the shift in generating the
+;; insn.  The lxvll buitl-in function required the user to have already done
+;; the shift.  Defining lxvrll this way, will optimize cases where the user has
+;; done the shift immediately before

[gcc(refs/vendors/ibm/heads/mmaplus)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:253c0abd46d96818f051ca6e7ae81983094abe6a

commit 253c0abd46d96818f051ca6e7ae81983094abe6a
Author: Michael Meissner 
Date:   Tue Oct 22 16:57:05 2024 -0400

RFC2653-PowerPC: Switch to dense math names for all MMA operations.

This patch changes the assembler instruction names for MMA instructions from
the original name used in power10 to the new name when used with the dense 
math
system.  I.e. xvf64gerpp becomes dmxvf64gerpp.  The assembler will emit the
same bits for either spelling.

For the non-prefixed MMA instructions, we add a 'dm' prefix in front of the
instruction.  However, the prefixed instructions have a 'pm' prefix, and we 
add
the 'dm' prefix afterwards.  To prevent having two sets of parallel int
attributes, we remove the "pm" prefix from the instruction string in the
attributes, and add it later, both in the insn name and in the output 
template.

2024-10-22   Michael Meissner  

gcc/

* config/rs6000/mma.md (vvi4i4i8): Change the instruction to not 
have a
"pm" prefix.
(avvi4i4i8): Likewise.
(vvi4i4i2): Likewise.
(avvi4i4i2): Likewise.
(vvi4i4): Likewise.
(avvi4i4): Likewise.
(pvi4i2): Likewise.
(apvi4i2): Likewise.
(vvi4i4i4): Likewise.
(avvi4i4i4): Likewise.
(mma_): Add support for running on DMF systems, generating the 
dense
math instruction and using the dense math accumulators.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_pm): Add support for running on DMF systems, 
generating
the dense math instruction and using the dense math accumulators.
Rename the insn with a 'pm' prefix and add either 'pm' or 'pmdm'
prefixes based on whether we have the original MMA specification or 
if
we have dense math support.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.

Diff:
---
 gcc/config/rs6000/mma.md | 157 +++
 1 file changed, 104 insertions(+), 53 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 683d2398ef90..31040ab1d5ba 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -225,44 +225,47 @@
 (UNSPEC_MMA_XVF64GERNP "xvf64gernp")
 (UNSPEC_MMA_XVF64GERNN "xvf64gernn")])
 
-(define_int_attr vvi4i4i8  [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")])
+;; The "pm" prefix is not in these expansions, so that we can generate
+;; pmdmxvi4ger8 on systems with dense math registers and xvi4ger8 on systems
+;; without dense math registers.
+(define_int_attr vvi4i4i8  [(UNSPEC_MMA_PMXVI4GER8 "xvi4ger8")])
 
-(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP   
"pmxvi4ger8pp")])
+(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP   "xvi4ger8pp")])
 
-(define_int_attr vvi4i4i2  [(UNSPEC_MMA_PMXVI16GER2"pmxvi16ger2")
-(UNSPEC_MMA_PMXVI16GER2S   "pmxvi16ger2s")
-(UNSPEC_MMA_PMXVF16GER2"pmxvf16ger2")
-(UNSPEC_MMA_PMXVBF16GER2   
"pmxvbf16ger2")])
+(define_int_attr vvi4i4i2  [(UNSPEC_MMA_PMXVI16GER2"xvi16ger2")
+(UNSPEC_MMA_PMXVI16GER2S   "xvi16ger2s")
+(UNSPEC_MMA_PMXVF16GER2"xvf16ger2")
+(UNSPEC_MMA_PMXVBF16GER2   "xvbf16ger2")])
 
-(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP  "pmxvi16ger2pp")
-(UNSPEC_MMA_PMXVI16GER2SPP 
"pmxvi16ger2spp")
-(UNSPEC_MMA_PMXVF16GER2PP  "pmxvf16ger2pp")
-(UNSPEC_MMA_PMXVF16GER2PN  "pmxvf16ger2pn")
-(UNSPEC_MMA_PMXVF16GER2NP  "pmxvf16ger2np")
-(UNSPEC_MMA_PMXVF16GER2NN  "pmxvf16ger2nn")
-(UNSPEC_MMA_PMXVBF16GER2PP 
"pmxvbf16ger2pp")
-(UNSPEC_MMA_PMXVBF16GER2PN 
"pmxvbf16ger2pn")
-(UNSPEC_MMA_PMXVBF16GER2NP 
"pmxvbf16ger2np")
-(UNSPEC_MMA_PMXVBF16GER2NN 
"pmxvbf16ger2nn")])
+(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP  "xvi16ger2pp")
+(UNSPEC_MMA_PMXVI16GER2SPP "xvi16ger2spp")
+(UNSPEC_MMA_PMXVF16GER2PP  "xvf16ger2pp")
+(UNSPEC_MMA_PMXVF16GER2PN  "xvf

[gcc(refs/vendors/ibm/heads/mmaplus)] Add rs6000 architecture masks.

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:930ca76e5ab0497a82dbc1ffdb53a370c444b9a0

commit 930ca76e5ab0497a82dbc1ffdb53a370c444b9a0
Author: Michael Meissner 
Date:   Tue Oct 22 16:40:13 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

This patch also changes the target_clones support to use an architecture 
mask
instead of isa bits.

This patch also switches the handling of .machine to use architecture masks 
if
they exist (power4 through power11).  All of the other PowerPCs will 
continue to
use the existing code for setting the .machine option.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-22  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument, 
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks 
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead 
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  48 +
 gcc/config/rs6000/rs6000.cc   | 215 +++---
 gcc/config/rs6000/rs6000.h|  24 +
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 259 insertions(+), 36 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..e5b6e9581331
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,48 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the optio