https://gcc.gnu.org/g:213136a56382d41afbdea35ec59a089552610db4
commit 213136a56382d41afbdea35ec59a089552610db4
Author: Peter Bergner <berg...@linux.ibm.com>
Date: Fri Apr 25 13:19:12 2025 -0500
MMA+: Fix TARGET_DENSE_MATH usage
Diff:
---
gcc/config/rs6000/mma.md | 24 ++++++++++++------------
gcc/config/rs6000/predicates.md | 2 +-
gcc/config/rs6000/rs6000.cc | 24 ++++++++++++------------
gcc/config/rs6000/rs6000.h | 4 +---
4 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index bc6631436274..8c47132e4901 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -352,7 +352,7 @@
(define_insn_and_split "*movxo_nodm"
[(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
(match_operand:XO 1 "input_operand" "ZwO,d,d"))]
- "TARGET_MMA_NO_DENSE_MATH
+ "TARGET_MMA && !TARGET_DENSE_MATH
&& (gpc_reg_operand (operands[0], XOmode)
|| gpc_reg_operand (operands[1], XOmode))"
"@
@@ -372,7 +372,7 @@
(define_insn_and_split "*movxo_dm"
[(set (match_operand:XO 0 "nonimmediate_operand" "=wa,ZwO,wa,wD,wD,wa")
(match_operand:XO 1 "input_operand" "ZwO,wa, wa,wa,wD,wD"))]
- "TARGET_MMA_DENSE_MATH
+ "TARGET_DENSE_MATH
&& (gpc_reg_operand (operands[0], XOmode)
|| gpc_reg_operand (operands[1], XOmode))"
"@
@@ -502,7 +502,7 @@
[(set (match_operand:XO 0 "accumulator_operand" "=&wD")
(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
MMA_ACC))]
- "TARGET_MMA_NO_DENSE_MATH"
+ "TARGET_MMA && !TARGET_DENSE_MATH"
"<acc> %A0"
[(set_attr "type" "mma")])
@@ -527,7 +527,7 @@
[(set (match_operand:XO 0 "fpr_reg_operand" "=d")
(unspec_volatile:XO [(const_int 0)]
UNSPECV_MMA_XXSETACCZ))]
- "TARGET_MMA_NO_DENSE_MATH"
+ "TARGET_MMA && !TARGET_DENSE_MATH"
"xxsetaccz %A0"
[(set_attr "type" "mma")])
@@ -535,7 +535,7 @@
[(set (match_operand:XO 0 "accumulator_operand" "=wD")
(unspec [(const_int 0)]
UNSPEC_MMA_DMSETDMRZ))]
- "TARGET_MMA_DENSE_MATH"
+ "TARGET_DENSE_MATH"
"dmsetdmrz %A0"
[(set_attr "type" "mma")])
@@ -760,7 +760,7 @@
(define_expand "movtdo"
[(set (match_operand:TDO 0 "nonimmediate_operand")
(match_operand:TDO 1 "input_operand"))]
- "TARGET_MMA_DENSE_MATH"
+ "TARGET_DENSE_MATH"
{
rs6000_emit_move (operands[0], operands[1], TDOmode);
DONE;
@@ -769,7 +769,7 @@
(define_insn_and_split "*movtdo"
[(set (match_operand:TDO 0 "nonimmediate_operand" "=wa,m,wa,wD,wD,wa")
(match_operand:TDO 1 "input_operand" "m,wa,wa,wa,wD,wD"))]
- "TARGET_MMA_DENSE_MATH
+ "TARGET_DENSE_MATH
&& (gpc_reg_operand (operands[0], TDOmode)
|| gpc_reg_operand (operands[1], TDOmode))"
"@
@@ -826,7 +826,7 @@
[(set (match_operand:TDO 0 "dmr_operand" "=wD")
(unspec:TDO [(match_operand:XO 1 "vsx_register_operand" "wa")]
UNSPEC_DM_INSERT512_UPPER))]
- "TARGET_MMA_DENSE_MATH"
+ "TARGET_DENSE_MATH"
"dmxxinstdmr512 %0,%1,%Y1,0"
[(set_attr "type" "mma")])
@@ -835,7 +835,7 @@
(unspec:TDO [(match_operand:TDO 1 "dmr_operand" "0")
(match_operand:XO 2 "vsx_register_operand" "wa")]
UNSPEC_DM_INSERT512_LOWER))]
- "TARGET_MMA_DENSE_MATH"
+ "TARGET_DENSE_MATH"
"dmxxinstdmr512 %0,%2,%Y2,1"
[(set_attr "type" "mma")])
@@ -846,7 +846,7 @@
(unspec:XO [(match_operand:TDO 1 "dmr_operand" "wD")
(match_operand 2 "const_0_to_1_operand" "n")]
UNSPEC_DM_EXTRACT512))]
- "TARGET_MMA_DENSE_MATH"
+ "TARGET_DENSE_MATH"
"dmxxextfdmr512 %0,%Y0,%1,%2"
[(set_attr "type" "mma")])
@@ -856,7 +856,7 @@
(unspec:TDO [(match_operand:TDO 1 "memory_operand" "m")]
UNSPEC_DMR_RELOAD_FROM_MEMORY))
(clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))]
- "TARGET_MMA_DENSE_MATH"
+ "TARGET_DENSE_MATH"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -884,7 +884,7 @@
(unspec:TDO [(match_operand:TDO 1 "dmr_operand" "wD")]
UNSPEC_DMR_RELOAD_TO_MEMORY))
(clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))]
- "TARGET_MMA_DENSE_MATH"
+ "TARGET_DENSE_MATH"
"#"
"&& reload_completed"
[(const_int 0)]
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index c95b4336f062..7086a518ab4d 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -213,7 +213,7 @@
return 1;
int r = REGNO (op);
- return (TARGET_MMA_DENSE_MATH
+ return (TARGET_DENSE_MATH
? DMR_REGNO_P (r)
: FP_REGNO_P (r) && (r & 3) == 0);
})
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7ac45d287d0b..73eda16af415 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -13618,7 +13618,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class
rclass)
return VSX_REGS;
if (mode == XOmode)
- return TARGET_MMA_DENSE_MATH ? VSX_REGS : FLOAT_REGS;
+ return TARGET_DENSE_MATH ? VSX_REGS : FLOAT_REGS;
if (mode == TDOmode)
return VSX_REGS;
@@ -13748,7 +13748,7 @@ rs6000_secondary_reload_class (enum reg_class rclass,
machine_mode mode,
/* DMR registers don't have loads or stores. We have to go through the VSX
registers to load XOmode (vector quad). */
- if (TARGET_MMA_DENSE_MATH && rclass == DM_REGS)
+ if (TARGET_DENSE_MATH && rclass == DM_REGS)
return VSX_REGS;
/* If we have VSX register moves, prefer moving scalar values between
@@ -14287,7 +14287,7 @@ print_operand (FILE *file, rtx x, int code)
overlapping with the FPR registers. */
if (!REG_P (x))
output_operand_lossage ("invalid %%A value");
- else if (TARGET_MMA_DENSE_MATH)
+ else if (TARGET_DENSE_MATH)
{
if (DMR_REGNO_P (REGNO (x)))
fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO);
@@ -22933,7 +22933,7 @@ rs6000_dmr_register_move_cost (machine_mode mode,
reg_class_t rclass)
HARD_REG_SET vsx_set = (reg_class_contents[rclass]
& reg_class_contents[VSX_REGS]);
- if (TARGET_MMA_DENSE_MATH && !hard_reg_set_empty_p (vsx_set))
+ if (TARGET_DENSE_MATH && !hard_reg_set_empty_p (vsx_set))
{
/* __vector_quad (i.e. XOmode) is tranfered in 1 instruction. */
if (mode == XOmode)
@@ -24292,7 +24292,7 @@ rs6000_compute_pressure_classes (enum reg_class
*pressure_classes)
if (TARGET_HARD_FLOAT)
pressure_classes[n++] = FLOAT_REGS;
}
- if (TARGET_MMA_DENSE_MATH)
+ if (TARGET_DENSE_MATH)
pressure_classes[n++] = DM_REGS;
pressure_classes[n++] = CR_REGS;
pressure_classes[n++] = SPECIAL_REGS;
@@ -27857,7 +27857,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are reading an accumulator register, we have to deprime it
before we can access it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH
+ if (TARGET_MMA && !TARGET_DENSE_MATH
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -27891,7 +27891,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are writing an accumulator register, we have to prime it
after we've written it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH
+ if (TARGET_MMA && !TARGET_DENSE_MATH
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
@@ -27905,7 +27905,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
|| XINT (src, 1) == UNSPECV_MMA_ASSEMBLE);
gcc_assert (REG_P (dst));
if (GET_MODE (src) == XOmode)
- gcc_assert ((TARGET_MMA_DENSE_MATH
+ gcc_assert ((TARGET_DENSE_MATH
? VSX_REGNO_P (REGNO (dst))
: FP_REGNO_P (REGNO (dst))));
if (GET_MODE (src) == OOmode)
@@ -27975,7 +27975,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
{
/* If we are reading an accumulator register, we have to deprime it
before we can access it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH
+ if (TARGET_MMA && !TARGET_DENSE_MATH
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -28003,7 +28003,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are writing an accumulator register, we have to prime it after
we've written it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH
+ if (TARGET_MMA && !TARGET_DENSE_MATH
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
}
@@ -28140,7 +28140,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are reading an accumulator register, we have to deprime it
before we can access it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH && REG_P (src)
+ if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (src)
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -28172,7 +28172,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are writing an accumulator register, we have to prime it after
we've written it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH && REG_P (dst)
+ if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (dst)
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3b386ad0ef33..9fb008a9b9fa 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -575,9 +575,7 @@ extern int rs6000_vector_align[];
/* Whether we have dense math support. At present, we don't have a dense math
ISA bit, just use the future bit set by -mcpu=future. */
-#define TARGET_DENSE_MATH TARGET_FUTURE
-#define TARGET_MMA_DENSE_MATH (TARGET_MMA && TARGET_DENSE_MATH)
-#define TARGET_MMA_NO_DENSE_MATH (TARGET_MMA && !TARGET_DENSE_MATH)
+#define TARGET_DENSE_MATH (TARGET_FUTURE && TARGET_MMA)
/* Inlining allows targets to define the meanings of bits in target_info
field of ipa_fn_summary by itself, the used bits for rs6000 are listed
