[gcc r15-9481] tailc: Fix up musttail calls vs. -fsanitize=thread [PR119801]
https://gcc.gnu.org/g:07565115371ea5cdf9e6d75ea3777540d1d31bda
commit r15-9481-g07565115371ea5cdf9e6d75ea3777540d1d31bda
Author: Jakub Jelinek
Date: Tue Apr 15 14:09:55 2025 +0200
tailc: Fix up musttail calls vs. -fsanitize=thread [PR119801]
Calls with musttail attribute don't really work with -fsanitize=thread in
GCC. The problem is that TSan instrumentation adds
__tsan_func_entry (__builtin_return_address (0));
calls at the start of each instrumented function and
__tsan_func_exit ();
call at the end of those and the latter stands in a way of normal tail calls
as well as musttail tail calls.
Looking at what LLVM does, for normal calls -fsanitize=thread also prevents
tail calls like in GCC (well, the __tsan_func_exit () call itself can be
tail called in GCC (and from what I see not in clang)).
But for [[clang::musttail]] calls it arranges to move the
__tsan_func_exit () before the musttail call instead of after it.
The following patch handles it similarly. If we for -fsanitize=thread
instrumented function detect __builtin_tsan_func_exit () call, we process
it normally (so that the call can be tail called in function returning void)
but set a flag that the builtin has been seen (only for cfun->has_musttail
in the diag_musttail phase). And then let tree_optimize_tail_calls_1
call find_tail_calls again in a new mode where the __tsan_func_exit ()
call is ignored and so we are able to find calls before it, but only
accept that if the call before it is actually a musttail. For C++ it needs
to verify that EH cleanup if any also has the __tsan_func_exit () call
and if all goes well, the musttail call is registered for tailcalling with
a flag that it has __tsan_func_exit () after it and when optimizing that
we emit __tsan_func_exit (); call before the musttail tail call (or musttail
tail recursion).
2025-04-15 Jakub Jelinek
PR sanitizer/119801
* sanitizer.def (BUILT_IN_TSAN_FUNC_EXIT): Use BT_FN_VOID rather
than BT_FN_VOID_PTR.
* tree-tailcall.cc: Include attribs.h and asan.h.
(struct tailcall): Add has_tsan_func_exit member.
(empty_eh_cleanup): Add eh_has_tsan_func_exit argument, set what
it points to to 1 if there is exactly one __tsan_func_exit call
and ignore that call otherwise. Adjust recursive call.
(find_tail_calls): Add RETRY_TSAN_FUNC_EXIT argument, pass it
to recursive calls. When seeing __tsan_func_exit call with
RETRY_TSAN_FUNC_EXIT 0, set it to -1. If RETRY_TSAN_FUNC_EXIT
is 1, initially ignore __tsan_func_exit calls. Adjust
empty_eh_cleanup caller. When looking through stmts after the call,
ignore exactly one __tsan_func_exit call but remember it in
t->has_tsan_func_exit. Diagnose if EH cleanups didn't have
__tsan_func_exit and normal path did or vice versa.
(optimize_tail_call): Emit __tsan_func_exit before the tail call
or tail recursion.
(tree_optimize_tail_calls_1): Adjust find_tail_calls callers. If
find_tail_calls changes retry_tsan_func_exit to -1, set it to 1
and call it again with otherwise the same arguments.
* c-c++-common/tsan/pr119801.c: New test.
Diff:
---
gcc/sanitizer.def | 2 +-
gcc/testsuite/c-c++-common/tsan/pr119801.c | 24 +++
gcc/tree-tailcall.cc | 103 ++---
3 files changed, 118 insertions(+), 11 deletions(-)
diff --git a/gcc/sanitizer.def b/gcc/sanitizer.def
index 4b7c9dc41e42..c5a9c2dea407 100644
--- a/gcc/sanitizer.def
+++ b/gcc/sanitizer.def
@@ -247,7 +247,7 @@ DEF_SANITIZER_BUILTIN(BUILT_IN_TSAN_INIT, "__tsan_init",
DEF_SANITIZER_BUILTIN(BUILT_IN_TSAN_FUNC_ENTRY, "__tsan_func_entry",
BT_FN_VOID_PTR, ATTR_NOTHROW_LEAF_LIST)
DEF_SANITIZER_BUILTIN(BUILT_IN_TSAN_FUNC_EXIT, "__tsan_func_exit",
- BT_FN_VOID_PTR, ATTR_NOTHROW_LEAF_LIST)
+ BT_FN_VOID, ATTR_NOTHROW_LEAF_LIST)
DEF_SANITIZER_BUILTIN(BUILT_IN_TSAN_VPTR_UPDATE, "__tsan_vptr_update",
BT_FN_VOID_PTR_PTR, ATTR_NOTHROW_LEAF_LIST)
DEF_SANITIZER_BUILTIN(BUILT_IN_TSAN_READ1, "__tsan_read1",
diff --git a/gcc/testsuite/c-c++-common/tsan/pr119801.c
b/gcc/testsuite/c-c++-common/tsan/pr119801.c
new file mode 100644
index ..d3a6bb4549ef
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/tsan/pr119801.c
@@ -0,0 +1,24 @@
+/* PR sanitizer/119801 */
+/* { dg-do compile } */
+/* { dg-options "-fsanitize=thread" } */
+
+[[gnu::noipa]] int
+bar (int *p)
+{
+ return ++*p;
+}
+
+int
+foo (int *p)
+{
+ ++*p;
+ [[gnu::musttail]] return bar (p);
+}
+
+[[gnu::noinline]] int
+baz (int x)
+{
+ if (x < 10)
+return x;
+ [[gnu::musttail]] return baz
[gcc r15-9482] ipa-cp: Fix up ipcp_print_widest_int
https://gcc.gnu.org/g:bf115fd45772de34cd24de02c41fdb175897f057
commit r15-9482-gbf115fd45772de34cd24de02c41fdb175897f057
Author: Jakub Jelinek
Date: Tue Apr 15 14:56:30 2025 +0200
ipa-cp: Fix up ipcp_print_widest_int
On Mon, Mar 31, 2025 at 03:34:07PM +0200, Martin Jambor wrote:
> This patch just introduces a form of dumping of widest ints that only
> have zeros in the lowest 128 bits so that instead of printing
> thousands of f's the output looks like:
>
>Bits: value = 0x, mask = all ones folled by
0x
>
> and then makes sure we use the function not only to print bits but
> also to print masks where values like these can also occur.
Shouldn't that be followed by instead?
And the widest_int checks seems to be quite expensive (especially for
large widest_ints), I think for the first one we can just == -1
and for the second one wi::arshift (value, 128) == -1 and the zero extension
by using wi::zext.
Anyway, I wonder if it wouldn't be better to use something shorter,
the variant patch uses 0xf..f prefix before the 128-bit hexadecimal
number (maybe we could also special case the even more common bits 64+
are all ones case). Or it could be 0xf*f prefix. Or printing such
numbers as -0x prefixed negative, though that is not a good idea for masks.
This version doesn't print e.g.
0xf..f
but just
0xf..f
(of course, for say mask of
0xf..f
it prints it like that, doesn't try to shorten the 0 digits.
But if the most significant bits aren't set, it will be just
0x.
2025-04-15 Jakub Jelinek
* ipa-cp.cc (ipcp_print_widest_int): Print values with all ones in
bits 128+ with "0xf..f" prefix instead of "all ones folled by ".
Simplify wide_int check for -1 or all ones above least significant
128 bits.
Diff:
---
gcc/ipa-cp.cc | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/gcc/ipa-cp.cc b/gcc/ipa-cp.cc
index 26b1496f29bb..379fbc5dd637 100644
--- a/gcc/ipa-cp.cc
+++ b/gcc/ipa-cp.cc
@@ -313,14 +313,24 @@ ipcp_lattice::print (FILE * f, bool
dump_sources, bool dump_benefits)
static void
ipcp_print_widest_int (FILE *f, const widest_int &value)
{
- if (wi::eq_p (wi::bit_not (value), 0))
+ if (value == -1)
fprintf (f, "-1");
- else if (wi::eq_p (wi::bit_not (wi::bit_or (value,
- wi::sub (wi::lshift (1, 128),
- 1))), 0))
-{
- fprintf (f, "all ones folled by ");
- print_hex (wi::bit_and (value, wi::sub (wi::lshift (1, 128), 1)), f);
+ else if (wi::arshift (value, 128) == -1)
+{
+ char buf[35], *p = buf + 2;
+ widest_int v = wi::zext (value, 128);
+ size_t len;
+ print_hex (v, buf);
+ len = strlen (p);
+ if (len == 32)
+ {
+ fprintf (f, "0xf..f");
+ while (*p == 'f')
+ ++p;
+ }
+ else
+ fprintf (f, "0xf..f%0*d", (int) (32 - len), 0);
+ fputs (p, f);
}
else
print_hex (value, f);
[gcc r15-9484] c++: prev declared hidden tmpl friend inst, cont [PR119807]
https://gcc.gnu.org/g:369461d0749790f1291f76096064d583d2547934
commit r15-9484-g369461d0749790f1291f76096064d583d2547934
Author: Patrick Palka
Date: Tue Apr 15 09:06:40 2025 -0400
c++: prev declared hidden tmpl friend inst, cont [PR119807]
When remapping existing specializations of a hidden template friend from
a previous declaration to the new definition, we must remap only those
specializations that match this new definition, but currently we
remap all specializations (since they all appear in the same
DECL_TEMPLATE_INSTANTIATIONS list of the most general template).
Concretely, in the first testcase below, we form two specializations of
the friend A::f, one with arguments {{0},{bool}} and another with
arguments {{1},{bool}}. Later when instantiating B, we need to remap
these specializations. During the B<0> instantiation we only want to
remap the first specialization, and during the B<1> instantiation only
the second specialization, but currently we remap both specializations
twice.
tsubst_friend_function needs to determine if an existing specialization
matches the shape of the new definition, which is tricky in general,
e.g. if the outer template parameters may not match up. Fortunately we
don't have to reinvent the wheel here since is_specialization_of_friend
seems to do exactly what we need. We can check this unconditionally,
but I think it's only necessary when dealing with specializations formed
from a class template scope previous declaration, hence the
TMPL_ARGS_HAVE_MULTIPLE_LEVELS check.
PR c++/119807
PR c++/112288
gcc/cp/ChangeLog:
* pt.cc (tsubst_friend_function): Skip remapping an
existing specialization if it doesn't match the shape of
the new friend definition.
gcc/testsuite/ChangeLog:
* g++.dg/template/friend86.C: New test.
* g++.dg/template/friend87.C: New test.
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/pt.cc | 4 +++
gcc/testsuite/g++.dg/template/friend86.C | 25 +++
gcc/testsuite/g++.dg/template/friend87.C | 42
3 files changed, 71 insertions(+)
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index b7060b4c5aa6..4349b19119b7 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -11772,6 +11772,10 @@ tsubst_friend_function (tree decl, tree args)
elt.args = DECL_TI_ARGS (spec);
elt.spec = NULL_TREE;
+ if (TMPL_ARGS_HAVE_MULTIPLE_LEVELS (DECL_TI_ARGS (spec))
+ && !is_specialization_of_friend (spec, new_template))
+ continue;
+
decl_specializations->remove_elt (&elt);
tree& spec_args = DECL_TI_ARGS (spec);
diff --git a/gcc/testsuite/g++.dg/template/friend86.C
b/gcc/testsuite/g++.dg/template/friend86.C
new file mode 100644
index ..9e2c1afb351c
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/friend86.C
@@ -0,0 +1,25 @@
+// PR c++/119807
+// { dg-do run }
+
+template
+struct A {
+ template friend int f(A, T);
+};
+
+template struct A<0>;
+template struct A<1>;
+
+int main() {
+ A<0> x;
+ A<1> y;
+ if (f(x, true) != 0) __builtin_abort();
+ if (f(y, true) != 1) __builtin_abort();
+}
+
+template
+struct B {
+ template friend int f(A, T) { return N; }
+};
+
+template struct B<0>;
+template struct B<1>;
diff --git a/gcc/testsuite/g++.dg/template/friend87.C
b/gcc/testsuite/g++.dg/template/friend87.C
new file mode 100644
index ..94c0dfc52924
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/friend87.C
@@ -0,0 +1,42 @@
+// PR c++/119807
+// { dg-do compile { target c++20 } }
+
+using size_t = decltype(sizeof(0));
+
+template
+struct CounterReader {
+ template
+ friend auto counterFlag(CounterReader) noexcept;
+};
+
+template
+struct CounterWriter {
+ static constexpr size_t value = current;
+
+ template
+ friend auto counterFlag(CounterReader) noexcept {}
+};
+
+template
+[[nodiscard]] constexpr size_t counterAdvance() noexcept {
+ if constexpr (!mask) {
+ return CounterWriter::value;
+ } else if constexpr (requires { counterFlag(CounterReader()); }) {
+ return counterAdvance>
1)>();
+ }
+ else {
+ return counterAdvance> 1)>();
+ }
+}
+
+constexpr auto defaultCounterTag = [] {};
+
+template
+constexpr size_t counter() noexcept {
+ return counterAdvance();
+}
+
+int main() {
+ static_assert(counter() == 1);
+ static_assert(counter() == 2);
+}
[gcc r15-9480] Wbuiltin-declaration-mismatch-4.c: accept long long in warning for llp64
https://gcc.gnu.org/g:039b566f2f03699676d31b681d1595bddc94a774
commit r15-9480-g039b566f2f03699676d31b681d1595bddc94a774
Author: Jonathan Yong <10wa...@gmail.com>
Date: Sun Apr 13 02:41:36 2025 +
Wbuiltin-declaration-mismatch-4.c: accept long long in warning for llp64
llp64 targets like mingw-w64 will print:
gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-4.c:80:17: warning:
‘memset’ argument 3 promotes to ‘ptrdiff_t’ {aka ‘long long int’} where ‘long
long unsigned int’ is expected in a call to built-in function declared without
prototype [-
Wbuiltin-declaration-mismatch]
Change the regex pattern to accept it.
Signed-off-by: Jonathan Yong <10wa...@gmail.com>
gcc/testsuite/ChangeLog:
* gcc.dg/Wbuiltin-declaration-mismatch-4.c: Make diagnostic
accept long long.
Diff:
---
gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-4.c
b/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-4.c
index c48fe5fcf300..09665b49 100644
--- a/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-4.c
+++ b/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-4.c
@@ -77,9 +77,9 @@ void test_integer_conversion_memset (void *d)
/* Passing a ptrdiff_t where size_t is expected may not be unsafe
but because GCC may emits suboptimal code for such calls warning
for them helps improve efficiency. */
- memset (d, 0, diffi); /* { dg-warning ".memset. argument 3 promotes to
.ptrdiff_t. {aka .\(long \)?\(int\)?\(__int20\)?.} where .\(long \)?\(__int20
\)?unsigned\( int\)?. is expected" } */
+ memset (d, 0, diffi); /* { dg-warning ".memset. argument 3 promotes to
.ptrdiff_t. {aka .\(long \)*\(int\)?\(__int20\)?.} where .\(long \)*\(__int20
\)?unsigned\( int\)?. is expected" } */
- memset (d, 0, 2.0); /* { dg-warning ".memset. argument 3 type is
.double. where '\(long \)?\(__int20 \)?unsigned\( int\)?' is expected" } */
+ memset (d, 0, 2.0); /* { dg-warning ".memset. argument 3 type is
.double. where '\(long \)*\(__int20 \)?unsigned\( int\)?' is expected" } */
/* Verify that the same call as above but to the built-in doesn't
trigger a warning. */
[gcc r15-9486] ipa-bit-cp: Fix adjusting value according to mask (PR119803)
https://gcc.gnu.org/g:b4cf69503bcb32491dbd7ab63fe7f0f9fcdcca38
commit r15-9486-gb4cf69503bcb32491dbd7ab63fe7f0f9fcdcca38
Author: Martin Jambor
Date: Tue Apr 15 15:55:34 2025 +0200
ipa-bit-cp: Fix adjusting value according to mask (PR119803)
In my fix for PR 119318 I put mask calculation in
ipcp_bits_lattice::meet_with_1 above a final fix to value so that all
the bits in the value which are meaningless according to mask have
value zero, which has tripped a validator in PR 119803. This patch
fixes that by moving the adjustment down.
Even thought the fix for PR 119318 did a similar thing in
ipcp_bits_lattice::meet_with, the same is not necessary because that
code path then feeds the new value and mask to
ipcp_bits_lattice::set_to_constant which does the final adjustment
correctly.
In both places, however, Jakup proposed a better way of calculating
cap_mask and so I have changed it accordingly.
gcc/ChangeLog:
2025-04-15 Martin Jambor
PR ipa/119803
* ipa-cp.cc (ipcp_bits_lattice::meet_with_1): Move m_value adjustmed
according to m_mask below the adjustment of the latter according to
cap_mask. Optimize the calculation of cap_mask a bit.
(ipcp_bits_lattice::meet_with): Optimize the calculation of
cap_mask a
bit.
gcc/testsuite/ChangeLog:
2025-04-15 Martin Jambor
PR ipa/119803
* gcc.dg/ipa/pr119803.c: New test.
Co-authored-by: Jakub Jelinek
Diff:
---
gcc/ipa-cp.cc | 6 +++---
gcc/testsuite/gcc.dg/ipa/pr119803.c | 16
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/gcc/ipa-cp.cc b/gcc/ipa-cp.cc
index 379fbc5dd637..806c2bdc97f2 100644
--- a/gcc/ipa-cp.cc
+++ b/gcc/ipa-cp.cc
@@ -933,13 +933,13 @@ ipcp_bits_lattice::meet_with_1 (widest_int value,
widest_int mask,
m_mask = (m_mask | mask) | (m_value ^ value);
if (drop_all_ones)
m_mask |= m_value;
- m_value &= ~m_mask;
- widest_int cap_mask = wi::bit_not (wi::sub (wi::lshift (1, precision), 1));
+ widest_int cap_mask = wi::shifted_mask (0, precision, true);
m_mask |= cap_mask;
if (wi::sext (m_mask, precision) == -1)
return set_to_bottom ();
+ m_value &= ~m_mask;
return m_mask != old_mask;
}
@@ -1015,7 +1015,7 @@ ipcp_bits_lattice::meet_with (ipcp_bits_lattice& other,
unsigned precision,
adjusted_mask |= adjusted_value;
adjusted_value &= ~adjusted_mask;
}
- widest_int cap_mask = wi::bit_not (wi::sub (wi::lshift (1, precision),
1));
+ widest_int cap_mask = wi::shifted_mask (0, precision, true);
adjusted_mask |= cap_mask;
if (wi::sext (adjusted_mask, precision) == -1)
return set_to_bottom ();
diff --git a/gcc/testsuite/gcc.dg/ipa/pr119803.c
b/gcc/testsuite/gcc.dg/ipa/pr119803.c
new file mode 100644
index ..1a7bfd25018a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ipa/pr119803.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern void f(int p);
+int a, b;
+char c;
+static int d(int e) { return !e || a == 1 ? 0 : a / e; }
+static void h(short e) {
+ int g = d(e);
+ f(g);
+}
+void i() {
+ c = 128;
+ h(c);
+ b = d(65536);
+}
[gcc r14-11616] c++: wrong targs in satisfaction diagnostic context line [PR99214]
https://gcc.gnu.org/g:3dc43f7f4394f8705090232e3506e1e94f484877
commit r14-11616-g3dc43f7f4394f8705090232e3506e1e94f484877
Author: Patrick Palka
Date: Mon Apr 14 11:20:13 2025 -0400
c++: wrong targs in satisfaction diagnostic context line [PR99214]
In the three-parameter version of satisfy_declaration_constraints, when
't' isn't the most general template, then 't' won't correspond with
'args' after we augment the latter via add_outermost_template_args, and
so the instantiation context that we push via push_tinst_level isn't
quite correct: 'args' is a complete set of template arguments, but 't'
is not necessarily the most general template. This manifests as
misleading diagnostic context lines when issuing a satisfaction failure
error, e.g. the below testcase without this patch we emit:
In substitution of '... void A::f() ... [with U = int]'
and with this patch we emit:
In substitution of '... void A::f() ... [with U = char]'.
This patch fixes this by passing the original 'args' to push_tinst_level,
which ought to properly correspond to 't'.
PR c++/99214
gcc/cp/ChangeLog:
* constraint.cc (satisfy_declaration_constraints): Pass the
original ARGS to push_tinst_level.
gcc/testsuite/ChangeLog:
* g++.dg/concepts/diagnostic20.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit 00966a7fdb1478b3af5254ff3a80a3ef336c5a94)
Diff:
---
gcc/cp/constraint.cc | 4 +++-
gcc/testsuite/g++.dg/concepts/diagnostic20.C | 13 +
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index 215a6c1fa938..4b6dc181d93d 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3359,6 +3359,8 @@ satisfy_declaration_constraints (tree t, sat_info info)
static tree
satisfy_declaration_constraints (tree t, tree args, sat_info info)
{
+ tree orig_args = args;
+
/* Update the declaration for diagnostics. */
info.in_decl = t;
@@ -3387,7 +3389,7 @@ satisfy_declaration_constraints (tree t, tree args,
sat_info info)
tree result = boolean_true_node;
if (tree norm = get_normalized_constraints_from_decl (t, info.noisy ()))
{
- if (!push_tinst_level (t, args))
+ if (!push_tinst_level (t, orig_args))
return result;
tree pattern = DECL_TEMPLATE_RESULT (t);
push_to_top_level ();
diff --git a/gcc/testsuite/g++.dg/concepts/diagnostic20.C
b/gcc/testsuite/g++.dg/concepts/diagnostic20.C
new file mode 100644
index ..2bb01db44dec
--- /dev/null
+++ b/gcc/testsuite/g++.dg/concepts/diagnostic20.C
@@ -0,0 +1,13 @@
+// PR c++/99214
+// { dg-do compile { target c++20 } }
+
+template
+struct A {
+ template static void f() requires requires { T::fail; };
+};
+
+int main() {
+ A::f(); // { dg-error "no match" }
+}
+
+// { dg-message "In substitution of '\[^\r\n\]* \\\[with U = char\\\]'" "" {
target *-*-* } 0 }
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Corrections ISO_Fortran_binding_18.f90
https://gcc.gnu.org/g:390ef6679cce82dc7636c031fa0e9bf6a9ff3c57
commit 390ef6679cce82dc7636c031fa0e9bf6a9ff3c57
Author: Mikael Morin
Date: Mon Apr 14 20:38:41 2025 +0200
Corrections ISO_Fortran_binding_18.f90
Diff:
---
gcc/fortran/trans-array.cc | 13 -
gcc/fortran/trans.cc | 17 +++--
gcc/fortran/trans.h| 6 --
3 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 8cd7de71fe4a..fe77af2e14e2 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -3487,7 +3487,8 @@ build_ptr_array_ref (tree data, tree offset)
tree
-build_array_ref_dim (gfc_ss *ss, tree index, tree spacing, bool tmp_array =
false)
+build_array_ref_dim (gfc_ss *ss, tree index, tree spacing,
+tree offset = NULL_TREE, bool tmp_array = false)
{
gfc_array_info *info = &ss->info->data.array;
@@ -3499,8 +3500,10 @@ build_array_ref_dim (gfc_ss *ss, tree index, tree
spacing, bool tmp_array = fals
|| ss_type == GFC_SS_INTRINSIC
|| tmp_array
|| non_negative_strides_array_p (info->descriptor);
- return gfc_build_array_ref (base, index, non_negative_stride,
- NULL_TREE, spacing);
+ return gfc_build_array_ref (base, index,
+ non_negative_stride
+ && (!offset || integer_zerop (offset)),
+ NULL_TREE, spacing, offset);
}
@@ -3520,8 +3523,8 @@ gfc_conv_scalarized_array_ref (gfc_se * se, gfc_array_ref
* ar, bool tmp_array =
tree index = conv_array_index (se, ss, ss->dim[n], n, ar);
- se->expr = build_array_ref_dim (ss, index,
- ss->info->data.array.spacing0,
+ gfc_array_info *info = &ss->info->data.array;
+ se->expr = build_array_ref_dim (ss, index, info->spacing0, info->offset,
tmp_array);
}
diff --git a/gcc/fortran/trans.cc b/gcc/fortran/trans.cc
index c59ebbdaf7bd..c2aae309b081 100644
--- a/gcc/fortran/trans.cc
+++ b/gcc/fortran/trans.cc
@@ -407,13 +407,13 @@ gfc_build_spanned_array_ref (tree base, tree offset, tree
span)
/* Build an ARRAY_REF with its natural type.
- NON_NEGATIVE_OFFSET indicates if it’s true that OFFSET can’t be negative,
+ NON_NEGATIVE_SPACING indicates if it’s true that SPACING can’t be negative,
and thus that an ARRAY_REF can safely be generated. If it’s false, we
have to play it safe and use pointer arithmetic. */
tree
gfc_build_array_ref (tree type, tree base, tree index, bool
non_negative_offset,
-tree min_val, tree spacing)
+tree min_idx, tree spacing, tree offset)
{
if (DECL_P (base))
TREE_ADDRESSABLE (base) = 1;
@@ -423,12 +423,12 @@ gfc_build_array_ref (tree type, tree base, tree index,
bool non_negative_offset,
if (non_negative_offset)
return build4_loc (input_location, ARRAY_REF, type, base, index,
- min_val, spacing);
+ min_idx, spacing);
/* Otherwise use pointer arithmetic. */
else
{
gcc_assert (TREE_CODE (TREE_TYPE (base)) == ARRAY_TYPE);
- tree min = min_val;
+ tree min = min_idx;
if (min == NULL_TREE
&& TYPE_DOMAIN (TREE_TYPE (base)))
min = TYPE_MIN_VALUE (TYPE_DOMAIN (TREE_TYPE (base)));
@@ -449,6 +449,11 @@ gfc_build_array_ref (tree type, tree base, tree index,
bool non_negative_offset,
tree offset_bytes = fold_build2_loc (input_location, MULT_EXPR,
gfc_array_index_type,
zero_based_index, delta);
+ if (offset && !integer_zerop (offset))
+ offset_bytes = fold_build2_loc (input_location, PLUS_EXPR,
+ gfc_array_index_type,
+ offset_bytes, offset);
+
offset_bytes = fold_convert_loc (input_location, sizetype,
offset_bytes);
@@ -464,7 +469,7 @@ gfc_build_array_ref (tree type, tree base, tree index, bool
non_negative_offset,
tree
gfc_build_array_ref (tree base, tree index, bool non_negative_offset,
-tree offset, tree spacing)
+tree min_idx, tree spacing, tree offset)
{
tree type = TREE_TYPE (base);
@@ -483,7 +488,7 @@ gfc_build_array_ref (tree base, tree index, bool
non_negative_offset,
}
return gfc_build_array_ref (TREE_TYPE (type), base, index,
non_negative_offset,
- offset, spacing);
+ min_idx, spacing, offset);
}
diff --git a/gcc/fortran/trans.h b/gcc/fortran/trans.h
index 72f9b82098e3..a232254fd63f 100644
--- a/gcc/fortran/trans.h
+++ b/gcc/fortran/trans.h
@@ -646,9 +646,11 @@ tree gfc_build_addr_expr (tree, tree);
/* Build an ARRAY_REF.
[gcc r14-11619] RISC-V: adjust testcase for gcc-14 [PR118182]
https://gcc.gnu.org/g:b7b1aeea684a8191d1503b4022cea8d0d218ca65 commit r14-11619-gb7b1aeea684a8191d1503b4022cea8d0d218ca65 Author: Alexandre Oliva Date: Wed Apr 16 01:10:53 2025 -0300 RISC-V: adjust testcase for gcc-14 [PR118182] The pr118182-2.c testcase backported from gcc-15 depended on the late combine pass after register allocation to substitute the zero constant into the pred_broadcast to get to the expected vmv.s.x instruction. Without that pass, we get a mfmv.s.f instead. Expect that on gcc-14. for gcc/testsuite/ChangeLog PR target/118182 * gcc.target/riscv/rvv/autovec/pr118182-2.c: Adjust. Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118182-2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118182-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118182-2.c index 619d757a14fa..0e334f599151 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118182-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118182-2.c @@ -9,7 +9,7 @@ ** ... ** vsetvli [ast][0-9]+,zero,.* ** ... -** vmv.s.x .* +** vfmv.s.f .* ** ... ** vfredusum.vs .* ** ...
[gcc r14-11620] RISC-V: revert pr114194 tests on gcc-14 [PR118601]
https://gcc.gnu.org/g:56b3858b6a1118d2e27e3047d5ee52faec7aac83
commit r14-11620-g56b3858b6a1118d2e27e3047d5ee52faec7aac83
Author: Alexandre Oliva
Date: Wed Apr 16 01:10:54 2025 -0300
RISC-V: revert pr114194 tests on gcc-14 [PR118601]
The gcc-14 backport that split the pr114194 testcase for rv32 and rv64
would only generate the expected rv32 sequence if commit
6b315907c0353f71169a7555e653d29a981fef67 had also been backported, but
it wasn't. Without it, we get the same code as before on both rv32
and rv64, so revert to the original test.
for gcc/testsuite/ChangeLog
PR target/118601
* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Restore.
* gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c: Remove.
* gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c: Likewise.
Diff:
---
.../riscv/rvv/xtheadvector/pr114194-rv32.c | 51 --
.../xtheadvector/{pr114194-rv64.c => pr114194.c} | 5 ++-
2 files changed, 3 insertions(+), 53 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
deleted file mode 100644
index 0bee5ec33de8..
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile { target rv32 } } */
-/* { dg-options "-march=rv32gc_xtheadvector -O2" } */
-/* { dg-final { check-function-bodies "**" "" } } */
-
-/*
-** foo0_1:
-** sb\tzero,0\([a-x0-9]+\)
-** ret
-*/
-void foo0_1 (void *p)
-{
- __builtin_memset (p, 0, 1);
-}
-
-/*
-** foo0_7:
-** li\t[a-x0-9]+,7
-** th.vsetvli\tzero,[a-x0-9]+,e8,m1
-** th\.vmv\.v\.i\tv[0-9],0
-** th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
-** ret
-*/
-void foo0_7 (void *p)
-{
- __builtin_memset (p, 0, 7);
-}
-
-/*
-** foo1_1:
-** li\t[a-x0-9]+,1
-** sb\t[a-x0-9]+,0\([a-x0-9]+\)
-** ret
-*/
-void foo1_1 (void *p)
-{
- __builtin_memset (p, 1, 1);
-}
-
-/*
-** foo1_5:
-** li\t[a-x0-9]+,5
-** th.vsetvli\tzero,[a-x0-9]+,e8,m1
-** th\.vmv\.v\.i\tv[0-9],1
-** th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
-** ret
-*/
-
-void foo1_5 (void *p)
-{
- __builtin_memset (p, 1, 5);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
similarity index 82%
rename from gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
rename to gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
index 84333c1cf5a7..2e53a7ecc3e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
@@ -1,5 +1,6 @@
-/* { dg-do compile { target rv64 } } */
-/* { dg-options "-march=rv64gc_xtheadvector -O2" } */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
/*
[gcc(refs/users/meissner/heads/work201-bugs)] PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
https://gcc.gnu.org/g:60843e98e637bf0b7eb5826f078a111ba9b82a52
commit 60843e98e637bf0b7eb5826f078a111ba9b82a52
Author: Michael Meissner
Date: Wed Apr 16 00:33:01 2025 -0400
PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
We had optimizations for splat of a vector extract for the other vector
types, but we missed having one for V2DI and V2DF. This patch adds a
combiner insn to do this optimization.
In looking at the source, we had similar optimizations for V4SI and V4SF
extract and splats, but we missed doing V2DI/V2DF.
Without the patch for the code:
vector long long splat_dup_l_0 (vector long long v)
{
return __builtin_vec_splats (__builtin_vec_extract (v, 0));
}
the compiler generates (on a little endian power9):
splat_dup_l_0:
mfvsrld 9,34
mtvsrdd 34,9,9
blr
Now it generates:
splat_dup_l_0:
xxpermdi 34,34,34,3
blr
2025-04-15 Michael Meissner
gcc/
PR target/99293
* config/rs6000/vsx.md (vsx_splat_extract_): New insn.
gcc/testsuite/
PR target/99293
* gcc.target/powerpc/builtins-1.c: Adjust insn count.
* gcc.target/powerpc/pr99293.c: New test.
Diff:
---
gcc/config/rs6000/vsx.md | 18 ++
gcc/testsuite/gcc.target/powerpc/builtins-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr99293.c| 22 ++
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index dd3573b80868..d84a2a357a31 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4798,6 +4798,24 @@
"lxvdsx %x0,%y1"
[(set_attr "type" "vecload")])
+;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
+(define_insn "*vsx_splat_extract_"
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
+ (vec_duplicate:VSX_D
+(vec_select:
+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")
+ (parallel [(match_operand 2 "const_0_to_1_operand" "n")]]
+ "VECTOR_MEM_VSX_P (mode)"
+{
+ int which_word = INTVAL (operands[2]);
+ if (!BYTES_BIG_ENDIAN)
+which_word = 1 - which_word;
+
+ operands[3] = GEN_INT (which_word ? 3 : 0);
+ return "xxpermdi %x0,%x1,%x1,%3";
+}
+ [(set_attr "type" "vecperm")])
+
;; V4SI splat support
(define_insn "vsx_splat_v4si"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 8410a5fd4319..4e7e5384675f 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -1035,4 +1035,4 @@ foo156 (vector unsigned short usa)
/* { dg-final { scan-assembler-times {\mvmrglb\M} 3 } } */
/* { dg-final { scan-assembler-times {\mvmrgew\M} 4 } } */
/* { dg-final { scan-assembler-times {\mvsplth|xxsplth\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 44 } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 42 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99293.c
b/gcc/testsuite/gcc.target/powerpc/pr99293.c
new file mode 100644
index ..20adc1f27f65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr99293.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test for PR 99263, which wants to do:
+ __builtin_vec_splats (__builtin_vec_extract (v, n))
+
+ where v is a V2DF or V2DI vector and n is either 0 or 1. Previously the
+ compiler would do a direct move to the GPR registers to select the item and
a
+ direct move from the GPR registers to do the splat. */
+
+vector long long splat_dup_l_0 (vector long long v)
+{
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+}
+
+vector long long splat_dup_l_1 (vector long long v)
+{
+ return __builtin_vec_splats (__builtin_vec_extract (v, 1));
+}
+
+/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */
[gcc(refs/users/meissner/heads/work201-bugs)] PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
https://gcc.gnu.org/g:73b321d24ce4320f0171b7b132d098e1a261f4b9
commit 73b321d24ce4320f0171b7b132d098e1a261f4b9
Author: Michael Meissner
Date: Wed Apr 16 00:32:09 2025 -0400
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
Previously GCC would zero externd a DImode GPR value to TImode by first zero
extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
move this value to a VSX register.
This patch does the move directly, since if the middle argument to MTVSRDD
is 0,
it does the zero extend.
If the DImode value is already in a vector register, it does a XXSPLTIB and
XXPERMDI to get the value into the bottom 64-bits of the register.
I have built GCC with the patches in this patch set applied on both little
and
big endian PowerPC systems and there were no regressions. Can I apply this
patch to GCC 15?
2025-04-15 Michael Meissner
gcc/
PR target/108598
* gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.
gcc/testsuite/
PR target/108598
* gcc.target/powerpc/pr108958.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.md | 46 +
gcc/testsuite/gcc.target/powerpc/pr108958.c | 27 +
2 files changed, 73 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 02c31b576b65..4c9e2dc6390b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1026,6 +1026,52 @@
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
+(define_insn_and_split "zero_extendditi2"
+ [(set (match_operand:TI 0 "gpc_reg_operand" "=r,wa,&wa")
+ (zero_extend:TI
+(match_operand:DI 1 "gpc_reg_operand" "rwa,r,wa")))]
+ "TARGET_P9_VECTOR && TARGET_POWERPC64"
+ "@
+ #
+ mtvsrdd %x0,0,%1
+ #"
+ "&& reload_completed
+ && (int_reg_operand (operands[0], TImode)
+ || vsx_register_operand (operands[1], DImode))"
+ [(set (match_dup 2)
+ (match_dup 3))
+ (set (match_dup 4)
+ (match_dup 5))]
+{
+ rtx op0 = operands[0];
+ rtx op1 = operands[1];
+ int r = reg_or_subregno (op0);
+
+ if (int_reg_operand (op0, TImode))
+{
+ int lo = BYTES_BIG_ENDIAN ? 1 : 0;
+ int hi = 1 - lo;
+
+ operands[2] = gen_rtx_REG (DImode, r + lo);
+ operands[3] = op1;
+ operands[4] = gen_rtx_REG (DImode, r + hi);
+ operands[5] = const0_rtx;
+}
+ else
+{
+ rtx op0_di = gen_rtx_REG (DImode, r);
+ rtx op0_v2di = gen_rtx_REG (V2DImode, r);
+ rtx lo = WORDS_BIG_ENDIAN ? op1 : op0_di;
+ rtx hi = WORDS_BIG_ENDIAN ? op0_di : op1;
+
+ operands[2] = op0_v2di;
+ operands[3] = CONST0_RTX (V2DImode);
+ operands[4] = op0_v2di;
+ operands[5] = gen_rtx_VEC_CONCAT (V2DImode, hi, lo);
+}
+}
+ [(set_attr "type" "*,mtvsr,vecperm")
+ (set_attr "length" "8,*,8")])
(define_insn "extendqi2"
[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108958.c
b/gcc/testsuite/gcc.target/powerpc/pr108958.c
new file mode 100644
index ..03eb58d069e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr108958.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
+
+/* PR target/108958, use mtvsrdd to zero extend gpr to vsx register. */
+
+void
+gpr_to_vsx (unsigned long long x, __uint128_t *p)
+{
+ /* mtvsrdd vsx,0,gpr. */
+ __uint128_t y = x;
+ __asm__ (" # %x0" : "+wa" (y));
+ *p = y;
+}
+
+void
+gpr_to_gpr (unsigned long long x, __uint128_t *p)
+{
+ /* mr and li. */
+ __uint128_t y = x;
+ __asm__ (" # %0" : "+r" (y));
+ *p = y;
+}
+
+/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mmtvsrdd .*,0,.*\M} 1 } } */
[gcc(refs/users/meissner/heads/work201-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:128192f13bd7a5b116fb84299dfe9f6cbe4a7ba7
commit 128192f13bd7a5b116fb84299dfe9f6cbe4a7ba7
Author: Michael Meissner
Date: Wed Apr 16 00:34:36 2025 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.bugs | 74 ++
1 file changed, 74 insertions(+)
diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 8da3c42bd934..a0ef07002b78 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,77 @@
+ Branch work201-bugs, patch #202
+
+PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
+
+We had optimizations for splat of a vector extract for the other vector
+types, but we missed having one for V2DI and V2DF. This patch adds a
+combiner insn to do this optimization.
+
+In looking at the source, we had similar optimizations for V4SI and V4SF
+extract and splats, but we missed doing V2DI/V2DF.
+
+Without the patch for the code:
+
+ vector long long splat_dup_l_0 (vector long long v)
+ {
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+ }
+
+the compiler generates (on a little endian power9):
+
+ splat_dup_l_0:
+ mfvsrld 9,34
+ mtvsrdd 34,9,9
+ blr
+
+Now it generates:
+
+ splat_dup_l_0:
+ xxpermdi 34,34,34,3
+ blr
+
+2025-04-15 Michael Meissner
+
+gcc/
+
+ PR target/99293
+ * config/rs6000/vsx.md (vsx_splat_extract_): New insn.
+
+gcc/testsuite/
+
+ PR target/99293
+ * gcc.target/powerpc/builtins-1.c: Adjust insn count.
+ * gcc.target/powerpc/pr99293.c: New test.
+
+ Branch work201-bugs, patch #201
+
+PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
+
+Previously GCC would zero externd a DImode GPR value to TImode by first zero
+extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
+move this value to a VSX register.
+
+This patch does the move directly, since if the middle argument to MTVSRDD is
0,
+it does the zero extend.
+
+If the DImode value is already in a vector register, it does a XXSPLTIB and
+XXPERMDI to get the value into the bottom 64-bits of the register.
+
+I have built GCC with the patches in this patch set applied on both little and
+big endian PowerPC systems and there were no regressions. Can I apply this
+patch to GCC 15?
+
+2025-04-15 Michael Meissner
+
+gcc/
+
+ PR target/108598
+ * gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.
+
+gcc/testsuite/
+
+ PR target/108598
+ * gcc.target/powerpc/pr108958.c: New test.
+
Branch work201-bugs, patch #200
Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.
[gcc r15-9513] testsuite: Add testcase for already fixed PR [PR116093]
https://gcc.gnu.org/g:45a708d7bf8369930f4f770bbb7047941727ba41
commit r15-9513-g45a708d7bf8369930f4f770bbb7047941727ba41
Author: Jakub Jelinek
Date: Wed Apr 16 08:42:35 2025 +0200
testsuite: Add testcase for already fixed PR [PR116093]
This testcase got fixed with r15-9397 PR119722 fix.
2025-04-16 Jakub Jelinek
PR tree-optimization/116093
* gcc.dg/bitint-122.c: New test.
Diff:
---
gcc/testsuite/gcc.dg/bitint-122.c | 20
1 file changed, 20 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/bitint-122.c
b/gcc/testsuite/gcc.dg/bitint-122.c
new file mode 100644
index ..c7919698b573
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/bitint-122.c
@@ -0,0 +1,20 @@
+/* PR tree-optimization/116093 */
+/* { dg-do run { target bitint } } */
+/* { dg-options "-Og -ftree-vrp -fno-tree-dce" } */
+
+#if __BITINT_MAXWIDTH__ >= 129
+char
+foo (int a, _BitInt (129) b, char c)
+{
+ return c << (5 / b % (0xdb75dbf5 | a));
+}
+#endif
+
+int
+main ()
+{
+#if __BITINT_MAXWIDTH__ >= 129
+ if (foo (0, 6, 1) != 1)
+__builtin_abort ();
+#endif
+}
[gcc r15-9512] AArch64: Fix operands order in vec_extract expander
https://gcc.gnu.org/g:31e16c8b75bd49a9c5c01ada340da340c6f15c99
commit r15-9512-g31e16c8b75bd49a9c5c01ada340da340c6f15c99
Author: Tejas Belagod
Date: Sun Apr 13 01:08:00 2025 +0530
AArch64: Fix operands order in vec_extract expander
The operand order to gen_vcond_mask call in the vec_extract pattern is
wrong.
Fix the order where predicate is operand 3.
Tested and bootstrapped on aarch64-linux-gnu. OK for trunk?
gcc/ChangeLog
* config/aarch64/aarch64-sve.md (vec_extract): Fix
operand
order to gen_vcond_mask_*.
Diff:
---
gcc/config/aarch64/aarch64-sve.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index 3dbd65986ec7..d4af3706294d 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3133,9 +3133,9 @@
"TARGET_SVE"
{
rtx tmp = gen_reg_rtx (mode);
-emit_insn (gen_vcond_mask_ (tmp, operands[1],
-CONST1_RTX (mode),
-CONST0_RTX (mode)));
+emit_insn (gen_vcond_mask_ (tmp, CONST1_RTX (mode),
+CONST0_RTX (mode),
+operands[1]));
emit_insn (gen_vec_extract (operands[0], tmp, operands[2]));
DONE;
}
[gcc r15-9515] riscv: Fix incorrect gnu property alignment on rv32
https://gcc.gnu.org/g:fc4099a4842805f1eb59a666e18f84e309df8cb1
commit r15-9515-gfc4099a4842805f1eb59a666e18f84e309df8cb1
Author: Jesse Huang
Date: Thu Apr 10 21:25:21 2025 -0700
riscv: Fix incorrect gnu property alignment on rv32
Codegen is incorrectly emitting a ".p2align 3" that coerces the
alignment of the .note.gnu.property section from 4 to 8 on rv32.
2025-04-11 Jesse Huang
gcc/ChangeLog
* config/riscv/riscv.cc (riscv_file_end): Fix .p2align value.
gcc/testsuite/ChangeLog
* gcc.target/riscv/gnu-property-align-rv32.c: New file.
* gcc.target/riscv/gnu-property-align-rv64.c: New file.
Diff:
---
gcc/config/riscv/riscv.cc| 2 +-
gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c | 7 +++
gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c | 7 +++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38f3ae7cd840..d3656a7a4307 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10382,7 +10382,7 @@ riscv_file_end ()
fprintf (asm_out_file, "1:\n");
/* pr_type. */
- fprintf (asm_out_file, "\t.p2align\t3\n");
+ fprintf (asm_out_file, "\t.p2align\t%u\n", p2align);
fprintf (asm_out_file, "2:\n");
fprintf (asm_out_file, "\t.long\t0xc000\n");
/* pr_datasz. */
diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c
b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c
new file mode 100644
index ..4f48cff33da9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32g_zicfiss -fcf-protection=return -mabi=ilp32d " }
*/
+
+void foo() {}
+
+/* { dg-final { scan-assembler-times ".p2align\t2" 3 } } */
+/* { dg-final { scan-assembler-not ".p2align\t3" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c
b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c
new file mode 100644
index ..1bfd12718262
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_zicfiss -fcf-protection=return -mabi=lp64d " } */
+
+void foo() {}
+
+/* { dg-final { scan-assembler-times ".p2align\t3" 3 } } */
+/* { dg-final { scan-assembler-not ".p2align\t2" } } */
[gcc r15-9514] RISC-V: Put jump table in text for large code model
https://gcc.gnu.org/g:1d9e02bb7e0af4f3d3eaaa1a0f4961970aba5560
commit r15-9514-g1d9e02bb7e0af4f3d3eaaa1a0f4961970aba5560
Author: Kito Cheng
Date: Mon Apr 14 16:03:07 2025 +0800
RISC-V: Put jump table in text for large code model
Large code model assume the data or rodata may put far away from
text section. So we need to put jump table in text section for
large code model.
gcc/ChangeLog:
* config/riscv/riscv.h (JUMP_TABLES_IN_TEXT_SECTION): Check if
large code model.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/jump-table-large-code-model.c: New test.
Diff:
---
gcc/config/riscv/riscv.h | 2 +-
.../gcc.target/riscv/jump-table-large-code-model.c | 24 ++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 2bcabd03517a..2759a4cb1c9f 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -888,7 +888,7 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
(PTR) = riscv_asm_output_opcode(STREAM, PTR)
-#define JUMP_TABLES_IN_TEXT_SECTION 0
+#define JUMP_TABLES_IN_TEXT_SECTION (riscv_cmodel == CM_LARGE)
#define CASE_VECTOR_MODE SImode
#define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
new file mode 100644
index ..1ee7f6c07d3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large" } */
+
+int foo(int x, int y)
+{
+ switch(x){
+ case 0:
+return 123 + y;
+ case 1:
+return 456 + y;
+ case 2:
+return 789 - y;
+ case 3:
+return 12 * y;
+ case 4:
+return 13 % y;
+ case 5:
+return 11 *y;
+ }
+ return 0;
+}
+
+
+/* { dg-final { scan-assembler-not "\.section \.rodata" } } */
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction regression spacing indexation tableaux.
https://gcc.gnu.org/g:67dff22e166513c9b8067ffc79537cf00cacd741
commit 67dff22e166513c9b8067ffc79537cf00cacd741
Author: Mikael Morin
Date: Tue Apr 15 16:45:46 2025 +0200
Correction regression spacing indexation tableaux.
Diff:
---
gcc/fortran/trans.cc | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/gcc/fortran/trans.cc b/gcc/fortran/trans.cc
index c2aae309b081..75825dcdc80f 100644
--- a/gcc/fortran/trans.cc
+++ b/gcc/fortran/trans.cc
@@ -413,7 +413,7 @@ gfc_build_spanned_array_ref (tree base, tree offset, tree
span)
tree
gfc_build_array_ref (tree type, tree base, tree index, bool
non_negative_offset,
-tree min_idx, tree spacing, tree offset)
+tree min_idx, tree spacing_bytes, tree offset)
{
if (DECL_P (base))
TREE_ADDRESSABLE (base) = 1;
@@ -422,8 +422,22 @@ gfc_build_array_ref (tree type, tree base, tree index,
bool non_negative_offset,
STRIP_TYPE_NOPS (index);
if (non_negative_offset)
-return build4_loc (input_location, ARRAY_REF, type, base, index,
- min_idx, spacing);
+{
+ tree spacing;
+ if (spacing_bytes == NULL_TREE)
+ spacing = NULL_TREE;
+ else
+ {
+ gcc_assert (TREE_CODE (TREE_TYPE (base)) == ARRAY_TYPE);
+ int elt_align = TYPE_ALIGN_UNIT (TREE_TYPE (TREE_TYPE (base)));
+ spacing = fold_build2_loc (input_location, EXACT_DIV_EXPR,
+gfc_array_index_type, spacing_bytes,
+build_int_cst (gfc_array_index_type,
+ elt_align));
+ }
+ return build4_loc (input_location, ARRAY_REF, type, base, index,
+min_idx, spacing);
+}
/* Otherwise use pointer arithmetic. */
else
{
@@ -441,7 +455,7 @@ gfc_build_array_ref (tree type, tree base, tree index, bool
non_negative_offset,
fold_convert (gfc_array_index_type, min))
: fold_convert (gfc_array_index_type, index);
- tree delta = spacing;
+ tree delta = spacing_bytes;
if (delta == NULL_TREE)
delta = fold_convert_loc (input_location, gfc_array_index_type,
TYPE_SIZE_UNIT (type));
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression dependency_12
https://gcc.gnu.org/g:f11ea3c6f57c5504b861d1b027bb7ef6cfa197c4
commit f11ea3c6f57c5504b861d1b027bb7ef6cfa197c4
Author: Mikael Morin
Date: Tue Apr 15 17:42:09 2025 +0200
Correction régression dependency_12
Diff:
---
gcc/fortran/trans-decl.cc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index b154cb3161c2..8f5e78bf1ffd 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -1033,6 +1033,9 @@ update_type_bounds (tree type, tree
lbound[GFC_MAX_DIMENSIONS],
tree ubound[GFC_MAX_DIMENSIONS],
tree spacing[GFC_MAX_DIMENSIONS], tree root_type, int dim)
{
+ if (dim > 0)
+update_type_bounds (type, lbound, ubound, spacing, root_type, dim - 1);
+
tree current_lbound = lbound[dim];
if (current_lbound != NULL_TREE)
{
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression index_3
https://gcc.gnu.org/g:8b549538cf7cc16869d664b50bb01e929bdd6a16
commit 8b549538cf7cc16869d664b50bb01e929bdd6a16
Author: Mikael Morin
Date: Tue Apr 15 17:09:40 2025 +0200
Correction régression index_3
Diff:
---
gcc/fortran/trans-array.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index fe77af2e14e2..3042573e1854 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -2096,7 +2096,7 @@ gfc_constant_array_constructor_p (gfc_constructor_base
base)
static void
-append_constructor (vec *v, tree t)
+append_constructor (vec *&v, tree t)
{
unsigned len = vec_safe_length (v);
tree idx = build_int_cst (gfc_array_index_type, len);
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression class_assign_3
https://gcc.gnu.org/g:983878efe9fb100269cb959d17152fb1db89421d
commit 983878efe9fb100269cb959d17152fb1db89421d
Author: Mikael Morin
Date: Tue Apr 15 16:51:23 2025 +0200
Correction régression class_assign_3
Diff:
---
gcc/fortran/trans-types.cc | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/fortran/trans-types.cc b/gcc/fortran/trans-types.cc
index 0c07de4bd18a..15d9f629feaf 100644
--- a/gcc/fortran/trans-types.cc
+++ b/gcc/fortran/trans-types.cc
@@ -2206,8 +2206,11 @@ gfc_get_array_type_bounds (tree etype, int dimen, int
codimen, tree * lbound,
else
{
stride = gfc_index_one_node;
- spacing = fold_convert_loc (input_location, gfc_array_index_type,
- TYPE_SIZE_UNIT (etype));
+ if (dimen == 0)
+ spacing = NULL_TREE;
+ else
+ spacing = fold_convert_loc (input_location, gfc_array_index_type,
+ TYPE_SIZE_UNIT (etype));
}
for (n = 0; n < dimen + codimen; n++)
{
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression dependency_42
https://gcc.gnu.org/g:b72f769bf930942f971aec04ceb944fc24dd371c commit b72f769bf930942f971aec04ceb944fc24dd371c Author: Mikael Morin Date: Tue Apr 15 20:28:17 2025 +0200 Correction régression dependency_42 Diff: --- gcc/fortran/trans-array.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc index 3042573e1854..5652eb1c7185 100644 --- a/gcc/fortran/trans-array.cc +++ b/gcc/fortran/trans-array.cc @@ -3423,7 +3423,7 @@ conv_array_index (gfc_se * se, gfc_ss * ss, int dim, int i, gfc_array_ref * ar) gfc_conv_array_data (desc)); index = gfc_build_array_ref (data, index, non_negative_strides_array_p (desc), - gfc_conv_array_lbound (desc, 0), + se->loop->from[i], gfc_conv_array_spacing (desc, 0)); index = gfc_evaluate_now (index, &se->pre); index = fold_convert (gfc_array_index_type, index);
[gcc(refs/users/meissner/heads/work201-libs)] Add ChangeLog.libs and update REVISION.
https://gcc.gnu.org/g:3ae93633aa1f94639571b6156958b118a3fb86c0 commit 3ae93633aa1f94639571b6156958b118a3fb86c0 Author: Michael Meissner Date: Mon Apr 14 15:15:07 2025 -0400 Add ChangeLog.libs and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.libs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.libs | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs new file mode 100644 index ..69f46576250c --- /dev/null +++ b/gcc/ChangeLog.libs @@ -0,0 +1,5 @@ + Branch work201-libs, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..7dae70785b31 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-libs branch
[gcc/meissner/heads/work201-math] (52 commits) Merge commit 'refs/users/meissner/heads/work201-math' of gi
The branch 'meissner/heads/work201-math' was updated to point to: 267198071642... Merge commit 'refs/users/meissner/heads/work201-math' of gi It previously pointed to: 882e2314109a... Merge commit 'refs/users/meissner/heads/work201-math' of gi Diff: Summary of changes (added commits): --- 2671980... Merge commit 'refs/users/meissner/heads/work201-math' of gi 0eab295... Add ChangeLog.math and update REVISION. c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh (*) e9b4cfa... Update ChangeLog.* (*) 07a339a... Use architecture flags for defining _ARCH_PWR macros. (*) 97c13da... Add rs6000 architecture masks. (*) bd351b3... xUse vector pair load/store for memcpy with -mcpu=future (*) caf3d48... Add -mcpu=future tests. (*) e82e341... Add -mcpu=future tuning support. (*) ac1f5a3... Add support for -mcpu=future (*) 256b94a... Change TARGET_MODULO to TARGET_POWER9. (*) 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. (*) 93b17d0... Change TARGET_CMPB to TARGET_POWER6. (*) ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. (*) f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. (*) abf2924... Add ChangeLog.meissner and REVISION. (*) e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-math' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-math)] Add ChangeLog.math and update REVISION.
https://gcc.gnu.org/g:0eab2952db329512dbd5f08f2dd2de21e515fbcb commit 0eab2952db329512dbd5f08f2dd2de21e515fbcb Author: Michael Meissner Date: Mon Apr 14 15:17:52 2025 -0400 Add ChangeLog.math and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.math: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.math | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.math b/gcc/ChangeLog.math new file mode 100644 index ..fe8cef4665ad --- /dev/null +++ b/gcc/ChangeLog.math @@ -0,0 +1,5 @@ + Branch work201-math, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..6f5edba6571c 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-math branch
[gcc(refs/users/meissner/heads/work201-math)] Merge commit 'refs/users/meissner/heads/work201-math' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:2671980716424e72593446426255a60a03d50305 commit 2671980716424e72593446426255a60a03d50305 Merge: 0eab2952db32 882e2314109a Author: Michael Meissner Date: Tue Apr 15 13:32:53 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-math' of git+ssh://gcc.gnu.org/git/gcc into me/work201-math Diff:
[gcc(refs/users/meissner/heads/work201-paddis)] Merge commit 'refs/users/meissner/heads/work201-paddis' of git+ssh://gcc.gnu.org/git/gcc into me/wor
https://gcc.gnu.org/g:1ead019f06cde930ce1c04017df7b85e49e738e4 commit 1ead019f06cde930ce1c04017df7b85e49e738e4 Merge: 3a7becbebaf2 0c0bc7f40f1a Author: Michael Meissner Date: Tue Apr 15 13:34:40 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-paddis' of git+ssh://gcc.gnu.org/git/gcc into me/work201-paddis Diff:
[gcc/meissner/heads/work201-paddis] (52 commits) Merge commit 'refs/users/meissner/heads/work201-paddis' of
The branch 'meissner/heads/work201-paddis' was updated to point to: 1ead019f06cd... Merge commit 'refs/users/meissner/heads/work201-paddis' of It previously pointed to: 0c0bc7f40f1a... Merge commit 'refs/users/meissner/heads/work201-paddis' of Diff: Summary of changes (added commits): --- 1ead019... Merge commit 'refs/users/meissner/heads/work201-paddis' of 3a7becb... Add ChangeLog.paddis and update REVISION. c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh (*) e9b4cfa... Update ChangeLog.* (*) 07a339a... Use architecture flags for defining _ARCH_PWR macros. (*) 97c13da... Add rs6000 architecture masks. (*) bd351b3... xUse vector pair load/store for memcpy with -mcpu=future (*) caf3d48... Add -mcpu=future tests. (*) e82e341... Add -mcpu=future tuning support. (*) ac1f5a3... Add support for -mcpu=future (*) 256b94a... Change TARGET_MODULO to TARGET_POWER9. (*) 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. (*) 93b17d0... Change TARGET_CMPB to TARGET_POWER6. (*) ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. (*) f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. (*) abf2924... Add ChangeLog.meissner and REVISION. (*) e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-paddis' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-paddis)] Add ChangeLog.paddis and update REVISION.
https://gcc.gnu.org/g:3a7becbebaf2af15a02f448ad10ec2aa41057a7d commit 3a7becbebaf2af15a02f448ad10ec2aa41057a7d Author: Michael Meissner Date: Mon Apr 14 15:19:36 2025 -0400 Add ChangeLog.paddis and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.paddis: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.paddis | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.paddis b/gcc/ChangeLog.paddis new file mode 100644 index ..b8c9b5293f20 --- /dev/null +++ b/gcc/ChangeLog.paddis @@ -0,0 +1,5 @@ + Branch work201-paddis, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..d90dc19a4f8f 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-paddis branch
[gcc(refs/users/meissner/heads/work201-sha)] Merge commit 'refs/users/meissner/heads/work201-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work20
https://gcc.gnu.org/g:1dbb90142ed052a6a54822ec19dc1bec473468ec commit 1dbb90142ed052a6a54822ec19dc1bec473468ec Merge: dd2a961fa2cd e326d72a05dc Author: Michael Meissner Date: Tue Apr 15 13:35:45 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work201-sha Diff:
[gcc(refs/users/meissner/heads/work201)] Add support for -mcpu=future
https://gcc.gnu.org/g:ac1f5a300d0cb0684b4ab9f1da8a23b1b7cac206
commit ac1f5a300d0cb0684b4ab9f1da8a23b1b7cac206
Author: Michael Meissner
Date: Mon Apr 14 20:26:49 2025 -0400
Add support for -mcpu=future
This patch adds the support that can be used in developing GCC support for
future PowerPC processors.
2025-04-14 Michael Meissner
* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=future.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
-mcpu=future, define _ARCH_FUTURE.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(POWERPC_MASKS): Add OPTION_MASK_FUTURE.
(future cpu): Define.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power10_cost): Update comment.
(get_arch_flags): Add support for future processor.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Add -mfuture.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Likewise.
* config/rs6000/rs6000.opt (-mfuture): New internal option.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 1 +
gcc/config/rs6000/rs6000-tables.opt | 11 +++
gcc/config/rs6000/rs6000.cc | 30 ++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 6 ++
13 files changed, 52 insertions(+), 15 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 40b50dc969ed..1d8a0c80672f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -535,7 +535,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5682,7 +5682,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
- "" | common | native \
+ "" | common | native | future \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 2b21dd7cd1e0..77651f5ea309 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 53c0bde5ad4a..652f60c7f494 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index c7639368a264..3c66ac1d9171 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=nati
[gcc(refs/users/meissner/heads/work201)] Change TARGET_CMPB to TARGET_POWER6.
https://gcc.gnu.org/g:93b17d062c1a45062ac27dc9c313fbc04f83dc7c
commit 93b17d062c1a45062ac27dc9c313fbc04f83dc7c
Author: Michael Meissner
Date: Mon Apr 14 20:22:47 2025 -0400
Change TARGET_CMPB to TARGET_POWER6.
This patch changes TARGET_CMPB to TARGET_POWER6. The -mcmpb switch is not
being
changed, just the name of the macros used to determine if the PowerPC
processor
supports ISA 2.5 (Power6).
2025-04-14 Michael Meissner
gcc/
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_POWER6): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Likewise.
(cmpb3): Likewise.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000.cc | 8
gcc/config/rs6000/rs6000.h | 7 ---
gcc/config/rs6000/rs6000.md | 16
4 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 4ed2bc1ca89e..dbb8520ab039 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P5:
return TARGET_POWER5;
case ENB_P6:
- return TARGET_CMPB;
+ return TARGET_POWER6;
case ENB_P6_64:
- return TARGET_CMPB && TARGET_POWERPC64;
+ return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
return TARGET_POPCNTD;
case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b2811d963fcf..c01af37200ac 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3922,7 +3922,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_CMPB)
+ else if (TARGET_POWER6)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_POWER5X)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
@@ -4797,7 +4797,7 @@ rs6000_option_override_internal (bool global_init_p)
DERAT mispredict penalty. However the LVE and STVE altivec instructions
need indexed accesses and the type used is the scalar type of the element
being loaded or stored. */
-TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
+TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
&& !TARGET_ALTIVEC);
/* Set the -mrecip options. */
@@ -22396,7 +22396,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case PARITY:
- *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
+ *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
return false;
case NOT:
@@ -23223,7 +23223,7 @@ rs6000_emit_parity (rtx dst, rtx src)
tmp = gen_reg_rtx (mode);
/* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
- if (TARGET_CMPB)
+ if (TARGET_POWER6)
{
if (mode == SImode)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3794e3c0658d..5b8cf054f98a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT/* 970/power4 */\
|| TARGET_POWER5 /* ISA 2.02 */ \
-|| TARGET_CMPB /* ISA 2.05 */ \
+|| TARGET_POWER6 /* ISA 2.05 */ \
|| TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX TARGET_CMPB
+#define TARGET_LFIWAX TARGET_POWER6
#define TARGET_LFIWZX TARGET_POPCNTD
#define TARGET_FCFIDS TARGET_POPCNTD
#define TARGET_FCFIDU TARGET_POPCNTD
@@ -502,6 +502,7 @@ extern int rs6000_vector_align[];
/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */
#define TARGET_POWER5 TARGET_POPCNTB
#define TARGET_POWER5X TARGET_FPRND
+#define TARGET_POWER6
[gcc(refs/users/meissner/heads/work201)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:abf292461ed3227e2ba9521bf8ae3fc17cc8b81c commit abf292461ed3227e2ba9521bf8ae3fc17cc8b81c Author: Michael Meissner Date: Mon Apr 14 15:11:21 2025 -0400 Add ChangeLog.meissner and REVISION. 2025-04-14 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 5 + gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 5 + gcc/c/ChangeLog.meissner | 5 + gcc/cp/ChangeLog.meissner| 5 + gcc/fortran/ChangeLog.meissner | 5 + gcc/testsuite/ChangeLog.meissner | 5 + libgcc/ChangeLog.meissner| 5 + libstdc++-v3/ChangeLog.meissner | 5 + 9 files changed, 41 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..5f8715c4844d --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work201 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch
[gcc(refs/users/meissner/heads/work201)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:e82e34154be869845327bebb42769eb39d33dc3c commit e82e34154be869845327bebb42769eb39d33dc3c Author: Michael Meissner Date: Mon Apr 14 20:28:29 2025 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2025-04-14 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fd31b16b3314..bdd7e58145ba 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM Power10 and Power11 processors. +;; Scheduling description for the IBM Power10, Power11, and +;; potential future processors. ;; Copyright (C) 2020-2025 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle lat
[gcc(refs/users/meissner/heads/work201)] Add -mcpu=future tests.
https://gcc.gnu.org/g:caf3d48ae5ba526697b4d0be3af087d30dc36c45
commit caf3d48ae5ba526697b4d0be3af087d30dc36c45
Author: Michael Meissner
Date: Mon Apr 14 20:29:30 2025 -0400
Add -mcpu=future tests.
This patch adds simple tests for -mcpu=future.
2025-04-14 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/future-1.c: New test.
* gcc.target/powerpc/future-2.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/future-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/future-2.c | 24
2 files changed, 37 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/future-1.c
b/gcc/testsuite/gcc.target/powerpc/future-1.c
new file mode 100644
index ..f1b940d7bebf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=future and if it defines
+ _ARCH_PWR11. */
+
+#ifndef _ARCH_FUTURE
+#error "-mcpu=future is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/future-2.c
b/gcc/testsuite/gcc.target/powerpc/future-2.c
new file mode 100644
index ..5552cefa3c2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the future target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
+
+__attribute__((__target__("cpu=future")))
+void foo_future (void)
+{
+}
[gcc(refs/users/meissner/heads/work201)] Change TARGET_POPCNTB to TARGET_POWER5.
https://gcc.gnu.org/g:f9fc96ef6ae9f6bb57b03e1fb63d0c9a133f6f2d commit f9fc96ef6ae9f6bb57b03e1fb63d0c9a133f6f2d Author: Michael Meissner Date: Mon Apr 14 20:20:49 2025 -0400 Change TARGET_POPCNTB to TARGET_POWER5. This patch changes TARGET_POPCNTB to TARGET_POWER5. The -mpopcntb switch is not being changed in this patch, just the name of the macros used to determine if the PowerPC processor supports ISA 2.2 (Power5). 2025-04-14 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_POPCNTB to TARGET_POWER5. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise. (TARGET_POWER5): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTB to TARGET_POWER5. (TARGET_FRE): Likewise. (TARGET_FRSQRTES): Likewise. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. Diff: --- gcc/config/rs6000/rs6000-builtin.cc | 2 +- gcc/config/rs6000/rs6000.cc | 2 +- gcc/config/rs6000/rs6000.h | 11 +++ gcc/config/rs6000/rs6000.md | 2 +- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 111802381acb..4ed2bc1ca89e 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_ALWAYS: return true; case ENB_P5: - return TARGET_POPCNTB; + return TARGET_POWER5; case ENB_P6: return TARGET_CMPB; case ENB_P6_64: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 737c3d6f7c75..a5ed93702494 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3926,7 +3926,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_FPRND) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); - else if (TARGET_POPCNTB) + else if (TARGET_POWER5) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); else if (TARGET_ALTIVEC) rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index db6112a09e11..d9a0ffe9f5b2 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -448,7 +448,7 @@ extern int rs6000_vector_align[]; Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT/* 970/power4 */\ -|| TARGET_POPCNTB /* ISA 2.02 */ \ +|| TARGET_POWER5 /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD) /* ISA 2.06 */ @@ -499,6 +499,9 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) +/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ +#define TARGET_POWER5 TARGET_POPCNTB + /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ @@ -525,7 +528,7 @@ extern int rs6000_vector_align[]; #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64\ || TARGET_PPC_GPOPT /* 970/power4 */\ -|| TARGET_POPCNTB /* ISA 2.02 */ \ +|| TARGET_POWER5/* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ @@ -541,9 +544,9 @@ extern int rs6000_vector_align[]; #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) #define TARGET_FRE (TARGET_HARD_FLOAT \ -&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) +&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode))) -#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \ +#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \ && TARGET_PPC_GFXOPT) #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9c718ca2a226..c5bd273be8b3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs
[gcc(refs/users/meissner/heads/work201)] Change TARGET_FPRND to TARGET_POWER5X.
https://gcc.gnu.org/g:ed0d85bff0ac6089e093ad6ee82e7310304eca31
commit ed0d85bff0ac6089e093ad6ee82e7310304eca31
Author: Michael Meissner
Date: Mon Apr 14 20:21:49 2025 -0400
Change TARGET_FPRND to TARGET_POWER5X.
This patch changes TARGET_POWER5X to TARGET_POWER5. The -mfprnd switch is
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.4 (Power5x).
2025-04-14 Michael Meissner
gcc/
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Change TARGET_FPRND to TARGET_POWER5X.
* gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro.
* gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to
TARGET_POWER5X.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 4 ++--
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 14 +++---
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a5ed93702494..b2811d963fcf 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3924,7 +3924,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
else if (TARGET_CMPB)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
- else if (TARGET_FPRND)
+ else if (TARGET_POWER5X)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
else if (TARGET_POWER5)
rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
@@ -3951,7 +3951,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
}
- if (!TARGET_FPRND && TARGET_VSX)
+ if (!TARGET_POWER5X && TARGET_VSX)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
/* TARGET_VSX = 1 implies Power 7 and newer */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d9a0ffe9f5b2..3794e3c0658d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -501,6 +501,7 @@ extern int rs6000_vector_align[];
/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */
#define TARGET_POWER5 TARGET_POPCNTB
+#define TARGET_POWER5X TARGET_FPRND
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_. The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c5bd273be8b3..045ce22a03c8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_FPRND
+ && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_FPRND
+ && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (mode);
@@ -6689,7 +6689,7 @@
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
- "TARGET_HARD_FLOAT && TARGET_FPRND
+ "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
@@ -6817,7 +6817,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIZ))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6827,7 +6827,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIP))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6837,7 +6837,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIM))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6848,7 +6848,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
UNSPEC_FRIN))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"frin %0,%1"
[(set_attr "type" "fp")])
[gcc(refs/users/meissner/heads/work201)] Use architecture flags for defining _ARCH_PWR macros.
https://gcc.gnu.org/g:07a339a9e569922bfb1f65ff20ebf050c9a62963
commit 07a339a9e569922bfb1f65ff20ebf050c9a62963
Author: Michael Meissner
Date: Mon Apr 14 20:32:30 2025 -0400
Use architecture flags for defining _ARCH_PWR macros.
For the newer architectures, this patch changes GCC to define the
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options
like
-mpower10.
The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were
removed.
The -mpower11 and -mfuture options were removed completely, since they were
just
added in GCC 15. The other two options were marked as WarnRemoved, and the
various ISA bits were removed.
TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were
re-defined
to use the architeture bits instead of the ISA bits.
There are other internal isa bits that aren't removed with this patch
because
the built-in function support uses those bits.
I have built both big endian and little endian bootstrap compilers and there
were no regressions.
Can I install this patch on the GCC 15 trunk?
2025-04-14 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10,
OPTION_MASK_POWER11, and OPTION_MASK_FUTURE.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros):
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr):
Likewise.
(rs6000_option_override_internal): Use architecture flags instead
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which
are
no longer in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use
architecture
flags.
(TARGET_POWER5X): Likewise.
(TARGET_POWER6): Likewise.
(TARGET_POWER7): Likewise.
(TARGET_POWER8): Likewise.
(TARGET_POWER9): Likewise.
(TARGET_POWER10): New macro.
(TARGET_POWER11): Likewise.
(TARGET_FUTURE): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.
(-mfuture): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 29 -
gcc/config/rs6000/rs6000-cpus.def | 10 +-
gcc/config/rs6000/rs6000-protos.h | 5 +++--
gcc/config/rs6000/rs6000.cc | 20 +++-
gcc/config/rs6000/rs6000.h| 19 +--
gcc/config/rs6000/rs6000.opt | 17 ++---
6 files changed, 46 insertions(+), 54 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 6757a2477ad1..6d6838735b33 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char
*name)
#pragma GCC target, we need to adjust the macros dynamically. */
void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
{
if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
summary of the flags associated with particular cpu
definitions. */
- /* rs6000_isa_flags based options. */
+ /* rs6000_isa_flags and rs6000_arch_flags based options. */
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,25 +420,27 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
if ((flags & OPTION_MASK_POWERPC64) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
- if ((flags & OPTION_MASK_MFCRF) != 0)
+ if ((flags & OPTION_MASK_POWERPC64) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
[gcc/meissner/heads/work201-submit] (39 commits) Merge commit 'refs/users/meissner/heads/work201-submit' of
The branch 'meissner/heads/work201-submit' was updated to point to: 33389c9ae8b0... Merge commit 'refs/users/meissner/heads/work201-submit' of It previously pointed to: 23957de2218d... Add ChangeLog.submit and update REVISION. Diff: Summary of changes (added commits): --- 33389c9... Merge commit 'refs/users/meissner/heads/work201-submit' of 29657ba... Add ChangeLog.submit and update REVISION. 439a88e... Add ChangeLog.meissner and REVISION. e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-submit' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-orig)] Add REVISION.
https://gcc.gnu.org/g:7ce90426fda5b13289a0aa00b79d5b4c8e7ac782 commit 7ce90426fda5b13289a0aa00b79d5b4c8e7ac782 Author: Michael Meissner Date: Mon Apr 14 15:20:36 2025 -0400 Add REVISION. 2025-04-14 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..311ed3c92ba2 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work201-orig branch
[gcc(refs/users/meissner/heads/work201-submit)] Add ChangeLog.submit and update REVISION.
https://gcc.gnu.org/g:29657baa2a83e2d9f4c1e17050820ec2d65e46e1 commit 29657baa2a83e2d9f4c1e17050820ec2d65e46e1 Author: Michael Meissner Date: Mon Apr 14 15:18:41 2025 -0400 Add ChangeLog.submit and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.submit: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.submit | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.submit b/gcc/ChangeLog.submit new file mode 100644 index ..8cada4ac5598 --- /dev/null +++ b/gcc/ChangeLog.submit @@ -0,0 +1,5 @@ + Branch work201-submit, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..e53943b0c13c 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-submit branch
[gcc(refs/users/meissner/heads/work201-submit)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:439a88e16cd12321690c81534440a41a974c5aab commit 439a88e16cd12321690c81534440a41a974c5aab Author: Michael Meissner Date: Mon Apr 14 15:11:21 2025 -0400 Add ChangeLog.meissner and REVISION. 2025-04-14 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 5 + gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 5 + gcc/c/ChangeLog.meissner | 5 + gcc/cp/ChangeLog.meissner| 5 + gcc/fortran/ChangeLog.meissner | 5 + gcc/testsuite/ChangeLog.meissner | 5 + libgcc/ChangeLog.meissner| 5 + libstdc++-v3/ChangeLog.meissner | 5 + 9 files changed, 41 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..5f8715c4844d --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work201 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index ..8fe7da956044 --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work201, baseline + +2025-04-14 Michael Meissner + + Clone branch
[gcc/meissner/heads/work201-bugs] (52 commits) Merge commit 'refs/users/meissner/heads/work201-bugs' of gi
The branch 'meissner/heads/work201-bugs' was updated to point to: 42181938b611... Merge commit 'refs/users/meissner/heads/work201-bugs' of gi It previously pointed to: 67f6869ed192... Merge commit 'refs/users/meissner/heads/work201-bugs' of gi Diff: Summary of changes (added commits): --- 4218193... Merge commit 'refs/users/meissner/heads/work201-bugs' of gi 0579ace... Add ChangeLog.bugs and update REVISION. c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh (*) e9b4cfa... Update ChangeLog.* (*) 07a339a... Use architecture flags for defining _ARCH_PWR macros. (*) 97c13da... Add rs6000 architecture masks. (*) bd351b3... xUse vector pair load/store for memcpy with -mcpu=future (*) caf3d48... Add -mcpu=future tests. (*) e82e341... Add -mcpu=future tuning support. (*) ac1f5a3... Add support for -mcpu=future (*) 256b94a... Change TARGET_MODULO to TARGET_POWER9. (*) 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. (*) 93b17d0... Change TARGET_CMPB to TARGET_POWER6. (*) ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. (*) f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. (*) abf2924... Add ChangeLog.meissner and REVISION. (*) e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-bugs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-bugs)] Merge commit 'refs/users/meissner/heads/work201-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:42181938b6119f93647495c287b66d585b349991 commit 42181938b6119f93647495c287b66d585b349991 Merge: 0579ace84fd3 67f6869ed192 Author: Michael Meissner Date: Tue Apr 15 13:29:28 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work201-bugs Diff:
[gcc(refs/users/meissner/heads/work201-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:0579ace84fd3043f4b93899cc4f9133691528735 commit 0579ace84fd3043f4b93899cc4f9133691528735 Author: Michael Meissner Date: Mon Apr 14 15:14:06 2025 -0400 Add ChangeLog.bugs and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index ..6f3c5d84f221 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,5 @@ + Branch work201-bugs, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..028186c1b5c7 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-bugs branch
[gcc r15-9496] Set znver5 issue rate to 4.
https://gcc.gnu.org/g:4a01869b963520d689fe9242cf2ff24984ea41d8 commit r15-9496-g4a01869b963520d689fe9242cf2ff24984ea41d8 Author: Jan Hubicka Date: Tue Apr 15 19:09:20 2025 +0200 Set znver5 issue rate to 4. this patch sets issue rate of znver5 to 4. With current model, unless a reservation is missing, we will never issue more than 4 instructions per cycle since that is the limit of decoders and the model does not take into acount the fact that typically code is run from op cache. gcc/ChangeLog: * config/i386/x86-tune-sched.cc (ix86_issue_rate): Set to 4 for znver5. Diff: --- gcc/config/i386/x86-tune-sched.cc | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/gcc/config/i386/x86-tune-sched.cc b/gcc/config/i386/x86-tune-sched.cc index 685a83c4311b..15d3d91a83b6 100644 --- a/gcc/config/i386/x86-tune-sched.cc +++ b/gcc/config/i386/x86-tune-sched.cc @@ -81,6 +81,14 @@ ix86_issue_rate (void) case PROCESSOR_YONGFENG: case PROCESSOR_SHIJIDADAO: case PROCESSOR_GENERIC: +/* For znver5 decoder can handle 4 or 8 instructions per cycle, + op cache 12 instruction/cycle, dispatch 8 instructions + integer rename 8 instructions and Fp 6 instructions. + + The scheduler, without understanding out of order nature of the CPU + is not going to be able to use more than 4 instructions since that + is limits of the decoders. */ +case PROCESSOR_ZNVER5: return 4; case PROCESSOR_ICELAKE_CLIENT: @@ -91,13 +99,6 @@ ix86_issue_rate (void) return 5; case PROCESSOR_SAPPHIRERAPIDS: -/* For znver5 decoder can handle 4 or 8 instructions per cycle, - op cache 12 instruction/cycle, dispatch 8 instructions - integer rename 8 instructions and Fp 6 instructions. - - The scheduler, without understanding out of order nature of the CPU - is unlikely going to be able to fill all of these. */ -case PROCESSOR_ZNVER5: return 6; default:
[gcc/meissner/heads/work201-sha] (52 commits) Merge commit 'refs/users/meissner/heads/work201-sha' of git
The branch 'meissner/heads/work201-sha' was updated to point to: 1dbb90142ed0... Merge commit 'refs/users/meissner/heads/work201-sha' of git It previously pointed to: e326d72a05dc... Merge commit 'refs/users/meissner/heads/work201-sha' of git Diff: Summary of changes (added commits): --- 1dbb901... Merge commit 'refs/users/meissner/heads/work201-sha' of git dd2a961... Add ChangeLog.sha and update REVISION. c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh (*) e9b4cfa... Update ChangeLog.* (*) 07a339a... Use architecture flags for defining _ARCH_PWR macros. (*) 97c13da... Add rs6000 architecture masks. (*) bd351b3... xUse vector pair load/store for memcpy with -mcpu=future (*) caf3d48... Add -mcpu=future tests. (*) e82e341... Add -mcpu=future tuning support. (*) ac1f5a3... Add support for -mcpu=future (*) 256b94a... Change TARGET_MODULO to TARGET_POWER9. (*) 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. (*) 93b17d0... Change TARGET_CMPB to TARGET_POWER6. (*) ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. (*) f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. (*) abf2924... Add ChangeLog.meissner and REVISION. (*) e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-sha' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-sha)] Add ChangeLog.sha and update REVISION.
https://gcc.gnu.org/g:dd2a961fa2cd81b46317c5ee798c767206f54962 commit dd2a961fa2cd81b46317c5ee798c767206f54962 Author: Michael Meissner Date: Mon Apr 14 15:16:10 2025 -0400 Add ChangeLog.sha and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.sha: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.sha | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha new file mode 100644 index ..389f91f54250 --- /dev/null +++ b/gcc/ChangeLog.sha @@ -0,0 +1,5 @@ + Branch work201-sha, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..4363e39c6b26 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-sha branch
[gcc(refs/users/meissner/heads/work201)] Change TARGET_POPCNTD to TARGET_POWER7.
https://gcc.gnu.org/g:0f365f1fe939785e1625df7d179f8452735fe02e
commit 0f365f1fe939785e1625df7d179f8452735fe02e
Author: Michael Meissner
Date: Mon Apr 14 20:23:40 2025 -0400
Change TARGET_POPCNTD to TARGET_POWER7.
This patch changes TARGET_POPCNTD to TARGET_POWER7. The -mpopcntd switch
is not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.6 (Power7).
2025-04-14 Michael Meissner
gcc/
* gcc/config/rs6000/dfp.md (cmp_internal1): Change
TARGET_POPCNTD
to TARGET_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare):
Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_POWER7): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.
Diff:
---
gcc/config/rs6000/dfp.md| 2 +-
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000-string.cc | 2 +-
gcc/config/rs6000/rs6000.cc | 8
gcc/config/rs6000/rs6000.h | 21 +++--
gcc/config/rs6000/rs6000.md | 20 ++--
6 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 59fa66ae15c8..5919149682b2 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_DFP && TARGET_POPCNTD"
+ "TARGET_DFP && TARGET_POWER7"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index dbb8520ab039..2366b2aee00a 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P6_64:
return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
- return TARGET_POPCNTD;
+ return TARGET_POWER7;
case ENB_P7_64:
- return TARGET_POPCNTD && TARGET_POWERPC64;
+ return TARGET_POWER7 && TARGET_POWERPC64;
case ENB_P8:
return TARGET_POWER8;
case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 3d2911ca08a0..703f77fa0bf1 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1949,7 +1949,7 @@ bool
expand_block_compare (rtx operands[])
{
/* TARGET_POPCNTD is already guarded at expand cmpmemsi. */
- gcc_assert (TARGET_POPCNTD);
+ gcc_assert (TARGET_POWER7);
/* For P8, this case is complicated to handle because the subtract
with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c01af37200ac..503b07339647 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1924,7 +1924,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -3918,7 +3918,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POPCNTD)
+ else if (TARGET_POWER7)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
@@ -4131,7 +4131,7 @@ rs6000_option_override_internal (bool global_init_p)
else if (TARGET_LONG_DOUBLE_128)
[gcc(refs/users/meissner/heads/work201)] Change TARGET_MODULO to TARGET_POWER9.
https://gcc.gnu.org/g:256b94af0e69fdd489b98c853d1ba8dd9952ae07
commit 256b94af0e69fdd489b98c853d1ba8dd9952ae07
Author: Michael Meissner
Date: Mon Apr 14 20:24:37 2025 -0400
Change TARGET_MODULO to TARGET_POWER9.
This patch changes TARGET_MODULO to TARGET_POWER9. The -mmodulo switch is
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 3.0 (Power9).
2025-04-14 Michael Meissner
gcc/
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_MODULO to TARGET_POWER9.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
(TARGET_POWER9): New macro.
* gcc/config/rs6000/rs6000.md (enabled attribute): Change
TARGET_MODULO
to TARGET_POWER9.
(mod3): Likewise.
(umod3): Likewise.
(divide/modulo peephole2): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000.cc | 4 ++--
gcc/config/rs6000/rs6000.h | 7 ---
gcc/config/rs6000/rs6000.md | 14 +++---
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 2366b2aee00a..d8ff7cf32dfd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P8V:
return TARGET_P8_VECTOR;
case ENB_P9:
- return TARGET_MODULO;
+ return TARGET_POWER9;
case ENB_P9_64:
- return TARGET_MODULO && TARGET_POWERPC64;
+ return TARGET_POWER9 && TARGET_POWERPC64;
case ENB_P9V:
return TARGET_P9_VECTOR;
case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 503b07339647..8d97b265ac91 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3888,7 +3888,7 @@ rs6000_option_override_internal (bool global_init_p)
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno- to disable the code. */
- if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+ if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
else if (TARGET_P9_MINMAX)
{
@@ -22377,7 +22377,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
*total = rs6000_cost->divsi;
}
/* Add in shift and subtract for MOD unless we have a mod instruction. */
- if ((!TARGET_MODULO
+ if ((!TARGET_POWER9
|| (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode)))
&& (code == MOD || code == UMOD))
*total += COSTS_N_INSNS (2);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f1da5d31441a..c2f1910b0ea2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -463,9 +463,9 @@ extern int rs6000_vector_align[];
#define TARGET_FCTIWUZ TARGET_POWER7
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD TARGET_POWER9
/* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.
*/
#define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -504,6 +504,7 @@ extern int rs6000_vector_align[];
#define TARGET_POWER5X TARGET_FPRND
#define TARGET_POWER6 TARGET_CMPB
#define TARGET_POWER7 TARGET_POPCNTD
+#define TARGET_POWER9 TARGET_MODULO
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_. The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 87ec37a9f8e4..db1b6c2d1164 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@
(const_int 1)
(and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
(const_int 1)
(and (eq_attr "isa" "p9v")
@@ -3457,7 +3457,7 @@
|| INTVAL (operands[2]) <= 0
|| (i = exact_log2 (INTVAL (operands[2]))) < 0)
{
- if (!TARGET_MODULO)
+ if (!TARGET_POWER9)
FAIL;
operands[2] = force_reg (mode, operands[2]);
@@ -3491,7 +3491,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
(mod:GPR (match_oper
[gcc(refs/users/meissner/heads/work201)] xUse vector pair load/store for memcpy with -mcpu=future
https://gcc.gnu.org/g:bd351b31d853952fde73738ec867ee8906d7f4e7
commit bd351b31d853952fde73738ec867ee8906d7f4e7
Author: Michael Meissner
Date: Mon Apr 14 20:30:13 2025 -0400
xUse vector pair load/store for memcpy with -mcpu=future
In the development for the power10 processor, GCC did not enable using the
load
vector pair and store vector pair instructions when optimizing things like
memory copy. This patch enables using those instructions if -mcpu=future is
used.
2025-04-14 Michael Meissner
gcc/
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable
using
load vector pair and store vector pair instructions for memory copy
operations.
(POWERPC_MASKS): Make the bit for enabling using load vector pair
and
store vector pair operations set and reset when the PowerPC
processor is
changed.
* gcc/config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable
-mblock-ops-vector-pair from influcing .machine selection.
gcc/testsuite/
* gcc.target/powerpc/future-3.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 4 +++-
gcc/config/rs6000/rs6000.cc | 2 +-
gcc/testsuite/gcc.target/powerpc/future-3.c | 22 ++
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 228d0b5e7b54..063591f5c094 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -84,7 +84,8 @@
| OPTION_MASK_POWER11)
#define FUTURE_MASKS_SERVER(POWER11_MASKS_SERVER \
-| OPTION_MASK_FUTURE)
+| OPTION_MASK_FUTURE \
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -114,6 +115,7 @@
/* Mask of all options to set the default isa flags based on -mcpu=. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC\
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4cea1775f110..011f67d290e9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5908,7 +5908,7 @@ rs6000_machine_from_flags (void)
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
-| OPTION_MASK_ALTIVEC);
+| OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR);
if ((flags & (FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
return "future";
diff --git a/gcc/testsuite/gcc.target/powerpc/future-3.c
b/gcc/testsuite/gcc.target/powerpc/future-3.c
new file mode 100644
index ..afa8b96d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-3.c
@@ -0,0 +1,22 @@
+/* 32-bit doesn't generate vector pair instructions. */
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test to see that memcpy will use load/store vector pair with
+ -mcpu=future. */
+
+#ifndef SIZE
+#define SIZE 4
+#endif
+
+extern vector double to[SIZE], from[SIZE];
+
+void
+copy (void)
+{
+ __builtin_memcpy (to, from, sizeof (to));
+ return;
+}
+
+/* { dg-final { scan-assembler {\mlxvpx?\M} } } */
+/* { dg-final { scan-assembler {\mstxvpx?\M} } } */
[gcc(refs/users/meissner/heads/work201)] Add rs6000 architecture masks.
https://gcc.gnu.org/g:97c13dac80e918b2d23d210a9c7b3140c861e4b5 commit 97c13dac80e918b2d23d210a9c7b3140c861e4b5 Author: Michael Meissner Date: Mon Apr 14 20:31:44 2025 -0400 Add rs6000 architecture masks. This patch begins the journey to move architecture bits that are not user ISA options from rs6000_isa_flags to a new targt variable rs6000_arch_flags. The intention is to remove switches that are currently isa options, but the user should not be using this particular option. For example, we want users to use -mcpu=power10 and not just -mpower10. This patch also changes the target_clones support to use an architecture mask instead of isa bits. This patch also switches the handling of .machine to use architecture masks if they exist (power4 through power11). All of the other PowerPCs will continue to use the existing code for setting the .machine option. I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. The only difference in this patch compared to the first version posted on November 6th is that I the correct attribution and copyright year (i.e. that I created rs6000-arch.def in 2024). Can I install this patch on the GCC 15 trunk? 2025-04-14 Michael Meissner gcc/ * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name. * config/rs6000/rs6000-arch.def: New file. * config/rs6000/rs6000.cc (struct clone_map): Switch to using architecture masks instead of ISA masks. (rs6000_clone_map): Likewise. (rs6000_print_isa_options): Add an architecture flags argument, change all callers. (get_arch_flag): New function. (rs6000_debug_reg_global): Update rs6000_print_isa_options calls. (rs6000_option_override_internal): Likewise. (rs6000_machine_from_flags): Switch to using architecture masks instead of ISA masks. (struct rs6000_arch_mask): New structure. (rs6000_arch_masks): New table of architecutre masks and names. (rs6000_function_specific_save): Save architecture flags. (rs6000_function_specific_restore): Restore architecture flags. (rs6000_function_specific_print): Update rs6000_print_isa_options calls. (rs6000_print_options_internal): Add architecture flags options. (rs6000_clone_priority): Switch to using architecture masks instead of ISA masks. (rs6000_can_inline_p): Don't allow inling if the callee requires a newer architecture than the caller. * config/rs6000/rs6000.h: Use rs6000-arch.def to create the architecture masks. * config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable. (x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags. Diff: --- gcc/config/rs6000/default64.h | 11 ++ gcc/config/rs6000/rs6000-arch.def | 49 + gcc/config/rs6000/rs6000.cc | 222 +++--- gcc/config/rs6000/rs6000.h| 24 + gcc/config/rs6000/rs6000.opt | 8 ++ 5 files changed, 277 insertions(+), 37 deletions(-) diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 7f6001ded852..188f5c1d1378 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -21,6 +21,7 @@ along with GCC; see the file COPYING3. If not see #define RS6000_CPU(NAME, CPU, FLAGS) #include "rs6000-cpus.def" #undef RS6000_CPU +#undef TARGET_CPU_DEFAULT #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) #undef TARGET_DEFAULT @@ -28,10 +29,20 @@ along with GCC; see the file COPYING3. If not see | MASK_LITTLE_ENDIAN) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower8" +#define TARGET_CPU_DEFAULT "power8" + #else #undef TARGET_DEFAULT #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower4" + +#if (TARGET_DEFAULT & MASK_POWERPC64) +#define TARGET_CPU_DEFAULT "powerpc64" + +#else +#define TARGET_CPU_DEFAULT "powerpc" +#endif + #endif diff --git a/gcc/config/rs6000/rs6000-arch.def b/gcc/config/rs6000/rs6000-arch.def new file mode 100644 index ..c0dbc5834333 --- /dev/null +++ b/gcc/config/rs6000/rs6000-arch.def @
[gcc(refs/users/meissner/heads/work201)] Update ChangeLog.*
https://gcc.gnu.org/g:e9b4cfa9b446c2e64f1cce3a13a4b1fa2a38f313 commit e9b4cfa9b446c2e64f1cce3a13a4b1fa2a38f313 Author: Michael Meissner Date: Mon Apr 14 20:35:57 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 396 + 1 file changed, 396 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 8fe7da956044..9257f309048e 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,5 +1,401 @@ + Branch work201, patch #21 + +Use architecture flags for defining _ARCH_PWR macros. + +For the newer architectures, this patch changes GCC to define the _ARCH_PWR +macros using the new architecture flags instead of relying on isa options like +-mpower10. + +The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were removed. +The -mpower11 and -mfuture options were removed completely, since they were just +added in GCC 15. The other two options were marked as WarnRemoved, and the +various ISA bits were removed. + +TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were re-defined +to use the architeture bits instead of the ISA bits. + +There are other internal isa bits that aren't removed with this patch because +the built-in function support uses those bits. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +Can I install this patch on the GCC 15 trunk? + +2025-04-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to + use architecture flags instead of ISA flags for setting most of the + _ARCH_PWR* macros. + (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call. + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove + OPTION_MASK_POWER8. + (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10. + (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11. + (FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE. + (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, + OPTION_MASK_POWER11, and OPTION_MASK_FUTURE. + * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update + declaration. + (rs6000_target_modify_macros_ptr): Likewise. + * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise. + (rs6000_option_override_internal): Use architecture flags instead of ISA + flags. + (rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which are + no longer in the ISA flags. + (rs6000_pragma_target_parse): Use architecture flags as well as ISA + flags. + * config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use architecture + flags. + (TARGET_POWER5X): Likewise. + (TARGET_POWER6): Likewise. + (TARGET_POWER7): Likewise. + (TARGET_POWER8): Likewise. + (TARGET_POWER9): Likewise. + (TARGET_POWER10): New macro. + (TARGET_POWER11): Likewise. + (TARGET_FUTURE): Likewise. + * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits. + (-mpower10): Likewise. + (-mpower11): Likewise. + (-mfuture): Likewise. + + Branch work201, patch #20 + +Add rs6000 architecture masks. + +This patch begins the journey to move architecture bits that are not user ISA +options from rs6000_isa_flags to a new targt variable rs6000_arch_flags. The +intention is to remove switches that are currently isa options, but the user +should not be using this particular option. For example, we want users to use +-mcpu=power10 and not just -mpower10. + +This patch also changes the target_clones support to use an architecture mask +instead of isa bits. + +This patch also switches the handling of .machine to use architecture masks if +they exist (power4 through power11). All of the other PowerPCs will continue to +use the existing code for setting the .machine option. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +In addition, I constructed a test case that used every archiecture define (like +_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran +this test for all supported combinations of -mcpu, big/little endian, and 32/64 +bit support. Every single instance generated exactly the same code with the +patches installed compared to the compiler before installing the patches. + +The only difference in this patch compared to the first version posted on +November 6th is that I the correct attribution and copyright year (i.e. that I +created rs6000-arch.def in 2024). + +Can I install this patch on the GCC 15 trunk? + +2025-04-14 Michael Meissner + +gcc/ + + * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name. + * config/rs6000/rs6000-arch.def: New file. + * conf
[gcc/meissner/heads/work201] (50 commits) Merge commit 'refs/users/meissner/heads/work201' of git+ssh
The branch 'meissner/heads/work201' was updated to point to: c9c681f4670f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh It previously pointed to: a6ffd5060cdf... Update ChangeLog.* Diff: Summary of changes (added commits): --- c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh e9b4cfa... Update ChangeLog.* 07a339a... Use architecture flags for defining _ARCH_PWR macros. 97c13da... Add rs6000 architecture masks. bd351b3... xUse vector pair load/store for memcpy with -mcpu=future caf3d48... Add -mcpu=future tests. e82e341... Add -mcpu=future tuning support. ac1f5a3... Add support for -mcpu=future 256b94a... Change TARGET_MODULO to TARGET_POWER9. 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. 93b17d0... Change TARGET_CMPB to TARGET_POWER6. ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. abf2924... Add ChangeLog.meissner and REVISION. e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201)] Merge commit 'refs/users/meissner/heads/work201' of git+ssh://gcc.gnu.org/git/gcc into me/work201
https://gcc.gnu.org/g:c9c681f4670f59b3b33b4c72187543de984873cd commit c9c681f4670f59b3b33b4c72187543de984873cd Merge: e9b4cfa9b446 a6ffd5060cdf Author: Michael Meissner Date: Tue Apr 15 13:24:57 2025 -0400 Merge commit 'refs/users/meissner/heads/work201' of git+ssh://gcc.gnu.org/git/gcc into me/work201 Diff:
[gcc(refs/users/meissner/heads/work201-orig)] Merge commit 'refs/users/meissner/heads/work201-orig' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:8ccd7506bd8fa4017e4d85089d6f4736590e565a commit 8ccd7506bd8fa4017e4d85089d6f4736590e565a Merge: 7ce90426fda5 7cfd776ecfda Author: Michael Meissner Date: Tue Apr 15 13:26:46 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-orig' of git+ssh://gcc.gnu.org/git/gcc into me/work201-orig Diff:
[gcc(refs/users/meissner/heads/work201-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:31f284d24ddf52c5d49681a5bba7cc3dc5b3d244 commit 31f284d24ddf52c5d49681a5bba7cc3dc5b3d244 Author: Michael Meissner Date: Mon Apr 14 15:12:24 2025 -0400 Add ChangeLog.dmf and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index ..211e3edc44fc --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,5 @@ + Branch work201-dmf, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..c257804fb56a 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-dmf branch
[gcc/meissner/heads/work201-dmf] (52 commits) Merge commit 'refs/users/meissner/heads/work201-dmf' of git
The branch 'meissner/heads/work201-dmf' was updated to point to: f59f55032eff... Merge commit 'refs/users/meissner/heads/work201-dmf' of git It previously pointed to: 6f82e02caa34... Merge commit 'refs/users/meissner/heads/work201-dmf' of git Diff: Summary of changes (added commits): --- f59f550... Merge commit 'refs/users/meissner/heads/work201-dmf' of git 31f284d... Add ChangeLog.dmf and update REVISION. c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh (*) e9b4cfa... Update ChangeLog.* (*) 07a339a... Use architecture flags for defining _ARCH_PWR macros. (*) 97c13da... Add rs6000 architecture masks. (*) bd351b3... xUse vector pair load/store for memcpy with -mcpu=future (*) caf3d48... Add -mcpu=future tests. (*) e82e341... Add -mcpu=future tuning support. (*) ac1f5a3... Add support for -mcpu=future (*) 256b94a... Change TARGET_MODULO to TARGET_POWER9. (*) 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. (*) 93b17d0... Change TARGET_CMPB to TARGET_POWER6. (*) ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. (*) f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. (*) abf2924... Add ChangeLog.meissner and REVISION. (*) e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-dmf)] Merge commit 'refs/users/meissner/heads/work201-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work20
https://gcc.gnu.org/g:f59f55032eff59b983d4864349cae307331e1ffc commit f59f55032eff59b983d4864349cae307331e1ffc Merge: 31f284d24ddf 6f82e02caa34 Author: Michael Meissner Date: Tue Apr 15 13:30:37 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work201-dmf Diff:
[gcc/meissner/heads/work201-orig] (38 commits) Merge commit 'refs/users/meissner/heads/work201-orig' of gi
The branch 'meissner/heads/work201-orig' was updated to point to: 8ccd7506bd8f... Merge commit 'refs/users/meissner/heads/work201-orig' of gi It previously pointed to: 7cfd776ecfda... Add REVISION. Diff: Summary of changes (added commits): --- 8ccd750... Merge commit 'refs/users/meissner/heads/work201-orig' of gi 7ce9042... Add REVISION. e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-orig' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-submit)] Merge commit 'refs/users/meissner/heads/work201-submit' of git+ssh://gcc.gnu.org/git/gcc into me/wor
https://gcc.gnu.org/g:33389c9ae8b042b207c81a2ec67a8b20e6fb3b01 commit 33389c9ae8b042b207c81a2ec67a8b20e6fb3b01 Merge: 29657baa2a83 23957de2218d Author: Michael Meissner Date: Tue Apr 15 13:27:56 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-submit' of git+ssh://gcc.gnu.org/git/gcc into me/work201-submit Diff:
[gcc/meissner/heads/work201-libs] (52 commits) Merge commit 'refs/users/meissner/heads/work201-libs' of gi
The branch 'meissner/heads/work201-libs' was updated to point to: 416cebee1f2b... Merge commit 'refs/users/meissner/heads/work201-libs' of gi It previously pointed to: c9ef15b5cf8e... Merge commit 'refs/users/meissner/heads/work201-libs' of gi Diff: Summary of changes (added commits): --- 416cebe... Merge commit 'refs/users/meissner/heads/work201-libs' of gi 3ae9363... Add ChangeLog.libs and update REVISION. c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh (*) e9b4cfa... Update ChangeLog.* (*) 07a339a... Use architecture flags for defining _ARCH_PWR macros. (*) 97c13da... Add rs6000 architecture masks. (*) bd351b3... xUse vector pair load/store for memcpy with -mcpu=future (*) caf3d48... Add -mcpu=future tests. (*) e82e341... Add -mcpu=future tuning support. (*) ac1f5a3... Add support for -mcpu=future (*) 256b94a... Change TARGET_MODULO to TARGET_POWER9. (*) 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. (*) 93b17d0... Change TARGET_CMPB to TARGET_POWER6. (*) ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. (*) f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. (*) abf2924... Add ChangeLog.meissner and REVISION. (*) e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-libs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-libs)] Merge commit 'refs/users/meissner/heads/work201-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:416cebee1f2b0c86fc934391f1941cb6aa3121d9 commit 416cebee1f2b0c86fc934391f1941cb6aa3121d9 Merge: 3ae93633aa1f c9ef15b5cf8e Author: Michael Meissner Date: Tue Apr 15 13:31:43 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work201-libs Diff:
[gcc r15-9497] cobol/119302 - transform gcobol.3 name during install, install as gcobol-io.3
https://gcc.gnu.org/g:248e228fecdfb68833481eff8c3c0c7aa9703a8d commit r15-9497-g248e228fecdfb68833481eff8c3c0c7aa9703a8d Author: Richard Biener Date: Sat Mar 15 15:56:49 2025 +0100 cobol/119302 - transform gcobol.3 name during install, install as gcobol-io.3 The following installs gcobol.3 as gcobol-io.3 and applies program-transform-name to the gcobol-io part. This follows naming of the pdf and the html variants. It also uses $(man1ext) and $(man3ext) consistently. PR cobol/119302 gcc/cobol/ * Make-lang.in (GCOBOLIO_INSTALL_NAME): Define. Use $(GCOBOLIO_INSTALL_NAME) for gcobol.3 manpage source upon install. Diff: --- gcc/cobol/Make-lang.in | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/cobol/Make-lang.in b/gcc/cobol/Make-lang.in index 422ebe28b213..9b74dd39b573 100644 --- a/gcc/cobol/Make-lang.in +++ b/gcc/cobol/Make-lang.in @@ -35,6 +35,7 @@ # - define the names for selecting the language in LANGUAGES. GCOBOL_INSTALL_NAME := $(shell echo gcobol|sed '$(program_transform_name)') +GCOBOLIO_INSTALL_NAME := $(shell echo gcobol-io|sed '$(program_transform_name)') GCOBOL_TARGET_INSTALL_NAME := $(target_noncanonical)-$(shell echo gcobol|sed '$(program_transform_name)') GCOBC_INSTALL_NAME := $(shell echo gcobc|sed '$(program_transform_name)') @@ -293,7 +294,7 @@ cobol.install-common: installdirs cobol.install-man: installdirs $(INSTALL_DATA) $(srcdir)/cobol/gcobol.1 $(DESTDIR)$(man1dir)/$(GCOBOL_INSTALL_NAME)$(man1ext) - $(INSTALL_DATA) $(srcdir)/cobol/gcobol.3 $(DESTDIR)$(man3dir)/ + $(INSTALL_DATA) $(srcdir)/cobol/gcobol.3 $(DESTDIR)$(man3dir)/$(GCOBOLIO_INSTALL_NAME)$(man3ext) cobol.install-info: @@ -342,8 +343,8 @@ cobol.uninstall: rm -rf $(DESTDIR)$(bindir)/$(GCOBOL_INSTALL_NAME)$(exeext) \ $(DESTDIR)$(bindir)/$(GCOBC_INSTALL_NAME) \ $(DESTDIR)$(datadir)/gcobol/\ - $(DESTDIR)$(man1dir)/$(GCOBOL_INSTALL_NAME).1 \ - $(DESTDIR)$(man3dir)/gcobol.3 + $(DESTDIR)$(man1dir)/$(GCOBOL_INSTALL_NAME)$(man1ext) \ + $(DESTDIR)$(man3dir)/$(GCOBOLIO_INSTALL_NAME)$(man3ext) cobol.man: cobol.srcman:
[gcc(refs/users/meissner/heads/work201-test)] Merge commit 'refs/users/meissner/heads/work201-test' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:50f37f21569f7ab4b6f0e8a587f67f24fd77df94 commit 50f37f21569f7ab4b6f0e8a587f67f24fd77df94 Merge: 236c72f00468 8616368e9404 Author: Michael Meissner Date: Tue Apr 15 13:36:51 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-test' of git+ssh://gcc.gnu.org/git/gcc into me/work201-test Diff:
[gcc/meissner/heads/work201-test] (52 commits) Merge commit 'refs/users/meissner/heads/work201-test' of gi
The branch 'meissner/heads/work201-test' was updated to point to: 50f37f21569f... Merge commit 'refs/users/meissner/heads/work201-test' of gi It previously pointed to: 8616368e9404... Merge commit 'refs/users/meissner/heads/work201-test' of gi Diff: Summary of changes (added commits): --- 50f37f2... Merge commit 'refs/users/meissner/heads/work201-test' of gi 236c72f... Add ChangeLog.test and update REVISION. c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh (*) e9b4cfa... Update ChangeLog.* (*) 07a339a... Use architecture flags for defining _ARCH_PWR macros. (*) 97c13da... Add rs6000 architecture masks. (*) bd351b3... xUse vector pair load/store for memcpy with -mcpu=future (*) caf3d48... Add -mcpu=future tests. (*) e82e341... Add -mcpu=future tuning support. (*) ac1f5a3... Add support for -mcpu=future (*) 256b94a... Change TARGET_MODULO to TARGET_POWER9. (*) 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. (*) 93b17d0... Change TARGET_CMPB to TARGET_POWER6. (*) ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. (*) f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. (*) abf2924... Add ChangeLog.meissner and REVISION. (*) e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:236c72f0046881524700176eaf9adeb2c7e87102 commit 236c72f0046881524700176eaf9adeb2c7e87102 Author: Michael Meissner Date: Mon Apr 14 15:17:00 2025 -0400 Add ChangeLog.test and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index ..b7353453a268 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,5 @@ + Branch work201-test, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..a43f066a082a 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-test branch
[gcc(refs/users/meissner/heads/work201-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:6ae8a833f13f18e84fadd2ddac2b3958257efcb8 commit 6ae8a833f13f18e84fadd2ddac2b3958257efcb8 Author: Michael Meissner Date: Mon Apr 14 15:13:15 2025 -0400 Add ChangeLog.vpair and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 5 + gcc/REVISION| 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index ..07257f300349 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,5 @@ + Branch work201-vpair, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..260696cdbbdd 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-vpair branch
[gcc/meissner/heads/work201-vpair] (52 commits) Merge commit 'refs/users/meissner/heads/work201-vpair' of g
The branch 'meissner/heads/work201-vpair' was updated to point to: fcbe6d57ecc5... Merge commit 'refs/users/meissner/heads/work201-vpair' of g It previously pointed to: 8092330895ee... Merge commit 'refs/users/meissner/heads/work201-vpair' of g Diff: Summary of changes (added commits): --- fcbe6d5... Merge commit 'refs/users/meissner/heads/work201-vpair' of g 6ae8a83... Add ChangeLog.vpair and update REVISION. c9c681f... Merge commit 'refs/users/meissner/heads/work201' of git+ssh (*) e9b4cfa... Update ChangeLog.* (*) 07a339a... Use architecture flags for defining _ARCH_PWR macros. (*) 97c13da... Add rs6000 architecture masks. (*) bd351b3... xUse vector pair load/store for memcpy with -mcpu=future (*) caf3d48... Add -mcpu=future tests. (*) e82e341... Add -mcpu=future tuning support. (*) ac1f5a3... Add support for -mcpu=future (*) 256b94a... Change TARGET_MODULO to TARGET_POWER9. (*) 0f365f1... Change TARGET_POPCNTD to TARGET_POWER7. (*) 93b17d0... Change TARGET_CMPB to TARGET_POWER6. (*) ed0d85b... Change TARGET_FPRND to TARGET_POWER5X. (*) f9fc96e... Change TARGET_POPCNTB to TARGET_POWER5. (*) abf2924... Add ChangeLog.meissner and REVISION. (*) e2011ab... Set ADDSS cost to 3 for znver5 (*) 25775e7... libstdc++: Do not define __cpp_lib_ranges_iota in (*) df59bf2... libstdc++: Do not declare namespace ranges in unc (*) edb4867... RISC-V: vsetvl: elide abnormal edges from LCM computations (*) 517f7e3... RISC-V: Do not lift up vsetvl into non-transparent blocks [ (*) f62e5d7... libstdc++: Implement formatter for ranges and range_formatt (*) a039bab... libgcobol: mark riscv64-*-linux* as supported target (*) 99cd28c... Fortran/OpenMP: Support automatic mapping allocatable compo (*) 6d9fdf4... Locality cloning pass: -fipa-reorder-for-locality (*) b4cf695... ipa-bit-cp: Fix adjusting value according to mask (PR119803 (*) 074b2b0... d: Fix internal compiler error: in visit, at d/decl.cc:838 (*) 369461d... c++: prev declared hidden tmpl friend inst, cont [PR119807] (*) f5ed7d1... d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2o (*) bf115fd... ipa-cp: Fix up ipcp_print_widest_int (*) 0756511... tailc: Fix up musttail calls vs. -fsanitize=thread [PR11980 (*) 039b566... Wbuiltin-declaration-mismatch-4.c: accept long long in warn (*) a591629... testsuite: Fix up ipa/pr119318.c test [PR119318] (*) 05d3aeb... libstdc++: Fix std::string construction from volatile char* (*) 8a20889... libstdc++: Enable __gnu_test::test_container constructor fo (*) 69ffddd... libgcobol: Handle long double as an alternate IEEE754 quad (*) fc89b1f... Doc: always_inline attribute vs multiple TUs and LTO [PR113 (*) 764f023... c++: shortcut constexpr vector ctor [PR113835] (*) fa58ff2... Revert documents from r11-344-g0fec3f62b9bfc0 (*) f7a2f0a... Doc: clarify -march=pentiumpro has no MMX support [PR42683] (*) 9f3d250... Daily bump. (*) fe283db... GCN, nvptx: Support '-mfake-exceptions', and use it for off (*) 6c0ea84... Add 'throw', dead code test cases for GCN, nvptx target and (*) 1daf570... Add 'throw', caught test cases for GCN, nvptx target and Op (*) 1362d9d... Add 'throw' test cases for GCN, nvptx target and OpenACC, O (*) 27f88cc... Add 'std::bad_cast' exception, dead code test cases for GCN (*) 00cde16... Add 'std::bad_cast' exception, caught test cases for GCN, n (*) 0e68f49... Add 'std::bad_cast' exception test cases for GCN, nvptx tar (*) aa3e72f... Add test cases for exception handling constructs in dead co (*) a304c88... Add PR119692 "C++ 'typeinfo', 'vtable' vs. OpenACC, OpenMP (*) 785448f... Add 'g++.target/gcn/gcn.exp' for GCN-specific C++ test case (*) 8621554... Polish 'dg-output-file' test logs (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-vpair' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-vpair)] Merge commit 'refs/users/meissner/heads/work201-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:fcbe6d57ecc55f7f415d8ad9e22e809eef4a05dd commit fcbe6d57ecc55f7f415d8ad9e22e809eef4a05dd Merge: 6ae8a833f13f 8092330895ee Author: Michael Meissner Date: Tue Apr 15 13:38:44 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work201-vpair Diff:
[gcc(refs/users/meissner/heads/work201-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:8e650b368108ec6e442ba2216b9b226aae3267b2 commit 8e650b368108ec6e442ba2216b9b226aae3267b2 Author: Michael Meissner Date: Mon Apr 14 15:13:15 2025 -0400 Add ChangeLog.vpair and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 5 + gcc/REVISION| 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index ..07257f300349 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,5 @@ + Branch work201-vpair, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..260696cdbbdd 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-vpair branch
[gcc r15-9491] RISC-V: Do not lift up vsetvl into non-transparent blocks [PR119547].
https://gcc.gnu.org/g:517f7e3f02b4c945d2b4bdabb490961cf986391e
commit r15-9491-g517f7e3f02b4c945d2b4bdabb490961cf986391e
Author: Robin Dapp
Date: Fri Apr 4 17:06:44 2025 +0200
RISC-V: Do not lift up vsetvl into non-transparent blocks [PR119547].
When lifting up a vsetvl into a block we currently don't consider the
block's transparency with respect to the vsetvl as in other parts of the
pass. This patch does not perform the lift when transparency is not
guaranteed.
This condition is more restrictive than necessary as we can still
perform a vsetvl lift if the conflicting register is only every used
in vsetvls and no regular insns but given how late we are in the GCC 15
cycle it seems better to defer this. Therefore
gcc.target/riscv/rvv/vsetvl/avl_single-68.c is XFAILed for now.
This issue was found in OpenCV where it manifests as a runtime error.
Zhijin Zeng debugged PR119547 and provided an initial patch.
Reported-By: 曾治金
PR target/119547
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(pre_vsetvl::earliest_fuse_vsetvl_info):
Do not perform lift if block is not transparent.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-68.c: xfail.
* g++.target/riscv/rvv/autovec/pr119547.C: New test.
* g++.target/riscv/rvv/autovec/pr119547-2.C: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Adjust.
Diff:
---
gcc/config/riscv/riscv-vsetvl.cc | 12 ++
.../g++.target/riscv/rvv/autovec/pr119547-2.C | 212 +
.../g++.target/riscv/rvv/autovec/pr119547.C| 82
.../gcc.target/riscv/rvv/vsetvl/avl_single-68.c| 8 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 4 +-
5 files changed, 315 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 0ac2538f596f..c4046bcc3455 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3022,6 +3022,18 @@ pre_vsetvl::earliest_fuse_vsetvl_info (int iter)
continue;
}
+ /* We cannot lift a vsetvl into the source block if the block is
+not transparent WRT to it.
+This is too restrictive for blocks where a register's use only
+feeds into vsetvls and no regular insns. One example is the
+test rvv/vsetvl/avl_single-68.c which is currently XFAILed for
+that reason.
+In order to support this case we'd need to check the vsetvl's
+AVL operand's uses in the source block and make sure they are
+only used in other vsetvls. */
+ if (!bitmap_bit_p (m_transp[eg->src->index], expr_index))
+ continue;
+
if (dump_file && (dump_flags & TDF_DETAILS))
{
fprintf (dump_file,
diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/pr119547-2.C
b/gcc/testsuite/g++.target/riscv/rvv/autovec/pr119547-2.C
new file mode 100644
index ..1b98d3d0c32b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/pr119547-2.C
@@ -0,0 +1,212 @@
+/* { dg-do run { target rv64 } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d
--param=logical-op-non-short-circuit=0" } */
+
+#include
+
+using v_uint8 = vuint8m2_t;
+using v_int8 = vint8m2_t;
+using v_uint16 = vuint16m2_t;
+using v_int16 = vint16m2_t;
+using v_uint32 = vuint32m2_t;
+using v_int32 = vint32m2_t;
+using v_uint64 = vuint64m2_t;
+using v_int64 = vint64m2_t;
+using v_float32 = vfloat32m2_t;
+using v_float64 = vfloat64m2_t;
+
+using uchar = unsigned char;
+using schar = signed char;
+using ushort = unsigned short;
+using uint = unsigned int;
+using uint64 = unsigned long int;
+using int64 = long int;
+
+struct Size
+{
+ int width;
+ int height;
+};
+
+template struct VTraits;
+
+template <> struct VTraits
+{
+ static inline int vlanes () { return __riscv_vsetvlmax_e32m1 (); }
+ using lane_type = int32_t;
+ static const int max_nlanes = 1024 / 32 * 2;
+};
+template <> struct VTraits
+{
+ static inline int vlanes () { return __riscv_vsetvlmax_e32m2 (); }
+ using lane_type = int32_t;
+ static const int max_nlanes = 1024 / 32 * 2;
+};
+template <> struct VTraits
+{
+ static inline int vlanes () { return __riscv_vsetvlmax_e32m4 (); }
+ using lane_type = int32_t;
+ static const int max_nlanes = 1024 / 32 * 2;
+};
+template <> struct VTraits
+{
+ static inline int vlanes () { return __riscv_vsetvlmax_e32m8 (); }
+ using lane_type = int32_t;
+ static const int max_nlanes = 1024 / 32 * 2;
+};
+
+template <> struct VTraits
+{
+ static inline int vlanes () { return __riscv_vsetvlmax_e64m1 (); }
+ using lane_type = double;
+ static const int max_nlanes = 102
[gcc r15-9501] c++: constexpr, trivial, and non-alias target [PR111075]
https://gcc.gnu.org/g:628aecb050bbbc4bb0bd4468c474623e20d64e21 commit r15-9501-g628aecb050bbbc4bb0bd4468c474623e20d64e21 Author: Jason Merrill Date: Tue Apr 15 11:23:57 2025 -0400 c++: constexpr, trivial, and non-alias target [PR111075] On Darwin and other targets with !can_alias_cdtor, we instead go to maybe_thunk_ctor, which builds a thunk function that calls the general constructor. And then cp_fold tries to constant-evaluate that call, and we ICE because we don't expect to ever be asked to constant-evaluate a call to a trivial function. No new test because this fixes g++.dg/torture/tail-padding1.C on affected targets. PR c++/111075 gcc/cp/ChangeLog: * constexpr.cc (cxx_eval_call_expression): Allow trivial call from a thunk. Diff: --- gcc/cp/constexpr.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc index dc59f59aa3f3..4346b29abc68 100644 --- a/gcc/cp/constexpr.cc +++ b/gcc/cp/constexpr.cc @@ -3103,6 +3103,9 @@ cxx_eval_call_expression (const constexpr_ctx *ctx, tree t, we can only get a trivial function here with -fno-elide-constructors. */ gcc_checking_assert (!trivial_fn_p (fun) || !flag_elide_constructors + /* Or it's a call from maybe_thunk_body (111075). */ + || (TREE_CODE (t) == CALL_EXPR ? CALL_FROM_THUNK_P (t) + : AGGR_INIT_FROM_THUNK_P (t)) /* We don't elide constructors when processing a noexcept-expression. */ || cp_noexcept_operand);
[gcc r15-9502] Docs: Address -fivopts, -O0, and -Q confusion [PR71094]
https://gcc.gnu.org/g:d91aab4dd6814ca54c211a93fec3f072745a52c4
commit r15-9502-gd91aab4dd6814ca54c211a93fec3f072745a52c4
Author: Sandra Loosemore
Date: Tue Apr 15 18:37:37 2025 +
Docs: Address -fivopts, -O0, and -Q confusion [PR71094]
There's a blurb at the top of the "Optimize Options" node telling
people that most optimization options are completely disabled at -O0
and a similar blurb in the entry for -Og, but nothing at the entry for
-O0. Since this is a continuing point of confusion it seems wise to
duplicate the information in all the places users are likely to look
for it.
gcc/ChangeLog
PR tree-optimization/71094
* doc/invoke.texi (Optimize Options): Document that -fivopts is
enabled at -O1 and higher. Add blurb about -O0 causing GCC to
completely ignore most optimization options.
Diff:
---
gcc/doc/invoke.texi | 9 +
1 file changed, 9 insertions(+)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b99da94dca15..0b6644b03154 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12746,6 +12746,7 @@ complexity than at @option{-O}.
-fipa-pure-const
-fipa-reference
-fipa-reference-addressable
+-fivopts
-fmerge-constants
-fmove-loop-invariants
-fmove-loop-stores
@@ -12854,6 +12855,13 @@ by @option{-O2} and also turns on the following
optimization flags:
Reduce compilation time and make debugging produce the expected
results. This is the default.
+At @option{-O0}, GCC completely disables most optimization passes;
+they are not run even if you explicitly enable them on the command
+line, or are listed by @option{-Q --help=optimizers} as being enabled by
+default. Many optimizations performed by GCC depend on code analysis
+or canonicalization passes that are enabled by @option{-O}, and it would
+not be useful to run individual optimization passes in isolation.
+
@opindex Os
@item -Os
Optimize for size. @option{-Os} enables all @option{-O2} optimizations
@@ -14306,6 +14314,7 @@ Enabled by default at @option{-O1} and higher.
@item -fivopts
Perform induction variable optimizations (strength reduction, induction
variable merging and induction variable elimination) on trees.
+Enabled by default at @option{-O1} and higher.
@opindex ftree-parallelize-loops
@item -ftree-parallelize-loops=n
[gcc r15-9503] x86: Update gcc.target/i386/apx-interrupt-1.c
https://gcc.gnu.org/g:5ed2fa4768f3d318b8ace5bd4a095596e06fad7b
commit r15-9503-g5ed2fa4768f3d318b8ace5bd4a095596e06fad7b
Author: H.J. Lu
Date: Mon Apr 14 15:49:26 2025 -0700
x86: Update gcc.target/i386/apx-interrupt-1.c
ix86_add_cfa_restore_note omits the REG_CFA_RESTORE REG note for registers
pushed in red-zone. Since
commit 0a074b8c7e79f9d9359d044f1499b0a9ce9d2801
Author: H.J. Lu
Date: Sun Apr 13 12:20:42 2025 -0700
APX: Don't use red-zone with 32 GPRs and no caller-saved registers
disabled red-zone, update gcc.target/i386/apx-interrupt-1.c to expect
31 .cfi_restore directives.
PR target/119784
* gcc.target/i386/apx-interrupt-1.c: Expect 31 .cfi_restore
directives.
Signed-off-by: H.J. Lu
Diff:
---
gcc/testsuite/gcc.target/i386/apx-interrupt-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
b/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
index fefe2e6d6fc4..fa1acc7a1420 100644
--- a/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
+++ b/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
@@ -66,7 +66,7 @@ void foo (void *frame)
/* { dg-final { scan-assembler-times {\t\.cfi_offset 132, -120} 1 } } */
/* { dg-final { scan-assembler-times {\t\.cfi_offset 131, -128} 1 } } */
/* { dg-final { scan-assembler-times {\t\.cfi_offset 130, -136} 1 } } */
-/* { dg-final { scan-assembler-times ".cfi_restore" 15} } */
+/* { dg-final { scan-assembler-times ".cfi_restore" 31 } } */
/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)ax" 1 } } */
/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */
/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)cx" 1 } } */
[gcc r15-9499] includes, Darwin: Handle modular use for macOS SDKs [PR116827].
https://gcc.gnu.org/g:9cf6b52d04df22726d88eef113211b3cc08515de commit r15-9499-g9cf6b52d04df22726d88eef113211b3cc08515de Author: Iain Sandoe Date: Sun Dec 29 23:06:54 2024 + includes, Darwin: Handle modular use for macOS SDKs [PR116827]. Recent changes to the OS SDKs have altered the way in which include guards are used for a number of headers when C++ modules are enabled. Instead of placing the guards in the included header, they are being placed in the including header. This breaks the assumptions in the current GCC stddef.h specifically, that the presence of __PTRDIFF_T and __SIZE_T means that the relevant defs are already made. However in the case of the module-enabled C++ with these SDKs, that is no longer true. stddef.h has a large body of special-cases already, but it seems that the only viable solution here is to add a new one specifically for __APPLE__ and modular code. This fixes around 280 new fails in the modules test-suite; it is needed on all open branches that support modules. PR target/116827 gcc/ChangeLog: * ginclude/stddef.h: Undefine __PTRDIFF_T and __SIZE_T for module- enabled c++ on Darwin/macOS platforms. Signed-off-by: Iain Sandoe Diff: --- gcc/ginclude/stddef.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/gcc/ginclude/stddef.h b/gcc/ginclude/stddef.h index 0d53103ce20c..bacf24d2425c 100644 --- a/gcc/ginclude/stddef.h +++ b/gcc/ginclude/stddef.h @@ -89,6 +89,21 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #undef _PTRDIFF_T_ #endif +/* When modular code is enabled with macOS SDKs from version 15, the + include guards are set in the includers of this code, rather than as + part of it. This means the we must unset them or the intended code + here will be bypassed (resulting in undefined values). */ +#if defined (__APPLE__) +# if defined(__has_feature) && __has_feature(modules) +# if defined (__need_ptrdiff_t) +# undef __PTRDIFF_T +# endif +# if defined (__need_size_t) +# undef __SIZE_T +# endif +# endif +#endif + /* On VxWorks, may have defined macros like _TYPE_size_t which will typedef size_t. fixincludes patched the vxTypesBase.h so that this macro is only defined if _GCC_SIZE_T is
[gcc r15-9500] configure, Darwin: Recognise new naming for Xcode ld.
https://gcc.gnu.org/g:7f56a8e8ad1c33d358e9e09fcbaf263c2caba1b9
commit r15-9500-g7f56a8e8ad1c33d358e9e09fcbaf263c2caba1b9
Author: Iain Sandoe
Date: Tue Apr 15 14:02:21 2025 +0100
configure, Darwin: Recognise new naming for Xcode ld.
The latest editions of XCode have altered the identify reported by 'ld -v'
(again). This means that GCC configure no longer detects the version.
Fixed by adding the new name to the set checked.
gcc/ChangeLog:
* configure: Regenerate.
* configure.ac: Recognise PROJECT:ld-.nn.aa as an identifier
for Darwin's static linker.
Signed-off-by: Iain Sandoe
Diff:
---
gcc/configure| 7 ---
gcc/configure.ac | 7 ---
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/gcc/configure b/gcc/configure
index 821f8b44bc6a..16965953f051 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -3948,7 +3948,7 @@ if test x"${DEFAULT_LINKER+set}" = x"set"; then
as_fn_error $? "cannot execute: $DEFAULT_LINKER: check --with-ld or env.
var. DEFAULT_LINKER" "$LINENO" 5
elif $DEFAULT_LINKER -v < /dev/null 2>&1 | grep GNU > /dev/null; then
gnu_ld_flag=yes
- elif $DEFAULT_LINKER -v < /dev/null 2>&1 | grep ld64- > /dev/null; then
+ elif $DEFAULT_LINKER -v < /dev/null 2>&1 | grep 'PROJECT:ld\(64\)*-' >
/dev/null; then
ld64_flag=yes
fi
@@ -32730,8 +32730,9 @@ $as_echo "$gcc_cv_ld64_major" >&6; }
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking linker version" >&5
$as_echo_n "checking linker version... " >&6; }
if test x"${gcc_cv_ld64_version}" = x; then
- gcc_cv_ld64_version=`$gcc_cv_ld -v 2>&1 | $EGREP 'ld64|dyld' \
- | sed -e 's/.*ld64-//' -e 's/.*dyld-//'| awk '{print $1}'`
+ gcc_cv_ld64_version=`$gcc_cv_ld -v 2>&1 | $EGREP 'ld64|dyld|PROJECT:ld' \
+ | sed -e 's/.*ld64-//' -e 's/.*dyld-//' -e 's/.*PROJECT:ld-//' \
+ | awk '{print $1}'`
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_ld64_version" >&5
$as_echo "$gcc_cv_ld64_version" >&6; }
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 3d0a4e6f8f55..9f67e62950a4 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -358,7 +358,7 @@ if test x"${DEFAULT_LINKER+set}" = x"set"; then
AC_MSG_ERROR([cannot execute: $DEFAULT_LINKER: check --with-ld or env.
var. DEFAULT_LINKER])
elif $DEFAULT_LINKER -v < /dev/null 2>&1 | grep GNU > /dev/null; then
gnu_ld_flag=yes
- elif $DEFAULT_LINKER -v < /dev/null 2>&1 | grep ld64- > /dev/null; then
+ elif $DEFAULT_LINKER -v < /dev/null 2>&1 | grep 'PROJECT:ld\(64\)*-' >
/dev/null; then
ld64_flag=yes
fi
AC_DEFINE_UNQUOTED(DEFAULT_LINKER,"$DEFAULT_LINKER",
@@ -6418,8 +6418,9 @@ if test x"$ld64_flag" = x"yes"; then
# If the version was not specified, try to find it.
AC_MSG_CHECKING(linker version)
if test x"${gcc_cv_ld64_version}" = x; then
- gcc_cv_ld64_version=`$gcc_cv_ld -v 2>&1 | $EGREP 'ld64|dyld' \
- | sed -e 's/.*ld64-//' -e 's/.*dyld-//'| awk '{print $1}'`
+ gcc_cv_ld64_version=`$gcc_cv_ld -v 2>&1 | $EGREP 'ld64|dyld|PROJECT:ld' \
+ | sed -e 's/.*ld64-//' -e 's/.*dyld-//' -e 's/.*PROJECT:ld-//' \
+ | awk '{print $1}'`
fi
AC_MSG_RESULT($gcc_cv_ld64_version)
[gcc r14-11617] discriminators: Fix assigning discriminators on edge [PR113546]
https://gcc.gnu.org/g:5f6285f2918f1835ec7c35c37cbec8c10a091b57
commit r14-11617-g5f6285f2918f1835ec7c35c37cbec8c10a091b57
Author: Andrew Pinski
Date: Sat Mar 15 16:37:41 2025 -0700
discriminators: Fix assigning discriminators on edge [PR113546]
The problem here is there was a compare debug since the discriminators
would still take into account debug statements. For the edge we would look
at the first statement after the labels and that might have been a debug
statement.
So we need to skip over debug statements otherwise we could get different
discriminators # with and without -g.
Bootstrapped and tested on x86_64-linux-gnu with no regressions.
PR middle-end/113546
gcc/ChangeLog:
* tree-cfg.cc (first_non_label_stmt): Rename to ...
(first_non_label_nondebug_stmt): This and use
gsi_start_nondebug_after_labels_bb.
(assign_discriminators): Update call to
first_non_label_nondebug_stmt.
gcc/testsuite/ChangeLog:
* c-c++-common/torture/pr113546-1.c: New test.
Signed-off-by: Andrew Pinski
(cherry picked from commit c5ca45b8069229b6ad9bc845f03f46340f6316d7)
Diff:
---
gcc/testsuite/c-c++-common/torture/pr113546-1.c | 8
gcc/tree-cfg.cc | 13 ++---
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/c-c++-common/torture/pr113546-1.c
b/gcc/testsuite/c-c++-common/torture/pr113546-1.c
new file mode 100644
index ..74989e992cd6
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/torture/pr113546-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-fcompare-debug" } */
+
+int x;
+void f() {
+fail:
+ switch (x) { case 0: goto fail;; }
+}
diff --git a/gcc/tree-cfg.cc b/gcc/tree-cfg.cc
index b1ba33018fd7..7414f2d0b3d3 100644
--- a/gcc/tree-cfg.cc
+++ b/gcc/tree-cfg.cc
@@ -167,7 +167,7 @@ static edge gimple_try_redirect_by_replacing_jump (edge,
basic_block);
static inline bool stmt_starts_bb_p (gimple *, gimple *);
static bool gimple_verify_flow_info (void);
static void gimple_make_forwarder_block (edge);
-static gimple *first_non_label_stmt (basic_block);
+static gimple *first_non_label_nondebug_stmt (basic_block);
static bool verify_gimple_transaction (gtransaction *);
static bool call_can_make_abnormal_goto (gimple *);
@@ -1262,7 +1262,7 @@ assign_discriminators (void)
FOR_EACH_EDGE (e, ei, bb->succs)
{
- gimple *first = first_non_label_stmt (e->dest);
+ gimple *first = first_non_label_nondebug_stmt (e->dest);
gimple *last = last_nondebug_stmt (e->dest);
gimple *stmt_on_same_line = NULL;
@@ -2944,14 +2944,13 @@ first_stmt (basic_block bb)
return stmt;
}
-/* Return the first non-label statement in basic block BB. */
+/* Return the first non-label/non-debug statement in basic block BB. */
static gimple *
-first_non_label_stmt (basic_block bb)
+first_non_label_nondebug_stmt (basic_block bb)
{
- gimple_stmt_iterator i = gsi_start_bb (bb);
- while (!gsi_end_p (i) && gimple_code (gsi_stmt (i)) == GIMPLE_LABEL)
-gsi_next (&i);
+ gimple_stmt_iterator i;
+ i = gsi_start_nondebug_after_labels_bb (bb);
return !gsi_end_p (i) ? gsi_stmt (i) : NULL;
}
[gcc r15-9504] OpenMP: omp.h omp::allocator C++ Allocator interface
https://gcc.gnu.org/g:99835bd68e5360b0b3c8ad9c61ea23f70ad3dce6
commit r15-9504-g99835bd68e5360b0b3c8ad9c61ea23f70ad3dce6
Author: waffl3x
Date: Tue Apr 15 14:34:38 2025 -0600
OpenMP: omp.h omp::allocator C++ Allocator interface
The implementation of each allocator is simplified by inheriting from
__detail::__allocator_templ. At the moment, none of the implementations
diverge in any way, simply passing in the allocator handle to be used when
an allocation is made. In the future, const_mem will need special handling
added to it to support constant memory space.
libgomp/ChangeLog:
* omp.h.in: Add omp::allocator::* and ompx::allocator::* allocators.
(__detail::__allocator_templ):
New struct template.
(null_allocator): New struct template.
(default_mem): Likewise.
(large_cap_mem): Likewise.
(const_mem): Likewise.
(high_bw_mem): Likewise.
(low_lat_mem): Likewise.
(cgroup_mem): Likewise.
(pteam_mem): Likewise.
(thread_mem): Likewise.
(ompx::allocator::gnu_pinned_mem): Likewise.
* testsuite/libgomp.c++/allocator-1.C: New test.
* testsuite/libgomp.c++/allocator-2.C: New test.
Signed-off-by: waffl3x
Diff:
---
libgomp/omp.h.in| 132 +++
libgomp/testsuite/libgomp.c++/allocator-1.C | 158
libgomp/testsuite/libgomp.c++/allocator-2.C | 132 +++
3 files changed, 422 insertions(+)
diff --git a/libgomp/omp.h.in b/libgomp/omp.h.in
index d5e8be46e944..8d17db1da9a7 100644
--- a/libgomp/omp.h.in
+++ b/libgomp/omp.h.in
@@ -432,4 +432,136 @@ extern const char *omp_get_uid_from_device (int)
__GOMP_NOTHROW;
}
#endif
+#if __cplusplus >= 201103L
+
+/* std::__throw_bad_alloc and std::__throw_bad_array_new_length. */
+#include
+
+namespace omp
+{
+namespace allocator
+{
+
+namespace __detail
+{
+
+template
+struct __allocator_templ
+{
+ using value_type = __T;
+ using pointer = __T*;
+ using const_pointer = const __T*;
+ using size_type = __SIZE_TYPE__;
+ using difference_type = __PTRDIFF_TYPE__;
+
+ __T*
+ allocate (size_type __n)
+ {
+if (__SIZE_MAX__ / sizeof(__T) < __n)
+ std::__throw_bad_array_new_length ();
+void *__p = omp_aligned_alloc (alignof(__T), __n * sizeof(__T), __Handle);
+if (!__p)
+ std::__throw_bad_alloc ();
+return static_cast<__T*>(__p);
+ }
+
+ void
+ deallocate (__T *__p, size_type) __GOMP_NOTHROW
+ {
+omp_free (static_cast(__p), __Handle);
+ }
+};
+
+template
+constexpr bool
+operator== (const __allocator_templ<__T, __Handle>&,
+ const __allocator_templ<__U, __Handle>&) __GOMP_NOTHROW
+{
+ return true;
+}
+
+template
+constexpr bool
+operator== (const __allocator_templ<__T, __Handle>&,
+ const __allocator_templ<__U, __UHandle>&) __GOMP_NOTHROW
+{
+ return false;
+}
+
+template
+constexpr bool
+operator!= (const __allocator_templ<__T, __Handle>&,
+ const __allocator_templ<__U, __Handle>&) __GOMP_NOTHROW
+{
+ return false;
+}
+
+template
+constexpr bool
+operator!= (const __allocator_templ<__T, __Handle>&,
+ const __allocator_templ<__U, __UHandle>&) __GOMP_NOTHROW
+{
+ return true;
+}
+
+} /* namespace __detail */
+
+template
+struct null_allocator
+ : __detail::__allocator_templ<__T, omp_null_allocator> {};
+
+template
+struct default_mem
+ : __detail::__allocator_templ<__T, omp_default_mem_alloc> {};
+
+template
+struct large_cap_mem
+ : __detail::__allocator_templ<__T, omp_large_cap_mem_alloc> {};
+
+template
+struct const_mem
+ : __detail::__allocator_templ<__T, omp_const_mem_alloc> {};
+
+template
+struct high_bw_mem
+ : __detail::__allocator_templ<__T, omp_high_bw_mem_alloc> {};
+
+template
+struct low_lat_mem
+ : __detail::__allocator_templ<__T, omp_low_lat_mem_alloc> {};
+
+template
+struct cgroup_mem
+ : __detail::__allocator_templ<__T, omp_cgroup_mem_alloc> {};
+
+template
+struct pteam_mem
+ : __detail::__allocator_templ<__T, omp_pteam_mem_alloc> {};
+
+template
+struct thread_mem
+ : __detail::__allocator_templ<__T, omp_thread_mem_alloc> {};
+
+} /* namespace allocator */
+
+} /* namespace omp */
+
+namespace ompx
+{
+
+namespace allocator
+{
+
+template
+struct gnu_pinned_mem
+ : omp::allocator::__detail::__allocator_templ<__T,
ompx_gnu_pinned_mem_alloc> {};
+
+} /* namespace allocator */
+
+} /* namespace ompx */
+
+#endif /* __cplusplus */
+
#endif /* _OMP_H */
diff --git a/libgomp/testsuite/libgomp.c++/allocator-1.C
b/libgomp/testsuite/libgomp.c++/allocator-1.C
new file mode 100644
index ..f82072284883
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c++/allocator-1.C
@@ -0,0 +1,158 @@
+// { dg-do run }
+
+#include
+#include
+#include
+
+template class Alloc>
+void test (T const initial_value = T())
+{
+ using Allocator = Alloc;
+ Allocator a;
+
[gcc r15-9505] c: Fully fold each parameter for call to .ACCESS_WITH_SIZE [PR119717]
https://gcc.gnu.org/g:727f330f9ac661339af1121fc5c9b67dd0d35872
commit r15-9505-g727f330f9ac661339af1121fc5c9b67dd0d35872
Author: Qing Zhao
Date: Mon Apr 14 19:41:12 2025 +
c: Fully fold each parameter for call to .ACCESS_WITH_SIZE [PR119717]
C_MAYBE_CONST_EXPR is a C FE operator that will be removed by c_fully_fold.
In c_fully_fold, it assumes that operands of function calls have already
been folded. However, when we build call to .ACCESS_WITH_SIZE, all its
operands are not fully folded. therefore the C FE specific operator is
passed to middle-end.
In order to fix this issue, fully fold the parameters before building the
call to .ACCESS_WITH_SIZE.
PR c/119717
gcc/c/ChangeLog:
* c-typeck.cc (build_access_with_size_for_counted_by): Fully fold
the
parameters for call to .ACCESS_WITH_SIZE.
gcc/testsuite/ChangeLog:
* gcc.dg/pr119717.c: New test.
Diff:
---
gcc/c/c-typeck.cc | 8 ++--
gcc/testsuite/gcc.dg/pr119717.c | 24
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index 3870e8a15587..55d896e02df5 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -3013,12 +3013,16 @@ build_access_with_size_for_counted_by (location_t loc,
tree ref,
gcc_assert (c_flexible_array_member_type_p (TREE_TYPE (ref)));
/* The result type of the call is a pointer to the flexible array type. */
tree result_type = c_build_pointer_type (TREE_TYPE (ref));
+ tree first_param
+= c_fully_fold (array_to_pointer_conversion (loc, ref), false, NULL);
+ tree second_param
+= c_fully_fold (counted_by_ref, false, NULL);
tree call
= build_call_expr_internal_loc (loc, IFN_ACCESS_WITH_SIZE,
result_type, 6,
- array_to_pointer_conversion (loc, ref),
- counted_by_ref,
+ first_param,
+ second_param,
build_int_cst (integer_type_node, 1),
build_int_cst (counted_by_type, 0),
build_int_cst (integer_type_node, -1),
diff --git a/gcc/testsuite/gcc.dg/pr119717.c b/gcc/testsuite/gcc.dg/pr119717.c
new file mode 100644
index ..e5eedc567b3d
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr119717.c
@@ -0,0 +1,24 @@
+/* PR c/119717 */
+/* { dg-additional-options "-std=c23" } */
+/* { dg-do compile } */
+
+struct annotated {
+ unsigned count;
+ [[gnu::counted_by(count)]] char array[];
+};
+
+[[gnu::noinline,gnu::noipa]]
+static unsigned
+size_of (bool x, struct annotated *a)
+{
+ char *p = (x ? a : 0)->array;
+ return __builtin_dynamic_object_size (p, 1);
+}
+
+int main()
+{
+ struct annotated *p = __builtin_malloc(sizeof *p);
+ p->count = 0;
+ __builtin_printf ("the bdos whole is %ld\n", size_of (0, p));
+ return 0;
+}
[gcc/meissner/heads/work201-paddis] (14 commits) Merge commit 'refs/users/meissner/heads/work201-paddis' of
The branch 'meissner/heads/work201-paddis' was updated to point to: 0c0bc7f40f1a... Merge commit 'refs/users/meissner/heads/work201-paddis' of It previously pointed to: f20a5086a2cf... Add ChangeLog.paddis and update REVISION. Diff: Summary of changes (added commits): --- 0c0bc7f... Merge commit 'refs/users/meissner/heads/work201-paddis' of 4736165... Add ChangeLog.paddis and update REVISION. a6ffd50... Update ChangeLog.* (*) ccc8b43... Use architecture flags for defining _ARCH_PWR macros. (*) 680d73b... Add rs6000 architecture masks. (*) c8a6cb0... xUse vector pair load/store for memcpy with -mcpu=future (*) 7880c5c... Add -mcpu=future tests. (*) 3e1e33a... Add -mcpu=future tuning support. (*) 51126db... Add support for -mcpu=future (*) 754bb7e... Change TARGET_MODULO to TARGET_POWER9. (*) 4bc7533... Change TARGET_POPCNTD to TARGET_POWER7. (*) d1ebe30... Change TARGET_CMPB to TARGET_POWER6. (*) aa02d95... Change TARGET_FPRND to TARGET_POWER5X. (*) 40b94e8... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work201-paddis' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work201-sha)] Add ChangeLog.sha and update REVISION.
https://gcc.gnu.org/g:00f23871ca09f41315e7bada51fcf7cfd75ffe59 commit 00f23871ca09f41315e7bada51fcf7cfd75ffe59 Author: Michael Meissner Date: Mon Apr 14 15:16:10 2025 -0400 Add ChangeLog.sha and update REVISION. 2025-04-14 Michael Meissner gcc/ * ChangeLog.sha: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.sha | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha new file mode 100644 index ..389f91f54250 --- /dev/null +++ b/gcc/ChangeLog.sha @@ -0,0 +1,5 @@ + Branch work201-sha, baseline + +2025-04-14 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 5f8715c4844d..4363e39c6b26 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work201 branch +work201-sha branch
[gcc(refs/users/meissner/heads/work201-paddis)] Merge commit 'refs/users/meissner/heads/work201-paddis' of git+ssh://gcc.gnu.org/git/gcc into me/wor
https://gcc.gnu.org/g:0c0bc7f40f1a5dd8fdaa144c09d389c848785ac5 commit 0c0bc7f40f1a5dd8fdaa144c09d389c848785ac5 Merge: 47361653dd9c f20a5086a2cf Author: Michael Meissner Date: Mon Apr 14 20:44:01 2025 -0400 Merge commit 'refs/users/meissner/heads/work201-paddis' of git+ssh://gcc.gnu.org/git/gcc into me/work201-paddis Diff:
[gcc r13-9523] c++: Properly fold .* [PR114525]
https://gcc.gnu.org/g:ca2b5edb99023d88c83ac6384e908fce6b546578
commit r13-9523-gca2b5edb99023d88c83ac6384e908fce6b546578
Author: Simon Martin
Date: Mon Apr 14 09:24:12 2025 +0200
c++: Properly fold .* [PR114525]
We've been miscompiling the following since r0-51314-gd6b4ea8592e338 (I
did not go compile something that old, and identified this change via
git blame, so might be wrong)
=== cut here ===
struct Foo { int x; };
Foo& get (Foo &v) { return v; }
void bar () {
Foo v; v.x = 1;
(true ? get (v) : get (v)).*(&Foo::x) = 2;
// v.x still equals 1 here...
}
=== cut here ===
The problem lies in build_m_component_ref, that computes the address of
the COND_EXPR using build_address to build the representation of
(true ? get (v) : get (v)).*(&Foo::x);
and gets something like
&(true ? get (v) : get (v)) // #1
instead of
(true ? &get (v) : &get (v)) // #2
and the write does not go where want it to, hence the miscompile.
This patch replaces the call to build_address by a call to
cp_build_addr_expr, which gives #2, that is properly handled.
PR c++/114525
gcc/cp/ChangeLog:
* typeck2.cc (build_m_component_ref): Call cp_build_addr_expr
instead of build_address.
gcc/testsuite/ChangeLog:
* g++.dg/expr/cond18.C: New test.
(cherry picked from commit 35ce9afc84a63fb647a90cbecb2adf3e748178be)
Diff:
---
gcc/cp/typeck2.cc | 2 +-
gcc/testsuite/g++.dg/expr/cond18.C | 36
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/typeck2.cc b/gcc/cp/typeck2.cc
index e499bf0f20ce..775d18f61fd7 100644
--- a/gcc/cp/typeck2.cc
+++ b/gcc/cp/typeck2.cc
@@ -2339,7 +2339,7 @@ build_m_component_ref (tree datum, tree component,
tsubst_flags_t complain)
(cp_type_quals (type)
| cp_type_quals (TREE_TYPE (datum;
- datum = build_address (datum);
+ datum = cp_build_addr_expr (datum, complain);
/* Convert object to the correct base. */
if (binfo)
diff --git a/gcc/testsuite/g++.dg/expr/cond18.C
b/gcc/testsuite/g++.dg/expr/cond18.C
new file mode 100644
index ..326985eed506
--- /dev/null
+++ b/gcc/testsuite/g++.dg/expr/cond18.C
@@ -0,0 +1,36 @@
+/* PR c++/114525 */
+/* { dg-do run } */
+
+struct Foo {
+ int x;
+};
+
+Foo& get (Foo& v) {
+ return v;
+}
+
+int main () {
+ bool cond = true;
+
+ /* Testcase from PR; v.x would wrongly remain equal to 1. */
+ Foo v_ko;
+ v_ko.x = 1;
+ (cond ? get (v_ko) : get (v_ko)).*(&Foo::x) = 2;
+ if (v_ko.x != 2)
+__builtin_abort ();
+
+ /* Those would already work, i.e. x be changed to 2. */
+ Foo v_ok_1;
+ v_ok_1.x = 1;
+ (cond ? get (v_ok_1) : get (v_ok_1)).x = 2;
+ if (v_ok_1.x != 2)
+__builtin_abort ();
+
+ Foo v_ok_2;
+ v_ok_2.x = 1;
+ get (v_ok_2).*(&Foo::x) = 2;
+ if (v_ok_2.x != 2)
+__builtin_abort ();
+
+ return 0;
+}
[gcc r15-9460] Polish 'dg-output-file' test logs
https://gcc.gnu.org/g:8621554d96eb040547588004c830ff8352492937
commit r15-9460-g8621554d96eb040547588004c830ff8352492937
Author: Thomas Schwinge
Date: Sun Apr 13 16:50:37 2025 +0200
Polish 'dg-output-file' test logs
Per commit r15-8260-g563e6d926d9826d76895086d0c40a29dc90d66e5
"testsuite: Add support for dg-output-file directive", this currently
produces
test logs as follows:
PASS: gcc.dg/dg-output-file-1.c (test for excess errors)
PASS: dg-output-file-1-lp64.txt output file test
PASS: gcc.dg/dg-output-file-1.c execution test
PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O0 (test for excess
errors)
PASS: COMP-6_arithmetic.out output file test
PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O0 execution test
PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O1 (test for excess
errors)
PASS: COMP-6_arithmetic.out output file test
PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O1 execution test
[Etc.]
Notice that the 'PASS: [...] output file test' lines easily produce
duplicate
test names, or might even produce PASS plus FAIL for the same test names.
Make the "output file test" use the same "descriptive name" as the other
parts,
and get properly sorted with parallel-testing
'contrib/dg-extract-results.sh'
processing:
PASS: c-c++-common/zero-scratch-regs-leafy-2.c -Wc++-compat (test
for excess errors)
-PASS: dg-output-file-1-lp64.txt output file test
PASS: gcc.dg/2108-1.c (test for excess errors)
[...]
PASS: gcc.dg/devnull-dump.c (test for excess errors)
PASS: gcc.dg/dg-output-file-1.c (test for excess errors)
PASS: gcc.dg/dg-output-file-1.c execution test
+PASS: gcc.dg/dg-output-file-1.c output file test
PASS: gcc.dg/dg-test-1.c (test for excess errors)
..., and gets de-duplicated test names, for example:
PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O0 (test for excess
errors)
-PASS: COMP-6_arithmetic.out output file test
+PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O0 output file test
PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O0 execution test
PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O1 (test for excess
errors)
-PASS: COMP-6_arithmetic.out output file test
+PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O1 output file test
PASS: cobol.dg/group2/COMP-6_arithmetic.cob -O1 execution test
[Etc.]
(Given that only ever a single 'dg-output-file' directive is active, don't
print the output filename.)
gcc/testsuite/
* lib/gcc-dg.exp (${tool}_load): Polish 'dg-output-file' test
logs.
Diff:
---
gcc/testsuite/lib/gcc-dg.exp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp
index eadc1cd90bcb..6dd8fa3fce9c 100644
--- a/gcc/testsuite/lib/gcc-dg.exp
+++ b/gcc/testsuite/lib/gcc-dg.exp
@@ -507,8 +507,7 @@ if { [info procs ${tool}_load] != [list] \
set linenum 1
set outfile [open [lindex ${output-file} 1]]
set do_fail 0
- set name [file tail [lindex ${output-file} 1]]
- verbose "output-file args is $args program is $program" 1
+ set name [testname-for-summary]
while { [gets $outfile line] >= 0 } {
if { $linenum != 1 } {
set c [string index $output $idx]
[gcc r15-9485] d: Fix internal compiler error: in visit, at d/decl.cc:838 [PR119799]
https://gcc.gnu.org/g:074b2b0f91f948fe3488ada91ec6a8576c684dea
commit r15-9485-g074b2b0f91f948fe3488ada91ec6a8576c684dea
Author: Iain Buclaw
Date: Tue Apr 15 15:19:13 2025 +0200
d: Fix internal compiler error: in visit, at d/decl.cc:838 [PR119799]
This was caused by a check in the D front-end disallowing static
VAR_DECLs with a size `0'.
While empty structs in D are give the size `1', the same symbol coming
from ImportC modules do infact have no size, so allow C variables to
pass the check as well as array objects.
PR d/119799
gcc/d/ChangeLog:
* decl.cc (DeclVisitor::visit (VarDeclaration *)): Check front-end
type size before building the VAR_DECL. Allow C symbols to have a
size of `0'.
gcc/testsuite/ChangeLog:
* gdc.dg/import-c/pr119799.d: New test.
* gdc.dg/import-c/pr119799c.c: New test.
Diff:
---
gcc/d/decl.cc | 15 ++-
gcc/testsuite/gdc.dg/import-c/pr119799.d | 2 ++
gcc/testsuite/gdc.dg/import-c/pr119799c.c | 1 +
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/gcc/d/decl.cc b/gcc/d/decl.cc
index 136f78b32ff0..9ddf7cf1540c 100644
--- a/gcc/d/decl.cc
+++ b/gcc/d/decl.cc
@@ -791,6 +791,12 @@ public:
}
else if (d->isDataseg ())
{
+ /* When the front-end type size is invalid, an error has already been
+ given for the declaration or type. */
+ dinteger_t size = dmd::size (d->type, d->loc);
+ if (size == SIZE_INVALID)
+ return;
+
tree decl = get_symbol_decl (d);
/* Only need to build the VAR_DECL for extern declarations. */
@@ -804,9 +810,7 @@ public:
return;
/* How big a symbol can be should depend on back-end. */
- tree size = build_integer_cst (dmd::size (d->type, d->loc),
- build_ctype (Type::tsize_t));
- if (!valid_constant_size_p (size))
+ if (!valid_constant_size_p (build_integer_cst (size, size_type_node)))
{
error_at (make_location_t (d->loc), "size is too large");
return;
@@ -835,8 +839,9 @@ public:
}
/* Frontend should have already caught this. */
- gcc_assert (!integer_zerop (size)
- || d->type->toBasetype ()->isTypeSArray ());
+ gcc_assert ((size != 0 && size != SIZE_INVALID)
+ || d->type->toBasetype ()->isTypeSArray ()
+ || d->isCsymbol ());
d_finish_decl (decl);
diff --git a/gcc/testsuite/gdc.dg/import-c/pr119799.d
b/gcc/testsuite/gdc.dg/import-c/pr119799.d
new file mode 100644
index ..d8b0fa22fe1f
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/import-c/pr119799.d
@@ -0,0 +1,2 @@
+// { dg-do compile }
+import pr119799c;
diff --git a/gcc/testsuite/gdc.dg/import-c/pr119799c.c
b/gcc/testsuite/gdc.dg/import-c/pr119799c.c
new file mode 100644
index ..b80e856f75f7
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/import-c/pr119799c.c
@@ -0,0 +1 @@
+static struct {} s119799;
[gcc r15-9487] Locality cloning pass: -fipa-reorder-for-locality
https://gcc.gnu.org/g:6d9fdf4bf57353f9260a2e0c8774854fb50f5128 commit r15-9487-g6d9fdf4bf57353f9260a2e0c8774854fb50f5128 Author: Kyrylo Tkachov Date: Thu Feb 27 09:24:10 2025 -0800 Locality cloning pass: -fipa-reorder-for-locality Implement partitioning and cloning in the callgraph to help locality. A new -fipa-reorder-for-locality flag is used to enable this. The majority of the logic is in the new IPA pass in ipa-locality-cloning.cc The optimization has two components: * Partitioning the callgraph so as to group callers and callees that frequently call each other in the same partition * Cloning functions that straddle multiple callchains and allowing each clone to be local to the partition of its callchain. The majority of the logic is in the new IPA pass in ipa-locality-cloning.cc. It creates a partitioning plan and does the prerequisite cloning. The partitioning is then implemented during the existing LTO partitioning pass. To guide these locality heuristics we use PGO data. In the absence of PGO data we use a static heuristic that uses the accumulated estimated edge frequencies of the callees for each function to guide the reordering. We are investigating some more elaborate static heuristics, in particular using the demangled C++ names to group template instantiatios together. This is promising but we are working out some kinks in the implementation currently and want to send that out as a follow-up once we're more confident in it. A new bootstrap-lto-locality bootstrap config is added that allows us to test this on GCC itself with either static or PGO heuristics. GCC bootstraps with both (normal LTO bootstrap and profiledbootstrap). As this new pass enables a new partitioning scheme it is incompatible with explicit -flto-partition= options so an error is introduced when the user uses both flags explicitly. With this optimization we are seeing good performance gains on some large internal workloads that stress the parts of the processor that is sensitive to code locality, but we'd appreciate wider performance evaluation. Bootstrapped and tested on aarch64-none-linux-gnu. Ok for mainline? Thanks, Kyrill Signed-off-by: Prachi Godbole Co-authored-by: Kyrylo Tkachov config/ChangeLog: * bootstrap-lto-locality.mk: New file. gcc/ChangeLog: * Makefile.in (OBJS): Add ipa-locality-cloning.o. * cgraph.h (set_new_clone_decl_and_node_flags): Declare prototype. * cgraphclones.cc (set_new_clone_decl_and_node_flags): Remove static qualifier. * common.opt (fipa-reorder-for-locality): New flag. (LTO_PARTITION_DEFAULT): Declare. (flto-partition): Change default to LTO_PARTITION_DFEAULT. * doc/invoke.texi: Document -fipa-reorder-for-locality. * flag-types.h (enum lto_locality_cloning_model): Declare. (lto_partitioning_model): Add LTO_PARTITION_DEFAULT. * lto-cgraph.cc (lto_set_symtab_encoder_in_partition): Add dumping of node and index. * opts.cc (validate_ipa_reorder_locality_lto_partition): Define. (finish_options): Handle LTO_PARTITION_DEFAULT. * params.opt (lto_locality_cloning_model): New enum. (lto-partition-locality-cloning): New param. (lto-partition-locality-frequency-cutoff): Likewise. (lto-partition-locality-size-cutoff): Likewise. (lto-max-locality-partition): Likewise. * passes.def: Register pass_ipa_locality_cloning. * timevar.def (TV_IPA_LC): New timevar. * tree-pass.h (make_pass_ipa_locality_cloning): Declare. * ipa-locality-cloning.cc: New file. * ipa-locality-cloning.h: New file. gcc/lto/ChangeLog: * lto-partition.cc (add_node_references_to_partition): Define. (create_partition): Likewise. (lto_locality_map): Likewise. (lto_promote_cross_file_statics): Add extra dumping. * lto-partition.h (lto_locality_map): Declare prototype. * lto.cc (do_whole_program_analysis): Handle flag_ipa_reorder_for_locality. Diff: --- config/bootstrap-lto-locality.mk | 20 + gcc/Makefile.in |2 + gcc/cgraph.h |1 + gcc/cgraphclones.cc |2 +- gcc/common.opt |9 +- gcc/doc/invoke.texi | 32 +- gcc/flag-types.h | 10 +- gcc/ipa-locality-cloning.cc | 1137 ++ gcc/ipa-locality-cloning.h | 35 ++ gcc/lto-cgraph.cc|2 + gcc/lto/lto-partition.cc | 126 + gcc/lto/lto-partition.h |1 + gcc/lto/lto.cc
[gcc r15-9495] Set ADDSS cost to 3 for znver5
https://gcc.gnu.org/g:e2011ab13de3e70774f869b356f5f9c750780b34
commit r15-9495-ge2011ab13de3e70774f869b356f5f9c750780b34
Author: Jan Hubicka
Date: Tue Apr 15 19:04:15 2025 +0200
Set ADDSS cost to 3 for znver5
Znver5 has latency of addss 2 in typical case while all earlier versions
has latency 3.
Unforunately addss cost is used to cost many other SSE instructions than
just addss and
setting the cost to 2 makes us to vectorize 4 64bit stores into one 256bit
store which
in turn regesses imagemagick.
This patch sets the cost back to 3. Next stage1 we can untie addss from
the other operatoins
and set it correctly.
bootstrapped/regtested x86_64-linux and also benchmarked on SPEC2k17
gcc/ChangeLog:
PR target/119298
* config/i386/x86-tune-costs.h (znver5_cost): Set ADDSS cost to 3.
Diff:
---
gcc/config/i386/x86-tune-costs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index 7c8cb738d7cd..9477345bdd7e 100644
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -2120,7 +2120,7 @@ struct processor_costs znver5_cost = {
COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
/* ADDSS has throughput 2 and latency 2
(in some cases when source is another addition). */
- COSTS_N_INSNS (2), /* cost of ADDSS/SD SUBSS/SD insns. */
+ COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
/* MULSS has throughput 2 and latency 3. */
COSTS_N_INSNS (3), /* cost of MULSS instruction. */
COSTS_N_INSNS (3), /* cost of MULSD instruction. */
[gcc(refs/users/meissner/heads/work201)] Change TARGET_POPCNTB to TARGET_POWER5.
https://gcc.gnu.org/g:40b94e807640291965777471e77e9cf257fdbc6b commit 40b94e807640291965777471e77e9cf257fdbc6b Author: Michael Meissner Date: Mon Apr 14 20:20:49 2025 -0400 Change TARGET_POPCNTB to TARGET_POWER5. This patch changes TARGET_POPCNTB to TARGET_POWER5. The -mpopcntb switch is not being changed in this patch, just the name of the macros used to determine if the PowerPC processor supports ISA 2.2 (Power5). 2025-04-14 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_POPCNTB to TARGET_POWER5. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise. (TARGET_POWER5): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTB to TARGET_POWER5. (TARGET_FRE): Likewise. (TARGET_FRSQRTES): Likewise. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. Diff: --- gcc/config/rs6000/rs6000-builtin.cc | 2 +- gcc/config/rs6000/rs6000.cc | 2 +- gcc/config/rs6000/rs6000.h | 11 +++ gcc/config/rs6000/rs6000.md | 2 +- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 111802381acb..4ed2bc1ca89e 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_ALWAYS: return true; case ENB_P5: - return TARGET_POPCNTB; + return TARGET_POWER5; case ENB_P6: return TARGET_CMPB; case ENB_P6_64: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 737c3d6f7c75..a5ed93702494 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3926,7 +3926,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_FPRND) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); - else if (TARGET_POPCNTB) + else if (TARGET_POWER5) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); else if (TARGET_ALTIVEC) rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index db6112a09e11..d9a0ffe9f5b2 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -448,7 +448,7 @@ extern int rs6000_vector_align[]; Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT/* 970/power4 */\ -|| TARGET_POPCNTB /* ISA 2.02 */ \ +|| TARGET_POWER5 /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD) /* ISA 2.06 */ @@ -499,6 +499,9 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) +/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ +#define TARGET_POWER5 TARGET_POPCNTB + /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ @@ -525,7 +528,7 @@ extern int rs6000_vector_align[]; #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64\ || TARGET_PPC_GPOPT /* 970/power4 */\ -|| TARGET_POPCNTB /* ISA 2.02 */ \ +|| TARGET_POWER5/* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ @@ -541,9 +544,9 @@ extern int rs6000_vector_align[]; #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) #define TARGET_FRE (TARGET_HARD_FLOAT \ -&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) +&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode))) -#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \ +#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \ && TARGET_PPC_GFXOPT) #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9c718ca2a226..c5bd273be8b3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs
[gcc r13-9524] Daily bump.
https://gcc.gnu.org/g:73f1d4e0116d8d3e7e5a1d4342cf4efe60f316e9 commit r13-9524-g73f1d4e0116d8d3e7e5a1d4342cf4efe60f316e9 Author: GCC Administrator Date: Tue Apr 15 00:22:08 2025 + Daily bump. Diff: --- gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog| 9 + gcc/testsuite/ChangeLog | 8 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 1e2b10c9cd98..6a8ff35d9ec6 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250414 +20250415 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 31a56c66fd36..5ef1e5713713 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,12 @@ +2025-04-14 Simon Martin + + Backported from master: + 2025-03-25 Simon Martin + + PR c++/114525 + * typeck2.cc (build_m_component_ref): Call cp_build_addr_expr + instead of build_address. + 2025-03-25 Simon Martin Backported from master: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 71afeb908bb3..0ccc7494f62e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2025-04-14 Simon Martin + + Backported from master: + 2025-03-25 Simon Martin + + PR c++/114525 + * g++.dg/expr/cond18.C: New test. + 2025-04-13 Richard Biener Backported from master:
[gcc r15-9483] d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2out.cc:27676 [PR119817]
https://gcc.gnu.org/g:f5ed7d19c965de9ccb158d77e929b17459bf65b5
commit r15-9483-gf5ed7d19c965de9ccb158d77e929b17459bf65b5
Author: Iain Buclaw
Date: Tue Apr 15 14:49:34 2025 +0200
d: Fix ICE in dwarf2out_imported_module_or_decl, at dwarf2out.cc:27676
[PR119817]
The ImportVisitor method for handling the importing of overload sets was
pushing NULL_TREE to the array of import decls, which in turn got passed
to `debug_hooks->imported_module_or_decl', triggering the observed
internal compiler error.
NULL_TREE is returned from `build_import_decl' when the symbol was
ignored for being non-trivial to represent in debug, for example,
template or tuple declarations. So similarly "skip" adding the symbol
when this is the case for overload sets too.
PR d/119817
gcc/d/ChangeLog:
* imports.cc (ImportVisitor::visit (OverloadSet *)): Don't push
NULL_TREE to vector of import symbols.
gcc/testsuite/ChangeLog:
* gdc.dg/debug/imports/m119817/a.d: New test.
* gdc.dg/debug/imports/m119817/b.d: New test.
* gdc.dg/debug/imports/m119817/package.d: New test.
* gdc.dg/debug/pr119817.d: New test.
Diff:
---
gcc/d/imports.cc | 6 +-
gcc/testsuite/gdc.dg/debug/imports/m119817/a.d | 2 ++
gcc/testsuite/gdc.dg/debug/imports/m119817/b.d | 2 ++
gcc/testsuite/gdc.dg/debug/imports/m119817/package.d | 4
gcc/testsuite/gdc.dg/debug/pr119817.d| 6 ++
5 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/gcc/d/imports.cc b/gcc/d/imports.cc
index 776caafd25ca..16e4df69d656 100644
--- a/gcc/d/imports.cc
+++ b/gcc/d/imports.cc
@@ -182,7 +182,11 @@ public:
vec_alloc (tset, d->a.length);
for (size_t i = 0; i < d->a.length; i++)
- vec_safe_push (tset, build_import_decl (d->a[i]));
+ {
+ tree overload = build_import_decl (d->a[i]);
+ if (overload != NULL_TREE)
+ vec_safe_push (tset, overload);
+ }
this->result_ = build_tree_list_vec (tset);
tset->truncate (0);
diff --git a/gcc/testsuite/gdc.dg/debug/imports/m119817/a.d
b/gcc/testsuite/gdc.dg/debug/imports/m119817/a.d
new file mode 100644
index ..a13747240c43
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/debug/imports/m119817/a.d
@@ -0,0 +1,2 @@
+module imports.m119817.a;
+void f119817()() { }
diff --git a/gcc/testsuite/gdc.dg/debug/imports/m119817/b.d
b/gcc/testsuite/gdc.dg/debug/imports/m119817/b.d
new file mode 100644
index ..aef0e373ca6e
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/debug/imports/m119817/b.d
@@ -0,0 +1,2 @@
+module imports.m119817.b;
+void f119817() { }
diff --git a/gcc/testsuite/gdc.dg/debug/imports/m119817/package.d
b/gcc/testsuite/gdc.dg/debug/imports/m119817/package.d
new file mode 100644
index ..188827e669f5
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/debug/imports/m119817/package.d
@@ -0,0 +1,4 @@
+module imports.m119817;
+public import
+imports.m119817.a,
+imports.m119817.b;
diff --git a/gcc/testsuite/gdc.dg/debug/pr119817.d
b/gcc/testsuite/gdc.dg/debug/pr119817.d
new file mode 100644
index ..3eea6ba9a906
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/debug/pr119817.d
@@ -0,0 +1,6 @@
+// { dg-do compile }
+// { dg-additional-sources "imports/m119817/package.d" }
+// { dg-additional-sources "imports/m119817/a.d" }
+// { dg-additional-sources "imports/m119817/b.d" }
+module pr119817;
+import imports.m119817 : f119817;
[gcc r15-9468] Add 'throw', caught test cases for GCN, nvptx target and OpenACC, OpenMP 'target' offloading
https://gcc.gnu.org/g:1daf57049878a79b8bb40fb57ee2370f3cd4d4e7
commit r15-9468-g1daf57049878a79b8bb40fb57ee2370f3cd4d4e7
Author: Thomas Schwinge
Date: Thu Mar 27 14:46:20 2025 +0100
Add 'throw', caught test cases for GCN, nvptx target and OpenACC, OpenMP
'target' offloading
gcc/testsuite/
* g++.target/gcn/exceptions-throw-2.C: New.
* g++.target/nvptx/exceptions-throw-2.C: Likewise.
libgomp/
* testsuite/libgomp.c++/target-exceptions-throw-2.C: New.
*
testsuite/libgomp.c++/target-exceptions-throw-2-offload-sorry-GCN.C: Likewise.
*
testsuite/libgomp.c++/target-exceptions-throw-2-offload-sorry-nvptx.C: Likewise.
* testsuite/libgomp.oacc-c++/exceptions-throw-2.C: Likewise.
*
testsuite/libgomp.oacc-c++/exceptions-throw-2-offload-sorry-GCN.C: Likewise.
*
testsuite/libgomp.oacc-c++/exceptions-throw-2-offload-sorry-nvptx.C: Likewise.
Diff:
---
gcc/testsuite/g++.target/gcn/exceptions-throw-2.C | 13
.../g++.target/nvptx/exceptions-throw-2.C | 13
.../target-exceptions-throw-2-offload-sorry-GCN.C | 20 +++
...target-exceptions-throw-2-offload-sorry-nvptx.C | 20 +++
.../libgomp.c++/target-exceptions-throw-2.C| 15 +
.../exceptions-throw-2-offload-sorry-GCN.C | 19 +++
.../exceptions-throw-2-offload-sorry-nvptx.C | 21
.../libgomp.oacc-c++/exceptions-throw-2.C | 39 ++
8 files changed, 160 insertions(+)
diff --git a/gcc/testsuite/g++.target/gcn/exceptions-throw-2.C
b/gcc/testsuite/g++.target/gcn/exceptions-throw-2.C
new file mode 100644
index ..0ae64eebd478
--- /dev/null
+++ b/gcc/testsuite/g++.target/gcn/exceptions-throw-2.C
@@ -0,0 +1,13 @@
+/* 'throw', caught. */
+
+/* Via the magic string "-std=*++" indicate that testing one (the default) C++
standard is sufficient. */
+/* { dg-additional-options -fexceptions } */
+/* { dg-additional-options -fdump-tree-optimized-raw } */
+
+#include "../../../../libgomp/testsuite/libgomp.oacc-c++/exceptions-throw-2.C"
+
+/* { dg-final { scan-tree-dump-times {gimple_call <__cxa_allocate_exception, }
1 optimized } }
+ { dg-final { scan-tree-dump-times {gimple_call <__cxa_throw, } 1 optimized
} }
+ Compilation fails:
+ { dg-regexp {[^\r\n]+: In function 'int main\(\)':[\r\n]+(?:[^\r\n]+:
sorry, unimplemented: exception handling not supported[\r\n]+)+} }
+ (Note, using 'dg-regexp' instead of 'dg-message', as the former runs before
the auto-mark-UNSUPPORTED.) */
diff --git a/gcc/testsuite/g++.target/nvptx/exceptions-throw-2.C
b/gcc/testsuite/g++.target/nvptx/exceptions-throw-2.C
new file mode 100644
index ..0ae64eebd478
--- /dev/null
+++ b/gcc/testsuite/g++.target/nvptx/exceptions-throw-2.C
@@ -0,0 +1,13 @@
+/* 'throw', caught. */
+
+/* Via the magic string "-std=*++" indicate that testing one (the default) C++
standard is sufficient. */
+/* { dg-additional-options -fexceptions } */
+/* { dg-additional-options -fdump-tree-optimized-raw } */
+
+#include "../../../../libgomp/testsuite/libgomp.oacc-c++/exceptions-throw-2.C"
+
+/* { dg-final { scan-tree-dump-times {gimple_call <__cxa_allocate_exception, }
1 optimized } }
+ { dg-final { scan-tree-dump-times {gimple_call <__cxa_throw, } 1 optimized
} }
+ Compilation fails:
+ { dg-regexp {[^\r\n]+: In function 'int main\(\)':[\r\n]+(?:[^\r\n]+:
sorry, unimplemented: exception handling not supported[\r\n]+)+} }
+ (Note, using 'dg-regexp' instead of 'dg-message', as the former runs before
the auto-mark-UNSUPPORTED.) */
diff --git
a/libgomp/testsuite/libgomp.c++/target-exceptions-throw-2-offload-sorry-GCN.C
b/libgomp/testsuite/libgomp.c++/target-exceptions-throw-2-offload-sorry-GCN.C
new file mode 100644
index ..484e3f8bd33b
--- /dev/null
+++
b/libgomp/testsuite/libgomp.c++/target-exceptions-throw-2-offload-sorry-GCN.C
@@ -0,0 +1,20 @@
+/* 'throw' in OpenMP 'target' region, caught. */
+
+/* As this test case involves an expected offload compilation failure, we have
to handle each offload target individually.
+ { dg-do link { target offload_target_amdgcn } }
+ { dg-additional-options -foffload=amdgcn-amdhsa } */
+/* { dg-require-effective-target exceptions }
+ { dg-additional-options -fexceptions } */
+/* { dg-additional-options -fdump-tree-optimized-raw }
+ { dg-additional-options -foffload-options=-fdump-tree-optimized-raw } */
+
+#include "target-exceptions-throw-2.C"
+
+/* { dg-final { scan-tree-dump-times {gimple_call <__cxa_allocate_exception, }
1 optimized } }
+ { dg-final { scan-tree-dump-times {gimple_call <__cxa_throw, } 1 optimized
} }
+ { dg-final { only_for_offload_target amdgcn-amdhsa
scan-offload-tree-dump-times {gimple_call <__cxa_allocate_exception, } 1
optimized } }
+ { dg-final { only_for_offload_target amdgcn-amdhsa
scan-offload-tree-dump-times {gimple_call <__cxa_throw,
[gcc r15-9444] gccrs: expansion: Only add fragments if the matcher succeeded
https://gcc.gnu.org/g:cb23182fa2b9b06acbd82993be57f3dc47cc62eb
commit r15-9444-gcb23182fa2b9b06acbd82993be57f3dc47cc62eb
Author: Arthur Cohen
Date: Tue Apr 8 14:41:16 2025 +0200
gccrs: expansion: Only add fragments if the matcher succeeded
gcc/rust/ChangeLog:
* expand/rust-macro-expand.cc (MacroExpander::match_n_matches): Do
not
insert fragments and substack fragments if the matcher failed.
gcc/testsuite/ChangeLog:
* rust/compile/macros/mbe/macro-issue3708.rs: New test.
Diff:
---
gcc/rust/expand/rust-macro-expand.cc | 15 ++--
.../rust/compile/macros/mbe/macro-issue3708.rs | 80 ++
2 files changed, 88 insertions(+), 7 deletions(-)
diff --git a/gcc/rust/expand/rust-macro-expand.cc
b/gcc/rust/expand/rust-macro-expand.cc
index cd17a3f9ba12..6e62a083ae7a 100644
--- a/gcc/rust/expand/rust-macro-expand.cc
+++ b/gcc/rust/expand/rust-macro-expand.cc
@@ -621,9 +621,10 @@ MacroExpander::match_n_matches (Parser
&parser,
// matched fragment get the offset in the token stream
size_t offs_end = source.get_offs ();
- sub_stack.insert_metavar (
- MatchedFragment (fragment->get_ident ().as_string (),
- offs_begin, offs_end));
+ if (valid_current_match)
+ sub_stack.insert_metavar (
+ MatchedFragment (fragment->get_ident ().as_string (),
+offs_begin, offs_end));
}
break;
@@ -650,15 +651,15 @@ MacroExpander::match_n_matches (Parser
&parser,
}
auto old_stack = sub_stack.pop ();
- // nest metavars into repetitions
- for (auto &ent : old_stack)
- sub_stack.append_fragment (ent.first, std::move (ent.second));
-
// If we've encountered an error once, stop trying to match more
// repetitions
if (!valid_current_match)
break;
+ // nest metavars into repetitions
+ for (auto &ent : old_stack)
+ sub_stack.append_fragment (ent.first, std::move (ent.second));
+
match_amount++;
// Break early if we notice there's too many expressions already
diff --git a/gcc/testsuite/rust/compile/macros/mbe/macro-issue3708.rs
b/gcc/testsuite/rust/compile/macros/mbe/macro-issue3708.rs
new file mode 100644
index ..e5b38bb0da7e
--- /dev/null
+++ b/gcc/testsuite/rust/compile/macros/mbe/macro-issue3708.rs
@@ -0,0 +1,80 @@
+// { dg-additional-options "-frust-name-resolution-2.0
-frust-compile-until=lowering" }
+
+macro_rules! impl_fn_for_zst {
+($(
+$( #[$attr: meta] )*
+struct $Name: ident impl$( <$( $lifetime : lifetime ),+> )? Fn =
+|$( $arg: ident: $ArgTy: ty ),*| -> $ReturnTy: ty
+$body: block;
+)+) => {
+$(
+$( #[$attr] )*
+struct $Name;
+
+impl $( <$( $lifetime ),+> )? Fn<($( $ArgTy, )*)> for $Name {
+#[inline]
+extern "rust-call" fn call(&self, ($( $arg, )*): ($( $ArgTy,
)*)) -> $ReturnTy {
+$body
+}
+}
+
+impl $( <$( $lifetime ),+> )? FnMut<($( $ArgTy, )*)> for $Name {
+#[inline]
+extern "rust-call" fn call_mut(
+&mut self,
+($( $arg, )*): ($( $ArgTy, )*)
+) -> $ReturnTy {
+Fn::call(&*self, ($( $arg, )*))
+}
+}
+
+impl $( <$( $lifetime ),+> )? FnOnce<($( $ArgTy, )*)> for $Name {
+type Output = $ReturnTy;
+
+#[inline]
+extern "rust-call" fn call_once(self, ($( $arg, )*): ($(
$ArgTy, )*)) -> $ReturnTy {
+Fn::call(&self, ($( $arg, )*))
+}
+}
+)+
+}
+}
+
+#[lang = "sized"]
+trait Sized {}
+
+#[lang = "copy"]
+trait Copy {}
+
+#[lang = "fn"]
+pub trait Fn: FnMut {
+/// Performs the call operation.
+#[unstable(feature = "fn_traits", issue = "29625")]
+extern "rust-call" fn call(&self, args: Args) -> Self::Output;
+}
+
+#[lang = "fn_mut"]
+#[must_use = "closures are lazy and do nothing unless called"]
+pub trait FnMut: FnOnce {
+/// Performs the call operation.
+#[unstable(feature = "fn_traits", issue = "29625")]
+extern "rust-call" fn call_mut(&mut self, args: Args) -> Self::Output;
+}
+
+#[lang = "fn_once"]
+pub trait FnOnce {
+/// The returned type after the call operator is used.
+#[lang = "fn_once_output"]
+#[stable(feature = "fn_once_output", since = "1.12.0")]
+type Output;
+
+/// Performs the call operation.
+#[unstable(feature = "fn_traits", issue = "29625")]
+extern "rust-call" fn call_once(self, args: Args) -> Self::Output;
+}
+
+impl_fn_for_zst! {
+#[derive(Copy)]
+struct LinesAnyMap impl<'a> Fn = |line: &'a str| -> () {
+
[gcc r15-9490] libstdc++: Implement formatter for ranges and range_formatter [PR109162]
https://gcc.gnu.org/g:f62e5d720de829cf346b799f3463fee53728ba6c commit r15-9490-gf62e5d720de829cf346b799f3463fee53728ba6c Author: Tomasz Kamiński Date: Fri Mar 28 09:30:22 2025 +0100 libstdc++: Implement formatter for ranges and range_formatter [PR109162] This patch implements formatter specialization for input_ranges and range_formatter class from P2286R8, as adjusted by P2585R1. The formatter for pair/tuple is not yet provided, making maps not formattable. This introduces an new _M_format_range member to internal __formatter_str, that formats range as _CharT as string, according to the format spec. This function transform any contiguous range into basic_string_view directly, by computing size if necessary. Otherwise, for ranges for which size can be computed (forward_range or sized_range) we use a stack buffer, if they are sufficiently small. Finally, we create a basic_string<_CharT> from the range, and format its content. In case when padding is specified, this is handled by firstly formatting the content of the range to the temporary string object. However, this can be only implemented if the iterator of the basic_format_context is internal type-erased iterator used by implementation. Otherwise a new basic_format_context would need to be created, which would require rebinding of handles stored in the arguments: note that format spec for element type could retrieve any format argument from format context, visit and use handle to format it. As basic_format_context provide no user-facing constructor, the user are not able to construct object of that type with arbitrary iterators. The signatures of the user-facing parse and format methods of the provided formatters deviate from the standard by constraining types of params: * _CharT is constrained __formatter::__char * basic_format_parse_context<_CharT> for parse argument * basic_format_context<_Out, _CharT> for format second argument The standard specifies last three of above as unconstrained types. These types are later passed to possibly user-provided formatter specializations, that are required via formattable concept to only accept above types. Finally, the formatter specialization is implemented without using specialization of range-default-formatter exposition only template as base class, while providing same functionality. PR libstdc++/109162 libstdc++-v3/ChangeLog: * include/std/format (__format::__has_debug_format, _Pres_type::_Pres_seq) (_Pres_type::_Pres_str, __format::__Stackbuf_size): Define. (_Separators::_S_squares, _Separators::_S_parens, _Separators::_S_comma) (_Separators::_S_colon): Define additional constants. (_Spec::_M_parse_fill_and_align): Define overload accepting list of excluded characters for fill, and forward existing overload. (__formatter_str::_M_format_range): Define. (__format::_Buf_sink) Use __Stackbuf_size for size of array. (__format::__is_map_formattable, std::range_formatter) (std::formatter<_Rg, _CharT>): Define. * src/c++23/std.cc.in (std::format_kind, std::range_format) (std::range_formatter): Export. * testsuite/std/format/formatter/lwg3944.cc: Guarded tests with __glibcxx_format_ranges. * testsuite/std/format/formatter/requirements.cc: Adjusted for standard behavior. * testsuite/23_containers/vector/bool/format.cc: Test vector formatting. * testsuite/std/format/ranges/format_kind.cc: New test. * testsuite/std/format/ranges/formatter.cc: New test. * testsuite/std/format/ranges/sequence.cc: New test. * testsuite/std/format/ranges/string.cc: New test. Reviewed-by: Jonathan Wakely Signed-off-by: Tomasz Kamiński Diff: --- libstdc++-v3/include/std/format| 505 ++--- libstdc++-v3/src/c++23/std.cc.in | 6 + .../testsuite/23_containers/vector/bool/format.cc | 6 + .../testsuite/std/format/formatter/lwg3944.cc | 4 +- .../testsuite/std/format/formatter/requirements.cc | 14 +- .../testsuite/std/format/ranges/format_kind.cc | 94 .../testsuite/std/format/ranges/formatter.cc | 145 ++ .../testsuite/std/format/ranges/sequence.cc| 190 libstdc++-v3/testsuite/std/format/ranges/string.cc | 226 + 9 files changed, 1125 insertions(+), 65 deletions(-) diff --git a/libstdc++-v3/include/std/format b/libstdc++-v3/include/std/format index 23f00970840f..096dda4f989c 100644 --- a/libstdc++-v3/include/std/format +++ b/libstdc++-v3/include/std/format @@ -97,6 +97,10 @@ namespace __format #define _GLIBCXX_WIDEN_(C, S) ::std::__format::_Widen(S, L##S) #define _GLIBCXX_WIDEN
[gcc r15-9493] libstdc++: Do not declare namespace ranges in unconditionally
https://gcc.gnu.org/g:df59bf20d85384f56395f573f294ddd45327347a
commit r15-9493-gdf59bf20d85384f56395f573f294ddd45327347a
Author: Jonathan Wakely
Date: Tue Apr 15 14:01:55 2025 +0100
libstdc++: Do not declare namespace ranges in unconditionally
Move namespace ranges inside the feature test macro guard, because
'ranges' is not a reserved name before C++20.
libstdc++-v3/ChangeLog:
* include/std/numeric (ranges): Only declare namespace for C++23
and later.
(ranges::iota_result): Fix indentation.
* testsuite/17_intro/names.cc: Check ranges is not used as an
identifier before C++20.
Diff:
---
libstdc++-v3/include/std/numeric | 8 +++-
libstdc++-v3/testsuite/17_intro/names.cc | 4
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/libstdc++-v3/include/std/numeric b/libstdc++-v3/include/std/numeric
index 4d36fcd36d98..490963ee46d1 100644
--- a/libstdc++-v3/include/std/numeric
+++ b/libstdc++-v3/include/std/numeric
@@ -732,12 +732,11 @@ namespace __detail
/// @} group numeric_ops
#endif // C++17
+#if __glibcxx_ranges_iota >= 202202L // C++ >= 23
namespace ranges
{
-#if __glibcxx_ranges_iota >= 202202L // C++ >= 23
-
template
- using iota_result = out_value_result<_Out, _Tp>;
+using iota_result = out_value_result<_Out, _Tp>;
struct __iota_fn
{
@@ -762,9 +761,8 @@ namespace ranges
};
inline constexpr __iota_fn iota{};
-
-#endif // __glibcxx_ranges_iota
} // namespace ranges
+#endif // __glibcxx_ranges_iota
_GLIBCXX_END_NAMESPACE_VERSION
} // namespace std
diff --git a/libstdc++-v3/testsuite/17_intro/names.cc
b/libstdc++-v3/testsuite/17_intro/names.cc
index 4458325e52b3..f67818db425f 100644
--- a/libstdc++-v3/testsuite/17_intro/names.cc
+++ b/libstdc++-v3/testsuite/17_intro/names.cc
@@ -142,6 +142,10 @@
#define try_emplace (
#endif
+#if __cplusplus < 202002L
+#define ranges (
+#endif
+
// These clash with newlib so don't use them.
# define __lockablecannot be used as an identifier
# define __null_sentinel cannot be used as an identifier
[gcc r15-9494] libstdc++: Do not define __cpp_lib_ranges_iota in
https://gcc.gnu.org/g:25775e73ea4d40a55a26b71c42cc6509caf4845f commit r15-9494-g25775e73ea4d40a55a26b71c42cc6509caf4845f Author: Jonathan Wakely Date: Tue Apr 15 14:00:23 2025 +0100 libstdc++: Do not define __cpp_lib_ranges_iota in In r14-7153-gadbc46942aee75 we removed a duplicate definition of __glibcxx_want_range_iota from , but __cpp_lib_ranges_iota should be defined in at all. libstdc++-v3/ChangeLog: * include/std/ranges (__glibcxx_want_ranges_iota): Do not define. Diff: --- libstdc++-v3/include/std/ranges | 1 - 1 file changed, 1 deletion(-) diff --git a/libstdc++-v3/include/std/ranges b/libstdc++-v3/include/std/ranges index 7a339c51368e..9300c364a165 100644 --- a/libstdc++-v3/include/std/ranges +++ b/libstdc++-v3/include/std/ranges @@ -64,7 +64,6 @@ #define __glibcxx_want_ranges_chunk #define __glibcxx_want_ranges_chunk_by #define __glibcxx_want_ranges_enumerate -#define __glibcxx_want_ranges_iota #define __glibcxx_want_ranges_join_with #define __glibcxx_want_ranges_repeat #define __glibcxx_want_ranges_slide
[gcc r15-9498] Regenerate common.opt.urls
https://gcc.gnu.org/g:5621b3b5c9ebd98f1f18787a6fceb015d19d33a5 commit r15-9498-g5621b3b5c9ebd98f1f18787a6fceb015d19d33a5 Author: Kyrylo Tkachov Date: Tue Apr 15 09:22:05 2025 -0700 Regenerate common.opt.urls Signed-off-by: Kyrylo Tkachov * common.opt.urls: Regenerate. Diff: --- gcc/common.opt.urls | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/common.opt.urls b/gcc/common.opt.urls index a4b14f5241fc..8bd75b1153b0 100644 --- a/gcc/common.opt.urls +++ b/gcc/common.opt.urls @@ -868,6 +868,9 @@ UrlSuffix(gcc/Optimize-Options.html#index-fipa-bit-cp) fipa-modref UrlSuffix(gcc/Optimize-Options.html#index-fipa-modref) +fipa-reorder-for-locality +UrlSuffix(gcc/Optimize-Options.html#index-fipa-reorder-for-locality) + fipa-profile UrlSuffix(gcc/Optimize-Options.html#index-fipa-profile)
[gcc(refs/users/omachota/heads/rtl-ssa-dce)] rtl-ssa-dce: remove useless conditions and fix dead debug insns
https://gcc.gnu.org/g:f495eae10735f687366a59884a25561de823daff
commit f495eae10735f687366a59884a25561de823daff
Author: Ondřej Machota
Date: Tue Apr 15 09:21:56 2025 +0200
rtl-ssa-dce: remove useless conditions and fix dead debug insns
Diff:
---
gcc/dce.cc | 87 ++
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git a/gcc/dce.cc b/gcc/dce.cc
index 40b4cd991151..630906fb1ec6 100644
--- a/gcc/dce.cc
+++ b/gcc/dce.cc
@@ -123,6 +123,8 @@ can_delete_call (rtx_insn *insn)
return true;
}
+static bool inside_ud = false;
+
/* Return true if INSN is a normal instruction that can be deleted by
the DCE pass. */
@@ -578,8 +580,6 @@ reset_unmarked_insns_debug_uses (void)
}
/* Delete every instruction that hasn't been marked. */
-static bool inside_ud = false;
-
static void
delete_unmarked_insns (void)
{
@@ -819,7 +819,6 @@ fini_dce (bool fast)
static unsigned int
rest_of_handle_ud_dce (void)
{
- inside_ud = true;
rtx_insn *insn;
init_dce (false);
@@ -833,6 +832,7 @@ rest_of_handle_ud_dce (void)
}
worklist.release ();
+ inside_ud = true;
if (MAY_HAVE_DEBUG_BIND_INSNS)
reset_unmarked_insns_debug_uses ();
@@ -1381,9 +1381,8 @@ bool is_rtx_insn_prelive(rtx_insn *insn) {
gcc_assert(GET_CODE(insn) == INSN);
/* Don't delete insns that may throw if we cannot do so. */
- if (!(cfun->can_delete_dead_exceptions && can_alter_cfg)
- && !insn_nothrow_p (insn))
-return true;
+ if (!cfun->can_delete_dead_exceptions && !insn_nothrow_p (insn))
+ return true;
/* Callee-save restores are needed. */
if (RTX_FRAME_RELATED_P (insn) && crtl->shrink_wrapped_separate
@@ -1410,8 +1409,8 @@ bool is_rtx_insn_prelive(rtx_insn *insn) {
bool is_prelive(insn_info *insn)
{
- /* Phi insns are never prelive, bb head and end contain artificial uses that
- we need to mark as prelive */
+ /* Phi insns and debug insns are never prelive, bb head and end contain
+ artificial uses that we need to mark as prelive */
if (insn->is_bb_head() || insn->is_bb_end())
return true;
@@ -1468,6 +1467,9 @@ rtl_ssa_dce_mark_prelive_insn(insn_info *insn,
auto_vec &worklist,
static auto_vec
rtl_ssa_dce_mark_prelive(std::unordered_set &marked)
{
+ if (dump_file)
+fprintf(dump_file, "DCE: prelive phase\n");
+
auto_vec worklist;
for (insn_info * insn : crtl->ssa->all_insns()) {
if (is_prelive(insn))
@@ -1478,12 +1480,13 @@ rtl_ssa_dce_mark_prelive(std::unordered_set &marked)
}
static std::unordered_set
-rtl_ssa_dce_mark()
+rtl_ssa_dce_mark(std::unordered_set &marked_phis)
{
- std::unordered_set marked{};
/* Phi insn might have more that one phi node:
gcc/gcc/testsuite/gcc.c-torture/execute/2224-1.c */
- std::unordered_set marked_phi_nodes{};
+ std::unordered_set marked{};
auto worklist = rtl_ssa_dce_mark_prelive(marked);
+ if (dump_file)
+fprintf(dump_file, "DCE: marking phase\n");
while (!worklist.is_empty()) {
set_info* set = worklist.pop();
@@ -1505,10 +1508,10 @@ rtl_ssa_dce_mark()
might be used. */
phi_info* pi = as_a (set);
auto pi_uid = pi->uid();
- if (marked_phi_nodes.count(pi) > 0)
+ if (marked_phis.count(pi) > 0)
continue;
- marked_phi_nodes.emplace(pi);
+marked_phis.emplace(pi);
uses = pi->inputs();
}
@@ -1527,37 +1530,43 @@ rtl_ssa_dce_mark()
return marked;
}
+// Iterate over non-debug instructions in RPO and remove all aren't marked.
static void
rtl_ssa_dce_sweep(std::unordered_set marked)
{
- /* We can get the number of items in the `marked` set and create an array
- of changes with appropriate size */
+ if (dump_file)
+fprintf(dump_file, "DCE: Sweep phase\n");
+
auto_vec to_delete;
- for (insn_info * insn : crtl->ssa->all_insns()) {
-/* Artificial and marked insns cannot be deleted.
- There is a slight problem with phis, because we might want to delete
- some phi nodes from phi insn. */
-if (insn->is_artificial() || insn->is_debug_insn() || marked.count(insn) >
0)
+ for (insn_info * insn : crtl->ssa->nondebug_insns()) {
+// Artificial or marked insns cannot be deleted.
+if (insn->is_artificial() || marked.count(insn) > 0)
continue;
-auto change = insn_change::delete_insn(insn);
-to_delete.safe_push(change);
if (dump_file)
- fprintf(dump_file, "Sweeping insn %d\n", insn->uid());
-/* crtl->ssa->change_insn(change); */
+ fprintf(dump_file, "Sweeping insn: %d\n", insn->uid());
+
+auto change = insn_change::delete_insn(insn);
+to_delete.safe_push(std::move(change));
+
+// If we use following way with reverse_nondebug_insns, not all insns seem
+// to be deleted...
+// crtl->ssa->change_insn(change);
}
- auto attempt = crtl->ssa->new_change_attempt ();
auto_vec changes(to_delete.length());
for (size_t i = 0; i != to_delete.length(); ++i)
[gcc r15-9478] libstdc++: Fix std::string construction from volatile char* [PR119748]
https://gcc.gnu.org/g:05d3aebe24be1177851574ab224f16492c5050fd
commit r15-9478-g05d3aebe24be1177851574ab224f16492c5050fd
Author: Jonathan Wakely
Date: Fri Apr 11 22:13:14 2025 +0100
libstdc++: Fix std::string construction from volatile char* [PR119748]
My recent r15-9381-g648d5c26e25497 change assumes that a contiguous
iterator with the correct value_type can be converted to a const charT*
but that's not true for volatile charT*. The optimization should only be
done if it can be converted to the right pointer type.
Additionally, some generic loops for non-contiguous iterators need an
explicit cast to deal with iterator reference types that do not bind to
the const charT& parameter of traits_type::assign.
libstdc++-v3/ChangeLog:
PR libstdc++/119748
* include/bits/basic_string.h (_S_copy_chars): Only optimize for
contiguous iterators that are convertible to const charT*. Use
explicit conversion to charT after dereferencing iterator.
(_S_copy_range): Likewise for contiguous ranges.
* include/bits/basic_string.tcc (_M_construct): Use explicit
conversion to charT after dereferencing iterator.
* include/bits/cow_string.h (_S_copy_chars): Likewise.
(basic_string(from_range_t, R&&, const Allocator&)): Likewise.
Only optimize for contiguous iterators that are convertible to
const charT*.
* testsuite/21_strings/basic_string/cons/char/119748.cc: New
test.
* testsuite/21_strings/basic_string/cons/wchar_t/119748.cc:
New test.
Reviewed-by: Tomasz Kaminski
Diff:
---
libstdc++-v3/include/bits/basic_string.h | 24 ++-
libstdc++-v3/include/bits/basic_string.tcc | 3 +-
libstdc++-v3/include/bits/cow_string.h | 17 +++
.../21_strings/basic_string/cons/char/119748.cc| 35 ++
.../21_strings/basic_string/cons/wchar_t/119748.cc | 7 +
5 files changed, 73 insertions(+), 13 deletions(-)
diff --git a/libstdc++-v3/include/bits/basic_string.h
b/libstdc++-v3/include/bits/basic_string.h
index 9c431c765ab4..c90bd099b639 100644
--- a/libstdc++-v3/include/bits/basic_string.h
+++ b/libstdc++-v3/include/bits/basic_string.h
@@ -488,8 +488,11 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
is_same<_IterBase, const _CharT*>>::value)
_S_copy(__p, std::__niter_base(__k1), __k2 - __k1);
#if __cpp_lib_concepts
- else if constexpr (contiguous_iterator<_Iterator>
- && is_same_v, _CharT>)
+ else if constexpr (requires {
+ requires contiguous_iterator<_Iterator>;
+ { std::to_address(__k1) }
+-> convertible_to;
+})
{
const auto __d = __k2 - __k1;
(void) (__k1 + __d); // See P3349R1
@@ -499,7 +502,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
else
#endif
for (; __k1 != __k2; ++__k1, (void)++__p)
- traits_type::assign(*__p, *__k1); // These types are off.
+ traits_type::assign(*__p, static_cast<_CharT>(*__k1));
}
#pragma GCC diagnostic pop
@@ -527,12 +530,19 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
static constexpr void
_S_copy_range(pointer __p, _Rg&& __rg, size_type __n)
{
- if constexpr (ranges::contiguous_range<_Rg>
- && is_same_v, _CharT>)
+ if constexpr (requires {
+ requires ranges::contiguous_range<_Rg>;
+ { ranges::data(std::forward<_Rg>(__rg)) }
+ -> convertible_to;
+ })
_S_copy(__p, ranges::data(std::forward<_Rg>(__rg)), __n);
else
- for (auto&& __e : __rg)
- traits_type::assign(*__p++, std::forward(__e));
+ {
+ auto __first = ranges::begin(__rg);
+ const auto __last = ranges::end(__rg);
+ for (; __first != __last; ++__first)
+ traits_type::assign(*__p++, static_cast<_CharT>(*__first));
+ }
}
#endif
diff --git a/libstdc++-v3/include/bits/basic_string.tcc
b/libstdc++-v3/include/bits/basic_string.tcc
index 02230aca5d27..bca55bc56581 100644
--- a/libstdc++-v3/include/bits/basic_string.tcc
+++ b/libstdc++-v3/include/bits/basic_string.tcc
@@ -210,7 +210,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
_M_data(__another);
_M_capacity(__capacity);
}
- traits_type::assign(_M_data()[__len++], *__beg);
+ traits_type::assign(_M_data()[__len++],
+ static_cast<_CharT>(*__beg));
++__beg;
}
diff --git a/libstdc++-v3/include/bits/cow_string.h
b/libstdc++-v3/include/bits/cow_string.
[gcc r13-9527] phiopt: Reset the number of iterations information of a loop when changing an exit from the loop [PR
https://gcc.gnu.org/g:cd53c305d46b88549f80de6145a52c5447c9c57e
commit r13-9527-gcd53c305d46b88549f80de6145a52c5447c9c57e
Author: Andrew Pinski
Date: Mon Dec 2 08:35:23 2024 -0800
phiopt: Reset the number of iterations information of a loop when changing
an exit from the loop [PR117243]
After r12-5300-gf98f373dd822b3, phiopt could get the following bb structure:
|
middle-bb -|
||
| || |
phi<1, 2> | |
cond | |
|| |
|+---|
Which was considered 2 loops. The inner loop had esimtate of upper_bound to
be 8,
due to the original `for (b = 0; b <= 7; b++)`. The outer loop was already
an
infinite one.
So phiopt would come along and change the condition to be unconditionally
true,
we change the inner loop to being an infinite one but don't reset the
estimate
on the loop and cleanup cfg comes along and changes it into one loop but
also
does not reset the estimate of the loop. Then the loop unrolling uses the
old estimate
and decides to add an unreachable there.o
So the fix is when phiopt changes an exit to a loop, reset the estimates,
similar to
how cleanupcfg does it when merging some basic blocks.
Bootstrapped and tested on x86_64-linux-gnu.
PR tree-optimization/117243
PR tree-optimization/116749
gcc/ChangeLog:
* tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Reset loop
estimates if the cond_block was an exit to a loop.
gcc/testsuite/ChangeLog:
* gcc.dg/torture/pr117243-1.c: New test.
* gcc.dg/torture/pr117243-2.c: New test.
Signed-off-by: Andrew Pinski
(cherry picked from commit b7c69cc072ef0da36439ebc55c513b48e68391b7)
Diff:
---
gcc/testsuite/gcc.dg/torture/pr117243-1.c | 30 +++
gcc/testsuite/gcc.dg/torture/pr117243-2.c | 34 +++
gcc/tree-ssa-phiopt.cc| 11 ++
3 files changed, 75 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/torture/pr117243-1.c
b/gcc/testsuite/gcc.dg/torture/pr117243-1.c
new file mode 100644
index ..c4bbc31467c5
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr117243-1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-tree-optimized" } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
+
+/* PR tree-optimization/117243 */
+/* foo should be an infinite but sometimes it gets optimized incorrectly into
+ an __builtin_unreachable(); which is not valid. */
+void
+foo (unsigned int a, unsigned char b)
+{
+ lbl:
+ for (b = 0; b <= 7; b++)
+{
+ unsigned char c[1][1];
+ int i, j;
+ for (i = 0; i < 1; i++)
+for (j = 0; j < 1; j++)
+ c[i][j] = 1;
+ if (b)
+ goto lbl;
+}
+}
+
+int
+main ()
+{
+ foo (1, 2);
+}
+
+/* { dg-final { scan-tree-dump-not "__builtin_unreachable " "optimized"} } */
diff --git a/gcc/testsuite/gcc.dg/torture/pr117243-2.c
b/gcc/testsuite/gcc.dg/torture/pr117243-2.c
new file mode 100644
index ..d9b0d3eeb982
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr117243-2.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-fno-tree-ch -fdump-tree-optimized" } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
+
+/* PR tree-optimization/117243 */
+/* PR tree-optimization/116749 */
+
+/* main1 should be an infinite but sometimes it gets optimized incorrectly into
+ an __builtin_unreachable(); which is not valid. */
+int main1 (void)
+{
+int g=0;
+int l1[1];
+int *l2 = &g;
+int i;
+for (i=0; i<1; i++)
+l1[i] = (1);
+for (g=0; g; ++g)
+{
+int *l3[1] = {&l1[0]};
+}
+*l2 = *l1;
+b:
+for (i=0; i<2; ++i)
+{
+if (i)
+goto b;
+if (g)
+continue;
+}
+return 0;
+}
+
+/* { dg-final { scan-tree-dump-not "__builtin_unreachable " "optimized"} } */
diff --git a/gcc/tree-ssa-phiopt.cc b/gcc/tree-ssa-phiopt.cc
index 06b099d517f9..9856d3e139e6 100644
--- a/gcc/tree-ssa-phiopt.cc
+++ b/gcc/tree-ssa-phiopt.cc
@@ -54,6 +54,7 @@ along with GCC; see the file COPYING3. If not see
#include "dbgcnt.h"
#include "tree-ssa-propagate.h"
#include "tree-ssa-dce.h"
+#include "tree-ssa-loop-niter.h"
static unsigned int tree_ssa_phiopt_worker (bool, bool, bool);
static bool two_value_replacement (basic_block, basic_block, edge, gphi *,
@@ -455,6 +456,16 @@ replace_phi_edge_with_variable (basic_block cond_block,
else
gcc_unreachable ();
+ /* If we are removing the cond on a loop exit,
+ reset number of iteration information of the loop. */
+ if (loop_exits_from_bb_p (cond_block->loop_father, cond_block))
+{
+ auto loop = cond_block->loop_father;
+ free_numbers_of_iterations_estimates (loop);
+ loop->any_upper_bound =
[gcc r13-9529] libstdc++: Document thread-safety for COW std::string [PR21334]
https://gcc.gnu.org/g:bbca95724c62ad1f860c2544e2b688b25ba79ec2 commit r13-9529-gbbca95724c62ad1f860c2544e2b688b25ba79ec2 Author: Jonathan Wakely Date: Fri Apr 11 11:08:34 2025 +0100 libstdc++: Document thread-safety for COW std::string [PR21334] The gcc4-compatible copy-on-write std::string does not conform to the C++11 requirements on data race avoidance in standard containers. Specifically, calling non-const member functions such as begin() and data() needs to do the "copy on write" operation and so is most definitely a modification of the object. As such, those non-const members must not be called concurrently with any other uses of the string object. libstdc++-v3/ChangeLog: PR libstdc++/21334 * doc/xml/manual/using.xml: Document that container data race avoidance rules do not apply to COW std::string. * doc/html/*: Regenerate. (cherry picked from commit dd35f66287b7cca196a720c9641e463255dceb1c) Diff: --- libstdc++-v3/doc/html/manual/using_concurrency.html | 10 ++ libstdc++-v3/doc/xml/manual/using.xml | 12 2 files changed, 22 insertions(+) diff --git a/libstdc++-v3/doc/html/manual/using_concurrency.html b/libstdc++-v3/doc/html/manual/using_concurrency.html index e09fc5e15bcb..f99cca414ec8 100644 --- a/libstdc++-v3/doc/html/manual/using_concurrency.html +++ b/libstdc++-v3/doc/html/manual/using_concurrency.html @@ -126,6 +126,16 @@ gcc version 4.1.2 20070925 (Red Hat 4.1.2-33) the container the iterator refers to (for example incrementing a list iterator must access the pointers between nodes, which are part of the container and so conflict with other accesses to the container). + +The Copy-On-Write std::string implementation +used before GCC 5 (and with +_GLIBCXX_USE_CXX11_ABI=0) +is not a standard container and does not conform to the data race +avoidance rules described above. For the Copy-On-Write +std::string, non-const member functions such as +begin() are considered to be modifying accesses +and so must not be used concurrently with any other accesses to the +same object. Programs which follow the rules above will not encounter data races in library code, even when using library types which share state between distinct objects. In the example below the diff --git a/libstdc++-v3/doc/xml/manual/using.xml b/libstdc++-v3/doc/xml/manual/using.xml index 3710465e5c1d..4e627654d97a 100644 --- a/libstdc++-v3/doc/xml/manual/using.xml +++ b/libstdc++-v3/doc/xml/manual/using.xml @@ -1914,6 +1914,18 @@ gcc version 4.1.2 20070925 (Red Hat 4.1.2-33) of the container and so conflict with other accesses to the container). + +The Copy-On-Write std::string implementation +used before GCC 5 (and with +_GLIBCXX_USE_CXX11_ABI=0) +is not a standard container and does not conform to the data race +avoidance rules described above. For the Copy-On-Write +std::string, non-const member functions such as +begin() are considered to be modifying accesses +and so must not be used concurrently with any other accesses to the +same object. + + Programs which follow the rules above will not encounter data races in library code, even when using library types which share state between distinct objects. In the example below the
