https://gcc.gnu.org/g:4a01869b963520d689fe9242cf2ff24984ea41d8
commit r15-9496-g4a01869b963520d689fe9242cf2ff24984ea41d8
Author: Jan Hubicka <hubi...@ucw.cz>
Date: Tue Apr 15 19:09:20 2025 +0200
Set znver5 issue rate to 4.
this patch sets issue rate of znver5 to 4. With current model, unless a
reservation is
missing, we will never issue more than 4 instructions per cycle since that
is the limit
of decoders and the model does not take into acount the fact that typically
code is run
from op cache.
gcc/ChangeLog:
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Set
to 4 for znver5.
Diff:
---
gcc/config/i386/x86-tune-sched.cc | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/x86-tune-sched.cc
b/gcc/config/i386/x86-tune-sched.cc
index 685a83c4311b..15d3d91a83b6 100644
--- a/gcc/config/i386/x86-tune-sched.cc
+++ b/gcc/config/i386/x86-tune-sched.cc
@@ -81,6 +81,14 @@ ix86_issue_rate (void)
case PROCESSOR_YONGFENG:
case PROCESSOR_SHIJIDADAO:
case PROCESSOR_GENERIC:
+ /* For znver5 decoder can handle 4 or 8 instructions per cycle,
+ op cache 12 instruction/cycle, dispatch 8 instructions
+ integer rename 8 instructions and Fp 6 instructions.
+
+ The scheduler, without understanding out of order nature of the CPU
+ is not going to be able to use more than 4 instructions since that
+ is limits of the decoders. */
+ case PROCESSOR_ZNVER5:
return 4;
case PROCESSOR_ICELAKE_CLIENT:
@@ -91,13 +99,6 @@ ix86_issue_rate (void)
return 5;
case PROCESSOR_SAPPHIRERAPIDS:
- /* For znver5 decoder can handle 4 or 8 instructions per cycle,
- op cache 12 instruction/cycle, dispatch 8 instructions
- integer rename 8 instructions and Fp 6 instructions.
-
- The scheduler, without understanding out of order nature of the CPU
- is unlikely going to be able to fill all of these. */
- case PROCESSOR_ZNVER5:
return 6;
default:
