[gcc r15-8988] testsuite: Fix up strub-internal-pr112938.C test for C++2{0, 3, 6}

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:50f8148a2754a1552704c6852c336ad008695388

commit r15-8988-g50f8148a2754a1552704c6852c336ad008695388
Author: Jakub Jelinek 
Date:   Thu Mar 27 21:21:48 2025 +0100

testsuite: Fix up strub-internal-pr112938.C test for C++2{0,3,6}

On Thu, Mar 27, 2025 at 12:05:21AM +, Sam James wrote:
> The test was being ignored because dg.exp looks for .C in g++.dg/.
>
> gcc/testsuite/ChangeLog:
>   PR middle-end/112938
>
>   * g++.dg/strub-internal-pr112938.cc: Move to...
>   * g++.dg/strub-internal-pr112938.C: ...here.

This regressed the test for C++20 and higher:
FAIL: g++.dg/strub-internal-pr112938.C  -std=gnu++20 (test for excess 
errors)
FAIL: g++.dg/strub-internal-pr112938.C  -std=gnu++23 (test for excess 
errors)
FAIL: g++.dg/strub-internal-pr112938.C  -std=gnu++26 (test for excess 
errors)

Here is a fix.

2025-03-27  Jakub Jelinek  

* g++.dg/strub-internal-pr112938.C: Add dg-warning for c++20.

Diff:
---
 gcc/testsuite/g++.dg/strub-internal-pr112938.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/strub-internal-pr112938.C 
b/gcc/testsuite/g++.dg/strub-internal-pr112938.C
index 933a4fbdecf7..7d7023c1b6c0 100644
--- a/gcc/testsuite/g++.dg/strub-internal-pr112938.C
+++ b/gcc/testsuite/g++.dg/strub-internal-pr112938.C
@@ -3,7 +3,7 @@
 /* { dg-require-effective-target strub } */
 
 bool __attribute__ ((__strub__ ("internal")))
-f(bool i, volatile bool j)
+f(bool i, volatile bool j) /* { dg-warning "'volatile'-qualified parameter 
is deprecated" "" { target c++20 } } */
 {
   return (i ^ j) == j;
 }

[gcc r15-8989] i386: Fix offset calculation in ix86_redzone_clobber

[Uros Bizjak via Gcc-cvs]

https://gcc.gnu.org/g:2af32814cf2ba3c632fd5a3f69f275613383723d

commit r15-8989-g2af32814cf2ba3c632fd5a3f69f275613383723d
Author: Uros Bizjak 
Date:   Thu Mar 27 21:25:36 2025 +0100

i386: Fix offset calculation in ix86_redzone_clobber

plus_constant expects integer as its third argument, not rtx.

gcc/ChangeLog:

* config/i386/i386.cc (ix86_redzone_clobber): Use integer, not rtx
as the third argument of plus_constant.

Diff:
---
 gcc/config/i386/i386.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 18127bcada81..f38e3db41fa9 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -26465,8 +26465,7 @@ ix86_redzone_clobber ()
   cfun->machine->asm_redzone_clobber_seen = true;
   if (ix86_using_red_zone ())
 {
-  rtx base = plus_constant (Pmode, stack_pointer_rtx,
-   GEN_INT (-RED_ZONE_SIZE));
+  rtx base = plus_constant (Pmode, stack_pointer_rtx, -RED_ZONE_SIZE);
   rtx mem = gen_rtx_MEM (BLKmode, base);
   set_mem_size (mem, RED_ZONE_SIZE);
   return mem;

[gcc(refs/users/meissner/heads/work198)] Change TARGET_POPCNTD to TARGET_POWER7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c8f4c7910f04712adf4cc35f3d3c3161ec7ca2b6

commit c8f4c7910f04712adf4cc35f3d3c3161ec7ca2b6
Author: Michael Meissner 
Date:   Thu Mar 27 18:58:00 2025 -0400

Change TARGET_POPCNTD to TARGET_POWER7.

This patch changes TARGET_POPCNTD to TARGET_POWER7.  The -mpopcntd switch 
is not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.6 (Power7).

2025-03-27  Michael Meissner  

gcc/

* gcc/config/rs6000/dfp.md (cmp_internal1): Change 
TARGET_POPCNTD
to TARGET_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare): 
Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_POWER7): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-string.cc  |  2 +-
 gcc/config/rs6000/rs6000.cc |  8 
 gcc/config/rs6000/rs6000.h  | 21 +++--
 gcc/config/rs6000/rs6000.md | 20 ++--
 6 files changed, 29 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 59fa66ae15c8..5919149682b2 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index dbb8520ab039..2366b2aee00a 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P6_64:
   return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POPCNTD;
+  return TARGET_POWER7;
 case ENB_P7_64:
-  return TARGET_POPCNTD && TARGET_POWERPC64;
+  return TARGET_POWER7 && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index 3d2911ca08a0..703f77fa0bf1 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1949,7 +1949,7 @@ bool
 expand_block_compare (rtx operands[])
 {
   /* TARGET_POPCNTD is already guarded at expand cmpmemsi.  */
-  gcc_assert (TARGET_POPCNTD);
+  gcc_assert (TARGET_POWER7);
 
   /* For P8, this case is complicated to handle because the subtract
  with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c01af37200ac..503b07339647 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1924,7 +1924,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
  if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
 
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
 
  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -3918,7 +3918,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_VSX)
 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
+  else if (TARGET_POWER7)
 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_DFP)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
@@ -4131,7 +4131,7 @@ rs6000_option_override_internal (bool global_init_p)
   else if (TARGET_LONG_DOUBLE_128)
 

[gcc(refs/users/meissner/heads/work198)] Change TARGET_MODULO to TARGET_POWER9.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e4017d644daf8f81e9ab9b70046a4eb61f5ce5a9

commit e4017d644daf8f81e9ab9b70046a4eb61f5ce5a9
Author: Michael Meissner 
Date:   Thu Mar 27 18:58:58 2025 -0400

Change TARGET_MODULO to TARGET_POWER9.

This patch changes TARGET_MODULO to TARGET_POWER9.  The -mmodulo switch is 
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 3.0 (Power9).

2025-03-27  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_MODULO to TARGET_POWER9.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
(TARGET_POWER9): New macro.
* gcc/config/rs6000/rs6000.md (enabled attribute): Change 
TARGET_MODULO
to TARGET_POWER9.
(mod3): Likewise.
(umod3): Likewise.
(divide/modulo peephole2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  7 ---
 gcc/config/rs6000/rs6000.md | 14 +++---
 4 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 2366b2aee00a..d8ff7cf32dfd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 503b07339647..8d97b265ac91 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3888,7 +3888,7 @@ rs6000_option_override_internal (bool global_init_p)
 
   /* For the newer switches (vsx, dfp, etc.) set some of the older options,
  unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+  if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_P9_MINMAX)
 {
@@ -22377,7 +22377,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int 
outer_code,
*total = rs6000_cost->divsi;
}
   /* Add in shift and subtract for MOD unless we have a mod instruction. */
-  if ((!TARGET_MODULO
+  if ((!TARGET_POWER9
   || (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode)))
 && (code == MOD || code == UMOD))
*total += COSTS_N_INSNS (2);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f1da5d31441a..c2f1910b0ea2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -463,9 +463,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID   (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD  TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD  TARGET_POWER9
 
 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.  
*/
 #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -504,6 +504,7 @@ extern int rs6000_vector_align[];
 #define TARGET_POWER5X TARGET_FPRND
 #define TARGET_POWER6  TARGET_CMPB
 #define TARGET_POWER7  TARGET_POPCNTD
+#define TARGET_POWER9  TARGET_MODULO
 
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 87ec37a9f8e4..db1b6c2d1164 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
  (const_int 1)
 
  (and (eq_attr "isa" "p9v")
@@ -3457,7 +3457,7 @@
   || INTVAL (operands[2]) <= 0
   || (i = exact_log2 (INTVAL (operands[2]))) < 0)
 {
-  if (!TARGET_MODULO)
+  if (!TARGET_POWER9)
FAIL;
 
   operands[2] = force_reg (mode, operands[2]);
@@ -3491,7 +3491,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
 (mod:GPR (match_oper

[gcc(refs/users/meissner/heads/work198)] Change TARGET_POPCNTB to TARGET_POWER5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0ff10700b4fc7ede1564ef2928597c0545ae21dd

commit 0ff10700b4fc7ede1564ef2928597c0545ae21dd
Author: Michael Meissner 
Date:   Thu Mar 27 18:52:38 2025 -0400

Change TARGET_POPCNTB to TARGET_POWER5.

This patch changes TARGET_POPCNTB to TARGET_POWER5.  The -mpopcntb switch 
is not
being changed in this patch, just the name of the macros used to determine 
if
the PowerPC processor supports ISA 2.2 (Power5).

2025-03-27  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_POWER5): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTB to TARGET_POWER5.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/config/rs6000/rs6000.h  | 11 +++
 gcc/config/rs6000/rs6000.md |  2 +-
 4 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 111802381acb..4ed2bc1ca89e 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 737c3d6f7c75..a5ed93702494 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3926,7 +3926,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_FPRND)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
+  else if (TARGET_POWER5)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
   else if (TARGET_ALTIVEC)
 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index db6112a09e11..d9a0ffe9f5b2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -448,7 +448,7 @@ extern int rs6000_vector_align[];
Enable 32-bit fcfid's on any of the switches for newer ISA machines.  */
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
-|| TARGET_POPCNTB  /* ISA 2.02 */  \
+|| TARGET_POWER5   /* ISA 2.02 */  \
 || TARGET_CMPB /* ISA 2.05 */  \
 || TARGET_POPCNTD) /* ISA 2.06 */
 
@@ -499,6 +499,9 @@ extern int rs6000_vector_align[];
 #define TARGET_MINMAX  (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
 && (TARGET_P9_MINMAX || !flag_trapping_math))
 
+/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
+#define TARGET_POWER5  TARGET_POPCNTB
+
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
options that have not yet been replaced by their OPTION_MASK_
@@ -525,7 +528,7 @@ extern int rs6000_vector_align[];
 
 #define TARGET_EXTRA_BUILTINS  (TARGET_POWERPC64\
 || TARGET_PPC_GPOPT /* 970/power4 */\
-|| TARGET_POPCNTB   /* ISA 2.02 */  \
+|| TARGET_POWER5/* ISA 2.02 */  \
 || TARGET_CMPB  /* ISA 2.05 */  \
 || TARGET_POPCNTD   /* ISA 2.06 */  \
 || TARGET_ALTIVEC   \
@@ -541,9 +544,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRE (TARGET_HARD_FLOAT \
-&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
+&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
 
-#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \
+#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \
 && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9c718ca2a226..c5bd273be8b3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs

[gcc(refs/users/meissner/heads/work198)] Change TARGET_CMPB to TARGET_POWER6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2f2376163661434d35fa3ec736a6e7b410246335

commit 2f2376163661434d35fa3ec736a6e7b410246335
Author: Michael Meissner 
Date:   Thu Mar 27 18:57:05 2025 -0400

Change TARGET_CMPB to TARGET_POWER6.

This patch changes TARGET_CMPB to TARGET_POWER6.  The -mcmpb switch is not 
being
changed, just the name of the macros used to determine if the PowerPC 
processor
supports ISA 2.5 (Power6).

2025-03-27  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_POWER6): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Likewise.
(cmpb3): Likewise.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc |  8 
 gcc/config/rs6000/rs6000.h  |  7 ---
 gcc/config/rs6000/rs6000.md | 16 
 4 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 4ed2bc1ca89e..dbb8520ab039 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b2811d963fcf..c01af37200ac 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3922,7 +3922,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_DFP)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
+  else if (TARGET_POWER6)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
@@ -4797,7 +4797,7 @@ rs6000_option_override_internal (bool global_init_p)
  DERAT mispredict penalty.  However the LVE and STVE altivec instructions
  need indexed accesses and the type used is the scalar type of the element
  being loaded or stored.  */
-TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
+TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
  && !TARGET_ALTIVEC);
 
   /* Set the -mrecip options.  */
@@ -22396,7 +22396,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int 
outer_code,
   return false;
 
 case PARITY:
-  *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
+  *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
   return false;
 
 case NOT:
@@ -23223,7 +23223,7 @@ rs6000_emit_parity (rtx dst, rtx src)
   tmp = gen_reg_rtx (mode);
 
   /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can.  */
-  if (TARGET_CMPB)
+  if (TARGET_POWER6)
 {
   if (mode == SImode)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3794e3c0658d..5b8cf054f98a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
 || TARGET_POWER5   /* ISA 2.02 */  \
-|| TARGET_CMPB /* ISA 2.05 */  \
+|| TARGET_POWER6   /* ISA 2.05 */  \
 || TARGET_POPCNTD) /* ISA 2.06 */
 
 #define TARGET_FCTIDZ  TARGET_FCFID
 #define TARGET_STFIWX  TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX  TARGET_CMPB
+#define TARGET_LFIWAX  TARGET_POWER6
 #define TARGET_LFIWZX  TARGET_POPCNTD
 #define TARGET_FCFIDS  TARGET_POPCNTD
 #define TARGET_FCFIDU  TARGET_POPCNTD
@@ -502,6 +502,7 @@ extern int rs6000_vector_align[];
 /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
 #define TARGET_POWER5  TARGET_POPCNTB
 #define TARGET_POWER5X TARGET_FPRND
+#define TARGET_POWER6

[gcc(refs/users/meissner/heads/work198)] Change TARGET_FPRND to TARGET_POWER5X.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:47c8b159f0981dca440bac9e446337d191125ed5

commit 47c8b159f0981dca440bac9e446337d191125ed5
Author: Michael Meissner 
Date:   Thu Mar 27 18:54:32 2025 -0400

Change TARGET_FPRND to TARGET_POWER5X.

This patch changes TARGET_POWER5X to TARGET_POWER5.  The -mfprnd switch is 
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.4 (Power5x).

2025-03-27  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Change TARGET_FPRND to TARGET_POWER5X.
* gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro.
* gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to
TARGET_POWER5X.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  1 +
 gcc/config/rs6000/rs6000.md | 14 +++---
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a5ed93702494..b2811d963fcf 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3924,7 +3924,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POWER5)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
@@ -3951,7 +3951,7 @@ rs6000_option_override_internal (bool global_init_p)
   rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
 }
 
-  if (!TARGET_FPRND && TARGET_VSX)
+  if (!TARGET_POWER5X && TARGET_VSX)
 {
   if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
/* TARGET_VSX = 1 implies Power 7 and newer */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d9a0ffe9f5b2..3794e3c0658d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -501,6 +501,7 @@ extern int rs6000_vector_align[];
 
 /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
 #define TARGET_POWER5  TARGET_POPCNTB
+#define TARGET_POWER5X TARGET_FPRND
 
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c5bd273be8b3..045ce22a03c8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -6689,7 +6689,7 @@
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
friz %0,%1
@@ -6817,7 +6817,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6827,7 +6827,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6837,7 +6837,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6848,7 +6848,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
 UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_attr "type" "fp")])

[gcc(refs/users/meissner/heads/work198)] Add support for -mcpu=future

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b0d73a5c4183cd0629eaa3adadb4ada6793d4198

commit b0d73a5c4183cd0629eaa3adadb4ada6793d4198
Author: Michael Meissner 
Date:   Thu Mar 27 19:02:41 2025 -0400

Add support for -mcpu=future

This patch adds the support that can be used in developing GCC support for
future PowerPC processors.

2025-03-27  Michael Meissner  

* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for 
-mcpu=future.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
-mcpu=future, define _ARCH_FUTURE.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(POWERPC_MASKS): Add OPTION_MASK_FUTURE.
(future cpu): Define.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power10_cost): Update comment.
(get_arch_flags): Add support for future processor.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Add -mfuture.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Likewise.
* config/rs6000/rs6000.opt (-mfuture): New internal option.

Diff:
---
 gcc/config.gcc  |  4 ++--
 gcc/config/rs6000/aix71.h   |  1 +
 gcc/config/rs6000/aix72.h   |  1 +
 gcc/config/rs6000/aix73.h   |  1 +
 gcc/config/rs6000/driver-rs6000.cc  |  2 ++
 gcc/config/rs6000/rs6000-c.cc   |  2 ++
 gcc/config/rs6000/rs6000-cpus.def   |  5 +
 gcc/config/rs6000/rs6000-opts.h |  1 +
 gcc/config/rs6000/rs6000-tables.opt | 11 +++
 gcc/config/rs6000/rs6000.cc | 30 ++
 gcc/config/rs6000/rs6000.h  |  1 +
 gcc/config/rs6000/rs6000.md |  2 +-
 gcc/config/rs6000/rs6000.opt|  6 ++
 13 files changed, 52 insertions(+), 15 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f7f2002a45f3..7bb8a2925cd3 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -535,7 +535,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h 
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5682,7 +5682,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
-   "" | common | native \
+   "" | common | native | future \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 2b21dd7cd1e0..77651f5ea309 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 53c0bde5ad4a..652f60c7f494 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index c7639368a264..3c66ac1d9171 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=nati

[gcc(refs/users/meissner/heads/work198)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ce63e2da77e715ad519a76b682d68b2de3b43577

commit ce63e2da77e715ad519a76b682d68b2de3b43577
Author: Michael Meissner 
Date:   Thu Mar 27 19:08:34 2025 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

This patch also changes the target_clones support to use an architecture 
mask
instead of isa bits.

This patch also switches the handling of .machine to use architecture masks 
if
they exist (power4 through power11).  All of the other PowerPCs will 
continue to
use the existing code for setting the .machine option.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

The only difference in this patch compared to the first version posted on
November 6th is that I the correct attribution and copyright year (i.e. 
that I
created rs6000-arch.def in 2024).

Can I install this patch on the GCC 15 trunk?

2025-03-27  Michael Meissner  

gcc/

* config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu 
name.
* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument, 
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks 
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead 
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/default64.h |  11 ++
 gcc/config/rs6000/rs6000-arch.def |  49 +
 gcc/config/rs6000/rs6000.cc   | 222 +++---
 gcc/config/rs6000/rs6000.h|  24 +
 gcc/config/rs6000/rs6000.opt  |   8 ++
 5 files changed, 277 insertions(+), 37 deletions(-)

diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index 7f6001ded852..188f5c1d1378 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -21,6 +21,7 @@ along with GCC; see the file COPYING3.  If not see
 #define RS6000_CPU(NAME, CPU, FLAGS)
 #include "rs6000-cpus.def"
 #undef RS6000_CPU
+#undef TARGET_CPU_DEFAULT
 
 #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
 #undef TARGET_DEFAULT
@@ -28,10 +29,20 @@ along with GCC; see the file COPYING3.  If not see
| MASK_LITTLE_ENDIAN)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower8"
+#define TARGET_CPU_DEFAULT "power8"
+
 #else
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower4"
+
+#if (TARGET_DEFAULT & MASK_POWERPC64)
+#define TARGET_CPU_DEFAULT "powerpc64"
+
+#else
+#define TARGET_CPU_DEFAULT "powerpc"
+#endif
+
 #endif
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..c0dbc5834333
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@

[gcc(refs/users/meissner/heads/work198)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0a2a81e01ad3f860f70752ec011fe265ac4d03dd

commit 0a2a81e01ad3f860f70752ec011fe265ac4d03dd
Author: Michael Meissner 
Date:   Thu Mar 27 19:09:30 2025 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were 
removed.
The -mpower11 and -mfuture options were removed completely, since they were 
just
added in GCC 15. The other two options were marked as WarnRemoved, and the
various ISA bits were removed.

TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were 
re-defined
to use the architeture bits instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

Can I install this patch on the GCC 15 trunk?

2025-03-27  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10,
OPTION_MASK_POWER11, and OPTION_MASK_FUTURE.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which 
are
no longer in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use 
architecture
flags.
(TARGET_POWER5X): Likewise.
(TARGET_POWER6): Likewise.
(TARGET_POWER7): Likewise.
(TARGET_POWER8): Likewise.
(TARGET_POWER9): Likewise.
(TARGET_POWER10): New macro.
(TARGET_POWER11): Likewise.
(TARGET_FUTURE): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.
(-mfuture): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 29 -
 gcc/config/rs6000/rs6000-cpus.def | 10 +-
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 20 +++-
 gcc/config/rs6000/rs6000.h| 19 +--
 gcc/config/rs6000/rs6000.opt  | 17 ++---
 6 files changed, 46 insertions(+), 54 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 6757a2477ad1..6d6838735b33 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,25 +420,27 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((flags & OPTION_MASK_POWERPC64) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");

[gcc(refs/users/meissner/heads/work198)] Use vector pair load/store for memcpy with -mcpu=future

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:6dd96375a52b4c31118d5d9f5e7e228893599a46

commit 6dd96375a52b4c31118d5d9f5e7e228893599a46
Author: Michael Meissner 
Date:   Thu Mar 27 19:06:43 2025 -0400

Use vector pair load/store for memcpy with -mcpu=future

In the development for the power10 processor, GCC did not enable using the 
load
vector pair and store vector pair instructions when optimizing things like
memory copy.  This patch enables using those instructions if -mcpu=future is
used.

2025-03-27  Michael Meissner  

gcc/

* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable 
using
load vector pair and store vector pair instructions for memory copy
operations.
(POWERPC_MASKS): Make the bit for enabling using load vector pair 
and
store vector pair operations set and reset when the PowerPC 
processor is
changed.
* gcc/config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable
-mblock-ops-vector-pair from influcing .machine selection.

gcc/testsuite/

* gcc.target/powerpc/future-3.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def   |  4 +++-
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/testsuite/gcc.target/powerpc/future-3.c | 22 ++
 3 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 228d0b5e7b54..063591f5c094 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -84,7 +84,8 @@
  | OPTION_MASK_POWER11)
 
 #define FUTURE_MASKS_SERVER(POWER11_MASKS_SERVER   \
-| OPTION_MASK_FUTURE)
+| OPTION_MASK_FUTURE   \
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -114,6 +115,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4cea1775f110..011f67d290e9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5908,7 +5908,7 @@ rs6000_machine_from_flags (void)
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
-| OPTION_MASK_ALTIVEC);
+| OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR);
 
   if ((flags & (FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
 return "future";
diff --git a/gcc/testsuite/gcc.target/powerpc/future-3.c 
b/gcc/testsuite/gcc.target/powerpc/future-3.c
new file mode 100644
index ..afa8b96d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-3.c
@@ -0,0 +1,22 @@
+/* 32-bit doesn't generate vector pair instructions.  */
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test to see that memcpy will use load/store vector pair with
+   -mcpu=future.  */
+
+#ifndef SIZE
+#define SIZE 4
+#endif
+
+extern vector double to[SIZE], from[SIZE];
+
+void
+copy (void)
+{
+  __builtin_memcpy (to, from, sizeof (to));
+  return;
+}
+
+/* { dg-final { scan-assembler {\mlxvpx?\M}  } } */
+/* { dg-final { scan-assembler {\mstxvpx?\M} } } */

[gcc r14-11465] libgcc: Fix up unwind-dw2-btree.h [PR119151]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:7fc02fc0150e6b1ddbac68d42db809522124a48b

commit r14-11465-g7fc02fc0150e6b1ddbac68d42db809522124a48b
Author: Jakub Jelinek 
Date:   Mon Mar 10 10:34:00 2025 +0100

libgcc: Fix up unwind-dw2-btree.h [PR119151]

The following testcase shows a bug in unwind-dw2-btree.h.
In short, the header provides lock-free btree data structure (so no parent
link on nodes, both insertion and deletion are done in top-down walks
with some locking of just a few nodes at a time so that lookups can notice
concurrent modifications and retry, non-leaf (inner) nodes contain keys
which are initially the base address of the left-most leaf entry of the
following child (or all ones if there is none) minus one, insertion ensures
balancing of the tree to ensure [d/2, d] entries filled through aggressive
splitting if it sees a full tree while walking, deletion performs various
operations like merging neighbour trees, merging into parent or moving some
nodes from neighbour to the current one).
What differs from the textbook implementations is mostly that the leaf nodes
don't include just address as a key, but address range, address + size
(where we don't insert any ranges with zero size) and the lookups can be
performed for any address in the [address, address + size) range.  The keys
on inner nodes are still just address-1, so the child covers all nodes
where addr <= key unless it is covered already in children to the left.
The user (static executables or JIT) should always ensure there is no
overlap in between any of the ranges.

In the testcase a bunch of insertions are done, always followed by one
removal, followed by one insertion of a range slightly different from the
removed one.  E.g. in the first case [&code[0x50], &code[0x59]] range
is removed and then we insert [&code[0x4c], &code[0x53]] range instead.
This is valid, it doesn't overlap anything.  But the problem is that some
non-leaf (inner) one used the &code[0x4f] key (after the 11 insertions
completely correctly).  On removal, nothing adjusts the keys on the parent
nodes (it really can't in the top-down only walk, the keys could be many 
nodes
above it and unlike insertion, removal only knows the start address, doesn't
know the removed size and so will discover it only when reaching the leaf
node which contains it; plus even if it knew the address and size, it still
doesn't know what the second left-most leaf node will be (i.e. the one after
removal)).  And on insertion, if nodes aren't split at a level, nothing
adjusts the inner keys either.  If a range is inserted and is either fully
bellow key (keys are - 1, so having address + size - 1 being equal to key is
fine) or fully after key (i.e. address > key), it works just fine, but if
the key is in a middle of the range like in this case, &code[0x4f] is in the
middle of the [&code[0x4c], &code[0x53]] range, then insertion works fine
(we only use size on the leaf nodes), and lookup of the addresses below
the key work fine too (i.e. [&code[0x4c], &code[0x4f]] will succeed).
The problem is with lookups after the key (i.e. [&code[0x50, &code[0x53]]),
the lookup looks for them in different children of the btree and doesn't
find an entry and returns NULL.

As users need to ensure non-overlapping entries at any time, the following
patch fixes it by adjusting keys during insertion where we know not just
the address but also size; if we find during the top-down walk a key
which is in the middle of the range being inserted, we simply increase the
key to be equal to address + size - 1 of the range being inserted.
There can't be any existing leaf nodes overlapping the range in correct
programs and the btree rebalancing done on deletion ensures we don't have
any empty nodes which would also cause problems.

The patch adjusts the keys in two spots, once for the current node being
walked (the last hunk in the header, with large comment trying to explain
it) and once during inner node splitting in a parent node if we'd otherwise
try to add that key in the middle of the range being inserted into the
parent node (in that case it would be missed in the last hunk).
The testcase covers both of those spots, so succeeds with GCC 12 (which
didn't have btrees) and fails with vanilla GCC trunk and also fails if
either the
  if (fence < base + size - 1)
fence = iter->content.children[slot].separator = base + size - 1;
or
  if (left_fence >= target && left_fence < target + size - 1)
left_fence = target + size - 1;
hunk is removed (of course, only with the current node sizes, i.e. up to
15 children of inner nodes and up to 10 entries in leaf nodes).

2025-03-10  Jakub Jelinek  
Michael Leuchtenburg  

PR libgcc/

[gcc(refs/users/meissner/heads/work198-dmf)] Merge commit 'refs/users/meissner/heads/work198-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work19

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0f3fe7f7fc549672e844b00877cf8e7395b1

commit 0f3fe7f7fc549672e844b00877cf8e7395b1
Merge: ba7bc781e98c 8c070a4ee656
Author: Michael Meissner 
Date:   Thu Mar 27 19:19:24 2025 -0400

Merge commit 'refs/users/meissner/heads/work198-dmf' of 
git+ssh://gcc.gnu.org/git/gcc into me/work198-dmf

Diff:

[gcc r15-8517] gccrs: fix typechecking of Fn trait calls using ADT types

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:6a65fb23a9b6e541460ebbfe4044b1ae062c37c9

commit r15-8517-g6a65fb23a9b6e541460ebbfe4044b1ae062c37c9
Author: Philip Herron 
Date:   Tue Nov 5 17:41:44 2024 +

gccrs: fix typechecking of Fn trait calls using ADT types

Fixes RustGcc#2953

gcc/rust/ChangeLog:

* typecheck/rust-hir-type-check-item.cc (TypeCheckItem::visit): fix 
the ty_id

gcc/testsuite/ChangeLog:

* rust/compile/nr2/exclude: nr2 cant handle these
* rust/compile/issue-2953-1.rs: New test.
* rust/compile/issue-2953-2.rs: New test.

Signed-off-by: Philip Herron 

Diff:
---
 gcc/rust/typecheck/rust-hir-type-check-item.cc | 10 ---
 gcc/testsuite/rust/compile/issue-2953-1.rs | 27 +++
 gcc/testsuite/rust/compile/issue-2953-2.rs | 37 ++
 gcc/testsuite/rust/compile/nr2/exclude |  2 ++
 4 files changed, 72 insertions(+), 4 deletions(-)

diff --git a/gcc/rust/typecheck/rust-hir-type-check-item.cc 
b/gcc/rust/typecheck/rust-hir-type-check-item.cc
index 81e2f25f73d0..28368d4730a4 100644
--- a/gcc/rust/typecheck/rust-hir-type-check-item.cc
+++ b/gcc/rust/typecheck/rust-hir-type-check-item.cc
@@ -231,7 +231,8 @@ TypeCheckItem::visit (HIR::TupleStruct &struct_decl)
 = parse_repr_options (attrs, struct_decl.get_locus ());
 
   auto *type = new TyTy::ADTType (
-struct_decl.get_mappings ().get_hirid (), mappings.get_next_hir_id (),
+struct_decl.get_mappings ().get_hirid (),
+struct_decl.get_mappings ().get_hirid (),
 struct_decl.get_identifier ().as_string (), ident,
 TyTy::ADTType::ADTKind::TUPLE_STRUCT, std::move (variants),
 std::move (substitutions), repr,
@@ -312,7 +313,8 @@ TypeCheckItem::visit (HIR::StructStruct &struct_decl)
 = parse_repr_options (attrs, struct_decl.get_locus ());
 
   auto *type = new TyTy::ADTType (
-struct_decl.get_mappings ().get_hirid (), mappings.get_next_hir_id (),
+struct_decl.get_mappings ().get_hirid (),
+struct_decl.get_mappings ().get_hirid (),
 struct_decl.get_identifier ().as_string (), ident,
 TyTy::ADTType::ADTKind::STRUCT_STRUCT, std::move (variants),
 std::move (substitutions), repr,
@@ -369,7 +371,7 @@ TypeCheckItem::visit (HIR::Enum &enum_decl)
   // multi variant ADT
   auto *type
 = new TyTy::ADTType (enum_decl.get_mappings ().get_hirid (),
-mappings.get_next_hir_id (),
+enum_decl.get_mappings ().get_hirid (),
 enum_decl.get_identifier ().as_string (), ident,
 TyTy::ADTType::ADTKind::ENUM, std::move (variants),
 std::move (substitutions));
@@ -440,7 +442,7 @@ TypeCheckItem::visit (HIR::Union &union_decl)
 
   auto *type
 = new TyTy::ADTType (union_decl.get_mappings ().get_hirid (),
-mappings.get_next_hir_id (),
+union_decl.get_mappings ().get_hirid (),
 union_decl.get_identifier ().as_string (), ident,
 TyTy::ADTType::ADTKind::UNION, std::move (variants),
 std::move (substitutions));
diff --git a/gcc/testsuite/rust/compile/issue-2953-1.rs 
b/gcc/testsuite/rust/compile/issue-2953-1.rs
new file mode 100644
index ..d07059e440e0
--- /dev/null
+++ b/gcc/testsuite/rust/compile/issue-2953-1.rs
@@ -0,0 +1,27 @@
+#[lang = "sized"]
+pub trait Sized {
+// Empty.
+}
+
+#[lang = "fn_once"]
+pub trait FnOnce {
+/// The returned type after the call operator is used.
+#[lang = "fn_once_output"]
+type Output;
+
+/// Performs the call operation.
+extern "rust-call" fn call_once(self, args: Args) -> Self::Output;
+}
+
+pub enum Ordering {
+/// An ordering where a compared value is less than another.
+Less = -1,
+/// An ordering where a compared value is equal to another.
+Equal = 0,
+/// An ordering where a compared value is greater than another.
+Greater = 1,
+}
+
+pub fn f Ordering>(g: F) -> Ordering {
+g(1)
+}
diff --git a/gcc/testsuite/rust/compile/issue-2953-2.rs 
b/gcc/testsuite/rust/compile/issue-2953-2.rs
new file mode 100644
index ..59276246a1c2
--- /dev/null
+++ b/gcc/testsuite/rust/compile/issue-2953-2.rs
@@ -0,0 +1,37 @@
+#[lang = "sized"]
+pub trait Sized {
+// Empty.
+}
+
+#[lang = "fn_once"]
+pub trait FnOnce {
+/// The returned type after the call operator is used.
+#[lang = "fn_once_output"]
+type Output;
+
+/// Performs the call operation.
+extern "rust-call" fn call_once(self, args: Args) -> Self::Output;
+}
+
+pub enum Ordering {
+/// An ordering where a compared value is less than another.
+Less = -1,
+/// An ordering where a compared value is equal to another.
+Equal = 0,
+/// An ordering where a compared value is greater than another.
+Greater = 1,
+}
+
+pub fn max_by Ordering>(v1: T, v2: T, compare: F) -> T 
{
+

[gcc r15-8994] libstdc++-v3 testsuite: fix malformed dg-require-static-libstdcxx directives

[David Malcolm via Libstdc++-cvs]

https://gcc.gnu.org/g:1ee9caf2f84832f9eefef4953758e26ab505173c

commit r15-8994-g1ee9caf2f84832f9eefef4953758e26ab505173c
Author: David Malcolm 
Date:   Thu Mar 27 20:00:34 2025 -0400

libstdc++-v3 testsuite: fix malformed dg-require-static-libstdcxx directives

I believe these don't get detected by DejaGnu's regexp.

Found by dg-lint.

libstdc++-v3/ChangeLog:
* testsuite/17_intro/shared_with_static_deps.cc: Fix malformed
dg-require-static-libstdcxx directive.
* testsuite/17_intro/static.cc: Likewise.
* testsuite/18_support/type_info/110572.cc: Likewise.
* testsuite/20_util/to_chars/4.cc: Likewise.
* testsuite/std/time/tzdb_list/pr118811.cc: Likewise.

Signed-off-by: David Malcolm 

Diff:
---
 libstdc++-v3/testsuite/17_intro/shared_with_static_deps.cc | 2 +-
 libstdc++-v3/testsuite/17_intro/static.cc  | 2 +-
 libstdc++-v3/testsuite/18_support/type_info/110572.cc  | 2 +-
 libstdc++-v3/testsuite/20_util/to_chars/4.cc   | 2 +-
 libstdc++-v3/testsuite/std/time/tzdb_list/pr118811.cc  | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/libstdc++-v3/testsuite/17_intro/shared_with_static_deps.cc 
b/libstdc++-v3/testsuite/17_intro/shared_with_static_deps.cc
index 9491bbcd5741..a84c110ab52c 100644
--- a/libstdc++-v3/testsuite/17_intro/shared_with_static_deps.cc
+++ b/libstdc++-v3/testsuite/17_intro/shared_with_static_deps.cc
@@ -1,5 +1,5 @@
 // { dg-do link }
-// { dg-require-static-libstdcxx }
+// { dg-require-static-libstdcxx "" }
 // { dg-require-sharedlib "" }
 // { dg-require-effective-target fpic }
 // { dg-options "-shared -fPIC -static-libgcc -static-libstdc++" }
diff --git a/libstdc++-v3/testsuite/17_intro/static.cc 
b/libstdc++-v3/testsuite/17_intro/static.cc
index ab0cf279d994..26b34c819d52 100644
--- a/libstdc++-v3/testsuite/17_intro/static.cc
+++ b/libstdc++-v3/testsuite/17_intro/static.cc
@@ -1,5 +1,5 @@
 // { dg-do run { target c++11 } }
-// { dg-require-static-libstdcxx }
+// { dg-require-static-libstdcxx "" }
 // { dg-options "-static-libstdc++" }
 
 // Copyright (C) 2012-2025 Free Software Foundation, Inc.
diff --git a/libstdc++-v3/testsuite/18_support/type_info/110572.cc 
b/libstdc++-v3/testsuite/18_support/type_info/110572.cc
index f727653adfb1..5a05078510fe 100644
--- a/libstdc++-v3/testsuite/18_support/type_info/110572.cc
+++ b/libstdc++-v3/testsuite/18_support/type_info/110572.cc
@@ -1,6 +1,6 @@
 // { dg-options "-static-libstdc++" }
 // { dg-do link }
-// { dg-require-static-libstdcxx }
+// { dg-require-static-libstdcxx "" }
 // { dg-require-cpp-feature-test __cpp_rtti }
 
 #include 
diff --git a/libstdc++-v3/testsuite/20_util/to_chars/4.cc 
b/libstdc++-v3/testsuite/20_util/to_chars/4.cc
index 3d76d5691287..65abfaaff952 100644
--- a/libstdc++-v3/testsuite/20_util/to_chars/4.cc
+++ b/libstdc++-v3/testsuite/20_util/to_chars/4.cc
@@ -17,7 +17,7 @@
 
 // { dg-do link { target c++17 } }
 // { dg-require-effective-target ieee_floats }
-// { dg-require-static-libstdcxx }
+// { dg-require-static-libstdcxx "" }
 // { dg-additional-options "-static-libstdc++" }
 
 // Verify the Ryu symbol generic_to_chars doesn't inadvertently leak into
diff --git a/libstdc++-v3/testsuite/std/time/tzdb_list/pr118811.cc 
b/libstdc++-v3/testsuite/std/time/tzdb_list/pr118811.cc
index 3968be3f0eca..fe86602ecce9 100644
--- a/libstdc++-v3/testsuite/std/time/tzdb_list/pr118811.cc
+++ b/libstdc++-v3/testsuite/std/time/tzdb_list/pr118811.cc
@@ -1,7 +1,7 @@
 // { dg-do run { target c++20 } }
 // { dg-require-effective-target tzdb }
 // { dg-require-effective-target cxx11_abi }
-// { dg-require-static-libstdcxx }
+// { dg-require-static-libstdcxx "" }
 // { dg-additional-options "-static-libstdc++" }
 
 #include 

[gcc(refs/users/omachota/heads/rtl-ssa-dce)] rtl-ssa: dce fix bad marked insn map passing

[Ondrej Machota via Gcc-cvs]

https://gcc.gnu.org/g:aecd918163914a09df0f619a9f3163dcadfaf425

commit aecd918163914a09df0f619a9f3163dcadfaf425
Author: Ondřej Machota 
Date:   Sun Mar 9 20:59:45 2025 +0100

rtl-ssa: dce fix bad marked insn map passing

Diff:
---
 gcc/dce.cc | 146 -
 1 file changed, 116 insertions(+), 30 deletions(-)

diff --git a/gcc/dce.cc b/gcc/dce.cc
index f51f27dbd143..9a217a795b76 100644
--- a/gcc/dce.cc
+++ b/gcc/dce.cc
@@ -1316,6 +1316,7 @@ bool sets_global_register(const_rtx rtx) {
 }
 
 // We should mark stack registers
+// use HARD_FRAME_POINTER_REGNUM, REGNO_PTR_FRAME_P
 bool sets_global_register(rtx_insn* insn) {
   rtx set = single_set(insn);
   if (!set)
@@ -1370,21 +1371,55 @@ bool is_unary_mem_modification(rtx_code code) {
   }
 }
 
-bool is_rtx_insn_prelive(const_rtx rtx) {
-  if (rtx == nullptr) {
-return false;
+bool is_rtx_insn_prelive(rtx_insn *insn) {
+  gcc_assert(insn != nullptr);
+
+  // TODO : handle calls correctly
+  if (CALL_P (insn)
+  /* We cannot delete pure or const sibling calls because it is
+hard to see the result.  */
+  && (!SIBLING_CALL_P (insn))
+  /* We can delete dead const or pure calls as long as they do not
+ infinite loop.  */
+  && (RTL_CONST_OR_PURE_CALL_P (insn) && !RTL_LOOPING_CONST_OR_PURE_CALL_P 
(insn))
+  /* Don't delete calls that may throw if we cannot do so.  */
+  && can_delete_call (insn))
+return true;
+// return !find_call_stack_args (as_a  (insn), false, 
fast, arg_stores);
+
+  // Jumps, notes, barriers should not be deleted
+// According to the docs, rtl ssa does not contain noteS and barrierS 
+  if (!NONJUMP_INSN_P (insn))
+  {
+std::cerr << "found jump instruction\n";
+debug(insn);
+return true;
   }
 
-  auto code = GET_CODE(rtx);
-  if (is_control_flow(code))
+  // Only rtx_insn should be handled here
+  auto code = GET_CODE(insn);
+  gcc_assert(code == INSN);
+
+  /* Don't delete insns that may throw if we cannot do so.  */
+  if (!(cfun->can_delete_dead_exceptions && can_alter_cfg) && !insn_nothrow_p 
(insn))
 return true;
 
+  /* TODO : What about call argumets? Accoring to the docs, for function 
prologue the RTX_FRAME_RELATED_P
+ should return true.
+  */  
+  /* Callee-save restores are needed.  */
+  if (RTX_FRAME_RELATED_P (insn) && crtl->shrink_wrapped_separate && 
find_reg_note (insn, REG_CFA_RESTORE, NULL))
+return true;
+
+  // if (is_control_flow(code))
+  //   return true;
+
   // Mark set of a global register
-  if (sets_global_register(rtx)) // check rtx_class with GET_RTX_CLASS if 
RTX_ISNS and convert if needed
+  if (sets_global_register(insn)) // check rtx_class with GET_RTX_CLASS if 
RTX_ISNS and convert if needed
 return true;
 
-  // Call is inside side_effects_p - how to mark parameter registers?
-  if (volatile_refs_p(rtx) || can_throw_internal(rtx) || BARRIER_P(rtx) || 
code == PREFETCH)
+  rtx body = PATTERN(insn);
+  if (side_effects_p(body) || can_throw_internal(body))
 return true;
 
   if (is_unary_mem_modification(code))
@@ -1394,21 +1429,34 @@ bool is_rtx_insn_prelive(const_rtx rtx) {
   // Parallel is handled by volatile_refs_p
 
   switch (code) {
-
-  }
-
-  const char *const fmt = GET_RTX_FORMAT (code);
-  for (size_t i = 0; i < GET_RTX_LENGTH(code); ++i) {
-if (fmt[i] == 'e' && is_rtx_insn_prelive(XEXP(rtx, i))) {
+case MEM:
+case ASM_INPUT:
+case ASM_OPERANDS:
   return true;
-} else if (fmt[i] == 'E') {
-  for (size_t j = 0; j < XVECLEN(rtx, i); ++j) {
-if (is_rtx_insn_prelive(XVECEXP(rtx, i, j)))
-  return true;
-  }
-}
+
+case PARALLEL:
+  for (int i = XVECLEN (body, 0) - 1; i >= 0; i--)
+ if (!deletable_insn_p_1 (XVECEXP (body, 0, i)))
+   return true;
+  return false;
+  break;
+
+default:
+  break;
   }
 
+  // const char *const fmt = GET_RTX_FORMAT (code);
+  // for (size_t i = 0; i < GET_RTX_LENGTH(code); ++i) {
+  //   if (fmt[i] == 'e' && is_rtx_insn_prelive(XEXP(rtx, i))) {
+  // return true;
+  //   } else if (fmt[i] == 'E') {
+  // for (size_t j = 0; j < XVECLEN(rtx, i); ++j) {
+  //   if (is_rtx_insn_prelive(XVECEXP(rtx, i, j)))
+  // return true;
+  // }
+  //   }
+  // }
+
   return false;
 }
 
@@ -1443,7 +1491,7 @@ bool is_prelive(insn_info *insn)
   if (!INSN_P(rtl)) // This might be useless
 return false;
 
-  rtx pat = PATTERN(rtl); // if we use this instead of rtl, then rtl notes 
wont be checked
+  return is_rtx_insn_prelive(rtl);
   
   // TODO : join if statements
   // We need to describe all possible prelive instructions, a list of all the 
instructions is inside `rtl.def`
@@ -1461,7 +1509,7 @@ bool is_prelive(insn_info *insn)
   std::cerr << "Prelive: " << GET_RTX_NAME(code) << '\n';
   // debug(insn);
   debug(rtl);
-  if (volatile_refs_p(rtl) || can_throw_internal(rtl) || BARRIER_P(rtl) || 
code == PREFETCH)

[gcc r14-11463] value-range: Fix up irange::union_bitmask [PR118953]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:375cc5fb9192c433c0f516c9e99786b92d2e9f95

commit r14-11463-g375cc5fb9192c433c0f516c9e99786b92d2e9f95
Author: Jakub Jelinek 
Date:   Wed Mar 5 14:30:35 2025 +0100

value-range: Fix up irange::union_bitmask [PR118953]

The following testcase is miscompiled during evrp.
Before vrp, we have (from ccp):
  # RANGE [irange] long long unsigned int [0, +INF] MASK 0xc000 
VALUE 0x2d
  _3 = _2 + 18446744073708503085;
...
  # RANGE [irange] long long unsigned int [0, +INF] MASK 0xc000 
VALUE 0x59
  _6 = (long long unsigned int) _5;
  # RANGE [irange] int [-INF, +INF] MASK 0xc000 VALUE 0x34
  _7 = k_11 + -1048524;
  switch (_7)  [33.33%], case 8:  [33.33%], case 24:  
[33.33%], case 32:  [33.33%]>
...
  # RANGE [irange] long long unsigned int [0, +INF] MASK 0xc07d 
VALUE 0x0
  # i_20 = PHI <_3(4), 0(3), _6(2)>
and evrp is now trying to figure out range for i_20 in range_of_phi.

All the ranges and MASK/VALUE pairs above are correct for the testcase,
k_11 and _2 based on it is a result of multiplication by a constant with low
14 bits cleared and then some numbers are added to it.

There is an obvious missed optimization for which I've filed PR119039,
simplify_switch_using_ranges could see that all the labels but default
are unreachable because the controlling expression has
MASK 0xc000 VALUE 0x34 and none of 8, 24 and 32 satisfy that.

Anyway, during range_of_phi for i_20, we process the PHI arguments
in order.  For the _3(4) case, we figure out that it is reachable
through the case 24: case 32: labels only of the switch and that
0x34 - 0x2d is 7, so derive
[irange] long long unsigned int [17, 17][25, 25] MASK 0xc000 
VALUE 0x2d
(the MASK/VALUE just got inherited from the _3 earlier range).
Now (not suprisingly because those labels aren't actually reachable),
that range is inconsistent, 0x2d is 45, so there is conflict between the
values and the irange_bitmask.
value-range.{h,cc} code differentiates between actually stored
irange_bitmask, which is that MASK 0xc000 VALUE 0x2d, and
semantic bitmask, which is what get_bitmask returns.  That is
  // The mask inherent in the range is calculated on-demand.  For
  // example, [0,255] does not have known bits set by default.  This
  // saves us considerable time, because setting it at creation incurs
  // a large penalty for irange::set.  At the time of writing there
  // was a 5% slowdown in VRP if we kept the mask precisely up to date
  // at all times.  Instead, we default to -1 and set it when
  // explicitly requested.  However, this function will always return
  // the correct mask.
  //
  // This also means that the mask may have a finer granularity than
  // the range and thus contradict it.  Think of the mask as an
  // enhancement to the range.  For example:
  //
  // [3, 1000] MASK 0xfffe VALUE 0x0
  //
  // 3 is in the range endpoints, but is excluded per the known 0 bits
  // in the mask.
  //
  // See also the note in irange_bitmask::intersect.
  irange_bitmask bm
= get_bitmask_from_range (type (), lower_bound (), upper_bound ());
  if (!m_bitmask.unknown_p ())
bm.intersect (m_bitmask);
Now, get_bitmask_from_range here is MASK 0x1f VALUE 0x0 and it intersects
that with that MASK 0xc000 VALUE 0x2d.
Which triggers the ugly special case in irange_bitmask::intersect:
  // If we have two known bits that are incompatible, the resulting
  // bit is undefined.  It is unclear whether we should set the entire
  // range to UNDEFINED, or just a subset of it.  For now, set the
  // entire bitmask to unknown (VARYING).
  if (wi::bit_and (~(m_mask | src.m_mask),
   m_value ^ src.m_value) != 0)
{
  unsigned prec = m_mask.get_precision ();
  m_mask = wi::minus_one (prec);
  m_value = wi::zero (prec);
}
so the semantic bitmask is actually MASK 0x VALUE 0x0.

Next, range_of_phi attempts to union it with the 0(3) PHI argument,
and during irange::union_ first adds the [0,0] to the subranges, so
[irange] long long unsigned int [0, 0][17, 17][25, 25] MASK 
0xc000 VALUE 0x2d
and then goes on to irange::union_bitmask which does
  if (m_bitmask == r.m_bitmask)
return false;
  irange_bitmask bm = get_bitmask ();
  irange_bitmask save = bm;
  bm.union_ (r.get_bitmask ());
  if (save == bm)
return false;
  m_bitmask = bm;
  if (save == get_bitmask ())
return false;
m_bitmask MASK 0xc000 VALUE 0x2d isn't the same as
r.m_bitmask MASK 0x0 VALUE 0x0, so we compute the semantic bitmask
(but note, not from the original range befor

[gcc] Created branch 'meissner/heads/work198-test' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-test' was created in namespace 'refs/users' 
pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work198-sha' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-sha' was created in namespace 'refs/users' 
pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work198)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0af95d73c34cd5fde59192b034197fff211158d7

commit 0af95d73c34cd5fde59192b034197fff211158d7
Author: Michael Meissner 
Date:   Thu Mar 27 19:15:27 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 396 +
 1 file changed, 396 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 7e6ce5818833..2e8efb607107 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,401 @@
+ Branch work198, patch #21 
+
+Use architecture flags for defining _ARCH_PWR macros.
+
+For the newer architectures, this patch changes GCC to define the _ARCH_PWR
+macros using the new architecture flags instead of relying on isa options like
+-mpower10.
+
+The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were removed.
+The -mpower11 and -mfuture options were removed completely, since they were 
just
+added in GCC 15. The other two options were marked as WarnRemoved, and the
+various ISA bits were removed.
+
+TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were 
re-defined
+to use the architeture bits instead of the ISA bits.
+
+There are other internal isa bits that aren't removed with this patch because
+the built-in function support uses those bits.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+Can I install this patch on the GCC 15 trunk?
+
+2025-03-27  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
+   use architecture flags instead of ISA flags for setting most of the
+   _ARCH_PWR* macros.
+   (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
+   OPTION_MASK_POWER8.
+   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
+   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
+   (FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE.
+   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10,
+   OPTION_MASK_POWER11, and OPTION_MASK_FUTURE.
+   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
+   declaration.
+   (rs6000_target_modify_macros_ptr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
+   (rs6000_option_override_internal): Use architecture flags instead of ISA
+   flags.
+   (rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which are
+   no longer in the ISA flags.
+   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
+   flags.
+   * config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use architecture
+   flags.
+   (TARGET_POWER5X): Likewise.
+   (TARGET_POWER6): Likewise.
+   (TARGET_POWER7): Likewise.
+   (TARGET_POWER8): Likewise.
+   (TARGET_POWER9): Likewise.
+   (TARGET_POWER10): New macro.
+   (TARGET_POWER11): Likewise.
+   (TARGET_FUTURE): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits.
+   (-mpower10): Likewise.
+   (-mpower11): Likewise.
+   (-mfuture): Likewise.
+
+ Branch work198, patch #20 
+
+Add rs6000 architecture masks.
+
+This patch begins the journey to move architecture bits that are not user ISA
+options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  The
+intention is to remove switches that are currently isa options, but the user
+should not be using this particular option. For example, we want users to use
+-mcpu=power10 and not just -mpower10.
+
+This patch also changes the target_clones support to use an architecture mask
+instead of isa bits.
+
+This patch also switches the handling of .machine to use architecture masks if
+they exist (power4 through power11).  All of the other PowerPCs will continue 
to
+use the existing code for setting the .machine option.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+In addition, I constructed a test case that used every archiecture define (like
+_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
+this test for all supported combinations of -mcpu, big/little endian, and 32/64
+bit support.  Every single instance generated exactly the same code with the
+patches installed compared to the compiler before installing the patches.
+
+The only difference in this patch compared to the first version posted on
+November 6th is that I the correct attribution and copyright year (i.e. that I
+created rs6000-arch.def in 2024).
+
+Can I install this patch on the GCC 15 trunk?
+
+2025-03-27  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name.
+   * config/rs6000/rs6000-arch.def: New file.
+   * conf

[gcc(refs/users/meissner/heads/work198)] Add -mcpu=future tests.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:29575fc8b3277a4d0fcd324101af77e9f013ed01

commit 29575fc8b3277a4d0fcd324101af77e9f013ed01
Author: Michael Meissner 
Date:   Thu Mar 27 19:05:21 2025 -0400

Add -mcpu=future tests.

This patch adds simple tests for -mcpu=future.

2025-03-27  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/future-1.c: New test.
* gcc.target/powerpc/future-2.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/future-1.c | 13 +
 gcc/testsuite/gcc.target/powerpc/future-2.c | 24 
 2 files changed, 37 insertions(+)

diff --git a/gcc/testsuite/gcc.target/powerpc/future-1.c 
b/gcc/testsuite/gcc.target/powerpc/future-1.c
new file mode 100644
index ..f1b940d7bebf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=future and if it defines
+   _ARCH_PWR11.  */
+
+#ifndef _ARCH_FUTURE
+#error "-mcpu=future is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/future-2.c 
b/gcc/testsuite/gcc.target/powerpc/future-2.c
new file mode 100644
index ..5552cefa3c2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the future target via a target attribute.  */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
+
+__attribute__((__target__("cpu=future")))
+void foo_future (void)
+{
+}

[gcc(refs/users/meissner/heads/work198-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ba7bc781e98ce650928cabfeee167bb04afd734a

commit ba7bc781e98ce650928cabfeee167bb04afd734a
Author: Michael Meissner 
Date:   Thu Mar 27 15:32:40 2025 -0400

Add ChangeLog.dmf and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..70118273928d
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,5 @@
+ Branch work198-dmf, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..f55420ff9cd6 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-dmf branch

[gcc(refs/users/meissner/heads/work198-bugs)] Merge commit 'refs/users/meissner/heads/work198-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8b0fcfa3d856de9e14eafcd043b71d0be24cc56b

commit 8b0fcfa3d856de9e14eafcd043b71d0be24cc56b
Merge: b7c8f7d0f653 c73646078a19
Author: Michael Meissner 
Date:   Thu Mar 27 19:17:35 2025 -0400

Merge commit 'refs/users/meissner/heads/work198-bugs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work198-bugs

Diff:

[gcc(refs/users/meissner/heads/work198-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b7c8f7d0f6530bdfc4c9da6bd55f7c44ccdc68a9

commit b7c8f7d0f6530bdfc4c9da6bd55f7c44ccdc68a9
Author: Michael Meissner 
Date:   Thu Mar 27 15:34:29 2025 -0400

Add ChangeLog.bugs and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..6279dfc648b8
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,5 @@
+ Branch work198-bugs, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..ca8757f6538c 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-bugs branch

[gcc/meissner/heads/work198-dmf] (14 commits) Merge commit 'refs/users/meissner/heads/work198-dmf' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-dmf' was updated to point to:

 0f3fe7f7fc54... Merge commit 'refs/users/meissner/heads/work198-dmf' of git

It previously pointed to:

 8c070a4ee656... Add ChangeLog.dmf and update REVISION.

Diff:

Summary of changes (added commits):
---

  0f3fe7f... Merge commit 'refs/users/meissner/heads/work198-dmf' of git
  ba7bc78... Add ChangeLog.dmf and update REVISION.
  0af95d7... Update ChangeLog.* (*)
  0a2a81e... Use architecture flags for defining _ARCH_PWR macros. (*)
  ce63e2d... Add rs6000 architecture masks. (*)
  6dd9637... Use vector pair load/store for memcpy with -mcpu=future (*)
  29575fc... Add -mcpu=future tests. (*)
  f8aee6f... Add -mcpu=future tuning support. (*)
  b0d73a5... Add support for -mcpu=future (*)
  e4017d6... Change TARGET_MODULO to TARGET_POWER9. (*)
  c8f4c79... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  2f23761... Change TARGET_CMPB to TARGET_POWER6. (*)
  47c8b15... Change TARGET_FPRND to TARGET_POWER5X. (*)
  0ff1070... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work198-dmf' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work198)] Add -mcpu=future tuning support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:f8aee6f1cd10126b090fec93e8bfe318103cb152

commit f8aee6f1cd10126b090fec93e8bfe318103cb152
Author: Michael Meissner 
Date:   Thu Mar 27 19:03:36 2025 -0400

Add -mcpu=future tuning support.

This patch makes -mtune=future use the same tuning decision as 
-mtune=power11.

2025-03-27  Michael Meissner  

gcc/

* config/rs6000/power10.md (all reservations): Add future as an
alterntive to power10 and power11.

Diff:
---
 gcc/config/rs6000/power10.md | 145 ++-
 1 file changed, 73 insertions(+), 72 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index fd31b16b3314..bdd7e58145ba 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,5 @@
-;; Scheduling description for the IBM Power10 and Power11 processors.
+;; Scheduling description for the IBM Power10, Power11, and
+;; potential future processors.
 ;; Copyright (C) 2020-2025 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +98,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +111,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +125,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +133,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +149,27 @@
   (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +179,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +192,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle lat

[gcc/meissner/heads/work198-libs] (14 commits) Merge commit 'refs/users/meissner/heads/work198-libs' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-libs' was updated to point to:

 2a7e23132b60... Merge commit 'refs/users/meissner/heads/work198-libs' of gi

It previously pointed to:

 3e3f396925a6... Add ChangeLog.libs and update REVISION.

Diff:

Summary of changes (added commits):
---

  2a7e231... Merge commit 'refs/users/meissner/heads/work198-libs' of gi
  f0e015c... Add ChangeLog.libs and update REVISION.
  0af95d7... Update ChangeLog.* (*)
  0a2a81e... Use architecture flags for defining _ARCH_PWR macros. (*)
  ce63e2d... Add rs6000 architecture masks. (*)
  6dd9637... Use vector pair load/store for memcpy with -mcpu=future (*)
  29575fc... Add -mcpu=future tests. (*)
  f8aee6f... Add -mcpu=future tuning support. (*)
  b0d73a5... Add support for -mcpu=future (*)
  e4017d6... Change TARGET_MODULO to TARGET_POWER9. (*)
  c8f4c79... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  2f23761... Change TARGET_CMPB to TARGET_POWER6. (*)
  47c8b15... Change TARGET_FPRND to TARGET_POWER5X. (*)
  0ff1070... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work198-libs' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work198-libs)] Add ChangeLog.libs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:f0e015c663cdf59075bcf9100e325a85bd6c15b3

commit f0e015c663cdf59075bcf9100e325a85bd6c15b3
Author: Michael Meissner 
Date:   Thu Mar 27 15:35:28 2025 -0400

Add ChangeLog.libs and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.libs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.libs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs
new file mode 100644
index ..e7c5609f55ea
--- /dev/null
+++ b/gcc/ChangeLog.libs
@@ -0,0 +1,5 @@
+ Branch work198-libs, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..3db41217765f 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-libs branch

[gcc/meissner/heads/work198-math] (14 commits) Merge commit 'refs/users/meissner/heads/work198-math' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-math' was updated to point to:

 c7affdeb5e90... Merge commit 'refs/users/meissner/heads/work198-math' of gi

It previously pointed to:

 16e9f45d080d... Add ChangeLog.math and update REVISION.

Diff:

Summary of changes (added commits):
---

  c7affde... Merge commit 'refs/users/meissner/heads/work198-math' of gi
  5e2a015... Add ChangeLog.math and update REVISION.
  0af95d7... Update ChangeLog.* (*)
  0a2a81e... Use architecture flags for defining _ARCH_PWR macros. (*)
  ce63e2d... Add rs6000 architecture masks. (*)
  6dd9637... Use vector pair load/store for memcpy with -mcpu=future (*)
  29575fc... Add -mcpu=future tests. (*)
  f8aee6f... Add -mcpu=future tuning support. (*)
  b0d73a5... Add support for -mcpu=future (*)
  e4017d6... Change TARGET_MODULO to TARGET_POWER9. (*)
  c8f4c79... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  2f23761... Change TARGET_CMPB to TARGET_POWER6. (*)
  47c8b15... Change TARGET_FPRND to TARGET_POWER5X. (*)
  0ff1070... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work198-math' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work198-math)] Add ChangeLog.math and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5e2a015d3c612928fa72b8f67514a86f79671e32

commit 5e2a015d3c612928fa72b8f67514a86f79671e32
Author: Michael Meissner 
Date:   Thu Mar 27 15:38:15 2025 -0400

Add ChangeLog.math and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.math: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.math | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.math b/gcc/ChangeLog.math
new file mode 100644
index ..bd91728ad74b
--- /dev/null
+++ b/gcc/ChangeLog.math
@@ -0,0 +1,5 @@
+ Branch work198-math, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..f1d57d80f2d9 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-math branch

[gcc(refs/users/meissner/heads/work198-math)] Merge commit 'refs/users/meissner/heads/work198-math' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c7affdeb5e90ba9e82f2572c6293df917f19164a

commit c7affdeb5e90ba9e82f2572c6293df917f19164a
Merge: 5e2a015d3c61 16e9f45d080d
Author: Michael Meissner 
Date:   Thu Mar 27 19:24:11 2025 -0400

Merge commit 'refs/users/meissner/heads/work198-math' of 
git+ssh://gcc.gnu.org/git/gcc into me/work198-math

Diff:

[gcc(refs/users/meissner/heads/work198-libs)] Merge commit 'refs/users/meissner/heads/work198-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2a7e23132b60bb3f73019710ee1f13c958c85544

commit 2a7e23132b60bb3f73019710ee1f13c958c85544
Merge: f0e015c663cd 3e3f396925a6
Author: Michael Meissner 
Date:   Thu Mar 27 19:21:43 2025 -0400

Merge commit 'refs/users/meissner/heads/work198-libs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work198-libs

Diff:

[gcc(refs/users/meissner/heads/work198-paddis)] Merge commit 'refs/users/meissner/heads/work198-paddis' of git+ssh://gcc.gnu.org/git/gcc into me/wor

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8618001631996599f64a8554e642bf33483f42e9

commit 8618001631996599f64a8554e642bf33483f42e9
Merge: 44560ac6d849 11918698ecff
Author: Michael Meissner 
Date:   Thu Mar 27 19:26:23 2025 -0400

Merge commit 'refs/users/meissner/heads/work198-paddis' of 
git+ssh://gcc.gnu.org/git/gcc into me/work198-paddis

Diff:

[gcc/meissner/heads/work198-sha] (14 commits) Merge commit 'refs/users/meissner/heads/work198-sha' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-sha' was updated to point to:

 04bfd2df9528... Merge commit 'refs/users/meissner/heads/work198-sha' of git

It previously pointed to:

 ada654291745... Add ChangeLog.sha and update REVISION.

Diff:

Summary of changes (added commits):
---

  04bfd2d... Merge commit 'refs/users/meissner/heads/work198-sha' of git
  ab464b6... Add ChangeLog.sha and update REVISION.
  0af95d7... Update ChangeLog.* (*)
  0a2a81e... Use architecture flags for defining _ARCH_PWR macros. (*)
  ce63e2d... Add rs6000 architecture masks. (*)
  6dd9637... Use vector pair load/store for memcpy with -mcpu=future (*)
  29575fc... Add -mcpu=future tests. (*)
  f8aee6f... Add -mcpu=future tuning support. (*)
  b0d73a5... Add support for -mcpu=future (*)
  e4017d6... Change TARGET_MODULO to TARGET_POWER9. (*)
  c8f4c79... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  2f23761... Change TARGET_CMPB to TARGET_POWER6. (*)
  47c8b15... Change TARGET_FPRND to TARGET_POWER5X. (*)
  0ff1070... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work198-sha' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work198-sha)] Merge commit 'refs/users/meissner/heads/work198-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work19

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:04bfd2df9528284f2068a025a6eee2ab72a33fcc

commit 04bfd2df9528284f2068a025a6eee2ab72a33fcc
Merge: ab464b6db89b ada654291745
Author: Michael Meissner 
Date:   Thu Mar 27 19:29:28 2025 -0400

Merge commit 'refs/users/meissner/heads/work198-sha' of 
git+ssh://gcc.gnu.org/git/gcc into me/work198-sha

Diff:

[gcc/meissner/heads/work198-bugs] (14 commits) Merge commit 'refs/users/meissner/heads/work198-bugs' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-bugs' was updated to point to:

 8b0fcfa3d856... Merge commit 'refs/users/meissner/heads/work198-bugs' of gi

It previously pointed to:

 c73646078a19... Add ChangeLog.bugs and update REVISION.

Diff:

Summary of changes (added commits):
---

  8b0fcfa... Merge commit 'refs/users/meissner/heads/work198-bugs' of gi
  b7c8f7d... Add ChangeLog.bugs and update REVISION.
  0af95d7... Update ChangeLog.* (*)
  0a2a81e... Use architecture flags for defining _ARCH_PWR macros. (*)
  ce63e2d... Add rs6000 architecture masks. (*)
  6dd9637... Use vector pair load/store for memcpy with -mcpu=future (*)
  29575fc... Add -mcpu=future tests. (*)
  f8aee6f... Add -mcpu=future tuning support. (*)
  b0d73a5... Add support for -mcpu=future (*)
  e4017d6... Change TARGET_MODULO to TARGET_POWER9. (*)
  c8f4c79... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  2f23761... Change TARGET_CMPB to TARGET_POWER6. (*)
  47c8b15... Change TARGET_FPRND to TARGET_POWER5X. (*)
  0ff1070... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work198-bugs' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc/meissner/heads/work198-paddis] (14 commits) Merge commit 'refs/users/meissner/heads/work198-paddis' of

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-paddis' was updated to point to:

 861800163199... Merge commit 'refs/users/meissner/heads/work198-paddis' of 

It previously pointed to:

 11918698ecff... Add ChangeLog.paddis and update REVISION.

Diff:

Summary of changes (added commits):
---

  8618001... Merge commit 'refs/users/meissner/heads/work198-paddis' of 
  44560ac... Add ChangeLog.paddis and update REVISION.
  0af95d7... Update ChangeLog.* (*)
  0a2a81e... Use architecture flags for defining _ARCH_PWR macros. (*)
  ce63e2d... Add rs6000 architecture masks. (*)
  6dd9637... Use vector pair load/store for memcpy with -mcpu=future (*)
  29575fc... Add -mcpu=future tests. (*)
  f8aee6f... Add -mcpu=future tuning support. (*)
  b0d73a5... Add support for -mcpu=future (*)
  e4017d6... Change TARGET_MODULO to TARGET_POWER9. (*)
  c8f4c79... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  2f23761... Change TARGET_CMPB to TARGET_POWER6. (*)
  47c8b15... Change TARGET_FPRND to TARGET_POWER5X. (*)
  0ff1070... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work198-paddis' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc/meissner/heads/work198-test] (14 commits) Merge commit 'refs/users/meissner/heads/work198-test' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-test' was updated to point to:

 07332b7e8d89... Merge commit 'refs/users/meissner/heads/work198-test' of gi

It previously pointed to:

 63b32bc92036... Add ChangeLog.test and update REVISION.

Diff:

Summary of changes (added commits):
---

  07332b7... Merge commit 'refs/users/meissner/heads/work198-test' of gi
  0bb8533... Add ChangeLog.test and update REVISION.
  0af95d7... Update ChangeLog.* (*)
  0a2a81e... Use architecture flags for defining _ARCH_PWR macros. (*)
  ce63e2d... Add rs6000 architecture masks. (*)
  6dd9637... Use vector pair load/store for memcpy with -mcpu=future (*)
  29575fc... Add -mcpu=future tests. (*)
  f8aee6f... Add -mcpu=future tuning support. (*)
  b0d73a5... Add support for -mcpu=future (*)
  e4017d6... Change TARGET_MODULO to TARGET_POWER9. (*)
  c8f4c79... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  2f23761... Change TARGET_CMPB to TARGET_POWER6. (*)
  47c8b15... Change TARGET_FPRND to TARGET_POWER5X. (*)
  0ff1070... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work198-test' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work198-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0bb8533eb14a63756321a3d5da5d04d293cdd5c2

commit 0bb8533eb14a63756321a3d5da5d04d293cdd5c2
Author: Michael Meissner 
Date:   Thu Mar 27 15:37:14 2025 -0400

Add ChangeLog.test and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..91b1269028a0
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,5 @@
+ Branch work198-test, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..3520a958372f 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-test branch

[gcc(refs/users/meissner/heads/work198-test)] Merge commit 'refs/users/meissner/heads/work198-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:07332b7e8d8913d91b911e861d7eb2ee5b8405b8

commit 07332b7e8d8913d91b911e861d7eb2ee5b8405b8
Merge: 0bb8533eb14a 63b32bc92036
Author: Michael Meissner 
Date:   Thu Mar 27 19:34:42 2025 -0400

Merge commit 'refs/users/meissner/heads/work198-test' of 
git+ssh://gcc.gnu.org/git/gcc into me/work198-test

Diff:

[gcc(refs/users/meissner/heads/work198-sha)] Add ChangeLog.sha and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ab464b6db89b9f1d3fdc0a0f90d229e4aa431391

commit ab464b6db89b9f1d3fdc0a0f90d229e4aa431391
Author: Michael Meissner 
Date:   Thu Mar 27 15:36:20 2025 -0400

Add ChangeLog.sha and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.sha: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.sha | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha
new file mode 100644
index ..365713781db6
--- /dev/null
+++ b/gcc/ChangeLog.sha
@@ -0,0 +1,5 @@
+ Branch work198-sha, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..9b3ce5ecb35f 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-sha branch

[gcc(refs/users/meissner/heads/work198-vpair)] Merge commit 'refs/users/meissner/heads/work198-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0cc8f15abe2e9685f44ad49b4b760d9f0b9d87f1

commit 0cc8f15abe2e9685f44ad49b4b760d9f0b9d87f1
Merge: e651b587bab9 7342a36448a6
Author: Michael Meissner 
Date:   Thu Mar 27 19:38:04 2025 -0400

Merge commit 'refs/users/meissner/heads/work198-vpair' of 
git+ssh://gcc.gnu.org/git/gcc into me/work198-vpair

Diff:

[gcc(refs/users/meissner/heads/work198-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e651b587bab9822d26db91a3238723d6ae609ccf

commit e651b587bab9822d26db91a3238723d6ae609ccf
Author: Michael Meissner 
Date:   Thu Mar 27 15:33:34 2025 -0400

Add ChangeLog.vpair and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 5 +
 gcc/REVISION| 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..da61dc2ec8af
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,5 @@
+ Branch work198-vpair, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..a14a3e5e6e3f 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-vpair branch

[gcc/meissner/heads/work198-vpair] (14 commits) Merge commit 'refs/users/meissner/heads/work198-vpair' of g

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-vpair' was updated to point to:

 0cc8f15abe2e... Merge commit 'refs/users/meissner/heads/work198-vpair' of g

It previously pointed to:

 7342a36448a6... Add ChangeLog.vpair and update REVISION.

Diff:

Summary of changes (added commits):
---

  0cc8f15... Merge commit 'refs/users/meissner/heads/work198-vpair' of g
  e651b58... Add ChangeLog.vpair and update REVISION.
  0af95d7... Update ChangeLog.* (*)
  0a2a81e... Use architecture flags for defining _ARCH_PWR macros. (*)
  ce63e2d... Add rs6000 architecture masks. (*)
  6dd9637... Use vector pair load/store for memcpy with -mcpu=future (*)
  29575fc... Add -mcpu=future tests. (*)
  f8aee6f... Add -mcpu=future tuning support. (*)
  b0d73a5... Add support for -mcpu=future (*)
  e4017d6... Change TARGET_MODULO to TARGET_POWER9. (*)
  c8f4c79... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  2f23761... Change TARGET_CMPB to TARGET_POWER6. (*)
  47c8b15... Change TARGET_FPRND to TARGET_POWER5X. (*)
  0ff1070... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work198-vpair' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc r14-11458] reassoc: Fix up optimize_range_tests_to_bit_test [PR118915]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:0a3a15cd1c00746f1d4154ea1567f0fd33a2d961

commit r14-11458-g0a3a15cd1c00746f1d4154ea1567f0fd33a2d961
Author: Jakub Jelinek 
Date:   Mon Feb 24 12:19:16 2025 +0100

reassoc: Fix up optimize_range_tests_to_bit_test [PR118915]

The following testcase is miscompiled due to a bug in
optimize_range_tests_to_bit_test.  It is trying to optimize
check for a in [-34,-34] or [-26,-26] or [-6,-6] or [-4,inf] ranges.
Another reassoc optimization folds the the test for the first
two ranges into (a + 34U) & ~8U in [0U,0U] range, and extract_bit_test_mask
actually has code to virtually undo it and treat that again as test
for a being -34 or -26.  The problem is that 
optimize_range_tests_to_bit_test
remembers in the type variable TREE_TYPE (ranges[i].exp); from the first
range.  If extract_bit_test_mask doesn't do that virtual undoing of the
BIT_AND_EXPR handling, that is just fine, the returned exp is ranges[i].exp.
But if the first range is BIT_AND_EXPR, the type could be different, the
BIT_AND_EXPR form has the optional cast to corresponding unsigned type
in order to avoid introducing UB.  Now, type was used to fill in the
max value if ranges[j].high was missing in subsequently tested range,
and so in this particular testcase the [-4,inf] range which was
signed int and so [-4,INT_MAX] was treated as [-4,UINT_MAX] instead.
And we were subtracting values of 2 different types and trying to make
sense out of that.

The following patch fixes this by using the type of the low bound
(which is always non-NULL) for the max value of the high bound instead.

2025-02-24  Jakub Jelinek  

PR tree-optimization/118915
* tree-ssa-reassoc.cc (optimize_range_tests_to_bit_test): For
highj == NULL_TREE use TYPE_MAX_VALUE (TREE_TYPE (lowj)) rather
than TYPE_MAX_VALUE (type).

* gcc.c-torture/execute/pr118915.c: New test.

(cherry picked from commit 5806279610783805286ebcd0af3b455602a3a8f9)

Diff:
---
 gcc/testsuite/gcc.c-torture/execute/pr118915.c | 22 ++
 gcc/tree-ssa-reassoc.cc|  2 +-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.c-torture/execute/pr118915.c 
b/gcc/testsuite/gcc.c-torture/execute/pr118915.c
new file mode 100644
index ..2e0cb71c728d
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr118915.c
@@ -0,0 +1,22 @@
+/* PR tree-optimization/118915 */
+
+int a;
+
+int
+foo (int c, int d, int e, int f)
+{
+  if (!d || !e)
+return -22;
+  if (c > 16)
+return -22;
+  if (!f)
+return -22;
+  return 2;
+}
+
+int
+main ()
+{
+  if (foo (a + 21, a + 6, a + 34, a + 26) != -22)
+__builtin_abort ();
+}
diff --git a/gcc/tree-ssa-reassoc.cc b/gcc/tree-ssa-reassoc.cc
index 377ab6f4b974..2ff5e49a3930 100644
--- a/gcc/tree-ssa-reassoc.cc
+++ b/gcc/tree-ssa-reassoc.cc
@@ -3362,7 +3362,7 @@ optimize_range_tests_to_bit_test (enum tree_code opcode, 
int first, int length,
continue;
  highj = ranges[j].high;
  if (highj == NULL_TREE)
-   highj = TYPE_MAX_VALUE (type);
+   highj = TYPE_MAX_VALUE (TREE_TYPE (lowj));
  wide_int mask2;
  exp2 = extract_bit_test_mask (ranges[j].exp, prec, lowi, lowj,
highj, &mask2, NULL);

[gcc r14-11459] openmp: Mark OpenMP atomic write expression as read [PR119000]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:f14094177725948569e54026b57d5f6dd371e80a

commit r14-11459-gf14094177725948569e54026b57d5f6dd371e80a
Author: Jakub Jelinek 
Date:   Tue Feb 25 09:33:21 2025 +0100

openmp: Mark OpenMP atomic write expression as read [PR119000]

The following testcase was emitting false positive warning that
the rhs of #pragma omp atomic write was stored but not read,
when the atomic actually does read it.  The following patch
fixes that by calling default_function_array_read_conversion
on it, so that it is marked as read as well as converted from
lvalue to rvalue.
Furthermore, the code had
if (code == NOP_EXPR) ... else ... if (code == NOP_EXPR) ...
with none of ... parts changing code, so I've merged the two ifs.

2025-02-25  Jakub Jelinek  

PR c/119000
* c-parser.cc (c_parser_omp_atomic): For omp write call
default_function_array_read_conversion on the rhs expression.
Merge the two adjacent if (code == NOP_EXPR) blocks.

* c-c++-common/gomp/pr119000.c: New test.

(cherry picked from commit cdffc76393488a73671b70481cf8a4b7c289029d)

Diff:
---
 gcc/c/c-parser.cc  | 22 ++
 gcc/testsuite/c-c++-common/gomp/pr119000.c | 16 
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/gcc/c/c-parser.cc b/gcc/c/c-parser.cc
index 194143f3bdff..686ab423d033 100644
--- a/gcc/c/c-parser.cc
+++ b/gcc/c/c-parser.cc
@@ -21192,9 +21192,16 @@ c_parser_omp_atomic (location_t loc, c_parser *parser, 
bool openacc)
goto saw_error;
   if (code == NOP_EXPR)
{
- lhs = c_parser_expression (parser).value;
- lhs = c_fully_fold (lhs, false, NULL);
- if (lhs == error_mark_node)
+ eloc = c_parser_peek_token (parser)->location;
+ expr = c_parser_expression (parser);
+ expr = default_function_array_read_conversion (eloc, expr);
+ /* atomic write is represented by OMP_ATOMIC with NOP_EXPR
+opcode.  */
+ code = OMP_ATOMIC;
+ lhs = v;
+ v = NULL_TREE;
+ rhs = c_fully_fold (expr.value, false, NULL);
+ if (rhs == error_mark_node)
goto saw_error;
}
   else
@@ -21207,15 +21214,6 @@ c_parser_omp_atomic (location_t loc, c_parser *parser, 
bool openacc)
  if (non_lvalue_p)
lhs = non_lvalue (lhs);
}
-  if (code == NOP_EXPR)
-   {
- /* atomic write is represented by OMP_ATOMIC with NOP_EXPR
-opcode.  */
- code = OMP_ATOMIC;
- rhs = lhs;
- lhs = v;
- v = NULL_TREE;
-   }
   goto done;
 case OMP_ATOMIC_CAPTURE_NEW:
   if (c_parser_next_token_is (parser, CPP_OPEN_BRACE))
diff --git a/gcc/testsuite/c-c++-common/gomp/pr119000.c 
b/gcc/testsuite/c-c++-common/gomp/pr119000.c
new file mode 100644
index ..e5b7ab0c2b8c
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/gomp/pr119000.c
@@ -0,0 +1,16 @@
+/* PR c/119000 */
+/* { dg-do compile } */
+/* { dg-options "-fopenmp -Wunused-but-set-variable" } */
+
+int
+foo (void)
+{
+  int a = 1, b, c = 1, v;  /* { dg-warning "variable 'b' set but not used" 
} */
+  #pragma omp atomic write
+  v = a;
+  #pragma omp atomic read
+  b = v;
+  #pragma omp atomic update
+  v += c;
+  return v;
+}

[gcc r14-11461] c++: Fix cxx_eval_store_expression {REAL, IMAG}PART_EXPR handling [PR119045]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:ab908fdb911d6a337cd02b6018bc74b3a2f99acf

commit r14-11461-gab908fdb911d6a337cd02b6018bc74b3a2f99acf
Author: Jakub Jelinek 
Date:   Fri Feb 28 15:22:47 2025 +0100

c++: Fix cxx_eval_store_expression {REAL,IMAG}PART_EXPR handling [PR119045]

I've added the asserts that probe == target because {REAL,IMAG}PART_EXPR
always implies a scalar type and so applying ARRAY_REF/COMPONENT_REF
etc. on it further doesn't make sense and the later code relies on it
to be the last one in refs array.  But as the following testcase shows,
we can fail those assertions in case there is a reference or pointer
to the __real__ or __imag__ part, in that case we just evaluate the
constant expression and so probe won't be the same as target.
That case doesn't push anything into the refs array though.

The following patch changes those asserts to verify that refs is still
empty, which fixes it.

2025-02-28  Jakub Jelinek  

PR c++/119045
* constexpr.cc (cxx_eval_store_expression) :
Assert that refs->is_empty () rather than probe == target.
(cxx_eval_store_expression) : Likewise.

* g++.dg/cpp1y/constexpr-complex2.C: New test.

(cherry picked from commit 7eb8ec1856f71b039d1c2235b1c941934fa28e22)

Diff:
---
 gcc/cp/constexpr.cc |  4 ++--
 gcc/testsuite/g++.dg/cpp1y/constexpr-complex2.C | 18 ++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc
index a5c6227b8dd6..f3b61f5f391a 100644
--- a/gcc/cp/constexpr.cc
+++ b/gcc/cp/constexpr.cc
@@ -6313,7 +6313,7 @@ cxx_eval_store_expression (const constexpr_ctx *ctx, tree 
t,
  break;
 
case REALPART_EXPR:
- gcc_assert (probe == target);
+ gcc_assert (refs->is_empty ());
  vec_safe_push (refs, NULL_TREE);
  vec_safe_push (refs, probe);
  vec_safe_push (refs, TREE_TYPE (probe));
@@ -6321,7 +6321,7 @@ cxx_eval_store_expression (const constexpr_ctx *ctx, tree 
t,
  break;
 
case IMAGPART_EXPR:
- gcc_assert (probe == target);
+ gcc_assert (refs->is_empty ());
  vec_safe_push (refs, NULL_TREE);
  vec_safe_push (refs, probe);
  vec_safe_push (refs, TREE_TYPE (probe));
diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-complex2.C 
b/gcc/testsuite/g++.dg/cpp1y/constexpr-complex2.C
new file mode 100644
index ..7baafd83a322
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-complex2.C
@@ -0,0 +1,18 @@
+// PR c++/119045
+// { dg-do compile { target c++14 } }
+
+constexpr float
+foo ()
+{
+  __complex__ float f {1, 2};
+  float s = __real__ f + __imag__ f;
+  float &r = __real__ f;
+  float &i = __imag__ f;
+  r = 42;
+  s += __real__ f;
+  i = 3;
+  s += __imag__ f;
+  return s;
+}
+
+static_assert (foo () == 48.0f, "");

[gcc r14-11460] c: stddef.h C23 fixes [PR114870]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:a266e7354bdae713f73c9f356bb15a387fd4d1b4

commit r14-11460-ga266e7354bdae713f73c9f356bb15a387fd4d1b4
Author: Jakub Jelinek 
Date:   Wed Feb 26 19:29:12 2025 +0100

c: stddef.h C23 fixes [PR114870]

The stddef.h header for C23 defines __STDC_VERSION_STDDEF_H__ and
unreachable macros multiple times in some cases.
The header doesn't have normal multiple inclusion guard, because it supports
for glibc inclusion with __need_{size_t,wchar_t,ptrdiff_t,wint_t,NULL}.
While the definition of __STDC_VERSION_STDDEF_H__ and unreachable is done
solely in the #ifdef _STDDEF_H part, so they are defined only if stddef.h
is included without those __need_* macros defined.  But actually once
stddef.h is included without the __need_* macros, _STDDEF_H is then defined
and while further stddef.h includes without __need_* macros don't do
anything:
 #if (!defined(_STDDEF_H) && !defined(_STDDEF_H_) && 
!defined(_ANSI_STDDEF_H) \
  && !defined(__STDDEF_H__)) \
 || defined(__need_wchar_t) || defined(__need_size_t) \
 || defined(__need_ptrdiff_t) || defined(__need_NULL) \
 || defined(__need_wint_t)
if one includes whole stddef.h first and then stddef.h with some of the
__need_* macros defined, the #ifdef _STDDEF_H part is used again.
It isn't that big deal for most cases, as it uses extra guarding macros
like:
 #ifndef _GCC_MAX_ALIGN_T
 #define _GCC_MAX_ALIGN_T
 ...
 #endif
etc., but for __STDC_VERSION_STDDEF_H__/unreachable nothing like that is
used.

So, either we do what the following patch does and just don't define
__STDC_VERSION_STDDEF_H__/unreachable second time, or use #ifndef
unreachable separately for the #define unreachable() case, or use
new _GCC_STDC_VERSION_STDDEF_H macro to guard this (or two, one for
__STDC_VERSION_STDDEF_H__ and one for unreachable), or rework the initial
condition to be just
 #if !defined(_STDDEF_H) && !defined(_STDDEF_H_) && 
!defined(_ANSI_STDDEF_H) \
 && !defined(__STDDEF_H__)
- I really don't understand why the header should do anything at all after
it has been included once without __need_* macros.  But changing how this
behaves after 35 years might be risky for various OS/libc combinations.

2025-02-26  Jakub Jelinek  

PR c/114870
* ginclude/stddef.h (__STDC_VERSION_STDDEF_H__, unreachable): Don't
redefine multiple times if stddef.h is first included without 
__need_*
defines and later with them.  Move nullptr_t and unreachable and
__STDC_VERSION_STDDEF_H__ definitions into the same
defined (__STDC_VERSION__) && __STDC_VERSION__ > 201710L #if block.

* gcc.dg/c23-stddef-2.c: New test.

(cherry picked from commit 8d22474af76a386eed488b3c66124134f0e41363)

Diff:
---
 gcc/ginclude/stddef.h   |  8 +++-
 gcc/testsuite/gcc.dg/c23-stddef-2.c | 17 +
 2 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/gcc/ginclude/stddef.h b/gcc/ginclude/stddef.h
index 349213108ce9..88730867eebe 100644
--- a/gcc/ginclude/stddef.h
+++ b/gcc/ginclude/stddef.h
@@ -444,18 +444,16 @@ typedef struct {
 #endif
 #endif /* C++11.  */
 
-#if (defined (__STDC_VERSION__) && __STDC_VERSION__ > 201710L)
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ > 201710L
 #ifndef _GCC_NULLPTR_T
 #define _GCC_NULLPTR_T
   typedef __typeof__(nullptr) nullptr_t;
-/* ??? This doesn't define __STDC_VERSION_STDDEF_H__ yet.  */
 #endif
-#endif /* C23.  */
-
-#if defined __STDC_VERSION__ && __STDC_VERSION__ > 201710L
+#ifndef __STDC_VERSION_STDDEF_H__
 #define unreachable() (__builtin_unreachable ())
 #define __STDC_VERSION_STDDEF_H__  202311L
 #endif
+#endif /* C23.  */
 
 #endif /* _STDDEF_H was defined this time */
 
diff --git a/gcc/testsuite/gcc.dg/c23-stddef-2.c 
b/gcc/testsuite/gcc.dg/c23-stddef-2.c
new file mode 100644
index ..53509b6a6246
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/c23-stddef-2.c
@@ -0,0 +1,17 @@
+/* Test __STDC_VERSION_STDDEF_H__ in C23.  */
+/* { dg-do preprocess } */
+/* { dg-options "-std=c23 -pedantic-errors -Wsystem-headers" } */
+
+#include 
+/* Simulate what glibc  does without actually including it.  */
+#define __need_size_t
+#define __need_NULL
+#include 
+
+#ifndef __STDC_VERSION_STDDEF_H__
+#error "__STDC_VERSION_STDDEF_H__ not defined"
+#endif
+
+#if __STDC_VERSION_STDDEF_H__ != 202311L
+#error "bad value of __STDC_VERSION_STDDEF_H__"
+#endif

[gcc r14-11466] tree: Improve skip_simple_arithmetic [PR119183]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:c6b38a75fc811f87b1beae1d95b86f613352e3da

commit r14-11466-gc6b38a75fc811f87b1beae1d95b86f613352e3da
Author: Jakub Jelinek 
Date:   Tue Mar 11 11:01:55 2025 +0100

tree: Improve skip_simple_arithmetic [PR119183]

The following testcase takes very long time to compile, because
skip_simple_arithmetic decides to first call tree_invariant_p on
the second argument (and indirectly recurse there).  I think before
canonicalization of operands for commutative binary expressions
(and for non-commutative ones always) it is pretty common that the
first operand is a constant, something which tree_invariant_p handles
immediately, so the following patch special cases that; I've added
there a tree_invariant_p call too after the checks, while it is not
really needed currently, tree_invariant_p has the same checks, I wanted
to be prepared in case tree_invariant_p changes.  But if you think
I should avoid it, I can drop it too.

This is just a partial fix, I think one can certainly construct a testcase
which will still have horrible compile time complexity (but I've tried and
haven't managed to do so), so perhaps we should just limit the recursion
depth through skip_simple_arithmetic/tree_invariant_p with some defaulted
argument.

2025-03-11  Jakub Jelinek  

PR c/119183
* tree.cc (skip_simple_arithmetic): If first operand of binary
expr is TREE_CONSTANT or TREE_READONLY with no side-effects, call
tree_invariant_p on that operand first instead of on the second.

* gcc.dg/pr119183.c: New test.

(cherry picked from commit 20e5aa9cc1519f871cce25dbfdc149d9d60da779)

Diff:
---
 gcc/testsuite/gcc.dg/pr119183.c | 12 
 gcc/tree.cc | 14 +-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/pr119183.c b/gcc/testsuite/gcc.dg/pr119183.c
new file mode 100644
index ..a98d77907731
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr119183.c
@@ -0,0 +1,12 @@
+/* PR c/119183 */
+/* { dg-do compile } */
+
+int foo (void);
+#define A(x) (1.0f * (1.0f * (1.0f * (1.0f * (1.0f * (1.0f * (1.0f * (1.0f * 
(x)
+
+float
+bar (float r)
+{
+  r += A (A (A (A (A (A (A (A (foo ();
+  return r;
+}
diff --git a/gcc/tree.cc b/gcc/tree.cc
index 6564b002dc1a..d716d7ccfe31 100644
--- a/gcc/tree.cc
+++ b/gcc/tree.cc
@@ -4006,7 +4006,19 @@ skip_simple_arithmetic (tree expr)
expr = TREE_OPERAND (expr, 0);
   else if (BINARY_CLASS_P (expr))
{
- if (tree_invariant_p (TREE_OPERAND (expr, 1)))
+ /* Before commutative binary operands are canonicalized,
+it is quite common to have constants in the first operand.
+Check for that common case first so that we don't walk
+large expressions with tree_invariant_p unnecessarily.
+This can still have terrible compile time complexity,
+we should limit the depth of the tree_invariant_p and
+skip_simple_arithmetic recursion.  */
+ if ((TREE_CONSTANT (TREE_OPERAND (expr, 0))
+  || (TREE_READONLY (TREE_OPERAND (expr, 0))
+  && !TREE_SIDE_EFFECTS (TREE_OPERAND (expr, 0
+ && tree_invariant_p (TREE_OPERAND (expr, 0)))
+   expr = TREE_OPERAND (expr, 1);
+ else if (tree_invariant_p (TREE_OPERAND (expr, 1)))
expr = TREE_OPERAND (expr, 0);
  else if (tree_invariant_p (TREE_OPERAND (expr, 0)))
expr = TREE_OPERAND (expr, 1);

[gcc r14-11467] middle-end/119204 - ICE with strcspn folding

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:01f20dec2d9ef22b2744a059c75b962d14de4303

commit r14-11467-g01f20dec2d9ef22b2744a059c75b962d14de4303
Author: Richard Biener 
Date:   Tue Mar 11 08:40:44 2025 +0100

middle-end/119204 - ICE with strcspn folding

The following makes sure to convert the folded expression to the
original expression type.

PR middle-end/119204
* builtins.cc (fold_builtin_strcspn): Preserve the original
expression type.

* gcc.dg/pr119204.c: New testcase.

(cherry picked from commit 68932eeb38f66fbc0c3cf4b77ff7dde8a408f2e4)

Diff:
---
 gcc/builtins.cc |  5 +++--
 gcc/testsuite/gcc.dg/pr119204.c | 13 +
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/gcc/builtins.cc b/gcc/builtins.cc
index 4856f81797a4..b683c130186e 100644
--- a/gcc/builtins.cc
+++ b/gcc/builtins.cc
@@ -11216,7 +11216,7 @@ fold_builtin_strcspn (location_t loc, tree expr, tree 
s1, tree s2)
 {
   /* Evaluate and ignore argument s2 in case it has
 side-effects.  */
-  return omit_one_operand_loc (loc, size_type_node,
+  return omit_one_operand_loc (loc, TREE_TYPE (expr),
   size_zero_node, s2);
 }
 
@@ -11231,7 +11231,8 @@ fold_builtin_strcspn (location_t loc, tree expr, tree 
s1, tree s2)
   if (!fn)
return NULL_TREE;
 
-  return build_call_expr_loc (loc, fn, 1, s1);
+  return fold_convert_loc (loc, TREE_TYPE (expr),
+  build_call_expr_loc (loc, fn, 1, s1));
 }
   return NULL_TREE;
 }
diff --git a/gcc/testsuite/gcc.dg/pr119204.c b/gcc/testsuite/gcc.dg/pr119204.c
new file mode 100644
index ..ecbd8dd1c22a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr119204.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-w" } */
+
+extern void abort(void);
+extern long long strcspn(const char *, const char *);
+
+void main_test(void) {
+  const char *const s1 = "hello world";
+  char dst[64], *d2;
+
+  if (strcspn(++d2 + 5, "") != 5 || d2 != dst + 1)
+abort();
+}

[gcc r14-11470] Fix up some further cases of missing or extraneous spaces in diagnostics

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:f9dab50e6e5e0ecd1f004432749b43b3caab059c

commit r14-11470-gf9dab50e6e5e0ecd1f004432749b43b3caab059c
Author: Jakub Jelinek 
Date:   Sat Mar 22 08:39:38 2025 +0100

Fix up some further cases of missing or extraneous spaces in diagnostics

Given the recent PR119406 I've tried to grep for concatenated string
literals without space at the end of one line and at the start of next line,
unless it was obviously intentional.
Furthermore, I've then looked through gcc.pot looking for 2 adjacent spaces
and looking back if that wasn't the case of "something "
" with spaces at both sides".

Here is the result from that.

I think just the c.opt change needs an explanation, the "" in the
description is simply eaten up somewhere during the option processing and
gcc -v --help before this patch was displaying
  -Wdeprecated-literal-operator Warn about deprecated space between  and 
suffix in a user-defined literal operator.

2025-03-22  Jakub Jelinek  

gcc/
* gimplify.cc (warn_switch_unreachable_and_auto_init_r): Add missing
space in the middle of diagnostics.
* tree-vect-stmts.cc (vectorizable_load): Add missing space in the
middle of debug dump message.
gcc/fortran/
* resolve.cc (resolve_procedure_expression): Remove extraneous space
from the middle of diagnostics.

(cherry picked from commit 20360e4b6b5a63bc65d1855a7ecf22eb7148a452)

Diff:
---
 gcc/fortran/resolve.cc | 2 +-
 gcc/gimplify.cc| 2 +-
 gcc/tree-vect-stmts.cc | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc
index 7df879bf1585..6a47550b613e 100644
--- a/gcc/fortran/resolve.cc
+++ b/gcc/fortran/resolve.cc
@@ -1968,7 +1968,7 @@ resolve_procedure_expression (gfc_expr* expr)
   if (is_illegal_recursion (sym, gfc_current_ns))
 {
   if (sym->attr.use_assoc && expr->symtree->name[0] == '@')
-   gfc_warning (0, "Non-RECURSIVE procedure %qs from module %qs is "
+   gfc_warning (0, "Non-RECURSIVE procedure %qs from module %qs is"
 " possibly calling itself recursively in procedure %qs. "
 " Declare it RECURSIVE or use %<-frecursive%>",
 sym->name, sym->module, gfc_current_ns->proc_name->name);
diff --git a/gcc/gimplify.cc b/gcc/gimplify.cc
index 401b663591f6..32ecb0cffe5d 100644
--- a/gcc/gimplify.cc
+++ b/gcc/gimplify.cc
@@ -2359,7 +2359,7 @@ warn_switch_unreachable_and_auto_init_r 
(gimple_stmt_iterator *gsi_p,
  const char *var_name_str = TREE_STRING_POINTER (var_name);
 
  warning_at (gimple_location (stmt), OPT_Wtrivial_auto_var_init,
- "%qs cannot be initialized with"
+ "%qs cannot be initialized with "
  "%<-ftrivial-auto-var_init%>",
  var_name_str);
  break;
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index a78f1d0e2cc6..5b910b30196c 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -11916,7 +11916,7 @@ vectorizable_load (vec_info *vinfo,
 
  if (dump_enabled_p ())
dump_printf_loc (MSG_NOTE, vect_location,
-"vect_model_load_cost:"
+"vect_model_load_cost: "
 "strided group_size = %d .\n",
 group_size);
}

[gcc r14-11462] openmp: Fix up simd clone mask argument creation on x86 [PR115871]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:fc39a29f75cb181dcefaebf4489303847ae4fe9d

commit r14-11462-gfc39a29f75cb181dcefaebf4489303847ae4fe9d
Author: Jakub Jelinek 
Date:   Sat Mar 1 09:15:57 2025 +0100

openmp: Fix up simd clone mask argument creation on x86 [PR115871]

The following testcase ICEs since r14-5057.
The Intel vector ABI says that in the ZMM case the masks is passed
in unsigned int or unsigned long long arguments and how many bits in
them and how many of those arguments are is determined by the characteristic
data type of the function.  In the testcase simdlen is 32 and characteristic
data type is double, so return as well as first argument is passed in 4
V8DFmode arguments and the mask is supposed to be passed in 4 unsigned int
arguments (8 bits in each).
Before the r14-5057 change there was
  sc->args[i].orig_type = parm_type;
...
case SIMD_CLONE_ARG_TYPE_LINEAR_VAL_CONSTANT_STEP:
case SIMD_CLONE_ARG_TYPE_LINEAR_VAL_VARIABLE_STEP:
case SIMD_CLONE_ARG_TYPE_VECTOR:
  if (INTEGRAL_TYPE_P (parm_type) || POINTER_TYPE_P (parm_type))
veclen = sc->vecsize_int;
  else
veclen = sc->vecsize_float;
  if (known_eq (veclen, 0U))
veclen = sc->simdlen;
  else
veclen
  = exact_div (veclen,
   GET_MODE_BITSIZE (SCALAR_TYPE_MODE (parm_type)));
for the argument handling and
  if (sc->inbranch)
{
  tree base_type = simd_clone_compute_base_data_type (sc->origin, sc);
...
  if (INTEGRAL_TYPE_P (base_type) || POINTER_TYPE_P (base_type))
veclen = sc->vecsize_int;
  else
veclen = sc->vecsize_float;
  if (known_eq (veclen, 0U))
veclen = sc->simdlen;
  else
veclen = exact_div (veclen,
GET_MODE_BITSIZE (SCALAR_TYPE_MODE 
(base_type)));
for the mask handling.  r14-5057 moved this argument creation later and
unified that:
case SIMD_CLONE_ARG_TYPE_MASK:
case SIMD_CLONE_ARG_TYPE_LINEAR_VAL_CONSTANT_STEP:
case SIMD_CLONE_ARG_TYPE_LINEAR_VAL_VARIABLE_STEP:
case SIMD_CLONE_ARG_TYPE_VECTOR:
  if (sc->args[i].arg_type == SIMD_CLONE_ARG_TYPE_MASK
  && sc->mask_mode != VOIDmode)
elem_type = boolean_type_node;
  else
elem_type = TREE_TYPE (sc->args[i].vector_type);
  if (INTEGRAL_TYPE_P (elem_type) || POINTER_TYPE_P (elem_type))
veclen = sc->vecsize_int;
  else
veclen = sc->vecsize_float;
  if (known_eq (veclen, 0U))
veclen = sc->simdlen;
  else
veclen
  = exact_div (veclen,
   GET_MODE_BITSIZE (SCALAR_TYPE_MODE (elem_type)));
This is correct for the argument cases (so linear or vector) (though
POINTER_TYPE_P will never appear as TREE_TYPE of a vector), but the
boolean_type_node in there is completely bogus, when using AVX512 integer
masks as I wrote above we need the characteristic data type, not bool,
and bool is strange in that it has bitsize of 8 (or 32 on darwin), while
the masks are 1 bit per lane anyway.

Fixed thusly.

2025-03-01  Jakub Jelinek  

PR middle-end/115871
* omp-simd-clone.cc (simd_clone_adjust): For 
SIMD_CLONE_ARG_TYPE_MASK
and sc->mask_mode not VOIDmode, set elem_type to the characteristic
type rather than boolean_type_node.

* gcc.dg/gomp/simd-clones-8.c: New test.

(cherry picked from commit 6589eb4efe39545ec7f7e641e1d302c89b260350)

Diff:
---
 gcc/omp-simd-clone.cc |  2 +-
 gcc/testsuite/gcc.dg/gomp/simd-clones-8.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/gcc/omp-simd-clone.cc b/gcc/omp-simd-clone.cc
index 864586207ee8..eb46ff97be26 100644
--- a/gcc/omp-simd-clone.cc
+++ b/gcc/omp-simd-clone.cc
@@ -1423,7 +1423,7 @@ simd_clone_adjust (struct cgraph_node *node)
case SIMD_CLONE_ARG_TYPE_VECTOR:
  if (sc->args[i].arg_type == SIMD_CLONE_ARG_TYPE_MASK
  && sc->mask_mode != VOIDmode)
-   elem_type = boolean_type_node;
+   elem_type = simd_clone_compute_base_data_type (sc->origin, sc);
  else
elem_type = TREE_TYPE (sc->args[i].vector_type);
  if (INTEGRAL_TYPE_P (elem_type) || POINTER_TYPE_P (elem_type))
diff --git a/gcc/testsuite/gcc.dg/gomp/simd-clones-8.c 
b/gcc/testsuite/gcc.dg/gomp/simd-clones-8.c
new file mode 100644
index ..a6ddb04388c7
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/gomp/simd-clones-8.c
@@ -0,0 +1,10 @@
+/* PR middle-end/115871 */
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-optio

[gcc r14-11471] i386: Require in peephole2 that memory is offsettable [PR119450]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:4b364531057c973795dc15d75132fb6c2ea6219b

commit r14-11471-g4b364531057c973795dc15d75132fb6c2ea6219b
Author: Jakub Jelinek 
Date:   Wed Mar 26 08:47:20 2025 +0100

i386: Require in peephole2 that memory is offsettable [PR119450]

The following testcase ICEs because a peephole2 attempts to offset
memory which is not offsettable (in particular address is a ZERO_EXTEND
in this case).

Because peephole2s don't support constraints, I've added a check for this
in the peephole2's condition.

2025-03-26  Jakub Jelinek  

PR target/119450
* config/i386/i386.md (narrow test peephole2): Test for
offsettable_memref_p in condition.

* gcc.target/i386/pr119450.c: New test.

(cherry picked from commit 84f0b648aeb053b3bd8e1cb6fe282f4da4143708)

Diff:
---
 gcc/config/i386/i386.md  |  4 +++-
 gcc/testsuite/gcc.target/i386/pr119450.c | 15 +++
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a7508d47d9b1..447a319f7a1c 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -11630,7 +11630,9 @@
  (and:SWI248 (match_operand:SWI248 0 "memory_operand")
  (match_operand 1 "const_int_operand"))
  (const_int 0)))]
-  "!TARGET_PARTIAL_MEMORY_READ_STALL && !MEM_VOLATILE_P (operands[0])"
+  "!TARGET_PARTIAL_MEMORY_READ_STALL
+   && !MEM_VOLATILE_P (operands[0])
+   && offsettable_memref_p (operands[0])"
   [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_dup 2) (const_int 0)))]
 {
diff --git a/gcc/testsuite/gcc.target/i386/pr119450.c 
b/gcc/testsuite/gcc.target/i386/pr119450.c
new file mode 100644
index ..fa4bbdaf88cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr119450.c
@@ -0,0 +1,15 @@
+/* PR target/119450 */
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+long *a;
+int b;
+
+void
+foo (void)
+{
+  unsigned d = b >> 30;
+  a = (long *) (__UINTPTR_TYPE__) d;
+  if (*a & 1 << 30)
+*a = 0;
+}

[gcc r14-11468] builtins: Fix up strspn/strcspn folding [PR119219]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:4164c2542952d82e7cdb06d28c8707ac131b5644

commit r14-11468-g4164c2542952d82e7cdb06d28c8707ac131b5644
Author: Jakub Jelinek 
Date:   Wed Mar 12 08:27:17 2025 +0100

builtins: Fix up strspn/strcspn folding [PR119219]

The PR119204 r15-7955 fix caused some regressions.
The problem is that the fold_builtin* APIs document that expr is
either a CALL_EXPR of the call or NULL, so using TREE_TYPE (expr)
can crash e.g. during constexpr evaluation etc.

As can be seen in the surrounding patch, for the neighbouring builtins
(both modf and strpbrk) fold_builtin_2 passes down type, which is the
result type, TREE_TYPE (TREE_TYPE (fndecl)) and those builtins use it
to build the return value, while strspn was always building size_type_node
and strcspn had this change from that to TREE_TYPE (expr).
The patch passes type to these two and uses it there as well.

The patch keeps passing expr because it is used in the
check_nul_terminated_array calls done for both strspn and strcspn,
those calls clearly can deal with NULL expr but prefer if it is non-NULL
for some warning.

2025-03-12  Jakub Jelinek  

PR middle-end/119204
PR middle-end/119219
* builtins.cc (fold_builtin_2): Pass type as another argument
to fold_builtin_strspn and fold_builtin_strcspn.
(fold_builtin_strspn): Add type argument, use it instead of
size_type_node.
(fold_builtin_strcspn): Add type argument, use it instead of
TREE_TYPE (expr).

(cherry picked from commit da967f0ff324053304b350fdb18384607a346ebd)

Diff:
---
 gcc/builtins.cc | 20 +---
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/gcc/builtins.cc b/gcc/builtins.cc
index b683c130186e..3e0b590039ff 100644
--- a/gcc/builtins.cc
+++ b/gcc/builtins.cc
@@ -176,8 +176,8 @@ static tree fold_builtin_iseqsig (location_t, tree, tree);
 static tree fold_builtin_varargs (location_t, tree, tree*, int);
 
 static tree fold_builtin_strpbrk (location_t, tree, tree, tree, tree);
-static tree fold_builtin_strspn (location_t, tree, tree, tree);
-static tree fold_builtin_strcspn (location_t, tree, tree, tree);
+static tree fold_builtin_strspn (location_t, tree, tree, tree, tree);
+static tree fold_builtin_strcspn (location_t, tree, tree, tree, tree);
 
 static rtx expand_builtin_object_size (tree);
 static rtx expand_builtin_memory_chk (tree, rtx, machine_mode,
@@ -10656,10 +10656,10 @@ fold_builtin_2 (location_t loc, tree expr, tree 
fndecl, tree arg0, tree arg1)
   return fold_builtin_modf (loc, arg0, arg1, type);
 
 case BUILT_IN_STRSPN:
-  return fold_builtin_strspn (loc, expr, arg0, arg1);
+  return fold_builtin_strspn (loc, expr, arg0, arg1, type);
 
 case BUILT_IN_STRCSPN:
-  return fold_builtin_strcspn (loc, expr, arg0, arg1);
+  return fold_builtin_strcspn (loc, expr, arg0, arg1, type);
 
 case BUILT_IN_STRPBRK:
   return fold_builtin_strpbrk (loc, expr, arg0, arg1, type);
@@ -11160,7 +11160,7 @@ fold_builtin_strpbrk (location_t loc, tree, tree s1, 
tree s2, tree type)
form of the builtin function call.  */
 
 static tree
-fold_builtin_strspn (location_t loc, tree expr, tree s1, tree s2)
+fold_builtin_strspn (location_t loc, tree expr, tree s1, tree s2, tree type)
 {
   if (!validate_arg (s1, POINTER_TYPE)
   || !validate_arg (s2, POINTER_TYPE))
@@ -11176,8 +11176,7 @@ fold_builtin_strspn (location_t loc, tree expr, tree 
s1, tree s2)
   if ((p1 && *p1 == '\0') || (p2 && *p2 == '\0'))
 /* Evaluate and ignore both arguments in case either one has
side-effects.  */
-return omit_two_operands_loc (loc, size_type_node, size_zero_node,
- s1, s2);
+return omit_two_operands_loc (loc, type, size_zero_node, s1, s2);
   return NULL_TREE;
 }
 
@@ -11200,7 +11199,7 @@ fold_builtin_strspn (location_t loc, tree expr, tree 
s1, tree s2)
form of the builtin function call.  */
 
 static tree
-fold_builtin_strcspn (location_t loc, tree expr, tree s1, tree s2)
+fold_builtin_strcspn (location_t loc, tree expr, tree s1, tree s2, tree type)
 {
   if (!validate_arg (s1, POINTER_TYPE)
   || !validate_arg (s2, POINTER_TYPE))
@@ -11216,8 +11215,7 @@ fold_builtin_strcspn (location_t loc, tree expr, tree 
s1, tree s2)
 {
   /* Evaluate and ignore argument s2 in case it has
 side-effects.  */
-  return omit_one_operand_loc (loc, TREE_TYPE (expr),
-  size_zero_node, s2);
+  return omit_one_operand_loc (loc, type, size_zero_node, s2);
 }
 
   /* If the second argument is "", return __builtin_strlen(s1).  */
@@ -11231,7 +11229,7 @@ fold_builtin_strcspn (location_t loc, tree expr, tree 
s1, tree s2)
   if (!fn)
return NULL_TREE;
 
-  return fold_convert_loc (loc, TREE_TYPE (expr),
+  return fold_convert_loc (loc, type,
 

[gcc r14-11469] c++: Evaluate immediate invocation call arguments with mce_true [PR119150]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:13fd7c971fb573b2f1721c3684b34a65133b7085

commit r14-11469-g13fd7c971fb573b2f1721c3684b34a65133b7085
Author: Jakub Jelinek 
Date:   Thu Mar 13 00:42:54 2025 +0100

c++: Evaluate immediate invocation call arguments with mce_true [PR119150]

Since Marek's r14-4140 which moved immediate invocation evaluation
from build_over_call to cp_fold_r, the following testcase is miscompiled.

The a = foo (bar ()); case is actually handled right, that is handled
in cp_fold_r and the whole CALL_EXPR is at that point evaluated by
cp_fold_immediate_r with cxx_constant_value (stmt, tf_none);
and that uses mce_true for evaluation of the argument as well as the actual
call.

But in the bool b = foo (bar ()); case we actually try to evaluate this
as non-manifestly constant-evaluated.  And while
  /* Make sure we fold std::is_constant_evaluated to true in an
 immediate function.  */
  if (DECL_IMMEDIATE_FUNCTION_P (fun))
call_ctx.manifestly_const_eval = mce_true;
ensures that if consteval and __builtin_is_constant_evaluated () is true
inside of that call, this happens after arguments to the function
have been already constant evaluated in cxx_bind_parameters_in_call.
The call_ctx in that case also includes new call_ctx.call, something that
shouldn't be used for the arguments, so the following patch just arranges
to call cxx_bind_parameters_in_call with manifestly_constant_evaluated =
mce_true.

2025-03-13  Jakub Jelinek  

PR c++/119150
* constexpr.cc (cxx_eval_call_expression): For
DECL_IMMEDIATE_FUNCTION_P (fun) set manifestly_const_eval in new_ctx
and new_call to mce_true and set ctx to &new_ctx.

* g++.dg/cpp2a/consteval41.C: New test.

(cherry picked from commit ebf6e6241f5658a3cae462b1314f4a8f2bc71760)

Diff:
---
 gcc/cp/constexpr.cc  |  9 
 gcc/testsuite/g++.dg/cpp2a/consteval41.C | 37 
 2 files changed, 46 insertions(+)

diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc
index f3b61f5f391a..d3b9fe08e1a5 100644
--- a/gcc/cp/constexpr.cc
+++ b/gcc/cp/constexpr.cc
@@ -3030,6 +3030,15 @@ cxx_eval_call_expression (const constexpr_ctx *ctx, tree 
t,
   ctx->global->put_value (new_ctx.object, ctor);
   ctx = &new_ctx;
 }
+  /* An immediate invocation is manifestly constant evaluated including the
+ arguments of the call, so use mce_true even for the argument
+ evaluation.  */
+  if (DECL_IMMEDIATE_FUNCTION_P (fun))
+{
+  new_ctx.manifestly_const_eval = mce_true;
+  new_call.manifestly_const_eval = mce_true;
+  ctx = &new_ctx;
+}
 
   /* We used to shortcut trivial constructor/op= here, but nowadays
  we can only get a trivial function here with -fno-elide-constructors.  */
diff --git a/gcc/testsuite/g++.dg/cpp2a/consteval41.C 
b/gcc/testsuite/g++.dg/cpp2a/consteval41.C
new file mode 100644
index ..76c4a5d2fff7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/consteval41.C
@@ -0,0 +1,37 @@
+// PR c++/119150
+// { dg-do run { target c++20 } }
+
+consteval bool
+foo (bool x)
+{
+  return x;
+}
+
+constexpr bool
+bar ()
+{
+#if __cpp_if_consteval >= 202106L
+  if consteval
+{
+  return true;
+}
+  else
+{
+  return false;
+}
+#else
+  return __builtin_is_constant_evaluated ();
+#endif
+}
+
+int
+main ()
+{
+  bool a = false;
+  a = foo (bar ());
+  if (!a)
+__builtin_abort ();
+  bool b = foo (bar ());
+  if (!b)
+__builtin_abort ();
+}

[gcc r14-11472] widening_mul: Fix up further r14-8680 widening mul issues [PR119417]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:6c7c25c282642565b23da21cab7e313e78744ab5

commit r14-11472-g6c7c25c282642565b23da21cab7e313e78744ab5
Author: Jakub Jelinek 
Date:   Wed Mar 26 14:03:50 2025 +0100

widening_mul: Fix up further r14-8680 widening mul issues [PR119417]

The following testcase is miscompiled since r14-8680 PR113560 changes.
I've already tried to fix some of the issues caused by that change in
r14-8823 PR113759, but apparently didn't get it right.

The problem is that the r14-8680 changes sometimes set *type_out to
a narrower type than the *new_rhs_out actually has (because it will
handle stuff like _1 = rhs1 & 0x; and imply from that HImode type_out.

Now, if in convert_mult_to_widen or convert_plusminus_to_widen we actually
get optab for the modes we've asked for (i.e. with from_mode and to_mode),
everything works fine, if the operands don't have the expected types,
they are converted to those (for INTEGER_CSTs with fold_convert,
otherwise with build_and_insert_cast).
On the following testcase on aarch64 that is not the case, we ask
for from_mode HImode and to_mode DImode, but get actual_mode SImode.
The mult_rhs1 operand already has SImode and we change type1 to unsigned int
and so no cast is actually done, except that the & 0x is lost that way.

The following patch ensures that if we change typeN because of wider
actual_mode (or because of a sign change), we first cast to the old
typeN (if the r14-8680 code was encountered, otherwise it would have the
same precision) and only then change it, and then perhaps cast again.

On the testcase on aarch64-linux the patch results in the expected
-   add x19, x19, w0, uxtw 1
+   add x19, x19, w0, uxth 1
difference.

2025-03-26  Jakub Jelinek  

PR tree-optimization/119417
* tree-ssa-math-opts.cc (convert_mult_to_widen): Before changing
typeN because actual_precision/from_unsignedN differs cast rhsN
to typeN if it has a different type.
(convert_plusminus_to_widen): Before changing
typeN because actual_precision/from_unsignedN differs cast mult_rhsN
to typeN if it has a different type.

* gcc.dg/torture/pr119417.c: New test.

(cherry picked from commit 02132faf4e2fb604758aa86f0b097e6871be595a)

Diff:
---
 gcc/testsuite/gcc.dg/torture/pr119417.c | 24 +
 gcc/tree-ssa-math-opts.cc   | 48 ++---
 2 files changed, 68 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/torture/pr119417.c 
b/gcc/testsuite/gcc.dg/torture/pr119417.c
new file mode 100644
index ..d0b5378ceb42
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr119417.c
@@ -0,0 +1,24 @@
+/* PR tree-optimization/119417 */
+/* { dg-do run { target int32 } } */
+
+__attribute__((noipa)) void
+foo (unsigned long long x)
+{
+  if (x != 0)
+__builtin_abort ();
+}
+
+unsigned v = 0x1;
+
+int
+main ()
+{
+  unsigned long long a = 0;
+  while (1)
+{
+  a = a + ((v & 0x) * 2);
+  foo (a);
+  if (v)
+   break;
+}
+}
diff --git a/gcc/tree-ssa-math-opts.cc b/gcc/tree-ssa-math-opts.cc
index 705f4a4695ac..60cc0c2a3eb2 100644
--- a/gcc/tree-ssa-math-opts.cc
+++ b/gcc/tree-ssa-math-opts.cc
@@ -2866,7 +2866,17 @@ convert_mult_to_widen (gimple *stmt, 
gimple_stmt_iterator *gsi)
 return false;
   if (actual_precision != TYPE_PRECISION (type1)
   || from_unsigned1 != TYPE_UNSIGNED (type1))
-type1 = build_nonstandard_integer_type (actual_precision, from_unsigned1);
+{
+  if (!useless_type_conversion_p (type1, TREE_TYPE (rhs1)))
+   {
+ if (TREE_CODE (rhs1) == INTEGER_CST)
+   rhs1 = fold_convert (type1, rhs1);
+ else
+   rhs1 = build_and_insert_cast (gsi, loc, type1, rhs1);
+   }
+  type1 = build_nonstandard_integer_type (actual_precision,
+ from_unsigned1);
+}
   if (!useless_type_conversion_p (type1, TREE_TYPE (rhs1)))
 {
   if (TREE_CODE (rhs1) == INTEGER_CST)
@@ -2876,7 +2886,17 @@ convert_mult_to_widen (gimple *stmt, 
gimple_stmt_iterator *gsi)
 }
   if (actual_precision != TYPE_PRECISION (type2)
   || from_unsigned2 != TYPE_UNSIGNED (type2))
-type2 = build_nonstandard_integer_type (actual_precision, from_unsigned2);
+{
+  if (!useless_type_conversion_p (type2, TREE_TYPE (rhs2)))
+   {
+ if (TREE_CODE (rhs2) == INTEGER_CST)
+   rhs2 = fold_convert (type2, rhs2);
+ else
+   rhs2 = build_and_insert_cast (gsi, loc, type2, rhs2);
+   }
+  type2 = build_nonstandard_integer_type (actual_precision,
+ from_unsigned2);
+}
   if (!useless_type_conversion_p (type2, TREE_TYPE (rhs2)))
 {
   if (TREE_CODE (rhs2) == INTEGER_CST)
@@ -308

[gcc r15-8992] contrib: add dg-lint and libgdiagnostics.py [PR116163]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:8d6de758cca6d16eb930ac1a7008ee54ec5489d9

commit r15-8992-g8d6de758cca6d16eb930ac1a7008ee54ec5489d9
Author: David Malcolm 
Date:   Thu Mar 27 19:46:20 2025 -0400

contrib: add dg-lint and libgdiagnostics.py [PR116163]

Changed in v2:
- eliminated COMMON_MISSPELLINGS in favor of retesting with a regexp
  that adds underscores
- add a list of KNOWN_DIRECTIVES, and complain if we see a directive
  that isn't in the list
- various refactorings to reduce the nesting within the script
- skip more kinds of file ('README', 'Makefile.am', 'Makefile.in',
  'gen_directive_tests')
- keep track of the number of files scanned and report it and the end
  with a note

This patch adds a new dg-lint subdirectory below contrib, containing
a "dg-lint" script for detecting common mistakes made in our DejaGnu
tests.

Specifically, DejaGnu's dg.exp's dg-get-options has a regexp for
detecting dg- directives
  https://git.savannah.gnu.org/gitweb/?p=dejagnu.git;a=blob;f=lib/dg.exp
here's the current:

set tmp [grep $prog "{\[ \t\]\+dg-\[-a-z\]\+\[ \t\]\+.*\[ \t\]\+}" line]

which if I'm reading it right requires a "{", then one or more tab/space
chars, then a "dg-" directive name, then one of more tab/space
characters, then anything (for arguments to the directive), then one of
more tab/space character, then a "}".

There are numerous places in our testsuite which look like attempts to
use a directive, but which don't match this regexp.

The script warns about such places, along with a list of misspelled
directives (currently just "dg_options" for "dg-options"), and a warning
if a dg-do appears after a dg-require-* (as per
https://gcc.gnu.org/onlinedocs/gccint/Directives.html
"This directive must appear after any dg-do directive in the test
and before any dg-additional-sources directive." for
dg-require-effective-target.

dg-lint uses libgdiagnostics to report its results; the patch adds a
new libgdiagnostics.py script below contrib/dg-lint.  This uses Python's
ctypes module to expose libgdianostics.so to Python via FFI.  Hence
the warnings have colorization, quote the pertinent parts of the tested
file, can have fix-it hints, etc.  Here's the output from the tests, run
from the top-level directory:

$ LD_LIBRARY_PATH=../build/gcc/ ./contrib/dg-lint/dg-lint 
contrib/dg-lint/test-*.c
contrib/dg-lint/test-1.c:6:6: warning: misspelled directive: 'dg_final'; 
did you mean 'dg-final'?
6 | /* { dg_final { scan_assembler_times "vmsumudm" 2 } } */
  |  ^~~~
  |  dg-final
contrib/dg-lint/test-1.c:15:4: warning: directive 'dg-output-file' appears 
not to match dg.exp's regexp
   15 |dg-output-file "m4.out"
  |^~
contrib/dg-lint/test-1.c:18:4: warning: directive 'dg-output-file' appears 
not to match dg.exp's regexp
   18 |dg-output-file "m4.out" }
  |^~
contrib/dg-lint/test-1.c:21:6: warning: directive 'dg-output-file' appears 
not to match dg.exp's regexp
   21 |{ dg-output-file "m4.out"
  |  ^~
contrib/dg-lint/test-1.c:24:5: warning: directive 'dg-output-file' appears 
not to match dg.exp's regexp
   24 |{dg-output-file "m4.out"}
  | ^~
contrib/dg-lint/test-1.c:27:6: warning: directive 'dg-output-file' appears 
not to match dg.exp's regexp
   27 |{ dg-output-file, "m4.out" }
  |  ^~
contrib/dg-lint/test-2.c:4:6: warning: 'dg-do' after 
'dg-require-effective-target'
4 | /* { dg-do compile } */
  |  ^
contrib/dg-lint/test-2.c:3:6: note: 'dg-require-effective-target' was here
3 | /* { dg-require-effective-target c++11 } */
  |  ^~~

I don't yet have a way to verify these tests (clearly we can't use
DejaGnu for this).

These Python bindings could be used by other projects, but so far I only
implemented what I needed for dg-lint.

Running the test on the GCC source tree finds dozens of issues, which
followup patches address.

Tested with Python 3.8

contrib/ChangeLog:
PR testsuite/116163
* dg-lint/dg-lint: New file.
* dg-lint/libgdiagnostics.py: New file.
* dg-lint/test-1.c: New file.
* dg-lint/test-2.c: New file.

Signed-off-by: David Malcolm 

Diff:
---
 contrib/dg-lint/dg-lint| 404 +
 contrib/dg-lint/libgdiagnostics.py | 250 +++
 contrib/dg-lint/test-1.c   |  41 
 contrib/dg-lint/test-2.c   |   8 +
 4 files changed, 703 insertions(+)

diff --git a/contrib/dg-lint/dg-lint b/contrib/dg-lint/dg-lint
new file mode 100755
index 00

[gcc/devel/omp/gcc-14] testsuite: Fix up append-args-interop.f90 test

[Sandra Loosemore via Gcc-cvs]

https://gcc.gnu.org/g:dbf98134378b63b1a5c206f8db0739ceb7fdffe3

commit dbf98134378b63b1a5c206f8db0739ceb7fdffe3
Author: Jakub Jelinek 
Date:   Wed Mar 26 14:41:15 2025 +0100

testsuite: Fix up append-args-interop.f90 test

The gcc/testsuite/*/gomp/ tests aren't compiled with include or module
paths pointing to libgomp, so shouldn't be using omp.h nor use omp_lib
etc.

The following patch adjusts the test to define it locally, like
e.g. recently in interop-5.f90 test or many other tests which have
their own definitions of types or enumerators they need.

2025-03-26  Jakub Jelinek  

* gfortran.dg/gomp/append-args-interop.f90: Don't use omp_lib,
instead use iso_c_binding and define omp_interop_kind parameter
locally.

(cherry picked from commit d402a3911d5eeb4680397458aa31dad4c3f5136e)

Diff:
---
 gcc/testsuite/gfortran.dg/gomp/append-args-interop.f90 | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gfortran.dg/gomp/append-args-interop.f90 
b/gcc/testsuite/gfortran.dg/gomp/append-args-interop.f90
index 11a0f01daa46..f2c4d9714647 100644
--- a/gcc/testsuite/gfortran.dg/gomp/append-args-interop.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/append-args-interop.f90
@@ -6,7 +6,8 @@
 ! append_args clause. 
 
 module m
-  use omp_lib, only: omp_interop_kind
+  use iso_c_binding, only: c_intptr_t
+  integer, parameter :: omp_interop_kind = c_intptr_t
 contains
 subroutine g(x,y,z)
   integer(omp_interop_kind) :: x, y, z

[gcc(refs/users/omachota/heads/rtl-ssa-dce)] rtl-ssa: dce improve prelive conditions

[Ondrej Machota via Gcc-cvs]

https://gcc.gnu.org/g:829a7f63e2616652a81a6ee432cf72ae4232235f

commit 829a7f63e2616652a81a6ee432cf72ae4232235f
Author: Ondřej Machota 
Date:   Fri Feb 21 23:06:19 2025 +0100

rtl-ssa: dce improve prelive conditions

Diff:
---
 gcc/dce.cc | 38 +++---
 1 file changed, 31 insertions(+), 7 deletions(-)

diff --git a/gcc/dce.cc b/gcc/dce.cc
index 909e47b99195..49bc4c3c6780 100644
--- a/gcc/dce.cc
+++ b/gcc/dce.cc
@@ -17,7 +17,6 @@ You should have received a copy of the GNU General Public 
License
 along with GCC; see the file COPYING3.  If not see
 .  */
 
-#include 
 #define INCLUDE_ALGORITHM
 #define INCLUDE_FUNCTIONAL
 #define INCLUDE_ARRAY
@@ -1319,6 +1318,28 @@ bool sets_global_register(rtx_insn* insn) {
   return false;
 }
 
+bool is_control_flow(rtx_code code) {
+  // What about BARRIERs?
+  switch (code) {
+case JUMP_INSN:
+case JUMP_TABLE_DATA: // Be careful with Table jump addresses - ADDR_VEC, 
ADDR_DIFF_VEC, PREFETCH 
+case TRAP_IF:
+case IF_THEN_ELSE: // Also COMPARE?
+case COND_EXEC: // We might want to check the operation that is under this?
+case RETURN:
+case SIMPLE_RETURN:
+case EH_RETURN:
+  return true;
+
+default:
+  return false;
+  }
+}
+
+bool handle_rtl_previle(rtx_insn *insn) {
+  // TODO : handle everything except parallel
+}
+
 bool is_prelive(insn_info *insn)
 {
   if (insn->is_artificial()) // phis are never prelive
@@ -1344,7 +1365,7 @@ bool is_prelive(insn_info *insn)
   */
 
   // Now, we only have to handle rtx insns
-  assert(insn->is_real());
+  gcc_assert (insn->is_real());
   auto rtl = insn->rtl();
 
   if (!INSN_P(rtl)) // This might be useless
@@ -1353,20 +1374,23 @@ bool is_prelive(insn_info *insn)
   rtx pat = PATTERN(rtl); // if we use this instead of rtl, then rtl notes 
wont be checked
   
   // TODO : join if statements
+  // We need to describe all possible prelive instructions, a list of all the 
instructions is inside `rtl.def`
 
-  if (JUMP_P(rtl))
+  // Control flow
+  auto rtl_code = GET_CODE(rtl);
+  if (is_control_flow(rtl_code))
 return true;
 
-  // We need to describe all possible prelive instructions, a list of all the 
instructions is inside `rtl.def`
-
   // Mark set of a global register
   if (sets_global_register(rtl))
 return true;
 
   // Call is inside side_effects_p
-  if (side_effects_p(rtl) || volatile_refs_p(rtl) || can_throw_internal(rtl))
+  if (volatile_refs_p(rtl) || can_throw_internal(rtl) || BARRIER_P(rtl) || 
rtl_code == PREFETCH)
 return true;
 
+  // TODO : handle parallel, {pre,post}_{int,dec}, {pre,post}_modify
+
   return false;
 }
 
@@ -1524,8 +1548,8 @@ rtl_ssa_dce_sweep(std::unordered_set marked)
 changes[i] = &to_delete[i];
   }
 
-  // if (verify_insn_changes())
   crtl->ssa->change_insns(changes);
+  // if (verify_insn_changes())
 }
 
 static unsigned int

[gcc] Created branch 'meissner/heads/work197-sha' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work197-sha' was created in namespace 'refs/users' 
pointing to:

 1c5c57092cf2... testsuite: Require effective target sigsetjmp for gcov-31/3

[gcc(refs/users/meissner/heads/work197-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e441f8a8a7cfb835c581fe62aadad0df6efa9947

commit e441f8a8a7cfb835c581fe62aadad0df6efa9947
Author: Michael Meissner 
Date:   Thu Mar 27 15:10:38 2025 -0400

Add ChangeLog.test and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 5 +
 gcc/REVISION   | 1 +
 2 files changed, 6 insertions(+)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..dc0a657d9ae0
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,5 @@
+ Branch work197-test, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..53ccefc60743
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work197-test branch

[gcc r15-8987] Ada: Fix too late initialization of tasking runtime with standalone library

[Eric Botcazou via Gcc-cvs]

https://gcc.gnu.org/g:f4649a8901b2ebd6bd87451c8b758022600bf281

commit r15-8987-gf4649a8901b2ebd6bd87451c8b758022600bf281
Author: Eric Botcazou 
Date:   Thu Mar 27 20:29:51 2025 +0100

Ada: Fix too late initialization of tasking runtime with standalone library

The Tasking_Runtime_Initialize routine installs the tasking version of the
RTS_Lock manipulation routines and thus needs to be called very early before
the elaboration of all the Ada units of the program, including those of the
runtime itself.

This is guaranteed by the binder when the tasking runtime is explicitly
dragged into the link.  However, for a standalone dynamic library that
does not depend on the tasking runtime and is auto-initialized, no such
guarantee holds, even though the library might be later dragged into a
link that contains the tasking runtime.

This change causes the routine to be called even earlier, in particular
at load time when a (standalone) dynamic library is involved in the link,
so as to meet the requirements.  It will cause the routine to be called
twice if the main subprogram is generated by the binder, but this is
harmless since the routine is idempotent.

ada/
* libgnarl/s-tasini.adb (Tasking_Runtime_Initialize): Add pragma
Linker_Constructor for the procedure.

Diff:
---
 gcc/ada/libgnarl/s-tasini.adb | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/libgnarl/s-tasini.adb b/gcc/ada/libgnarl/s-tasini.adb
index 144ac7c1c4e8..ae0826590c86 100644
--- a/gcc/ada/libgnarl/s-tasini.adb
+++ b/gcc/ada/libgnarl/s-tasini.adb
@@ -115,11 +115,13 @@ package body System.Tasking.Initialization is
procedure Tasking_Runtime_Initialize;
pragma Export (Ada, Tasking_Runtime_Initialize,
   "__gnat_tasking_runtime_initialize");
+   pragma Linker_Constructor (Tasking_Runtime_Initialize);
--  This procedure starts the initialization of the GNARL. It installs the
-   --  tasking versions of the RTS_Lock manipulation routines. It is called
+   --  tasking version of the RTS_Lock manipulation routines. It is called
--  very early before the elaboration of all the Ada units of the program,
--  including those of the runtime, because this elaboration may require
-   --  the initialization of RTS_Lock objects.
+   --  the initialization of RTS_Lock objects, which means that it must only
+   --  contain code to which pragma Restrictions (No_Elaboration_Code) applies.
 
--
-- Change_Base_Priority --

[gcc] Created branch 'meissner/heads/work198' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198' was created in namespace 'refs/users' 
pointing to:

 4242ea1916ff... testsuite: fix g++.dg/template/explicit-args6.C

[gcc(refs/users/meissner/heads/work198-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7342a36448a615d64027c7c219b4c7f4dcc30ba4

commit 7342a36448a615d64027c7c219b4c7f4dcc30ba4
Author: Michael Meissner 
Date:   Thu Mar 27 15:33:34 2025 -0400

Add ChangeLog.vpair and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 5 +
 gcc/REVISION| 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..da61dc2ec8af
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,5 @@
+ Branch work198-vpair, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..a14a3e5e6e3f 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-vpair branch

[gcc(refs/users/meissner/heads/work198-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8c070a4ee65622ac46bb24ab8d477ef88b33e44f

commit 8c070a4ee65622ac46bb24ab8d477ef88b33e44f
Author: Michael Meissner 
Date:   Thu Mar 27 15:32:40 2025 -0400

Add ChangeLog.dmf and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..70118273928d
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,5 @@
+ Branch work198-dmf, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..f55420ff9cd6 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-dmf branch

[gcc(refs/users/meissner/heads/work198)] Add ChangeLog.meissner and REVISION.

[Michael Meissner via Libstdc++-cvs]

https://gcc.gnu.org/g:ebf3fca574e96dc8207e1deaa60769987d935c6e

commit ebf3fca574e96dc8207e1deaa60769987d935c6e
Author: Michael Meissner 
Date:   Thu Mar 27 15:31:49 2025 -0400

Add ChangeLog.meissner and REVISION.

2025-03-27  Michael Meissner  

gcc/

* REVISION: New file for branch.
* ChangeLog.meissner: New file.

gcc/c-family/

* ChangeLog.meissner: New file.

gcc/c/

* ChangeLog.meissner: New file.

gcc/cp/

* ChangeLog.meissner: New file.

gcc/fortran/

* ChangeLog.meissner: New file.

gcc/testsuite/

* ChangeLog.meissner: New file.

libgcc/

* ChangeLog.meissner: New file.

Diff:
---
 gcc/ChangeLog.meissner   | 5 +
 gcc/REVISION | 1 +
 gcc/c-family/ChangeLog.meissner  | 5 +
 gcc/c/ChangeLog.meissner | 5 +
 gcc/cp/ChangeLog.meissner| 5 +
 gcc/fortran/ChangeLog.meissner   | 5 +
 gcc/testsuite/ChangeLog.meissner | 5 +
 libgcc/ChangeLog.meissner| 5 +
 libstdc++-v3/ChangeLog.meissner  | 5 +
 9 files changed, 41 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
new file mode 100644
index ..7e6ce5818833
--- /dev/null
+++ b/gcc/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work198, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..0fe73178b1f2
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work198 branch
diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner
new file mode 100644
index ..7e6ce5818833
--- /dev/null
+++ b/gcc/c-family/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work198, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner
new file mode 100644
index ..7e6ce5818833
--- /dev/null
+++ b/gcc/c/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work198, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner
new file mode 100644
index ..7e6ce5818833
--- /dev/null
+++ b/gcc/cp/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work198, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner
new file mode 100644
index ..7e6ce5818833
--- /dev/null
+++ b/gcc/fortran/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work198, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
new file mode 100644
index ..7e6ce5818833
--- /dev/null
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work198, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
new file mode 100644
index ..7e6ce5818833
--- /dev/null
+++ b/libgcc/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work198, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner
new file mode 100644
index ..7e6ce5818833
--- /dev/null
+++ b/libstdc++-v3/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work198, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch

[gcc] Created branch 'meissner/heads/work198-vpair' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-vpair' was created in namespace 'refs/users' 
pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work197-test' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work197-test' was created in namespace 'refs/users' 
pointing to:

 1c5c57092cf2... testsuite: Require effective target sigsetjmp for gcov-31/3

[gcc(refs/users/meissner/heads/work198-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c73646078a196f9433a68bb2ddb8e701b63fa1c0

commit c73646078a196f9433a68bb2ddb8e701b63fa1c0
Author: Michael Meissner 
Date:   Thu Mar 27 15:34:29 2025 -0400

Add ChangeLog.bugs and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..6279dfc648b8
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,5 @@
+ Branch work198-bugs, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..ca8757f6538c 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-bugs branch

[gcc] Created branch 'meissner/heads/work198-bugs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-bugs' was created in namespace 'refs/users' 
pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work198-dmf' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-dmf' was created in namespace 'refs/users' 
pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work198-libs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-libs' was created in namespace 'refs/users' 
pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work198-libs)] Add ChangeLog.libs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3e3f396925a655ba176a376f03ede9316b12e77a

commit 3e3f396925a655ba176a376f03ede9316b12e77a
Author: Michael Meissner 
Date:   Thu Mar 27 15:35:28 2025 -0400

Add ChangeLog.libs and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.libs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.libs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs
new file mode 100644
index ..e7c5609f55ea
--- /dev/null
+++ b/gcc/ChangeLog.libs
@@ -0,0 +1,5 @@
+ Branch work198-libs, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..3db41217765f 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-libs branch

[gcc(refs/users/meissner/heads/work197-math)] Add ChangeLog.math and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8a139c7b3a2ed108be74f6a7d82f5ec98fec540b

commit 8a139c7b3a2ed108be74f6a7d82f5ec98fec540b
Author: Michael Meissner 
Date:   Thu Mar 27 15:11:39 2025 -0400

Add ChangeLog.math and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.math: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.math | 5 +
 gcc/REVISION   | 1 +
 2 files changed, 6 insertions(+)

diff --git a/gcc/ChangeLog.math b/gcc/ChangeLog.math
new file mode 100644
index ..f39ead6bbdf0
--- /dev/null
+++ b/gcc/ChangeLog.math
@@ -0,0 +1,5 @@
+ Branch work197-math, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..07ebd8f72dfa
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work197-math branch

[gcc(refs/users/meissner/heads/work198-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:63b32bc920366f5841273760e7536c102cb507ef

commit 63b32bc920366f5841273760e7536c102cb507ef
Author: Michael Meissner 
Date:   Thu Mar 27 15:37:14 2025 -0400

Add ChangeLog.test and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..91b1269028a0
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,5 @@
+ Branch work198-test, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..3520a958372f 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-test branch

[gcc] Created branch 'meissner/heads/work198-math' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-math' was created in namespace 'refs/users' 
pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work198-math)] Add ChangeLog.math and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:16e9f45d080d495b2a4a148729868dcb4ee3f314

commit 16e9f45d080d495b2a4a148729868dcb4ee3f314
Author: Michael Meissner 
Date:   Thu Mar 27 15:38:15 2025 -0400

Add ChangeLog.math and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.math: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.math | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.math b/gcc/ChangeLog.math
new file mode 100644
index ..bd91728ad74b
--- /dev/null
+++ b/gcc/ChangeLog.math
@@ -0,0 +1,5 @@
+ Branch work198-math, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..f1d57d80f2d9 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-math branch

[gcc] Created branch 'meissner/heads/work198-submit' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-submit' was created in namespace 
'refs/users' pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work198-submit)] Add ChangeLog.submit and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:efa3b7e39317d4ec8c05f58889a2b0ccc80959a5

commit efa3b7e39317d4ec8c05f58889a2b0ccc80959a5
Author: Michael Meissner 
Date:   Thu Mar 27 15:39:14 2025 -0400

Add ChangeLog.submit and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.submit: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.submit | 5 +
 gcc/REVISION | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.submit b/gcc/ChangeLog.submit
new file mode 100644
index ..f2900ea7c30c
--- /dev/null
+++ b/gcc/ChangeLog.submit
@@ -0,0 +1,5 @@
+ Branch work198-submit, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..98fec1896ce4 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-submit branch

[gcc] Created branch 'meissner/heads/work198-paddis' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work198-paddis' was created in namespace 
'refs/users' pointing to:

 ebf3fca574e9... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work198-paddis)] Add ChangeLog.paddis and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:11918698ecff7e99f6fb4c722bb70cb2dffb4610

commit 11918698ecff7e99f6fb4c722bb70cb2dffb4610
Author: Michael Meissner 
Date:   Thu Mar 27 15:40:05 2025 -0400

Add ChangeLog.paddis and update REVISION.

2025-03-27  Michael Meissner  

gcc/

* ChangeLog.paddis: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.paddis | 5 +
 gcc/REVISION | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.paddis b/gcc/ChangeLog.paddis
new file mode 100644
index ..322c5d4c6894
--- /dev/null
+++ b/gcc/ChangeLog.paddis
@@ -0,0 +1,5 @@
+ Branch work198-paddis, baseline 
+
+2025-03-27   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 0fe73178b1f2..80f070afe22c 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work198 branch
+work198-paddis branch

[gcc r15-8486] libstdc++: Fix std.compat exports of and

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:ff3343518ae6e1aa1efe7fe02a6a4c6cb24f3b62

commit r15-8486-gff3343518ae6e1aa1efe7fe02a6a4c6cb24f3b62
Author: Jonathan Wakely 
Date:   Thu Mar 20 18:47:33 2025 +

libstdc++: Fix std.compat exports of  and 

libstdc++-v3/ChangeLog:

* src/c++23/std.compat.cc.in: Only export  and
 contents for C++26 and later.

Reviewed-by: Tomasz Kamiński 

Diff:
---
 libstdc++-v3/src/c++23/std.compat.cc.in | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/src/c++23/std.compat.cc.in 
b/libstdc++-v3/src/c++23/std.compat.cc.in
index ba7ed0312ab8..344502195b1c 100644
--- a/libstdc++-v3/src/c++23/std.compat.cc.in
+++ b/libstdc++-v3/src/c++23/std.compat.cc.in
@@ -21,11 +21,15 @@
 // see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 // .
 
-export module std.compat;
-export import std;
+module;
 
 #include 
+#include 
+
+export module std.compat;
+export import std;
 
+#ifdef __STDC_VERSION_STDBIT_H__
 // 
 export
 {
@@ -52,7 +56,9 @@ _GLIBCXX_STDBIT_FUNC(stdc_bit_floor);
 _GLIBCXX_STDBIT_FUNC(stdc_bit_ceil);
 #undef _GLIBCXX_STDBIT_FUNC
 }
+#endif
 
+#ifdef __STDC_VERSION_STDCKDINT_H__
 // 
 export
 {
@@ -60,6 +66,7 @@ export
   using __gnu_cxx::ckd_sub;
   using __gnu_cxx::ckd_mul;
 }
+#endif
 
 #define STD_COMPAT 1

[gcc(refs/users/meissner/heads/work198-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:857ec60fc5609f89b0a0cbbf8bb3003c78c293e7

commit 857ec60fc5609f89b0a0cbbf8bb3003c78c293e7
Author: Michael Meissner 
Date:   Thu Mar 27 20:41:46 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 212 +
 1 file changed, 212 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 6279dfc648b8..8ae245fe2af6 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,5 +1,217 @@
+ Branch work198-bugs, patch #202 
+
+PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
+
+We had optimizations for splat of a vector extract for the other vector
+types, but we missed having one for V2DI and V2DF.  This patch adds a
+combiner insn to do this optimization.
+
+In looking at the source, we had similar optimizations for V4SI and V4SF
+extract and splats, but we missed doing V2DI/V2DF.
+
+Without the patch for the code:
+
+   vector long long splat_dup_l_0 (vector long long v)
+   {
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+   }
+
+the compiler generates (on a little endian power9):
+
+   splat_dup_l_0:
+   mfvsrld 9,34
+   mtvsrdd 34,9,9
+   blr
+
+Now it generates:
+
+   splat_dup_l_0:
+   xxpermdi 34,34,34,3
+   blr
+
+2025-03-27  Michael Meissner  
+
+gcc/
+
+   PR target/99293
+   * config/rs6000/vsx.md (vsx_splat_extract_): New insn.
+
+gcc/testsuite/
+
+   PR target/99293
+   * gcc.target/powerpc/builtins-1.c: Adjust insn count.
+   * gcc.target/powerpc/pr99293.c: New test.
+
+ Branch work198-bugs, patch #201 
+
+PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
+
+Previously GCC would zero externd a DImode GPR value to TImode by first zero
+extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
+move this value to a VSX register.
+
+This patch does the move directly, since if the middle argument to MTVSRDD is 
0,
+it does the zero extend.
+
+If the DImode value is already in a vector register, it does a XXSPLTIB and
+XXPERMDI to get the value into the bottom 64-bits of the register.
+
+I have built GCC with the patches in this patch set applied on both little and
+big endian PowerPC systems and there were no regressions.  Can I apply this
+patch to GCC 15?
+
+2025-03-27  Michael Meissner  
+
+gcc/
+
+   PR target/108598
+   * gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.
+
+gcc/testsuite/
+
+   PR target/108598
+   * gcc.target/powerpc/pr108958.c: New test.
+
+ Branch work198-bugs, patch #200 
+
+Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.
+
+This is version 5 of the patch.
+
+In versions 4 and 5, I made the following changes:
+
+1: I changed the use of enums to match current C++.
+
+In version 3, I made the following changes:
+
+1: The new argument to rs6000_reverse_condition that says whether we should
+   allow ordered floating point compares to be reversed is now an
+   enumeration instead of a boolean.
+
+2: I tried to make the code in rs6000_reverse_condition clearer.
+
+3: I added checks in invert_fpmask_comparison_operator to prevent ordered
+   floating point compares from being reversed unless -ffast-math.
+
+4: I split the test cases into 4 separate tests (ordered vs. unordered
+   compare and -O2 vs. -Ofast).
+
+In bug PR target/118541 on power9, power10, and power11 systems, for the
+function:
+
+extern double __ieee754_acos (double);
+
+double
+__acospi (double x)
+{
+  double ret = __ieee754_acos (x) / 3.14;
+  return __builtin_isgreater (ret, 1.0) ? 1.0 : ret;
+}
+
+GCC currently generates the following code:
+
+Power9  Power10 and Power11
+==  ===
+bl __ieee754_acos   bl __ieee754_acos@notoc
+nop plfd 0,.LC0@pcrel
+addis 9,2,.LC2@toc@ha   xxspltidp 12,1065353216
+addi 1,1,32 addi 1,1,32
+lfd 0,.LC2@toc@l(9) ld 0,16(1)
+addis 9,2,.LC0@toc@ha   fdiv 0,1,0
+ld 0,16(1)  mtlr 0
+lfd 12,.LC0@toc@l(9)xscmpgtdp 1,0,12
+fdiv 0,1,0  xxsel 1,0,12,1
+mtlr 0  blr
+xscmpgtdp 1,0,12
+xxsel 1,0,12,1
+blr
+
+This is because ifcvt.c optimizes the conditional floating point move to use 
the
+XSCMPGTDP instruction.
+
+However, the XSCMPGTDP instruction will generate an interrupt if one of the
+arguments is a signalling NaN and signalling NaNs can generate an interrupt.
+The IEEE comparison functions (isgreater, et

[gcc(refs/users/meissner/heads/work198-bugs)] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a6be4a6e0827fbd9b895c409639a4379b7e00a6e

commit a6be4a6e0827fbd9b895c409639a4379b7e00a6e
Author: Michael Meissner 
Date:   Thu Mar 27 20:22:34 2025 -0400

Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

This is version 4 of the patch.

In version 4, I made the following changes:

1:  I changed the use of enums to match current C++.

In version 3, I made the following changes:

1:  The new argument to rs6000_reverse_condition that says whether we 
should
allow ordered floating point compares to be reversed is now an
enumeration instead of a boolean.

2:  I tried to make the code in rs6000_reverse_condition clearer.

3:  I added checks in invert_fpmask_comparison_operator to prevent 
ordered
floating point compares from being reversed unless -ffast-math.

4:  I split the test cases into 4 separate tests (ordered vs. unordered
compare and -O2 vs. -Ofast).

In bug PR target/118541 on power9, power10, and power11 systems, for the
function:

extern double __ieee754_acos (double);

double
__acospi (double x)
{
  double ret = __ieee754_acos (x) / 3.14;
  return __builtin_isgreater (ret, 1.0) ? 1.0 : ret;
}

GCC currently generates the following code:

Power9  Power10 and Power11
==  ===
bl __ieee754_acos   bl __ieee754_acos@notoc
nop plfd 0,.LC0@pcrel
addis 9,2,.LC2@toc@ha   xxspltidp 12,1065353216
addi 1,1,32 addi 1,1,32
lfd 0,.LC2@toc@l(9) ld 0,16(1)
addis 9,2,.LC0@toc@ha   fdiv 0,1,0
ld 0,16(1)  mtlr 0
lfd 12,.LC0@toc@l(9)xscmpgtdp 1,0,12
fdiv 0,1,0  xxsel 1,0,12,1
mtlr 0  blr
xscmpgtdp 1,0,12
xxsel 1,0,12,1
blr

This is because ifcvt.c optimizes the conditional floating point move to 
use the
XSCMPGTDP instruction.

However, the XSCMPGTDP instruction will generate an interrupt if one of the
arguments is a signalling NaN and signalling NaNs can generate an interrupt.
The IEEE comparison functions (isgreater, etc.) require that the comparison 
not
raise an interrupt.

The following patch changes the PowerPC back end so that ifcvt.c will not 
change
the if/then test and move into a conditional move if the comparison is one 
of
the comparisons that do not raise an error with signalling NaNs and -Ofast 
is
not used.  If a normal comparison is used or -Ofast is used, GCC will 
continue
to generate XSCMPGTDP and XXSEL.

For the following code:

double
ordered_compare (double a, double b, double c, double d)
{
  return __builtin_isgreater (a, b) ? c : d;
}

/* Verify normal > does generate xscmpgtdp.  */

double
normal_compare (double a, double b, double c, double d)
{
  return a > b ? c : d;
}

with the following patch, GCC generates the following for power9, power10, 
and
power11:

ordered_compare:
fcmpu 0,1,2
fmr 1,4
bnglr 0
fmr 1,3
blr

normal_compare:
xscmpgtdp 1,1,2
xxsel 1,4,3,1
blr

I have built bootstrap compilers on big endian power9 systems and little 
endian
power9/power10 systems and there were no regressions.  Can I check this 
patch
into the GCC trunk, and after a waiting period, can I check this into the 
active
older branches?

2025-03-27  Michael Meissner  

gcc/

PR target/118541
* config/rs6000/predicates.md (invert_fpmask_comparison_operator): 
Do
not allow UNLT and UNLE unless -ffast-math.
* config/rs6000/rs6000-protos.h (enum rev_cond_ordered): New 
enumeration.
(rs6000_reverse_condition): Add argument.
* config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow
ordered comparisons to be reversed for floating point conditional 
moves,
but allow ordered comparisons to be reversed on jumps.
(rs6000_emit_sCOND): Adjust rs6000_reverse_condition call.
* config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise.
* config/rs6000/rs6000.md (reverse_branch_comparison): Name insn.
Adjust rs6000_reverse_condition calls.
   

[gcc(refs/users/meissner/heads/work198-dmf)] RFC2653-Add support for dense math registers.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:aedda1de28f94d6e07c97601e830f91d9b0a8947

commit aedda1de28f94d6e07c97601e830f91d9b0a8947
Author: Michael Meissner 
Date:   Thu Mar 27 20:50:50 2025 -0400

RFC2653-Add support for dense math registers.

The MMA subsystem added the notion of accumulator registers as an optional
feature of ISA 3.1 (power10).  In ISA 3.1, these accumulators overlapped 
with
the VSX registers 0..31, but logically the accumulator registers were 
separate
from the FPR registers.  In ISA 3.1, it was anticipated that in future 
systems,
the accumulator registers may no overlap with the FPR registers.  This patch
adds the support for dense math registers as separate registers.

This particular patch does not change the MMA support to use the 
accumulators
within the dense math registers.  This patch just adds the basic support for
having separate DMRs.  The next patch will switch the MMA support to use the
accumulators if -mcpu=future is used.

For testing purposes, I added an undocumented option '-mdense-math' to 
enable
or disable the dense math support.

This patch updates the wD constraint added in the previous patch.  If MMA is
selected but dense math is not selected (i.e. -mcpu=power10), the wD 
constraint
will allow access to accumulators that overlap with VSX registers 0..31.  If
both MMA and dense math are selected (i.e. -mcpu=future), the wD constraint
will only allow dense math registers.

This patch modifies the existing %A output modifier.  If MMA is selected but
dense math is not selected, then %A output modifier converts the VSX 
register
number to the accumulator number, by dividing it by 4.  If both MMA and 
dense
math are selected, then %A will map the separate DMR registers into 0..7.

The intention is that user code using extended asm can be modified to run on
both MMA without dense math and MMA with dense math:

1)  If possible, don't use extended asm, but instead use the MMA 
built-in
functions;

2)  If you do need to write extended asm, change the d constraints
targetting accumulators should now use wD;

3)  Only use the built-in zero, assemble and disassemble functions 
create
move data between vector quad types and dense math accumulators.
I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the
extended asm code.  The reason is these instructions assume there 
is a
1-to-1 correspondence between 4 adjacent FPR registers and an
accumulator that overlaps with those instructions.  With 
accumulators
now being separate registers, there no longer is a 1-to-1
correspondence.

It is possible that the mangling for DMRs and the GDB register numbers may
produce other changes in the future.

gcc/

2025-03-27   Michael Meissner  

* config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec.
(movxo): Add comments about dense math registers.
(movxo_nodm): Rename from movxo and restrict the usage to machines
without dense math registers.
(movxo_dm): New insn for movxo support for machines with dense math
registers.
(mma_): Restrict usage to machines without dense math 
registers.
(mma_xxsetaccz): Add a define_expand wrapper, and add support for 
dense
math registers.
(mma_dmsetaccz): New insn.
* config/rs6000/predicates.md (dmr_operand): New predicate.
(accumulator_operand): Add support for dense math registers.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): 
Do
not issue a de-prime instruction when disassembling a vector quad 
on a
system with dense math registers.
* config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): 
Define
__DENSE_MATH__ if we have dense math registers.
* config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE.
(enum rs6000_reload_reg_type): Add RELOAD_REG_DMR.
(LAST_RELOAD_REG_CLASS): Add support for DMR registers and the wD
constraint.
(reload_reg_map): Likewise.
(rs6000_reg_names): Likewise.
(alt_reg_names): Likewise.
(rs6000_hard_regno_nregs_internal): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_secondary_reload_memory): Add support for DMR registers.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(print_operan

[gcc(refs/users/meissner/heads/work198-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:06fd3a91146af331e7d8f88029efcc6a390904c8

commit 06fd3a91146af331e7d8f88029efcc6a390904c8
Author: Michael Meissner 
Date:   Thu Mar 27 20:52:01 2025 -0400

RFC2653-PowerPC: Add support for 1,024 bit DMR registers.

This patch is a prelimianry patch to add the full 1,024 bit dense math 
register
(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of 
the
DMR register.

This patch only adds the new 1,024 bit register support.  It does not add
support for any instructions that need 1,024 bit registers instead of 512 
bit
registers.

I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
registers.  The 'wD' constraint added in previous patches is used for these
registers.  I added support to do load and store of DMRs via the VSX 
registers,
since there are no load/store dense math instructions.  I added the new 
keyword
'__dmr' to create 1,024 bit types that can be loaded into DMRs.  At 
present, I
don't have aliases for __dmr512 and __dmr1024 that we've discussed 
internally.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2025-03-27   Michael Meissner  

gcc/

* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(movtdo): New define_expand and define_insn_and_split to implement 
1,024
bit DMR registers.
(movtdo_insert512_upper): New insn.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr_to_memory): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
support.
(rs6000_init_builtins): Add support for __dmr keyword.
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add 
support
for TDOmode.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-modes.def (TDOmode): New mode.
* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
support for TDOmode.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_hard_regno_mode_ok): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Add support for TDOmode.  Setup 
reload
hooks for DMR mode.
(reg_offset_addressing_ok_p): Add support for TDOmode.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(rs6000_mangle_type): Add mangling for __dmr type.
(rs6000_dmr_register_move_cost): Add support for TDOmode.
(rs6000_split_multireg_move): Likewise.
(rs6000_invalid_conversion): Likewise.
* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
(enum rs6000_builtin_type_index): Add DMR type nodes.
(dmr_type_node): Likewise.
(ptr_dmr_type_node): Likewise.

gcc/testsuite/

* gcc.target/powerpc/dm-1024bit.c: New test.
* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
target test.

Diff:
---
 gcc/config/rs6000/mma.md  | 154 ++
 gcc/config/rs6000/rs6000-builtin.cc   |  17 +++
 gcc/config/rs6000/rs6000-call.cc  |  10 +-
 gcc/config/rs6000/rs6000-modes.def|   4 +
 gcc/config/rs6000/rs6000.cc   | 101 -
 gcc/config/rs6000/rs6000.h|   6 +-
 gcc/testsuite/gcc.target/powerpc/dm-1024bit.c |  63 +++
 gcc/testsuite/lib/target-supports.exp |  35 ++
 8 files changed, 356 insertions(+), 34 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 683d2398ef90..1420fadd4355 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -92,6 +92,11 @@
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
UNSPEC_MMA_DMSETDMRZ
+   UNSPEC_DM_INSERT512_UPPER
+   UNSPEC_DM_INSERT512_LOWER
+   UNSPEC_DM_EXTRACT512
+   UNSPEC_DMR_RELOAD_FROM_MEMORY
+   UNSPEC_DMR_RELOAD_TO_MEMORY
   ])
 
 (define_c_enum "unspecv"
@@ -742,3 +747,152 @@
   " %A0,%x2,%x3,%4,%5,%6"
   [(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
+
+;; TDOmode (__dmr keyword for 1,024 bit registers).
+(define_expand "movtdo"
+  [(set (match_operand:TDO 0 "nonimmediate_operand")
+   (match_operand:

[gcc(refs/users/meissner/heads/work198-paddis)] RFC2686-Add paddis support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d2c3205d161a4e1046afad683160a929ba442a09

commit d2c3205d161a4e1046afad683160a929ba442a09
Author: Michael Meissner 
Date:   Thu Mar 27 21:09:06 2025 -0400

RFC2686-Add paddis support.

2025-03-27  Michael Meissner  

gcc/

* config/rs6000/constraints.md (eU): New constraint.
(eV): Likewise.
* config/rs6000/predicates.md (paddis_operand): New predicate.
(paddis_paddi_operand): Likewise.
(add_operand): Add paddis support.
* config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis 
support.
(num_insns_constant_multi): Likewise.
(print_operand): Add %B for paddis support.
* config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
(SIGNED_INTEGER_32BIT_P): Likewise.
* config/rs6000/rs6000.md (isa attribute): Add paddis support.
(enabled attribute); Likewise.
(add3): Likewise.
(adddi3 splitter): New splitter for paddis.
(movdi_internal64): Add paddis support.
(movdi splitter): New splitter for paddis.

gcc/testsuite/

* gcc.target/powerpc/prefixed-addis.c: New test.

Diff:
---
 gcc/config/rs6000/constraints.md  | 10 +++
 gcc/config/rs6000/predicates.md   | 52 +++-
 gcc/config/rs6000/rs6000.cc   | 25 ++
 gcc/config/rs6000/rs6000.h|  4 +
 gcc/config/rs6000/rs6000.md   | 96 ---
 gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 ++
 6 files changed, 197 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 3da9ed086810..5440becb6e6c 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,6 +222,16 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
+(define_constraint "eU"
+  "@internal integer constant that can be loaded with paddis"
+  (and (match_code "const_int")
+   (match_operand 0 "paddis_operand")))
+
+(define_constraint "eV"
+  "@internal integer constant that can be loaded with paddis + paddi"
+  (and (match_code "const_int")
+   (match_operand 0 "paddis_paddi_operand")))
+
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index c95b4336f062..c206860e4927 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,6 +369,53 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
+;; Return 1 if op is a 64-bit constant that uses the paddis instruction
+(define_predicate "paddis_operand"
+  (match_code "const_int")
+{
+  if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+  /* If addi, addis, or paddi can handle the number, don't return true.  */
+  HOST_WIDE_INT value = INTVAL (op);
+  if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+  /* If the number is too large for padds, return false.  */
+  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
+  if ((value & HOST_WIDE_INT_C(0x)) != 0)
+return false;
+
+  return true;
+})
+
+;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
+;; addi/addis/paddi instruction combination.
+(define_predicate "paddis_paddi_operand"
+  (match_code "const_int")
+{
+  if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+  /* If addi, addis, or paddi can handle the number, don't return true.  */
+  HOST_WIDE_INT value = INTVAL (op);
+  if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+  /* If the number is too large for padds, return false.  */
+  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
+  if ((value & HOST_WIDE_INT_C(0x)) == 0)
+return false;
+
+  return true;
+})
+
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1113,7 +1160,10 @@
   (if_then_else (match_code "const_int")
 (match_test "satisfies_constraint_I (op)
 || satisfies_constraint_L (op)
-|| satisfies_constraint_eI (op)")
+|| satisfies_constraint_eI (op)
+|| satisfies_constraint_eU (op)
+|| satisfies_constraint_eV (op)")
+
 (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d5564ab090a4..ef46a8011000 100644
--- a/gcc/con

[gcc(refs/users/meissner/heads/work198-paddis)] RFC2677-Add xvrlw support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:07889dd13574181bb74477c8d43f7bb4f2a7a13f

commit 07889dd13574181bb74477c8d43f7bb4f2a7a13f
Author: Michael Meissner 
Date:   Thu Mar 27 21:09:59 2025 -0400

RFC2677-Add xvrlw support.

2025-03-27  Michael Meissner  

gcc/

* config/rs6000/altivec.md (xvrlw): New insn.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.

gcc/testsuite/

* gcc.target/powerpc/vector-rotate-left.c: New test.

Diff:
---
 gcc/config/rs6000/altivec.md   | 14 +
 gcc/config/rs6000/rs6000.h |  3 ++
 .../gcc.target/powerpc/vector-rotate-left.c| 34 ++
 3 files changed, 51 insertions(+)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7edc288a6565..d158cf479d60 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,6 +1982,20 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; -mcpu=future adds a vector rotate left word variant.  There is no vector
+;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*xvrlw"
+  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+   (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+(match_operand:V4SI 2 "register_operand" "v,wa")))]
+  "TARGET_XVRLW"
+  "@
+   vrlw %0,%1,%2
+   xvrlw %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "altivec_vrl"
   [(set (match_operand:VI2 0 "register_operand" "=v")
 (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 1267169de509..76f1f87290f3 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -584,6 +584,9 @@ extern int rs6000_vector_align[];
 /* Whether we have PADDIS support.  */
 #define TARGET_PADDIS  TARGET_FUTURE
 
+/* Whether we have XVRLW support.  */
+#define TARGET_XVRLW   TARGET_FUTURE
+
 /* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c 
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
new file mode 100644
index ..5a5f37755077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the xvrl (vector word rotate left using VSX registers insead of
+   Altivec registers is generated.  */
+
+#include 
+
+typedef vector unsigned int  v4si_t;
+
+v4si_t
+rotl_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x << n) | (x >> (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotr_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x >> n) | (x << (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotl_v4si_vector (v4si_t x, v4si_t y)
+{
+  __asm__ (" # %x0" : "+f" (x));   /* xvrlw.  */
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvrlw\M} 3  } } */

[gcc(refs/users/meissner/heads/work198-paddis)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:47a36f33f1c733095c3bd7ef60dfb21725967658

commit 47a36f33f1c733095c3bd7ef60dfb21725967658
Author: Michael Meissner 
Date:   Thu Mar 27 21:11:41 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.paddis | 44 
 1 file changed, 44 insertions(+)

diff --git a/gcc/ChangeLog.paddis b/gcc/ChangeLog.paddis
index 57222325a8b1..2cb83fa01731 100644
--- a/gcc/ChangeLog.paddis
+++ b/gcc/ChangeLog.paddis
@@ -1,3 +1,47 @@
+ Branch work198-paddis, patch #311 
+
+RFC2677-Add xvrlw support.
+
+2025-03-27  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/altivec.md (xvrlw): New insn.
+   * config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/vector-rotate-left.c: New test.
+
+ Branch work198-paddis, patch #310 
+
+RFC2686-Add paddis support.
+
+2025-03-27  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/constraints.md (eU): New constraint.
+   (eV): Likewise.
+   * config/rs6000/predicates.md (paddis_operand): New predicate.
+   (paddis_paddi_operand): Likewise.
+   (add_operand): Add paddis support.
+   * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support.
+   (num_insns_constant_multi): Likewise.
+   (print_operand): Add %B for paddis support.
+   * config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
+   (SIGNED_INTEGER_32BIT_P): Likewise.
+   * config/rs6000/rs6000.md (isa attribute): Add paddis support.
+   (enabled attribute); Likewise.
+   (add3): Likewise.
+   (adddi3 splitter): New splitter for paddis.
+   (movdi_internal64): Add paddis support.
+   (movdi splitter): New splitter for paddis.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/prefixed-addis.c: New test.
+
  Branch work198-paddis, patch #301 
 
 RFC2655-Add saturating subtract built-ins.

[gcc r15-8350] gccrs: Perform type check on InlineAsm's operand

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:29c6aba1d8dc925a0f43b68928004344ea212987

commit r15-8350-g29c6aba1d8dc925a0f43b68928004344ea212987
Author: badumbatish 
Date:   Thu Aug 1 16:18:38 2024 -0700

gccrs: Perform type check on InlineAsm's operand

gcc/rust/ChangeLog:

* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit):
Perform type check on InlineAsm's operand
(typecheck_inline_asm_operand): Likewise

Diff:
---
 gcc/rust/typecheck/rust-hir-type-check-expr.cc | 65 --
 1 file changed, 60 insertions(+), 5 deletions(-)

diff --git a/gcc/rust/typecheck/rust-hir-type-check-expr.cc 
b/gcc/rust/typecheck/rust-hir-type-check-expr.cc
index 1197916d1f5d..a9255fc69f2a 100644
--- a/gcc/rust/typecheck/rust-hir-type-check-expr.cc
+++ b/gcc/rust/typecheck/rust-hir-type-check-expr.cc
@@ -623,9 +623,10 @@ TypeCheckExpr::visit (HIR::BlockExpr &expr)
  && (((TyTy::InferType *) loop_context_type)->get_infer_kind ()
  != TyTy::InferType::GENERAL));
 
-  infered = loop_context_type_infered ? loop_context_type
- : TyTy::TupleType::get_unit_type (
-   expr.get_mappings ().get_hirid ());
+  infered = loop_context_type_infered
+ ? loop_context_type
+ : TyTy::TupleType::get_unit_type (
+ expr.get_mappings ().get_hirid ());
 }
   else
 {
@@ -775,9 +776,63 @@ TypeCheckExpr::visit (HIR::RangeToExpr &expr)
   infered = SubstMapperInternal::Resolve (adt, subst);
 }
 
+void
+typecheck_inline_asm_operand (HIR::InlineAsm &expr)
+{
+  const auto &operands = expr.get_operands ();
+  using RegisterType = AST::InlineAsmOperand::RegisterType;
+  for (auto &operand : operands)
+{
+  switch (operand.get_register_type ())
+   {
+ case RegisterType::In: {
+   auto in = operand.get_in ();
+   TypeCheckExpr::Resolve (in.expr.get ());
+   break;
+ }
+ case RegisterType::Out: {
+   auto out = operand.get_out ();
+   TypeCheckExpr::Resolve (out.expr.get ());
+   break;
+ }
+ case RegisterType::InOut: {
+   auto in_out = operand.get_in_out ();
+   TypeCheckExpr::Resolve (in_out.expr.get ());
+   break;
+ }
+ case RegisterType::SplitInOut: {
+   auto split_in_out = operand.get_split_in_out ();
+   TypeCheckExpr::Resolve (split_in_out.in_expr.get ());
+   TypeCheckExpr::Resolve (split_in_out.out_expr.get ());
+   break;
+ }
+ case RegisterType::Const: {
+   auto anon_const = operand.get_const ().anon_const;
+   TypeCheckExpr::Resolve (anon_const.expr.get ());
+   break;
+ }
+ case RegisterType::Sym: {
+   auto sym = operand.get_sym ();
+   TypeCheckExpr::Resolve (sym.expr.get ());
+   break;
+ }
+ case RegisterType::Label: {
+   auto label = operand.get_label ();
+   TypeCheckExpr::Resolve (label.expr.get ());
+   break;
+ }
+   }
+}
+}
 void
 TypeCheckExpr::visit (HIR::InlineAsm &expr)
-{}
+{
+  typecheck_inline_asm_operand (expr);
+
+  // TODO: Hoise out if we have noreturn as an option
+  // to return a never type
+  infered = TyTy::TupleType::get_unit_type (expr.get_mappings ().get_hirid ());
+}
 
 void
 TypeCheckExpr::visit (HIR::RangeFullExpr &expr)
@@ -1570,7 +1625,7 @@ TypeCheckExpr::visit (HIR::ClosureExpr &expr)
   TyTy::TyVar result_type
 = expr.has_return_type ()
? TyTy::TyVar (
- TypeCheckType::Resolve (expr.get_return_type ().get ())->get_ref ())
+   TypeCheckType::Resolve (expr.get_return_type ().get ())->get_ref ())
: TyTy::TyVar::get_implicit_infer_var (expr.get_locus ());
 
   // resolve the block

[gcc(refs/users/meissner/heads/work198-bugs)] PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c29cabbcae9a9e0df2501771777b8cc2d6d94f56

commit c29cabbcae9a9e0df2501771777b8cc2d6d94f56
Author: Michael Meissner 
Date:   Thu Mar 27 20:33:13 2025 -0400

PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode

Previously GCC would zero externd a DImode GPR value to TImode by first zero
extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
move this value to a VSX register.

This patch does the move directly, since if the middle argument to MTVSRDD 
is 0,
it does the zero extend.

If the DImode value is already in a vector register, it does a XXSPLTIB and
XXPERMDI to get the value into the bottom 64-bits of the register.

I have built GCC with the patches in this patch set applied on both little 
and
big endian PowerPC systems and there were no regressions.  Can I apply this
patch to GCC 15?

2025-03-27  Michael Meissner  

gcc/

PR target/108598
* gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.

gcc/testsuite/

PR target/108598
* gcc.target/powerpc/pr108958.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000.md | 46 +
 gcc/testsuite/gcc.target/powerpc/pr108958.c | 27 +
 2 files changed, 73 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 22e8cdde1e0a..e4ab95e5a580 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1026,6 +1026,52 @@
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
 
+(define_insn_and_split "zero_extendditi2"
+  [(set (match_operand:TI 0 "gpc_reg_operand" "=r,wa,&wa")
+   (zero_extend:TI
+(match_operand:DI 1 "gpc_reg_operand" "rwa,r,wa")))]
+  "TARGET_P9_VECTOR && TARGET_POWERPC64"
+  "@
+  #
+  mtvsrdd %x0,0,%1
+  #"
+  "&& reload_completed
+   && (int_reg_operand (operands[0], TImode)
+   || vsx_register_operand (operands[1], DImode))"
+  [(set (match_dup 2)
+   (match_dup 3))
+   (set (match_dup 4)
+   (match_dup 5))]
+{
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  int r = reg_or_subregno (op0);
+
+  if (int_reg_operand (op0, TImode))
+{
+  int lo = BYTES_BIG_ENDIAN ? 1 : 0;
+  int hi = 1 - lo;
+
+  operands[2] = gen_rtx_REG (DImode, r + lo);
+  operands[3] = op1;
+  operands[4] = gen_rtx_REG (DImode, r + hi);
+  operands[5] = const0_rtx;
+}
+  else
+{
+  rtx op0_di = gen_rtx_REG (DImode, r);
+  rtx op0_v2di = gen_rtx_REG (V2DImode, r);
+  rtx lo = WORDS_BIG_ENDIAN ? op1 : op0_di;
+  rtx hi = WORDS_BIG_ENDIAN ? op0_di : op1;
+
+  operands[2] = op0_v2di;
+  operands[3] = CONST0_RTX (V2DImode);
+  operands[4] = op0_v2di;
+  operands[5] = gen_rtx_VEC_CONCAT (V2DImode, hi, lo);
+}
+}
+  [(set_attr "type" "*,mtvsr,vecperm")
+   (set_attr "length" "8,*,8")])
 
 (define_insn "extendqi2"
   [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108958.c 
b/gcc/testsuite/gcc.target/powerpc/pr108958.c
new file mode 100644
index ..03eb58d069e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr108958.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
+
+/* PR target/108958, use mtvsrdd to zero extend gpr to vsx register.  */
+
+void
+gpr_to_vsx (unsigned long long x, __uint128_t *p)
+{
+  /* mtvsrdd vsx,0,gpr.  */
+  __uint128_t y = x;
+  __asm__ (" # %x0" : "+wa" (y));
+  *p = y;
+}
+
+void
+gpr_to_gpr (unsigned long long x, __uint128_t *p)
+{
+  /* mr and li.  */
+  __uint128_t y = x;
+  __asm__ (" # %0" : "+r" (y));
+  *p = y;
+}
+
+/* { dg-final { scan-assembler-times {\mli\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mmtvsrdd .*,0,.*\M} 1 } } */

[gcc(refs/users/meissner/heads/work198-paddis)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ea6e839e9a3a3730708a3696d8e2aebaa090d7b3

commit ea6e839e9a3a3730708a3696d8e2aebaa090d7b3
Author: Michael Meissner 
Date:   Thu Mar 27 21:02:58 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.dmf | 111 --
 1 file changed, 8 insertions(+), 103 deletions(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
index 145e927a7a35..eae8125e775a 100644
--- a/gcc/ChangeLog.dmf
+++ b/gcc/ChangeLog.dmf
@@ -1,99 +1,4 @@
- Branch work196-dmf, patch #121 was reverted 

- Branch work196-dmf, patch #120 was reverted 

-
- Branch work196-dmf, patch #111 
-
-RFC2655-Add saturating subtract built-ins.
-
-This patch adds support for a saturating subtract built-in function that may be
-added to a future PowerPC processor.  Note, if it is added, the name of the
-built-in function may change before GCC 13 is released.  If the name changes,
-we will submit a patch changing the name.
-
-I also added support for providing dense math built-in functions, even though
-at present, we have not added any new built-in functions for dense math.  It is
-likely we will want to add new dense math built-in functions as the dense math
-support is fleshed out.
-
-The patches have been tested on both little and big endian systems.  Can I 
check
-it into the master branch?
-
-2025-03-08   Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support
-   for flagging invalid use of future built-in functions.
-   (rs6000_builtin_is_supported): Add support for future built-in
-   functions.
-   * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New
-   built-in function for -mcpu=future.
-   (__builtin_saturate_subtract64): Likewise.
-   * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas
-   for -mcpu=future built-ins.
-   (stanza_map): Likewise.
-   (enable_string): Likewise.
-   (struct attrinfo): Likewise.
-   (parse_bif_attrs): Likewise.
-   (write_decls): Likewise.
-   * config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
-   built-in insn declarations.
-   (sat_sub3_dot): Likewise.
-   (sat_sub3_dot2): Likewise.
-   * doc/extend.texi (Future PowerPC built-ins): New section.
-
-gcc/testsuite/
-
-   * gcc.target/powerpc/subfus-1.c: New test.
-   * gcc.target/powerpc/subfus-2.c: Likewise.
-
- Branch work196-dmf, patch #110 
-
-RFC2656-Support load/store vector with right length.
-
-This patch adds support for new instructions that may be added to the PowerPC
-architecture in the future to enhance the load and store vector with length
-instructions.
-
-The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use
-since the count for the number of bytes must be in the top 8 bits of the GPR
-register, instead of the bottom 8 bits.  This meant that code generating these
-instructions typically had to do a shift left by 56 bits to get the count into
-the right position.  In a future version of the PowerPC architecture, new
-variants of these instructions might be added that expect the count to be in
-the bottom 8 bits of the GPR register.  These patches add this support to GCC
-if the user uses the -mcpu=future option.
-
-I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl
-future lxvll/stxvll instructions would generate these instructions on 32-bit.
-However the patterns for these instructions is only done on 64-bit systems.  So
-I added a check for 64-bit support before generating the instructions.
-
-The patches have been tested on both little and big endian systems.  Can I 
check
-it into the master branch?
-
-2025-03-08   Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-string.cc (expand_block_move): Do not generate
-   lxvl and stxvl on 32-bit.
-   * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with
-   the shift count automaticaly used in the insn.
-   (lxvrl): New insn for -mcpu=future.
-   (lxvrll): Likewise.
-   (stxvl): If -mcpu=future, generate the stxvl with the shift count
-   automaticaly used in the insn.
-   (stxvrl): New insn for -mcpu=future.
-   (stxvrll): Likewise.
-
-gcc/testsuite/
-
-   * gcc.target/powerpc/lxvrl.c: New test.
-   * lib/target-supports.exp (check_effective_target_powerpc_future_ok):
-   New effective target.
-
- Branch work196-dmf, patch #102 
+ Branch work198-dmf, patch #102 
 
 RFC2653-PowerPC: Add support for 1,024 bit DMR registers.
 
@@ -167,7 +72,7 @@ gcc/testsuite/
* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
target test.
 
- Branch work19

[gcc] Created branch 'meissner/heads/work196-libs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-libs' was created in namespace 'refs/users' 
pointing to:

 bc61a0720b30... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work198-vpair)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a48c0437d5c6b90ec6be5203a8aaad48a88d83a3

commit a48c0437d5c6b90ec6be5203a8aaad48a88d83a3
Author: Michael Meissner 
Date:   Thu Mar 27 21:20:13 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.vpair | 420 
 1 file changed, 420 insertions(+)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
index da61dc2ec8af..c01d76e81005 100644
--- a/gcc/ChangeLog.vpair
+++ b/gcc/ChangeLog.vpair
@@ -1,5 +1,425 @@
+ Branch work198-vpair, patch #500 
+
+Vector pair support.
+
+This patch adds a new include file (vector-pair.h) that adds support so that
+users writing high performance libraries can change their code to allow the
+generation of the vector pair load and store instructions on power10.
+
+The intention is that if the library authors need to write special loops that
+go over arrays that they could modify their code to use the functions provided
+to change loops that can take advantage of the higher bandwidth for load vector
+pair and store instructions.
+
+This particular patch just adds a new include file (vector-pair.h) that
+provides a bunch of functions that on a power10 system would use the vector
+pair load operation, 2 floating point operations, and a vector pair store.  It
+does not add any new types, modes, or built-in function.
+
+I have additional patches that can add built-in functions that the functions in
+vector-pair.h could utilize so that the compiler can optimize and combine
+operations.  I may submit those patches in the future, but I would like to
+provide this patch to allow the library writer to optimize their code.
+
+I've measured the performance of these new functions on a power10.  For default
+unrolling, the percentage of change for the 3 methods over the normal vector
+loop method:
+
+   116%Vector-pair.h function, default unroll
+93%Vector pair split built-in & 2 vector stores, default unroll
+86%Vector pair split & combine built-ins, default unroll
+
+Using explicit 2 way unrolling the numbers are:
+
+   114%Vector-pair.h function, unroll 2
+   106%Vector pair split built-in & 2 vector stores, unroll 2
+98%Vector pair split & combine built-ins, unroll 2
+
+These new functions provided in vector-pair.h use the vector pair load/store
+instructions, and don't generate extra vector moves.  Using the existing
+vector pair disassemble and assemble built-ins generate extra vector moves
+which can hinder performance.
+
+If I compile the loop code for power9, there is a minor speed up for default
+unrolling and more of an improvement using the framework provided in the
+vector-pair.h for explicit unrolling by 2:
+
+   101%Vector-pair.h function, default unroll for power9
+   107%Vector-pair.h function, unroll 2 for power9
+
+Of course this is a synthetic benchmark run on a quiet power10 system.  Results
+would vary for real code on real systems.  However, I feel adding these
+functions can allow the writers of high performance libraries to better
+optimize their code.
+
+As an example, if the library wants to code a simple fused multiply-add loop,
+they might write the code as follows:
+
+   #include 
+   #include 
+   #include 
+
+   void
+   fma_vector (double * __restrict__ r,
+   const double * __restrict__ a,
+   const double * __restrict__ b,
+   size_t n)
+   {
+ vector double * __restrict__ vr = (vector double * __restrict__)r;
+ const vector double * __restrict__ va = (const vector double * 
__restrict__)a;
+ const vector double * __restrict__ vb = (const vector double * 
__restrict__)b;
+ size_t num_elements = sizeof (vector double) / sizeof (double);
+ size_t nv = n / num_elements;
+ size_t i;
+
+ for (i = 0; i < nv; i++)
+   vr[i] = __builtin_vsx_xvmadddp (va[i], vb[i], vr[i]);
+
+ for (i = nv * num_elements; i < n; i++)
+   r[i] = fma (a[i], b[i], r[i]);
+   }
+
+The inner loop would look like:
+
+   .L3:
+   lxvx 0,3,9
+   lxvx 12,4,9
+   addi 10,9,16
+   addi 2,2,-2
+   lxvx 11,5,9
+   xvmaddadp 0,12,11
+   lxvx 12,4,10
+   lxvx 11,5,10
+   stxvx 0,3,9
+   lxvx 0,3,10
+   addi 9,9,32
+   xvmaddadp 0,12,11
+   stxvx 0,3,10
+   bdnz .L3
+
+Now if you code the loop to use __builtin_vsx_disassemble_pair to do a vector
+pair load, but then do 2 vector stores:
+
+
+   #include 
+   #include 
+   #include 
+
+   void
+   fma_mma_ld (double * __restrict__ r,
+   const double * __restrict__ a,
+   const double * __restrict__ b,
+   size_t n)
+   {
+ __vector_pair * __restrict__ vp_r

[gcc(refs/users/meissner/heads/work198-sha)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0cf8cce59f3677cb7d8bd0fbc07ee2f1199ef6fb

commit 0cf8cce59f3677cb7d8bd0fbc07ee2f1199ef6fb
Author: Michael Meissner 
Date:   Thu Mar 27 21:16:20 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.sha | 168 ++
 1 file changed, 168 insertions(+)

diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha
index 365713781db6..79d76e056089 100644
--- a/gcc/ChangeLog.sha
+++ b/gcc/ChangeLog.sha
@@ -1,5 +1,173 @@
+ Branch work198-sha, patch #401 
+
+Add potential p-future XVRLD and XVRLDI instructions.
+
+2025-03-27  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/altivec.md (altivec_vrl): Add support for a
+   possible XVRLD instruction in the future.
+   (altivec_vrl_immediate): New insns.
+   * config/rs6000/predicates.md (vector_shift_immediate): New predicate.
+   * config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
+   * config/rs6000/rs6000.md (isa attribute): Add xvrlw.
+   (enabled attribute): Add support for xvrlw.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/vector-rotate-left.c: New test.
+   * lib/target-supports.exp (check_effective_target_powerpc_future_ok):
+   Add support to test -mcpu=future.
+
+ Branch work198-sha, patch #400 
+
+PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations
+
+The multibuff.c benchmark attached to the PR target/117251 compiled for Power10
+PowerPC that implement SHA3 has a slowdown in the current trunk and GCC 14
+compared to GCC 11 - GCC 13, due to excessive amounts of spilling.
+
+The main function for the multibuf.c file has 3,747 lines, all of which are
+using vector unsigned long long.  There are 696 vector rotates (all rotates are
+constant), 1,824 vector xor's and 600 vector andc's.
+
+In looking at it, the main thing that steps out is the reason for either
+spilling or moving variables is the support in fusion.md (generated by
+genfusion.pl) that tries to fuse the vec_andc feeding into vec_xor, and other
+vec_xor's feeding into vec_xor.
+
+On the powerpc for power10, there is a special fusion mode that happens if the
+machine has a VANDC or VXOR instruction that is adjacent to a VXOR instruction
+and the VANDC/VXOR feeds into the 2nd VXOR instruction.
+
+While the Power10 has 64 vector registers (which uses the XXL prefix to do
+logical operations), the fusion only works with the older Altivec instruction
+set (which uses the V prefix).  The Altivec instruction only has 32 vector
+registers (which are overlaid over the VSX vector registers 32-63).
+
+By having the combiner patterns fuse_vandc_vxor and fuse_vxor_vxor to do this
+fusion, it means that the register allocator has more register pressure for the
+traditional Altivec registers instead of the VSX registers.
+
+In addition, since there are vector rotates, these rotates only work on the
+traditional Altivec registers, which adds to the Altivec register pressure.
+
+Finally in addition to doing the explicit xor, andc, and rotates using the
+Altivec registers, we have to also load vector constants for the rotate amount
+and these registers also are allocated as Altivec registers.
+
+Current trunk and GCC 12-14 have more vector spills than GCC 11, but GCC 11 has
+many more vector moves that the later compilers.  Thus even though it has way
+less spills, the vector moves are why GCC 11 have the slowest results.
+
+There is an instruction that was added in power10 (XXEVAL) that does provide
+fusion between VSX vectors that includes ANDC->XOR and XOR->XOR fusion.
+
+The latency of XXEVAL is slightly more than the fused VANDC/VXOR or VXOR/VXOR,
+so I have written the patch to prefer doing the Altivec instructions if they
+don't need a temporary register.
+
+Here are the results for adding support for XXEVAL for the multibuff.c
+benchmark attached to the PR.  Note that we essentially recover the speed with
+this patch that were lost with GCC 14 and the current trunk:
+
+  XXEVALTrunk   GCC14   GCC13   GCC12GCC11
+  ---   -   -   --
+Benchmark time in seconds   5.53 6.156.265.575.61 9.56
+
+Fuse VANDC -> VXOR   209 600  600 600 600  600
+Fuse VXOR -> VXOR  0 240  240 120 120  120
+XXEVAL to fuse ANDC -> XOR   391   00   0   00
+XXEVAL to fuse XOR -> XOR240   00   0   00
+
+Spill vector to stack 78 364  364 172 184  110
+Load spilled vector from stack   431 962  962 713 723  166
+Vector moves  10 100  100  70  723,055
+
+Vector rotate right  696 696  696 696 696  696
+XXLANDC or VANDC 209 600  600 600 

[gcc(refs/users/meissner/heads/work198-vpair)] Vector pair support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5d726d2ce79cdde877d870ea739631d1aab6be52

commit 5d726d2ce79cdde877d870ea739631d1aab6be52
Author: Michael Meissner 
Date:   Thu Mar 27 21:17:59 2025 -0400

Vector pair support.

This patch adds a new include file (vector-pair.h) that adds support so that
users writing high performance libraries can change their code to allow the
generation of the vector pair load and store instructions on power10.

The intention is that if the library authors need to write special loops 
that
go over arrays that they could modify their code to use the functions 
provided
to change loops that can take advantage of the higher bandwidth for load 
vector
pair and store instructions.

This particular patch just adds a new include file (vector-pair.h) that
provides a bunch of functions that on a power10 system would use the vector
pair load operation, 2 floating point operations, and a vector pair store.  
It
does not add any new types, modes, or built-in function.

I have additional patches that can add built-in functions that the 
functions in
vector-pair.h could utilize so that the compiler can optimize and combine
operations.  I may submit those patches in the future, but I would like to
provide this patch to allow the library writer to optimize their code.

I've measured the performance of these new functions on a power10.  For 
default
unrolling, the percentage of change for the 3 methods over the normal vector
loop method:

116%Vector-pair.h function, default unroll
 93%Vector pair split built-in & 2 vector stores, default unroll
 86%Vector pair split & combine built-ins, default unroll

Using explicit 2 way unrolling the numbers are:

114%Vector-pair.h function, unroll 2
106%Vector pair split built-in & 2 vector stores, unroll 2
 98%Vector pair split & combine built-ins, unroll 2

These new functions provided in vector-pair.h use the vector pair load/store
instructions, and don't generate extra vector moves.  Using the existing
vector pair disassemble and assemble built-ins generate extra vector moves
which can hinder performance.

If I compile the loop code for power9, there is a minor speed up for default
unrolling and more of an improvement using the framework provided in the
vector-pair.h for explicit unrolling by 2:

101%Vector-pair.h function, default unroll for power9
107%Vector-pair.h function, unroll 2 for power9

Of course this is a synthetic benchmark run on a quiet power10 system.  
Results
would vary for real code on real systems.  However, I feel adding these
functions can allow the writers of high performance libraries to better
optimize their code.

As an example, if the library wants to code a simple fused multiply-add 
loop,
they might write the code as follows:

#include 
#include 
#include 

void
fma_vector (double * __restrict__ r,
const double * __restrict__ a,
const double * __restrict__ b,
size_t n)
{
  vector double * __restrict__ vr = (vector double * __restrict__)r;
  const vector double * __restrict__ va = (const vector double * 
__restrict__)a;
  const vector double * __restrict__ vb = (const vector double * 
__restrict__)b;
  size_t num_elements = sizeof (vector double) / sizeof (double);
  size_t nv = n / num_elements;
  size_t i;

  for (i = 0; i < nv; i++)
vr[i] = __builtin_vsx_xvmadddp (va[i], vb[i], vr[i]);

  for (i = nv * num_elements; i < n; i++)
r[i] = fma (a[i], b[i], r[i]);
}

The inner loop would look like:

.L3:
lxvx 0,3,9
lxvx 12,4,9
addi 10,9,16
addi 2,2,-2
lxvx 11,5,9
xvmaddadp 0,12,11
lxvx 12,4,10
lxvx 11,5,10
stxvx 0,3,9
lxvx 0,3,10
addi 9,9,32
xvmaddadp 0,12,11
stxvx 0,3,10
bdnz .L3

Now if you code the loop to use __builtin_vsx_disassemble_pair to do a 
vector
pair load, but then do 2 vector stores:

#include 
#include 
#include 

void
fma_mma_ld (double * __restrict__ r,
const double * __restrict__ a,
const double * __restrict__ b,
size_t n)
{
  __vector_pair * __restrict__ vp_r

[gcc(refs/users/meissner/heads/work198-dmf)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8fae9b6f3acc5b92ca0ffad85579d8b863df47f1

commit 8fae9b6f3acc5b92ca0ffad85579d8b863df47f1
Author: Michael Meissner 
Date:   Thu Mar 27 20:55:11 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.dmf | 234 ++
 1 file changed, 234 insertions(+)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
index 70118273928d..eae8125e775a 100644
--- a/gcc/ChangeLog.dmf
+++ b/gcc/ChangeLog.dmf
@@ -1,5 +1,239 @@
+ Branch work198-dmf, patch #102 
+
+RFC2653-PowerPC: Add support for 1,024 bit DMR registers.
+
+This patch is a prelimianry patch to add the full 1,024 bit dense math register
+(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of the
+DMR register.
+
+This patch only adds the new 1,024 bit register support.  It does not add
+support for any instructions that need 1,024 bit registers instead of 512 bit
+registers.
+
+I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
+registers.  The 'wD' constraint added in previous patches is used for these
+registers.  I added support to do load and store of DMRs via the VSX registers,
+since there are no load/store dense math instructions.  I added the new keyword
+'__dmr' to create 1,024 bit types that can be loaded into DMRs.  At present, I
+don't have aliases for __dmr512 and __dmr1024 that we've discussed internally.
+
+The patches have been tested on both little and big endian systems.  Can I 
check
+it into the master branch?
+
+2025-03-08   Michael Meissner  
+
+gcc/
+
+   * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
+   (UNSPEC_DM_INSERT512_LOWER): Likewise.
+   (UNSPEC_DM_EXTRACT512): Likewise.
+   (UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
+   (UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
+   (movtdo): New define_expand and define_insn_and_split to implement 1,024
+   bit DMR registers.
+   (movtdo_insert512_upper): New insn.
+   (movtdo_insert512_lower): Likewise.
+   (movtdo_extract512): Likewise.
+   (reload_dmr_from_memory): Likewise.
+   (reload_dmr_to_memory): Likewise.
+   * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
+   support.
+   (rs6000_init_builtins): Add support for __dmr keyword.
+   * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support
+   for TDOmode.
+   (rs6000_function_arg): Likewise.
+   * config/rs6000/rs6000-modes.def (TDOmode): New mode.
+   * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
+   support for TDOmode.
+   (rs6000_hard_regno_mode_ok_uncached): Likewise.
+   (rs6000_hard_regno_mode_ok): Likewise.
+   (rs6000_modes_tieable_p): Likewise.
+   (rs6000_debug_reg_global): Likewise.
+   (rs6000_setup_reg_addr_masks): Likewise.
+   (rs6000_init_hard_regno_mode_ok): Add support for TDOmode.  Setup reload
+   hooks for DMR mode.
+   (reg_offset_addressing_ok_p): Add support for TDOmode.
+   (rs6000_emit_move): Likewise.
+   (rs6000_secondary_reload_simple_move): Likewise.
+   (rs6000_preferred_reload_class): Likewise.
+   (rs6000_secondary_reload_class): Likewise.
+   (rs6000_mangle_type): Add mangling for __dmr type.
+   (rs6000_dmr_register_move_cost): Add support for TDOmode.
+   (rs6000_split_multireg_move): Likewise.
+   (rs6000_invalid_conversion): Likewise.
+   * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
+   (enum rs6000_builtin_type_index): Add DMR type nodes.
+   (dmr_type_node): Likewise.
+   (ptr_dmr_type_node): Likewise.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/dm-1024bit.c: New test.
+   * lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
+   target test.
+
+ Branch work198-dmf, patch #101 
+
+RFC2653-Add support for dense math registers.
+
+The MMA subsystem added the notion of accumulator registers as an optional
+feature of ISA 3.1 (power10).  In ISA 3.1, these accumulators overlapped with
+the VSX registers 0..31, but logically the accumulator registers were separate
+from the FPR registers.  In ISA 3.1, it was anticipated that in future systems,
+the accumulator registers may no overlap with the FPR registers.  This patch
+adds the support for dense math registers as separate registers.
+
+This particular patch does not change the MMA support to use the accumulators
+within the dense math registers.  This patch just adds the basic support for
+having separate DMRs.  The next patch will switch the MMA support to use the
+accumulators if -mcpu=future is used.
+
+For testing purposes, I added an undocumented option '-mdense-math' to enable
+or disable the dense math support.
+
+This patch updates the wD constraint added in the previous patch.  If MMA is
+selected but dense math is not selected (i.e. -mcpu=power10), the wD constraint
+will allow access 

[gcc(refs/users/meissner/heads/work198-dmf)] RFC2653-Add wD constraint.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2e330c72f836d4f2411a1564518e19a5a94d6cd5

commit 2e330c72f836d4f2411a1564518e19a5a94d6cd5
Author: Michael Meissner 
Date:   Thu Mar 27 20:48:50 2025 -0400

RFC2653-Add wD constraint.

This patch adds a new constraint ('wD') that matches the accumulator 
registers
that overlap with VSX registers 0..31 on power10.  Future patches will add 
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.

2025-03-27   Michael Meissner  

* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/mma.md (mma_): Prepare for alternate 
accumulator
registers.  Use wD constraint instead of 'd' constraint.  Use
accumulator_operand instead of fpr_reg_operand.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
   "TARGET_MMA"
   " %A0"
@@ -523,7 +523,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
@@ -532,8 +532,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
@@ -542,7 +542,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
@@ -551,8 +551,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
@@ -561,7 +561,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -574,8 +574,8 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
(match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -588,7 +588,7 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -601,8 +601,8 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
   

[gcc(refs/users/meissner/heads/work198-paddis)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:18032a28b5e7e78d866a121fa105e9d20a7aaee7

commit 18032a28b5e7e78d866a121fa105e9d20a7aaee7
Author: Michael Meissner 
Date:   Thu Mar 27 20:59:29 2025 -0400

RFC2653-PowerPC: Add support for 1,024 bit DMR registers.

This patch is a prelimianry patch to add the full 1,024 bit dense math 
register
(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of 
the
DMR register.

This patch only adds the new 1,024 bit register support.  It does not add
support for any instructions that need 1,024 bit registers instead of 512 
bit
registers.

I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
registers.  The 'wD' constraint added in previous patches is used for these
registers.  I added support to do load and store of DMRs via the VSX 
registers,
since there are no load/store dense math instructions.  I added the new 
keyword
'__dmr' to create 1,024 bit types that can be loaded into DMRs.  At 
present, I
don't have aliases for __dmr512 and __dmr1024 that we've discussed 
internally.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

RFC2653-Add support for dense math registers.

The MMA subsystem added the notion of accumulator registers as an optional
feature of ISA 3.1 (power10).  In ISA 3.1, these accumulators overlapped 
with
the VSX registers 0..31, but logically the accumulator registers were 
separate
from the FPR registers.  In ISA 3.1, it was anticipated that in future 
systems,
the accumulator registers may no overlap with the FPR registers.  This patch
adds the support for dense math registers as separate registers.

This particular patch does not change the MMA support to use the 
accumulators
within the dense math registers.  This patch just adds the basic support for
having separate DMRs.  The next patch will switch the MMA support to use the
accumulators if -mcpu=future is used.

For testing purposes, I added an undocumented option '-mdense-math' to 
enable
or disable the dense math support.

This patch updates the wD constraint added in the previous patch.  If MMA is
selected but dense math is not selected (i.e. -mcpu=power10), the wD 
constraint
will allow access to accumulators that overlap with VSX registers 0..31.  If
both MMA and dense math are selected (i.e. -mcpu=future), the wD constraint
will only allow dense math registers.

This patch modifies the existing %A output modifier.  If MMA is selected but
dense math is not selected, then %A output modifier converts the VSX 
register
number to the accumulator number, by dividing it by 4.  If both MMA and 
dense
math are selected, then %A will map the separate DMR registers into 0..7.

The intention is that user code using extended asm can be modified to run on
both MMA without dense math and MMA with dense math:

1)  If possible, don't use extended asm, but instead use the MMA 
built-in
functions;

2)  If you do need to write extended asm, change the d constraints
targetting accumulators should now use wD;

3)  Only use the built-in zero, assemble and disassemble functions 
create
move data between vector quad types and dense math accumulators.
I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the
extended asm code.  The reason is these instructions assume there 
is a
1-to-1 correspondence between 4 adjacent FPR registers and an
accumulator that overlaps with those instructions.  With 
accumulators
now being separate registers, there no longer is a 1-to-1
correspondence.

It is possible that the mangling for DMRs and the GDB register numbers may
produce other changes in the future.

RFC2653-Add wD constraint.

This patch adds a new constraint ('wD') that matches the accumulator 
registers
that overlap with VSX registers 0..31 on power10.  Future patches will add 
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.

2025-03-27   Michael Meissner  

gcc/

* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(movtdo): New define_expand and define_insn_and_split to implement 
1,024
bit DMR registers.
(movtdo_insert512_upper): New insn.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr

[gcc r15-8523] gccrs: Fix bad handling for recursive type query

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:2992ff08f68e7b9bb36cdeb6747cdc1ee9015d54

commit r15-8523-g2992ff08f68e7b9bb36cdeb6747cdc1ee9015d54
Author: Philip Herron 
Date:   Tue Nov 12 12:16:40 2024 +

gccrs: Fix bad handling for recursive type query

When resolving a type like this which is generic it causes the argument
substitution to go through bounds checking which is expected. But this
can call a type bounds probe which again calls a type query which will be
on the Impl Type on an impl block which can result in a recursive type
query which does eventually get caught and errors correctly. But this then
triggers some old error diagnositcs which are not valid error codes but old
error messages we used to catch simple errors very early on which do not
apply for this senario.

Fixes Rust-GCC#2905

gcc/rust/ChangeLog:

* typecheck/rust-hir-type-check-item.cc 
(TypeCheckItem::resolve_impl_block_substitutions):
dont check for unconstrained when the self is not resolved
* typecheck/rust-hir-type-check-type.cc 
(TypeCheckType::resolve_root_path):
remove bad debug error diagnostic
* typecheck/rust-tyty-subst.cc: likewise

gcc/testsuite/ChangeLog:

* rust/compile/nr2/exclude: nr2 cant handle this
* rust/compile/issue-2905-1.rs: New test.
* rust/compile/issue-2905-2.rs: New test.

Signed-off-by: Philip Herron 

Diff:
---
 gcc/rust/typecheck/rust-hir-type-check-item.cc |   8 ++
 gcc/rust/typecheck/rust-hir-type-check-type.cc |   7 +-
 gcc/rust/typecheck/rust-tyty-subst.cc  |   3 -
 gcc/testsuite/rust/compile/issue-2905-1.rs |  27 +
 gcc/testsuite/rust/compile/issue-2905-2.rs | 136 +
 gcc/testsuite/rust/compile/nr2/exclude |   2 +
 6 files changed, 175 insertions(+), 8 deletions(-)

diff --git a/gcc/rust/typecheck/rust-hir-type-check-item.cc 
b/gcc/rust/typecheck/rust-hir-type-check-item.cc
index 28368d4730a4..0652777c8c62 100644
--- a/gcc/rust/typecheck/rust-hir-type-check-item.cc
+++ b/gcc/rust/typecheck/rust-hir-type-check-item.cc
@@ -724,6 +724,14 @@ TypeCheckItem::resolve_impl_block_substitutions 
(HIR::ImplBlock &impl_block,
 }
 
   TyTy::BaseType *self = TypeCheckType::Resolve (impl_block.get_type ().get 
());
+  if (self->is ())
+{
+  // we cannot check for unconstrained type arguments when the Self type is
+  // not resolved it will just add extra errors that dont help as well as
+  // the case where this could just be a recursive type query that should
+  // fail and will work later on anyway
+  return {substitutions, region_constraints};
+}
 
   // inherit the bounds
   if (!specified_bound.is_error ())
diff --git a/gcc/rust/typecheck/rust-hir-type-check-type.cc 
b/gcc/rust/typecheck/rust-hir-type-check-type.cc
index ee17e53eb306..0ff4ac45247a 100644
--- a/gcc/rust/typecheck/rust-hir-type-check-type.cc
+++ b/gcc/rust/typecheck/rust-hir-type-check-type.cc
@@ -426,11 +426,8 @@ TypeCheckType::resolve_root_path (HIR::TypePath &path, 
size_t *offset,
   if (!query_type (ref, &lookup))
{
  if (is_root)
-   {
- rust_error_at (seg->get_locus (),
-"failed to resolve root segment");
- return new TyTy::ErrorType (path.get_mappings ().get_hirid ());
-   }
+   return new TyTy::ErrorType (path.get_mappings ().get_hirid ());
+
  return root_tyty;
}
 
diff --git a/gcc/rust/typecheck/rust-tyty-subst.cc 
b/gcc/rust/typecheck/rust-tyty-subst.cc
index a3ebf0aa8d55..575f04a3030c 100644
--- a/gcc/rust/typecheck/rust-tyty-subst.cc
+++ b/gcc/rust/typecheck/rust-tyty-subst.cc
@@ -634,8 +634,6 @@ SubstitutionRef::get_mappings_from_generic_args (
  if (resolved == nullptr
  || resolved->get_kind () == TyTy::TypeKind::ERROR)
{
- rust_error_at (binding.get_locus (),
-"failed to resolve type arguments");
  return SubstitutionArgumentMappings::error ();
}
 
@@ -701,7 +699,6 @@ SubstitutionRef::get_mappings_from_generic_args (
   BaseType *resolved = Resolver::TypeCheckType::Resolve (arg.get ());
   if (resolved == nullptr || resolved->get_kind () == 
TyTy::TypeKind::ERROR)
{
- rust_error_at (args.get_locus (), "failed to resolve type arguments");
  return SubstitutionArgumentMappings::error ();
}
 
diff --git a/gcc/testsuite/rust/compile/issue-2905-1.rs 
b/gcc/testsuite/rust/compile/issue-2905-1.rs
new file mode 100644
index ..9b0c19da9bb5
--- /dev/null
+++ b/gcc/testsuite/rust/compile/issue-2905-1.rs
@@ -0,0 +1,27 @@
+#![feature(lang_items)]
+
+#[lang = "sized"]
+trait Sized {}
+
+pub struct A(T);
+
+pub trait B {
+type C;
+}
+
+// --
+// swap these two items
+
+impl B for i32 {
+type C = Weird;
+}
+