date:20241014

[gcc r12-10772] testsuite: fix PR111613 test

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:0e3580191b449e599a4c8d7bfd634df2ca351d4a

commit r12-10772-g0e3580191b449e599a4c8d7bfd634df2ca351d4a
Author: Sam James 
Date:   Mon Jul 29 21:47:16 2024 +0100

testsuite: fix PR111613 test

PR ipa/111613
* gcc.c-torture/pr111613.c: Rename to..
* gcc.c-torture/execute/pr111613.c: ...this.

(cherry picked from commit 5e5d7a88932b132437069f716160f8b20862890b)

Diff:
---
 gcc/testsuite/gcc.c-torture/{ => execute}/pr111613.c | 0
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/gcc/testsuite/gcc.c-torture/pr111613.c 
b/gcc/testsuite/gcc.c-torture/execute/pr111613.c
similarity index 100%
rename from gcc/testsuite/gcc.c-torture/pr111613.c
rename to gcc/testsuite/gcc.c-torture/execute/pr111613.c

[gcc r12-10771] Fix modref's iteraction with store merging

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:65b67169fb1c641a11973988bd439e255d62131a

commit r12-10771-g65b67169fb1c641a11973988bd439e255d62131a
Author: Jan Hubicka 
Date:   Mon Jul 22 19:00:39 2024 +0200

Fix modref's iteraction with store merging

Hi,
this patch fixes wrong code in case store-merging introduces load of 
function
parameter that was previously write-only (which happens for bitfields).
Without this, the whole store-merged area is consdered to be killed.

PR ipa/111613

gcc/ChangeLog:

* ipa-modref.cc (analyze_parms): Do not preserve EAF_NO_DIRECT_READ 
and
EAF_NO_INDIRECT_READ from past flags.

gcc/testsuite/ChangeLog:

* gcc.c-torture/pr111613.c: New test.

(cherry picked from commit 14074773350ffed7efdebbc553adf0f23b572e87)

Diff:
---
 gcc/ipa-modref.cc  |  3 +++
 gcc/testsuite/gcc.c-torture/pr111613.c | 29 +
 2 files changed, 32 insertions(+)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index 1d954954786f..ba7f21834ef9 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -3008,6 +3008,9 @@ analyze_parms (modref_summary *summary, 
modref_summary_lto *summary_lto,
 (past, ecf_flags,
  VOID_TYPE_P (TREE_TYPE
  (TREE_TYPE (current_function_decl;
+ /* Store merging can produce reads when combining together multiple
+bitfields.  See PR111613.  */
+ past &= ~(EAF_NO_DIRECT_READ | EAF_NO_INDIRECT_READ);
  if (dump_file && (flags | past) != flags && !(flags & EAF_UNUSED))
{
  fprintf (dump_file,
diff --git a/gcc/testsuite/gcc.c-torture/pr111613.c 
b/gcc/testsuite/gcc.c-torture/pr111613.c
new file mode 100644
index ..1ea1c4dec072
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/pr111613.c
@@ -0,0 +1,29 @@
+#include 
+#include 
+
+struct bitfield {
+   unsigned int field1 : 1;
+   unsigned int field2 : 1;
+   unsigned int field3 : 1;
+};
+
+__attribute__((noinline)) static void
+set_field1_and_field2(struct bitfield *b) {
+   b->field1 = 1;
+   b->field2 = 1;
+}
+
+__attribute__((noinline)) static struct bitfield *
+new_bitfield(void) {
+   struct bitfield *b = (struct bitfield *)malloc(sizeof(*b));
+   b->field3 = 1;
+   set_field1_and_field2(b);
+   return b;
+}
+
+int main(void) {
+   struct bitfield *b = new_bitfield();
+   if (b->field3 != 1)
+   __builtin_abort ();
+   return 0;
+}

[gcc r15-4341] libstdc++: Implement LWG 3564 for ranges::transform_view

2024-10-14 Thread Jonathan Wakely via Libstdc++-cvs

https://gcc.gnu.org/g:dde19c600c3c8a1d765c9b4961d2556e89edad14

commit r15-4341-gdde19c600c3c8a1d765c9b4961d2556e89edad14
Author: Jonathan Wakely 
Date:   Sun Oct 13 21:47:14 2024 +0100

libstdc++: Implement LWG 3564 for ranges::transform_view

The _Iterator type returned by begin() const uses const F& to
transform the elements, so it should use const F& to determine the
iterator's value_type and iterator_category as well.

This was accepted into the WP in July 2022.

libstdc++-v3/ChangeLog:

* include/std/ranges (transform_view:_Iterator): Use const F&
to determine value_type and iterator_category of
_Iterator, as per LWG 3564.
* testsuite/std/ranges/adaptors/transform.cc: Check value_type
and iterator_category.

Reviewed-by: Patrick Palka 

Diff:
---
 libstdc++-v3/include/std/ranges   |  9 +++--
 .../testsuite/std/ranges/adaptors/transform.cc| 19 +++
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/include/std/ranges b/libstdc++-v3/include/std/ranges
index 6e6e3b97d82f..98442dcfbd51 100644
--- a/libstdc++-v3/include/std/ranges
+++ b/libstdc++-v3/include/std/ranges
@@ -1886,8 +1886,12 @@ namespace views::__adaptor
  static auto
  _S_iter_cat()
  {
+   // _GLIBCXX_RESOLVE_LIB_DEFECTS
+   // 3564. transform_view::iterator::value_type and
+   // iterator_category should use const F&
using _Base = transform_view::_Base<_Const>;
-   using _Res = invoke_result_t<_Fp&, range_reference_t<_Base>>;
+   using _Res = invoke_result_t<__maybe_const_t<_Const, _Fp>&,
+range_reference_t<_Base>>;
if constexpr (is_lvalue_reference_v<_Res>)
  {
using _Cat
@@ -1936,7 +1940,8 @@ namespace views::__adaptor
  using iterator_concept = decltype(_S_iter_concept());
  // iterator_category defined in __transform_view_iter_cat
  using value_type
-   = remove_cvref_t>>;
+   = remove_cvref_t&,
+range_reference_t<_Base>>>;
  using difference_type = range_difference_t<_Base>;
 
  _Iterator() requires default_initializable<_Base_iter> = default;
diff --git a/libstdc++-v3/testsuite/std/ranges/adaptors/transform.cc 
b/libstdc++-v3/testsuite/std/ranges/adaptors/transform.cc
index bcb18a3fc6c8..ca695349650a 100644
--- a/libstdc++-v3/testsuite/std/ranges/adaptors/transform.cc
+++ b/libstdc++-v3/testsuite/std/ranges/adaptors/transform.cc
@@ -196,6 +196,24 @@ test09()
 #endif
 }
 
+void
+test10()
+{
+  struct F {
+short operator()(int) { return 0; }
+const int& operator()(const int& i) const { return i; }
+  };
+
+  int x[] {2, 4};
+  const auto xform = x | views::transform(F{});
+  using const_iterator = decltype(xform.begin());
+  // LWG 3564. transform_view::iterator::value_type and iterator_category
+  // should use const F&
+  static_assert(std::same_as, int>);
+  using cat = std::iterator_traits::iterator_category;
+  static_assert(std::same_as);
+}
+
 int
 main()
 {
@@ -208,4 +226,5 @@ main()
   test07();
   test08();
   test09();
+  test10();
 }

[gcc r15-4343] diagnostics: fix overload of emit_diagnostic [PR117109]

2024-10-14 Thread David Malcolm via Gcc-cvs

https://gcc.gnu.org/g:23e7b702521aa5611060a0b8dd194f3801fc

commit r15-4343-g23e7b702521aa5611060a0b8dd194f3801fc
Author: David Malcolm 
Date:   Mon Oct 14 19:22:46 2024 -0400

diagnostics: fix overload of emit_diagnostic [PR117109]

I accidentally broke "make gcc.pot" in r15-4081 by adding
a member function diagnostic_context::emit_diagnostic with a
gmsgid in a different position to the existing emit_diagnostic
functions, which exgettext's parser can't handle.

Fixed thusly.

gcc/ChangeLog:
PR bootstrap/117109
* diagnostic-format-sarif.cc
(diagnostic_output_format_init_sarif_file): Rename
diagnostic_context::emit_diagnostic to
diagnostic_context::emit_diagnostic_with_group.
* diagnostic.cc (diagnostic_context::emit_diagnostic): Rename
to...
(diagnostic_context::emit_diagnostic_with_group): ...this.
(diagnostic_context::emit_diagnostic_va): Rename to...
(diagnostic_context::emit_diagnostic_with_group_va): ...this.
* diagnostic.h (diagnostic_context::emit_diagnostic): Rename to...
(diagnostic_context::emit_diagnostic_with_group): ...this.
(diagnostic_context::emit_diagnostic_va): Rename to...
(diagnostic_context::emit_diagnostic_with_group_va): ...this.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/diagnostic-format-sarif.cc | 12 +++-
 gcc/diagnostic.cc  | 26 ++
 gcc/diagnostic.h   | 20 ++--
 3 files changed, 31 insertions(+), 27 deletions(-)

diff --git a/gcc/diagnostic-format-sarif.cc b/gcc/diagnostic-format-sarif.cc
index f053dec19205..70832513b6d9 100644
--- a/gcc/diagnostic-format-sarif.cc
+++ b/gcc/diagnostic-format-sarif.cc
@@ -3435,8 +3435,9 @@ diagnostic_output_format_init_sarif_file 
(diagnostic_context &context,
   if (!base_file_name)
 {
   rich_location richloc (line_maps, UNKNOWN_LOCATION);
-  context.emit_diagnostic (DK_ERROR, richloc, nullptr, 0,
-  "unable to determine filename for SARIF output");
+  context.emit_diagnostic_with_group
+   (DK_ERROR, richloc, nullptr, 0,
+"unable to determine filename for SARIF output");
   return;
 }
 
@@ -3447,9 +3448,10 @@ diagnostic_output_format_init_sarif_file 
(diagnostic_context &context,
   if (!outf)
 {
   rich_location richloc (line_maps, UNKNOWN_LOCATION);
-  context.emit_diagnostic (DK_ERROR, richloc, nullptr, 0,
-  "unable to open %qs for SARIF output: %m",
-  filename.get ());
+  context.emit_diagnostic_with_group
+   (DK_ERROR, richloc, nullptr, 0,
+"unable to open %qs for SARIF output: %m",
+filename.get ());
   return;
 }
   diagnostic_output_file output_file (outf, true, std::move (filename));
diff --git a/gcc/diagnostic.cc b/gcc/diagnostic.cc
index 9647e1382dd1..41656a607b81 100644
--- a/gcc/diagnostic.cc
+++ b/gcc/diagnostic.cc
@@ -1160,18 +1160,19 @@ diagnostic_context::warning_enabled_at (location_t loc,
 /* Emit a diagnostic within a diagnostic group on this context.  */
 
 bool
-diagnostic_context::emit_diagnostic (diagnostic_t kind,
-rich_location &richloc,
-const diagnostic_metadata *metadata,
-diagnostic_option_id option_id,
-const char *gmsgid, ...)
+diagnostic_context::
+emit_diagnostic_with_group (diagnostic_t kind,
+   rich_location &richloc,
+   const diagnostic_metadata *metadata,
+   diagnostic_option_id option_id,
+   const char *gmsgid, ...)
 {
   begin_group ();
 
   va_list ap;
   va_start (ap, gmsgid);
-  bool ret = emit_diagnostic_va (kind, richloc, metadata, option_id,
-gmsgid, &ap);
+  bool ret = emit_diagnostic_with_group_va (kind, richloc, metadata, option_id,
+   gmsgid, &ap);
   va_end (ap);
 
   end_group ();
@@ -1182,11 +1183,12 @@ diagnostic_context::emit_diagnostic (diagnostic_t kind,
 /* As above, but taking a va_list *.  */
 
 bool
-diagnostic_context::emit_diagnostic_va (diagnostic_t kind,
-   rich_location &richloc,
-   const diagnostic_metadata *metadata,
-   diagnostic_option_id option_id,
-   const char *gmsgid, va_list *ap)
+diagnostic_context::
+emit_diagnostic_with_group_va (diagnostic_t kind,
+  rich_location &richloc,
+  const diagnostic_metadata *metadata,
+  diagnostic_option_id option_id,
+

[gcc r15-4342] libcpp: avoid extra spaces in module preprocessing

2024-10-14 Thread Jason Merrill via Gcc-cvs

https://gcc.gnu.org/g:2c08ddd3fdd4af794ce66dbabb81ba2e6aee0b7c

commit r15-4342-g2c08ddd3fdd4af794ce66dbabb81ba2e6aee0b7c
Author: Jason Merrill 
Date:   Tue Oct 8 18:26:40 2024 -0400

libcpp: avoid extra spaces in module preprocessing

Within the compiler, module keywords "import", "module", and "export" that
are recognized as part of module directives gain an extra trailing space to
distinguish them from other non-keyword uses of those words in the code.
But when dumping preprocessed output, printing those spaces creates a
gratuitous inconsistency with non-modules preprocessing, as revealed by
several of the g++.dg/modules/cpp* tests if modules are enabled by default
in C++20 mode.

libcpp/ChangeLog:

* lex.cc (cpp_output_token): Omit terminal space from name.

gcc/testsuite/ChangeLog:

* g++.dg/modules/cpp-2_c.C: Expect only one space after import.
* g++.dg/modules/cpp-5_c.C
* g++.dg/modules/dep-2.C
* g++.dg/modules/dir-only-2_b.C
* g++.dg/modules/pr99050_b.C
* g++.dg/modules/inc-xlate-1_b.H
* g++.dg/modules/legacy-3_b.H
* g++.dg/modules/legacy-3_c.H: Likewise.

Diff:
---
 gcc/testsuite/g++.dg/modules/cpp-2_c.C   |  2 +-
 gcc/testsuite/g++.dg/modules/cpp-5_c.C   |  2 +-
 gcc/testsuite/g++.dg/modules/dep-2.C |  2 +-
 gcc/testsuite/g++.dg/modules/dir-only-2_b.C  | 10 +-
 gcc/testsuite/g++.dg/modules/pr99050_b.C |  2 +-
 libcpp/lex.cc|  7 +--
 gcc/testsuite/g++.dg/modules/inc-xlate-1_b.H |  2 +-
 gcc/testsuite/g++.dg/modules/legacy-3_b.H|  2 +-
 gcc/testsuite/g++.dg/modules/legacy-3_c.H|  2 +-
 9 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/gcc/testsuite/g++.dg/modules/cpp-2_c.C 
b/gcc/testsuite/g++.dg/modules/cpp-2_c.C
index c6e02b7800ad..2a79031eb345 100644
--- a/gcc/testsuite/g++.dg/modules/cpp-2_c.C
+++ b/gcc/testsuite/g++.dg/modules/cpp-2_c.C
@@ -11,7 +11,7 @@ import nope;
 #endif
 think
 
-// { dg-final { scan-file cpp-2_c.i {cpp-2_c.C"\n\n\n\nmodule  bob;\n#pragma 
GCC unused\nimport  "[^\n]*\./cpp-2_b.H" \[\[ CLOSE ]];\nimport  
"[^\n]*cpp-2_a.H" \[\[ ]];\n} } }
+// { dg-final { scan-file cpp-2_c.i {cpp-2_c.C"\n\n\n\nmodule bob;\n#pragma 
GCC unused\nimport "[^\n]*\./cpp-2_b.H" \[\[ CLOSE ]];\nimport 
"[^\n]*cpp-2_a.H" \[\[ ]];\n} } }
 // { dg-final { scan-file cpp-2_c.i "int i;" } }
 // { dg-final { scan-file-not cpp-2_c.i "import *nope;" } }
 // { dg-final { scan-file cpp-2_c.i "THIS IS STDIO\n" } }
diff --git a/gcc/testsuite/g++.dg/modules/cpp-5_c.C 
b/gcc/testsuite/g++.dg/modules/cpp-5_c.C
index e0a78a516ae3..7f75a228cda7 100644
--- a/gcc/testsuite/g++.dg/modules/cpp-5_c.C
+++ b/gcc/testsuite/g++.dg/modules/cpp-5_c.C
@@ -7,4 +7,4 @@ import "cpp-5_a.H";
 
 Q
 
-// { dg-final { scan-file cpp-5_c.i {\nimport  "[^\n]*cpp-5_a.H";\n\n0\n} } }
+// { dg-final { scan-file cpp-5_c.i {\nimport "[^\n]*cpp-5_a.H";\n\n0\n} } }
diff --git a/gcc/testsuite/g++.dg/modules/dep-2.C 
b/gcc/testsuite/g++.dg/modules/dep-2.C
index 2dccab3554d0..3c869755785a 100644
--- a/gcc/testsuite/g++.dg/modules/dep-2.C
+++ b/gcc/testsuite/g++.dg/modules/dep-2.C
@@ -9,4 +9,4 @@ module m:part;
 // { dg-final { scan-file dep-2.d {\ngcm.cache/m:part\.gcm:| dep-2\.o} } }
 // { dg-final { scan-file dep-2.d {\n\.PHONY: m:part\.c\+\+-module} } }
 
-// { dg-final { scan-file dep-2.i {\nmodule  m:part;\n} } }
+// { dg-final { scan-file dep-2.i {\nmodule m:part;\n} } }
diff --git a/gcc/testsuite/g++.dg/modules/dir-only-2_b.C 
b/gcc/testsuite/g++.dg/modules/dir-only-2_b.C
index 1009ae5b3a26..b1ef9b95e587 100644
--- a/gcc/testsuite/g++.dg/modules/dir-only-2_b.C
+++ b/gcc/testsuite/g++.dg/modules/dir-only-2_b.C
@@ -21,8 +21,8 @@ export module bob;
 
 export import q;
 
-// { dg-final { scan-file dir-only-2_b.i {// a comment\nmodule ;\nfrob} } }
-// { dg-final { scan-file dir-only-2_b.i {frob\nexport\nimport  foo;\nimport 
7;} } }
-// { dg-final { scan-file dir-only-2_b.i {import  
"[^\n]*/dir-only-2_a.H";\nimport  "[^\n]*/dir-only-2_a.H";\nX} } }
-// { dg-final { scan-file dir-only-2_b.i {export  module  bob;\n\nexport  
import  q;} } }
-// { dg-final { scan-file dir-only-2_b.i {import  sing;\n\n\n// comment} } }
+// { dg-final { scan-file dir-only-2_b.i {// a comment\nmodule;\nfrob} } }
+// { dg-final { scan-file dir-only-2_b.i {frob\nexport\nimport foo;\nimport 
7;} } }
+// { dg-final { scan-file dir-only-2_b.i {import 
"[^\n]*/dir-only-2_a.H";\nimport "[^\n]*/dir-only-2_a.H";\nX} } }
+// { dg-final { scan-file dir-only-2_b.i {export module bob;\n\nexport import 
q;} } }
+// { dg-final { scan-file dir-only-2_b.i {import sing;\n\n\n// comment} } }
diff --git a/gcc/testsuite/g++.dg/modules/pr99050_b.C 
b/gcc/testsuite/g++.dg/modules/pr99050_b.C
index 439e216eb166..f2c956313219 100644
--- a/gcc/testsuite/g++.dg/modules/pr99050_b.C
+++ b/gcc/testsuite/g++.dg/modules/pr99050_b.C
@@ -4,4 +4,4 @@

[gcc r15-4346] libcpp: Add -Wtrailing-blanks warning

2024-10-14 Thread Jakub Jelinek via Gcc-cvs

https://gcc.gnu.org/g:ac615e10471f45031e69bd3eda6795dd8b75e4ad

commit r15-4346-gac615e10471f45031e69bd3eda6795dd8b75e4ad
Author: Jakub Jelinek 
Date:   Tue Oct 15 07:53:56 2024 +0200

libcpp: Add -Wtrailing-blanks warning

Trailing blanks is something even git diff diagnoses; while it is a coding
style issue, if it is so common that git diff diagnoses it, I think it could
be useful to various projects to check that at compile time.

Dunno if it should be included in -Wextra, currently it isn't, and due to
tons of trailing whitespace in our sources, haven't enabled it for when
building gcc itself either.

Note, git diff also diagnoses indentation with tab following space, wonder
if we couldn't have trivial warning options where one would simply ask for
checking of indentation with no tabs, just spaces vs. indentation with
tabs followed by spaces (but never tab width or more spaces in the
indentation).  I think that would be easy to do also on the libcpp side.
Checking how much something should be exactly indented requires syntax
analysis (at least some limited one) and can consider columns of first token
on line, but what the exact indentation blanks were is something only libcpp
knows.

On Thu, Sep 19, 2024 at 08:17:24AM +0200, Richard Biener wrote:
> Generally I like diagnosing this early.  For the above I'd say 
-Wtrailing-whitespace=
> with a set of things to diagnose (and a sane default - just spaces and 
tabs - for
> -Wtrailiing-whitespace) would be nice.  As for naming possibly follow the
> is{space,blank,cntrl} character classifications?  If those are a good
> fit, that is.

The patch currently allows blank (' ' '\t') and space (' ' '\t' '\f' '\v'),
cntrl not yet added, not anything non-ASCII, but in theory could
be added later (though, non-ASCII would be just for inside of comments,
say non-breaking space etc. in the source is otherwise an error).

2024-10-15  Jakub Jelinek  

libcpp/
* include/cpplib.h (struct cpp_options): Add
cpp_warn_trailing_whitespace member.
(enum cpp_warning_reason): Add CPP_W_TRAILING_WHITESPACE.
* internal.h (struct _cpp_line_note): Document 'W' line note.
* lex.cc (_cpp_clean_line): Add 'W' line note for trailing 
whitespace
except for trailing whitespace after backslash.  Formatting fix.
(_cpp_process_line_notes): Emit -Wtrailing-whitespace diagnostics.
Formatting fixes.
(lex_raw_string): Clear type on 'W' notes.
gcc/
* doc/invoke.texi (Wtrailing-whitespace): Document.
gcc/c-family/
* c.opt (Wtrailing-whitespace=): New option.
(Wtrailing-whitespace): New alias.
* c.opt.urls: Regenerate.
gcc/testsuite/
* c-c++-common/cpp/Wtrailing-whitespace-1.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-2.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-3.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-4.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-5.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-6.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-7.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-8.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-9.c: New test.
* c-c++-common/cpp/Wtrailing-whitespace-10.c: New test.

Diff:
---
 gcc/c-family/c.opt | 20 
 gcc/c-family/c.opt.urls|  6 +++
 gcc/doc/invoke.texi| 18 ++-
 .../c-c++-common/cpp/Wtrailing-whitespace-1.c  | 37 ++
 .../c-c++-common/cpp/Wtrailing-whitespace-10.c | 29 +++
 .../c-c++-common/cpp/Wtrailing-whitespace-2.c  | 37 ++
 .../c-c++-common/cpp/Wtrailing-whitespace-3.c  | 43 +
 .../c-c++-common/cpp/Wtrailing-whitespace-4.c  | 28 +++
 .../c-c++-common/cpp/Wtrailing-whitespace-5.c  | 28 +++
 .../c-c++-common/cpp/Wtrailing-whitespace-6.c  | 38 +++
 .../c-c++-common/cpp/Wtrailing-whitespace-7.c  | 38 +++
 .../c-c++-common/cpp/Wtrailing-whitespace-8.c  | 44 +
 .../c-c++-common/cpp/Wtrailing-whitespace-9.c  | 29 +++
 libcpp/include/cpplib.h|  6 ++-
 libcpp/internal.h  |  4 +-
 libcpp/lex.cc  | 56 +-
 16 files changed, 444 insertions(+), 17 deletions(-)

diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt
index 1f2e72a0bb73..f758d7b941c0 100644
--- a/gcc/c-family/c.opt
+++ b/gcc/c-family/c.opt
@@ -1466,6 +1466,26 @@ Wtraditional-conversion
 C ObjC Var(warn_traditional_conversion) Warning
 Warn of prototypes c

[gcc r15-4345] genmatch: Revert recent genmatch changes, instead add custom diag_vfprintf routine [PR117110]

2024-10-14 Thread Jakub Jelinek via Gcc-cvs

https://gcc.gnu.org/g:384faebde257b0b5a0aa334718ef1b645d4c8d1e

commit r15-4345-g384faebde257b0b5a0aa334718ef1b645d4c8d1e
Author: Jakub Jelinek 
Date:   Tue Oct 15 07:50:35 2024 +0200

genmatch: Revert recent genmatch changes, instead add custom diag_vfprintf 
routine [PR117110]

My recent changes to genmatch apparently broke bootstrap on FreeBSD
and Darwin and perhaps others, and also broke $build != $host
builds including canadian cross.

The change was to link in libcommon.a into build/genmatch, so that
we can use pp_format_verbatim.  Unfortunately that has various
dependencies in libcommon.a, and more importantly, libcommon.a is
a host library, while build/genmatch carefully links with build/vec.o
etc., build version of libcpp.
So, in order to use pretty-print.o stuff, we'd need to build a build/
version of all those objects and worse ensure there is and we properly
link build version of libintl and/or libiconv when needed (those 2 are
the reasons for FreeBSD/Darwin failures).

The following patch just reverts those changes and instead adds a very
simple variant of gcc_diag style vfprintf, which prints the result
directly into a stream.
We don't need anything fancy, like UTF-8 quotes, colors, URLs, in the
usual case genmatch shouldn't print anything at all.
The patch implements what pretty-print.cc implements, except the fancy
stuff (no colors, no URLs printed, quotes always printed just as
'something', strings even in %qs printed normally rather than trying to
pass through ASCII and valid UTF-8 and use <80><35> style printing for the
rest) and except %@ and %e (neither libcpp nor genmatch.cc use those
currently and they need extra structures etc. which aren't used in libcpp
at all).  It handles both "%.*s %d" and "%3$.*2$s %1$d" styles just in case
something got translated (although at least the cross-compiler and stage1
genmatch shouldn't be translating anything, but stage2+ native can).

I've tested it with hacking up most of pretty-print.cc self-tests
to just use warning_at ((location_t) 1, ...) and doing manual verification
of what was printed vs. what was expected (with a few additions for the
%M$ style formats); as it goes into a FILE * directly, I'm afraid self-tests
of this aren't easily possible.

2024-10-15  Jakub Jelinek  

PR bootstrap/117110
* Makefile.in (generated_files, generated_match_files,
build/genmatch$(build_exeext), LINKER_FOR_BUILD): Revert
2024-10-12 changes.
* genmatch.cc: Don't include pretty-print.h and input.h.
(fatal, ggc_internal_cleared_alloc, ggc_free, line_table,
linemap_client_expand_location_to_spelling_point): Revert
2024-10-12 changes.
(DIAG_ARGMAX): Define.
(diag_integer_with_precision): Define.
(diag_vfprintf): New function.
(diagnostic_cb): Use diag_vfprintf instead of pp_format_verbatim.
(output_line_directive): Revert 2024-10-12 changes.

Diff:
---
 gcc/Makefile.in |  14 +-
 gcc/genmatch.cc | 564 ++--
 2 files changed, 548 insertions(+), 30 deletions(-)

diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index b7735908de7a..059cf2e8f79f 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -2957,12 +2957,12 @@ generated_files = config.h tm.h $(TM_P_H) $(TM_D_H) 
$(TM_H) multilib.h \
$(ALL_GTFILES_H) gtype-desc.cc gtype-desc.h version.h \
options.h target-hooks-def.h insn-opinit.h \
common/common-target-hooks-def.h pass-instances.def \
+   $(GIMPLE_MATCH_PD_SEQ_SRC) $(GENERIC_MATCH_PD_SEQ_SRC) \
+   gimple-match-auto.h generic-match-auto.h \
c-family/c-target-hooks-def.h d/d-target-hooks-def.h \
$(TM_RUST_H) rust/rust-target-hooks-def.h \
case-cfn-macros.h \
cfn-operators.pd omp-device-properties.h
-generated_match_files = gimple-match-auto.h generic-match-auto.h \
-   $(GIMPLE_MATCH_PD_SEQ_SRC) $(GENERIC_MATCH_PD_SEQ_SRC)
 
 #
 # How to compile object files to run on the build machine.
@@ -3145,14 +3145,8 @@ build/genmatch$(build_exeext): BUILD_LIBDEPS += 
$(LIBINTL_DEP) $(LIBICONV_DEP)
 build/genmatch$(build_exeext): BUILD_LIBS += $(LIBINTL) $(LIBICONV)
 endif
 
-# genmatch links in libcommon.a, which could have been compiled with
-# $(PICFLAG) set to -fno-PIE.  Make sure to link genmatch with -no-pie
-# in that case.
-build/genmatch$(build_exeext): LINKER_FOR_BUILD += $(findstring 
-no-pie,$(LD_PICFLAG))
-
 build/genmatch$(build_exeext) : $(BUILD_CPPLIB) \
-  build/vec.o build/hash-table.o build/sort.o libcommon.a \
-  $(LIBBACKTRACE)
+  $(BUILD_ERRORS) build/vec.o build/hash-table.o build/sort.o
 
 # These programs are not linked with the MD reader.
 build/gengtype$(build_exeext) : build/gengtype-lex.o build/gengtype-parse.o \
@@ -4581

[gcc r15-4347] SVE intrinsics: Fold svmul with constant power-of-2 operand to svlsl

2024-10-14 Thread Jennifer Schmitz via Gcc-cvs

https://gcc.gnu.org/g:441ec5f9191443818ac1c10c72860d8a8ee2f9d2

commit r15-4347-g441ec5f9191443818ac1c10c72860d8a8ee2f9d2
Author: Jennifer Schmitz 
Date:   Thu Sep 19 03:18:05 2024 -0700

SVE intrinsics: Fold svmul with constant power-of-2 operand to svlsl

For svmul, if one of the operands is a constant vector with a uniform
power of 2, this patch folds the multiplication to a left-shift by
immediate (svlsl).
Because the shift amount in svlsl is the second operand, the order of the
operands is switched, if the first operand contained the powers of 2. 
However,
this switching is not valid for some predications: If the predication is
_m and the predicate not ptrue, the result of svlsl might not be the
same as for svmul. Therefore, we do not apply the fold in this case.
The transform is also not applied to constant vectors of 1 (this case is
partially covered by constant folding already and the missing cases will be
addressed by the follow-up patch suggested in
https://gcc.gnu.org/pipermail/gcc-patches/2024-September/663275.html).

Tests were added in the existing test harness to check the produced assembly
- when the first or second operand contains the power of 2
- when the second operand is a vector or scalar (_n)
- for _m, _z, _x predication
- for _m with ptrue or non-ptrue
- for intmin for signed integer types
- for the maximum power of 2 for signed and unsigned integer types.
Note that we used 4 as a power of 2, instead of 2, because a recent
patch optimizes left-shifts by 1 to an add instruction. But since we
wanted to highlight the change to an lsl instruction we used a higher
power of 2.
To also check correctness, runtime tests were added.

The patch was bootstrapped and regtested on aarch64-linux-gnu, no 
regression.
OK for mainline?

Signed-off-by: Jennifer Schmitz 

gcc/
* config/aarch64/aarch64-sve-builtins-base.cc (svmul_impl::fold):
Implement fold to svlsl for power-of-2 operands.

gcc/testsuite/
* gcc.target/aarch64/sve/acle/asm/mul_s8.c: New test.
* gcc.target/aarch64/sve/acle/asm/mul_s16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/mul_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/mul_s64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/mul_u8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/mul_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/mul_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/mul_u64.c: Likewise.
* gcc.target/aarch64/sve/mul_const_run.c: Likewise.

Diff:
---
 gcc/config/aarch64/aarch64-sve-builtins-base.cc|  33 +-
 .../gcc.target/aarch64/sve/acle/asm/mul_s16.c  | 350 ++--
 .../gcc.target/aarch64/sve/acle/asm/mul_s32.c  | 350 ++--
 .../gcc.target/aarch64/sve/acle/asm/mul_s64.c  | 360 +++--
 .../gcc.target/aarch64/sve/acle/asm/mul_s8.c   | 355 ++--
 .../gcc.target/aarch64/sve/acle/asm/mul_u16.c  | 322 --
 .../gcc.target/aarch64/sve/acle/asm/mul_u32.c  | 322 --
 .../gcc.target/aarch64/sve/acle/asm/mul_u64.c  | 332 +--
 .../gcc.target/aarch64/sve/acle/asm/mul_u8.c   | 327 +--
 .../gcc.target/aarch64/sve/mul_const_run.c | 101 ++
 10 files changed, 2609 insertions(+), 243 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc 
b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 5210f41c0130..1c17149e1f07 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -2036,7 +2036,38 @@ public:
|| is_ptrue (pg, f.type_suffix (0).element_bytes)))
   return gimple_build_assign (f.lhs, build_zero_cst (TREE_TYPE (f.lhs)));
 
-return NULL;
+/* If one of the operands is a uniform power of 2, fold to a left shift
+   by immediate.  */
+tree op1_cst = uniform_integer_cst_p (op1);
+tree op2_cst = uniform_integer_cst_p (op2);
+tree shift_op1, shift_op2;
+if (op1_cst && integer_pow2p (op1_cst)
+   && (f.pred != PRED_m
+   || is_ptrue (pg, f.type_suffix (0).element_bytes)))
+  {
+   shift_op1 = op2;
+   shift_op2 = op1_cst;
+  }
+else if (op2_cst && integer_pow2p (op2_cst))
+  {
+   shift_op1 = op1;
+   shift_op2 = op2_cst;
+  }
+else
+  return NULL;
+
+if (integer_onep (shift_op2))
+  return NULL;
+
+shift_op2 = wide_int_to_tree (unsigned_type_for (TREE_TYPE (shift_op2)),
+ tree_log2 (shift_op2));
+function_instance instance ("svlsl", functions::svlsl,
+   shapes::binary_uint_opt_n, MODE_n,
+   f.type_suffix_ids, GROUP_none, f.pred);
+gcall *call = f.redire

[gcc r15-4340] c++: address deduction and concepts [CWG2918]

2024-10-14 Thread Jason Merrill via Gcc-cvs

https://gcc.gnu.org/g:cacbb4daac3e9a9d86992fef1a7c607b4cee5f22

commit r15-4340-gcacbb4daac3e9a9d86992fef1a7c607b4cee5f22
Author: Jason Merrill 
Date:   Fri Oct 11 14:52:43 2024 -0400

c++: address deduction and concepts [CWG2918]

CWG2918 changes deduction from an overload set for the case where multiple
candidates succeed and have the same type; previously this made the overload
set a non-deduced context, now it succeeds since the result is consistent
between the candidates.

This is needed for cases of overloading based on requirements, where we want
to choose the most constrained overload.  I also needed to adjust
resolve_address_of_overloaded_function accordingly; we already handled the
comparison for template candidates in most_specialized_instantiation, but
need to also do the comparison for non-template candidates such as member
functions of a class template.

CWG 2918 (proposed)

gcc/cp/ChangeLog:

* cp-tree.h (most_constrained_function): Declare..
* class.cc (resolve_address_of_overloaded_function): Call it.
* pt.cc (get_template_for_ordering): Handle list from
resolve_address_of_overloaded_function.
(most_constrained_function): No longer static.
(resolve_overloaded_unification): Always compare type rather
than decl.

gcc/testsuite/ChangeLog:

* g++.dg/DRs/dr2918.C: New test.

Diff:
---
 gcc/cp/cp-tree.h  |  1 +
 gcc/cp/class.cc   | 13 ++---
 gcc/cp/pt.cc  | 18 ++
 gcc/testsuite/g++.dg/DRs/dr2918.C | 11 +++
 4 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index dc153a97dc46..94ee550bd9cb 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -7593,6 +7593,7 @@ extern int template_args_equal  (tree, 
tree);
 extern tree maybe_process_partial_specialization (tree);
 extern tree most_specialized_instantiation (tree);
 extern tree most_specialized_partial_spec   (tree, tsubst_flags_t, bool = 
false);
+extern tree most_constrained_function  (tree);
 extern void print_candidates   (tree);
 extern void instantiate_pending_templates  (int);
 extern tree tsubst_default_argument(tree, int, tree, tree,
diff --git a/gcc/cp/class.cc b/gcc/cp/class.cc
index 646072d4f202..8c39bb4a76b1 100644
--- a/gcc/cp/class.cc
+++ b/gcc/cp/class.cc
@@ -8896,11 +8896,18 @@ resolve_address_of_overloaded_function (tree 
target_type,
  tree match = most_specialized_instantiation (matches);
 
  if (match != error_mark_node)
-   matches = tree_cons (TREE_PURPOSE (match),
-NULL_TREE,
-NULL_TREE);
+   {
+ matches = match;
+ TREE_CHAIN (match) = NULL_TREE;
+   }
}
 }
+  else if (flag_concepts && TREE_CHAIN (matches))
+if (tree match = most_constrained_function (matches))
+  {
+   matches = match;
+   TREE_CHAIN (match) = NULL_TREE;
+  }
 
   /* Now we should have exactly one function in MATCHES.  */
   if (matches == NULL_TREE)
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index 03a1144765b2..c0a37a51cba3 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -2071,6 +2071,10 @@ get_template_for_ordering (tree list)
 {
   gcc_assert (TREE_CODE (list) == TREE_LIST);
   tree f = TREE_VALUE (list);
+  if (f == NULL_TREE)
+/* Also handle a list from resolve_address_of_overloaded_function with the
+   function in TREE_PURPOSE.  */
+f = TREE_PURPOSE (list);
   if (tree ti = DECL_TEMPLATE_INFO (f))
 return TI_TEMPLATE (ti);
   return f;
@@ -2084,7 +2088,7 @@ get_template_for_ordering (tree list)
 
Note that we don't compare constraints on the functions
themselves, but rather those of their templates. */
-static tree
+tree
 most_constrained_function (tree candidates)
 {
   // Try to find the best candidate in a first pass.
@@ -23865,11 +23869,14 @@ resolve_overloaded_unification (tree tparms,
tree fn = *iter;
if (flag_noexcept_type)
  maybe_instantiate_noexcept (fn, tf_none);
-   if (try_one_overload (tparms, targs, tempargs, parm, TREE_TYPE (fn),
+   if (TREE_CODE (fn) == FUNCTION_DECL && !constraints_satisfied_p (fn))
+ continue;
+   tree elem = TREE_TYPE (fn);
+   if (try_one_overload (tparms, targs, tempargs, parm, elem,
  strict, sub_strict, addr_p, explain_p)
-   && (!goodfn || !decls_match (goodfn, fn)))
+   && (!goodfn || !same_type_p (goodfn, elem)))
  {
-   goodfn = fn;
+   goodfn = elem;
++good;
  }
   }
@@ -23879,6 +23886,9 @@ resolve_overloaded_unification (tree tparms,
  overloaded functions does not contain function templates and at mo

[gcc r12-10769] Fix points_to_local_or_readonly_memory_p wrt TARGET_MEM_REF

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:92889011625f16e7eed654a137b9c14a29282917

commit r12-10769-g92889011625f16e7eed654a137b9c14a29282917
Author: Jan Hubicka 
Date:   Thu May 16 15:33:55 2024 +0200

Fix points_to_local_or_readonly_memory_p wrt TARGET_MEM_REF

TARGET_MEM_REF can be used to offset constant base into a memory object (to
produce lea instruction).  This confuses 
points_to_local_or_readonly_memory_p
which treats the constant address as a base of the access.

Bootstrapped/regtsted x86_64-linux, comitted.
Honza

gcc/ChangeLog:

PR ipa/113787
* ipa-fnsummary.cc (points_to_local_or_readonly_memory_p): Do not
look into TARGET_MEM_REFS with constant opreand 0.

gcc/testsuite/ChangeLog:

* gcc.c-torture/execute/pr113787.c: New test.

(cherry picked from commit 96d53252aefcbc2fe419c4c3b4bcd3fc03d4d187)

Diff:
---
 gcc/ipa-fnsummary.cc   |  4 ++-
 gcc/testsuite/gcc.c-torture/execute/pr113787.c | 38 ++
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/gcc/ipa-fnsummary.cc b/gcc/ipa-fnsummary.cc
index b12e7a1124d5..65e6687428ee 100644
--- a/gcc/ipa-fnsummary.cc
+++ b/gcc/ipa-fnsummary.cc
@@ -2589,7 +2589,9 @@ points_to_local_or_readonly_memory_p (tree t)
return true;
   return !ptr_deref_may_alias_global_p (t, false);
 }
-  if (TREE_CODE (t) == ADDR_EXPR)
+  if (TREE_CODE (t) == ADDR_EXPR
+  && (TREE_CODE (TREE_OPERAND (t, 0)) != TARGET_MEM_REF
+ || TREE_CODE (TREE_OPERAND (TREE_OPERAND (t, 0), 0)) != INTEGER_CST))
 return refs_local_or_readonly_memory_p (TREE_OPERAND (t, 0));
   return false;
 }
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr113787.c 
b/gcc/testsuite/gcc.c-torture/execute/pr113787.c
new file mode 100644
index ..702b6c35fc68
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr113787.c
@@ -0,0 +1,38 @@
+void foo(int x, int y, int z, int d, int *buf)
+{
+  for(int i = z; i < y-z; ++i)
+for(int j = 0; j < d; ++j)
+  /* buf[x(i+1) + j] = buf[x(i+1)-j-1] */
+  buf[i*x+(x-z+j)] = buf[i*x+(x-z-1-j)];
+}
+
+void bar(int x, int y, int z, int d, int *buf)
+{
+  for(int i = 0; i < d; ++i)
+for(int j = z; j < x-z; ++j)
+  /* buf[j+(y+i)*x] = buf[j+(y-1-i)*x] */
+  buf[j+(y-z+i)*x] = buf[j+(y-z-1-i)*x];
+}
+
+__attribute__((noipa))
+void baz(int x, int y, int d, int *buf)
+{
+  foo(x, y, 0, d, buf);
+  bar(x, y, 0, d, buf);
+}
+
+int main(void)
+{
+  int a[] = { 1, 2, 3 };
+  baz (1, 2, 1, a);
+  /* foo does:
+ buf[1] = buf[0];
+ buf[2] = buf[1];
+
+ bar does:
+ buf[2] = buf[1]; (no-op)
+ so we should have { 1, 1, 1 }.  */
+  for (int i = 0; i < 3; i++)
+if (a[i] != 1)
+  __builtin_abort ();
+}

[gcc r12-10770] Fix handling of ICF_NOVOPS in ipa-modref

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:b454ad0e4eb6bb38a6dfe15a43acb6792315640b

commit r12-10770-gb454ad0e4eb6bb38a6dfe15a43acb6792315640b
Author: Jan Hubicka 
Date:   Mon Jul 22 23:01:50 2024 +0200

Fix handling of ICF_NOVOPS in ipa-modref

As shown in somewhat convoluted testcase, ipa-modref is mistreating
ECF_NOVOPS as "having no side effects".  This come from time when
modref cared only about memory accesses and thus it was possible to
shortcut on it.

This patch removes (hopefully) all those bad shortcuts.
Bootstrapped/regtested x86_64-linux, comitted.

gcc/ChangeLog:

PR ipa/109985

* ipa-modref.cc (modref_summary::useful_p): Fix handling of 
ECF_NOVOPS.
(modref_access_analysis::process_fnspec): Likevise.
(modref_access_analysis::analyze_call): Likevise.
(propagate_unknown_call): Likevise.
(modref_propagate_in_scc): Likevise.
(modref_propagate_flags_in_scc): Likewise.
(ipa_merge_modref_summary_after_inlining): Likewise.

(cherry picked from commit efcbe7b985e24ac002a863afd609c44a67761195)

Diff:
---
 gcc/ipa-modref.cc | 36 +---
 1 file changed, 21 insertions(+), 15 deletions(-)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index bcd9b49fe631..1d954954786f 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -332,7 +332,7 @@ modref_summary::useful_p (int ecf_flags, bool check_flags)
   if (check_flags
   && remove_useless_eaf_flags (static_chain_flags, ecf_flags, false))
 return true;
-  if (ecf_flags & (ECF_CONST | ECF_NOVOPS))
+  if (ecf_flags & ECF_CONST)
 return ((!side_effects || !nondeterministic)
&& (ecf_flags & ECF_LOOPING_CONST_OR_PURE));
   if (loads && !loads->every_base)
@@ -1261,7 +1261,7 @@ modref_access_analysis::merge_call_side_effects
   int flags = gimple_call_flags (call);
 
   /* Nothing to do for non-looping cont functions.  */
-  if ((flags & (ECF_CONST | ECF_NOVOPS))
+  if ((flags & ECF_CONST)
   && !(flags & ECF_LOOPING_CONST_OR_PURE))
 return false;
 
@@ -1274,7 +1274,7 @@ modref_access_analysis::merge_call_side_effects
   /* Merge side effects and non-determinism.
  PURE/CONST flags makes functions deterministic and if there is
  no LOOPING_CONST_OR_PURE they also have no side effects.  */
-  if (!(flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(flags & (ECF_CONST | ECF_PURE))
   || (flags & ECF_LOOPING_CONST_OR_PURE))
 {
   if (!m_summary->side_effects && callee_summary->side_effects)
@@ -1463,7 +1463,7 @@ modref_access_analysis::process_fnspec (gcall *call)
 
   /* PURE/CONST flags makes functions deterministic and if there is
  no LOOPING_CONST_OR_PURE they also have no side effects.  */
-  if (!(flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(flags & (ECF_CONST | ECF_PURE))
   || (flags & ECF_LOOPING_CONST_OR_PURE)
   || (cfun->can_throw_non_call_exceptions
  && stmt_could_throw_p (cfun, call)))
@@ -1602,12 +1602,12 @@ modref_access_analysis::analyze_call (gcall *stmt)
   print_gimple_stmt (dump_file, stmt, 0);
 }
 
-  if ((flags & (ECF_CONST | ECF_NOVOPS))
+  if ((flags & ECF_CONST)
   && !(flags & ECF_LOOPING_CONST_OR_PURE))
 {
   if (dump_file)
fprintf (dump_file,
-" - ECF_CONST | ECF_NOVOPS, ignoring all stores and all loads "
+" - ECF_CONST, ignoring all stores and all loads "
 "except for args.\n");
   return;
 }
@@ -1622,7 +1622,13 @@ modref_access_analysis::analyze_call (gcall *stmt)
   if (dump_file)
fprintf (dump_file, gimple_call_internal_p (stmt)
 ? " - Internal call" : " - Indirect call.\n");
-  process_fnspec (stmt);
+  if (flags & ECF_NOVOPS)
+{
+ set_side_effects ();
+ set_nondeterministic ();
+}
+  else
+   process_fnspec (stmt);
   return;
 }
   /* We only need to handle internal calls in IPA mode.  */
@@ -4510,7 +4516,7 @@ propagate_unknown_call (cgraph_node *node,
   return changed;
 }
 
-  if (!(ecf_flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(ecf_flags & (ECF_CONST | ECF_PURE))
   || (ecf_flags & ECF_LOOPING_CONST_OR_PURE)
   || nontrivial_scc)
 {
@@ -4724,7 +4730,7 @@ modref_propagate_in_scc (cgraph_node *component_node)
  struct cgraph_node *callee;
 
  if (!callee_edge->inline_failed
-|| ((flags & (ECF_CONST | ECF_NOVOPS))
+|| ((flags & ECF_CONST)
 && !(flags & ECF_LOOPING_CONST_OR_PURE)))
continue;
 
@@ -5147,8 +5153,8 @@ modref_propagate_flags_in_scc (cgraph_node 
*component_node)
{
  escape_summary *sum = escape_summaries->get (e);
 
- if (!sum || (e->indirect_info->ecf_flags
-  & (ECF_CONST | ECF_NOVOPS)))
+ if (!sum || ((e->in

[gcc r12-10767] Fix accounting of offsets in unadjusted_ptr_and_unit_offset

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:e098149b6b2c61ffe9e758dcd3ef021a78f2d132

commit r12-10767-ge098149b6b2c61ffe9e758dcd3ef021a78f2d132
Author: Jan Hubicka 
Date:   Mon Jul 22 18:05:26 2024 +0200

Fix accounting of offsets in unadjusted_ptr_and_unit_offset

unadjusted_ptr_and_unit_offset accidentally throws away the offset computed 
by
get_addr_base_and_unit_offset. Instead of passing extra_offset it passes 
offset.

PR ipa/114207

gcc/ChangeLog:

* ipa-prop.cc (unadjusted_ptr_and_unit_offset): Fix accounting of 
offsets in ADDR_EXPR.

gcc/testsuite/ChangeLog:

* gcc.c-torture/execute/pr114207.c: New test.

(cherry picked from commit 391f46f10b0586c074014de82efe76787739bb0c)

Diff:
---
 gcc/ipa-prop.cc|  4 ++--
 gcc/testsuite/gcc.c-torture/execute/pr114207.c | 23 +++
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc
index e2e83b5f3f50..848d62e49cf9 100644
--- a/gcc/ipa-prop.cc
+++ b/gcc/ipa-prop.cc
@@ -1263,9 +1263,9 @@ unadjusted_ptr_and_unit_offset (tree op, tree *ret, 
poly_int64 *offset_ret)
 {
   if (TREE_CODE (op) == ADDR_EXPR)
{
- poly_int64 extra_offset = 0;
+ poly_int64 extra_offset;
  tree base = get_addr_base_and_unit_offset (TREE_OPERAND (op, 0),
-&offset);
+&extra_offset);
  if (!base)
{
  base = get_base_address (TREE_OPERAND (op, 0));
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr114207.c 
b/gcc/testsuite/gcc.c-torture/execute/pr114207.c
new file mode 100644
index ..052fa85e9fc6
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr114207.c
@@ -0,0 +1,23 @@
+#include 
+#include 
+
+struct S {
+int a, b;
+};
+
+__attribute__((noinline))
+void foo (struct S *s) {
+struct S ss = (struct S) {
+.a = s->b,
+.b = s->a
+};
+*s = ss;
+}
+
+int main() {
+  struct S s = {6, 12};
+  foo(&s);
+  if (s.a != 12 || s.b != 6)
+__builtin_abort ();
+  return 0;
+}

[gcc r12-10768] Fix modref_eaf_analysis::analyze_ssa_name handling of values dereferenced to function call parameter

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:f2686f12e9345d95a2d6b7291bd777501d197869

commit r12-10768-gf2686f12e9345d95a2d6b7291bd777501d197869
Author: Jan Hubicka 
Date:   Mon Jul 22 18:08:08 2024 +0200

Fix modref_eaf_analysis::analyze_ssa_name handling of values dereferenced 
to function call parameters

modref_eaf_analysis::analyze_ssa_name misinterprets EAF flags.  If 
dereferenced
parameter is passed (to map_iterator in the testcase) it can be returned
indirectly which in turn makes it to escape into the next function call.

PR ipa/115033

gcc/ChangeLog:

* ipa-modref.cc (modref_eaf_analysis::analyze_ssa_name): Fix 
checking of
EAF flags when analysing values dereferenced as function parameters.

gcc/testsuite/ChangeLog:

* gcc.c-torture/execute/pr115033.c: New test.

(cherry picked from commit cf8ffc58aad3127031c229a75cc4b99c8ace25e0)

Diff:
---
 gcc/ipa-modref.cc  |  6 +++--
 gcc/testsuite/gcc.c-torture/execute/pr115033.c | 35 ++
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index c3e3fd50d173..bcd9b49fe631 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -2568,8 +2568,10 @@ modref_eaf_analysis::analyze_ssa_name (tree name, bool 
deferred)
int call_flags = deref_flags
(gimple_call_arg_flags (call, i), ignore_stores);
if (!ignore_retval && !(call_flags & EAF_UNUSED)
-   && !(call_flags & EAF_NOT_RETURNED_DIRECTLY)
-   && !(call_flags & EAF_NOT_RETURNED_INDIRECTLY))
+   && (call_flags & (EAF_NOT_RETURNED_DIRECTLY
+ | EAF_NOT_RETURNED_INDIRECTLY))
+   != (EAF_NOT_RETURNED_DIRECTLY
+   | EAF_NOT_RETURNED_INDIRECTLY))
  merge_call_lhs_flags (call, i, name, false, true);
if (ecf_flags & (ECF_CONST | ECF_NOVOPS))
  m_lattice[index].merge_direct_load ();
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr115033.c 
b/gcc/testsuite/gcc.c-torture/execute/pr115033.c
new file mode 100644
index ..3e79367d401c
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr115033.c
@@ -0,0 +1,35 @@
+
+typedef struct func
+{
+  int *a;
+}func;
+__attribute__((noinline))
+void ff(struct func *t)
+{
+  *(t->a) = 0;
+}
+
+
+typedef struct mapped_iterator {
+  func F;
+}mapped_iterator;
+
+__attribute__((noinline))
+mapped_iterator map_iterator(func F) {
+  mapped_iterator t = {F};
+  return t;
+}
+
+void map_to_vector(func *F) {
+  mapped_iterator t = map_iterator(*F);
+  ff(&t.F);
+}
+int main() {
+  int resultIsStatic = 1;
+  func t ={&resultIsStatic};
+  map_to_vector(&t);
+
+  if (resultIsStatic)
+__builtin_trap();
+  __builtin_exit(0);
+}

[gcc r15-4344] RISC-V: Fix UNRESOLVED testcases for SAT alu vector mode

2024-10-14 Thread Pan Li via Gcc-cvs

https://gcc.gnu.org/g:14493126c0f56dd201b27bfd28fb4575351a9725

commit r15-4344-g14493126c0f56dd201b27bfd28fb4575351a9725
Author: Pan Li 
Date:   Tue Oct 15 09:19:44 2024 +0800

RISC-V: Fix UNRESOLVED testcases for SAT alu vector mode

Some saturation related alu testcases missed additional option
for expand check, which result in some UNRESOLVED issues.  This
patch would like to fix it by adding the option back as other
testcases.

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Add
compile option for expanding check.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c  | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c| 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c| 1 +
 8 files changed, 8 insertions(+)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
index 236fe68123fb..1320b05e76cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
index 2eda4197abba..e71758d9c4ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
index ae97fece59bc..1626e857d28f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
index f0c5289764f7..8792bb6112b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
index 7cde4c9d378e..4a93c7f89cbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
index 341226838a37..bc6d441759f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/b

[gcc r14-10787] Fix handling of ICF_NOVOPS in ipa-modref

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:f0629e32278ef3966c00e889d0c6dce1de6115cc

commit r14-10787-gf0629e32278ef3966c00e889d0c6dce1de6115cc
Author: Jan Hubicka 
Date:   Mon Jul 22 23:01:50 2024 +0200

Fix handling of ICF_NOVOPS in ipa-modref

As shown in somewhat convoluted testcase, ipa-modref is mistreating
ECF_NOVOPS as "having no side effects".  This come from time when
modref cared only about memory accesses and thus it was possible to
shortcut on it.

This patch removes (hopefully) all those bad shortcuts.
Bootstrapped/regtested x86_64-linux, comitted.

gcc/ChangeLog:

PR ipa/109985

* ipa-modref.cc (modref_summary::useful_p): Fix handling of 
ECF_NOVOPS.
(modref_access_analysis::process_fnspec): Likevise.
(modref_access_analysis::analyze_call): Likevise.
(propagate_unknown_call): Likevise.
(modref_propagate_in_scc): Likevise.
(modref_propagate_flags_in_scc): Likewise.
(ipa_merge_modref_summary_after_inlining): Likewise.

(cherry picked from commit efcbe7b985e24ac002a863afd609c44a67761195)

Diff:
---
 gcc/ipa-modref.cc | 36 +---
 1 file changed, 21 insertions(+), 15 deletions(-)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index ccf788e6398c..400a8856de2d 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -334,7 +334,7 @@ modref_summary::useful_p (int ecf_flags, bool check_flags)
   if (check_flags
   && remove_useless_eaf_flags (static_chain_flags, ecf_flags, false))
 return true;
-  if (ecf_flags & (ECF_CONST | ECF_NOVOPS))
+  if (ecf_flags & ECF_CONST)
 return ((!side_effects || !nondeterministic)
&& (ecf_flags & ECF_LOOPING_CONST_OR_PURE));
   if (loads && !loads->every_base)
@@ -1263,7 +1263,7 @@ modref_access_analysis::merge_call_side_effects
   int flags = gimple_call_flags (call);
 
   /* Nothing to do for non-looping cont functions.  */
-  if ((flags & (ECF_CONST | ECF_NOVOPS))
+  if ((flags & ECF_CONST)
   && !(flags & ECF_LOOPING_CONST_OR_PURE))
 return false;
 
@@ -1276,7 +1276,7 @@ modref_access_analysis::merge_call_side_effects
   /* Merge side effects and non-determinism.
  PURE/CONST flags makes functions deterministic and if there is
  no LOOPING_CONST_OR_PURE they also have no side effects.  */
-  if (!(flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(flags & (ECF_CONST | ECF_PURE))
   || (flags & ECF_LOOPING_CONST_OR_PURE))
 {
   if (!m_summary->side_effects && callee_summary->side_effects)
@@ -1465,7 +1465,7 @@ modref_access_analysis::process_fnspec (gcall *call)
 
   /* PURE/CONST flags makes functions deterministic and if there is
  no LOOPING_CONST_OR_PURE they also have no side effects.  */
-  if (!(flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(flags & (ECF_CONST | ECF_PURE))
   || (flags & ECF_LOOPING_CONST_OR_PURE)
   || (cfun->can_throw_non_call_exceptions
  && stmt_could_throw_p (cfun, call)))
@@ -1604,12 +1604,12 @@ modref_access_analysis::analyze_call (gcall *stmt)
   print_gimple_stmt (dump_file, stmt, 0);
 }
 
-  if ((flags & (ECF_CONST | ECF_NOVOPS))
+  if ((flags & ECF_CONST)
   && !(flags & ECF_LOOPING_CONST_OR_PURE))
 {
   if (dump_file)
fprintf (dump_file,
-" - ECF_CONST | ECF_NOVOPS, ignoring all stores and all loads "
+" - ECF_CONST, ignoring all stores and all loads "
 "except for args.\n");
   return;
 }
@@ -1624,7 +1624,13 @@ modref_access_analysis::analyze_call (gcall *stmt)
   if (dump_file)
fprintf (dump_file, gimple_call_internal_p (stmt)
 ? " - Internal call" : " - Indirect call.\n");
-  process_fnspec (stmt);
+  if (flags & ECF_NOVOPS)
+{
+ set_side_effects ();
+ set_nondeterministic ();
+}
+  else
+   process_fnspec (stmt);
   return;
 }
   /* We only need to handle internal calls in IPA mode.  */
@@ -4570,7 +4576,7 @@ propagate_unknown_call (cgraph_node *node,
   return changed;
 }
 
-  if (!(ecf_flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(ecf_flags & (ECF_CONST | ECF_PURE))
   || (ecf_flags & ECF_LOOPING_CONST_OR_PURE)
   || nontrivial_scc)
 {
@@ -4784,7 +4790,7 @@ modref_propagate_in_scc (cgraph_node *component_node)
  struct cgraph_node *callee;
 
  if (!callee_edge->inline_failed
-|| ((flags & (ECF_CONST | ECF_NOVOPS))
+|| ((flags & ECF_CONST)
 && !(flags & ECF_LOOPING_CONST_OR_PURE)))
continue;
 
@@ -5207,8 +5213,8 @@ modref_propagate_flags_in_scc (cgraph_node 
*component_node)
{
  escape_summary *sum = escape_summaries->get (e);
 
- if (!sum || (e->indirect_info->ecf_flags
-  & (ECF_CONST | ECF_NOVOPS)))
+ if (!sum || ((e->in

[gcc r14-10784] ada: Type conversion in instance incorrectly rejected.

2024-10-14 Thread Eric Botcazou via Gcc-cvs

https://gcc.gnu.org/g:aff061f0f51e2547b04c8d24c3b0dc713a6d62a3

commit r14-10784-gaff061f0f51e2547b04c8d24c3b0dc713a6d62a3
Author: Steve Baird 
Date:   Mon Jul 8 14:45:55 2024 -0700

ada: Type conversion in instance incorrectly rejected.

In some cases, a legal type conversion in a generic package is correctly
accepted but the corresponding type conversion in an instance of the generic
is incorrectly rejected.

gcc/ada/
PR ada/114593
* sem_res.adb (Valid_Conversion): Test In_Instance instead of
In_Instance_Body.

Diff:
---
 gcc/ada/sem_res.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 075c0d85ccd9..a1d5fe4ff541 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -14621,7 +14621,7 @@ package body Sem_Res is
 
   --  If it was legal in the generic, it's legal in the instance
 
-  elsif In_Instance_Body then
+  elsif In_Instance then
  return True;
 
   --  If both are tagged types, check legality of view conversions

[gcc r14-10785] Add regression test

2024-10-14 Thread Eric Botcazou via Gcc-cvs

https://gcc.gnu.org/g:b62c956f775408b9058a3c9b738462e5d67d8df7

commit r14-10785-gb62c956f775408b9058a3c9b738462e5d67d8df7
Author: Eric Botcazou 
Date:   Mon Oct 14 11:57:57 2024 +0200

Add regression test

gcc/testsuite/
PR ada/114593
* gnat.dg/specs/generic_inst2-child2.ads: New test.
* gnat.dg/specs/generic_inst2.ads: New helper.
* gnat.dg/specs/generic_inst2-child1.ads: Likewise.

Diff:
---
 gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads | 17 +
 gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads | 10 ++
 gcc/testsuite/gnat.dg/specs/generic_inst2.ads| 11 +++
 3 files changed, 38 insertions(+)

diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
new file mode 100644
index ..18e212b2e58c
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
@@ -0,0 +1,17 @@
+generic
+package Generic_Inst2.Child1 is
+
+   function Get_Custom return Custom_Type;
+
+private
+
+   type Dummy is null record;
+
+   Placeholder : constant Dummy := (null record);
+
+   -- This type conversion fails (though only when
+   -- instantiated in the other package)
+   function Get_Custom return Custom_Type is 
+  (Custom_Type(Placeholder'Address));
+
+end Generic_Inst2.Child1;
diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
new file mode 100644
index ..3bb5b0aca107
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
@@ -0,0 +1,10 @@
+-- { dg-do compile }
+
+with Generic_Inst2.Child1;
+
+generic
+package Generic_Inst2.Child2 is
+
+   package Second is new Generic_Inst2.Child1;
+
+end Generic_Inst2.Child2;
diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2.ads
new file mode 100644
index ..0a74e36273bd
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2.ads
@@ -0,0 +1,11 @@
+private with System;
+
+package Generic_Inst2 is
+
+   type Custom_Type is private;
+
+private
+
+   type Custom_Type is new System.Address;
+
+end Generic_Inst2;

[gcc r12-10765] Add regression test

2024-10-14 Thread Eric Botcazou via Gcc-cvs

https://gcc.gnu.org/g:3bb9418811d2ce870bd1c1c98a2ddca1bdcce998

commit r12-10765-g3bb9418811d2ce870bd1c1c98a2ddca1bdcce998
Author: Eric Botcazou 
Date:   Mon Oct 14 11:57:57 2024 +0200

Add regression test

gcc/testsuite/
PR ada/114593
* gnat.dg/specs/generic_inst2-child2.ads: New test.
* gnat.dg/specs/generic_inst2.ads: New helper.
* gnat.dg/specs/generic_inst2-child1.ads: Likewise.

Diff:
---
 gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads | 17 +
 gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads | 10 ++
 gcc/testsuite/gnat.dg/specs/generic_inst2.ads| 11 +++
 3 files changed, 38 insertions(+)

diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
new file mode 100644
index ..18e212b2e58c
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
@@ -0,0 +1,17 @@
+generic
+package Generic_Inst2.Child1 is
+
+   function Get_Custom return Custom_Type;
+
+private
+
+   type Dummy is null record;
+
+   Placeholder : constant Dummy := (null record);
+
+   -- This type conversion fails (though only when
+   -- instantiated in the other package)
+   function Get_Custom return Custom_Type is 
+  (Custom_Type(Placeholder'Address));
+
+end Generic_Inst2.Child1;
diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
new file mode 100644
index ..3bb5b0aca107
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
@@ -0,0 +1,10 @@
+-- { dg-do compile }
+
+with Generic_Inst2.Child1;
+
+generic
+package Generic_Inst2.Child2 is
+
+   package Second is new Generic_Inst2.Child1;
+
+end Generic_Inst2.Child2;
diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2.ads
new file mode 100644
index ..0a74e36273bd
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2.ads
@@ -0,0 +1,11 @@
+private with System;
+
+package Generic_Inst2 is
+
+   type Custom_Type is private;
+
+private
+
+   type Custom_Type is new System.Address;
+
+end Generic_Inst2;

[gcc r12-10764] ada: Type conversion in instance incorrectly rejected.

2024-10-14 Thread Eric Botcazou via Gcc-cvs

https://gcc.gnu.org/g:fb61a7a203c5de3552e11bd633bc351463e51594

commit r12-10764-gfb61a7a203c5de3552e11bd633bc351463e51594
Author: Steve Baird 
Date:   Mon Jul 8 14:45:55 2024 -0700

ada: Type conversion in instance incorrectly rejected.

In some cases, a legal type conversion in a generic package is correctly
accepted but the corresponding type conversion in an instance of the generic
is incorrectly rejected.

gcc/ada/
PR ada/114593
* sem_res.adb (Valid_Conversion): Test In_Instance instead of
In_Instance_Body.

Diff:
---
 gcc/ada/sem_res.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 09a2d8adb507..7dde7538734e 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -14273,7 +14273,7 @@ package body Sem_Res is
 
   --  If it was legal in the generic, it's legal in the instance
 
-  elsif In_Instance_Body then
+  elsif In_Instance then
  return True;
 
   --  If both are tagged types, check legality of view conversions

[gcc r13-9106] Add regression test

2024-10-14 Thread Eric Botcazou via Gcc-cvs

https://gcc.gnu.org/g:19e7179f654e4d6192a8460425c8ac69221d8a7b

commit r13-9106-g19e7179f654e4d6192a8460425c8ac69221d8a7b
Author: Eric Botcazou 
Date:   Mon Oct 14 11:57:57 2024 +0200

Add regression test

gcc/testsuite/
PR ada/114593
* gnat.dg/specs/generic_inst2-child2.ads: New test.
* gnat.dg/specs/generic_inst2.ads: New helper.
* gnat.dg/specs/generic_inst2-child1.ads: Likewise.

Diff:
---
 gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads | 17 +
 gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads | 10 ++
 gcc/testsuite/gnat.dg/specs/generic_inst2.ads| 11 +++
 3 files changed, 38 insertions(+)

diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
new file mode 100644
index ..18e212b2e58c
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
@@ -0,0 +1,17 @@
+generic
+package Generic_Inst2.Child1 is
+
+   function Get_Custom return Custom_Type;
+
+private
+
+   type Dummy is null record;
+
+   Placeholder : constant Dummy := (null record);
+
+   -- This type conversion fails (though only when
+   -- instantiated in the other package)
+   function Get_Custom return Custom_Type is 
+  (Custom_Type(Placeholder'Address));
+
+end Generic_Inst2.Child1;
diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
new file mode 100644
index ..3bb5b0aca107
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
@@ -0,0 +1,10 @@
+-- { dg-do compile }
+
+with Generic_Inst2.Child1;
+
+generic
+package Generic_Inst2.Child2 is
+
+   package Second is new Generic_Inst2.Child1;
+
+end Generic_Inst2.Child2;
diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2.ads
new file mode 100644
index ..0a74e36273bd
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2.ads
@@ -0,0 +1,11 @@
+private with System;
+
+package Generic_Inst2 is
+
+   type Custom_Type is private;
+
+private
+
+   type Custom_Type is new System.Address;
+
+end Generic_Inst2;

[gcc r13-9105] ada: Type conversion in instance incorrectly rejected.

2024-10-14 Thread Eric Botcazou via Gcc-cvs

https://gcc.gnu.org/g:3288028d0db7ef2152dc62056516d35722fb6590

commit r13-9105-g3288028d0db7ef2152dc62056516d35722fb6590
Author: Steve Baird 
Date:   Mon Jul 8 14:45:55 2024 -0700

ada: Type conversion in instance incorrectly rejected.

In some cases, a legal type conversion in a generic package is correctly
accepted but the corresponding type conversion in an instance of the generic
is incorrectly rejected.

gcc/ada/
PR ada/114593
* sem_res.adb (Valid_Conversion): Test In_Instance instead of
In_Instance_Body.

Diff:
---
 gcc/ada/sem_res.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index dce35a71ddaa..01ff1f9a97e1 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -14672,7 +14672,7 @@ package body Sem_Res is
 
   --  If it was legal in the generic, it's legal in the instance
 
-  elsif In_Instance_Body then
+  elsif In_Instance then
  return True;
 
   --  If both are tagged types, check legality of view conversions

[gcc r15-4324] middle-end: support SLP early break

2024-10-14 Thread Tamar Christina via Gcc-cvs

https://gcc.gnu.org/g:accb85345edb91368221fd07b74e74df427b7de0

commit r15-4324-gaccb85345edb91368221fd07b74e74df427b7de0
Author: Tamar Christina 
Date:   Mon Oct 14 11:58:59 2024 +0100

middle-end: support SLP early break

This patch introduces feature parity for early break int the SLP only
vectorizer.

The approach taken here is to treat the early exits as root statements for 
an
SLP tree.  This means that we don't need any changes to build_slp to support
gconds.

Codegen for the gcond itself now has to be done out of line but the body of 
the
SLP blocks itself is simply driven by SLP scheduling.  There is a slight
awkwardness in having re-used vectorizable_early_exit for both SLP and 
non-SLP
but I've documented the differences and when I did try to refactor it it 
wasn't
really worth it given that this is a temporary state anyway.

This version is restricted to lane = 1, as such we can re-use the existing
move_early_break function instead of having to do safety update through
scheduling.  I have a branch where I'm working on that but lane > 1 is out 
of
scope for GCC 15 anyway.   The only reason I will try to get moving through
scheduling done as a stretch goal is so we get epilogue vectorization back 
for
early break.

The example:

unsigned test4(unsigned x)
{
 unsigned ret = 0;
 for (int i = 0; i < N; i++)
 {
   vect_b[i] = x + i;
   if (vect_a[i]*2 != x)
 break;
   vect_a[i] = x;

 }
 return ret;
}

builds the following SLP instance for early break:

note:   Analyzing vectorizable control flow: if (patt_6 != 0)
note:   Starting SLP discovery for
note: patt_6 = _4 != x_9(D);
note:   starting SLP discovery for node 0x63abc80
note:   Build SLP for patt_6 = _4 != x_9(D);
note:   precomputed vectype: vector(4) 
note:   nunits = 4
note:   vect_is_simple_use: operand x_9(D), type of def: external
note:   vect_is_simple_use: operand # RANGE [irange] unsigned int [0, 0][2, 
+INF] MASK 0x
_3 * 2, type of def: internal
note:   starting SLP discovery for node 0x63abdc0
note:   Build SLP for _4 = _3 * 2;
note:   precomputed vectype: vector(4) unsigned int
note:   nunits = 4
note:   vect_is_simple_use: operand #
vect_aD.4416[i_15], type of def: internal
note:   vect_is_simple_use: operand 2, type of def: constant
note:   starting SLP discovery for node 0x63abe60
note:   Build SLP for _3 = vect_a[i_15];
note:   precomputed vectype: vector(4) unsigned int
note:   nunits = 4
note:   SLP discovery for node 0x63abe60 succeeded
note:   SLP discovery for node 0x63abdc0 succeeded
note:   SLP discovery for node 0x63abc80 succeeded
note:   SLP size 3 vs. limit 10.
note:   Final SLP tree for instance 0x6474190:
note:   node 0x63abc80 (max_nunits=4, refcnt=2) vector(4) 

note:   op template: patt_6 = _4 != x_9(D);
note:   stmt 0 patt_6 = _4 != x_9(D);
note:   children 0x63abd20 0x63abdc0
note:   node (external) 0x63abd20 (max_nunits=1, refcnt=1)
note:   { x_9(D) }
note:   node 0x63abdc0 (max_nunits=4, refcnt=2) vector(4) unsigned int
note:   op template: _4 = _3 * 2;
note:   stmt 0 _4 = _3 * 2;
note:   children 0x63abe60 0x63abf00
note:   node 0x63abe60 (max_nunits=4, refcnt=2) vector(4) unsigned int
note:   op template: _3 = vect_a[i_15];
note:   stmt 0 _3 = vect_a[i_15];
note:   load permutation { 0 }
note:   node (constant) 0x63abf00 (max_nunits=1, refcnt=1)
note:   { 2 }

and during codegen:

note:   -->vectorizing SLP node starting from: patt_6 = _4 != x_9(D);
note:   vect_is_simple_use: operand # RANGE [irange] unsigned int [0, 0][2, 
+INF] MASK 0x
_3 * 2, type of def: internal
note:   add new stmt: mask_patt_6.18_58 = _53 != vect__4.17_57;
note:=== vectorizable_early_exit ===
note:transform early-exit.
note:   vectorizing stmts using SLP.
note:   Vectorizing SLP tree:
note:   node 0x63abfa0 (max_nunits=4, refcnt=1) vector(4) int
note:   op template: i_12 = i_15 + 1;
note:   stmt 0 i_12 = i_15 + 1;
note:   children 0x63aba00 0x63ac040
note:   node 0x63aba00 (max_nunits=4, refcnt=2) vector(4) int
note:   op template: i_15 = PHI 
note:   [l] stmt 0 i_15 = PHI 
note:   children (nil) (nil)
note:   node (constant) 0x63ac040 (max_nunits=1, refcnt=1) vector(4) int
note:   { 1 }

gcc/ChangeLog:

* tree-vect-loop.cc (vect_analyze_loop_2): Handle SLP trees with no
children.
* tree-vectorizer.h (enum slp_instance_kind): Add 
slp_inst_kind_gcond.
(LOOP_VINFO_EARLY_BREAKS_LIVE_IVS): New.
(vectorizable

[gcc r15-4310] Match: Support form 3 for vector signed integer SAT_SUB

2024-10-14 Thread Pan Li via Gcc-cvs

https://gcc.gnu.org/g:5920bc841492e04b2bd06426db8620784b263d8d

commit r15-4310-g5920bc841492e04b2bd06426db8620784b263d8d
Author: Pan Li 
Date:   Sat Oct 12 10:34:55 2024 +0800

Match: Support form 3 for vector signed integer SAT_SUB

This patch would like to support the form 3 of the vector signed
integer SAT_SUB.  Aka below example:

Form 3:
  #define DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX) \
  void __attribute__((noinline))   \
  vec_sat_s_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
T minus;   \
bool overflow = __builtin_sub_overflow (x, y, &minus); \
out[i] = overflow ? x < 0 ? MIN : MAX : minus; \
  }\
  }

Before this patch:
  25   │   if (limit_11(D) != 0)
  26   │ goto ; [89.00%]
  27   │   else
  28   │ goto ; [11.00%]
  29   │ ;;succ:   3
  30   │ ;;8
  31   │
  32   │ ;;   basic block 3, loop depth 0
  33   │ ;;pred:   2
  34   │   _13 = (unsigned long) limit_11(D);
  35   │ ;;succ:   4
  36   │
  37   │ ;;   basic block 4, loop depth 1
  38   │ ;;pred:   3
  39   │ ;;7
  40   │   # ivtmp.7_34 = PHI <0(3), ivtmp.7_30(7)>
  41   │   _26 = op_1_12(D) + ivtmp.7_34;
  42   │   x_29 = MEM[(int8_t *)_26];
  43   │   _1 = op_2_14(D) + ivtmp.7_34;
  44   │   y_24 = MEM[(int8_t *)_1];
  45   │   _9 = .SUB_OVERFLOW (x_29, y_24);
  46   │   _7 = IMAGPART_EXPR <_9>;
  47   │   if (_7 != 0)
  48   │ goto ; [50.00%]
  49   │   else
  50   │ goto ; [50.00%]
  51   │ ;;succ:   6
  52   │ ;;5
  53   │
  54   │ ;;   basic block 5, loop depth 1
  55   │ ;;pred:   4
  56   │   _42 = REALPART_EXPR <_9>;
  57   │   _2 = out_17(D) + ivtmp.7_34;
  58   │   MEM[(int8_t *)_2] = _42;
  59   │   ivtmp.7_27 = ivtmp.7_34 + 1;
  60   │   if (_13 != ivtmp.7_27)
  61   │ goto ; [89.00%]
  62   │   else
  63   │ goto ; [11.00%]
  64   │ ;;succ:   7
  65   │ ;;8
  66   │
  67   │ ;;   basic block 6, loop depth 1
  68   │ ;;pred:   4
  69   │   _38 = x_29 < 0;
  70   │   _39 = (signed char) _38;
  71   │   _40 = -_39;
  72   │   _41 = _40 ^ 127;
  73   │   _33 = out_17(D) + ivtmp.7_34;
  74   │   MEM[(int8_t *)_33] = _41;
  75   │   ivtmp.7_25 = ivtmp.7_34 + 1;
  76   │   if (_13 != ivtmp.7_25)
  77   │ goto ; [89.00%]
  78   │   else
  79   │ goto ; [11.00%]

After this patch:
  77   │   _94 = .SELECT_VL (ivtmp_92, POLY_INT_CST [16, 16]);
  78   │   vect_x_13.9_81 = .MASK_LEN_LOAD (vectp_op_1.7_79, 8B, { -1, ... 
}, _94, 0);
  79   │   vect_y_15.12_85 = .MASK_LEN_LOAD (vectp_op_2.10_83, 8B, { -1, 
... }, _94, 0);
  80   │   vect_patt_49.13_86 = .SAT_SUB (vect_x_13.9_81, vect_y_15.12_85);
  81   │   .MASK_LEN_STORE (vectp_out.14_88, 8B, { -1, ... }, _94, 0, 
vect_patt_49.13_86);
  82   │   vectp_op_1.7_80 = vectp_op_1.7_79 + _94;
  83   │   vectp_op_2.10_84 = vectp_op_2.10_83 + _94;
  84   │   vectp_out.14_89 = vectp_out.14_88 + _94;
  85   │   ivtmp_93 = ivtmp_92 - _94;

The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Add matching pattern for vector signed SAT_SUB form 3.

Signed-off-by: Pan Li 

Diff:
---
 gcc/match.pd | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/match.pd b/gcc/match.pd
index eff1ace87f54..2814618124d7 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3417,6 +3417,18 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
@2)
  (if (INTEGRAL_TYPE_P (type) && !TYPE_UNSIGNED (type
 
+/* Signed saturation sub, case 5:
+   Z = .SUB_OVERFLOW (X, Y)
+   SAT_S_SUB = IMAGPART_EXPR (Z) != 0 ? (-(T)(X < 0) ^ MAX) : minus;  */
+(match (signed_integer_sat_sub @0 @1)
+ (cond^ (ne (imagpart (IFN_SUB_OVERFLOW:c@2 @0 @1)) integer_zerop)
+   (bit_xor:c (nop_convert?
+   (negate (nop_convert? (convert (lt @0 integer_zerop)
+  m

[gcc r15-4311] RISC-V: Add testcases for form 3 of vector signed SAT_SUB

2024-10-14 Thread Pan Li via Gcc-cvs

https://gcc.gnu.org/g:b97629226d9be496bc30bb13608ef1c2bcdceeb7

commit r15-4311-gb97629226d9be496bc30bb13608ef1c2bcdceeb7
Author: Pan Li 
Date:   Sat Oct 12 10:40:30 2024 +0800

RISC-V: Add testcases for form 3 of vector signed SAT_SUB

Form 3:
  #define DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX) \
  void __attribute__((noinline))   \
  vec_sat_s_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
T minus;   \
bool overflow = __builtin_sub_overflow (x, y, &minus); \
out[i] = overflow ? x < 0 ? MIN : MAX : minus; \
  }\
  }

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper 
macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i16.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i32.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i64.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-3-i16.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-3-i32.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-3-i64.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-3-i8.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-3-i16.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-3-i32.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-3-i64.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-3-i8.c   |  9 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-3-i16.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-3-i32.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-3-i64.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-3-i8.c | 17 +
 .../gcc.target/riscv/rvv/autovec/vec_sat_arith.h   | 22 ++
 9 files changed, 126 insertions(+)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i16.c
new file mode 100644
index ..c10dc0903c45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i32.c
new file mode 100644
index ..d1352ed56e4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i64.c
new file mode 100644
index ..b86887d332bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times

[gcc r15-4312] RISC-V: Add testcases for form 4 of vector signed SAT_SUB

2024-10-14 Thread Pan Li via Gcc-cvs

https://gcc.gnu.org/g:4d8373f853269cd3a6f99ad0cb774fccd68cb874

commit r15-4312-g4d8373f853269cd3a6f99ad0cb774fccd68cb874
Author: Pan Li 
Date:   Sat Oct 12 11:08:21 2024 +0800

RISC-V: Add testcases for form 4 of vector signed SAT_SUB

Form 4:
  #define DEF_VEC_SAT_S_SUB_FMT_4(T, UT, MIN, MAX) \
  void __attribute__((noinline))   \
  vec_sat_s_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
T minus;   \
bool overflow = __builtin_sub_overflow (x, y, &minus); \
out[i] = !overflow ? minus : x < 0 ? MIN : MAX;\
  }\
  }

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper 
macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i16.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i32.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i64.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-4-i16.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-4-i32.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-4-i64.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-4-i8.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-4-i16.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-4-i32.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-4-i64.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-4-i8.c   |  9 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-4-i16.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-4-i32.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-4-i64.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-4-i8.c | 17 +
 .../gcc.target/riscv/rvv/autovec/vec_sat_arith.h   | 22 ++
 9 files changed, 126 insertions(+)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i16.c
new file mode 100644
index ..4497f0c1f83c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i32.c
new file mode 100644
index ..9f06e6a76509
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i64.c
new file mode 100644
index ..e806fd06c003
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times

[gcc r15-4309] RISC-V: Add testcases for form 2 of vector signed SAT_SUB

2024-10-14 Thread Pan Li via Gcc-cvs

https://gcc.gnu.org/g:72d24d2a130a54fbe1479cb85e5639a7eab6c971

commit r15-4309-g72d24d2a130a54fbe1479cb85e5639a7eab6c971
Author: Pan Li 
Date:   Sat Oct 12 09:13:54 2024 +0800

RISC-V: Add testcases for form 2 of vector signed SAT_SUB

Form 2:
  #define DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) \
  void __attribute__((noinline))   \
  vec_sat_s_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
T minus = (UT)x - (UT)y;   \
out[i] = (x ^ y) >= 0 || (minus ^ x) >= 0  \
  ? minus : x < 0 ? MIN : MAX; \
  }\
  }

DEF_VEC_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper 
macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i16.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i32.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i64.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i8.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c  |  9 +
 .../riscv/rvv/autovec/binop/vec_sat_s_sub-2-i8.c   |  9 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-2-i16.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-2-i32.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-2-i64.c| 17 +
 .../rvv/autovec/binop/vec_sat_s_sub-run-2-i8.c | 17 +
 .../gcc.target/riscv/rvv/autovec/vec_sat_arith.h   | 22 ++
 9 files changed, 126 insertions(+)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c
new file mode 100644
index ..dec0359c5ed9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c
new file mode 100644
index ..72b2d6778cca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c
new file mode 100644
index ..3ca44589e427
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-rtl-dump-time

[gcc r15-4319] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

2024-10-14 Thread Kito Cheng via Gcc-cvs

https://gcc.gnu.org/g:ca44eb7f6a33ff3b93e7685606b4fc286ce0fe80

commit r15-4319-gca44eb7f6a33ff3b93e7685606b4fc286ce0fe80
Author: Kito Cheng 
Date:   Mon Oct 14 16:07:16 2024 +0800

RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and 
__riscv_vendor_feature_bits

This provides a common abstraction layer to probe the available extensions 
at
run-time. These functions can be used to implement function 
multi-versioning or
to detect available extensions.

The advantages of providing this abstraction layer are:
- Easy to port to other new platforms.
- Easier to maintain in GCC for function multi-versioning.
  - For example, maintaining platform-dependent code in C code/libgcc is 
much
easier than maintaining it in GCC by creating GIMPLEs...

This API is intended to provide the capability to query minimal common 
available extensions on the system.

The API is defined in the riscv-c-api-doc:
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc

Proposal to use unsigned long long for marchid and mimpid:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/91

Full function multi-versioning implementation will come later. We are 
posting
this first because we intend to backport it to the GCC 14 branch to unblock
LLVM 19 to use this with GCC 14.2, rather than waiting for GCC 15.

Changes since v7:
- Remove vendorID field in __riscv_vendor_feature_bits.
- Fix C implies Zcf only for RV32.
- Add more comments to kernel versions.

Changes since v6:
- Implement __riscv_cpu_model.
- Set new sub extension bits which implied from previous extensions.

Changes since v5:
- Minor fixes on indentation.

Changes since v4:
- Bump to newest riscv-c-api-doc with some new extensions like Zve*, Zc*
  Zimop, Zcmop, Zawrs.
- Rename the return variable name of hwprobe syscall.
- Minor fixes on indentation.

Changes since v3:
- Fix non-linux build.
- Let __init_riscv_feature_bits become constructor

Changes since v2:
- Prevent it initialize more than once.

Changes since v1:
- Fix the format.
- Prevented race conditions by introducing a local variable to avoid 
load/store
  operations during the computation of the feature bit.

Co-Developed-by: Yangyu Chen 
Signed-off-by: Yangyu Chen 

libgcc/ChangeLog:

* config/riscv/feature_bits.c: New.
* config/riscv/t-elf (LIB2ADD): Add feature_bits.c.

Diff:
---
 libgcc/config/riscv/feature_bits.c | 409 +
 libgcc/config/riscv/t-elf  |   1 +
 2 files changed, 410 insertions(+)

diff --git a/libgcc/config/riscv/feature_bits.c 
b/libgcc/config/riscv/feature_bits.c
new file mode 100644
index ..9bdbc466feea
--- /dev/null
+++ b/libgcc/config/riscv/feature_bits.c
@@ -0,0 +1,409 @@
+/* Helper function for function multi-versioning for RISC-V.
+
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+.  */
+
+#define RISCV_FEATURE_BITS_LENGTH 2
+
+struct {
+  unsigned length;
+  unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
+} __riscv_feature_bits __attribute__ ((visibility ("hidden"), nocommon));
+
+#define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
+
+struct {
+  unsigned length;
+  unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
+} __riscv_vendor_feature_bits __attribute__ ((visibility ("hidden"), 
nocommon));
+
+struct {
+  unsigned mvendorid;
+  unsigned long long marchid;
+  unsigned long long mimpid;
+} __riscv_cpu_model __attribute__ ((visibility ("hidden"), nocommon));
+
+#define A_GROUPID 0
+#define A_BITMASK (1ULL << 0)
+#define C_GROUPID 0
+#define C_BITMASK (1ULL << 2)
+#define D_GROUPID 0
+#define D_BITMASK (1ULL << 3)
+#define F_GROUPID 0
+#define F_BITMASK (1ULL << 5)
+#define I_GROUPID 0
+#define I_BITMASK (1ULL << 8)
+#define M_GROUPID 0
+#define M_BITMASK (1ULL << 12)
+#define V_GROUPID 0
+#define V_BITMASK (1ULL << 21)
+#d

[gcc r15-4321] libstdc++: Enable memset optimizations for distinct character types [PR93059]

2024-10-14 Thread Jonathan Wakely via Libstdc++-cvs

https://gcc.gnu.org/g:d8ef4471cb9c9f86784b62424a215ea42173bfe1

commit r15-4321-gd8ef4471cb9c9f86784b62424a215ea42173bfe1
Author: Jonathan Wakely 
Date:   Thu Oct 10 13:36:33 2024 +0100

libstdc++: Enable memset optimizations for distinct character types 
[PR93059]

Currently we only optimize std::fill to memset when the source and
destination types are the same byte-sized type. This means that we fail
to optimize cases like std::fill(buf. buf+n, 0) because the literal 0 is
not the same type as the character buffer.

Such cases can safely be optimized to use memset, because assigning an
int (or other integer) to a narrow character type has the same effects
as converting the integer to unsigned char then copying it with memset.

This patch enables the optimized code path when the fill character is a
memcpy-able integer (using the new __memcpyable_integer trait). We still
need to check is_same to enable the memset optimization for
filling a range of std::byte with a std::byte value, because that isn't
a memcpyable integer.

libstdc++-v3/ChangeLog:

PR libstdc++/93059
* include/bits/stl_algobase.h (__fill_a1(T*, T*, const T&)):
Change template parameters and enable_if condition to allow the
fill value to be an integer.

Diff:
---
 libstdc++-v3/include/bits/stl_algobase.h | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/libstdc++-v3/include/bits/stl_algobase.h 
b/libstdc++-v3/include/bits/stl_algobase.h
index 9e92211c1246..384e5fdcdc99 100644
--- a/libstdc++-v3/include/bits/stl_algobase.h
+++ b/libstdc++-v3/include/bits/stl_algobase.h
@@ -967,23 +967,27 @@ _GLIBCXX_END_NAMESPACE_CONTAINER
 #pragma GCC diagnostic pop
 
   // Specialization: for char types we can use memset.
-  template
+  template
 _GLIBCXX20_CONSTEXPR
 inline typename
-__gnu_cxx::__enable_if<__is_byte<_Tp>::__value, void>::__type
-__fill_a1(_Tp* __first, _Tp* __last, const _Tp& __c)
-{
-  const _Tp __tmp = __c;
+__gnu_cxx::__enable_if<__is_byte<_Up>::__value
+&& (__are_same<_Up, _Tp>::__value // for std::byte
+  || __memcpyable_integer<_Tp>::__value),
+  void>::__type
+__fill_a1(_Up* __first, _Up* __last, const _Tp& __x)
+{
+  // This hoists the load out of the loop and also ensures that we don't
+  // use memset for cases where the assignment would be ill-formed.
+  const _Up __val = __x;
 #if __cpp_lib_is_constant_evaluated
   if (std::is_constant_evaluated())
{
  for (; __first != __last; ++__first)
-   *__first = __tmp;
- return;
+   *__first = __val;
}
 #endif
   if (const size_t __len = __last - __first)
-   __builtin_memset(__first, static_cast(__tmp), __len);
+   __builtin_memset(__first, static_cast(__val), __len);
 }
 
   template

[gcc r15-4320] libstdc++: Enable memcpy optimizations for distinct integral types [PR93059]

2024-10-14 Thread Jonathan Wakely via Gcc-cvs

https://gcc.gnu.org/g:308d19c11e119b2c5abf67778dd0ac8a370e5df7

commit r15-4320-g308d19c11e119b2c5abf67778dd0ac8a370e5df7
Author: Jonathan Wakely 
Date:   Thu Oct 10 13:36:33 2024 +0100

libstdc++: Enable memcpy optimizations for distinct integral types [PR93059]

Currently we only optimize std::copy, std::copy_n etc. to memmove when
the source and destination types are the same. This means that we fail
to optimize copying between distinct 1-byte types, e.g. copying from a
buffer of unsigned char to a buffer of char8_t or vice versa.

This patch adds more partial specializations of the __memcpyable trait
so that we allow memcpy between integers of equal widths. This will
enable memmove for copies between narrow character types and also
between same-width types like int and unsigned.

Enabling the optimization needs to be based on the width of the integer
type, not just the size in bytes. This is because some targets define
non-standard integral types such as __int20 in msp430, which has padding
bits. It would not be safe to memcpy between e.g. __int20 and int32_t,
even though sizeof(__int20) == sizeof(int32_t). A new trait is
introduced to define the width, __memcpyable_integer, and then the
__memcpyable trait compares the widths.

It's safe to copy between signed and unsigned integers of the same
width, because GCC only supports two's complement integers.

I initially though it would be useful to define the specialization
__memcpyable_integer to enable copying between narrow character
types and std::byte. But that isn't possible with std::copy, because
is_assignable is false. Optimized copies using memmove
will already happen for copying std::byte to std::byte, because
__memcpyable is true.

libstdc++-v3/ChangeLog:

PR libstdc++/93059
* include/bits/cpp_type_traits.h (__memcpyable): Add partial
specialization for pointers to distinct types.
(__memcpyable_integer): New trait to control which types can use
cross-type memcpy optimizations.

Diff:
---
 libstdc++-v3/include/bits/cpp_type_traits.h | 89 -
 1 file changed, 87 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/include/bits/cpp_type_traits.h 
b/libstdc++-v3/include/bits/cpp_type_traits.h
index 060652afb183..2f9ce75e82c2 100644
--- a/libstdc++-v3/include/bits/cpp_type_traits.h
+++ b/libstdc++-v3/include/bits/cpp_type_traits.h
@@ -434,8 +434,6 @@ __INT_N(__GLIBCXX_TYPE_INT_N_3)
 };
 #endif
 
-  template struct iterator_traits;
-
   // A type that is safe for use with memcpy, memmove, memcmp etc.
   template
 struct __is_nonvolatile_trivially_copyable
@@ -459,16 +457,103 @@ __INT_N(__GLIBCXX_TYPE_INT_N_3)
   enum { __value = 0 };
 };
 
+  // Allow memcpy when source and destination are pointers to the same type.
   template
 struct __memcpyable<_Tp*, _Tp*>
 : __is_nonvolatile_trivially_copyable<_Tp>
 { };
 
+  // Source pointer can be const.
   template
 struct __memcpyable<_Tp*, const _Tp*>
 : __is_nonvolatile_trivially_copyable<_Tp>
 { };
 
+  template struct __memcpyable_integer;
+
+  // For heterogeneous types, allow memcpy between equal-sized integers.
+  template
+struct __memcpyable<_Tp*, _Up*>
+{
+  enum {
+   __value = __memcpyable_integer<_Tp>::__width != 0
+   && ((int)__memcpyable_integer<_Tp>::__width
+ == (int)__memcpyable_integer<_Up>::__width)
+  };
+};
+
+  // Specialization for const U* because __is_integer is never true.
+  template
+struct __memcpyable<_Tp*, const _Up*>
+: __memcpyable<_Tp*, _Up*>
+{ };
+
+  template
+struct __memcpyable_integer
+{
+  enum {
+   __width = __is_integer<_Tp>::__value ? (sizeof(_Tp) * __CHAR_BIT__) : 0
+  };
+};
+
+  // Cannot memcpy volatile memory.
+  template
+struct __memcpyable_integer
+{ enum { __width = 0 }; };
+
+  // Specializations for __intNN types with padding bits.
+#if defined __GLIBCXX_TYPE_INT_N_0 && __GLIBCXX_BITSIZE_INT_N_0 % __CHAR_BIT__
+  __extension__
+  template<>
+struct __memcpyable_integer<__GLIBCXX_TYPE_INT_N_0>
+{ enum { __width = __GLIBCXX_BITSIZE_INT_N_0 }; };
+  __extension__
+  template<>
+struct __memcpyable_integer
+{ enum { __width = __GLIBCXX_BITSIZE_INT_N_0 }; };
+#endif
+#if defined __GLIBCXX_TYPE_INT_N_1 && __GLIBCXX_BITSIZE_INT_N_1 % __CHAR_BIT__
+  __extension__
+  template<>
+struct __memcpyable_integer<__GLIBCXX_TYPE_INT_N_1>
+{ enum { __width = __GLIBCXX_BITSIZE_INT_N_1 }; };
+  __extension__
+  template<>
+struct __memcpyable_integer
+{ enum { __width = __GLIBCXX_BITSIZE_INT_N_1 }; };
+#endif
+#if defined __GLIBCXX_TYPE_INT_N_2 && __GLIBCXX_BITSIZE_INT_N_2 % __CHAR_BIT__
+  __extension__
+  template<>
+struct __memcpyable_integer<__GLIBCXX_TYPE_INT_N_2>
+

[gcc r15-4316] aarch64: Fix folding of degenerate svwhilele case [PR117045]

2024-10-14 Thread Richard Sandiford via Gcc-cvs

https://gcc.gnu.org/g:50e7c51b0a0e9dc1d93f829016ae743b4f2e5070

commit r15-4316-g50e7c51b0a0e9dc1d93f829016ae743b4f2e5070
Author: Richard Sandiford 
Date:   Mon Oct 14 09:52:44 2024 +0100

aarch64: Fix folding of degenerate svwhilele case [PR117045]

The svwhilele folder mishandled the degenerate case in which
the second argument is the maximum integer.  In that case,
the result is all-true regardless of the first parameter:

  If the second scalar operand is equal to the maximum signed integer
  value then a condition which includes an equality test can never fail
  and the result will be an all-true predicate.

This is because the conceptual "increment the first operand
by 1 after each element" is done modulo the range of the operand.
The GCC code was instead treating it as infinite precision.
whilele_5.c even had a test for the incorrect behaviour.

The easiest fix seemed to be to handle that case specially before
doing constant folding.  This also copes with variable first operands.

gcc/
PR target/116999
PR target/117045
* config/aarch64/aarch64-sve-builtins-base.cc
(svwhilelx_impl::fold): Check for WHILELTs of the minimum value
and WHILELEs of the maximum value.  Fold them to all-false and
all-true respectively.

gcc/testsuite/
PR target/116999
PR target/117045
* gcc.target/aarch64/sve/acle/general/whilele_5.c: Fix bogus
expected result.
* gcc.target/aarch64/sve/acle/general/whilele_11.c: New test.
* gcc.target/aarch64/sve/acle/general/whilele_12.c: Likewise.

Diff:
---
 gcc/config/aarch64/aarch64-sve-builtins-base.cc| 11 ++-
 .../aarch64/sve/acle/general/whilele_11.c  | 31 
 .../aarch64/sve/acle/general/whilele_12.c  | 34 ++
 .../aarch64/sve/acle/general/whilele_5.c   |  2 +-
 4 files changed, 76 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc 
b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index b189818d6430..5210f41c0130 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -2945,7 +2945,9 @@ public:
 : while_comparison (unspec_for_sint, unspec_for_uint), m_eq_p (eq_p)
   {}
 
-  /* Try to fold a call by treating its arguments as constants of type T.  */
+  /* Try to fold a call by treating its arguments as constants of type T.
+ We have already filtered out the degenerate cases of X .LT. MIN
+ and X .LE. MAX.  */
   template
   gimple *
   fold_type (gimple_folder &f) const
@@ -3001,6 +3003,13 @@ public:
 if (f.vectors_per_tuple () > 1)
   return nullptr;
 
+/* Filter out cases where the condition is always true or always false.  */
+tree arg1 = gimple_call_arg (f.call, 1);
+if (!m_eq_p && operand_equal_p (arg1, TYPE_MIN_VALUE (TREE_TYPE (arg1
+  return f.fold_to_pfalse ();
+if (m_eq_p && operand_equal_p (arg1, TYPE_MAX_VALUE (TREE_TYPE (arg1
+  return f.fold_to_ptrue ();
+
 if (f.type_suffix (1).unsigned_p)
   return fold_type (f);
 else
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_11.c 
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_11.c
new file mode 100644
index ..2be9dc5c5347
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_11.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include 
+#include 
+
+svbool_t
+f1 (volatile int32_t *ptr)
+{
+  return svwhilelt_b8_s32 (*ptr, INT32_MIN);
+}
+
+svbool_t
+f2 (volatile uint32_t *ptr)
+{
+  return svwhilelt_b16_u32 (*ptr, 0);
+}
+
+svbool_t
+f3 (volatile int64_t *ptr)
+{
+  return svwhilelt_b32_s64 (*ptr, INT64_MIN);
+}
+
+svbool_t
+f4 (volatile uint64_t *ptr)
+{
+  return svwhilelt_b64_u64 (*ptr, 0);
+}
+
+/* { dg-final { scan-assembler-times {\tpfalse\tp[0-9]+\.b\n} 4 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_12.c 
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_12.c
new file mode 100644
index ..713065c31453
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_12.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include 
+#include 
+
+svbool_t
+f1 (volatile int32_t *ptr)
+{
+  return svwhilele_b8_s32 (*ptr, INT32_MAX);
+}
+
+svbool_t
+f2 (volatile uint32_t *ptr)
+{
+  return svwhilele_b16_u32 (*ptr, UINT32_MAX);
+}
+
+svbool_t
+f3 (volatile int64_t *ptr)
+{
+  return svwhilele_b32_s64 (*ptr, INT64_MAX);
+}
+
+svbool_t
+f4 (volatile uint64_t *ptr)
+{
+  return svwhilele_b64_u64 (*ptr, UINT64_MAX);
+}
+
+/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.b(?:, all)\n} } } */
+/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.h(?:, all)\n} } } */
+/* { dg-final { scan-assem

[gcc r15-4317] middle-end: [PR middle-end/116926] Allow widening optabs for vec-mode -> scalar-mode

2024-10-14 Thread Victor Do Nascimento via Gcc-cvs

https://gcc.gnu.org/g:a6f4404689f12fa169540d94c0d06532c7152c2f

commit r15-4317-ga6f4404689f12fa169540d94c0d06532c7152c2f
Author: Victor Do Nascimento 
Date:   Thu Oct 10 12:55:04 2024 +0100

middle-end: [PR middle-end/116926] Allow widening optabs for vec-mode -> 
scalar-mode

The recent refactoring of the dot_prod optab to convert-type exposed a
limitation in how `find_widening_optab_handler_and_mode' is currently
implemented, owing to the fact that, while the function expects the

  GET_MODE_CLASS (from_mode) == GET_MODE_CLASS (to_mode)

condition to hold, the c6x backend implements a dot product from V2HI
to SI, which triggers an ICE.

Consequently, this patch adds some logic to allow widening optabs
which accumulate vector elements to a single scalar.

gcc/ChangeLog:

PR middle-end/116926
* optabs-query.cc (find_widening_optab_handler_and_mode): Add
handling of vector -> scalar optab handling.

Diff:
---
 gcc/optabs-query.cc | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/gcc/optabs-query.cc b/gcc/optabs-query.cc
index c3134d6a2cee..cc52bc0f5ea7 100644
--- a/gcc/optabs-query.cc
+++ b/gcc/optabs-query.cc
@@ -485,6 +485,12 @@ find_widening_optab_handler_and_mode (optab op, 
machine_mode to_mode,
   if (GET_MODE_CLASS (limit_mode) == MODE_PARTIAL_INT)
limit_mode = GET_MODE_WIDER_MODE (limit_mode).require ();
 }
+  else if (is_a  (to_mode))
+{
+  gcc_checking_assert (VECTOR_MODE_P (from_mode)
+  && GET_MODE_INNER (from_mode) < to_mode);
+  limit_mode = from_mode;
+}
   else
 gcc_checking_assert (GET_MODE_CLASS (from_mode) == GET_MODE_CLASS (to_mode)
 && from_mode < to_mode);

[gcc r15-4318] MAINTAINERS (s390 port): Add myself

2024-10-14 Thread Stefan Schulze Frielinghaus via Gcc-cvs

https://gcc.gnu.org/g:fa04a1713b54bdc4c7b686c88117c9c46043ec73

commit r15-4318-gfa04a1713b54bdc4c7b686c88117c9c46043ec73
Author: Stefan Schulze Frielinghaus 
Date:   Mon Oct 14 11:12:48 2024 +0200

MAINTAINERS (s390 port): Add myself

ChangeLog:

* MAINTAINERS (s390 port): Add myself.

Diff:
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index f94aa9aeb791..cf1cf78e16cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -120,6 +120,7 @@ rs6000 vector extns Aldy Hernandez  

 rx port Nick Clifton
 s390 port   Ulrich Weigand  
 s390 port   Andreas Krebbel 
+s390 port   Stefan Schulze Frielinghaus 
 sh port Alexandre Oliva 
 sh port Oleg Endo   
 sparc port  David S. Miller

[gcc r15-4313] middle-end/116891 - fix (negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)

2024-10-14 Thread Richard Biener via Gcc-cvs

https://gcc.gnu.org/g:c53bd48c6920bc1f4039b6682aafbf414a600e47

commit r15-4313-gc53bd48c6920bc1f4039b6682aafbf414a600e47
Author: Richard Biener 
Date:   Mon Oct 14 08:11:22 2024 +0200

middle-end/116891 - fix (negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)

Transforming -fma (-a, b, -c) to fma (a, b, c) is only valid when
not rounding towards -inf or +inf as the sign of the multiplication
changes.

PR middle-end/116891
* match.pd ((negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)):
Only enable for !HONOR_SIGN_DEPENDENT_ROUNDING.

Diff:
---
 gcc/match.pd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/match.pd b/gcc/match.pd
index 2814618124d7..ee53c25cef97 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -9494,7 +9494,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
   (IFN_FMA @0 @1 @2))
  (simplify
   (negate (IFN_FNMS@3 @0 @1 @2))
-  (if (single_use (@3))
+  (if (!HONOR_SIGN_DEPENDENT_ROUNDING (type) && single_use (@3))
(IFN_FMA @0 @1 @2
 
 /* CLZ simplifications.  */

[gcc r15-4314] Fortran: Use OpenACC's acc_on_device builtin, fix OpenMP' __builtin_is_initial_device: Fix effective

2024-10-14 Thread Thomas Schwinge via Gcc-cvs

https://gcc.gnu.org/g:c3774b2e2d7d00ad9f9f6fce10aa6bc872bd951f

commit r15-4314-gc3774b2e2d7d00ad9f9f6fce10aa6bc872bd951f
Author: Thomas Schwinge 
Date:   Mon Oct 14 10:26:13 2024 +0200

Fortran: Use OpenACC's acc_on_device builtin, fix OpenMP' 
__builtin_is_initial_device: Fix effective-target keyword in 
'libgomp.oacc-fortran/acc_on_device-2.f90'

The test case 'libgomp.oacc-fortran/acc_on_device-2.f90' added in
commit 3269a722b7a03613e9c4e2862bc5088c4a17cc11
"Fortran: Use OpenACC's acc_on_device builtin, fix OpenMP' 
__builtin_is_initial_device"
had a mismatch between dump file production and its scanning; the former 
needs
to use 'offload_target_nvptx' (like 'offload_target_amdgcn'), not
'offload_device_nvptx'.

PR testsuite/82250
libgomp/
* testsuite/libgomp.oacc-fortran/acc_on_device-2.f90: Fix
effective-target keyword.

Diff:
---
 libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-2.f90 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-2.f90 
b/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-2.f90
index 39d4357dd55d..306555cfccf2 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-2.f90
+++ b/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-2.f90
@@ -3,7 +3,7 @@
 ! Check whether 'acc_on_device()' is properly compile-time optimized. */
 
 ! { dg-additional-options "-fdump-tree-gimple -fdump-tree-optimized" }
-! { dg-additional-options -foffload-options=-fdump-tree-optimized { target { 
offload_device_nvptx || offload_target_amdgcn } } }
+! { dg-additional-options -foffload-options=-fdump-tree-optimized { target { 
offload_target_nvptx || offload_target_amdgcn } } }
 
 ! { dg-final { scan-tree-dump-times "acc_on_device" 1 "gimple" } }

[gcc r15-4315] Fortran: Use OpenACC's acc_on_device builtin, fix OpenMP' __builtin_is_initial_device: Harmonize 'li

2024-10-14 Thread Thomas Schwinge via Gcc-cvs

https://gcc.gnu.org/g:9f549d216c9716e787aaa38593bc9f83195b60ae

commit r15-4315-g9f549d216c9716e787aaa38593bc9f83195b60ae
Author: Thomas Schwinge 
Date:   Mon Oct 14 10:34:34 2024 +0200

Fortran: Use OpenACC's acc_on_device builtin, fix OpenMP' 
__builtin_is_initial_device: Harmonize 'libgomp.oacc-fortran/acc_on_device-1-*'

The test case 'libgomp.oacc-fortran/acc_on_device-1-1.f90' added in
commit 3269a722b7a03613e9c4e2862bc5088c4a17cc11
"Fortran: Use OpenACC's acc_on_device builtin, fix OpenMP' 
__builtin_is_initial_device"
was missing '-fno-builtin-acc_on_device', and all
'libgomp.oacc-fortran/acc_on_device-1-*' need comments, why that option is
specified.

PR testsuite/82250
libgomp/
* testsuite/libgomp.oacc-fortran/acc_on_device-1-1.f90: Add
'-fno-builtin-acc_on_device'.
* testsuite/libgomp.oacc-fortran/acc_on_device-1-2.f: Comment.
* testsuite/libgomp.oacc-fortran/acc_on_device-1-3.f: Comment.

Diff:
---
 libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-1.f90 | 3 +++
 libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-2.f   | 5 -
 libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-3.f   | 5 -
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-1.f90 
b/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-1.f90
index 89748204f05a..774c2b869e80 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-1.f90
+++ b/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-1.f90
@@ -1,6 +1,9 @@
 ! { dg-do run }
 ! { dg-additional-options "-cpp" }
 
+! Disable the acc_on_device builtin; we want to test the libgomp library 
function.
+! { dg-additional-options -fno-builtin-acc_on_device }
+
 ! { dg-additional-options "-fopt-info-all-omp" }
 ! { dg-additional-options "--param=openacc-privatization=noisy" }
 ! { dg-additional-options "-foffload=-fopt-info-all-omp" }
diff --git a/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-2.f 
b/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-2.f
index e31e0fc715bd..b57beac6f43d 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-2.f
+++ b/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-2.f
@@ -1,5 +1,8 @@
 ! { dg-do run }
-! { dg-additional-options "-cpp -fno-builtin-acc_on_device" }
+! { dg-additional-options "-cpp" }
+
+! Disable the acc_on_device builtin; we want to test the libgomp library 
function.
+! { dg-additional-options -fno-builtin-acc_on_device }
 
 ! { dg-additional-options "-fopt-info-all-omp" }
 ! { dg-additional-options "--param=openacc-privatization=noisy" }
diff --git a/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-3.f 
b/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-3.f
index 0595be241f8f..969d530e30ff 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-3.f
+++ b/libgomp/testsuite/libgomp.oacc-fortran/acc_on_device-1-3.f
@@ -1,5 +1,8 @@
 ! { dg-do run }
-! { dg-additional-options "-cpp -fno-builtin-acc_on_device" }
+! { dg-additional-options "-cpp" }
+
+! Disable the acc_on_device builtin; we want to test the libgomp library 
function.
+! { dg-additional-options -fno-builtin-acc_on_device }
 
 ! { dg-additional-options "-fopt-info-all-omp" }
 ! { dg-additional-options "--param=openacc-privatization=noisy" }

[gcc(refs/users/mikael/heads/inline_minmaxloc_v341)] fortran: Add tests covering inline MINLOC/MAXLOC with DIM [PR90608]

2024-10-14 Thread Mikael Morin via Gcc-cvs

https://gcc.gnu.org/g:e36062b427002907f31b3686dffb96bfbe160dce

commit e36062b427002907f31b3686dffb96bfbe160dce
Author: Mikael Morin 
Date:   Thu Nov 16 10:00:26 2023 +0100

fortran: Add tests covering inline MINLOC/MAXLOC with DIM [PR90608]

Checked on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Add the tests covering the cases for which the following patches will
implement inline expansion of MINLOC and MAXLOC.  Those are cases where the
DIM argument is a constant value, and the ARRAY argument has rank greater
than 1.

PR fortran/90608

gcc/testsuite/ChangeLog:

* gfortran.dg/ieee/maxloc_nan_2.f90: New test.
* gfortran.dg/ieee/minloc_nan_2.f90: New test.
* gfortran.dg/maxloc_with_dim_1.f90: New test.
* gfortran.dg/maxloc_with_dim_and_mask_1.f90: New test.
* gfortran.dg/minloc_with_dim_1.f90: New test.
* gfortran.dg/minloc_with_dim_and_mask_1.f90: New test.

Diff:
---
 gcc/testsuite/gfortran.dg/ieee/maxloc_nan_2.f90|  64 +++
 gcc/testsuite/gfortran.dg/ieee/minloc_nan_2.f90|  64 +++
 gcc/testsuite/gfortran.dg/maxloc_with_dim_1.f90| 201 +
 .../gfortran.dg/maxloc_with_dim_and_mask_1.f90 | 452 +
 gcc/testsuite/gfortran.dg/minloc_with_dim_1.f90| 201 +
 .../gfortran.dg/minloc_with_dim_and_mask_1.f90 | 452 +
 6 files changed, 1434 insertions(+)

diff --git a/gcc/testsuite/gfortran.dg/ieee/maxloc_nan_2.f90 
b/gcc/testsuite/gfortran.dg/ieee/maxloc_nan_2.f90
new file mode 100644
index ..4d9b87073622
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/ieee/maxloc_nan_2.f90
@@ -0,0 +1,64 @@
+! { dg-do run }
+!
+! PR fortran/90608
+! Check the correct behaviour of the inline maxloc implementation,
+! when the dim argument is present.
+
+program p
+  implicit none
+  call check_without_mask
+  call check_with_mask
+contains
+  subroutine check_without_mask()
+use, intrinsic :: ieee_arithmetic
+real, allocatable :: a(:,:,:)
+real :: nan
+integer, allocatable :: r(:,:)
+if (.not. ieee_support_nan(nan)) return
+nan = ieee_value(nan, ieee_quiet_nan)
+allocate(a(3,4,5), source = nan)
+r = maxloc(a, dim=1)
+if (any(shape(r) /= (/ 4, 5 /))) error stop 21
+if (any(r /= 1)) error stop 22
+r = maxloc(a, dim=2)
+if (any(shape(r) /= (/ 3, 5 /))) error stop 23
+if (any(r /= 1)) error stop 24
+r = maxloc(a, dim=3)
+if (any(shape(r) /= (/ 3, 4 /))) error stop 25
+if (any(r /= 1)) error stop 26
+  end subroutine
+  subroutine check_with_mask()
+use, intrinsic :: ieee_arithmetic
+real, allocatable :: a(:,:,:)
+logical, allocatable :: m(:,:,:)
+real :: nan
+integer, allocatable :: r(:,:)
+if (.not. ieee_support_nan(nan)) return
+nan = ieee_value(nan, ieee_quiet_nan)
+allocate(a(2,3,4), source = nan)
+allocate(m(2,3,4))
+m(:,:,:) = reshape((/ .false., .false., .true. , .true. ,  &
+  .false., .true. , .false., .false.,  &
+  .false., .true. , .true. , .false.,  &
+  .true. , .true. , .true. , .false.,  &
+  .false., .true. , .true. , .false.,  &
+  .false., .true. , .false., .false.  /), shape(m))
+r = maxloc(a, dim = 1, mask = m)
+if (any(shape(r) /= (/ 3, 4 /))) error stop 51
+if (any(r /= reshape((/ 0, 1, 2,  &
+0, 2, 1,  &
+1, 1, 2,  &
+1, 2, 0  /), (/ 3, 4 / error stop 52
+r = maxloc(a, dim = 2, mask = m)
+if (any(shape(r) /= (/ 2, 4 /))) error stop 53
+if (any(r /= reshape((/ 2, 2,  &
+3, 2,  &
+1, 1,  &
+1, 2  /), (/ 2, 4 / error stop 54
+r = maxloc(a, dim = 3, mask = m)
+if (any(shape(r) /= (/ 2, 3 /))) error stop 55
+if (any(r /= reshape((/ 3, 3,  &
+1, 1,  &
+2, 1  /), (/ 2, 3 / error stop 56
+  end subroutine
+end program p
diff --git a/gcc/testsuite/gfortran.dg/ieee/minloc_nan_2.f90 
b/gcc/testsuite/gfortran.dg/ieee/minloc_nan_2.f90
new file mode 100644
index ..37c097a7acbe
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/ieee/minloc_nan_2.f90
@@ -0,0 +1,64 @@
+! { dg-do run }
+!
+! PR fortran/90608
+! Check the correct behaviour of the inline minloc implementation,
+! when the dim argument is present.
+
+program p
+  implicit none
+  call check_without_mask
+  call check_with_mask
+contains
+  subroutine check_without_mask()
+use, intrinsic :: ieee_arithmetic
+real, allocatable :: a(:,:,:)
+real :: nan
+integer, allocatable :: r(:,:)
+if (.not. ieee_support_nan(nan)) return
+nan = ieee_value(nan, ieee_quiet_nan)
+allocate(a(3,4,5), source = nan)
+r = minloc(a, dim=1)
+

[gcc(refs/users/mikael/heads/inline_minmaxloc_v341)] fortran: Inline unmasked integral MINLOC/MAXLOC with DIM [PR90608]

2024-10-14 Thread Mikael Morin via Gcc-cvs

https://gcc.gnu.org/g:90048759521fc9fffc853548ec70f230b02dcb72

commit 90048759521fc9fffc853548ec70f230b02dcb72
Author: Mikael Morin 
Date:   Fri Nov 17 19:04:19 2023 +0100

fortran: Inline unmasked integral MINLOC/MAXLOC with DIM [PR90608]

Bootstrapped and regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Enable generation of inline code for the MINLOC and MAXLOC intrinsics,
if the ARRAY argument is of integral type and of rank > 1 (only the rank 1
case was previously inlined), the DIM argument is a constant value and there
is no MASK argument.

The restriction to integral ARRAY and absent MASK limits the scope of
the change to the cases where we generate single loop inline code.

This change uses the existing scalarizer suport for reductions, that is
arrays used in scalarization loops, where each element uses a nested
scalarization loop to calculate its value.  The nested loop (and
respectively the nested scalarization chain) is created while walking the
MINLOC/MAXLOC expression, it's set up automatically at the time the outer
loop is set up, and gfc_conv_intrinsic_minmaxloc is changed to use it as a
replacement for the local loop variable (respectively ARRAY scalarization
chain) used in the non-reduction case (i.e. when DIM is absent).

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Return true
if DIM is constant, ARRAY is integral and MASK is absent.
(walk_inline_intrinsic_minmaxloc): If DIM is present, walk ARRAY and
move the dimension corresponding to DIM to a nested chain, keeping
the rest of the dimensions as the returned scalarization chain.
(gfc_conv_intrinsic_minmaxloc): When inside the scalarization loops,
proceed with inline code generation If DIM is present.  If DIM is
present, skip result array creation and final initialization from
individual result local variables.  If DIM is present and ARRAY has
rank greater than 1, use the nested loop initialized by the
scalarizer instead of the local one, use 1 as scalarization
dimension, and evaluate ARRAY using the inherited scalarization
chain instead of creating a local one by walking the expression.

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_bounds_1.f90: Also accept the error message
generated by the scalarizer in case the function call is implemented
through inline code.
* gfortran.dg/maxloc_bounds_2.f90: Likewise.
* gfortran.dg/maxloc_bounds_3.f90: Likewise.
* gfortran.dg/minmaxloc_19.f90: New test.

Diff:
---
 gcc/fortran/trans-intrinsic.cc| 227 ++
 gcc/testsuite/gfortran.dg/maxloc_bounds_1.f90 |   4 +-
 gcc/testsuite/gfortran.dg/maxloc_bounds_2.f90 |   4 +-
 gcc/testsuite/gfortran.dg/maxloc_bounds_3.f90 |   4 +-
 gcc/testsuite/gfortran.dg/minmaxloc_19.f90| 182 +
 5 files changed, 343 insertions(+), 78 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index a282ae1c0903..e44a245ec758 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5472,12 +5472,14 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   tree lab1, lab2;
   tree b_if, b_else;
   tree back;
-  gfc_loopinfo loop;
-  gfc_actual_arglist *actual;
-  gfc_ss *arrayss;
-  gfc_ss *maskss;
+  gfc_loopinfo loop, *ploop;
+  gfc_actual_arglist *actual, *array_arg, *dim_arg, *mask_arg, *kind_arg;
+  gfc_actual_arglist *back_arg;
+  gfc_ss *arrayss = nullptr;
+  gfc_ss *maskss = nullptr;
   gfc_se arrayse;
   gfc_se maskse;
+  gfc_se *base_se;
   gfc_expr *arrayexpr;
   gfc_expr *maskexpr;
   gfc_expr *backexpr;
@@ -5489,6 +5491,14 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   bool optional_mask;
 
   actual = expr->value.function.actual;
+  array_arg = actual;
+  dim_arg = array_arg->next;
+  mask_arg = dim_arg->next;
+  kind_arg = mask_arg->next;
+  back_arg = kind_arg->next;
+
+  bool dim_present = dim_arg->expr != nullptr;
+  bool nested_loop = dim_present && expr->rank > 0;
 
   /* The last argument, BACK, is passed by value. Ensure that
  by setting its name to %VAL. */
@@ -5502,11 +5512,15 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 {
   if (se->ss->info->useflags)
{
- /* The inline implementation of MINLOC/MAXLOC has been generated
-before, out of the scalarization loop; now we can just use the
-result.  */
- gfc_conv_tmp_array_ref (se);
- return;
+ if (!dim_present || !gfc_inline_intrinsic_function_p (expr))
+   {
+

[gcc(refs/users/mikael/heads/inline_minmaxloc_v341)] fortran: Inline non-character MINLOC/MAXLOC with DIM [PR90608]

2024-10-14 Thread Mikael Morin via Gcc-cvs

https://gcc.gnu.org/g:7cbaf2828144da5c7938b465da72fb1e76dd62ff

commit 7cbaf2828144da5c7938b465da72fb1e76dd62ff
Author: Mikael Morin 
Date:   Thu Aug 8 12:23:16 2024 +0200

fortran: Inline non-character MINLOC/MAXLOC with DIM [PR90608]

Bootstrapped and regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Enable generation of inline MINLOC/MAXLOC code in the cases where DIM is a
constant, and either ARRAY is of REAL type or MASK is an array.  Those cases
are the remaining bits to fully support inlining of non-CHARACTER
MINLOC/MAXLOC with constant DIM.  They are treated together because they
generate similar code, the NANs for REAL types being handled a bit like a
second level of masking.  These are the cases for which we generate two
loops.

This change affects the code generating the second loop, that was
previously accessible only in cases ARRAY had rank 1.

The main changes are in gfc_conv_intrinsic_minmaxloc the replacement of the
locally initialized scalarization loop with the one provided and previously
initialized by the scalarizer.  Same goes for the locally initialized MASK
scalarizer chain.

As this is enabling the code generating a second loop in a context of
reduction and nested loops, care is taken not to advance the parent
scalarization chain twice.

The scalarization chain element(s) for an array MASK are inserted in the
chain at a different place from that of a scalar MASK.  This is done on
purpose to match the code consuming the chains which are in different places
for scalar and array MASK.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Return TRUE
for MINLOC/MAXLOC with constant DIM and either REAL ARRAY or
non-scalar MASK.
(walk_inline_intrinsic_minmaxloc): Walk MASK and if it's an array
add the chain obtained before that of ARRAY.
(gfc_conv_intrinsic_minmaxloc): Use the nested loop if there is one.
To evaluate MASK (respectively ARRAY in the second loop), inherit
the scalarizer chain if in a nested loop, otherwise keep using the
chain obtained by walking MASK (respectively ARRAY).  If there is a
nested loop, avoid advancing the parent scalarization chain a second
time in the second loop.

gcc/testsuite/ChangeLog:

* gfortran.dg/minmaxloc_21.f90: New test.

Diff:
---
 gcc/fortran/trans-intrinsic.cc |  96 ++---
 gcc/testsuite/gfortran.dg/minmaxloc_21.f90 | 572 +
 2 files changed, 625 insertions(+), 43 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index 0ac3d7fe3a1b..b77183ab11e8 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5477,6 +5477,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   gfc_actual_arglist *back_arg;
   gfc_ss *arrayss = nullptr;
   gfc_ss *maskss = nullptr;
+  gfc_ss *orig_ss = nullptr;
   gfc_se arrayse;
   gfc_se maskse;
   gfc_se nested_se;
@@ -5711,6 +5712,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   if (nested_loop)
 {
   ploop = enter_nested_loop (&nested_se);
+  orig_ss = nested_se.ss;
   ploop->temp_dim = 1;
 }
   else
@@ -5785,9 +5787,8 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 }
   else
 {
-  gcc_assert (!nested_loop);
-  for (int i = 0; i < loop.dimen; i++)
-   gfc_add_modify (&loop.pre, pos[i], gfc_index_zero_node);
+  for (int i = 0; i < ploop->dimen; i++)
+   gfc_add_modify (&ploop->pre, pos[i], gfc_index_zero_node);
   lab1 = gfc_build_label_decl (NULL_TREE);
   TREE_USED (lab1) = 1;
   lab2 = gfc_build_label_decl (NULL_TREE);
@@ -5818,10 +5819,10 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   /* If we have a mask, only check this element if the mask is set.  */
   if (maskexpr && maskexpr->rank > 0)
 {
-  gcc_assert (!nested_loop);
-  gfc_init_se (&maskse, NULL);
-  gfc_copy_loopinfo_to_se (&maskse, &loop);
-  maskse.ss = maskss;
+  gfc_init_se (&maskse, base_se);
+  gfc_copy_loopinfo_to_se (&maskse, ploop);
+  if (!nested_loop)
+   maskse.ss = maskss;
   gfc_conv_expr_val (&maskse, maskexpr);
   gfc_add_block_to_block (&body, &maskse.pre);
 
@@ -5849,13 +5850,11 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   stmtblock_t ifblock2;
   tree ifbody2;
 
-  gcc_assert (!nested_loop);
-
   gfc_start_block (&ifblock2);
-  for (int i = 0; i < loop.dimen; i++)
+  for (int i = 0; i < ploop->dimen; i++)
{
  tmp = fold_build2_loc (input_loc

[gcc(refs/users/mikael/heads/inline_minmaxloc_v341)] fortran: Check for empty MINLOC/MAXLOC ARRAY along DIM only

2024-10-14 Thread Mikael Morin via Gcc-cvs

https://gcc.gnu.org/g:fdaba0139d4346b460a79eddc5c4faaac5e02a8a

commit fdaba0139d4346b460a79eddc5c4faaac5e02a8a
Author: Mikael Morin 
Date:   Sat Nov 18 20:54:20 2023 +0100

fortran: Check for empty MINLOC/MAXLOC ARRAY along DIM only

Bootstrapped and regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

In the function generating inline code to implement MINLOC and MAXLOC, only
check for ARRAY size along DIM if DIM is present.

The check for ARRAY emptyness had been checking the size of the full array,
which is correct for MINLOC and MAXLOC without DIM.  But if DIM is
present, the reduction is along DIM only so the check for emptyness
should consider that dimension only as well.

This sounds like a correctness issue, but fortunately the cases where it
makes a difference are cases where ARRAY is empty, so even if the value
calculated for MINLOC or MAXLOC is wrong, it's wrapped in a zero iteration
loop, and the wrong values are not actually used.  In the end this just
avoids unnecessary calculations.

A previous version of this patch regressed on non-constant DIM with rank 1
ARRAY.  The new testcase checks that that case is supported.

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Only get the 
size
along DIM instead of the full size if DIM is present.

gcc/testsuite/ChangeLog:

* gfortran.dg/minmaxloc_22.f90: New test.

Diff:
---
 gcc/fortran/trans-intrinsic.cc | 19 ++-
 gcc/testsuite/gfortran.dg/minmaxloc_22.f90 | 26 ++
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index b77183ab11e8..e1a5fdef26c2 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5641,7 +5641,24 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   if (!(maskexpr && maskexpr->rank > 0))
 {
   mpz_t asize;
-  if (gfc_array_size (arrayexpr, &asize))
+  bool reduction_size_known;
+
+  if (dim_present)
+   {
+ int reduction_dim;
+ if (dim_arg->expr->expr_type == EXPR_CONSTANT)
+   reduction_dim = mpz_get_si (dim_arg->expr->value.integer) - 1;
+ else if (arrayexpr->rank == 1)
+   reduction_dim = 0;
+ else
+   gcc_unreachable ();
+ reduction_size_known = gfc_array_dimen_size (arrayexpr, reduction_dim,
+  &asize);
+   }
+  else
+   reduction_size_known = gfc_array_size (arrayexpr, &asize);
+
+  if (reduction_size_known)
{
  nonempty = gfc_conv_mpz_to_tree (asize, gfc_index_integer_kind);
  mpz_clear (asize);
diff --git a/gcc/testsuite/gfortran.dg/minmaxloc_22.f90 
b/gcc/testsuite/gfortran.dg/minmaxloc_22.f90
new file mode 100644
index ..ec97d1435af8
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/minmaxloc_22.f90
@@ -0,0 +1,26 @@
+! { dg-do compile }
+! { dg-additional-options "-O" }
+!
+! Check that the inline code generated for MINLOC and MAXLOC supports
+! a non-constant DIM argument if ARRAY has rank 1.
+
+program p
+  implicit none
+  integer, parameter :: n = 5
+  integer :: a(n), i
+  a = (/ (i**2, i=1,n) /)
+  print *, f(a, 1), g(a, 1)
+contains
+  function f(a, d)
+integer :: a(n)
+integer :: d
+integer :: f
+f = minloc(a, dim=d) 
+  end function
+  function g(a, d)
+integer :: a(n)
+integer :: d
+integer :: g
+g = maxloc(a, dim=d) 
+  end function
+end program p

[gcc(refs/users/mikael/heads/inline_minmaxloc_v341)] fortran: Evaluate once BACK argument of MINLOC/MAXLOC with DIM [PR90608]

2024-10-14 Thread Mikael Morin via Gcc-cvs

https://gcc.gnu.org/g:2a9ae1ffb40de944438193984a83642531362344

commit 2a9ae1ffb40de944438193984a83642531362344
Author: Mikael Morin 
Date:   Thu Oct 3 15:57:50 2024 +0200

fortran: Evaluate once BACK argument of MINLOC/MAXLOC with DIM [PR90608]

Bootstrapped and regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Evaluate the BACK argument of MINLOC/MAXLOC once before the
scalarization loops in the case where the DIM argument is present.

This is a follow-up to r15-1994-ga55d24b3cf7f4d07492bb8e6fcee557175b47ea3
which added knowledge of BACK to the scalarizer, to
r15-2701-ga10436a8404ad2f0cc5aa4d6a0cc850abe5ef49e which removed it to
handle it out of scalarization instead, and to more immediate previous
patches that added support for MINLOC/MAXLOC with DIM.  The support for
MINLOC/MAXLOC with DIM introduced nested loops, which made the evaluation of
BACK (removed from the scalarizer knowledge by the forementionned commit)
wrapped in a loop, so possibly executed more than once.  This change adds
BACK to the scalarization chain if MINLOC/MAXLOC will use nested loops, so
that it is evaluated by the scalarizer only once before the outermost loop
in that case.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc
(walk_inline_intrinsic_minmaxloc): Add a scalar element for BACK as
first item of the chain if BACK is present and there will be nested
loops.
(gfc_conv_intrinsic_minmaxloc): Evaluate BACK using an inherited
scalarization chain if there is a nested loop.

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_8.f90: New test.
* gfortran.dg/minloc_9.f90: New test.

Diff:
---
 gcc/fortran/trans-intrinsic.cc |  21 +-
 gcc/testsuite/gfortran.dg/maxloc_8.f90 | 349 +
 gcc/testsuite/gfortran.dg/minloc_9.f90 | 349 +
 3 files changed, 717 insertions(+), 2 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index e1a5fdef26c2..4cd4f4b19776 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5594,7 +5594,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 && maskexpr->symtree->n.sym->attr.optional;
   backexpr = back_arg->expr;
 
-  gfc_init_se (&backse, NULL);
+  gfc_init_se (&backse, nested_loop ? se : nullptr);
   if (backexpr == nullptr)
 back = logical_false_node;
   else if (maybe_absent_optional_variable (backexpr))
@@ -11885,10 +11885,13 @@ walk_inline_intrinsic_minmaxloc (gfc_ss *ss, gfc_expr 
*expr ATTRIBUTE_UNUSED)
   gfc_actual_arglist *array_arg = expr->value.function.actual;
   gfc_actual_arglist *dim_arg = array_arg->next;
   gfc_actual_arglist *mask_arg = dim_arg->next;
+  gfc_actual_arglist *kind_arg = mask_arg->next;
+  gfc_actual_arglist *back_arg = kind_arg->next;
 
   gfc_expr *array = array_arg->expr;
   gfc_expr *dim = dim_arg->expr;
   gfc_expr *mask = mask_arg->expr;
+  gfc_expr *back = back_arg->expr;
 
   if (dim == nullptr)
 return gfc_get_array_ss (ss, expr, 1, GFC_SS_INTRINSIC);
@@ -11916,7 +11919,21 @@ walk_inline_intrinsic_minmaxloc (gfc_ss *ss, gfc_expr 
*expr ATTRIBUTE_UNUSED)
  chain, "hiding" that dimension from the outer scalarization.  */
   int dim_val = mpz_get_si (dim->value.integer);
   gfc_ss *tail = nest_loop_dimension (tmp_ss, dim_val - 1);
-  tail->next = ss;
+
+  if (back && array->rank > 1)
+{
+  /* If there are nested scalarization loops, include BACK in the
+scalarization chains to avoid evaluating it multiple times in a loop.
+Otherwise, prefer to handle it outside of scalarization.  */
+  gfc_ss *back_ss = gfc_get_scalar_ss (ss, back);
+  back_ss->info->type = GFC_SS_REFERENCE;
+  if (maybe_absent_optional_variable (back))
+   back_ss->info->can_be_null_ref = true;
+
+  tail->next = back_ss;
+}
+  else
+tail->next = ss;
 
   if (scalar_mask)
 {
diff --git a/gcc/testsuite/gfortran.dg/maxloc_8.f90 
b/gcc/testsuite/gfortran.dg/maxloc_8.f90
new file mode 100644
index ..20f63a84bbe5
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/maxloc_8.f90
@@ -0,0 +1,349 @@
+! { dg-do run }
+!
+! PR fortran/90608
+! Check that the evaluation of MAXLOC's BACK argument is made only once
+! before the scalarization loops, when the DIM argument is present.
+
+program p
+  implicit none
+  integer, parameter :: data60(*) = (/ 7, 4, 5, 3, 9, 0, 6, 4, 5, 5,  &
+   8, 2, 6, 7, 8, 7, 4, 5, 3, 9,  &
+   0, 6, 4, 5, 5, 8, 2, 6, 7, 8,  &
+   7, 4, 5, 3, 9, 0, 6, 4, 5, 5,  &
+   8, 2, 6, 7, 8, 7, 4, 5, 3, 9,  &
+   0, 6, 4, 5, 5,

[gcc(refs/users/mikael/heads/inline_minmaxloc_v341)] fortran: Inline MINLOC/MAXLOC with DIM and scalar MASK [PR90608]

2024-10-14 Thread Mikael Morin via Gcc-cvs

https://gcc.gnu.org/g:d1830b5054f471d922c6bb1876e0e2303ba6581f

commit d1830b5054f471d922c6bb1876e0e2303ba6581f
Author: Mikael Morin 
Date:   Thu Aug 8 13:44:16 2024 +0200

fortran: Inline MINLOC/MAXLOC with DIM and scalar MASK [PR90608]

Bootstrapped and regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Enable the generation of inline code for MINLOC/MAXLOC when argument
ARRAY is of integral type and has rank > 1, DIM is a constant, and MASK is
scalar (only absent MASK or rank 1 ARRAY were inlined before).

Scalar masks are implemented with a wrapping condition around the code
one would generate if MASK wasn't present, so they are easy to support
once inline code without MASK is working.

With this change, there are both expressions evaluated inside the nested
loop (ARRAY, and in the future MASK if non-scalar) and expressions evaluated
outside of it (MASK if scalar).  For both one has to advance the
scalarization chain passed as argument SE to gfc_conv_intrinsic_minmaxloc as
they are evaluated, but for expressions evaluated from within the nested
loop one has to advance additionally the nested scalarization chain of the
reduction loop.  This is normally handled transparently through the
inheritance that is defined when initializing gfc_se structs, but there has
to be some variable to inherit from, and there is a single one, SE.  This
variable is kept as base for out of nested loop expressions only (i.e. for
scalar MASK), and this change introduces a new variable to hold the current
advance of the nested loop scalarization chain and serve as inheritance base
to evaluate nested loop expressions (just ARRAY for now, additionally
non-scalar MASK later).

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Return TRUE
if MASK is scalar.
(walk_inline_intrinsic_minmaxloc): Append to the scalarization chain
a scalar element for MASK if it's present.
(gfc_conv_intrinsic_minmaxloc): Use a local gfc_se struct to serve
as base for all the expressions evaluated in the nested loop.  To
evaluate MASK when there is a nested loop, enable usage of the
scalarizer and set the original passed in SE argument as current
scalarization chain element to use.  And use the nested loop from
the scalarizer instead of the local loop in that case.

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_bounds_8.f90: Accept the error message
generated by the scalarizer in case the MAXLOC intrinsic call is
implemented through inline code.
* gfortran.dg/minmaxloc_20.f90: New test.

Diff:
---
 gcc/fortran/trans-intrinsic.cc|  35 +++--
 gcc/testsuite/gfortran.dg/maxloc_bounds_8.f90 |   4 +-
 gcc/testsuite/gfortran.dg/minmaxloc_20.f90| 182 ++
 3 files changed, 209 insertions(+), 12 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index e44a245ec758..29f17f334a3c 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5479,6 +5479,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   gfc_ss *maskss = nullptr;
   gfc_se arrayse;
   gfc_se maskse;
+  gfc_se nested_se;
   gfc_se *base_se;
   gfc_expr *arrayexpr;
   gfc_expr *maskexpr;
@@ -5616,7 +5617,10 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   gfc_add_block_to_block (&se->pre, &backse.post);
 
   if (nested_loop)
-base_se = se;
+{
+  gfc_init_se (&nested_se, se);
+  base_se = &nested_se;
+}
   else
 {
   /* Walk the arguments.  */
@@ -5706,7 +5710,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 
   if (nested_loop)
 {
-  ploop = enter_nested_loop (se);
+  ploop = enter_nested_loop (&nested_se);
   ploop->temp_dim = 1;
 }
   else
@@ -6063,21 +6067,19 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 {
   tree ifmask;
 
-  gcc_assert (!nested_loop);
-
-  gfc_init_se (&maskse, NULL);
+  gfc_init_se (&maskse, nested_loop ? se : nullptr);
   gfc_conv_expr_val (&maskse, maskexpr);
   gfc_add_block_to_block (&se->pre, &maskse.pre);
   gfc_init_block (&block);
-  gfc_add_block_to_block (&block, &loop.pre);
-  gfc_add_block_to_block (&block, &loop.post);
+  gfc_add_block_to_block (&block, &ploop->pre);
+  gfc_add_block_to_block (&block, &ploop->post);
   tmp = gfc_finish_block (&block);
 
   /* For the else part of the scalar mask, just initialize
 the pos variable the same way as above.  */
 
   gfc_init_block (&elseblock);
-  for (int i = 0; i < loop.

[gcc(refs/users/mikael/heads/inline_minmaxloc_v341)] fortran: Check MASK directly instead of its scalarization chain

2024-10-14 Thread Mikael Morin via Gcc-cvs

https://gcc.gnu.org/g:381a8e764164265159c8c3d927b4163a7e3fbc4a

commit 381a8e764164265159c8c3d927b4163a7e3fbc4a
Author: Mikael Morin 
Date:   Thu Sep 12 16:56:39 2024 +0200

fortran: Check MASK directly instead of its scalarization chain

Bootstrapped and regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Update the conditions used by the inline MINLOC/MAXLOC code generation
function to check directly the properties of MASK instead of the
variable holding its scalarization chain.

The inline implementation of MINLOC/MAXLOC in gfc_conv_intrinsic_minmaxloc
uses several conditions checking the presence of a scalarization chain for
MASK, which means that the argument is present and non-scalar.  The next
patch will allow inlining MINLOC/MAXLOC with DIM and MASK, and in that
case the scalarization chain for MASK is initialized elsewhere, so the
variable usually holding it in the function is not used, and the conditions
won't work in that case.

This change updates the conditions to check directly the properties of
MASK so that they work even if the scalarization chain variable is not used.

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Use
conditionals based on the MASK expression rather than on its
scalarization chains.

Diff:
---
 gcc/fortran/trans-intrinsic.cc | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index 29f17f334a3c..0ac3d7fe3a1b 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5746,7 +5746,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 
   gcc_assert (reduction_dimensions == ploop->dimen);
 
-  if (nonempty == NULL && maskss == NULL)
+  if (nonempty == NULL && !(maskexpr && maskexpr->rank > 0))
 {
   nonempty = logical_true_node;
 
@@ -5816,7 +5816,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   gfc_start_scalarized_body (ploop, &body);
 
   /* If we have a mask, only check this element if the mask is set.  */
-  if (maskss)
+  if (maskexpr && maskexpr->rank > 0)
 {
   gcc_assert (!nested_loop);
   gfc_init_se (&maskse, NULL);
@@ -5921,7 +5921,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 }
   gfc_add_expr_to_block (&block, ifbody);
 
-  if (maskss)
+  if (maskexpr && maskexpr->rank > 0)
 {
   /* We enclose the above in if (mask) {...}.  If the mask is an
 optional argument, generate IF (.NOT. PRESENT(MASK)
@@ -5972,7 +5972,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   gfc_add_expr_to_block (outer_block, build1_v (LABEL_EXPR, lab1));
 
   /* If we have a mask, only check this element if the mask is set.  */
-  if (maskss)
+  if (maskexpr && maskexpr->rank > 0)
{
  gfc_init_se (&maskse, NULL);
  gfc_copy_loopinfo_to_se (&maskse, &loop);
@@ -6038,7 +6038,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 
   gfc_add_expr_to_block (&block, tmp);
 
-  if (maskss)
+  if (maskexpr && maskexpr->rank > 0)
{
  /* We enclose the above in if (mask) {...}.  If the mask is
 an optional argument, generate IF (.NOT. PRESENT(MASK)
@@ -6063,7 +6063,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 gfc_add_expr_to_block (&loop.pre, build1_v (LABEL_EXPR, lab2));
 
   /* For a scalar mask, enclose the loop in an if statement.  */
-  if (maskexpr && maskss == NULL)
+  if (maskexpr && maskexpr->rank == 0)
 {
   tree ifmask;

[gcc] Created branch 'mikael/heads/inline_minmaxloc_v341' in namespace 'refs/users'

2024-10-14 Thread Mikael Morin via Gcc-cvs

The branch 'mikael/heads/inline_minmaxloc_v341' was created in namespace 
'refs/users' pointing to:

 2a9ae1ffb40d... fortran: Evaluate once BACK argument of MINLOC/MAXLOC with

[gcc r15-4325] RISC-V: Add detailed comments on processing implied extensions. [NFC]

2024-10-14 Thread Kito Cheng via Gcc-cvs

https://gcc.gnu.org/g:1c507a02f29c6ca735f40f4b16b341ce9d5aa1b1

commit r15-4325-g1c507a02f29c6ca735f40f4b16b341ce9d5aa1b1
Author: Yangyu Chen 
Date:   Mon Oct 14 18:31:06 2024 +0800

RISC-V: Add detailed comments on processing implied extensions. [NFC]

In some cases, we don't need to handle implied extensions. Add detailed
comments to help developers understand what implied ISAs should be
considered.

libgcc/ChangeLog:

* config/riscv/feature_bits.c (__init_riscv_features_bits_linux):
Add detailed comments on processing implied extensions.

Signed-off-by: Yangyu Chen 

Diff:
---
 libgcc/config/riscv/feature_bits.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/libgcc/config/riscv/feature_bits.c 
b/libgcc/config/riscv/feature_bits.c
index 9bdbc466feea..a90e553b83d6 100644
--- a/libgcc/config/riscv/feature_bits.c
+++ b/libgcc/config/riscv/feature_bits.c
@@ -290,9 +290,12 @@ static void __init_riscv_features_bits_linux ()
 }
 
   const struct riscv_hwprobe hwprobe_ima_ext = hwprobes[4];
-
   /* Every time we add new extensions, we should check if previous extensions
- imply the new extension and set the corresponding bit.  */
+ imply the new extension and set the corresponding bit.
+ We don't need to handle cases where:
+ 1.  The new extension implies a previous extension (e.g., Zve32f -> F).
+ 2.  The extensions imply some other extensions appear in the same release
+version of Linux Kernel (e.g., Zbc - > Zbkc).  */
 
   if (hwprobe_ima_ext.value & RISCV_HWPROBE_IMA_FD)
 {
@@ -397,7 +400,7 @@ __init_riscv_feature_bits ()
 #ifdef __linux
   __init_riscv_features_bits_linux ();
 #else
-  /* Unsupported, just initlizaed that into all zeros.  */
+  /* Unsupported, just initialize that into all zeros.  */
   __riscv_feature_bits.length = 0;
   __riscv_vendor_feature_bits.length = 0;
   __riscv_cpu_model.mvendorid = 0;

[gcc r15-4330] libcpp: Support extended characters for #pragma {push, pop}_macro [PR109704]

2024-10-14 Thread Lewis Hyatt via Gcc-cvs

https://gcc.gnu.org/g:998eb2a126d33ab622a6f12c7e1faccf4429835c

commit r15-4330-g998eb2a126d33ab622a6f12c7e1faccf4429835c
Author: Lewis Hyatt 
Date:   Fri Jan 12 13:26:06 2024 -0500

libcpp: Support extended characters for #pragma {push,pop}_macro [PR109704]

The implementation of #pragma push_macro and #pragma pop_macro has to date
made use of an ad-hoc function, _cpp_lex_identifier(), which lexes an
identifier out of a string. When support was added for extended characters
in identifiers ($, UCNs, or UTF-8), that support was added only for the
"normal" way of lexing identifiers out of a cpp_buffer (_cpp_lex_direct) and
not for the ad-hoc way. Consequently, extended identifiers are not usable
with these pragmas.

The logic for lexing identifiers has become more complicated than it was
when _cpp_lex_identifier() was written -- it now handles things like \N{}
escapes in C++, for instance -- and it no longer seems practical to maintain
a redundant code path for lexing identifiers. Address the issue by changing
the implementation of #pragma {push,pop}_macro to lex identifiers in the
expected way, i.e. by pushing a cpp_buffer and lexing the identifier from
there.

The existing implementation has some quirks because of the ad-hoc parsing
logic. For example:

 #pragma push_macro("X ")
 ...
 #pragma pop_macro("X")

will not restore macro X (note the extra space in the first string). 
However:

 #pragma push_macro("X ")
 ...
 #pragma pop_macro("X ")

actually does sucessfully restore "X". This is because the key for looking
up the saved macro on the push stack is the original string passed, so the
string passed to pop_macro needs to match it exactly. It is not that easy to
reproduce this logic in the world of extended characters, given that for
example it should be valid to pass a UCN to push_macro, and the
corresponding UTF-8 to pop_macro. Given that this aspect of the existing
behavior seems unintentional and has no tests (and does not match other
implementations), I opted to make the new logic more straightforward. The
string passed needs to lex to one token, which must be a valid identifier,
or else no action is taken and no error is generated. Any diagnostics
encountered during lexing (e.g., due to a UTF-8 character not permitted to
appear in an identifier) are also suppressed.

It could be nice (for GCC 15) to also add a warning if a pop_macro does not
match a previous push_macro.

libcpp/ChangeLog:

PR preprocessor/109704
* include/cpplib.h (class cpp_auto_suppress_diagnostics): New class.
* errors.cc
(cpp_auto_suppress_diagnostics::cpp_auto_suppress_diagnostics): New
function.
(cpp_auto_suppress_diagnostics::~cpp_auto_suppress_diagnostics): New
function.
* charset.cc (noop_diagnostic_cb): Remove.
(cpp_interpret_string_ranges): Refactor diagnostic suppression logic
into new class cpp_auto_suppress_diagnostics.
(count_source_chars): Likewise.
* directives.cc (cpp_pop_definition): Add cpp_hashnode argument.
(lex_identifier_from_string): New static helper function.
(push_pop_macro_common): Refactor common logic from
do_pragma_push_macro and do_pragma_pop_macro; use
lex_identifier_from_string instead of _cpp_lex_identifier.
(do_pragma_push_macro): Reimplement using push_pop_macro_common.
(do_pragma_pop_macro): Likewise.
* internal.h (_cpp_lex_identifier): Remove.
* lex.cc (lex_identifier_intern): Remove.
(_cpp_lex_identifier): Remove.

gcc/testsuite/ChangeLog:

PR preprocessor/109704
* c-c++-common/cpp/pragma-push-pop-utf8.c: New test.
* g++.dg/pch/pushpop-2.C: New test.
* g++.dg/pch/pushpop-2.Hs: New test.
* gcc.dg/pch/pushpop-2.c: New test.
* gcc.dg/pch/pushpop-2.hs: New test.

Diff:
---
 .../c-c++-common/cpp/pragma-push-pop-utf8.c| 203 +
 gcc/testsuite/g++.dg/pch/pushpop-2.C   |  18 ++
 gcc/testsuite/g++.dg/pch/pushpop-2.Hs  |   9 +
 gcc/testsuite/gcc.dg/pch/pushpop-2.c   |  18 ++
 gcc/testsuite/gcc.dg/pch/pushpop-2.hs  |   9 +
 libcpp/charset.cc  |  34 +---
 libcpp/directives.cc   | 175 +-
 libcpp/errors.cc   |  16 ++
 libcpp/include/cpplib.h|  13 ++
 libcpp/internal.h  |   1 -
 libcpp/lex.cc  |  33 
 11 files changed, 378 insertions(+), 151 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/cpp/pragma-p

[gcc r15-4331] libcpp: Fix _Pragma("GCC system_header") [PR114436]

2024-10-14 Thread Lewis Hyatt via Gcc-cvs

https://gcc.gnu.org/g:8c56d697b35d3d2ef802d068cad6b3bd026a2a1a

commit r15-4331-g8c56d697b35d3d2ef802d068cad6b3bd026a2a1a
Author: Lewis Hyatt 
Date:   Fri Mar 22 15:42:43 2024 -0400

libcpp: Fix _Pragma("GCC system_header") [PR114436]

_Pragma("GCC system_header") currently takes effect only partially. It does
succeed in updating the line_map, so that checks like in_system_header_at()
return correctly, but it does not update pfile->buffer->sysp.  One result is
that a subsequent #include does not set up the system header state properly
for the newly included file, as pointed out in the PR. Fix by propagating
the new system header state back to the buffer after processing the pragma.

libcpp/ChangeLog:

PR preprocessor/114436
* directives.cc (destringize_and_run): If the _Pragma changed the
buffer system header state (e.g. because it was "GCC
system_header"), propagate that change back to the actual buffer
too.

gcc/testsuite/ChangeLog:

PR preprocessor/114436
* c-c++-common/cpp/pragma-system-header-1.h: New test.
* c-c++-common/cpp/pragma-system-header-2.h: New test.
* c-c++-common/cpp/pragma-system-header.c: New test.

Diff:
---
 gcc/testsuite/c-c++-common/cpp/pragma-system-header-1.h |  1 +
 gcc/testsuite/c-c++-common/cpp/pragma-system-header-2.h |  5 +
 gcc/testsuite/c-c++-common/cpp/pragma-system-header.c   |  3 +++
 libcpp/directives.cc| 11 ---
 4 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/cpp/pragma-system-header-1.h 
b/gcc/testsuite/c-c++-common/cpp/pragma-system-header-1.h
new file mode 100644
index ..bd9ff0cb1385
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cpp/pragma-system-header-1.h
@@ -0,0 +1 @@
+#pragma GCC warning "this warning should not be output (1)"
diff --git a/gcc/testsuite/c-c++-common/cpp/pragma-system-header-2.h 
b/gcc/testsuite/c-c++-common/cpp/pragma-system-header-2.h
new file mode 100644
index ..a62d9e2685a6
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cpp/pragma-system-header-2.h
@@ -0,0 +1,5 @@
+_Pragma("GCC system_header")
+#include "pragma-system-header-1.h"
+#pragma GCC warning "this warning should not be output (2)"
+_Pragma("unknown")
+#include "pragma-system-header-1.h"
diff --git a/gcc/testsuite/c-c++-common/cpp/pragma-system-header.c 
b/gcc/testsuite/c-c++-common/cpp/pragma-system-header.c
new file mode 100644
index ..fdea12009e13
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cpp/pragma-system-header.c
@@ -0,0 +1,3 @@
+#include "pragma-system-header-2.h" /* { dg-bogus "this warning should not be 
output" } */
+/* { dg-do preprocess } */
+/* PR preprocessor/114436 */
diff --git a/libcpp/directives.cc b/libcpp/directives.cc
index bc4a95b66feb..9d235fa1b057 100644
--- a/libcpp/directives.cc
+++ b/libcpp/directives.cc
@@ -2424,9 +2424,11 @@ destringize_and_run (cpp_reader *pfile, const cpp_string 
*in,
  until we've read all of the tokens that we want.  */
   cpp_push_buffer (pfile, (const uchar *) result, dest - result,
   /* from_stage3 */ true);
-  /* ??? Antique Disgusting Hack.  What does this do?  */
-  if (pfile->buffer->prev)
-pfile->buffer->file = pfile->buffer->prev->file;
+
+  /* This is needed for _Pragma("once") and _Pragma("GCC system_header") to 
work
+ properly.  */
+  pfile->buffer->file = pfile->buffer->prev->file;
+  pfile->buffer->sysp = pfile->buffer->prev->sysp;
 
   start_directive (pfile);
   _cpp_clean_line (pfile);
@@ -2491,6 +2493,9 @@ destringize_and_run (cpp_reader *pfile, const cpp_string 
*in,
 
   /* Finish inlining run_directive.  */
   pfile->buffer->file = NULL;
+  /* If the system header state changed due to #pragma GCC system_header, then
+ make that applicable to the real buffer too.  */
+  pfile->buffer->prev->sysp = pfile->buffer->sysp;
   _cpp_pop_buffer (pfile);
 
   /* Reset the old macro state before ...  */

[gcc/meissner/heads/work181-sha] (3 commits) Merge commit 'refs/users/meissner/heads/work181-sha' of git

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-sha' was updated to point to:

 cd37254fc84b... Merge commit 'refs/users/meissner/heads/work181-sha' of git

It previously pointed to:

 a7951e232b3d... Add ChangeLog.sha and update REVISION.

Diff:

Summary of changes (added commits):
---

  cd37254... Merge commit 'refs/users/meissner/heads/work181-sha' of git
  beea0dd... Add ChangeLog.sha and update REVISION.
  05ef8ce... Add ChangeLog.meissner and REVISION. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work181-sha' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work181)] Update ChangeLog.*

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:e794689a0b96dcbe05f854def882ca3cffc72de5

commit e794689a0b96dcbe05f854def882ca3cffc72de5
Author: Michael Meissner 
Date:   Mon Oct 14 12:30:21 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 448 +
 1 file changed, 448 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 2f869b4f7869..d55f84fbe72c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,453 @@
+ Branch work181, patch #21 
+
+Add -mcpu=future tuning support.
+
+This patch makes -mtune=future use the same tuning decision as -mtune=power11.
+
+2024-10-05  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add future as an
+   alterntive to power10 and power11.
+
+ Branch work181, patch #20 
+
+Add support for -mcpu=future
+
+This patch adds the support that can be used in developing GCC support for
+future PowerPC processors.
+
+2024-10-05  Michael Meissner  
+
+   * config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
+   * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future.
+   * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+   * config/rs6000/rs6000-arch.def: Add future cpu.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
+   -mcpu=future, define _ARCH_FUTURE.
+   * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
+   (future cpu): Define.
+   * config/rs6000/rs6000-opts.h (enum processor_type): Add
+   PROCESSOR_FUTURE.
+   * config/rs6000/rs6000-tables.opt: Regenerate.
+   * config/rs6000/rs6000.cc (power10_cost): Update comment.
+   (get_arch_flags): Add support for future processor.
+   (rs6000_option_override_internal): Likewise.
+   (rs6000_machine_from_flags): Likewise.
+   (rs6000_reassociation_width): Likewise.
+   (rs6000_adjust_cost): Likewise.
+   (rs6000_issue_rate): Likewise.
+   (rs6000_sched_reorder): Likewise.
+   (rs6000_sched_reorder2): Likewise.
+   (rs6000_register_move_cost): Likewise.
+   * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+   (TARGET_POWER11): New macro.
+   * config/rs6000/rs6000.md (cpu attribute): Likewise.
+
+ Branch work181, patch #9 
+
+Update tests to work with architecture flags changes.
+
+Two tests used -mvsx to raise the processor level to at least power7.  These
+tests were rewritten to add cpu=power7 support.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+In addition, I constructed a test case that used every archiecture define (like
+_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
+this test for all supported combinations of -mcpu, big/little endian, and 32/64
+bit support.  Every single instance generated exactly the same code with the
+patches installed compared to the compiler before installing the patches.
+
+Can I install this patch on the GCC 15 trunk?
+
+2024-10-05  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
+   instructions.
+
+ Branch work181, patch #8 
+
+Change TARGET_MODULO to TARGET_POWER9
+
+As part of the architecture flags patches, this patch changes the use of
+TARGET_MODULO to TARGET_POWER9.  The modulo instructions were added in power9 
(ISA
+3.0).  Note, I did not change the uses of TARGET_MODULO where it was explicitly
+generating different code if the machine had a modulo instruction.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+In addition, I constructed a test case that used every archiecture define (like
+_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
+this test for all supported combinations of -mcpu, big/little endian, and 32/64
+bit support.  Every single instance generated exactly the same code with the
+patches installed compared to the compiler before installing the patches.
+
+Can I install this patch on the GCC 15 trunk?
+
+2024-10-05  Michael Meissner  
+
+   * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
+   TARGET_POWER9 instead of TARGET_MODULO.
+   * config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
+   (TARGET_EXTSWSLI): Likewise.
+   (TARGET_MADDLD): Likewise.
+   * config/rs6000/rs6000.md (enabled attribute): Likewise.
+
+===

[gcc/meissner/heads/work181-bugs] (14 commits) Merge commit 'refs/users/meissner/heads/work181-bugs' of gi

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-bugs' was updated to point to:

 f96511e60821... Merge commit 'refs/users/meissner/heads/work181-bugs' of gi

It previously pointed to:

 84dbc16decf7... Merge commit 'refs/users/meissner/heads/work181-bugs' of gi

Diff:

Summary of changes (added commits):
---

  f96511e... Merge commit 'refs/users/meissner/heads/work181-bugs' of gi
  2836b35... Add ChangeLog.bugs and update REVISION.
  e794689... Update ChangeLog.* (*)
  7ab185d... Add -mcpu=future tuning support. (*)
  2e4723b... Add support for -mcpu=future (*)
  e369efc... Update tests to work with architecture flags changes. (*)
  93ac155... Change TARGET_MODULO to TARGET_POWER9 (*)
  82fe872... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  492d7f2... Change TARGET_CMPB to TARGET_POWER6 (*)
  d7027d7... Change TARGET_FPRND to TARGET_POWER5X (*)
  8166d15... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  8e34b86... Do not allow -mvsx to boost processor to power7. (*)
  6704009... Use architecture flags for defining _ARCH_PWR macros. (*)
  036b90d... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work181-bugs' matches
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[gcc(refs/users/meissner/heads/work181-bugs)] Add ChangeLog.bugs and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:2836b35eba2232942637118e666e62a7f4b48c41

commit 2836b35eba2232942637118e666e62a7f4b48c41
Author: Michael Meissner 
Date:   Mon Oct 14 11:45:10 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..95de79b3b81b
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,5 @@
+ Branch work181-bugs, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 5cf926789393..ace14cd51ab2 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work181 branch
+work181-bugs branch

[gcc(refs/users/meissner/heads/work181-bugs)] Merge commit 'refs/users/meissner/heads/work181-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:f96511e60821a82c9e65d3c3124d550b07d76c37

commit f96511e60821a82c9e65d3c3124d550b07d76c37
Merge: 2836b35eba22 84dbc16decf7
Author: Michael Meissner 
Date:   Mon Oct 14 12:31:08 2024 -0400

Merge commit 'refs/users/meissner/heads/work181-bugs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work181-bugs

Diff:

[gcc(refs/users/meissner/heads/work181-dmf)] Merge commit 'refs/users/meissner/heads/work181-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work18

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:fb2501b139b5b35fedcc6f0c38d6f307a3652748

commit fb2501b139b5b35fedcc6f0c38d6f307a3652748
Merge: 592c968efd09 28be49ff2116
Author: Michael Meissner 
Date:   Mon Oct 14 12:32:45 2024 -0400

Merge commit 'refs/users/meissner/heads/work181-dmf' of 
git+ssh://gcc.gnu.org/git/gcc into me/work181-dmf

Diff:

[gcc/meissner/heads/work181-dmf] (14 commits) Merge commit 'refs/users/meissner/heads/work181-dmf' of git

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-dmf' was updated to point to:

 fb2501b139b5... Merge commit 'refs/users/meissner/heads/work181-dmf' of git

It previously pointed to:

 28be49ff2116... Merge commit 'refs/users/meissner/heads/work181-dmf' of git

Diff:

Summary of changes (added commits):
---

  fb2501b... Merge commit 'refs/users/meissner/heads/work181-dmf' of git
  592c968... Add ChangeLog.dmf and update REVISION.
  e794689... Update ChangeLog.* (*)
  7ab185d... Add -mcpu=future tuning support. (*)
  2e4723b... Add support for -mcpu=future (*)
  e369efc... Update tests to work with architecture flags changes. (*)
  93ac155... Change TARGET_MODULO to TARGET_POWER9 (*)
  82fe872... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  492d7f2... Change TARGET_CMPB to TARGET_POWER6 (*)
  d7027d7... Change TARGET_FPRND to TARGET_POWER5X (*)
  8166d15... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  8e34b86... Do not allow -mvsx to boost processor to power7. (*)
  6704009... Use architecture flags for defining _ARCH_PWR macros. (*)
  036b90d... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work181-dmf' matches
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no separate email is sent for this commit.

[gcc/meissner/heads/work181-libs] (14 commits) Merge commit 'refs/users/meissner/heads/work181-libs' of gi

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-libs' was updated to point to:

 e8a01961571b... Merge commit 'refs/users/meissner/heads/work181-libs' of gi

It previously pointed to:

 4ef2f307279d... Merge commit 'refs/users/meissner/heads/work181-libs' of gi

Diff:

Summary of changes (added commits):
---

  e8a0196... Merge commit 'refs/users/meissner/heads/work181-libs' of gi
  8e48fdf... Add ChangeLog.libs and update REVISION.
  e794689... Update ChangeLog.* (*)
  7ab185d... Add -mcpu=future tuning support. (*)
  2e4723b... Add support for -mcpu=future (*)
  e369efc... Update tests to work with architecture flags changes. (*)
  93ac155... Change TARGET_MODULO to TARGET_POWER9 (*)
  82fe872... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  492d7f2... Change TARGET_CMPB to TARGET_POWER6 (*)
  d7027d7... Change TARGET_FPRND to TARGET_POWER5X (*)
  8166d15... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  8e34b86... Do not allow -mvsx to boost processor to power7. (*)
  6704009... Use architecture flags for defining _ARCH_PWR macros. (*)
  036b90d... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work181-libs' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work181-dmf)] Add ChangeLog.dmf and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:592c968efd0983624138a6a7deb6a9b431589c47

commit 592c968efd0983624138a6a7deb6a9b431589c47
Author: Michael Meissner 
Date:   Mon Oct 14 11:42:15 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..0ef2e1298fff
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,5 @@
+ Branch work181-dmf, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 5cf926789393..b64275253072 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work181 branch
+work181-dmf branch

[gcc(refs/users/meissner/heads/work181-libs)] Add ChangeLog.libs and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:8e48fdf475795420d5c49db95197a91af24223b2

commit 8e48fdf475795420d5c49db95197a91af24223b2
Author: Michael Meissner 
Date:   Mon Oct 14 11:46:38 2024 -0400

Add ChangeLog.libs and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.libs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.libs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs
new file mode 100644
index ..8f396b6bb10c
--- /dev/null
+++ b/gcc/ChangeLog.libs
@@ -0,0 +1,5 @@
+ Branch work181-libs, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 5cf926789393..93e72340b654 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work181 branch
+work181-libs branch

[gcc(refs/users/meissner/heads/work181-libs)] Merge commit 'refs/users/meissner/heads/work181-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:e8a01961571bd1fee615eee8de87fd8a05d4fedf

commit e8a01961571bd1fee615eee8de87fd8a05d4fedf
Merge: 8e48fdf47579 4ef2f307279d
Author: Michael Meissner 
Date:   Mon Oct 14 12:33:52 2024 -0400

Merge commit 'refs/users/meissner/heads/work181-libs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work181-libs

Diff:

[gcc(refs/users/meissner/heads/work181)] Change TARGET_POPCNTB to TARGET_POWER5

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:8166d15cead0eb497e0d3f8ec9f73f09a4ecd696

commit 8166d15cead0eb497e0d3f8ec9f73f09a4ecd696
Author: Michael Meissner 
Date:   Mon Oct 14 12:18:56 2024 -0400

Change TARGET_POPCNTB to TARGET_POWER5

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTB to TARGET_POWER5.  The POPCNTB instruction was added in ISA 
2.02
(power5).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER5 instead of TARGET_POPCNTB.
* config/rs6000/rs6000.h (TARGET_EXTRA_BUILTINS): Use TARGET_POWER5
instead of TARGET_POPCNTB.  Eliminate TARGET_CMPB and TARGET_POPCNTD
tests since TARGET_POWER5 will always be true for those tests.
(TARGET_FRE): Use TARGET_POWER5 instead of TARGET_POPCNTB.
(TARGET_FRSQRTES): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount): Use TARGET_POWER5 instead of TARGET_POPCNTB.  Drop
test for TARGET_POPCNTD (i.e power7), since TARGET_POPCNTB will 
always
be set if TARGET_POPCNTD is set.
(popcntb2): Use TARGET_POWER5 instead of TARGET_POPCNTB.
(parity2): Likewise.
(parity2_cmpb): Remove TARGET_POPCNTB test, since it will 
always
be true when TARGET_CMPB (i.e. power6) is set.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000.h  |  8 +++-
 gcc/config/rs6000/rs6000.md | 10 +-
 3 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 7ad8baca177a..4500724d895c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -547,9 +547,7 @@ extern int rs6000_vector_align[];
 
 #define TARGET_EXTRA_BUILTINS  (TARGET_POWERPC64\
 || TARGET_PPC_GPOPT /* 970/power4 */\
-|| TARGET_POPCNTB   /* ISA 2.02 */  \
-|| TARGET_CMPB  /* ISA 2.05 */  \
-|| TARGET_POPCNTD   /* ISA 2.06 */  \
+|| TARGET_POWER5/* ISA 2.02 & above */ \
 || TARGET_ALTIVEC   \
 || TARGET_VSX   \
 || TARGET_HARD_FLOAT)
@@ -563,9 +561,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRE (TARGET_HARD_FLOAT \
-&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
+&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
 
-#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \
+#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \
 && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8eda2f7bb0d7..10d13bf812d2 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -379,7 +379,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p5")
- (match_test "TARGET_POPCNTB"))
+ (match_test "TARGET_POWER5"))
  (const_int 1)
 
  (and (eq_attr "isa" "p6")
@@ -2510,7 +2510,7 @@
 (define_expand "popcount2"
   [(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
-  "TARGET_POPCNTB || TARGET_POPCNTD"
+  "TARGET_POWER5"
 {
   rs6000_emit_popcount (operands[0], operands[1]);
   DONE;
@@ -2520,7 +2520,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNS

[gcc(refs/users/meissner/heads/work181)] Change TARGET_FPRND to TARGET_POWER5X

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:d7027d757560755f678584e6a86a33117de6e238

commit d7027d757560755f678584e6a86a33117de6e238
Author: Michael Meissner 
Date:   Mon Oct 14 12:20:03 2024 -0400

Change TARGET_FPRND to TARGET_POWER5X

As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER5X.  The FPRND instruction was added in power5+.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

* config/rs6000/rs6000.cc (report_architecture_mismatch): Use
TARGET_POWER5X instead of TARGET_FPRND.
* config/rs6000/rs6000.md (fmod3): Use TARGET_POWER5X instead 
of
TARGET_FPRND.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(btrunc2): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/config/rs6000/rs6000.md | 14 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a944ffde28a6..dd51d75c4957 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -25428,7 +25428,7 @@ report_architecture_mismatch (void)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POPCNTB)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 10d13bf812d2..7f9fe609a031 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -6687,7 +6687,7 @@
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
friz %0,%1
@@ -6815,7 +6815,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
 UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_attr "type" "fp")])

[gcc(refs/users/meissner/heads/work181)] Change TARGET_CMPB to TARGET_POWER6

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:492d7f28463e13ab26cb2499bbded18c97d50b29

commit 492d7f28463e13ab26cb2499bbded18c97d50b29
Author: Michael Meissner 
Date:   Mon Oct 14 12:21:14 2024 -0400

Change TARGET_CMPB to TARGET_POWER6

As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER6.  The CMPB instruction was added in power6 
(ISA
2.05).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.h (TARGET_FCFID): Merge tests for popcntb, 
cmpb,
and popcntd into a single test for TARGET_POWER5.
(TARGET_LFIWAX): Use TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Likewise.
(cmpb): Likewise.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  6 ++
 gcc/config/rs6000/rs6000.md | 16 
 3 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 4500724d895c..d22693eb2bfb 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -448,13 +448,11 @@ extern int rs6000_vector_align[];
Enable 32-bit fcfid's on any of the switches for newer ISA machines.  */
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
-|| TARGET_POPCNTB  /* ISA 2.02 */  \
-|| TARGET_CMPB /* ISA 2.05 */  \
-|| TARGET_POPCNTD) /* ISA 2.06 */
+|| TARGET_POWER5)  /* ISA 2.02 and above */ \
 
 #define TARGET_FCTIDZ  TARGET_FCFID
 #define TARGET_STFIWX  TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX  TARGET_CMPB
+#define TARGET_LFIWAX  TARGET_POWER6
 #define TARGET_LFIWZX  TARGET_POPCNTD
 #define TARGET_FCFIDS  TARGET_POPCNTD
 #define TARGET_FCFIDU  TARGET_POPCNTD
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7f9fe609a031..0c303087e944 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -383,7 +383,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p6")
- (match_test "TARGET_CMPB"))
+ (match_test "TARGET_POWER6"))
  (const_int 1)
 
  (and (eq_attr "isa" "p7")
@@ -2544,7 +2544,7 @@
 (define_insn "parity2_cmpb"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] 
UNSPEC_PARITY))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "prty %0,%1"
   [(set_attr "type" "popcnt")])
 
@@ -2597,7 +2597,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
 (match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "cmpb %0,%1,%2"
   [(set_attr "type" "cmp")])
 
@@ -5401,7 +5401,7 @@
&& ((TARGET_PPC_GFXOPT
 && !HONOR_NANS (mode)
 && !HONOR_SIGNED_ZEROS (mode))
-   || TARGET_CMPB
+   || TARGET_POWER6
|| VECTOR_UNIT_VSX_P (mode))"
 {
   /* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5422,7 +5422,7 @@
   if (!gpc_reg_operand (operands[2], mode))
 operands[2] = copy_to_mode_reg (mode, operands[2]);
 
-  if (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))
+  if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode))
 {
   emit_insn (gen_copysign3_fcpsg

[gcc(refs/users/meissner/heads/work181)] Change TARGET_POPCNTD to TARGET_POWER7

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:82fe872b5c547a133a0e46633f3bb68d8f5a6002

commit 82fe872b5c547a133a0e46633f3bb68d8f5a6002
Author: Michael Meissner 
Date:   Mon Oct 14 12:22:26 2024 -0400

Change TARGET_POPCNTD to TARGET_POWER7

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTD to TARGET_POWER7.  The POPCNTD instruction was added in 
power7
(ISA 2.06).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

* config/rs6000/dfp.md (floatdidd2): Change TARGET_POPCNTD to
TARGET_POWER7.
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* config/rs6000/rs6000-string.cc (expand_block_compare_gpr): 
Likewise.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_popcount): Likewise.
* config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz2): Likewise.
(popcntd2): Likewise.
(lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_"): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-string.cc  |  4 ++--
 gcc/config/rs6000/rs6000.cc |  6 +++---
 gcc/config/rs6000/rs6000.h  | 16 
 gcc/config/rs6000/rs6000.md | 24 
 6 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd3..b8189390d410 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..dae43b672ea7 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P6_64:
   return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POPCNTD;
+  return TARGET_POWER7;
 case ENB_P7_64:
-  return TARGET_POPCNTD && TARGET_POWERPC64;
+  return TARGET_POWER7 && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index 55b4133b1a34..3674c4bd9847 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes, 
unsigned int base_align,
 bool
 expand_block_compare (rtx operands[])
 {
-  /* TARGET_POPCNTD is already guarded at expand cmpmemsi.  */
-  gcc_assert (TARGET_POPCNTD);
+  /* TARGET_POWER7 is already guarded at expand cmpmemsi.  */
+  gcc_assert (TARGET_POWER7);
 
   /* For P8, this case is complicated to handle because the subtract
  with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index dd51d75c4957..7d20e757c7c4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1999,7 +1999,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
  if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
 
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
 
  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -22473,7 +22473,7 @@ rs6000_rtx

[gcc(refs/users/meissner/heads/work181)] Add rs6000 architecture masks.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:036b90d27a2917aab2750bf60f8f2e7ae9dccd7a

commit 036b90d27a2917aab2750bf60f8f2e7ae9dccd7a
Author: Michael Meissner 
Date:   Mon Oct 14 12:15:24 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

This patch also changes the target_clones support to use an architecture 
mask
instead of isa bits.

This patch also switches the handling of .machine to use architecture masks 
if
they exist (power4 through power11).  All of the other PowerPCs will 
continue to
use the existing code for setting the .machine option.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument, 
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks 
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead 
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  48 +
 gcc/config/rs6000/rs6000.cc   | 215 +++---
 gcc/config/rs6000/rs6000.h|  24 +
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 259 insertions(+), 36 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..e5b6e9581331
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,48 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the optio

[gcc(refs/users/meissner/heads/work181)] Do not allow -mvsx to boost processor to power7.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:8e34b86b710266e82e823b71edf9c85d3a730be5

commit 8e34b86b710266e82e823b71edf9c85d3a730be5
Author: Michael Meissner 
Date:   Mon Oct 14 12:17:57 2024 -0400

Do not allow -mvsx to boost processor to power7.

This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7.  The user must now use -mcpu=power7 or 
higher.
This means if the user does -mvsx and the default processor does not have 
VSX
support, it will be an error.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 1 file changed, 79 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 8388542b7210..a944ffde28a6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1173,6 +1173,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3695,7 +3696,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3964,59 +3964,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target a

[gcc(refs/users/meissner/heads/work181)] Use architecture flags for defining _ARCH_PWR macros.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:67040097e351052be30aeef7196343a4cdc9b596

commit 67040097e351052be30aeef7196343a4cdc9b596
Author: Michael Meissner 
Date:   Mon Oct 14 12:17:02 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11, which are no 
longer
in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER4): New macro.
(TARGET_POWER5): Likewise.
(TARGET_POWER5X): Likewise.
(TARGET_POWER6): Likewise.
(TARGET_POWER7): Likewise.
(TARGET_POWER8): Likewise.
(TARGET_POWER9): Likewise.
(TARGET_POWER10): Likewise.
(TARGET_POWER11): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 27 +++
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h| 20 
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 52 insertions(+), 38 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 04882c396bfe..c8f33289fa38 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,23 +420,25 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefin

[gcc(refs/users/meissner/heads/work181)] Change TARGET_MODULO to TARGET_POWER9

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:93ac1555b8b2e88e23c1025b4220b5a34533f7e8

commit 93ac1555b8b2e88e23c1025b4220b5a34533f7e8
Author: Michael Meissner 
Date:   Mon Oct 14 12:23:47 2024 -0400

Change TARGET_MODULO to TARGET_POWER9

As part of the architecture flags patches, this patch changes the use of
TARGET_MODULO to TARGET_POWER9.  The modulo instructions were added in 
power9 (ISA
3.0).  Note, I did not change the uses of TARGET_MODULO where it was 
explicitly
generating different code if the machine had a modulo instruction.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER9 instead of TARGET_MODULO.
* config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
 gcc/config/rs6000/rs6000.h  | 6 +++---
 gcc/config/rs6000/rs6000.md | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index dae43b672ea7..b6093b3cb64c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3a03c32f..89ca1bad80f3 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -461,9 +461,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID   (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD  TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD  TARGET_POWER9
 
 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.  
*/
 #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bff898a4eff1..fc0d454e9a42 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
  (const_int 1)
 
  (and (eq_attr "isa" "p9v")

[gcc(refs/users/meissner/heads/work181)] Update tests to work with architecture flags changes.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:e369efc402f7a7ac4568c2dab420258a20adcdb8

commit e369efc402f7a7ac4568c2dab420258a20adcdb8
Author: Michael Meissner 
Date:   Mon Oct 14 12:24:53 2024 -0400

Update tests to work with architecture flags changes.

Two tests used -mvsx to raise the processor level to at least power7.  These
tests were rewritten to add cpu=power7 support.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-14  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 38 +++--
 gcc/testsuite/gcc.target/powerpc/pr115688.c |  3 +-
 2 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index feef76db4618..5e2ecf34f249 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_fprs } */
 /* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include 
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;

[gcc(refs/users/meissner/heads/work181)] Add support for -mcpu=future

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:2e4723b174af128a169452294fe9327fbd51e42f

commit 2e4723b174af128a169452294fe9327fbd51e42f
Author: Michael Meissner 
Date:   Mon Oct 14 12:26:25 2024 -0400

Add support for -mcpu=future

This patch adds the support that can be used in developing GCC support for
future PowerPC processors.

2024-10-14  Michael Meissner  

* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for 
-mcpu=future.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-arch.def: Add future cpu.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
-mcpu=future, define _ARCH_FUTURE.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(future cpu): Define.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power10_cost): Update comment.
(get_arch_flags): Add support for future processor.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
(TARGET_POWER11): New macro.
* config/rs6000/rs6000.md (cpu attribute): Likewise.

Diff:
---
 gcc/config.gcc  |  4 ++--
 gcc/config/rs6000/aix71.h   |  1 +
 gcc/config/rs6000/aix72.h   |  1 +
 gcc/config/rs6000/aix73.h   |  1 +
 gcc/config/rs6000/driver-rs6000.cc  |  2 ++
 gcc/config/rs6000/rs6000-arch.def   |  1 +
 gcc/config/rs6000/rs6000-c.cc   |  2 ++
 gcc/config/rs6000/rs6000-cpus.def   |  3 +++
 gcc/config/rs6000/rs6000-opts.h |  1 +
 gcc/config/rs6000/rs6000-tables.opt | 11 +++
 gcc/config/rs6000/rs6000.cc | 34 ++
 gcc/config/rs6000/rs6000.h  |  2 ++
 gcc/config/rs6000/rs6000.md |  2 +-
 13 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 71ac3badafd9..9dce896409f7 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -539,7 +539,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h 
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5646,7 +5646,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
-   "" | common | native \
+   "" | common | native | future \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d7..570ddcc451db 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b48..242ca94bd065 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662d..2bd6b4bb3c4f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -

[gcc(refs/users/meissner/heads/work181-tar)] Merge commit 'refs/users/meissner/heads/work181-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work18

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:00dae9f7d4672ab99eb12c8dcceb506f5272116c

commit 00dae9f7d4672ab99eb12c8dcceb506f5272116c
Merge: 55237aa6c1ad 5f1f68c03e81
Author: Michael Meissner 
Date:   Mon Oct 14 12:02:23 2024 -0400

Merge commit 'refs/users/meissner/heads/work181-tar' of 
git+ssh://gcc.gnu.org/git/gcc into me/work181-tar

Diff:

[gcc/meissner/heads/work181-tar] (3 commits) Merge commit 'refs/users/meissner/heads/work181-tar' of git

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-tar' was updated to point to:

 00dae9f7d467... Merge commit 'refs/users/meissner/heads/work181-tar' of git

It previously pointed to:

 5f1f68c03e81... Add ChangeLog.tar and update REVISION.

Diff:

Summary of changes (added commits):
---

  00dae9f... Merge commit 'refs/users/meissner/heads/work181-tar' of git
  55237aa... Add ChangeLog.tar and update REVISION.
  05ef8ce... Add ChangeLog.meissner and REVISION. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work181-tar' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work181-vpair)] Add ChangeLog.vpair and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:523937a3dab674d914844d819835f2bf8d08dca8

commit 523937a3dab674d914844d819835f2bf8d08dca8
Author: Michael Meissner 
Date:   Mon Oct 14 11:43:16 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 5 +
 gcc/REVISION| 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..88217963f0d9
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,5 @@
+ Branch work181-vpair, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 5cf926789393..67bbb81087f8 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work181 branch
+work181-vpair branch

[gcc/meissner/heads/work181-dmf] (3 commits) Merge commit 'refs/users/meissner/heads/work181-dmf' of git

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-dmf' was updated to point to:

 28be49ff2116... Merge commit 'refs/users/meissner/heads/work181-dmf' of git

It previously pointed to:

 6f5b94463611... Add ChangeLog.dmf and update REVISION.

Diff:

Summary of changes (added commits):
---

  28be49f... Merge commit 'refs/users/meissner/heads/work181-dmf' of git
  2d9ed97... Add ChangeLog.dmf and update REVISION.
  05ef8ce... Add ChangeLog.meissner and REVISION. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work181-dmf' matches
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[gcc(refs/users/meissner/heads/work181-sha)] Merge commit 'refs/users/meissner/heads/work181-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work18

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:cd37254fc84b7ac0a78fe78c29fe174d681f9817

commit cd37254fc84b7ac0a78fe78c29fe174d681f9817
Merge: beea0ddf229a a7951e232b3d
Author: Michael Meissner 
Date:   Mon Oct 14 12:00:25 2024 -0400

Merge commit 'refs/users/meissner/heads/work181-sha' of 
git+ssh://gcc.gnu.org/git/gcc into me/work181-sha

Diff:

[gcc(refs/users/meissner/heads/work181-test)] Add ChangeLog.test and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:273de72c68bed56eaff457b3ee556ae1d61dcdb5

commit 273de72c68bed56eaff457b3ee556ae1d61dcdb5
Author: Michael Meissner 
Date:   Mon Oct 14 11:48:26 2024 -0400

Add ChangeLog.test and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..49a2783f0668
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,5 @@
+ Branch work181-test, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 5cf926789393..8c603501b5dc 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work181 branch
+work181-test branch

[gcc/meissner/heads/work181-vpair] (3 commits) Merge commit 'refs/users/meissner/heads/work181-vpair' of g

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-vpair' was updated to point to:

 250ef7a0befe... Merge commit 'refs/users/meissner/heads/work181-vpair' of g

It previously pointed to:

 9dabd45c2873... Add ChangeLog.vpair and update REVISION.

Diff:

Summary of changes (added commits):
---

  250ef7a... Merge commit 'refs/users/meissner/heads/work181-vpair' of g
  523937a... Add ChangeLog.vpair and update REVISION.
  05ef8ce... Add ChangeLog.meissner and REVISION. (*)

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[gcc(refs/users/meissner/heads/work181)] Add -mcpu=future tuning support.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:7ab185da7948453f4245d8d5046c987e03229715

commit 7ab185da7948453f4245d8d5046c987e03229715
Author: Michael Meissner 
Date:   Mon Oct 14 12:27:07 2024 -0400

Add -mcpu=future tuning support.

This patch makes -mtune=future use the same tuning decision as 
-mtune=power11.

2024-10-14  Michael Meissner  

gcc/

* config/rs6000/power10.md (all reservations): Add future as an
alterntive to power10 and power11.

Diff:
---
 gcc/config/rs6000/power10.md | 144 +--
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 2310c4603457..e42b057dc45b 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@
-;; Scheduling description for the IBM Power10 and Power11 processors.
+;; Scheduling description for the IBM Power10, Power11, and Future processors.
 ;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
   (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +178,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle latency for updat

[gcc/meissner/heads/work181-sha] (14 commits) Merge commit 'refs/users/meissner/heads/work181-sha' of git

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-sha' was updated to point to:

 9a784521c261... Merge commit 'refs/users/meissner/heads/work181-sha' of git

It previously pointed to:

 cd37254fc84b... Merge commit 'refs/users/meissner/heads/work181-sha' of git

Diff:

Summary of changes (added commits):
---

  9a78452... Merge commit 'refs/users/meissner/heads/work181-sha' of git
  6774cc5... Add ChangeLog.sha and update REVISION.
  e794689... Update ChangeLog.* (*)
  7ab185d... Add -mcpu=future tuning support. (*)
  2e4723b... Add support for -mcpu=future (*)
  e369efc... Update tests to work with architecture flags changes. (*)
  93ac155... Change TARGET_MODULO to TARGET_POWER9 (*)
  82fe872... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  492d7f2... Change TARGET_CMPB to TARGET_POWER6 (*)
  d7027d7... Change TARGET_FPRND to TARGET_POWER5X (*)
  8166d15... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  8e34b86... Do not allow -mvsx to boost processor to power7. (*)
  6704009... Use architecture flags for defining _ARCH_PWR macros. (*)
  036b90d... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work181-sha' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work181-sha)] Add ChangeLog.sha and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:6774cc5cb2bac3f4b2f2c739cbe488b82f62e0f2

commit 6774cc5cb2bac3f4b2f2c739cbe488b82f62e0f2
Author: Michael Meissner 
Date:   Mon Oct 14 11:47:32 2024 -0400

Add ChangeLog.sha and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.sha: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.sha | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha
new file mode 100644
index ..6afb87fdaaae
--- /dev/null
+++ b/gcc/ChangeLog.sha
@@ -0,0 +1,5 @@
+ Branch work181-sha, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 5cf926789393..652cc5183061 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work181 branch
+work181-sha branch

[gcc(refs/users/meissner/heads/work181-sha)] Merge commit 'refs/users/meissner/heads/work181-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work18

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:9a784521c2611f8f1193fa062521324103cbef88

commit 9a784521c2611f8f1193fa062521324103cbef88
Merge: 6774cc5cb2ba cd37254fc84b
Author: Michael Meissner 
Date:   Mon Oct 14 12:35:27 2024 -0400

Merge commit 'refs/users/meissner/heads/work181-sha' of 
git+ssh://gcc.gnu.org/git/gcc into me/work181-sha

Diff:

[gcc(refs/users/meissner/heads/work181-tar)] Merge commit 'refs/users/meissner/heads/work181-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work18

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:f8ed11d91f5bb2ff26fcc3280dbcff960d171277

commit f8ed11d91f5bb2ff26fcc3280dbcff960d171277
Merge: ab14655c0cae 00dae9f7d467
Author: Michael Meissner 
Date:   Mon Oct 14 12:37:12 2024 -0400

Merge commit 'refs/users/meissner/heads/work181-tar' of 
git+ssh://gcc.gnu.org/git/gcc into me/work181-tar

Diff:

[gcc r15-4339] OpenACC 'nohost' clause: harmonize 'libgomp.oacc-{c-c++-common, fortran}/routine-nohost-1.*'

2024-10-14 Thread Thomas Schwinge via Gcc-cvs

https://gcc.gnu.org/g:de0320712d026a2d1eeb57aef277fa5a91808ac2

commit r15-4339-gde0320712d026a2d1eeb57aef277fa5a91808ac2
Author: Thomas Schwinge 
Date:   Mon Oct 14 14:38:13 2024 +0200

OpenACC 'nohost' clause: harmonize 
'libgomp.oacc-{c-c++-common,fortran}/routine-nohost-1.*'

The test case 'libgomp.oacc-fortran/routine-nohost-1.f90' added in 2021
commit a61f6afbee370785cf091fe46e2e022748528307 "OpenACC 'nohost' clause" 
was
dependend on inlining being enabled, and otherwise ('-fno-inline') failed to
optimize/link:

/tmp/ccb2hsPd.o: In function `MAIN__._omp_fn.0':
routine-nohost-1.f90:(.text+0xf4): undefined reference to `fact_nohost_'

However, as of recent commit 3269a722b7a03613e9c4e2862bc5088c4a17cc11
"Fortran: Use OpenACC's acc_on_device builtin, fix OpenMP' 
__builtin_is_initial_device",
we're now properly handling OpenACC/Fortran 'acc_on_device', and may specify
'-fno-inline', like done in 'libgomp.oacc-c-c++-common/routine-nohost-1.c'.

libgomp/
* testsuite/libgomp.oacc-fortran/routine-nohost-1.f90: Add
'-fno-inline'.

Diff:
---
 libgomp/testsuite/libgomp.oacc-fortran/routine-nohost-1.f90 | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libgomp/testsuite/libgomp.oacc-fortran/routine-nohost-1.f90 
b/libgomp/testsuite/libgomp.oacc-fortran/routine-nohost-1.f90
index b0537b8ff0be..e5f3e5740da3 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/routine-nohost-1.f90
+++ b/libgomp/testsuite/libgomp.oacc-fortran/routine-nohost-1.f90
@@ -7,6 +7,8 @@
 
 ! { dg-additional-options "-fdump-tree-oaccloops" }
 
+! { dg-additional-options "-fno-inline" } for stable results regarding OpenACC 
'routine'.
+
 program main
   use openacc
   implicit none

[gcc/meissner/heads/work181-tar] (14 commits) Merge commit 'refs/users/meissner/heads/work181-tar' of git

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-tar' was updated to point to:

 f8ed11d91f5b... Merge commit 'refs/users/meissner/heads/work181-tar' of git

It previously pointed to:

 00dae9f7d467... Merge commit 'refs/users/meissner/heads/work181-tar' of git

Diff:

Summary of changes (added commits):
---

  f8ed11d... Merge commit 'refs/users/meissner/heads/work181-tar' of git
  ab14655... Add ChangeLog.tar and update REVISION.
  e794689... Update ChangeLog.* (*)
  7ab185d... Add -mcpu=future tuning support. (*)
  2e4723b... Add support for -mcpu=future (*)
  e369efc... Update tests to work with architecture flags changes. (*)
  93ac155... Change TARGET_MODULO to TARGET_POWER9 (*)
  82fe872... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  492d7f2... Change TARGET_CMPB to TARGET_POWER6 (*)
  d7027d7... Change TARGET_FPRND to TARGET_POWER5X (*)
  8166d15... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  8e34b86... Do not allow -mvsx to boost processor to power7. (*)
  6704009... Use architecture flags for defining _ARCH_PWR macros. (*)
  036b90d... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work181-tar' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc r13-9112] Fix handling of ICF_NOVOPS in ipa-modref

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:d5b42d1aa0cdfc11dc400ce66fcd4d13f8622b57

commit r13-9112-gd5b42d1aa0cdfc11dc400ce66fcd4d13f8622b57
Author: Jan Hubicka 
Date:   Mon Jul 22 23:01:50 2024 +0200

Fix handling of ICF_NOVOPS in ipa-modref

As shown in somewhat convoluted testcase, ipa-modref is mistreating
ECF_NOVOPS as "having no side effects".  This come from time when
modref cared only about memory accesses and thus it was possible to
shortcut on it.

This patch removes (hopefully) all those bad shortcuts.
Bootstrapped/regtested x86_64-linux, comitted.

gcc/ChangeLog:

PR ipa/109985

* ipa-modref.cc (modref_summary::useful_p): Fix handling of 
ECF_NOVOPS.
(modref_access_analysis::process_fnspec): Likevise.
(modref_access_analysis::analyze_call): Likevise.
(propagate_unknown_call): Likevise.
(modref_propagate_in_scc): Likevise.
(modref_propagate_flags_in_scc): Likewise.
(ipa_merge_modref_summary_after_inlining): Likewise.

(cherry picked from commit efcbe7b985e24ac002a863afd609c44a67761195)

Diff:
---
 gcc/ipa-modref.cc | 36 +---
 1 file changed, 21 insertions(+), 15 deletions(-)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index d62a5703a21b..c98e38524dfb 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -332,7 +332,7 @@ modref_summary::useful_p (int ecf_flags, bool check_flags)
   if (check_flags
   && remove_useless_eaf_flags (static_chain_flags, ecf_flags, false))
 return true;
-  if (ecf_flags & (ECF_CONST | ECF_NOVOPS))
+  if (ecf_flags & ECF_CONST)
 return ((!side_effects || !nondeterministic)
&& (ecf_flags & ECF_LOOPING_CONST_OR_PURE));
   if (loads && !loads->every_base)
@@ -1261,7 +1261,7 @@ modref_access_analysis::merge_call_side_effects
   int flags = gimple_call_flags (call);
 
   /* Nothing to do for non-looping cont functions.  */
-  if ((flags & (ECF_CONST | ECF_NOVOPS))
+  if ((flags & ECF_CONST)
   && !(flags & ECF_LOOPING_CONST_OR_PURE))
 return false;
 
@@ -1274,7 +1274,7 @@ modref_access_analysis::merge_call_side_effects
   /* Merge side effects and non-determinism.
  PURE/CONST flags makes functions deterministic and if there is
  no LOOPING_CONST_OR_PURE they also have no side effects.  */
-  if (!(flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(flags & (ECF_CONST | ECF_PURE))
   || (flags & ECF_LOOPING_CONST_OR_PURE))
 {
   if (!m_summary->side_effects && callee_summary->side_effects)
@@ -1463,7 +1463,7 @@ modref_access_analysis::process_fnspec (gcall *call)
 
   /* PURE/CONST flags makes functions deterministic and if there is
  no LOOPING_CONST_OR_PURE they also have no side effects.  */
-  if (!(flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(flags & (ECF_CONST | ECF_PURE))
   || (flags & ECF_LOOPING_CONST_OR_PURE)
   || (cfun->can_throw_non_call_exceptions
  && stmt_could_throw_p (cfun, call)))
@@ -1602,12 +1602,12 @@ modref_access_analysis::analyze_call (gcall *stmt)
   print_gimple_stmt (dump_file, stmt, 0);
 }
 
-  if ((flags & (ECF_CONST | ECF_NOVOPS))
+  if ((flags & ECF_CONST)
   && !(flags & ECF_LOOPING_CONST_OR_PURE))
 {
   if (dump_file)
fprintf (dump_file,
-" - ECF_CONST | ECF_NOVOPS, ignoring all stores and all loads "
+" - ECF_CONST, ignoring all stores and all loads "
 "except for args.\n");
   return;
 }
@@ -1622,7 +1622,13 @@ modref_access_analysis::analyze_call (gcall *stmt)
   if (dump_file)
fprintf (dump_file, gimple_call_internal_p (stmt)
 ? " - Internal call" : " - Indirect call.\n");
-  process_fnspec (stmt);
+  if (flags & ECF_NOVOPS)
+{
+ set_side_effects ();
+ set_nondeterministic ();
+}
+  else
+   process_fnspec (stmt);
   return;
 }
   /* We only need to handle internal calls in IPA mode.  */
@@ -4514,7 +4520,7 @@ propagate_unknown_call (cgraph_node *node,
   return changed;
 }
 
-  if (!(ecf_flags & (ECF_CONST | ECF_NOVOPS | ECF_PURE))
+  if (!(ecf_flags & (ECF_CONST | ECF_PURE))
   || (ecf_flags & ECF_LOOPING_CONST_OR_PURE)
   || nontrivial_scc)
 {
@@ -4728,7 +4734,7 @@ modref_propagate_in_scc (cgraph_node *component_node)
  struct cgraph_node *callee;
 
  if (!callee_edge->inline_failed
-|| ((flags & (ECF_CONST | ECF_NOVOPS))
+|| ((flags & ECF_CONST)
 && !(flags & ECF_LOOPING_CONST_OR_PURE)))
continue;
 
@@ -5151,8 +5157,8 @@ modref_propagate_flags_in_scc (cgraph_node 
*component_node)
{
  escape_summary *sum = escape_summaries->get (e);
 
- if (!sum || (e->indirect_info->ecf_flags
-  & (ECF_CONST | ECF_NOVOPS)))
+ if (!sum || ((e->ind

[gcc r13-9110] Fix modref_eaf_analysis::analyze_ssa_name handling of values dereferenced to function call parameter

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:55b3fc2ab64594c4ac50925ce3d3cfdbb2a53374

commit r13-9110-g55b3fc2ab64594c4ac50925ce3d3cfdbb2a53374
Author: Jan Hubicka 
Date:   Mon Jul 22 18:08:08 2024 +0200

Fix modref_eaf_analysis::analyze_ssa_name handling of values dereferenced 
to function call parameters

modref_eaf_analysis::analyze_ssa_name misinterprets EAF flags.  If 
dereferenced
parameter is passed (to map_iterator in the testcase) it can be returned
indirectly which in turn makes it to escape into the next function call.

PR ipa/115033

gcc/ChangeLog:

* ipa-modref.cc (modref_eaf_analysis::analyze_ssa_name): Fix 
checking of
EAF flags when analysing values dereferenced as function parameters.

gcc/testsuite/ChangeLog:

* gcc.c-torture/execute/pr115033.c: New test.

(cherry picked from commit cf8ffc58aad3127031c229a75cc4b99c8ace25e0)

Diff:
---
 gcc/ipa-modref.cc  |  6 +++--
 gcc/testsuite/gcc.c-torture/execute/pr115033.c | 35 ++
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index 4ec2c7979f1e..d62a5703a21b 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -2569,8 +2569,10 @@ modref_eaf_analysis::analyze_ssa_name (tree name, bool 
deferred)
int call_flags = deref_flags
(gimple_call_arg_flags (call, i), ignore_stores);
if (!ignore_retval && !(call_flags & EAF_UNUSED)
-   && !(call_flags & EAF_NOT_RETURNED_DIRECTLY)
-   && !(call_flags & EAF_NOT_RETURNED_INDIRECTLY))
+   && (call_flags & (EAF_NOT_RETURNED_DIRECTLY
+ | EAF_NOT_RETURNED_INDIRECTLY))
+   != (EAF_NOT_RETURNED_DIRECTLY
+   | EAF_NOT_RETURNED_INDIRECTLY))
  merge_call_lhs_flags (call, i, name, false, true);
if (ecf_flags & (ECF_CONST | ECF_NOVOPS))
  m_lattice[index].merge_direct_load ();
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr115033.c 
b/gcc/testsuite/gcc.c-torture/execute/pr115033.c
new file mode 100644
index ..3e79367d401c
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr115033.c
@@ -0,0 +1,35 @@
+
+typedef struct func
+{
+  int *a;
+}func;
+__attribute__((noinline))
+void ff(struct func *t)
+{
+  *(t->a) = 0;
+}
+
+
+typedef struct mapped_iterator {
+  func F;
+}mapped_iterator;
+
+__attribute__((noinline))
+mapped_iterator map_iterator(func F) {
+  mapped_iterator t = {F};
+  return t;
+}
+
+void map_to_vector(func *F) {
+  mapped_iterator t = map_iterator(*F);
+  ff(&t.F);
+}
+int main() {
+  int resultIsStatic = 1;
+  func t ={&resultIsStatic};
+  map_to_vector(&t);
+
+  if (resultIsStatic)
+__builtin_trap();
+  __builtin_exit(0);
+}

[gcc r13-9111] Fix points_to_local_or_readonly_memory_p wrt TARGET_MEM_REF

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:63557666869a2857665df5b387240231a6f7e5fc

commit r13-9111-g63557666869a2857665df5b387240231a6f7e5fc
Author: Jan Hubicka 
Date:   Thu May 16 15:33:55 2024 +0200

Fix points_to_local_or_readonly_memory_p wrt TARGET_MEM_REF

TARGET_MEM_REF can be used to offset constant base into a memory object (to
produce lea instruction).  This confuses 
points_to_local_or_readonly_memory_p
which treats the constant address as a base of the access.

Bootstrapped/regtsted x86_64-linux, comitted.
Honza

gcc/ChangeLog:

PR ipa/113787
* ipa-fnsummary.cc (points_to_local_or_readonly_memory_p): Do not
look into TARGET_MEM_REFS with constant opreand 0.

gcc/testsuite/ChangeLog:

* gcc.c-torture/execute/pr113787.c: New test.

(cherry picked from commit 96d53252aefcbc2fe419c4c3b4bcd3fc03d4d187)

Diff:
---
 gcc/ipa-fnsummary.cc   |  4 ++-
 gcc/testsuite/gcc.c-torture/execute/pr113787.c | 38 ++
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/gcc/ipa-fnsummary.cc b/gcc/ipa-fnsummary.cc
index 63bd525b4c56..de9a6dd0c421 100644
--- a/gcc/ipa-fnsummary.cc
+++ b/gcc/ipa-fnsummary.cc
@@ -2572,7 +2572,9 @@ points_to_local_or_readonly_memory_p (tree t)
return true;
   return !ptr_deref_may_alias_global_p (t, false);
 }
-  if (TREE_CODE (t) == ADDR_EXPR)
+  if (TREE_CODE (t) == ADDR_EXPR
+  && (TREE_CODE (TREE_OPERAND (t, 0)) != TARGET_MEM_REF
+ || TREE_CODE (TREE_OPERAND (TREE_OPERAND (t, 0), 0)) != INTEGER_CST))
 return refs_local_or_readonly_memory_p (TREE_OPERAND (t, 0));
   return false;
 }
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr113787.c 
b/gcc/testsuite/gcc.c-torture/execute/pr113787.c
new file mode 100644
index ..702b6c35fc68
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr113787.c
@@ -0,0 +1,38 @@
+void foo(int x, int y, int z, int d, int *buf)
+{
+  for(int i = z; i < y-z; ++i)
+for(int j = 0; j < d; ++j)
+  /* buf[x(i+1) + j] = buf[x(i+1)-j-1] */
+  buf[i*x+(x-z+j)] = buf[i*x+(x-z-1-j)];
+}
+
+void bar(int x, int y, int z, int d, int *buf)
+{
+  for(int i = 0; i < d; ++i)
+for(int j = z; j < x-z; ++j)
+  /* buf[j+(y+i)*x] = buf[j+(y-1-i)*x] */
+  buf[j+(y-z+i)*x] = buf[j+(y-z-1-i)*x];
+}
+
+__attribute__((noipa))
+void baz(int x, int y, int d, int *buf)
+{
+  foo(x, y, 0, d, buf);
+  bar(x, y, 0, d, buf);
+}
+
+int main(void)
+{
+  int a[] = { 1, 2, 3 };
+  baz (1, 2, 1, a);
+  /* foo does:
+ buf[1] = buf[0];
+ buf[2] = buf[1];
+
+ bar does:
+ buf[2] = buf[1]; (no-op)
+ so we should have { 1, 1, 1 }.  */
+  for (int i = 0; i < 3; i++)
+if (a[i] != 1)
+  __builtin_abort ();
+}

[gcc r13-9108] testsuite: fix PR111613 test

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:1a2725d346d382503c8d4f18f095fa8678b9f823

commit r13-9108-g1a2725d346d382503c8d4f18f095fa8678b9f823
Author: Sam James 
Date:   Mon Jul 29 21:47:16 2024 +0100

testsuite: fix PR111613 test

PR ipa/111613
* gcc.c-torture/pr111613.c: Rename to..
* gcc.c-torture/execute/pr111613.c: ...this.

(cherry picked from commit 5e5d7a88932b132437069f716160f8b20862890b)

Diff:
---
 gcc/testsuite/gcc.c-torture/{ => execute}/pr111613.c | 0
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/gcc/testsuite/gcc.c-torture/pr111613.c 
b/gcc/testsuite/gcc.c-torture/execute/pr111613.c
similarity index 100%
rename from gcc/testsuite/gcc.c-torture/pr111613.c
rename to gcc/testsuite/gcc.c-torture/execute/pr111613.c

[gcc r13-9109] Fix accounting of offsets in unadjusted_ptr_and_unit_offset

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:477e905d6f300b2354ece26a474c18a84a046b9e

commit r13-9109-g477e905d6f300b2354ece26a474c18a84a046b9e
Author: Jan Hubicka 
Date:   Mon Jul 22 18:05:26 2024 +0200

Fix accounting of offsets in unadjusted_ptr_and_unit_offset

unadjusted_ptr_and_unit_offset accidentally throws away the offset computed 
by
get_addr_base_and_unit_offset. Instead of passing extra_offset it passes 
offset.

PR ipa/114207

gcc/ChangeLog:

* ipa-prop.cc (unadjusted_ptr_and_unit_offset): Fix accounting of 
offsets in ADDR_EXPR.

gcc/testsuite/ChangeLog:

* gcc.c-torture/execute/pr114207.c: New test.

(cherry picked from commit 391f46f10b0586c074014de82efe76787739bb0c)

Diff:
---
 gcc/ipa-prop.cc|  4 ++--
 gcc/testsuite/gcc.c-torture/execute/pr114207.c | 23 +++
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc
index 11ba2521b2c9..b4495dfb2732 100644
--- a/gcc/ipa-prop.cc
+++ b/gcc/ipa-prop.cc
@@ -1267,9 +1267,9 @@ unadjusted_ptr_and_unit_offset (tree op, tree *ret, 
poly_int64 *offset_ret)
 {
   if (TREE_CODE (op) == ADDR_EXPR)
{
- poly_int64 extra_offset = 0;
+ poly_int64 extra_offset;
  tree base = get_addr_base_and_unit_offset (TREE_OPERAND (op, 0),
-&offset);
+&extra_offset);
  if (!base)
{
  base = get_base_address (TREE_OPERAND (op, 0));
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr114207.c 
b/gcc/testsuite/gcc.c-torture/execute/pr114207.c
new file mode 100644
index ..052fa85e9fc6
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr114207.c
@@ -0,0 +1,23 @@
+#include 
+#include 
+
+struct S {
+int a, b;
+};
+
+__attribute__((noinline))
+void foo (struct S *s) {
+struct S ss = (struct S) {
+.a = s->b,
+.b = s->a
+};
+*s = ss;
+}
+
+int main() {
+  struct S s = {6, 12};
+  foo(&s);
+  if (s.a != 12 || s.b != 6)
+__builtin_abort ();
+  return 0;
+}

[gcc r13-9107] Fix modref's iteraction with store merging

2024-10-14 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:fefa09cb6a1afe0c16186bfc9c80f91e2d5aa5ba

commit r13-9107-gfefa09cb6a1afe0c16186bfc9c80f91e2d5aa5ba
Author: Jan Hubicka 
Date:   Mon Jul 22 19:00:39 2024 +0200

Fix modref's iteraction with store merging

Hi,
this patch fixes wrong code in case store-merging introduces load of 
function
parameter that was previously write-only (which happens for bitfields).
Without this, the whole store-merged area is consdered to be killed.

PR ipa/111613

gcc/ChangeLog:

* ipa-modref.cc (analyze_parms): Do not preserve EAF_NO_DIRECT_READ 
and
EAF_NO_INDIRECT_READ from past flags.

gcc/testsuite/ChangeLog:

* gcc.c-torture/pr111613.c: New test.

(cherry picked from commit 14074773350ffed7efdebbc553adf0f23b572e87)

Diff:
---
 gcc/ipa-modref.cc  |  3 +++
 gcc/testsuite/gcc.c-torture/pr111613.c | 29 +
 2 files changed, 32 insertions(+)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index 795c4425ce37..4ec2c7979f1e 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -3001,6 +3001,9 @@ analyze_parms (modref_summary *summary, 
modref_summary_lto *summary_lto,
 (past, ecf_flags,
  VOID_TYPE_P (TREE_TYPE
  (TREE_TYPE (current_function_decl;
+ /* Store merging can produce reads when combining together multiple
+bitfields.  See PR111613.  */
+ past &= ~(EAF_NO_DIRECT_READ | EAF_NO_INDIRECT_READ);
  if (dump_file && (flags | past) != flags && !(flags & EAF_UNUSED))
{
  fprintf (dump_file,
diff --git a/gcc/testsuite/gcc.c-torture/pr111613.c 
b/gcc/testsuite/gcc.c-torture/pr111613.c
new file mode 100644
index ..1ea1c4dec072
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/pr111613.c
@@ -0,0 +1,29 @@
+#include 
+#include 
+
+struct bitfield {
+   unsigned int field1 : 1;
+   unsigned int field2 : 1;
+   unsigned int field3 : 1;
+};
+
+__attribute__((noinline)) static void
+set_field1_and_field2(struct bitfield *b) {
+   b->field1 = 1;
+   b->field2 = 1;
+}
+
+__attribute__((noinline)) static struct bitfield *
+new_bitfield(void) {
+   struct bitfield *b = (struct bitfield *)malloc(sizeof(*b));
+   b->field3 = 1;
+   set_field1_and_field2(b);
+   return b;
+}
+
+int main(void) {
+   struct bitfield *b = new_bitfield();
+   if (b->field3 != 1)
+   __builtin_abort ();
+   return 0;
+}

[gcc r15-4322] libstdc++: Use std::move for iterator in ranges::fill [PR117094]

2024-10-14 Thread Jonathan Wakely via Libstdc++-cvs

https://gcc.gnu.org/g:03623fa91ff36ecb9faa3b55f7842a39b759594e

commit r15-4322-g03623fa91ff36ecb9faa3b55f7842a39b759594e
Author: Jonathan Wakely 
Date:   Sun Oct 13 22:48:43 2024 +0100

libstdc++: Use std::move for iterator in ranges::fill [PR117094]

Input iterators aren't required to be copyable.

libstdc++-v3/ChangeLog:

PR libstdc++/117094
* include/bits/ranges_algobase.h (__fill_fn): Use std::move for
iterator that might not be copyable.
* testsuite/25_algorithms/fill/constrained.cc: Check
non-copyable iterator with sized sentinel.

Diff:
---
 libstdc++-v3/include/bits/ranges_algobase.h|  2 +-
 .../testsuite/25_algorithms/fill/constrained.cc| 34 ++
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/bits/ranges_algobase.h 
b/libstdc++-v3/include/bits/ranges_algobase.h
index 3c8d46198c5d..0345ea850a4e 100644
--- a/libstdc++-v3/include/bits/ranges_algobase.h
+++ b/libstdc++-v3/include/bits/ranges_algobase.h
@@ -592,7 +592,7 @@ namespace ranges
if constexpr (sized_sentinel_for<_Sent, _Out>)
  {
const auto __len = __last - __first;
-   return ranges::fill_n(__first, __len, __value);
+   return ranges::fill_n(std::move(__first), __len, __value);
  }
else if constexpr (is_scalar_v<_Tp>)
  {
diff --git a/libstdc++-v3/testsuite/25_algorithms/fill/constrained.cc 
b/libstdc++-v3/testsuite/25_algorithms/fill/constrained.cc
index 126515eddcaa..7cae99f2d5ce 100644
--- a/libstdc++-v3/testsuite/25_algorithms/fill/constrained.cc
+++ b/libstdc++-v3/testsuite/25_algorithms/fill/constrained.cc
@@ -83,9 +83,43 @@ test02()
   return ok;
 }
 
+void
+test03()
+{
+  // Bug libstdc++/117094 - ranges::fill misses std::move for output_iterator
+
+  // Move-only output iterator
+  struct Iterator
+  {
+using difference_type = long;
+Iterator(int* p) : p(p) { }
+Iterator(Iterator&&) = default;
+Iterator& operator=(Iterator&&) = default;
+int& operator*() const { return *p; }
+Iterator& operator++() { ++p; return *this; }
+Iterator operator++(int) { return Iterator(p++ ); }
+int* p;
+
+struct Sentinel
+{
+  const int* p;
+  bool operator==(const Iterator& i) const { return p == i.p; }
+  long operator-(const Iterator& i) const { return p - i.p; }
+};
+
+long operator-(Sentinel s) const { return p - s.p; }
+  };
+  static_assert(std::sized_sentinel_for);
+  int a[2];
+  std::ranges::fill(Iterator(a), Iterator::Sentinel{a+2}, 999);
+  VERIFY( a[0] == 999 );
+  VERIFY( a[1] == 999 );
+}
+
 int
 main()
 {
   test01();
   static_assert(test02());
+  test03();
 }

[gcc r15-4323] Add regression test

2024-10-14 Thread Eric Botcazou via Gcc-cvs

https://gcc.gnu.org/g:df25d528d36352af9dd677a4d67e44fa5ed5dc43

commit r15-4323-gdf25d528d36352af9dd677a4d67e44fa5ed5dc43
Author: Eric Botcazou 
Date:   Mon Oct 14 11:57:57 2024 +0200

Add regression test

gcc/testsuite/
PR ada/114593
* gnat.dg/specs/generic_inst2-child2.ads: New test.
* gnat.dg/specs/generic_inst2.ads: New helper.
* gnat.dg/specs/generic_inst2-child1.ads: Likewise.

Diff:
---
 gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads | 17 +
 gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads | 10 ++
 gcc/testsuite/gnat.dg/specs/generic_inst2.ads| 11 +++
 3 files changed, 38 insertions(+)

diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
new file mode 100644
index ..18e212b2e58c
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
@@ -0,0 +1,17 @@
+generic
+package Generic_Inst2.Child1 is
+
+   function Get_Custom return Custom_Type;
+
+private
+
+   type Dummy is null record;
+
+   Placeholder : constant Dummy := (null record);
+
+   -- This type conversion fails (though only when
+   -- instantiated in the other package)
+   function Get_Custom return Custom_Type is 
+  (Custom_Type(Placeholder'Address));
+
+end Generic_Inst2.Child1;
diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
new file mode 100644
index ..3bb5b0aca107
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
@@ -0,0 +1,10 @@
+-- { dg-do compile }
+
+with Generic_Inst2.Child1;
+
+generic
+package Generic_Inst2.Child2 is
+
+   package Second is new Generic_Inst2.Child1;
+
+end Generic_Inst2.Child2;
diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst2.ads 
b/gcc/testsuite/gnat.dg/specs/generic_inst2.ads
new file mode 100644
index ..0a74e36273bd
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/generic_inst2.ads
@@ -0,0 +1,11 @@
+private with System;
+
+package Generic_Inst2 is
+
+   type Custom_Type is private;
+
+private
+
+   type Custom_Type is new System.Address;
+
+end Generic_Inst2;

[gcc r15-4326] AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371]

2024-10-14 Thread Tamar Christina via Gcc-cvs

https://gcc.gnu.org/g:306834b7f74ab61160f205e04f5bf35b71f9ec52

commit r15-4326-g306834b7f74ab61160f205e04f5bf35b71f9ec52
Author: Tamar Christina 
Date:   Mon Oct 14 13:58:09 2024 +0100

AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371]

The psel intrinsics. similar to the pext, should be name psel_lane.  This
corrects the naming.

gcc/ChangeLog:

PR target/116371
* config/aarch64/aarch64-sve-builtins-sve2.cc (class svpsel_impl):
Renamed to ...
(class svpsel_lane_impl): ... This and adjust initialization.
* config/aarch64/aarch64-sve-builtins-sve2.def (svpsel): Renamed to 
...
(svpsel_lane): ... This.
* config/aarch64/aarch64-sve-builtins-sve2.h (svpsel): Renamed to
svpsel_lane.

gcc/testsuite/ChangeLog:

PR target/116371
* gcc.target/aarch64/sme2/acle-asm/psel_b16.c,
gcc.target/aarch64/sme2/acle-asm/psel_b32.c,
gcc.target/aarch64/sme2/acle-asm/psel_b64.c,
gcc.target/aarch64/sme2/acle-asm/psel_b8.c,
gcc.target/aarch64/sme2/acle-asm/psel_c16.c,
gcc.target/aarch64/sme2/acle-asm/psel_c32.c,
gcc.target/aarch64/sme2/acle-asm/psel_c64.c,
gcc.target/aarch64/sme2/acle-asm/psel_c8.c: Renamed to
* gcc.target/aarch64/sme2/acle-asm/psel_lane_b16.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_b32.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_b64.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_b8.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_c16.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_c32.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_c64.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_c8.c: ... These.

Diff:
---
 gcc/config/aarch64/aarch64-sve-builtins-sve2.cc|  4 +-
 gcc/config/aarch64/aarch64-sve-builtins-sve2.def   |  2 +-
 gcc/config/aarch64/aarch64-sve-builtins-sve2.h |  2 +-
 .../gcc.target/aarch64/sme2/acle-asm/psel_b16.c| 89 --
 .../gcc.target/aarch64/sme2/acle-asm/psel_b32.c| 89 --
 .../gcc.target/aarch64/sme2/acle-asm/psel_b64.c| 80 ---
 .../gcc.target/aarch64/sme2/acle-asm/psel_b8.c | 89 --
 .../gcc.target/aarch64/sme2/acle-asm/psel_c16.c| 89 --
 .../gcc.target/aarch64/sme2/acle-asm/psel_c32.c| 89 --
 .../gcc.target/aarch64/sme2/acle-asm/psel_c64.c| 80 ---
 .../gcc.target/aarch64/sme2/acle-asm/psel_c8.c | 89 --
 .../aarch64/sme2/acle-asm/psel_lane_b16.c  | 89 ++
 .../aarch64/sme2/acle-asm/psel_lane_b32.c  | 89 ++
 .../aarch64/sme2/acle-asm/psel_lane_b64.c  | 80 +++
 .../aarch64/sme2/acle-asm/psel_lane_b8.c   | 89 ++
 .../aarch64/sme2/acle-asm/psel_lane_c16.c  | 89 ++
 .../aarch64/sme2/acle-asm/psel_lane_c32.c  | 89 ++
 .../aarch64/sme2/acle-asm/psel_lane_c64.c  | 80 +++
 .../aarch64/sme2/acle-asm/psel_lane_c8.c   | 89 ++
 19 files changed, 698 insertions(+), 698 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc 
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
index 146a5459930f..6a20a613f832 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
@@ -234,7 +234,7 @@ public:
   }
 };
 
-class svpsel_impl : public function_base
+class svpsel_lane_impl : public function_base
 {
 public:
   rtx
@@ -625,7 +625,7 @@ FUNCTION (svpmullb, unspec_based_function, (-1, 
UNSPEC_PMULLB, -1))
 FUNCTION (svpmullb_pair, unspec_based_function, (-1, UNSPEC_PMULLB_PAIR, -1))
 FUNCTION (svpmullt, unspec_based_function, (-1, UNSPEC_PMULLT, -1))
 FUNCTION (svpmullt_pair, unspec_based_function, (-1, UNSPEC_PMULLT_PAIR, -1))
-FUNCTION (svpsel, svpsel_impl,)
+FUNCTION (svpsel_lane, svpsel_lane_impl,)
 FUNCTION (svqabs, rtx_code_function, (SS_ABS, UNKNOWN, UNKNOWN))
 FUNCTION (svqcadd, svqcadd_impl,)
 FUNCTION (svqcvt, integer_conversion, (UNSPEC_SQCVT, UNSPEC_SQCVTU,
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def 
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
index 4543402f836f..318dfff06f0d 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
@@ -235,7 +235,7 @@ DEF_SVE_FUNCTION (svsm4ekey, binary, s_unsigned, none)
 | AARCH64_FL_SME \
 | AARCH64_FL_SM_ON)
 DEF_SVE_FUNCTION (svclamp, clamp, all_integer, none)
-DEF_SVE_FUNCTION (svpsel, select_pred, all_pred_count, none)
+DEF_SVE_FUNCTION (svpsel_lane, select_pred, all_pred_count, none)
 DEF_SVE_FUNCTION (svre

[gcc r15-4327] simplify-rtx: Fix incorrect folding of shift and AND [PR117012]

2024-10-14 Thread Tamar Christina via Gcc-cvs

https://gcc.gnu.org/g:be966baa353dfcc20b76b5a5586ab2494bb0a735

commit r15-4327-gbe966baa353dfcc20b76b5a5586ab2494bb0a735
Author: Tamar Christina 
Date:   Mon Oct 14 14:00:25 2024 +0100

simplify-rtx: Fix incorrect folding of shift and AND [PR117012]

The optimization added in r15-1047-g7876cde25cbd2f is using the wrong
operaiton to check for uniform constant vectors.

The Author intended to check that all the lanes in the vector are the same 
and
so used CONST_VECTOR_DUPLICATE_P.  However this only checks that the vector
is created from a pattern duplication, but doesn't say how many pattern
alternatives make up the duplication.  Normally would would need to check 
this
separately or use const_vec_duplicate_p.

Without this the optimization incorrectly triggers.

gcc/ChangeLog:

PR rtl-optimization/117012
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1): 
Use
const_vec_duplicate_p instead of CONST_VECTOR_DUPLICATE_P.

gcc/testsuite/ChangeLog:

PR rtl-optimization/117012
* gcc.target/aarch64/pr117012.c: New test.

Diff:
---
 gcc/simplify-rtx.cc |  4 ++--
 gcc/testsuite/gcc.target/aarch64/pr117012.c | 16 
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index dc0d192dd218..4d024ec523b1 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -4088,10 +4088,10 @@ simplify_context::simplify_binary_operation_1 (rtx_code 
code,
   if (VECTOR_MODE_P (mode) && GET_CODE (op0) == ASHIFTRT
  && (CONST_INT_P (XEXP (op0, 1))
  || (GET_CODE (XEXP (op0, 1)) == CONST_VECTOR
- && CONST_VECTOR_DUPLICATE_P (XEXP (op0, 1))
+ && const_vec_duplicate_p (XEXP (op0, 1))
  && CONST_INT_P (XVECEXP (XEXP (op0, 1), 0, 0
  && GET_CODE (op1) == CONST_VECTOR
- && CONST_VECTOR_DUPLICATE_P (op1)
+ && const_vec_duplicate_p (op1)
  && CONST_INT_P (XVECEXP (op1, 0, 0)))
{
  unsigned HOST_WIDE_INT shift_count
diff --git a/gcc/testsuite/gcc.target/aarch64/pr117012.c 
b/gcc/testsuite/gcc.target/aarch64/pr117012.c
new file mode 100644
index ..537c0fa566c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr117012.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define vector16 __attribute__((vector_size(16)))
+
+vector16 unsigned char
+g (vector16 unsigned char a)
+{
+  vector16 signed char b = (vector16 signed char)a;
+  b = b >> 7;
+  vector16 unsigned char c = (vector16 unsigned char)b;
+  vector16 unsigned char d = { 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 
};
+  return c & d;
+}
+
+/* { dg-final { scan-assembler-times {and\tv[0-9]+\.16b, v[0-9]+\.16b, 
v[0-9]+\.16b} 1 } } */

[gcc r15-4329] Allow for class type coarray parameters. [PR77871]

2024-10-14 Thread Andre Vehreschild via Gcc-cvs

https://gcc.gnu.org/g:fd1a2f63bcac14cbedb8c8b1790525b9642567d9

commit r15-4329-gfd1a2f63bcac14cbedb8c8b1790525b9642567d9
Author: Andre Vehreschild 
Date:   Thu Aug 15 13:49:49 2024 +0200

Allow for class type coarray parameters. [PR77871]

gcc/fortran/ChangeLog:

PR fortran/77871

* trans-expr.cc (gfc_conv_derived_to_class): Assign token when
converting a coarray to class.
(gfc_get_tree_for_caf_expr): For classes get the caf decl from
the saved descriptor.
(gfc_get_caf_token_offset):Assert that coarray=lib is set and
cover more cases where the tree having the coarray token can be.
* trans-intrinsic.cc (gfc_conv_intrinsic_caf_get): Use unified
test for pointers.

gcc/testsuite/ChangeLog:

* gfortran.dg/coarray/dummy_3.f90: New test.

Diff:
---
 gcc/fortran/trans-expr.cc | 36 ++-
 gcc/fortran/trans-intrinsic.cc|  2 +-
 gcc/testsuite/gfortran.dg/coarray/dummy_3.f90 | 33 
 3 files changed, 58 insertions(+), 13 deletions(-)

diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 8094171eb275..b9f585d0d2f1 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -810,6 +810,16 @@ gfc_conv_derived_to_class (gfc_se *parmse, gfc_expr *e, 
gfc_symbol *fsym,
   /* Now set the data field.  */
   ctree = gfc_class_data_get (var);
 
+  if (flag_coarray == GFC_FCOARRAY_LIB && CLASS_DATA (fsym)->attr.codimension)
+{
+  tree token;
+  tmp = gfc_get_tree_for_caf_expr (e);
+  if (POINTER_TYPE_P (TREE_TYPE (tmp)))
+   tmp = build_fold_indirect_ref (tmp);
+  gfc_get_caf_token_offset (parmse, &token, nullptr, tmp, NULL_TREE, e);
+  gfc_add_modify (&parmse->pre, gfc_conv_descriptor_token (ctree), token);
+}
+
   if (optional)
 cond_optional = gfc_conv_expr_present (e->symtree->n.sym);
 
@@ -2344,6 +2354,10 @@ gfc_get_tree_for_caf_expr (gfc_expr *expr)
 
   if (expr->symtree->n.sym->ts.type == BT_CLASS)
 {
+  if (DECL_P (caf_decl) && DECL_LANG_SPECIFIC (caf_decl)
+ && GFC_DECL_SAVED_DESCRIPTOR (caf_decl))
+   caf_decl = GFC_DECL_SAVED_DESCRIPTOR (caf_decl);
+
   if (expr->ref && expr->ref->type == REF_ARRAY)
{
  caf_decl = gfc_class_data_get (caf_decl);
@@ -2408,16 +2422,12 @@ gfc_get_caf_token_offset (gfc_se *se, tree *token, tree 
*offset, tree caf_decl,
 {
   tree tmp;
 
+  gcc_assert (flag_coarray == GFC_FCOARRAY_LIB);
+
   /* Coarray token.  */
   if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (caf_decl)))
-{
-  gcc_assert (GFC_TYPE_ARRAY_AKIND (TREE_TYPE (caf_decl))
-   == GFC_ARRAY_ALLOCATABLE
- || expr->symtree->n.sym->attr.select_type_temporary
- || expr->symtree->n.sym->assoc);
   *token = gfc_conv_descriptor_token (caf_decl);
-}
-  else if (DECL_LANG_SPECIFIC (caf_decl)
+  else if (DECL_P (caf_decl) && DECL_LANG_SPECIFIC (caf_decl)
   && GFC_DECL_TOKEN (caf_decl) != NULL_TREE)
 *token = GFC_DECL_TOKEN (caf_decl);
   else
@@ -2435,7 +2445,7 @@ gfc_get_caf_token_offset (gfc_se *se, tree *token, tree 
*offset, tree caf_decl,
   && (GFC_TYPE_ARRAY_AKIND (TREE_TYPE (caf_decl)) == GFC_ARRAY_ALLOCATABLE
  || GFC_TYPE_ARRAY_AKIND (TREE_TYPE (caf_decl)) == GFC_ARRAY_POINTER))
 *offset = build_int_cst (gfc_array_index_type, 0);
-  else if (DECL_LANG_SPECIFIC (caf_decl)
+  else if (DECL_P (caf_decl) && DECL_LANG_SPECIFIC (caf_decl)
   && GFC_DECL_CAF_OFFSET (caf_decl) != NULL_TREE)
 *offset = GFC_DECL_CAF_OFFSET (caf_decl);
   else if (GFC_TYPE_ARRAY_CAF_OFFSET (TREE_TYPE (caf_decl)) != NULL_TREE)
@@ -2502,11 +2512,13 @@ gfc_get_caf_token_offset (gfc_se *se, tree *token, tree 
*offset, tree caf_decl,
 }
   else if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (caf_decl)))
 tmp = gfc_conv_descriptor_data_get (caf_decl);
+  else if (INDIRECT_REF_P (caf_decl))
+tmp = TREE_OPERAND (caf_decl, 0);
   else
-   {
- gcc_assert (POINTER_TYPE_P (TREE_TYPE (caf_decl)));
- tmp = caf_decl;
-   }
+{
+  gcc_assert (POINTER_TYPE_P (TREE_TYPE (caf_decl)));
+  tmp = caf_decl;
+}
 
   *offset = fold_build2_loc (input_location, MINUS_EXPR, gfc_array_index_type,
fold_convert (gfc_array_index_type, *offset),
diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index a282ae1c0903..80d75f26b095 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -1900,7 +1900,7 @@ gfc_conv_intrinsic_caf_get (gfc_se *se, gfc_expr *expr, 
tree lhs, tree lhs_kind,
   gfc_add_block_to_block (&se->post, &argse.post);
 
   caf_decl = gfc_get_tree_for_caf_expr (array_expr);
-  if (TREE_CODE (TREE_TYPE (caf_decl)) == REFERENCE_TYPE)
+  if (POINTER_TYPE_P (TREE_TYPE (caf_decl)))
 caf_decl = build_fold_indirect_ref_loc (input_location, c

[gcc(refs/users/meissner/heads/work181)] Add ChangeLog.meissner and REVISION.

2024-10-14 Thread Michael Meissner via Libstdc++-cvs

https://gcc.gnu.org/g:05ef8ce8a9519dd5d1e332f46eae86add3d54d3f

commit 05ef8ce8a9519dd5d1e332f46eae86add3d54d3f
Author: Michael Meissner 
Date:   Mon Oct 14 11:41:15 2024 -0400

Add ChangeLog.meissner and REVISION.

2024-10-14  Michael Meissner  

gcc/

* REVISION: New file for branch.
* ChangeLog.meissner: New file.

gcc/c-family/

* ChangeLog.meissner: New file.

gcc/c/

* ChangeLog.meissner: New file.

gcc/cp/

* ChangeLog.meissner: New file.

gcc/fortran/

* ChangeLog.meissner: New file.

gcc/testsuite/

* ChangeLog.meissner: New file.

libgcc/

* ChangeLog.meissner: New file.

Diff:
---
 gcc/ChangeLog.meissner   | 5 +
 gcc/REVISION | 1 +
 gcc/c-family/ChangeLog.meissner  | 5 +
 gcc/c/ChangeLog.meissner | 5 +
 gcc/cp/ChangeLog.meissner| 5 +
 gcc/fortran/ChangeLog.meissner   | 5 +
 gcc/testsuite/ChangeLog.meissner | 5 +
 libgcc/ChangeLog.meissner| 5 +
 libstdc++-v3/ChangeLog.meissner  | 5 +
 9 files changed, 41 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
new file mode 100644
index ..2f869b4f7869
--- /dev/null
+++ b/gcc/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work181, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..5cf926789393
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work181 branch
diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner
new file mode 100644
index ..2f869b4f7869
--- /dev/null
+++ b/gcc/c-family/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work181, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner
new file mode 100644
index ..2f869b4f7869
--- /dev/null
+++ b/gcc/c/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work181, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner
new file mode 100644
index ..2f869b4f7869
--- /dev/null
+++ b/gcc/cp/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work181, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner
new file mode 100644
index ..2f869b4f7869
--- /dev/null
+++ b/gcc/fortran/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work181, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
new file mode 100644
index ..2f869b4f7869
--- /dev/null
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work181, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
new file mode 100644
index ..2f869b4f7869
--- /dev/null
+++ b/libgcc/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work181, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner
new file mode 100644
index ..2f869b4f7869
--- /dev/null
+++ b/libstdc++-v3/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work181, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch

[gcc] Created branch 'meissner/heads/work181-dmf' in namespace 'refs/users'

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-dmf' was created in namespace 'refs/users' 
pointing to:

 2e30e90a0c2b... fold-const: Fix BIT_INSERT_EXPR folding for BYTES_BIG_ENDIA

[gcc] Created branch 'meissner/heads/work181' in namespace 'refs/users'

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181' was created in namespace 'refs/users' 
pointing to:

 2e30e90a0c2b... fold-const: Fix BIT_INSERT_EXPR folding for BYTES_BIG_ENDIA

[gcc] Created branch 'meissner/heads/work181-vpair' in namespace 'refs/users'

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-vpair' was created in namespace 'refs/users' 
pointing to:

 2e30e90a0c2b... fold-const: Fix BIT_INSERT_EXPR folding for BYTES_BIG_ENDIA

[gcc(refs/users/meissner/heads/work181-dmf)] Add ChangeLog.dmf and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:6f5b944636117e4a6f4165df70761ff27dcf5490

commit 6f5b944636117e4a6f4165df70761ff27dcf5490
Author: Michael Meissner 
Date:   Mon Oct 14 11:42:15 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 5 +
 gcc/REVISION  | 1 +
 2 files changed, 6 insertions(+)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..0ef2e1298fff
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,5 @@
+ Branch work181-dmf, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..b64275253072
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work181-dmf branch

[gcc(refs/users/meissner/heads/work181-tar)] Add ChangeLog.tar and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:5f1f68c03e81ab5a8ca5f9b53e7a2e78e18aae6c

commit 5f1f68c03e81ab5a8ca5f9b53e7a2e78e18aae6c
Author: Michael Meissner 
Date:   Mon Oct 14 11:44:09 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 5 +
 gcc/REVISION  | 1 +
 2 files changed, 6 insertions(+)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index ..05435eefbf39
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,5 @@
+ Branch work181-tar, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..39f755ec2ac1
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work181-tar branch

[gcc] Created branch 'meissner/heads/work181-bugs' in namespace 'refs/users'

2024-10-14 Thread Michael Meissner via Gcc-cvs

The branch 'meissner/heads/work181-bugs' was created in namespace 'refs/users' 
pointing to:

 2e30e90a0c2b... fold-const: Fix BIT_INSERT_EXPR folding for BYTES_BIG_ENDIA

[gcc(refs/users/meissner/heads/work181-vpair)] Add ChangeLog.vpair and update REVISION.

2024-10-14 Thread Michael Meissner via Gcc-cvs

https://gcc.gnu.org/g:9dabd45c28734eaaeccf8147be54664dc781cab4

commit 9dabd45c28734eaaeccf8147be54664dc781cab4
Author: Michael Meissner 
Date:   Mon Oct 14 11:43:16 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-10-14  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 5 +
 gcc/REVISION| 1 +
 2 files changed, 6 insertions(+)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..88217963f0d9
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,5 @@
+ Branch work181-vpair, baseline 
+
+2024-10-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..67bbb81087f8
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work181-vpair branch

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