[gcc r15-2713] libgomp.texi: Add OpenMP TR13 routines to @menu (commented out)

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:1a5734135d265a7b363ead9f821676a2a358969b

commit r15-2713-g1a5734135d265a7b363ead9f821676a2a358969b
Author: Tobias Burnus 
Date:   Mon Aug 5 09:18:29 2024 +0200

libgomp.texi: Add OpenMP TR13 routines to @menu (commented out)

To keep track of missing routine documentation (both implemented and not),
the libgomp.texi file contains all non-OMPT routines as commented items
in @menu. This commit adds the routines added in TR13 as commented fixme
items.

libgomp/ChangeLog:

* libgomp.texi (OpenMP Runtime Library Routines): Add TR13 routines
to @menu (commented out).

Diff:
---
 libgomp/libgomp.texi | 27 +--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/libgomp/libgomp.texi b/libgomp/libgomp.texi
index 07cd75124b07..c6759dd03bc3 100644
--- a/libgomp/libgomp.texi
+++ b/libgomp/libgomp.texi
@@ -1591,12 +1591,18 @@ They have C linkage and do not throw exceptions.
 @menu
 * omp_get_num_procs::   Number of processors online
 @c * omp_get_max_progress_width:: /TR11
+@c * omp_get_device_from_uid::  /TR13
+@c * omp_get_uid_from_device::  /TR13
 * omp_set_default_device::  Set the default device for target regions
 * omp_get_default_device::  Get the default device for target regions
 * omp_get_num_devices:: Number of target devices
 * omp_get_device_num::  Get device that current thread is running on
 * omp_is_initial_device::   Whether executing on the host device
 * omp_get_initial_device::  Device number of host device
+@c * omp_get_device_num_teams::  /TR13
+@c * omp_set_device_num_teams::  /TR13
+@c * omp_get_device_teams_thread_limit::  /TR13
+@c * omp_set_device_teams_thread_limit::  /TR13
 @end menu
 
 
@@ -2813,8 +2819,27 @@ Routines to manage and allocate memory on the current 
device.
 They have C linkage and do not throw exceptions.
 
 @menu
+@c * omp_get_devices_memspace:: /TR13
+@c * omp_get_device_memspace:: /TR13
+@c * omp_get_devices_and_host_memspace:: /TR13
+@c * omp_get_device_and_host_memspace:: /TR13
+@c * omp_get_devices_all_memspace:: /TR13
+@c * omp_get_memspace_num_resources:: /TR11
+@c * omp_get_memspace_pagesize:: /TR13
+@c * omp_get_submemspace:: /TR11
+@c * omp_init_mempartitioner:: /TR13
+@c * omp_destroy_mempartitioner:: /TR13
+@c * omp_init_mempartition:: /TR13
+@c * omp_destroy_mempartition:: /TR13
+@c * omp_mempartition_set_part:: /TR13
+@c * omp_mempartition_get_user_data:: /TR13
 * omp_init_allocator:: Create an allocator
 * omp_destroy_allocator:: Destroy an allocator
+@c * omp_get_devices_allocator:: /TR13
+@c * omp_get_device_allocator:: /TR13
+@c * omp_get_devices_and_host_allocator:: /TR13
+@c * omp_get_device_and_host_allocator:: /TR13
+@c * omp_get_devices_all_allocator:: /TR13
 * omp_set_default_allocator:: Set the default allocator
 * omp_get_default_allocator:: Get the default allocator
 * omp_alloc:: Memory allocation with an allocator
@@ -2823,8 +2848,6 @@ They have C linkage and do not throw exceptions.
 * omp_calloc:: Allocate nullified memory with an allocator
 * omp_aligned_calloc:: Allocate nullified aligned memory with an allocator
 * omp_realloc:: Reallocate memory allocated with OpenMP routines
-@c * omp_get_memspace_num_resources:: /TR11
-@c * omp_get_submemspace:: /TR11
 @end menu

[gcc r15-2714] gdbhooks: Make dot viewer configurable

[Alex Coplan via Gcc-cvs]

https://gcc.gnu.org/g:08cc516a8cfe553064f84a86be4c30f05a614342

commit r15-2714-g08cc516a8cfe553064f84a86be4c30f05a614342
Author: Alex Coplan 
Date:   Mon Aug 5 08:45:29 2024 +0100

gdbhooks: Make dot viewer configurable

This adds a new GDB parameter 'gcc-dot-cmd' which allows the user to
configure the command used to render the CFG within dot-fn.

E.g. with this patch the user can change their dot viewer like so:

(gdb) show gcc-dot-cmd
The current value of 'gcc-dot-cmd' is "dot -Tx11".
(gdb) set gcc-dot-cmd xdot
(gdb) dot-fn # opens in xdot

The second patch in this series adds a hook which users can define in
their .gdbinit in order to be called when the GCC extensions have
finished loading, thus allowing users to automatically configure
gcc-dot-cmd as desired in their .gdbinit.

gcc/ChangeLog:

* gdbhooks.py (GCCDotCmd): New.
(gcc_dot_cmd): New. Use it ...
(DotFn.invoke): ... here.

Diff:
---
 gcc/gdbhooks.py | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/gcc/gdbhooks.py b/gcc/gdbhooks.py
index 92e38880a70a..db8ce0d071bb 100644
--- a/gcc/gdbhooks.py
+++ b/gcc/gdbhooks.py
@@ -783,6 +783,18 @@ class DumpFn(gdb.Command):
 
 DumpFn()
 
+class GCCDotCmd(gdb.Parameter):
+"""
+This parameter controls the command used to render dot files within
+GCC's dot-fn command.  It will be invoked as gcc-dot-cmd .
+"""
+def __init__(self):
+super(GCCDotCmd, self).__init__('gcc-dot-cmd',
+gdb.COMMAND_NONE, gdb.PARAM_STRING)
+self.value = "dot -Tx11"
+
+gcc_dot_cmd = GCCDotCmd()
+
 class DotFn(gdb.Command):
 """
 A custom command to show a gimple/rtl function control flow graph.
@@ -848,7 +860,8 @@ class DotFn(gdb.Command):
 return
 
 # Show graph in temp file
-os.system("( dot -Tx11 \"%s\"; rm \"%s\" ) &" % (filename, filename))
+dot_cmd = gcc_dot_cmd.value
+os.system("( %s \"%s\"; rm \"%s\" ) &" % (dot_cmd, filename, filename))
 
 DotFn()

[gcc r15-2715] gdbhooks: Add attempt to invoke on-gcc-hooks-load

[Alex Coplan via Gcc-cvs]

https://gcc.gnu.org/g:f01df5e47b2551e0f435a9efa8e0a30142f3d46b

commit r15-2715-gf01df5e47b2551e0f435a9efa8e0a30142f3d46b
Author: Alex Coplan 
Date:   Mon Aug 5 08:45:58 2024 +0100

gdbhooks: Add attempt to invoke on-gcc-hooks-load

This extends GCC's GDB hooks to attempt invoking the user-defined
command "on-gcc-hooks-load".  The idea is that users can define the
command in their .gdbinit to override the default values of parameters
defined by GCC's GDB extensions.

For example, together with the previous patch, I can add the following
fragment to my .gdbinit:

define on-gcc-hooks-load
  set gcc-dot-cmd xdot
end

which means, once the GCC extensions get loaded, whenever I invoke
dot-fn then the graph will be rendered using xdot.

The try/except should make this patch a no-op for users that don't
currently define this command.  I looked for a way to test explicitly
for whether a GDB command exists but didn't find one.

This is needed because the user's .gdbinit is sourced before GCC's GDB
extensions are loaded, and GCC-specific parameters can't be configured
before they are defined.

gcc/ChangeLog:

* gdbhooks.py: Add attempted call to "on-gcc-hooks-load" once
we've finished loading the hooks.

Diff:
---
 gcc/gdbhooks.py | 8 
 1 file changed, 8 insertions(+)

diff --git a/gcc/gdbhooks.py b/gcc/gdbhooks.py
index db8ce0d071bb..7a64c03b8acb 100644
--- a/gcc/gdbhooks.py
+++ b/gcc/gdbhooks.py
@@ -865,4 +865,12 @@ class DotFn(gdb.Command):
 
 DotFn()
 
+# Try and invoke the user-defined command "on-gcc-hooks-load".  Doing
+# this allows users to customize the GCC extensions once they've been
+# loaded by defining the hook in their .gdbinit.
+try:
+gdb.execute('on-gcc-hooks-load')
+except gdb.error:
+pass
+
 print('Successfully loaded GDB hooks for GCC')

[gcc r15-2716] Don't override 'LIBS' if '--enable-languages=rust'; use 'CRAB1_LIBS'

[Thomas Schwinge via Gcc-cvs]

https://gcc.gnu.org/g:816c4de4d062c89f5b7a68f68f29b2b033f5b136

commit r15-2716-g816c4de4d062c89f5b7a68f68f29b2b033f5b136
Author: Thomas Schwinge 
Date:   Mon Aug 5 10:06:05 2024 +0200

Don't override 'LIBS' if '--enable-languages=rust'; use 'CRAB1_LIBS'

Recent commit 6fef4d6ffcab0fec8518adcb05458cba5dbeac25
"gccrs: libgrust: Add format_parser library", added a general override of
'LIBS += -ldl -lpthread' if '--enable-languages=rust'.  This is wrong
conceptually, and will make the build fail on systems not providing such
libraries.  Instead, 'CRAB1_LIBS', added a while ago in
commit 75299e4fe50aa8d9b3ff529e48db4ed246083e64
"rust: Do not link with libdl and libpthread unconditionally", should be 
used,
and not generally, but for 'crab1' only.

gcc/rust/
* Make-lang.in (LIBS): Don't override.
(crab1$(exeext):): Use 'CRAB1_LIBS'.

Diff:
---
 gcc/rust/Make-lang.in | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/rust/Make-lang.in b/gcc/rust/Make-lang.in
index 24229c02770d..c3be5f9d81b5 100644
--- a/gcc/rust/Make-lang.in
+++ b/gcc/rust/Make-lang.in
@@ -54,8 +54,6 @@ GCCRS_D_OBJS = \
rust/rustspec.o \
$(END)
 
-LIBS += -ldl -lpthread
-
 gccrs$(exeext): $(GCCRS_D_OBJS) $(EXTRA_GCC_OBJS) libcommon-target.a $(LIBDEPS)
+$(LINKER) $(ALL_LINKERFLAGS) $(LDFLAGS) -o $@ \
  $(GCCRS_D_OBJS) $(EXTRA_GCC_OBJS) libcommon-target.a \
@@ -237,7 +235,7 @@ RUST_LIBDEPS = $(LIBDEPS) $(LIBPROC_MACRO_INTERNAL)
 crab1$(exeext): $(RUST_ALL_OBJS) attribs.o $(BACKEND) $(RUST_LIBDEPS) 
$(rust.prev)
@$(call LINK_PROGRESS,$(INDEX.rust),start)
+$(LLINKER) $(ALL_LINKERFLAGS) $(LDFLAGS) -o $@ \
- $(RUST_ALL_OBJS) attribs.o $(BACKEND) $(LIBS) 
$(LIBPROC_MACRO_INTERNAL) $(LIBFORMAT_PARSER) $(BACKENDLIBS)
+ $(RUST_ALL_OBJS) attribs.o $(BACKEND) $(LIBS) $(CRAB1_LIBS) 
$(LIBPROC_MACRO_INTERNAL) $(LIBFORMAT_PARSER) $(BACKENDLIBS)
@$(call LINK_PROGRESS,$(INDEX.rust),end)
 
 # Build hooks.

[gcc r15-2717] Inline 'gcc/rust/Make-lang.in:RUST_LIBDEPS'

[Thomas Schwinge via Gcc-cvs]

https://gcc.gnu.org/g:aab9f33ed1f1b92444a82eb3ea5cab1048593791

commit r15-2717-gaab9f33ed1f1b92444a82eb3ea5cab1048593791
Author: Thomas Schwinge 
Date:   Wed Feb 28 23:06:25 2024 +0100

Inline 'gcc/rust/Make-lang.in:RUST_LIBDEPS'

..., also fixing up an apparently mis-merged
commit 2340894554334a310b891a1d9e9d5e3f502357ac
"gccrs: Add 'gcc/rust/Make-lang.in:LIBFORMAT_PARSER'", which was adding a 
bogus
second definition of 'RUST_LIBDEPS'.

gcc/rust/
* Make-lang.in (RUST_LIBDEPS): Inline into all users.

Diff:
---
 gcc/rust/Make-lang.in | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/gcc/rust/Make-lang.in b/gcc/rust/Make-lang.in
index c3be5f9d81b5..aed9a998c80a 100644
--- a/gcc/rust/Make-lang.in
+++ b/gcc/rust/Make-lang.in
@@ -226,13 +226,8 @@ rust_OBJS = $(RUST_ALL_OBJS) rust/rustspec.o
 LIBPROC_MACRO_INTERNAL = 
../libgrust/libproc_macro_internal/libproc_macro_internal.a
 LIBFORMAT_PARSER = ../libgrust/libformat_parser/debug/liblibformat_parser.a
 
-RUST_LIBDEPS = $(LIBDEPS) $(LIBPROC_MACRO_INTERNAL) $(LIBFORMAT_PARSER)
-
-
-RUST_LIBDEPS = $(LIBDEPS) $(LIBPROC_MACRO_INTERNAL)
-
 # The compiler itself is called crab1
-crab1$(exeext): $(RUST_ALL_OBJS) attribs.o $(BACKEND) $(RUST_LIBDEPS) 
$(rust.prev)
+crab1$(exeext): $(RUST_ALL_OBJS) attribs.o $(BACKEND) $(LIBDEPS) 
$(LIBPROC_MACRO_INTERNAL) $(LIBFORMAT_PARSER) $(rust.prev)
@$(call LINK_PROGRESS,$(INDEX.rust),start)
+$(LLINKER) $(ALL_LINKERFLAGS) $(LDFLAGS) -o $@ \
  $(RUST_ALL_OBJS) attribs.o $(BACKEND) $(LIBS) $(CRAB1_LIBS) 
$(LIBPROC_MACRO_INTERNAL) $(LIBFORMAT_PARSER) $(BACKENDLIBS)

[gcc r15-2718] Revert "Make may_trap_p_1 return false for constant pool references [PR116145]" [PR116200]

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:162a1ed70303a031c81b0aaac499aaf394560390

commit r15-2718-g162a1ed70303a031c81b0aaac499aaf394560390
Author: Richard Sandiford 
Date:   Mon Aug 5 10:02:45 2024 +0100

Revert "Make may_trap_p_1 return false for constant pool references 
[PR116145]" [PR116200]

This reverts commit ba730fd10934e4ca004251aa3748bf9da4d35e62.

Diff:
---
 gcc/rtlanal.cc | 14 ++-
 .../gcc.target/aarch64/sve/acle/general/pr116145.c | 46 --
 2 files changed, 4 insertions(+), 56 deletions(-)

diff --git a/gcc/rtlanal.cc b/gcc/rtlanal.cc
index 893a6afbbc53..4158a531bdd7 100644
--- a/gcc/rtlanal.cc
+++ b/gcc/rtlanal.cc
@@ -3152,16 +3152,10 @@ may_trap_p_1 (const_rtx x, unsigned flags)
  && MEM_VOLATILE_P (x)
  && XEXP (x, 0) == stack_pointer_rtx)
return true;
-  if (/* MEM_READONLY_P means that the memory is both statically
-allocated and readonly, so MEM_NOTRAP_P should remain true
-even if the memory reference is moved.  This is certainly
-true for the important case of force_const_mem.
-
-Otherwise, MEM_NOTRAP_P only relates to the actual position
-of the memory reference; moving it out of context such as
-when moving code when optimizing, might cause its address
-to become invalid.  */
- (code_changed && !MEM_READONLY_P (x))
+  if (/* MEM_NOTRAP_P only relates to the actual position of the memory
+reference; moving it out of context such as when moving code
+when optimizing, might cause its address to become invalid.  */
+ code_changed
  || !MEM_NOTRAP_P (x))
{
  poly_int64 size = MEM_SIZE_KNOWN_P (x) ? MEM_SIZE (x) : -1;
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr116145.c 
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr116145.c
deleted file mode 100644
index a3d93d3e1c84..
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr116145.c
+++ /dev/null
@@ -1,46 +0,0 @@
-// { dg-options "-O2" }
-
-#include 
-#include 
-
-#pragma GCC target "+sve2"
-
-typedef unsigned char uchar;
-
-const uchar *
-search_line_fast (const uchar *s, const uchar *end)
-{
-  size_t VL = svcntb();
-  svuint8_t arr1, arr2;
-  svbool_t pc, pg = svptrue_b8();
-
-  // This should not be loaded inside the loop every time.
-  arr2 = svreinterpret_u8(svdup_u32(0x0a0d5c3f));
-
-  for (; s+VL <= end; s += VL) {
-arr1 = svld1_u8(pg, s);
-pc = svmatch_u8(pg, arr1, arr2);
-
-if (svptest_any(pg, pc)) {
-  pc = svbrkb_z(pg, pc);
-  return s+svcntp_b8(pg, pc);
-}
-  }
-
-  // Handle remainder.
-  if (s < end) {
-pg = svwhilelt_b8((size_t)s, (size_t)end);
-
-arr1 = svld1_u8(pg, s);
-pc = svmatch_u8(pg, arr1, arr2);
-
-if (svptest_any(pg, pc)) {
-  pc = svbrkb_z(pg, pc);
-  return s+svcntp_b8(pg, pc);
-}
-  }
-
-  return end;
-}
-
-// { dg-final { scan-assembler {:\n\tld1b\t[^\n]*\n\tmatch\t[^\n]*\n\tb\.} } }

[gcc r15-2719] vect: Fix dot-product slp testcases [PR116000]

[Feng Xue via Gcc-cvs]

https://gcc.gnu.org/g:8e2c9360c2df4b16582d3b9eb34e8c448798a1f3

commit r15-2719-g8e2c9360c2df4b16582d3b9eb34e8c448798a1f3
Author: Feng Xue 
Date:   Mon Aug 5 18:13:55 2024 +0800

vect: Fix dot-product slp testcases [PR116000]

These testcases were added by the patch of supporting multiple lane-reducing
operations. For target that has no dot-product instrution, we should add
matching condition to skip it.

2024-08-05 Feng Xue 

gcc/testsuite/
PR tree-optimization/116000
* gcc.dg/vect/vect-reduc-chain-dot-slp-1.c: Skip target with no dot-
product instruction.
* gcc.dg/vect/vect-reduc-chain-dot-slp-2.c: Likewise.
* gcc.dg/vect/vect-reduc-chain-dot-slp-3.c: Likewise.
* gcc.dg/vect/vect-reduc-chain-dot-slp-4.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c | 3 +--
 gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c | 3 +--
 gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c | 3 +--
 gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c | 3 +--
 4 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c 
b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c
index 72a370ab3c01..0901357ea6ad 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c
@@ -91,5 +91,4 @@ main (void)
 }
 
 /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" 
} } */
-/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */
-/* { dg-final { scan-tree-dump-times "vectorizing statement: \\S+ = 
DOT_PROD_EXPR" 16 "vect" } } */
+/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = 
DOT_PROD_EXPR" "vect" { target vect_sdot_qi } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c 
b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c
index aab86ee2f1cd..818eeddcece1 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c
@@ -63,5 +63,4 @@ main (void)
 }
 
 /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" 
} } */
-/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */
-/* { dg-final { scan-tree-dump-times "vectorizing statement: \\S+ = 
DOT_PROD_EXPR" 5 "vect" } } */
+/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = 
DOT_PROD_EXPR" "vect" { target vect_sdot_qi } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c 
b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c
index 9f1d2136ab6e..87541cd83423 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c
@@ -75,5 +75,4 @@ main (void)
 }
 
 /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" 
} } */
-/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */
-/* { dg-final { scan-tree-dump-times "vectorizing statement: \\S+ = 
DOT_PROD_EXPR" 8 "vect"  { target vect_sdot_hi } } } */
+/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = 
DOT_PROD_EXPR" "vect" { target vect_sdot_hi } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c 
b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c
index f4dcebdfa100..11719430e582 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c
@@ -59,5 +59,4 @@ main (void)
 }
 
 /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" 
} } */
-/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */
-/* { dg-final { scan-tree-dump-times "vectorizing statement: \\S+ = 
DOT_PROD_EXPR" 3 "vect"  { target vect_sdot_hi } } } */
+/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = 
DOT_PROD_EXPR" "vect" { target vect_sdot_hi } } } */

[gcc r15-2720] tree-reassoc.cc: PR tree-optimization/116139 Don't assert when forming fully-pipelined FMAs on wide

[Kyrylo Tkachov via Gcc-cvs]

https://gcc.gnu.org/g:44da85f4455ea11296667434172810ea76a62add

commit r15-2720-g44da85f4455ea11296667434172810ea76a62add
Author: Kyrylo Tkachov 
Date:   Fri Aug 2 06:21:16 2024 -0700

tree-reassoc.cc: PR tree-optimization/116139 Don't assert when forming 
fully-pipelined FMAs on wide MULT targets

The code in get_reassociation_width that forms FMAs aggressively when
they are fully pipelined expects the FMUL reassociation width in the
target to be less than for FMAs. This doesn't hold for all target
tunings.

This code shouldn't ICE, just avoid forming these FMAs here.
This patch does that.

Signed-off-by: Kyrylo Tkachov 

PR tree-optimization/116139

gcc/ChangeLog:

* tree-ssa-reassoc.cc (get_reassociation_width): Move width_mult
<= width comparison to if condition rather than assert.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/pr116139.c: New test.

Diff:
---
 gcc/testsuite/gcc.target/aarch64/pr116139.c | 35 +
 gcc/tree-ssa-reassoc.cc | 17 +++---
 2 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/gcc/testsuite/gcc.target/aarch64/pr116139.c 
b/gcc/testsuite/gcc.target/aarch64/pr116139.c
new file mode 100644
index ..78a21323030a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr116139.c
@@ -0,0 +1,35 @@
+/* PR tree-optimization/116139 */
+/* { dg-do compile } */
+/* { dg-options "-Ofast --param fully-pipelined-fma=1 -mcpu=neoverse-n3" } */
+
+#define LOOP_COUNT 8
+typedef double data_e;
+
+data_e
+foo (data_e in)
+{
+  data_e a1, a2, a3, a4;
+  data_e tmp, result = 0;
+  a1 = in + 0.1;
+  a2 = in * 0.1;
+  a3 = in + 0.01;
+  a4 = in * 0.59;
+
+  data_e result2 = 0;
+
+  for (int ic = 0; ic < LOOP_COUNT; ic++)
+{
+  tmp = a1 + a2 * a2 + a3 * a3 + a4 * a4 ;
+  result += tmp - ic;
+  result2 = result2 / 2 - tmp;
+
+  a1 += 0.91;
+  a2 += 0.1;
+  a3 -= 0.01;
+  a4 -= 0.89;
+
+}
+
+  return result + result2;
+}
+
diff --git a/gcc/tree-ssa-reassoc.cc b/gcc/tree-ssa-reassoc.cc
index d74352268b5d..70c810c51984 100644
--- a/gcc/tree-ssa-reassoc.cc
+++ b/gcc/tree-ssa-reassoc.cc
@@ -5509,16 +5509,15 @@ get_reassociation_width (vec *ops, int 
mult_num, tree lhs,
  , it is latency(MULT)*2 + latency(ADD)*2.  Assuming latency(MULT) >=
  latency(ADD), the first variant is preferred.
 
- Find out if we can get a smaller width considering FMA.  */
-  if (width > 1 && mult_num && param_fully_pipelined_fma)
+ Find out if we can get a smaller width considering FMA.
+ Assume FMUL and FMA use the same units that can also do FADD.
+ For other scenarios, such as when FMUL and FADD are using separated units,
+ the following code may not apply.  */
+
+  int width_mult = targetm.sched.reassociation_width (MULT_EXPR, mode);
+  if (width > 1 && mult_num && param_fully_pipelined_fma
+  && width_mult <= width)
 {
-  /* When param_fully_pipelined_fma is set, assume FMUL and FMA use the
-same units that can also do FADD.  For other scenarios, such as when
-FMUL and FADD are using separated units, the following code may not
-appy.  */
-  int width_mult = targetm.sched.reassociation_width (MULT_EXPR, mode);
-  gcc_checking_assert (width_mult <= width);
-
   /* Latency of MULT_EXPRs.  */
   int lat_mul
= get_mult_latency_consider_fma (ops_num, mult_num, width_mult);

[gcc r14-10558] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

[Christoph Mﾃｼllner via Gcc-cvs]

https://gcc.gnu.org/g:eccf707e5ceb7e405ffe4edfbcae2f769b8386cf

commit r14-10558-geccf707e5ceb7e405ffe4edfbcae2f769b8386cf
Author: Christoph Müllner 
Date:   Wed Jul 24 14:10:01 2024 +0200

RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

auto_inc_dec (-O3) performs optimizations like the following
if RVV and XTheadMemIdx is enabled.

(insn 23 20 27 3 (set (mem:V4QI (reg:DI 136 [ ivtmp.13 ]) [0 MEM  [(char *)_39]+0 S4 A32])
(reg:V4QI 168)) "gcc/testsuite/gcc.target/riscv/pr116033.c":12:27 
3183 {*movv4qi}
 (nil))
(insn 40 39 41 3 (set (reg:DI 136 [ ivtmp.13 ])
(plus:DI (reg:DI 136 [ ivtmp.13 ])
(const_int 20 [0x14]))) 5 {adddi3}
 (nil))
>
(insn 23 20 27 3 (set (mem:V4QI (post_modify:DI (reg:DI 136 [ ivtmp.13 ])
(plus:DI (reg:DI 136 [ ivtmp.13 ])
(const_int 20 [0x14]))) [0 MEM  [(char 
*)_39]+0 S4 A32])
(reg:V4QI 168)) "gcc/testsuite/gcc.target/riscv/pr116033.c":12:27 
3183 {*movv4qi}
 (expr_list:REG_INC (reg:DI 136 [ ivtmp.13 ])
(nil)))

The reason why the pass believes that this is legal is,
that the mode test in th_memidx_classify_address_modify()
requires INTEGRAL_MODE_P (mode), which includes vector modes.

Let's restrict the mode test such, that only MODE_INT is allowed.

PR target/116033

gcc/ChangeLog:

* config/riscv/thead.cc (th_memidx_classify_address_modify):
Fix mode test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr116033.c: New test.

(cherry picked from commit a86c0cb9379e7b86625908a0250cf698276e9e02)
Reported-by: Patrick O'Neill 
Signed-off-by: Christoph Müllner 

Diff:
---
 gcc/config/riscv/thead.cc |  6 ++
 gcc/testsuite/gcc.target/riscv/pr116033.c | 16 
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index 951b60888596..6f5edeb7e0ac 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -453,10 +453,8 @@ th_memidx_classify_address_modify (struct 
riscv_address_info *info, rtx x,
   if (!TARGET_XTHEADMEMIDX)
 return false;
 
-  if (!TARGET_64BIT && mode == DImode)
-return false;
-
-  if (!(INTEGRAL_MODE_P (mode) && GET_MODE_SIZE (mode).to_constant () <= 8))
+  if (GET_MODE_CLASS (mode) != MODE_INT
+  || GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
 return false;
 
   if (GET_CODE (x) != POST_MODIFY
diff --git a/gcc/testsuite/gcc.target/riscv/pr116033.c 
b/gcc/testsuite/gcc.target/riscv/pr116033.c
new file mode 100644
index ..881922da0260
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr116033.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gv_xtheadmemidx" { target { rv64 } } } */
+/* { dg-options "-march=rv32gv_xtheadmemidx" { target { rv32 } } } */
+
+char arr_3[20][20];
+void init()
+{
+  for (int i_0 = 0; i_0 < 20; ++i_0)
+for (int i_1 = 0; i_0 < 20; ++i_0)
+  for (int i_1 = 0; i_1 < 20; ++i_0)
+for (int i_1 = 0; i_1 < 20; ++i_1)
+  arr_3[i_0][i_1] = i_1;
+}
+
+/* { dg-final { scan-assembler-not 
"vse8.v\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),\[0-9\]+,\[0-9\]+" } } */

[gcc r15-2721] libiberty/argv.c: remove only_whitespace

[Andrew Burgess via Gcc-cvs]

https://gcc.gnu.org/g:ea238096883211f8c6e72f69912c51307996dc24

commit r15-2721-gea238096883211f8c6e72f69912c51307996dc24
Author: Andrew Burgess 
Date:   Mon Jul 29 13:47:32 2024 +0100

libiberty/argv.c: remove only_whitespace

After the commit:

  commit 5e1d530da87a6d2aa7e719744cb278e7e54a6623 (gcc-buildargv)
  Date:   Sat Feb 10 11:22:13 2024 +

  libiberty/buildargv: handle input consisting of only white space

The function only_whitespace (in argv.c) was no longer being called.
Lets delete it.

There should be no user visible changes after this commit.

2024-07-29  Andrew Burgess  

libiberty/

* argv.c (only_whitespace): Delete.

Diff:
---
 libiberty/argv.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/libiberty/argv.c b/libiberty/argv.c
index 675336273f3a..f889432a8683 100644
--- a/libiberty/argv.c
+++ b/libiberty/argv.c
@@ -124,15 +124,6 @@ consume_whitespace (const char **input)
 }
 }
 
-static int
-only_whitespace (const char* input)
-{
-  while (*input != EOS && ISSPACE (*input))
-input++;
-
-  return (*input == EOS);
-}
-
 /*
 
 @deftypefn Extension char** buildargv (char *@var{sp})

[gcc r15-2722] [MAINTAINERS] Add my email address to write after approval and DCO.

[Jennifer Schmitz via Gcc-cvs]

https://gcc.gnu.org/g:219b09215f530e4a4a3763746986b7068e00f000

commit r15-2722-g219b09215f530e4a4a3763746986b7068e00f000
Author: Jennifer Schmitz 
Date:   Mon Aug 5 14:08:19 2024 +0200

[MAINTAINERS] Add my email address to write after approval and DCO.

ChangeLog:
* MAINTAINERS: Add myself.

Diff:
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 595140b6f64f..7f697bfa193b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -763,6 +763,7 @@ Roger Sayle sayle   

 Tobias Schlüter tobi

 Bernd Schmidt   bernds  
 Will Schmidtwillschm
+Jennifer Schmitzjschmitz
 Stefan Schulze Frielinghaus stefansf
 Andreas Schwab  schwab  
 Tilo Schwarztiloschwarz 
@@ -933,6 +934,7 @@ Navid Rahimi

 Rishi Raj   
 Trevor Saunders 
 Bill Schmidt
+Jennifer Schmitz
 Nathaniel Shead 
 Nathan Sidwell  
 Edward Smith-Rowland

[gcc r15-2723] gimple ssa: Fix a typo in gimple-ssa-sccopy.cc

[Filip Kastl via Gcc-cvs]

https://gcc.gnu.org/g:bb30fdd3436987aee6a22610e1d22b091c7ded6e

commit r15-2723-gbb30fdd3436987aee6a22610e1d22b091c7ded6e
Author: Filip Kastl 
Date:   Mon Aug 5 14:39:06 2024 +0200

gimple ssa: Fix a typo in gimple-ssa-sccopy.cc

Fixes a misplaced comment in gimple-ssa-sccopy.cc.  The comment belongs
to a bitmap definition but was instead placed before the beginning of a
namespace block.

gcc/ChangeLog:

* gimple-ssa-sccopy.cc: Move a misplaced comment.

Signed-off-by: Filip Kastl 

Diff:
---
 gcc/gimple-ssa-sccopy.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/gimple-ssa-sccopy.cc b/gcc/gimple-ssa-sccopy.cc
index 138ee9a0ac48..191a4c0b451d 100644
--- a/gcc/gimple-ssa-sccopy.cc
+++ b/gcc/gimple-ssa-sccopy.cc
@@ -92,10 +92,11 @@ along with GCC; see the file COPYING3.  If not see
  Braun, Buchwald, Hack, Leissa, Mallon, Zwinkau, 2013, LNCS vol. 7791,
  Section 3.2.  */
 
+namespace {
+
 /* Bitmap tracking statements which were propagated to be removed at the end of
the pass.  */
 
-namespace {
 static bitmap dead_stmts;
 
 /* State of vertex during SCC discovery.

[gcc r15-2724] AArch64: Set instruction attribute of TST to logics_imm

[Jennifer Schmitz via Gcc-cvs]

https://gcc.gnu.org/g:7268d7249b3ca31bf322de99b1d59baf06f83eb3

commit r15-2724-g7268d7249b3ca31bf322de99b1d59baf06f83eb3
Author: Jennifer Schmitz 
Date:   Mon Jul 29 07:59:33 2024 -0700

AArch64: Set instruction attribute of TST to logics_imm

As suggested in
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658249.html,
this patch changes the instruction attribute of "*and_compare0" (TST) 
from
alus_imm to logics_imm.

The patch was bootstrapped and regtested on aarch64-linux-gnu, no 
regression.
OK for mainline?

Signed-off-by: Jennifer Schmitz 

gcc/

* config/aarch64/aarch64.md (*and_compare0): Change attribute.

Diff:
---
 gcc/config/aarch64/aarch64.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index ed1bd2ede7d7..665a333903c9 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -5408,7 +5408,7 @@
 (const_int 0)))]
   ""
   "tst\\t%0, "
-  [(set_attr "type" "alus_imm")]
+  [(set_attr "type" "logics_imm")]
 )
 
 (define_insn "*ands_compare0"

[gcc r15-2725] testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50, 51.

[Jiawei Chen via Gcc-cvs]

https://gcc.gnu.org/g:70ffc57fd2fdb3c8fa67f11d2e8e6b6275dcc7c0

commit r15-2725-g70ffc57fd2fdb3c8fa67f11d2e8e6b6275dcc7c0
Author: Jiawei 
Date:   Mon Aug 5 20:15:59 2024 +0800

testsuite: Add RISC-V to targets not xfailing 
gcc.dg/attr-alloc_size-11.c:50,51.

The test has been observed to pass on most architectures including RISC-V:
https://godbolt.org/z/8nYEvW6n1

Origin issue see:
https://gcc.gnu.org/PR79356#c11

Update RISC-V target to the pass list.

gcc/testsuite/ChangeLog:

* gcc.dg/attr-alloc_size-11.c: Add RISC-V to the list
of targets excluding xfail on lines 50 and 51.

Diff:
---
 gcc/testsuite/gcc.dg/attr-alloc_size-11.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c 
b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
index a2efe1289151..6346d5e084bd 100644
--- a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
+++ b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
@@ -47,8 +47,8 @@ typedef __SIZE_TYPE__size_t;
 
 /* The following tests fail because of missing range information.  The xfail
exclusions are PR79356.  */
-TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX);   /* { dg-warning "argument 1 
range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info 
for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-* 
cris-*-* ia64-*-* mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* 
s390*-*-* visium-*-* msp430-*-* nvptx*-*-*} } } } */
-TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for 
short" { xfail { ! { aarch64*-*-* arm*-*-* alpha*-*-* avr-*-* cris-*-* ia64-*-* 
mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* s390x-*-* visium-*-* 
msp430-*-* nvptx*-*-* } } } } */
+TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX);   /* { dg-warning "argument 1 
range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info 
for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-* 
cris-*-* ia64-*-* mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* riscv*-*-* 
sparc*-*-* s390*-*-* visium-*-* msp430-*-* nvptx*-*-*} } } } */
+TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for 
short" { xfail { ! { aarch64*-*-* arm*-*-* alpha*-*-* avr-*-* cris-*-* ia64-*-* 
mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* riscv*-*-* sparc*-*-* s390x-*-* 
visium-*-* msp430-*-* nvptx*-*-* } } } } */
 TEST (int, INT_MIN + 2, ALLOC_MAX);/* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
 TEST (int, -3, ALLOC_MAX); /* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
 TEST (int, -2, ALLOC_MAX); /* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */

[gcc r15-2726] bpf: do not emit BPF non-fetching atomic instructions

[Jose E. Marchesi via Gcc-cvs]

https://gcc.gnu.org/g:c26534d21159dd4c5d1472f0050b65e148161691

commit r15-2726-gc26534d21159dd4c5d1472f0050b65e148161691
Author: Jose E. Marchesi 
Date:   Mon Aug 5 16:23:47 2024 +0200

bpf: do not emit BPF non-fetching atomic instructions

When GCC finds a call to one of the __atomic_OP_fetch built-ins in
which the return value is not used it optimizes it into the
corresponding non-fetching atomic operation.  Up to now we had
definitions in gcc/config/bpf/atomic.md to implement both atomic_OP
and atomic_fetch_OP sets of insns:

  atomic_add -> aadd (aka xadd)
  atomic_and -> aand
  atomic_or  -> aor
  atomic_xor -> axor

  atomic_fetch_add -> afadd
  atomic_fetch_and -> afand
  atomic_fetch_or  -> afor
  atomic_fetch_xor -> afxor

This was not correct, because as it happens the non-fetching BPF
atomic instructions imply different memory ordering semantics than the
fetching BPF atomic instructions, and they cannot be used
interchangeably, as it would be expected.

This patch modifies config/bpf/atomic.md in order to not define the
atomic_{add,and,or,xor} insns.  This makes GCC to implement them in
terms of the corresponding fetching operations; this is less
efficient, but correct.  It also updates the expected results in the
corresponding tests, which are also updated to cover cases where the
value resulting from the __atomic_fetch_* operations is actually used.

Tested in bpf-unknown-none target in x86_64-linux-gnu host.

gcc/ChangeLog

* config/bpf/atomic.md ("atomic_add"): Remove insn.
("atomic_and"): Likewise
("atomic_or"): Likewise.
("atomic_xor"): Likewise.

gcc/testsuite/ChangeLog

* gcc.target/bpf/atomic-op-1.c (test_used_atomic_add): New
function.
(test_used_atomic_sub): Likewise.
(test_used_atomic_and): Likewise.
(test_used_atomic_nand): Likewise.
(test_used_atomic_or): Likewise.
(test_used_atomic_xor): Likewise.
* gcc.target/bpf/atomic-op-2.c (test_used_atomic_add): Likewise.
(test_used_atomic_sub): Likewise.
(test_used_atomic_and): Likewise.
(test_used_atomic_nand): Likewise.
(test_used_atomic_or): Likewise.
(test_used_atomic_xor): Likewise.
* gcc.target/bpf/sync-fetch-and-add.c: Expected results updated.

Diff:
---
 gcc/config/bpf/atomic.md  | 59 ++-
 gcc/testsuite/gcc.target/bpf/atomic-op-1.c| 53 +---
 gcc/testsuite/gcc.target/bpf/atomic-op-2.c| 53 +---
 gcc/testsuite/gcc.target/bpf/sync-fetch-and-add.c |  4 +-
 4 files changed, 111 insertions(+), 58 deletions(-)

diff --git a/gcc/config/bpf/atomic.md b/gcc/config/bpf/atomic.md
index be4511bb51bf..4e94c0352fe5 100644
--- a/gcc/config/bpf/atomic.md
+++ b/gcc/config/bpf/atomic.md
@@ -22,50 +22,21 @@
 
 ;;; Plain atomic modify operations.
 
-;; Non-fetching atomic add predates all other BPF atomic insns.
-;; Use xadd{w,dw} for compatibility with older GAS without support
-;; for v3 atomics.  Newer GAS supports "aadd[32]" in line with the
-;; other atomic operations.
-(define_insn "atomic_add"
-  [(set (match_operand:AMO 0 "memory_operand" "+m")
-(unspec_volatile:AMO
- [(plus:AMO (match_dup 0)
-(match_operand:AMO 1 "register_operand" "r"))
-  (match_operand:SI 2 "const_int_operand")] ;; Memory model.
- UNSPEC_AADD))]
-  ""
-  "{xadd\t%0,%1|lock *( *)%w0 += %w1}"
-  [(set_attr "type" "atomic")])
-
-(define_insn "atomic_and"
-  [(set (match_operand:AMO 0 "memory_operand" "+m")
-(unspec_volatile:AMO
- [(and:AMO (match_dup 0)
-   (match_operand:AMO 1 "register_operand" "r"))
-  (match_operand:SI 2 "const_int_operand")] ;; Memory model.
- UNSPEC_AAND))]
-  "bpf_has_v3_atomics"
-  "{aand\t%0,%1|lock *( *)%w0 &= %w1}")
-
-(define_insn "atomic_or"
-  [(set (match_operand:AMO 0 "memory_operand" "+m")
-(unspec_volatile:AMO
- [(ior:AMO (match_dup 0)
-   (match_operand:AMO 1 "register_operand" "r"))
-  (match_operand:SI 2 "const_int_operand")] ;; Memory model.
- UNSPEC_AOR))]
-  "bpf_has_v3_atomics"
-  "{aor\t%0,%1|lock *( *)%w0 %|= %w1}")
-
-(define_insn "atomic_xor"
-  [(set (match_operand:AMO 0 "memory_operand" "+m")
-(unspec_volatile:AMO
- [(xor:AMO (match_dup 0)
-   (match_operand:AMO 1 "register_operand" "r"))
-  (match_operand:SI 2 "const_int_operand")] ;; Memory model.
- UNSPEC_AXOR))]
-  "bpf_has_v3_atomics"
-  "{axor\t%0,%1|lock *( *)%w0 ^= %w1}")
+;; The BPF instruction set provides non-fetching atomic instructions
+;; that could be used to implement the corresponding named insns:
+;;
+;;  atomic_add -> aad

[gcc r15-2727] c++: fix -Wdangling-reference false positive [PR115987]

[Marek Polacek via Gcc-cvs]

https://gcc.gnu.org/g:34d947134403e7482ba4f153d8faabee0bc4933e

commit r15-2727-g34d947134403e7482ba4f153d8faabee0bc4933e
Author: Marek Polacek 
Date:   Wed Jul 31 17:33:55 2024 -0400

c++: fix -Wdangling-reference false positive [PR115987]

This fixes another false positive.  When a function is taking a
temporary of scalar type that couldn't be bound to the return type
of the function, don't warn, such a program would be ill-formed.

Thanks to Jonathan for reporting the problem.

PR c++/115987

gcc/cp/ChangeLog:

* call.cc (do_warn_dangling_reference): Don't consider a
temporary with a scalar type that cannot bind to the return type.

gcc/testsuite/ChangeLog:

* g++.dg/ext/attr-no-dangling6.C: Adjust.
* g++.dg/ext/attr-no-dangling7.C: Likewise.
* g++.dg/warn/Wdangling-reference22.C: New test.

Diff:
---
 gcc/cp/call.cc| 14 --
 gcc/testsuite/g++.dg/ext/attr-no-dangling6.C  | 22 +++---
 gcc/testsuite/g++.dg/ext/attr-no-dangling7.C  |  8 
 gcc/testsuite/g++.dg/warn/Wdangling-reference22.C | 19 +++
 4 files changed, 46 insertions(+), 17 deletions(-)

diff --git a/gcc/cp/call.cc b/gcc/cp/call.cc
index 40cb582acc70..a75e2e5e3afd 100644
--- a/gcc/cp/call.cc
+++ b/gcc/cp/call.cc
@@ -14290,8 +14290,18 @@ do_warn_dangling_reference (tree expr, bool arg_p)
/* Recurse to see if the argument is a temporary.  It could also
   be another call taking a temporary and returning it and
   initializing this reference parameter.  */
-   if (do_warn_dangling_reference (arg, /*arg_p=*/true))
- return expr;
+   if ((arg = do_warn_dangling_reference (arg, /*arg_p=*/true)))
+ {
+   /* If we know the temporary could not bind to the return type,
+  don't warn.  This is for scalars only because for classes
+  we can't be sure we are not returning its sub-object.  */
+   if (SCALAR_TYPE_P (TREE_TYPE (arg))
+   && TYPE_REF_P (rettype)
+   && !reference_related_p (TREE_TYPE (arg),
+TREE_TYPE (rettype)))
+ continue;
+   return expr;
+ }
  /* Don't warn about member functions like:
  std::any a(...);
  S& s = a.emplace({0}, 0);
diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling6.C 
b/gcc/testsuite/g++.dg/ext/attr-no-dangling6.C
index 235a5fd86c55..5b349e8e6827 100644
--- a/gcc/testsuite/g++.dg/ext/attr-no-dangling6.C
+++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling6.C
@@ -12,26 +12,26 @@ struct SF { static constexpr bool value = false; };
 
 template
 [[gnu::no_dangling(T::value)]]
-const X& get (const int& i)
+const X& get (const int& i, const X&)
 {
return i == 0 ? x1 : x2;
 }
 
 template
 [[gnu::no_dangling(B)]]
-const X& foo (const int& i)
+const X& foo (const int& i, const X&)
 {
return i == 0 ? x1 : x2;
 }
 
 [[gnu::no_dangling(val ())]]
-const X& bar (const int& i)
+const X& bar (const int& i, const X&)
 {
return i == 0 ? x1 : x2;
 }
 
 [[gnu::no_dangling(!val ())]]
-const X& baz (const int& i)
+const X& baz (const int& i, const X&)
 {
return i == 0 ? x1 : x2;
 }
@@ -52,13 +52,13 @@ auto gety() -> Span;
 void
 test ()
 {
-  [[maybe_unused]] const X& x1 = get (10);   // { dg-bogus "dangling" }
-  [[maybe_unused]] const X& x2 = get (10);   // { dg-warning "dangling" }
-  [[maybe_unused]] const X& x3 = foo (10);  // { dg-bogus "dangling" }
-  [[maybe_unused]] const X& x4 = foo (10); // { dg-warning "dangling" }
-  [[maybe_unused]] const X& x7 = foo<> (10); // { dg-bogus "dangling" }
-  [[maybe_unused]] const X& x5 = bar (10);   // { dg-bogus "dangling" }
-  [[maybe_unused]] const X& x6 = baz (10);   // { dg-warning "dangling" }
+  [[maybe_unused]] const X& x1 = get (10, X{});  // { dg-bogus 
"dangling" }
+  [[maybe_unused]] const X& x2 = get (10, X{});  // { dg-warning 
"dangling" }
+  [[maybe_unused]] const X& x3 = foo (10, X{});  // { dg-bogus 
"dangling" }
+  [[maybe_unused]] const X& x4 = foo (10, X{}); // { dg-warning 
"dangling" }
+  [[maybe_unused]] const X& x7 = foo<> (10, X{});// { dg-bogus 
"dangling" }
+  [[maybe_unused]] const X& x5 = bar (10, X{});  // { dg-bogus 
"dangling" }
+  [[maybe_unused]] const X& x6 = baz (10, X{});  // { dg-warning 
"dangling" }
 
   [[maybe_unused]] const auto &b1 = geti()[0];   // { dg-bogus "dangling" }
   [[maybe_unused]] const auto &b2 = gety()[0];   // { dg-warning "dangling" }
diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling7.C 
b/gcc/testsuite/g++.dg/ext/attr-no-dangling7.C
index 3c392ed409f8..a5fb809e6bdb 100644
--- a/gcc/testsuite/g++.dg/ext/attr-no-dangling7.C
+++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling7.C
@@ -16,16 +1

[gcc r15-2728] Update gcc fr.po

[Joseph Myers via Gcc-cvs]

https://gcc.gnu.org/g:5aa90b9db1cc27beef03411de05b87a257540d1c

commit r15-2728-g5aa90b9db1cc27beef03411de05b87a257540d1c
Author: Joseph Myers 
Date:   Mon Aug 5 16:32:59 2024 +

Update gcc fr.po

* fr.po: Update.

Diff:
---
 gcc/po/fr.po | 88 +---
 1 file changed, 36 insertions(+), 52 deletions(-)

diff --git a/gcc/po/fr.po b/gcc/po/fr.po
index c14d5719b712..149d4c098ccf 100644
--- a/gcc/po/fr.po
+++ b/gcc/po/fr.po
@@ -97,10 +97,10 @@
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: gcc 14.1.0\n"
+"Project-Id-Version: gcc 14.2.0\n"
 "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n";
 "POT-Creation-Date: 2024-07-25 16:23+\n"
-"PO-Revision-Date: 2024-05-09 14:43+0200\n"
+"PO-Revision-Date: 2024-08-03 07:39+0200\n"
 "Last-Translator: Frédéric Marchal \n"
 "Language-Team: French \n"
 "Language: fr\n"
@@ -37329,16 +37329,14 @@ msgid "comparison between two arrays"
 msgstr "comparaison entre deux tableaux"
 
 #: c-family/c-warn.cc:3832
-#, fuzzy, gcc-internal-format
-#| msgid "use unary %<+%> which decays operands to pointers or %<&%D[0] %s 
&%D[0]%> to compare the addresses"
+#, gcc-internal-format
 msgid "use unary %<+%> which decays operands to pointers or %<&%s%E%s[0] %s 
&%s%E%s[0]%> to compare the addresses"
-msgstr "utiliser le %<+%> unaire qui dégrade les opérandes vers des pointeurs 
ou %<&%D[0] %s &%D[0]%> pour comparer les adresses"
+msgstr "utiliser le %<+%> unaire qui dégrade les opérandes vers des pointeurs 
ou %<&%s%E%s[0] %s &%s%E%s[0]%> pour comparer les adresses"
 
 #: c-family/c-warn.cc:3839
-#, fuzzy, gcc-internal-format
-#| msgid "use %<&%D[0] %s &%D[0]%> to compare the addresses"
+#, gcc-internal-format
 msgid "use %<&%s%E%s[0] %s &%s%E%s[0]%> to compare the addresses"
-msgstr "utilisez %<&%D[0] %s &%D[0]%> pour comparer les adresses"
+msgstr "utilisez %<&%s%E%s[0] %s &%s%E%s[0]%> pour comparer les adresses"
 
 #: c-family/c-warn.cc:3901
 #, gcc-internal-format
@@ -43357,28 +43355,24 @@ msgid "capture by copy of RVV type %qT"
 msgstr "capture par copie du type RVV %qT"
 
 #: config/riscv/riscv-vector-builtins.cc:4645
-#, fuzzy, gcc-internal-format
-#| msgid "built-in function %qE requires the %qs ISA extension"
+#, gcc-internal-format
 msgid "built-in function %qE requires the zvfhmin or zvfh ISA extension"
-msgstr "la fonction interne %qE requiert l'extension ISA %qs"
+msgstr "la fonction interne %qE requiert l'extension ISA zvfhmin ou zvfh"
 
 #: config/riscv/riscv-vector-builtins.cc:4655
-#, fuzzy, gcc-internal-format
-#| msgid "%s %qT requires the zve32f, zve64f, zve64d or v ISA extension"
+#, gcc-internal-format
 msgid "built-in function %qE requires the zve32f, zve64f, zve64d or v ISA 
extension"
-msgstr "%s %qT requiert l'extension ISA zve32f, zve64f, zve64d ou v"
+msgstr "la fonction interne %qE requiert l'extension ISA zve32f, zve64f, 
zve64d ou v"
 
 #: config/riscv/riscv-vector-builtins.cc:4665
-#, fuzzy, gcc-internal-format
-#| msgid "built-in function %qE requires the %qs ISA extension"
+#, gcc-internal-format
 msgid "built-in function %qE requires the zve64d or v ISA extension"
-msgstr "la fonction interne %qE requiert l'extension ISA %qs"
+msgstr "la fonction interne %qE requiert l'extension ISA zve64d ou v"
 
 #: config/riscv/riscv-vector-builtins.cc:4674
-#, fuzzy, gcc-internal-format
-#| msgid "%s %qT requires the zve64x, zve64f, zve64d or v ISA extension"
+#, gcc-internal-format
 msgid "built-in function %qE requires the zve64x, zve64f, zve64d or v ISA 
extension"
-msgstr "%s %qT requiert l'extension ISA zve64x, zve64f, zve64d ou v"
+msgstr "la fonction interne %qE requiert l'extension ISA zve64x, zve64f, 
zve64d ou v"
 
 #: config/riscv/riscv-vector-builtins.cc:4694
 #, gcc-internal-format
@@ -44004,13 +43998,12 @@ msgstr "option inconnue pour %<%s=%s%>"
 #: config/rs6000/rs6000.cc:4833
 #, gcc-internal-format
 msgid "%<-mrop-protect%> requires %<-mcpu=power8%> or later"
-msgstr ""
+msgstr "%<-mrop-protect%> requiert %<-mcpu=power8%> ou ultérieur"
 
 #: config/rs6000/rs6000.cc:4837
-#, fuzzy, gcc-internal-format
-#| msgid "%qs requires the ELFv2 ABI"
+#, gcc-internal-format
 msgid "%<-mrop-protect%> requires the ELFv2 ABI"
-msgstr "%qs exige l'ABI ELFv2"
+msgstr "%<-mrop-protect%> exige l'ABI ELFv2"
 
 #: config/rs6000/rs6000.cc:4855
 #, gcc-internal-format
@@ -59409,54 +59402,46 @@ msgid "declaration %qD conflicts with builtin"
 msgstr "la déclaration %qD est en conflit avec la fonction interne"
 
 #: cp/module.cc:19122
-#, fuzzy, gcc-internal-format
-#| msgid "declaration %qD conflicts with import"
+#, gcc-internal-format
 msgid "redeclaring %qD in module %qs conflicts with import"
-msgstr "la déclaration %qD est en conflit avec l'import"
+msgstr "la redéclaration %qD dans le module %qs est en conflit avec l'import"
 
 #: cp/module.cc:19125
-#, fuzzy, gcc-internal-format
-#| msgid "declaration %qD conflicts with import"
+#, gcc-internal-format
 msgid "redeclaring %qD in global module co

[gcc r14-10559] Update gcc fr.po

[Joseph Myers via Gcc-cvs]

https://gcc.gnu.org/g:daced7625e606228e64284f2a1d0b1dec1a83965

commit r14-10559-gdaced7625e606228e64284f2a1d0b1dec1a83965
Author: Joseph Myers 
Date:   Mon Aug 5 16:34:13 2024 +

Update gcc fr.po

* fr.po: Update.

Diff:
---
 gcc/po/fr.po | 88 +---
 1 file changed, 36 insertions(+), 52 deletions(-)

diff --git a/gcc/po/fr.po b/gcc/po/fr.po
index c14d5719b712..149d4c098ccf 100644
--- a/gcc/po/fr.po
+++ b/gcc/po/fr.po
@@ -97,10 +97,10 @@
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: gcc 14.1.0\n"
+"Project-Id-Version: gcc 14.2.0\n"
 "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n";
 "POT-Creation-Date: 2024-07-25 16:23+\n"
-"PO-Revision-Date: 2024-05-09 14:43+0200\n"
+"PO-Revision-Date: 2024-08-03 07:39+0200\n"
 "Last-Translator: Frédéric Marchal \n"
 "Language-Team: French \n"
 "Language: fr\n"
@@ -37329,16 +37329,14 @@ msgid "comparison between two arrays"
 msgstr "comparaison entre deux tableaux"
 
 #: c-family/c-warn.cc:3832
-#, fuzzy, gcc-internal-format
-#| msgid "use unary %<+%> which decays operands to pointers or %<&%D[0] %s 
&%D[0]%> to compare the addresses"
+#, gcc-internal-format
 msgid "use unary %<+%> which decays operands to pointers or %<&%s%E%s[0] %s 
&%s%E%s[0]%> to compare the addresses"
-msgstr "utiliser le %<+%> unaire qui dégrade les opérandes vers des pointeurs 
ou %<&%D[0] %s &%D[0]%> pour comparer les adresses"
+msgstr "utiliser le %<+%> unaire qui dégrade les opérandes vers des pointeurs 
ou %<&%s%E%s[0] %s &%s%E%s[0]%> pour comparer les adresses"
 
 #: c-family/c-warn.cc:3839
-#, fuzzy, gcc-internal-format
-#| msgid "use %<&%D[0] %s &%D[0]%> to compare the addresses"
+#, gcc-internal-format
 msgid "use %<&%s%E%s[0] %s &%s%E%s[0]%> to compare the addresses"
-msgstr "utilisez %<&%D[0] %s &%D[0]%> pour comparer les adresses"
+msgstr "utilisez %<&%s%E%s[0] %s &%s%E%s[0]%> pour comparer les adresses"
 
 #: c-family/c-warn.cc:3901
 #, gcc-internal-format
@@ -43357,28 +43355,24 @@ msgid "capture by copy of RVV type %qT"
 msgstr "capture par copie du type RVV %qT"
 
 #: config/riscv/riscv-vector-builtins.cc:4645
-#, fuzzy, gcc-internal-format
-#| msgid "built-in function %qE requires the %qs ISA extension"
+#, gcc-internal-format
 msgid "built-in function %qE requires the zvfhmin or zvfh ISA extension"
-msgstr "la fonction interne %qE requiert l'extension ISA %qs"
+msgstr "la fonction interne %qE requiert l'extension ISA zvfhmin ou zvfh"
 
 #: config/riscv/riscv-vector-builtins.cc:4655
-#, fuzzy, gcc-internal-format
-#| msgid "%s %qT requires the zve32f, zve64f, zve64d or v ISA extension"
+#, gcc-internal-format
 msgid "built-in function %qE requires the zve32f, zve64f, zve64d or v ISA 
extension"
-msgstr "%s %qT requiert l'extension ISA zve32f, zve64f, zve64d ou v"
+msgstr "la fonction interne %qE requiert l'extension ISA zve32f, zve64f, 
zve64d ou v"
 
 #: config/riscv/riscv-vector-builtins.cc:4665
-#, fuzzy, gcc-internal-format
-#| msgid "built-in function %qE requires the %qs ISA extension"
+#, gcc-internal-format
 msgid "built-in function %qE requires the zve64d or v ISA extension"
-msgstr "la fonction interne %qE requiert l'extension ISA %qs"
+msgstr "la fonction interne %qE requiert l'extension ISA zve64d ou v"
 
 #: config/riscv/riscv-vector-builtins.cc:4674
-#, fuzzy, gcc-internal-format
-#| msgid "%s %qT requires the zve64x, zve64f, zve64d or v ISA extension"
+#, gcc-internal-format
 msgid "built-in function %qE requires the zve64x, zve64f, zve64d or v ISA 
extension"
-msgstr "%s %qT requiert l'extension ISA zve64x, zve64f, zve64d ou v"
+msgstr "la fonction interne %qE requiert l'extension ISA zve64x, zve64f, 
zve64d ou v"
 
 #: config/riscv/riscv-vector-builtins.cc:4694
 #, gcc-internal-format
@@ -44004,13 +43998,12 @@ msgstr "option inconnue pour %<%s=%s%>"
 #: config/rs6000/rs6000.cc:4833
 #, gcc-internal-format
 msgid "%<-mrop-protect%> requires %<-mcpu=power8%> or later"
-msgstr ""
+msgstr "%<-mrop-protect%> requiert %<-mcpu=power8%> ou ultérieur"
 
 #: config/rs6000/rs6000.cc:4837
-#, fuzzy, gcc-internal-format
-#| msgid "%qs requires the ELFv2 ABI"
+#, gcc-internal-format
 msgid "%<-mrop-protect%> requires the ELFv2 ABI"
-msgstr "%qs exige l'ABI ELFv2"
+msgstr "%<-mrop-protect%> exige l'ABI ELFv2"
 
 #: config/rs6000/rs6000.cc:4855
 #, gcc-internal-format
@@ -59409,54 +59402,46 @@ msgid "declaration %qD conflicts with builtin"
 msgstr "la déclaration %qD est en conflit avec la fonction interne"
 
 #: cp/module.cc:19122
-#, fuzzy, gcc-internal-format
-#| msgid "declaration %qD conflicts with import"
+#, gcc-internal-format
 msgid "redeclaring %qD in module %qs conflicts with import"
-msgstr "la déclaration %qD est en conflit avec l'import"
+msgstr "la redéclaration %qD dans le module %qs est en conflit avec l'import"
 
 #: cp/module.cc:19125
-#, fuzzy, gcc-internal-format
-#| msgid "declaration %qD conflicts with import"
+#, gcc-internal-format
 msgid "redeclaring %qD in global module c

[gcc r14-10560] Fortran: Suppress bogus used uninitialized warnings [PR108889].

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:9906a9863d65386ee4045333eb26a2569783abb5

commit r14-10560-g9906a9863d65386ee4045333eb26a2569783abb5
Author: Paul Thomas 
Date:   Thu Jul 18 08:51:35 2024 +0100

Fortran: Suppress bogus used uninitialized warnings [PR108889].

2024-07-18  Paul Thomas  

gcc/fortran
PR fortran/108889
* gfortran.h: Add bit field 'allocated_in_scope' to gfc_symbol.
* trans-array.cc (gfc_array_allocate): Set 'allocated_in_scope'
after allocation if not a component reference.
(gfc_alloc_allocatable_for_assignment): If 'allocated_in_scope'
not set, not a component ref and not allocated, set the array
bounds and offset to give zero length in all dimensions. Then
set allocated_in_scope.

gcc/testsuite/
PR fortran/108889
* gfortran.dg/pr108889.f90: New test.

(cherry picked from commit c3aa339ea50f050caf7ed2e497f5499ec2d7b9cc)

Diff:
---
 gcc/fortran/gfortran.h |  4 
 gcc/fortran/trans-array.cc | 43 ++
 gcc/testsuite/gfortran.dg/pr108889.f90 | 43 ++
 3 files changed, 90 insertions(+)

diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index de3d9e25911b..fbdf00590bc2 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -1946,6 +1946,10 @@ typedef struct gfc_symbol
   /* Set if this should be passed by value, but is not a VALUE argument
  according to the Fortran standard.  */
   unsigned pass_as_value:1;
+  /* Set if an allocatable array variable has been allocated in the current
+ scope. Used in the suppression of uninitialized warnings in reallocation
+ on assignment.  */
+  unsigned allocated_in_scope:1;
 
   /* Reference counter, used for memory management.
 
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 761f0a425078..d5d9c730826e 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -6561,6 +6561,8 @@ gfc_array_allocate (gfc_se * se, gfc_expr * expr, tree 
status, tree errmsg,
   else
   gfc_add_expr_to_block (&se->pre, set_descriptor);
 
+  expr->symtree->n.sym->allocated_in_scope = 1;
+
   return true;
 }
 
@@ -10932,6 +10934,8 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo 
*loop,
   stmtblock_t realloc_block;
   stmtblock_t alloc_block;
   stmtblock_t fblock;
+  stmtblock_t loop_pre_block;
+  gfc_ref *ref;
   gfc_ss *rss;
   gfc_ss *lss;
   gfc_array_info *linfo;
@@ -11132,6 +11136,45 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo 
*loop,
 array1, build_int_cst (TREE_TYPE (array1), 0));
   cond_null= gfc_evaluate_now (cond_null, &fblock);
 
+  /* If the data is null, set the descriptor bounds and offset. This suppresses
+ the maybe used uninitialized warning and forces the use of malloc because
+ the size is zero in all dimensions. Note that this block is only executed
+ if the lhs is unallocated and is only applied once in any namespace.
+ Component references are not subject to the warnings.  */
+  for (ref = expr1->ref; ref; ref = ref->next)
+if (ref->type == REF_COMPONENT)
+  break;
+
+  if (!expr1->symtree->n.sym->allocated_in_scope && !ref)
+{
+  gfc_start_block (&loop_pre_block);
+  for (n = 0; n < expr1->rank; n++)
+   {
+ gfc_conv_descriptor_lbound_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_one_node);
+ gfc_conv_descriptor_ubound_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_zero_node);
+ gfc_conv_descriptor_stride_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_zero_node);
+   }
+
+  tmp = gfc_conv_descriptor_offset (desc);
+  gfc_add_modify (&loop_pre_block, tmp, gfc_index_zero_node);
+
+  tmp = fold_build2_loc (input_location, EQ_EXPR,
+logical_type_node, array1,
+build_int_cst (TREE_TYPE (array1), 0));
+  tmp = build3_v (COND_EXPR, tmp,
+ gfc_finish_block (&loop_pre_block),
+ build_empty_stmt (input_location));
+  gfc_prepend_expr_to_block (&loop->pre, tmp);
+
+  expr1->symtree->n.sym->allocated_in_scope = 1;
+}
+
   tmp = build3_v (COND_EXPR, cond_null,
  build1_v (GOTO_EXPR, jump_label1),
  build_empty_stmt (input_location));
diff --git a/gcc/testsuite/gfortran.dg/pr108889.f90 
b/gcc/testsuite/gfortran.dg/pr108889.f90
new file mode 100644
index ..7fd4e3882a48
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr108889.f90
@@ -0,0 +1,43 @@
+! { dg-do compile }
+! { dg-options "-Wall -fdump-tree-original" }
+!
+!

[gcc r14-10561] libgomp: Remove bogus warnings from privatized-ref-2.f90.

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:2405d29086d5045821b1a7260b589fbae1e6f05a

commit r14-10561-g2405d29086d5045821b1a7260b589fbae1e6f05a
Author: Paul Thomas 
Date:   Fri Jul 19 16:58:33 2024 +0100

libgomp: Remove bogus warnings from privatized-ref-2.f90.

2024-07-19  Paul Thomas  

libgomp/ChangeLog

* testsuite/libgomp.oacc-fortran/privatized-ref-2.f90: Cut
dg-note about 'a' and remove bogus warnings about its array
descriptor components being used uninitialized.

(cherry picked from commit 8d6994f33a98a168151a57a3d21395b19196cd9d)

Diff:
---
 libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90 | 6 --
 1 file changed, 6 deletions(-)

diff --git a/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90 
b/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
index 498ef70b63a4..8cf79a10e8d2 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
+++ b/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
@@ -29,16 +29,10 @@ program main
   implicit none (type, external)
   integer :: j
   integer, allocatable :: A(:)
-  ! { dg-note {'a' declared here} {} { target *-*-* } .-1 }
   character(len=:), allocatable :: my_str
   character(len=15), allocatable :: my_str15
 
   A = [(3*j, j=1, 10)]
-  ! { dg-bogus {'a\.offset' is used uninitialized} {PR77504 etc.} { xfail 
*-*-* } .-1 }
-  ! { dg-bogus {'a\.dim\[0\]\.lbound' is used uninitialized} {PR77504 etc.} { 
xfail *-*-* } .-2 }
-  ! { dg-bogus {'a\.dim\[0\]\.ubound' is used uninitialized} {PR77504 etc.} { 
xfail *-*-* } .-3 }
-  ! { dg-bogus {'a\.dim\[0\]\.lbound' may be used uninitialized} {PR77504 
etc.} { xfail { ! __OPTIMIZE__ } } .-4 }
-  ! { dg-bogus {'a\.dim\[0\]\.ubound' may be used uninitialized} {PR77504 
etc.} { xfail { ! __OPTIMIZE__ } } .-5 }
   call foo (A, size(A))
   call bar (A)
   my_str = "1234567890"

[gcc r13-8959] Fortran: Suppress bogus used uninitialized warnings [PR108889].

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:7195144e39e404ec712ca5401f2328c14d5020eb

commit r13-8959-g7195144e39e404ec712ca5401f2328c14d5020eb
Author: Paul Thomas 
Date:   Thu Jul 18 08:51:35 2024 +0100

Fortran: Suppress bogus used uninitialized warnings [PR108889].

2024-07-18  Paul Thomas  

gcc/fortran
PR fortran/108889
* gfortran.h: Add bit field 'allocated_in_scope' to gfc_symbol.
* trans-array.cc (gfc_array_allocate): Set 'allocated_in_scope'
after allocation if not a component reference.
(gfc_alloc_allocatable_for_assignment): If 'allocated_in_scope'
not set, not a component ref and not allocated, set the array
bounds and offset to give zero length in all dimensions. Then
set allocated_in_scope.

gcc/testsuite/
PR fortran/108889
* gfortran.dg/pr108889.f90: New test.

(cherry picked from commit c3aa339ea50f050caf7ed2e497f5499ec2d7b9cc)

Diff:
---
 gcc/fortran/gfortran.h |  4 
 gcc/fortran/trans-array.cc | 43 ++
 gcc/testsuite/gfortran.dg/pr108889.f90 | 43 ++
 3 files changed, 90 insertions(+)

diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index c1430f7dfeca..c710945f1013 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -1927,6 +1927,10 @@ typedef struct gfc_symbol
   /* Set if this should be passed by value, but is not a VALUE argument
  according to the Fortran standard.  */
   unsigned pass_as_value:1;
+  /* Set if an allocatable array variable has been allocated in the current
+ scope. Used in the suppression of uninitialized warnings in reallocation
+ on assignment.  */
+  unsigned allocated_in_scope:1;
 
   int refs;
   struct gfc_namespace *ns;/* namespace containing this symbol */
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 4d42cf1131aa..eecb342f32af 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -6341,6 +6341,8 @@ gfc_array_allocate (gfc_se * se, gfc_expr * expr, tree 
status, tree errmsg,
   else
   gfc_add_expr_to_block (&se->pre, set_descriptor);
 
+  expr->symtree->n.sym->allocated_in_scope = 1;
+
   return true;
 }
 
@@ -10645,6 +10647,8 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo 
*loop,
   stmtblock_t realloc_block;
   stmtblock_t alloc_block;
   stmtblock_t fblock;
+  stmtblock_t loop_pre_block;
+  gfc_ref *ref;
   gfc_ss *rss;
   gfc_ss *lss;
   gfc_array_info *linfo;
@@ -10845,6 +10849,45 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo 
*loop,
 array1, build_int_cst (TREE_TYPE (array1), 0));
   cond_null= gfc_evaluate_now (cond_null, &fblock);
 
+  /* If the data is null, set the descriptor bounds and offset. This suppresses
+ the maybe used uninitialized warning and forces the use of malloc because
+ the size is zero in all dimensions. Note that this block is only executed
+ if the lhs is unallocated and is only applied once in any namespace.
+ Component references are not subject to the warnings.  */
+  for (ref = expr1->ref; ref; ref = ref->next)
+if (ref->type == REF_COMPONENT)
+  break;
+
+  if (!expr1->symtree->n.sym->allocated_in_scope && !ref)
+{
+  gfc_start_block (&loop_pre_block);
+  for (n = 0; n < expr1->rank; n++)
+   {
+ gfc_conv_descriptor_lbound_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_one_node);
+ gfc_conv_descriptor_ubound_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_zero_node);
+ gfc_conv_descriptor_stride_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_zero_node);
+   }
+
+  tmp = gfc_conv_descriptor_offset (desc);
+  gfc_add_modify (&loop_pre_block, tmp, gfc_index_zero_node);
+
+  tmp = fold_build2_loc (input_location, EQ_EXPR,
+logical_type_node, array1,
+build_int_cst (TREE_TYPE (array1), 0));
+  tmp = build3_v (COND_EXPR, tmp,
+ gfc_finish_block (&loop_pre_block),
+ build_empty_stmt (input_location));
+  gfc_prepend_expr_to_block (&loop->pre, tmp);
+
+  expr1->symtree->n.sym->allocated_in_scope = 1;
+}
+
   tmp = build3_v (COND_EXPR, cond_null,
  build1_v (GOTO_EXPR, jump_label1),
  build_empty_stmt (input_location));
diff --git a/gcc/testsuite/gfortran.dg/pr108889.f90 
b/gcc/testsuite/gfortran.dg/pr108889.f90
new file mode 100644
index ..7fd4e3882a48
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr108889.f90
@@ -0,0 +1,43 @@
+! { dg-do compile }
+! { dg-options "-Wall -

[gcc r13-8960] libgomp: Remove bogus warnings from privatized-ref-2.f90.

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:bf0673ef66a6dd8a000c6fb882a206c1cef639c7

commit r13-8960-gbf0673ef66a6dd8a000c6fb882a206c1cef639c7
Author: Paul Thomas 
Date:   Fri Jul 19 16:58:33 2024 +0100

libgomp: Remove bogus warnings from privatized-ref-2.f90.

2024-07-19  Paul Thomas  

libgomp/ChangeLog

* testsuite/libgomp.oacc-fortran/privatized-ref-2.f90: Cut
dg-note about 'a' and remove bogus warnings about its array
descriptor components being used uninitialized.

(cherry picked from commit 8d6994f33a98a168151a57a3d21395b19196cd9d)

Diff:
---
 libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90 | 6 --
 1 file changed, 6 deletions(-)

diff --git a/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90 
b/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
index 498ef70b63a4..8cf79a10e8d2 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
+++ b/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
@@ -29,16 +29,10 @@ program main
   implicit none (type, external)
   integer :: j
   integer, allocatable :: A(:)
-  ! { dg-note {'a' declared here} {} { target *-*-* } .-1 }
   character(len=:), allocatable :: my_str
   character(len=15), allocatable :: my_str15
 
   A = [(3*j, j=1, 10)]
-  ! { dg-bogus {'a\.offset' is used uninitialized} {PR77504 etc.} { xfail 
*-*-* } .-1 }
-  ! { dg-bogus {'a\.dim\[0\]\.lbound' is used uninitialized} {PR77504 etc.} { 
xfail *-*-* } .-2 }
-  ! { dg-bogus {'a\.dim\[0\]\.ubound' is used uninitialized} {PR77504 etc.} { 
xfail *-*-* } .-3 }
-  ! { dg-bogus {'a\.dim\[0\]\.lbound' may be used uninitialized} {PR77504 
etc.} { xfail { ! __OPTIMIZE__ } } .-4 }
-  ! { dg-bogus {'a\.dim\[0\]\.ubound' may be used uninitialized} {PR77504 
etc.} { xfail { ! __OPTIMIZE__ } } .-5 }
   call foo (A, size(A))
   call bar (A)
   my_str = "1234567890"

[gcc r12-10657] Fortran: Suppress bogus used uninitialized warnings [PR108889].

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:0e945f6e8849ae4722ea7ac70d713f7b35d3fade

commit r12-10657-g0e945f6e8849ae4722ea7ac70d713f7b35d3fade
Author: Paul Thomas 
Date:   Thu Jul 18 08:51:35 2024 +0100

Fortran: Suppress bogus used uninitialized warnings [PR108889].

2024-07-18  Paul Thomas  

gcc/fortran
PR fortran/108889
* gfortran.h: Add bit field 'allocated_in_scope' to gfc_symbol.
* trans-array.cc (gfc_array_allocate): Set 'allocated_in_scope'
after allocation if not a component reference.
(gfc_alloc_allocatable_for_assignment): If 'allocated_in_scope'
not set, not a component ref and not allocated, set the array
bounds and offset to give zero length in all dimensions. Then
set allocated_in_scope.

gcc/testsuite/
PR fortran/108889
* gfortran.dg/pr108889.f90: New test.

(cherry picked from commit c3aa339ea50f050caf7ed2e497f5499ec2d7b9cc)

Diff:
---
 gcc/fortran/gfortran.h |  4 
 gcc/fortran/trans-array.cc | 43 ++
 gcc/testsuite/gfortran.dg/pr108889.f90 | 43 ++
 3 files changed, 90 insertions(+)

diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index 0b0a8fe71180..7162f39f39c4 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -1887,6 +1887,10 @@ typedef struct gfc_symbol
   /* Set if this should be passed by value, but is not a VALUE argument
  according to the Fortran standard.  */
   unsigned pass_as_value:1;
+  /* Set if an allocatable array variable has been allocated in the current
+ scope. Used in the suppression of uninitialized warnings in reallocation
+ on assignment.  */
+  unsigned allocated_in_scope:1;
 
   int refs;
   struct gfc_namespace *ns;/* namespace containing this symbol */
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 85c641b55c52..59668177bbf7 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -6285,6 +6285,8 @@ gfc_array_allocate (gfc_se * se, gfc_expr * expr, tree 
status, tree errmsg,
   else
   gfc_add_expr_to_block (&se->pre, set_descriptor);
 
+  expr->symtree->n.sym->allocated_in_scope = 1;
+
   return true;
 }
 
@@ -10509,6 +10511,8 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo 
*loop,
   stmtblock_t realloc_block;
   stmtblock_t alloc_block;
   stmtblock_t fblock;
+  stmtblock_t loop_pre_block;
+  gfc_ref *ref;
   gfc_ss *rss;
   gfc_ss *lss;
   gfc_array_info *linfo;
@@ -10717,6 +10721,45 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo 
*loop,
   else
 cond_null= gfc_evaluate_now (cond_null, &fblock);
 
+  /* If the data is null, set the descriptor bounds and offset. This suppresses
+ the maybe used uninitialized warning and forces the use of malloc because
+ the size is zero in all dimensions. Note that this block is only executed
+ if the lhs is unallocated and is only applied once in any namespace.
+ Component references are not subject to the warnings.  */
+  for (ref = expr1->ref; ref; ref = ref->next)
+if (ref->type == REF_COMPONENT)
+  break;
+
+  if (!expr1->symtree->n.sym->allocated_in_scope && !ref)
+{
+  gfc_start_block (&loop_pre_block);
+  for (n = 0; n < expr1->rank; n++)
+   {
+ gfc_conv_descriptor_lbound_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_one_node);
+ gfc_conv_descriptor_ubound_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_zero_node);
+ gfc_conv_descriptor_stride_set (&loop_pre_block, desc,
+ gfc_rank_cst[n],
+ gfc_index_zero_node);
+   }
+
+  tmp = gfc_conv_descriptor_offset (desc);
+  gfc_add_modify (&loop_pre_block, tmp, gfc_index_zero_node);
+
+  tmp = fold_build2_loc (input_location, EQ_EXPR,
+logical_type_node, array1,
+build_int_cst (TREE_TYPE (array1), 0));
+  tmp = build3_v (COND_EXPR, tmp,
+ gfc_finish_block (&loop_pre_block),
+ build_empty_stmt (input_location));
+  gfc_prepend_expr_to_block (&loop->pre, tmp);
+
+  expr1->symtree->n.sym->allocated_in_scope = 1;
+}
+
   tmp = build3_v (COND_EXPR, cond_null,
  build1_v (GOTO_EXPR, jump_label1),
  build_empty_stmt (input_location));
diff --git a/gcc/testsuite/gfortran.dg/pr108889.f90 
b/gcc/testsuite/gfortran.dg/pr108889.f90
new file mode 100644
index ..7fd4e3882a48
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr108889.f90
@@ -0,0 +1,43 @@
+! { dg-do compile }
+! { dg-options "-Wall -fdump-tree-original" }
+!
+! Contributed by Tobias Burnus  
+!

[gcc r12-10658] libgomp: Remove bogus warnings from privatized-ref-2.f90.

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:3f356a88d6c15d0ea93a5191c23b668744254f72

commit r12-10658-g3f356a88d6c15d0ea93a5191c23b668744254f72
Author: Paul Thomas 
Date:   Fri Jul 19 16:58:33 2024 +0100

libgomp: Remove bogus warnings from privatized-ref-2.f90.

2024-07-19  Paul Thomas  

libgomp/ChangeLog

* testsuite/libgomp.oacc-fortran/privatized-ref-2.f90: Cut
dg-note about 'a' and remove bogus warnings about its array
descriptor components being used uninitialized.

(cherry picked from commit 8d6994f33a98a168151a57a3d21395b19196cd9d)

Diff:
---
 libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90 | 6 --
 1 file changed, 6 deletions(-)

diff --git a/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90 
b/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
index 498ef70b63a4..8cf79a10e8d2 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
+++ b/libgomp/testsuite/libgomp.oacc-fortran/privatized-ref-2.f90
@@ -29,16 +29,10 @@ program main
   implicit none (type, external)
   integer :: j
   integer, allocatable :: A(:)
-  ! { dg-note {'a' declared here} {} { target *-*-* } .-1 }
   character(len=:), allocatable :: my_str
   character(len=15), allocatable :: my_str15
 
   A = [(3*j, j=1, 10)]
-  ! { dg-bogus {'a\.offset' is used uninitialized} {PR77504 etc.} { xfail 
*-*-* } .-1 }
-  ! { dg-bogus {'a\.dim\[0\]\.lbound' is used uninitialized} {PR77504 etc.} { 
xfail *-*-* } .-2 }
-  ! { dg-bogus {'a\.dim\[0\]\.ubound' is used uninitialized} {PR77504 etc.} { 
xfail *-*-* } .-3 }
-  ! { dg-bogus {'a\.dim\[0\]\.lbound' may be used uninitialized} {PR77504 
etc.} { xfail { ! __OPTIMIZE__ } } .-4 }
-  ! { dg-bogus {'a\.dim\[0\]\.ubound' may be used uninitialized} {PR77504 
etc.} { xfail { ! __OPTIMIZE__ } } .-5 }
   call foo (A, size(A))
   call bar (A)
   my_str = "1234567890"

[gcc r15-2729] Fix handling of const or volatile void pointers in CodeView

[Mark Harmstone via Gcc-cvs]

https://gcc.gnu.org/g:b0e2ccef0b3c469d5d242766328a24a94990f83b

commit r15-2729-gb0e2ccef0b3c469d5d242766328a24a94990f83b
Author: Mark Harmstone 
Date:   Sun Aug 4 23:26:53 2024 +0100

Fix handling of const or volatile void pointers in CodeView

DWARF represents voids in DW_TAG_const_type and DW_TAG_volatile_type
DIEs by the absence of a DW_AT_type attribute, which we weren't handling
correctly.

gcc/
* dwarf2codeview.cc (get_type_num_const_type): Handle missing
DW_AT_type attribute.
(get_type_num_volatile_type): Likewise.

Diff:
---
 gcc/dwarf2codeview.cc | 36 
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/gcc/dwarf2codeview.cc b/gcc/dwarf2codeview.cc
index 470cbae71103..f7107021bc71 100644
--- a/gcc/dwarf2codeview.cc
+++ b/gcc/dwarf2codeview.cc
@@ -2344,23 +2344,26 @@ get_type_num_const_type (dw_die_ref type, bool 
in_struct)
   bool is_volatile = false;
 
   base_type = get_AT_ref (type, DW_AT_type);
-  if (!base_type)
-return 0;
 
   /* Handle case when this is a const volatile type - we only need one
  LF_MODIFIER for this.  */
-  if (dw_get_die_tag (base_type) == DW_TAG_volatile_type)
+  if (base_type && dw_get_die_tag (base_type) == DW_TAG_volatile_type)
 {
   is_volatile = true;
 
   base_type = get_AT_ref (base_type, DW_AT_type);
-  if (!base_type)
-   return 0;
 }
 
-  base_type_num = get_type_num (base_type, in_struct, false);
-  if (base_type_num == 0)
-return 0;
+  if (!base_type)
+{
+  base_type_num = T_VOID;
+}
+  else
+{
+  base_type_num = get_type_num (base_type, in_struct, false);
+  if (base_type_num == 0)
+   return 0;
+}
 
   ct = (codeview_custom_type *) xmalloc (sizeof (codeview_custom_type));
 
@@ -2383,13 +2386,22 @@ get_type_num_const_type (dw_die_ref type, bool 
in_struct)
 static uint32_t
 get_type_num_volatile_type (dw_die_ref type, bool in_struct)
 {
+  dw_die_ref base_type;
   uint32_t base_type_num;
   codeview_custom_type *ct;
 
-  base_type_num = get_type_num (get_AT_ref (type, DW_AT_type), in_struct,
-   false);
-  if (base_type_num == 0)
-return 0;
+  base_type = get_AT_ref (type, DW_AT_type);
+
+  if (base_type)
+{
+  base_type_num = get_type_num (base_type, in_struct, false);
+  if (base_type_num == 0)
+   return 0;
+}
+  else
+{
+  base_type_num = T_VOID;
+}
 
   ct = (codeview_custom_type *) xmalloc (sizeof (codeview_custom_type));

[gcc r15-2730] c++, coroutines: Simplify separation of the user function body and ramp.

[Iain D Sandoe via Gcc-cvs]

https://gcc.gnu.org/g:86512292270860bbe1dd33cef1ebe041d597462c

commit r15-2730-g86512292270860bbe1dd33cef1ebe041d597462c
Author: Iain Sandoe 
Date:   Wed Jul 31 23:05:49 2024 +0100

c++, coroutines: Simplify separation of the user function body and ramp.

We need to separate the original user-authored function body from the
definition of the ramp function (which is what is called instead).
The function body tree is either in DECL_SAVED_TREE or the first operand
of current_eh_spec_block (for functions with an EH spec).
This version simplifies the process by extracting the second case directly
instead of inspecting the DECL_SAVED_TREE trees to discover it.

gcc/cp/ChangeLog:

* coroutines.cc (split_coroutine_body_from_ramp): New.
(morph_fn_to_coro): Use split_coroutine_body_from_ramp().
* cp-tree.h (use_eh_spec_block): New.
* decl.cc (use_eh_spec_block): Make non-static.

Signed-off-by: Iain Sandoe 

Diff:
---
 gcc/cp/coroutines.cc | 90 ++--
 gcc/cp/cp-tree.h |  1 +
 gcc/cp/decl.cc   |  2 +-
 3 files changed, 47 insertions(+), 46 deletions(-)

diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc
index 742f0e505976..145ec4b1d16b 100644
--- a/gcc/cp/coroutines.cc
+++ b/gcc/cp/coroutines.cc
@@ -4547,6 +4547,43 @@ coro_rewrite_function_body (location_t fn_start, tree 
fnbody, tree orig,
   return update_body;
 }
 
+/* Extract the body of the function we are going to outline, leaving
+   to original function decl ready to build the ramp.  */
+
+static tree
+split_coroutine_body_from_ramp (tree fndecl)
+{
+  tree body;
+  /* Once we've tied off the original user-authored body in fn_body.
+ Start the replacement synthesized ramp body.  */
+
+  if (use_eh_spec_block (fndecl))
+{
+  body = pop_stmt_list (TREE_OPERAND (current_eh_spec_block, 0));
+  TREE_OPERAND (current_eh_spec_block, 0) = push_stmt_list ();
+}
+  else
+{
+  body = pop_stmt_list (DECL_SAVED_TREE (fndecl));
+  DECL_SAVED_TREE (fndecl) = push_stmt_list ();
+}
+
+  /* We can't validly get here with an empty statement list, since there's no
+ way for the FE to decide it's a coroutine in the absence of any code.  */
+  gcc_checking_assert (body != NULL_TREE);
+
+  /* If we have an empty or erroneous function body, do not try to transform it
+ since that would potentially wrap errors.  */
+  tree body_start = expr_first (body);
+  if (body_start == NULL_TREE || body_start == error_mark_node)
+{
+  /* Restore the original state.  */
+  add_stmt (body);
+  return NULL_TREE;
+}
+  return body;
+}
+
 /* Here we:
a) Check that the function and promise type are valid for a
   coroutine.
@@ -4593,57 +4630,22 @@ morph_fn_to_coro (tree orig, tree *resumer, tree 
*destroyer)
   /* Discard the body, we can't process it further.  */
   pop_stmt_list (DECL_SAVED_TREE (orig));
   DECL_SAVED_TREE (orig) = push_stmt_list ();
+  /* Match the expected nesting when an eh block is in use.  */
+  if (use_eh_spec_block (orig))
+   current_eh_spec_block = begin_eh_spec_block ();
   return false;
 }
 
-  /* We can't validly get here with an empty statement list, since there's no
- way for the FE to decide it's a coroutine in the absence of any code.  */
-  tree fnbody = pop_stmt_list (DECL_SAVED_TREE (orig));
-  gcc_checking_assert (fnbody != NULL_TREE);
-
   /* We don't have the locus of the opening brace - it's filled in later (and
  there doesn't really seem to be any easy way to get at it).
  The closing brace is assumed to be input_location.  */
   location_t fn_start = DECL_SOURCE_LOCATION (orig);
-  gcc_rich_location fn_start_loc (fn_start);
-
-  /* Initial processing of the function-body.
- If we have no expressions or just an error then punt.  */
-  tree body_start = expr_first (fnbody);
-  if (body_start == NULL_TREE || body_start == error_mark_node)
-{
-  DECL_SAVED_TREE (orig) = push_stmt_list ();
-  append_to_statement_list (fnbody, &DECL_SAVED_TREE (orig));
-  /* Suppress warnings about the missing return value.  */
-  suppress_warning (orig, OPT_Wreturn_type);
-  return false;
-}
-
-  /* So, we've tied off the original user-authored body in fn_body.
-
- Start the replacement synthesized ramp body as newbody.
- If we encounter a fatal error we might return a now-empty body.
-
- Note, the returned ramp body is not 'popped', to be compatible with
- the way that decl.cc handles regular functions, the scope pop is done
- in the caller.  */
 
-  tree newbody = push_stmt_list ();
-  DECL_SAVED_TREE (orig) = newbody;
-
-  /* If our original body is noexcept, then that's what we apply to our
- generated ramp, transfer any MUST_NOT_THOW_EXPR to that.  */
-  bool is_noexcept = TREE_CODE (body_start) == MUST_NOT_THROW_EXPR;
-  if (is_noexcept)
-{

[gcc/devel/fortran_unsigned] Implement dshift[lr], ibclr, ibset and ibits.

[Thomas Kﾃｶnig via Gcc-cvs]

https://gcc.gnu.org/g:ef35d21d9218259706b1ab37766ead2ad0f3e231

commit ef35d21d9218259706b1ab37766ead2ad0f3e231
Author: Thomas Koenig 
Date:   Mon Aug 5 23:02:21 2024 +0200

Implement dshift[lr], ibclr, ibset and ibits.

Diff:
---
 gcc/fortran/check.cc | 88 +++-
 gcc/fortran/gfortran.h   |  2 +-
 gcc/fortran/iresolve.cc  | 30 +++
 gcc/fortran/simplify.cc  | 72 ++
 gcc/testsuite/gfortran.dg/unsigned_9.f90 | 32 
 5 files changed, 170 insertions(+), 54 deletions(-)

diff --git a/gcc/fortran/check.cc b/gcc/fortran/check.cc
index 1a8f601ce838..54a84ae40756 100644
--- a/gcc/fortran/check.cc
+++ b/gcc/fortran/check.cc
@@ -913,14 +913,20 @@ static bool
 less_than_bitsizekind (const char *arg, gfc_expr *expr, int k)
 {
   int i, val;
+  int bit_size;
 
   if (expr->expr_type != EXPR_CONSTANT)
 return true;
 
-  i = gfc_validate_kind (BT_INTEGER, k, false);
+  i = gfc_validate_kind (expr->ts.type, k, false);
   gfc_extract_int (expr, &val);
 
-  if (val > gfc_integer_kinds[i].bit_size)
+  if (expr->ts.type == BT_INTEGER)
+bit_size = gfc_integer_kinds[i].bit_size;
+  else
+bit_size = gfc_unsigned_kinds[i].bit_size;
+
+  if (val > bit_size)
 {
   gfc_error ("%qs at %L must be less than or equal to the BIT_SIZE of "
 "INTEGER(KIND=%d)", arg, &expr->where, k);
@@ -939,14 +945,21 @@ less_than_bitsize2 (const char *arg1, gfc_expr *expr1, 
const char *arg2,
   gfc_expr *expr2, const char *arg3, gfc_expr *expr3)
 {
   int i2, i3;
+  int k, bit_size;
 
   if (expr2->expr_type == EXPR_CONSTANT && expr3->expr_type == EXPR_CONSTANT)
 {
   gfc_extract_int (expr2, &i2);
   gfc_extract_int (expr3, &i3);
   i2 += i3;
-  i3 = gfc_validate_kind (BT_INTEGER, expr1->ts.kind, false);
-  if (i2 > gfc_integer_kinds[i3].bit_size)
+  k = gfc_validate_kind (expr1->ts.type, expr1->ts.kind, false);
+
+  if (expr1->ts.type == BT_INTEGER)
+   bit_size = gfc_integer_kinds[k].bit_size;
+  else
+   bit_size = gfc_unsigned_kinds[k].bit_size;
+
+  if (i2 > bit_size)
{
  gfc_error ("%<%s + %s%> at %L must be less than or equal "
 "to BIT_SIZE(%qs)",
@@ -2822,33 +2835,54 @@ gfc_check_dshift (gfc_expr *i, gfc_expr *j, gfc_expr 
*shift)
   if (!boz_args_check (i, j))
 return false;
 
-  /* If i is BOZ and j is integer, convert i to type of j.  If j is not
- an integer, clear the BOZ; otherwise, check that i is an integer.  */
   if (i->ts.type == BT_BOZ)
 {
-  if (j->ts.type != BT_INTEGER)
-reset_boz (i);
-  else if (!gfc_boz2int (i, j->ts.kind))
-   return false;
+  if (j->ts.type == BT_INTEGER)
+   {
+ if (!gfc_boz2int (i, j->ts.kind))
+   return false;
+   }
+  else if (flag_unsigned && j->ts.type == BT_UNSIGNED)
+   {
+ if (!gfc_boz2uint (i, j->ts.kind))
+   return false;
+   }
+  else
+   reset_boz (i);
 }
-  else if (!type_check (i, 0, BT_INTEGER))
+
+  if (j->ts.type == BT_BOZ)
 {
-  if (j->ts.type == BT_BOZ)
+  if (i->ts.type == BT_INTEGER)
+   {
+ if (!gfc_boz2int (j, i->ts.kind))
+   return false;
+   }
+  else if (flag_unsigned && i->ts.type == BT_UNSIGNED)
+   {
+ if (!gfc_boz2uint (j, i->ts.kind))
+   return false;
+   }
+  else
reset_boz (j);
-  return false;
 }
 
-  /* If j is BOZ and i is integer, convert j to type of i.  If i is not
- an integer, clear the BOZ; otherwise, check that i is an integer.  */
-  if (j->ts.type == BT_BOZ)
+  if (flag_unsigned)
 {
-  if (i->ts.type != BT_INTEGER)
-reset_boz (j);
-  else if (!gfc_boz2int (j, i->ts.kind))
+  if (!type_check2 (i, 0, BT_INTEGER, BT_UNSIGNED))
+   return false;
+
+  if (!type_check2 (j, 1, BT_INTEGER, BT_UNSIGNED))
+   return false;
+}
+  else
+{
+  if (!type_check (i, 0, BT_INTEGER))
+   return false;
+
+  if (!type_check (j, 1, BT_INTEGER))
return false;
 }
-  else if (!type_check (j, 1, BT_INTEGER))
-return false;
 
   if (!same_type_check (i, 0, j, 1))
 return false;
@@ -3231,8 +3265,16 @@ gfc_check_iand_ieor_ior (gfc_expr *i, gfc_expr *j)
 bool
 gfc_check_ibits (gfc_expr *i, gfc_expr *pos, gfc_expr *len)
 {
-  if (!type_check (i, 0, BT_INTEGER))
-return false;
+  if (flag_unsigned)
+{
+  if (!type_check2 (i, 0, BT_INTEGER, BT_UNSIGNED))
+   return false;
+}
+  else
+{
+  if (!type_check (i, 0, BT_INTEGER))
+   return false;
+}
 
   if (!type_check (pos, 1, BT_INTEGER))
 return false;
diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index 5f8dd1300a50..16395a35b030 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -3474,7 +3474,7 @@ arith gfc_check_integer_range (mpz_t p, int kind)

[gcc r15-2731] RISC-V: Add deprecation warning to LP64E abi

[Patrick O'Neill via Gcc-cvs]

https://gcc.gnu.org/g:51db1f307ba395ee322de5adadf56c316e82ae00

commit r15-2731-g51db1f307ba395ee322de5adadf56c316e82ae00
Author: Patrick O'Neill 
Date:   Tue Jul 30 17:32:09 2024 -0700

RISC-V: Add deprecation warning to LP64E abi

gcc/ChangeLog:

PR target/116152
* config/riscv/riscv.cc (riscv_option_override): Add deprecation
warning.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-9.c: Add check for warning.

Signed-off-by: Patrick O'Neill 

Diff:
---
 gcc/config/riscv/riscv.cc | 7 +++
 gcc/testsuite/gcc.target/riscv/predef-9.c | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b19d56149e75..b005af62e61f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9823,6 +9823,13 @@ riscv_option_override (void)
 error ("ILP32E ABI does not support the %qc extension",
   UNITS_PER_FP_REG > 8 ? 'Q' : 'D');
 
+  if (riscv_abi == ABI_LP64E)
+{
+  if (warning (OPT_Wdeprecated, "LP64E ABI is marked for deprecation in 
GCC"))
+   inform (UNKNOWN_LOCATION, "If you need LP64E please notify the GCC "
+   "project via https://gcc.gnu.org/PR116152";);
+}
+
   /* Zfinx require abi ilp32, ilp32e, lp64 or lp64e.  */
   if (TARGET_ZFINX
   && riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64
diff --git a/gcc/testsuite/gcc.target/riscv/predef-9.c 
b/gcc/testsuite/gcc.target/riscv/predef-9.c
index cc3abc9a741a..0d9488529ea5 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-9.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-9.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow" } */
+/* { dg-warning "LP64E ABI is marked for deprecation in GCC" "" { target *-*-* 
} 0 } */
+/* { dg-note "If you need LP64E please notify the GCC project via 
https://gcc.gnu.org/PR116152"; "" { target *-*-* } 0 } */
 
 int main () {
 #if !defined(__riscv)

[gcc r15-2732] compiler: panic arguments are empty interface type

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:ecb6153e3b9895c6e058646262c7c9e9c9c24a3c

commit r15-2732-gecb6153e3b9895c6e058646262c7c9e9c9c24a3c
Author: Ian Lance Taylor 
Date:   Mon Aug 5 13:01:32 2024 -0700

compiler: panic arguments are empty interface type

After CL 536643 passing NULL as the expected type permitted an untyped
constant expression to remain untyped. Change to passing the empty
interface type.

The panic and print/println functions are the only builtin functions
that turn an untyped constant expression into a regular function call,
and we already handled print/println specially.

The test case is https://go.dev/cl/603096.

Fixes golang/go#68734

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/603215

Diff:
---
 gcc/go/gofrontend/MERGE  | 2 +-
 gcc/go/gofrontend/expressions.cc | 6 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE
index 9a4b402573a6..e13dc5f58a3d 100644
--- a/gcc/go/gofrontend/MERGE
+++ b/gcc/go/gofrontend/MERGE
@@ -1,4 +1,4 @@
-60f985a7852632834936b4b859aa75d9df88f038
+5f6fae5ff33e996243acd098c71904695c414c53
 
 The first line of this file holds the git revision number of the last
 merge done from the gofrontend repository.
diff --git a/gcc/go/gofrontend/expressions.cc b/gcc/go/gofrontend/expressions.cc
index 238d5a56ca2a..2b0e40fc6f81 100644
--- a/gcc/go/gofrontend/expressions.cc
+++ b/gcc/go/gofrontend/expressions.cc
@@ -11137,6 +11137,12 @@ Builtin_call_expression::do_determine_type(Gogo* gogo,
   is_print = false;
   break;
 
+case BUILTIN_PANIC:
+  arg_type =
+   Type::make_empty_interface_type(Linemap::predeclared_location());
+  is_print = false;
+  break;
+
 case BUILTIN_PRINT:
 case BUILTIN_PRINTLN:
   // Do not force a large integer constant to "int".

[gcc r14-10562] compiler: panic arguments are empty interface type

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:de738988ff62b76e433f2fce570fcd8ab4b16c07

commit r14-10562-gde738988ff62b76e433f2fce570fcd8ab4b16c07
Author: Ian Lance Taylor 
Date:   Mon Aug 5 16:07:12 2024 -0700

compiler: panic arguments are empty interface type

After CL 536643 passing NULL as the expected type permitted an untyped
constant expression to remain untyped. Change to passing the empty
interface type.

The panic and print/println functions are the only builtin functions
that turn an untyped constant expression into a regular function call,
and we already handled print/println specially.

The test case is https://go.dev/cl/603096.

Fixes golang/go#68734

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/603215

Diff:
---
 gcc/go/gofrontend/expressions.cc | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/gcc/go/gofrontend/expressions.cc b/gcc/go/gofrontend/expressions.cc
index 238d5a56ca2a..2b0e40fc6f81 100644
--- a/gcc/go/gofrontend/expressions.cc
+++ b/gcc/go/gofrontend/expressions.cc
@@ -11137,6 +11137,12 @@ Builtin_call_expression::do_determine_type(Gogo* gogo,
   is_print = false;
   break;
 
+case BUILTIN_PANIC:
+  arg_type =
+   Type::make_empty_interface_type(Linemap::predeclared_location());
+  is_print = false;
+  break;
+
 case BUILTIN_PRINT:
 case BUILTIN_PRINTLN:
   // Do not force a large integer constant to "int".

[gcc(refs/users/meissner/heads/work175-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4eda1be11b75c2cbaed2cdb795e9552cb219103c

commit 4eda1be11b75c2cbaed2cdb795e9552cb219103c
Author: Michael Meissner 
Date:   Thu Aug 1 15:51:21 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-08-01  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..94889013fa70
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,6 @@
+ Branch work175-bugs, baseline 
+
+2024-08-01   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 1573af834b31..90da570993ff 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work175 branch
+work175-bugs branch

[gcc/meissner/heads/work175-bugs] (6 commits) Merge commit 'refs/users/meissner/heads/work175-bugs' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work175-bugs' was updated to point to:

 819d8189d2f8... Merge commit 'refs/users/meissner/heads/work175-bugs' of gi

It previously pointed to:

 63e8b76ddfe7... Merge commit 'refs/users/meissner/heads/work175-bugs' of gi

Diff:

Summary of changes (added commits):
---

  819d818... Merge commit 'refs/users/meissner/heads/work175-bugs' of gi
  4eda1be... Add ChangeLog.bugs and update REVISION.
  6ef0fb1... Update ChangeLog.* (*)
  e198be0... Add -mcpu=future tuning support. (*)
  8553a0e... Add support for -mcpu=future (*)
  71db6b9... Revert changes (*)

(*) This commit already exists in another branch.
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[gcc(refs/users/meissner/heads/work175-bugs)] Merge commit 'refs/users/meissner/heads/work175-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:819d8189d2f8dcb922e0c25d7d1081046ad7598c

commit 819d8189d2f8dcb922e0c25d7d1081046ad7598c
Merge: 4eda1be11b75 63e8b76ddfe7
Author: Michael Meissner 
Date:   Mon Aug 5 19:24:52 2024 -0400

Merge commit 'refs/users/meissner/heads/work175-bugs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work175-bugs

Diff:

[gcc(refs/users/meissner/heads/work175-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:27dc640d1a90c738203a2168eb5ce10e33c58b34

commit 27dc640d1a90c738203a2168eb5ce10e33c58b34
Author: Michael Meissner 
Date:   Thu Aug 1 15:48:37 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-08-01  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..d3f1cc6620a5
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,6 @@
+ Branch work175-dmf, baseline 
+
+2024-08-01   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 1573af834b31..c8ba460272a5 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work175 branch
+work175-dmf branch

[gcc/meissner/heads/work175-dmf] (6 commits) Merge commit 'refs/users/meissner/heads/work175-dmf' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work175-dmf' was updated to point to:

 450406814595... Merge commit 'refs/users/meissner/heads/work175-dmf' of git

It previously pointed to:

 1fc1d66280c2... Merge commit 'refs/users/meissner/heads/work175-dmf' of git

Diff:

Summary of changes (added commits):
---

  4504068... Merge commit 'refs/users/meissner/heads/work175-dmf' of git
  27dc640... Add ChangeLog.dmf and update REVISION.
  6ef0fb1... Update ChangeLog.* (*)
  e198be0... Add -mcpu=future tuning support. (*)
  8553a0e... Add support for -mcpu=future (*)
  71db6b9... Revert changes (*)

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[gcc(refs/users/meissner/heads/work175-dmf)] Merge commit 'refs/users/meissner/heads/work175-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4504068145957df22936be81a57e37b0dcb9b626

commit 4504068145957df22936be81a57e37b0dcb9b626
Merge: 27dc640d1a90 1fc1d66280c2
Author: Michael Meissner 
Date:   Mon Aug 5 19:26:32 2024 -0400

Merge commit 'refs/users/meissner/heads/work175-dmf' of 
git+ssh://gcc.gnu.org/git/gcc into me/work175-dmf

Diff:

[gcc/meissner/heads/work175-tar] (6 commits) Merge commit 'refs/users/meissner/heads/work175-tar' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work175-tar' was updated to point to:

 43f8fc81a03e... Merge commit 'refs/users/meissner/heads/work175-tar' of git

It previously pointed to:

 a154e40b3459... Merge commit 'refs/users/meissner/heads/work175-tar' of git

Diff:

Summary of changes (added commits):
---

  43f8fc8... Merge commit 'refs/users/meissner/heads/work175-tar' of git
  6888c95... Add ChangeLog.tar and update REVISION.
  6ef0fb1... Update ChangeLog.* (*)
  e198be0... Add -mcpu=future tuning support. (*)
  8553a0e... Add support for -mcpu=future (*)
  71db6b9... Revert changes (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work175-tar' matches
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[gcc(refs/users/meissner/heads/work175-tar)] Add ChangeLog.tar and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:6888c95c6ab368f51aee025de02d23ac1b9b048b

commit 6888c95c6ab368f51aee025de02d23ac1b9b048b
Author: Michael Meissner 
Date:   Thu Aug 1 15:50:27 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-08-01  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index ..3a9f2525f736
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,6 @@
+ Branch work175-tar, baseline 
+
+2024-08-01   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 1573af834b31..abb1260b1697 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work175 branch
+work175-tar branch

[gcc(refs/users/meissner/heads/work175-tar)] Merge commit 'refs/users/meissner/heads/work175-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:43f8fc81a03efb073344d746fd1542dcdb0c018b

commit 43f8fc81a03efb073344d746fd1542dcdb0c018b
Merge: 6888c95c6ab3 a154e40b3459
Author: Michael Meissner 
Date:   Mon Aug 5 19:28:20 2024 -0400

Merge commit 'refs/users/meissner/heads/work175-tar' of 
git+ssh://gcc.gnu.org/git/gcc into me/work175-tar

Diff:

[gcc/meissner/heads/work175-test] (6 commits) Merge commit 'refs/users/meissner/heads/work175-test' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work175-test' was updated to point to:

 6e72c30acf25... Merge commit 'refs/users/meissner/heads/work175-test' of gi

It previously pointed to:

 7338f4b69698... Merge commit 'refs/users/meissner/heads/work175-test' of gi

Diff:

Summary of changes (added commits):
---

  6e72c30... Merge commit 'refs/users/meissner/heads/work175-test' of gi
  baf3c89... Add ChangeLog.test and update REVISION.
  6ef0fb1... Update ChangeLog.* (*)
  e198be0... Add -mcpu=future tuning support. (*)
  8553a0e... Add support for -mcpu=future (*)
  71db6b9... Revert changes (*)

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[gcc(refs/users/meissner/heads/work175-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:baf3c8921ab64203ca248ce8f1c8c1de31edd7d0

commit baf3c8921ab64203ca248ce8f1c8c1de31edd7d0
Author: Michael Meissner 
Date:   Thu Aug 1 15:52:09 2024 -0400

Add ChangeLog.test and update REVISION.

2024-08-01  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..a94f433cda2b
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,6 @@
+ Branch work175-test, baseline 
+
+2024-08-01   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 1573af834b31..ad7bacba19e3 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work175 branch
+work175-test branch

[gcc(refs/users/meissner/heads/work175-test)] Merge commit 'refs/users/meissner/heads/work175-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:6e72c30acf2532af02022645376d6e0dd3900da8

commit 6e72c30acf2532af02022645376d6e0dd3900da8
Merge: baf3c8921ab6 7338f4b69698
Author: Michael Meissner 
Date:   Mon Aug 5 19:30:32 2024 -0400

Merge commit 'refs/users/meissner/heads/work175-test' of 
git+ssh://gcc.gnu.org/git/gcc into me/work175-test

Diff:

[gcc/meissner/heads/work175-vpair] (6 commits) Merge commit 'refs/users/meissner/heads/work175-vpair' of g

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work175-vpair' was updated to point to:

 e7885a2fcaab... Merge commit 'refs/users/meissner/heads/work175-vpair' of g

It previously pointed to:

 b8e6d6a6961d... Merge commit 'refs/users/meissner/heads/work175-vpair' of g

Diff:

Summary of changes (added commits):
---

  e7885a2... Merge commit 'refs/users/meissner/heads/work175-vpair' of g
  dba201f... Add ChangeLog.vpair and update REVISION.
  6ef0fb1... Update ChangeLog.* (*)
  e198be0... Add -mcpu=future tuning support. (*)
  8553a0e... Add support for -mcpu=future (*)
  71db6b9... Revert changes (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work175-vpair' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work175-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:dba201fdf0d088c55743fc3e15e7a5ec692d71f4

commit dba201fdf0d088c55743fc3e15e7a5ec692d71f4
Author: Michael Meissner 
Date:   Thu Aug 1 15:49:33 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-08-01  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 6 ++
 gcc/REVISION| 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..8355bde3ebaa
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,6 @@
+ Branch work175-vpair, baseline 
+
+2024-08-01   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 1573af834b31..55efdc156d49 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work175 branch
+work175-vpair branch

[gcc(refs/users/meissner/heads/work175-vpair)] Merge commit 'refs/users/meissner/heads/work175-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e7885a2fcaab21f6986bda41254001f2e8b3238c

commit e7885a2fcaab21f6986bda41254001f2e8b3238c
Merge: dba201fdf0d0 b8e6d6a6961d
Author: Michael Meissner 
Date:   Mon Aug 5 19:31:43 2024 -0400

Merge commit 'refs/users/meissner/heads/work175-vpair' of 
git+ssh://gcc.gnu.org/git/gcc into me/work175-vpair

Diff:

[gcc r15-2733] libbacktrace: avoid -Wpointer-arith errors

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:3a51aaf5f4ccd3d2ed871727c16f9c6f9ed54e50

commit r15-2733-g3a51aaf5f4ccd3d2ed871727c16f9c6f9ed54e50
Author: Ian Lance Taylor 
Date:   Mon Aug 5 16:46:03 2024 -0700

libbacktrace: avoid -Wpointer-arith errors

Based on patch from Kirill Müller.

* configure.ac (ACX_PROG_CC_WARNING_OPTS): Add -Wpointer-arith.
* pecoff.c (coff_add): Cast void pointers.
* xcoff.c (xcoff_add): Likewise.
* configure: Regenerate.

Diff:
---
 libbacktrace/configure| 3 ++-
 libbacktrace/configure.ac | 3 ++-
 libbacktrace/pecoff.c | 7 ---
 libbacktrace/xcoff.c  | 4 +++-
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/libbacktrace/configure b/libbacktrace/configure
index fe0bb2083eb1..db491a782349 100755
--- a/libbacktrace/configure
+++ b/libbacktrace/configure
@@ -12385,7 +12385,8 @@ save_CFLAGS="$CFLAGS"
 for real_option in -W -Wall -Wwrite-strings -Wstrict-prototypes \
  -Wmissing-prototypes -Wold-style-definition \
  -Wmissing-format-attribute -Wcast-qual \
- -Wno-attributes -Wno-unknown-attributes; do
+ -Wno-attributes -Wno-unknown-attributes \
+ -Wpointer-arith; do
   # Do the check with the no- prefix removed since gcc silently
   # accepts any -Wno-* option on purpose
   case $real_option in
diff --git a/libbacktrace/configure.ac b/libbacktrace/configure.ac
index bfd7f35d2d2b..69eb2023677a 100644
--- a/libbacktrace/configure.ac
+++ b/libbacktrace/configure.ac
@@ -145,7 +145,8 @@ AC_SUBST(EXTRA_FLAGS)
 ACX_PROG_CC_WARNING_OPTS([-W -Wall -Wwrite-strings -Wstrict-prototypes \
  -Wmissing-prototypes -Wold-style-definition \
  -Wmissing-format-attribute -Wcast-qual \
- -Wno-attributes -Wno-unknown-attributes],
+ -Wno-attributes -Wno-unknown-attributes \
+ -Wpointer-arith],
  [WARN_FLAGS])
 
 AC_ARG_ENABLE([werror],
diff --git a/libbacktrace/pecoff.c b/libbacktrace/pecoff.c
index ccd5ccbce2ce..15a73ff0b2aa 100644
--- a/libbacktrace/pecoff.c
+++ b/libbacktrace/pecoff.c
@@ -704,7 +704,7 @@ coff_add (struct backtrace_state *state, int descriptor,
   magic_ok = memcmp (magic, "PE\0", 4) == 0;
   fhdr_off += 4;
 
-  memcpy (&fhdr, fhdr_view.data + 4, sizeof fhdr);
+  memcpy (&fhdr, (const unsigned char *) fhdr_view.data + 4, sizeof fhdr);
 }
   else
 {
@@ -738,7 +738,7 @@ coff_add (struct backtrace_state *state, int descriptor,
   sects_view_valid = 1;
   opt_hdr = (const b_coff_optional_header *) sects_view.data;
   sects = (const b_coff_section_header *)
-(sects_view.data + fhdr.size_of_optional_header);
+((const unsigned char *) sects_view.data + fhdr.size_of_optional_header);
 
   is_64 = 0;
   memset (&image_base, 0, sizeof image_base);
@@ -781,7 +781,8 @@ coff_add (struct backtrace_state *state, int descriptor,
goto fail;
   syms_view_valid = 1;
 
-  str_size = coff_read4 (syms_view.data + syms_size);
+  str_size = coff_read4 ((const unsigned char *) syms_view.data
++ syms_size);
 
   str_off = syms_off + syms_size;
 
diff --git a/libbacktrace/xcoff.c b/libbacktrace/xcoff.c
index 01443c48401b..84ce07b8e2ca 100644
--- a/libbacktrace/xcoff.c
+++ b/libbacktrace/xcoff.c
@@ -1203,7 +1203,9 @@ xcoff_add (struct backtrace_state *state, int descriptor, 
off_t offset,
goto fail;
   syms_view_valid = 1;
 
-  memcpy (&str_size, syms_view.data + syms_size, 4);
+  memcpy (&str_size,
+ (const unsigned char *) syms_view.data + syms_size,
+ 4);
 
   str_off = fhdr.f_symptr + syms_size;

[gcc r15-2735] c++: remove function/var concepts code

[Marek Polacek via Gcc-cvs]

https://gcc.gnu.org/g:935e82248873c3798d4ede742a75ad10e99257ad

commit r15-2735-g935e82248873c3798d4ede742a75ad10e99257ad
Author: Marek Polacek 
Date:   Thu Aug 1 15:39:10 2024 -0400

c++: remove function/var concepts code

This patch removes vestigial Concepts TS code as discussed in
.

In particular, it removes code related to function/variable concepts.
That includes variable_concept_p and function_concept_p, which then
cascades into removing DECL_DECLARED_CONCEPT_P etc.  So I think we
no longer need to say "standard concept" since there are no non-standard
ones anymore.

I've added two new errors saying that "variable/function concepts are
no longer supported".

gcc/cp/ChangeLog:

* constexpr.cc (cxx_eval_constant_expression): Don't call
unpack_concept_check.  Add a concept_check_p assert.  Remove
function_concept_p code.
* constraint.cc (check_constraint_atom): Remove function concepts 
code.
(unpack_concept_check): Remove.
(get_concept_check_template): Remove Concepts TS code.
(resolve_function_concept_overload): Remove.
(resolve_function_concept_check): Remove.
(resolve_concept_check): Remove Concepts TS code.
(get_returned_expression): Remove.
(get_variable_initializer): Remove.
(get_concept_definition): Remove Concepts TS code.
(normalize_concept_check): Likewise.
(build_function_check): Remove.
(build_variable_check): Remove.
(build_standard_check): Use concept_definition_p instead of
standard_concept_p.
(build_concept_check): Remove variable_concept_p/function_concept_p
code.
(build_concept_id): Simplify.
(build_type_constraint): Likewise.
(placeholder_extract_concept_and_args): Likewise.
(satisfy_nondeclaration_constraints): Likewise.
(check_function_concept): Remove.
(get_constraint_error_location): Remove Concepts TS code.
* cp-tree.h (DECL_DECLARED_CONCEPT_P): Remove.
(check_function_concept): Remove.
(unpack_concept_check): Remove.
(standard_concept_p): Remove.
(variable_concept_p): Remove.
(function_concept_p): Remove.
(concept_definition_p): Simplify.
(concept_check_p): Don't check for CALL_EXPR.
* decl.cc (check_concept_refinement): Remove.
(duplicate_decls): Remove check_concept_refinement code.
(is_concept_var): Remove.
(cp_finish_decl): Remove is_concept_var.
(check_concept_fn): Remove.
(grokfndecl): Give an error about function concepts not being 
supported
anymore.  Remove unused code.
(grokvardecl): Give an error about variable concepts not being
supported anymore.
(finish_function): Remove DECL_DECLARED_CONCEPT_P code.
* decl2.cc (min_vis_expr_r): Use concept_definition_p instead of
standard_concept_p.
(maybe_instantiate_decl): Remove DECL_DECLARED_CONCEPT_P check.
(mark_used): Likewise.
* error.cc (dump_simple_decl): Use concept_definition_p instead of
standard_concept_p.
(dump_function_decl): Remove DECL_DECLARED_CONCEPT_P code.
(print_concept_check_info): Don't call unpack_concept_check.  
Simplify.
* mangle.cc (write_type_constraint): Likewise.
* parser.cc (cp_parser_nested_name_specifier_opt): Remove
function_concept_p code.  Only check concept_definition_p, not
variable_concept_p/standard_concept_p.
(add_debug_begin_stmt): Remove DECL_DECLARED_CONCEPT_P code.
(cp_parser_template_declaration_after_parameters): Remove a stale
comment.
* pt.cc (check_explicit_specialization): Remove
DECL_DECLARED_CONCEPT_P code.
(process_partial_specialization): Remove variable_concept_p code.
(lookup_template_variable): Likewise.
(tsubst_expr) : Remove Concepts TS code and 
simplify.
(do_decl_instantiation): Remove DECL_DECLARED_CONCEPT_P code.
(instantiate_decl): Likewise.
(placeholder_type_constraint_dependent_p): Don't call
unpack_concept_check.  Add a concept_check_p assert.
(convert_generic_types_to_packs): Likewise.
* semantics.cc (finish_call_expr): Remove Concepts TS code and 
simplify.

gcc/testsuite/ChangeLog:

* g++.dg/concepts/decl-diagnose.C: Adjust dg-error.
* g++.dg/concepts/fn-concept2.C: Likewise.
* g++.dg/concepts/pr71128.C: Likewise.
* g++.dg/concepts/var-concept6.C: Likewise.

[gcc(refs/users/meissner/heads/work175-dmf)] Use vector pair load/store for memcpy with -mcpu=future

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3df0a672245ea3a628ecca1be66f491c7fb5ae97

commit 3df0a672245ea3a628ecca1be66f491c7fb5ae97
Author: Michael Meissner 
Date:   Mon Aug 5 19:45:19 2024 -0400

Use vector pair load/store for memcpy with -mcpu=future

In the development for the power10 processor, GCC did not enable using the 
load
vector pair and store vector pair instructions when optimizing things like
memory copy.  This patch enables using those instructions if -mcpu=future is
used.

2024-08-05  Michael Meissner  

gcc/

* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable 
using
load vector pair and store vector pair instructions for memory copy
operations.
(POWERPC_MASKS): Make the bit for enabling using load vector pair 
and
store vector pair operations set and reset when the PowerPC 
processor is
changed.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index e73d9ef51f8d..74151be40484 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,7 +86,8 @@
 
 #define POWER11_MASKS_SERVER   ISA_3_1_MASKS_SERVER
 
-#define FUTURE_MASKS_SERVERPOWER11_MASKS_SERVER
+#define FUTURE_MASKS_SERVER(POWER11_MASKS_SERVER   \
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -116,6 +117,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2653-Add wD constraint.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:42a68d59f44ab8cfe36d40cf6e16d80d65fc8891

commit 42a68d59f44ab8cfe36d40cf6e16d80d65fc8891
Author: Michael Meissner 
Date:   Mon Aug 5 19:54:18 2024 -0400

RFC2653-Add wD constraint.

This patch adds a new constraint ('wD') that matches the accumulator 
registers
that overlap with VSX registers 0..31 on power10.  Future patches will add 
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.

2024-08-05   Michael Meissner  

* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/mma.md (mma_): Prepare for alternate 
accumulator
registers.  Use wD constraint instead of 'd' constraint.  Use
accumulator_operand instead of fpr_reg_operand.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
   "TARGET_MMA"
   " %A0"
@@ -523,7 +523,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
@@ -532,8 +532,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
@@ -542,7 +542,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
@@ -551,8 +551,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
@@ -561,7 +561,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -574,8 +574,8 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
(match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -588,7 +588,7 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -601,8 +601,8 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2653-Add support for dense math registers.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:dacedf2cde444a8fd76dc9917ed5bb6b4f7f299c

commit dacedf2cde444a8fd76dc9917ed5bb6b4f7f299c
Author: Michael Meissner 
Date:   Mon Aug 5 20:04:10 2024 -0400

RFC2653-Add support for dense math registers.

The MMA subsystem added the notion of accumulator registers as an optional
feature of ISA 3.1 (power10).  In ISA 3.1, these accumulators overlapped 
with
the VSX registers 0..31, but logically the accumulator registers were 
separate
from the FPR registers.  In ISA 3.1, it was anticipated that in future 
systems,
the accumulator registers may no overlap with the FPR registers.  This patch
adds the support for dense math registers as separate registers.

This particular patch does not change the MMA support to use the 
accumulators
within the dense math registers.  This patch just adds the basic support for
having separate DMRs.  The next patch will switch the MMA support to use the
accumulators if -mcpu=future is used.

For testing purposes, I added an undocumented option '-mdense-math' to 
enable
or disable the dense math support.

This patch adds a new constraint (wD).  If MMA is selected but dense math is
not selected (i.e. -mcpu=power10), the wD constraint will allow access to
accumulators that overlap with VSX registers 0..31.  If both MMA and dense 
math
are selected (i.e. -mcpu=future), the wD constraint will only allow dense 
math
registers.

This patch modifies the existing %A output modifier.  If MMA is selected but
dense math is not selected, then %A output modifier converts the VSX 
register
number to the accumulator number, by dividing it by 4.  If both MMA and 
dense
math are selected, then %A will map the separate DMR registers into 0..7.

The intention is that user code using extended asm can be modified to run on
both MMA without dense math and MMA with dense math:

1)  If possible, don't use extended asm, but instead use the MMA 
built-in
functions;

2)  If you do need to write extended asm, change the d constraints
targetting accumulators should now use wD;

3)  Only use the built-in zero, assemble and disassemble functions 
create
move data between vector quad types and dense math accumulators.
I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the
extended asm code.  The reason is these instructions assume there 
is a
1-to-1 correspondence between 4 adjacent FPR registers and an
accumulator that overlaps with those instructions.  With 
accumulators
now being separate registers, there no longer is a 1-to-1
correspondence.

It is possible that the mangling for DMRs and the GDB register numbers may
produce other changes in the future.

2024-08-05   Michael Meissner  

* config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec.
(movxo): Add comments about dense math registers.
(movxo_nodm): Rename from movxo and restrict the usage to machines
without dense math registers.
(movxo_dm): New insn for movxo support for machines with dense math
registers.
(mma_): Restrict usage to machines without dense math 
registers.
(mma_xxsetaccz): Add a define_expand wrapper, and add support for 
dense
math registers.
(mma_dmsetaccz): New insn.
* config/rs6000/predicates.md (dmr_operand): New predicate.
(accumulator_operand): Add support for dense math registers.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): 
Do
not issue a de-prime instruction when disassembling a vector quad 
on a
system with dense math registers.
* config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): 
Define
__DENSE_MATH__ if we have dense math registers.
* config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE.
(enum rs6000_reload_reg_type): Add RELOAD_REG_DMR.
(LAST_RELOAD_REG_CLASS): Add support for DMR registers and the wD
constraint.
(reload_reg_map): Likewise.
(rs6000_reg_names): Likewise.
(alt_reg_names): Likewise.
(rs6000_hard_regno_nregs_internal): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_secondary_reload_memory): Add support for DMR registers.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(print_operand): Make %A handle both FPRs and DMRs.
  

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:dbc25c21da736a9c71d755109756cbbdb6c71744

commit dbc25c21da736a9c71d755109756cbbdb6c71744
Author: Michael Meissner 
Date:   Mon Aug 5 20:07:06 2024 -0400

RFC2653-PowerPC: Switch to dense math names for all MMA operations.

This patch changes the assembler instruction names for MMA instructions from
the original name used in power10 to the new name when used with the dense 
math
system.  I.e. xvf64gerpp becomes dmxvf64gerpp.  The assembler will emit the
same bits for either spelling.

For the non-prefixed MMA instructions, we add a 'dm' prefix in front of the
instruction.  However, the prefixed instructions have a 'pm' prefix, and we 
add
the 'dm' prefix afterwards.  To prevent having two sets of parallel int
attributes, we remove the "pm" prefix from the instruction string in the
attributes, and add it later, both in the insn name and in the output 
template.

2024-08-05   Michael Meissner  

gcc/

* config/rs6000/mma.md (vvi4i4i8): Change the instruction to not 
have a
"pm" prefix.
(avvi4i4i8): Likewise.
(vvi4i4i2): Likewise.
(avvi4i4i2): Likewise.
(vvi4i4): Likewise.
(avvi4i4): Likewise.
(pvi4i2): Likewise.
(apvi4i2): Likewise.
(vvi4i4i4): Likewise.
(avvi4i4i4): Likewise.
(mma_): Add support for running on DMF systems, generating the 
dense
math instruction and using the dense math accumulators.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_pm): Add support for running on DMF systems, 
generating
the dense math instruction and using the dense math accumulators.
Rename the insn with a 'pm' prefix and add either 'pm' or 'pmdm'
prefixes based on whether we have the original MMA specification or 
if
we have dense math support.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.
(mma_pm): Likewise.

Diff:
---
 gcc/config/rs6000/mma.md | 157 +++
 1 file changed, 104 insertions(+), 53 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index ae6e7e9695be..2e04eb653fa6 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -225,44 +225,47 @@
 (UNSPEC_MMA_XVF64GERNP "xvf64gernp")
 (UNSPEC_MMA_XVF64GERNN "xvf64gernn")])
 
-(define_int_attr vvi4i4i8  [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")])
+;; The "pm" prefix is not in these expansions, so that we can generate
+;; pmdmxvi4ger8 on systems with dense math registers and xvi4ger8 on systems
+;; without dense math registers.
+(define_int_attr vvi4i4i8  [(UNSPEC_MMA_PMXVI4GER8 "xvi4ger8")])
 
-(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP   
"pmxvi4ger8pp")])
+(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP   "xvi4ger8pp")])
 
-(define_int_attr vvi4i4i2  [(UNSPEC_MMA_PMXVI16GER2"pmxvi16ger2")
-(UNSPEC_MMA_PMXVI16GER2S   "pmxvi16ger2s")
-(UNSPEC_MMA_PMXVF16GER2"pmxvf16ger2")
-(UNSPEC_MMA_PMXVBF16GER2   
"pmxvbf16ger2")])
+(define_int_attr vvi4i4i2  [(UNSPEC_MMA_PMXVI16GER2"xvi16ger2")
+(UNSPEC_MMA_PMXVI16GER2S   "xvi16ger2s")
+(UNSPEC_MMA_PMXVF16GER2"xvf16ger2")
+(UNSPEC_MMA_PMXVBF16GER2   "xvbf16ger2")])
 
-(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP  "pmxvi16ger2pp")
-(UNSPEC_MMA_PMXVI16GER2SPP 
"pmxvi16ger2spp")
-(UNSPEC_MMA_PMXVF16GER2PP  "pmxvf16ger2pp")
-(UNSPEC_MMA_PMXVF16GER2PN  "pmxvf16ger2pn")
-(UNSPEC_MMA_PMXVF16GER2NP  "pmxvf16ger2np")
-(UNSPEC_MMA_PMXVF16GER2NN  "pmxvf16ger2nn")
-(UNSPEC_MMA_PMXVBF16GER2PP 
"pmxvbf16ger2pp")
-(UNSPEC_MMA_PMXVBF16GER2PN 
"pmxvbf16ger2pn")
-(UNSPEC_MMA_PMXVBF16GER2NP 
"pmxvbf16ger2np")
-(UNSPEC_MMA_PMXVBF16GER2NN 
"pmxvbf16ger2nn")])
+(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP  "xvi16ger2pp")
+(UNSPEC_MMA_PMXVI16GER2SPP "xvi16ger2spp")
+(UNSPEC_MMA_PMXVF16GER2PP  "xvf16ger2pp")
+(UNSPEC_MMA_PMXVF16GER2PN  "xvf1

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2653-Add dense math test for new instruction names.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8b1aaea7b4ad06eba8baaf2528966ae75c926953

commit 8b1aaea7b4ad06eba8baaf2528966ae75c926953
Author: Michael Meissner 
Date:   Mon Aug 5 22:09:03 2024 -0400

RFC2653-Add dense math test for new instruction names.

2024-08-05   Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/dm-double-test.c: New test.
* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
target test.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/dm-double-test.c | 194 ++
 gcc/testsuite/lib/target-supports.exp |  23 +++
 2 files changed, 217 insertions(+)

diff --git a/gcc/testsuite/gcc.target/powerpc/dm-double-test.c 
b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
new file mode 100644
index ..66c197795856
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
@@ -0,0 +1,194 @@
+/* Test derived from mma-double-1.c, modified for dense math.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_dense_math_ok } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+#include 
+#include 
+#include 
+
+typedef unsigned char vec_t __attribute__ ((vector_size (16)));
+typedef double v4sf_t __attribute__ ((vector_size (16)));
+#define SAVE_ACC(ACC, ldc, J)  \
+ __builtin_mma_disassemble_acc (result, ACC); \
+ rowC = (v4sf_t *) &CO[0*ldc+J]; \
+  rowC[0] += result[0]; \
+  rowC = (v4sf_t *) &CO[1*ldc+J]; \
+  rowC[0] += result[1]; \
+  rowC = (v4sf_t *) &CO[2*ldc+J]; \
+  rowC[0] += result[2]; \
+  rowC = (v4sf_t *) &CO[3*ldc+J]; \
+ rowC[0] += result[3];
+
+void
+DM (int m, int n, int k, double *A, double *B, double *C)
+{
+  __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;
+  v4sf_t result[4];
+  v4sf_t *rowC;
+  for (int l = 0; l < n; l += 4)
+{
+  double *CO;
+  double *AO;
+  AO = A;
+  CO = C;
+  C += m * 4;
+  for (int j = 0; j < m; j += 16)
+   {
+ double *BO = B;
+ __builtin_mma_xxsetaccz (&acc0);
+ __builtin_mma_xxsetaccz (&acc1);
+ __builtin_mma_xxsetaccz (&acc2);
+ __builtin_mma_xxsetaccz (&acc3);
+ __builtin_mma_xxsetaccz (&acc4);
+ __builtin_mma_xxsetaccz (&acc5);
+ __builtin_mma_xxsetaccz (&acc6);
+ __builtin_mma_xxsetaccz (&acc7);
+ unsigned long i;
+
+ for (i = 0; i < k; i++)
+   {
+ vec_t *rowA = (vec_t *) & AO[i * 16];
+ __vector_pair rowB;
+ vec_t *rb = (vec_t *) & BO[i * 4];
+ __builtin_mma_assemble_pair (&rowB, rb[1], rb[0]);
+ __builtin_mma_xvf64gerpp (&acc0, rowB, rowA[0]);
+ __builtin_mma_xvf64gerpp (&acc1, rowB, rowA[1]);
+ __builtin_mma_xvf64gerpp (&acc2, rowB, rowA[2]);
+ __builtin_mma_xvf64gerpp (&acc3, rowB, rowA[3]);
+ __builtin_mma_xvf64gerpp (&acc4, rowB, rowA[4]);
+ __builtin_mma_xvf64gerpp (&acc5, rowB, rowA[5]);
+ __builtin_mma_xvf64gerpp (&acc6, rowB, rowA[6]);
+ __builtin_mma_xvf64gerpp (&acc7, rowB, rowA[7]);
+   }
+ SAVE_ACC (&acc0, m, 0);
+ SAVE_ACC (&acc2, m, 4);
+ SAVE_ACC (&acc1, m, 2);
+ SAVE_ACC (&acc3, m, 6);
+ SAVE_ACC (&acc4, m, 8);
+ SAVE_ACC (&acc6, m, 12);
+ SAVE_ACC (&acc5, m, 10);
+ SAVE_ACC (&acc7, m, 14);
+ AO += k * 16;
+ BO += k * 4;
+ CO += 16;
+   }
+  B += k * 4;
+}
+}
+
+void
+init (double *matrix, int row, int column)
+{
+  for (int j = 0; j < column; j++)
+{
+  for (int i = 0; i < row; i++)
+   {
+ matrix[j * row + i] = (i * 16 + 2 + j) / 0.123;
+   }
+}
+}
+
+void
+init0 (double *matrix, double *matrix1, int row, int column)
+{
+  for (int j = 0; j < column; j++)
+for (int i = 0; i < row; i++)
+  matrix[j * row + i] = matrix1[j * row + i] = 0;
+}
+
+
+void
+print (const char *name, const double *matrix, int row, int column)
+{
+  printf ("Matrix %s has %d rows and %d columns:\n", name, row, column);
+  for (int i = 0; i < row; i++)
+{
+  for (int j = 0; j < column; j++)
+   {
+ printf ("%f ", matrix[j * row + i]);
+   }
+  printf ("\n");
+}
+  printf ("\n");
+}
+
+int
+main (int argc, char *argv[])
+{
+  int rowsA, colsB, common;
+  int i, j, k;
+  int ret = 0;
+
+  for (int t = 16; t <= 128; t += 16)
+{
+  for (int t1 = 4; t1 <= 16; t1 += 4)
+   {
+ rowsA = t;
+ colsB = t1;
+ common = 1;
+ /* printf ("Running test for rows = %d,cols = %d\n", t, t1); */
+ double A[rowsA * common];
+ double B[common * colsB];
+ double C[rowsA * colsB];
+ double D[rowsA * colsB];
+
+
+ init (A, rowsA, common);
+ init (B, common, colsB);
+ init0 (C, D, rowsA, colsB);
+ DM (rowsA, colsB, common, A, B,

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:db9f4a42fdb491fbe7f820e58931c3e330ed5cdd

commit db9f4a42fdb491fbe7f820e58931c3e330ed5cdd
Author: Michael Meissner 
Date:   Mon Aug 5 22:14:33 2024 -0400

RFC2653-PowerPC: Add support for 1,024 bit DMR registers.

This patch is a prelimianry patch to add the full 1,024 bit dense math 
register
(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of 
the
DMR register.

This patch only adds the new 1,024 bit register support.  It does not add
support for any instructions that need 1,024 bit registers instead of 512 
bit
registers.

I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
registers.  The 'wD' constraint added in previous patches is used for these
registers.  I added support to do load and store of DMRs via the VSX 
registers,
since there are no load/store dense math instructions.  I added the new 
keyword
'__dmr' to create 1,024 bit types that can be loaded into DMRs.  At 
present, I
don't have aliases for __dmr512 and __dmr1024 that we've discussed 
internally.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-08-05   Michael Meissner  

gcc/

* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(movtdo): New define_expand and define_insn_and_split to implement 
1,024
bit DMR registers.
(movtdo_insert512_upper): New insn.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr_to_memory): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
support.
(rs6000_init_builtins): Add support for __dmr keyword.
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add 
support
for TDOmode.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-modes.def (TDOmode): New mode.
* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
support for TDOmode.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_hard_regno_mode_ok): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Add support for TDOmode.  Setup 
reload
hooks for DMR mode.
(reg_offset_addressing_ok_p): Add support for TDOmode.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(rs6000_mangle_type): Add mangling for __dmr type.
(rs6000_dmr_register_move_cost): Add support for TDOmode.
(rs6000_split_multireg_move): Likewise.
(rs6000_invalid_conversion): Likewise.
* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
(enum rs6000_builtin_type_index): Add DMR type nodes.
(dmr_type_node): Likewise.
(ptr_dmr_type_node): Likewise.

gcc/testsuite/

* gcc.target/powerpc/dm-1024bit.c: New test.

Diff:
---
 gcc/config/rs6000/mma.md  | 154 ++
 gcc/config/rs6000/rs6000-builtin.cc   |  17 +++
 gcc/config/rs6000/rs6000-call.cc  |  10 +-
 gcc/config/rs6000/rs6000-modes.def|   4 +
 gcc/config/rs6000/rs6000.cc   | 101 -
 gcc/config/rs6000/rs6000.h|   6 +-
 gcc/testsuite/gcc.target/powerpc/dm-1024bit.c |  63 +++
 7 files changed, 321 insertions(+), 34 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 2e04eb653fa6..8461499e1c3d 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -92,6 +92,11 @@
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
UNSPEC_MMA_DMSETDMRZ
+   UNSPEC_DM_INSERT512_UPPER
+   UNSPEC_DM_INSERT512_LOWER
+   UNSPEC_DM_EXTRACT512
+   UNSPEC_DMR_RELOAD_FROM_MEMORY
+   UNSPEC_DMR_RELOAD_TO_MEMORY
   ])
 
 (define_c_enum "unspecv"
@@ -793,3 +798,152 @@
 }
   [(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
+
+;; TDOmode (__dmr keyword for 1,024 bit registers).
+(define_expand "movtdo"
+  [(set (match_operand:TDO 0 "nonimmediate_operand")
+   (match_operand:TDO 1 "input_operand"))]
+  "TARGET_MMA_DENSE_MATH"
+{
+  rs6000_emit_move (operands[0], operands[1], TDOmode);
+  DONE;
+})
+
+(define_insn_and_split "*movtdo"
+  [(set (match_operand:TDO 

[gcc r15-2736] sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR116189]

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:0355c943b9e954e8f59068971d934f1b91ecb729

commit r15-2736-g0355c943b9e954e8f59068971d934f1b91ecb729
Author: Andrew Pinski 
Date:   Sat Aug 3 09:30:57 2024 -0700

sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR116189]

This was an interesting compare debug failure to debug. The first symptom
was in gcse which would produce different order of creating 
psedu-registers. This
was caused by a different order of a hashtable walk, due to the hash table 
having different
number of entries. Which in turn was due to the number of max insn being 
different between
the 2 runs. The place max insn uid comes from was in sh_recog_treg_set_expr 
which is called
via rtx_costs and fwprop would cause rtx_costs in some cases for debug insn 
related stuff.

Build and tested for sh4-linux-gnu.

PR target/116189

gcc/ChangeLog:

* config/sh/sh.cc (sh_recog_treg_set_expr): Don't call 
make_insn_raw,
make the insn with a fake uid.

gcc/testsuite/ChangeLog:

* c-c++-common/torture/pr116189-1.c: New test.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/config/sh/sh.cc | 12 +-
 gcc/testsuite/c-c++-common/torture/pr116189-1.c | 30 +
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index bc0174203810..7391b8df5830 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -12297,7 +12297,17 @@ sh_recog_treg_set_expr (rtx op, machine_mode mode)
  have to capture its current state and restore it afterwards.  */
   recog_data_d prev_recog_data = recog_data;
 
-  rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op));
+  /* Note we can't use insn_raw here since that increases the uid
+ and could cause debug compare differences; this insn never leaves
+ this function so create a dummy one. */
+  rtx_insn* i = as_a  (rtx_alloc (INSN));
+
+  INSN_UID (i) = 1;
+  PATTERN (i) = gen_rtx_SET (get_t_reg_rtx (), op);
+  INSN_CODE (i) = -1;
+  REG_NOTES (i) = NULL;
+  INSN_LOCATION (i) = curr_insn_location ();
+  BLOCK_FOR_INSN (i) = NULL;
   SET_PREV_INSN (i) = NULL;
   SET_NEXT_INSN (i) = NULL;
 
diff --git a/gcc/testsuite/c-c++-common/torture/pr116189-1.c 
b/gcc/testsuite/c-c++-common/torture/pr116189-1.c
new file mode 100644
index ..055c563f43e5
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/torture/pr116189-1.c
@@ -0,0 +1,30 @@
+/* { dg-additional-options "-fcompare-debug" } */
+
+/* PR target/116189 */
+
+/* In the sh backend, we used to create insn in the path of rtx_costs.
+   This means sometimes the max uid for insns would be different between
+   debugging and non debugging which then would cause gcse's hashtable
+   to have different number of slots which would cause a different walk
+   for that hash table.  */
+
+extern void ff(void);
+extern short nn[8][4];
+typedef unsigned short move_table[4];
+extern signed long long ira_overall_cost;
+extern signed long long ira_load_cost;
+extern move_table *x_ira_register_move_cost[1];
+struct move { struct move *next; };
+unsigned short t;
+void emit_move_list(struct move * list, int freq, unsigned char mode, int 
regno) {
+  int cost;
+  for (; list != 0; list = list->next)
+  {
+ff();
+unsigned short aclass = t;
+cost = (nn)[mode][aclass] ;
+ira_load_cost = cost;
+cost = x_ira_register_move_cost[mode][aclass][aclass] * freq ;
+ira_overall_cost = cost;
+  }
+}

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2655-Add saturating subtract built-ins.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:6cb2d07ddd27b44ce00d3ddc809abea63d52fe71

commit 6cb2d07ddd27b44ce00d3ddc809abea63d52fe71
Author: Michael Meissner 
Date:   Mon Aug 5 22:29:02 2024 -0400

RFC2655-Add saturating subtract built-ins.

This patch adds support for a saturating subtract built-in function that 
may be
added to a future PowerPC processor.  Note, if it is added, the name of the
built-in function may change before GCC 13 is released.  If the name 
changes,
we will submit a patch changing the name.

I also added support for providing dense math built-in functions, even 
though
at present, we have not added any new built-in functions for dense math.  
It is
likely we will want to add new dense math built-in functions as the dense 
math
support is fleshed out.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-08-05   Michael Meissner  

gcc/

* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add 
support
for flagging invalid use of future built-in functions.
(rs6000_builtin_is_supported): Add support for future built-in
functions.
* config/rs6000/rs6000-builtins.def 
(__builtin_saturate_subtract32): New
built-in function for -mcpu=future.
(__builtin_saturate_subtract64): Likewise.
* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add 
stanzas
for -mcpu=future built-ins.
(stanza_map): Likewise.
(enable_string): Likewise.
(struct attrinfo): Likewise.
(parse_bif_attrs): Likewise.
(write_decls): Likewise.
* config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
built-in insn declarations.
(sat_sub3_dot): Likewise.
(sat_sub3_dot2): Likewise.
* doc/extend.texi (Future PowerPC built-ins): New section.

gcc/testsuite/

* gcc.target/powerpc/subfus-1.c: New test.
* gcc.target/powerpc/subfus-2.c: Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc | 17 
 gcc/config/rs6000/rs6000-builtins.def   | 10 +
 gcc/config/rs6000/rs6000-gen-builtins.cc| 35 ++---
 gcc/config/rs6000/rs6000.md | 60 +
 gcc/doc/extend.texi | 24 
 gcc/testsuite/gcc.target/powerpc/subfus-1.c | 32 +++
 gcc/testsuite/gcc.target/powerpc/subfus-2.c | 32 +++
 7 files changed, 205 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 432a0d77ef0b..1fadf3440941 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,6 +139,17 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
 case ENB_MMA:
   error ("%qs requires the %qs option", name, "-mmma");
   break;
+case ENB_FUTURE:
+  error ("%qs requires the %qs option", name, "-mcpu=future");
+  break;
+case ENB_FUTURE_64:
+  error ("%qs requires the %qs option and either the %qs or %qs option",
+name, "-mcpu=future", "-m64", "-mpowerpc64");
+  break;
+case ENB_DM:
+  error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
+"-mdense-math");
+  break;
 default:
 case ENB_ALWAYS:
   gcc_unreachable ();
@@ -194,6 +205,12 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
   return TARGET_HTM;
 case ENB_MMA:
   return TARGET_MMA;
+case ENB_FUTURE:
+  return TARGET_FUTURE;
+case ENB_FUTURE_64:
+  return TARGET_FUTURE && TARGET_POWERPC64;
+case ENB_DM:
+  return TARGET_DENSE_MATH;
 default:
   gcc_unreachable ();
 }
diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index 0c3c884c1104..17fedc9cef53 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -137,6 +137,8 @@
 ;   endian   Needs special handling for endianness
 ;   ibmldRestrict usage to the case when TFmode is IBM-128
 ;   ibm128   Restrict usage to the case where __ibm128 is supported or if ibmld
+;   future   Restrict usage to future instructions
+;   dm   Restrict usage to dense math
 ;
 ; Each attribute corresponds to extra processing required when
 ; the built-in is expanded.  All such special processing should
@@ -3921,3 +3923,11 @@
 
   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
 STXVP nothing {mma,pair}
+
+[future]
+  const signed int __builtin_saturate_subtract32 (signed int, signed int);
+  SAT_SUBSI sat_subsi3 {}
+
+[future-64]
+  const signed long __builtin_saturate_subtract64 (signed long,  signed long);
+  SAT_SUBDI sat_subdi3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc 
b/gcc/confi

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2656-Support load/store vector with right length.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3b1a2b3d129ea5d4c370e81adfed87957cc4a767

commit 3b1a2b3d129ea5d4c370e81adfed87957cc4a767
Author: Michael Meissner 
Date:   Mon Aug 5 22:20:39 2024 -0400

RFC2656-Support load/store vector with right length.

This patch adds support for new instructions that may be added to the 
PowerPC
architecture in the future to enhance the load and store vector with length
instructions.

The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to 
use
since the count for the number of bytes must be in the top 8 bits of the GPR
register, instead of the bottom 8 bits.  This meant that code generating 
these
instructions typically had to do a shift left by 56 bits to get the count 
into
the right position.  In a future version of the PowerPC architecture, new
variants of these instructions might be added that expect the count to be in
the bottom 8 bits of the GPR register.  These patches add this support to 
GCC
if the user uses the -mcpu=future option.

I discovered that the code in rs6000-string.cc to generate ISA 3.1 
lxvl/stxvl
future lxvll/stxvll instructions would generate these instructions on 
32-bit.
However the patterns for these instructions is only done on 64-bit systems. 
 So
I added a check for 64-bit support before generating the instructions.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2024-08-05   Michael Meissner  

gcc/

* config/rs6000/rs6000-string.cc (expand_block_move): Do not 
generate
lxvl and stxvl on 32-bit.
* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl 
with
the shift count automaticaly used in the insn.
(lxvrl): New insn for -mcpu=future.
(lxvrll): Likewise.
(stxvl): If -mcpu=future, generate the stxvl with the shift count
automaticaly used in the insn.
(stxvrl): New insn for -mcpu=future.
(stxvrll): Likewise.

gcc/testsuite/

* gcc.target/powerpc/lxvrl.c: New test.
* lib/target-supports.exp 
(check_effective_target_powerpc_future_ok):
New effective target.

Diff:
---
 gcc/config/rs6000/rs6000-string.cc   |   1 +
 gcc/config/rs6000/vsx.md | 122 +--
 gcc/testsuite/gcc.target/powerpc/lxvrl.c |  32 
 gcc/testsuite/lib/target-supports.exp|  12 +++
 4 files changed, 146 insertions(+), 21 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index 3674c4bd9847..818ff10a8ac8 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2786,6 +2786,7 @@ expand_block_move (rtx operands[], bool might_overlap)
 
   if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
  && TARGET_BLOCK_OPS_VECTOR_PAIR
+ && TARGET_POWERPC64
  && bytes >= 32
  && (align >= 256 || !STRICT_ALIGNMENT))
{
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7892477fa922..d916a2d648ad 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5697,20 +5697,32 @@
   DONE;
 })
 
-;; Load VSX Vector with Length
+;; Load VSX Vector with Length.  If we have lxvrl, we don't have to do an
+;; explicit shift left into a pseudo.
 (define_expand "lxvl"
-  [(set (match_dup 3)
-(ashift:DI (match_operand:DI 2 "register_operand")
-   (const_int 56)))
-   (set (match_operand:V16QI 0 "vsx_register_operand")
-   (unspec:V16QI
-[(match_operand:DI 1 "gpc_reg_operand")
-  (mem:V16QI (match_dup 1))
- (match_dup 3)]
-UNSPEC_LXVL))]
+  [(use (match_operand:V16QI 0 "vsx_register_operand"))
+   (use (match_operand:DI 1 "gpc_reg_operand"))
+   (use (match_operand:DI 2 "gpc_reg_operand"))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  operands[3] = gen_reg_rtx (DImode);
+  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
+  rtx len;
+
+  if (TARGET_FUTURE)
+len = shift_len;
+  else
+{
+  len = gen_reg_rtx (DImode);
+  emit_insn (gen_rtx_SET (len, shift_len));
+}
+
+  rtx dest = operands[0];
+  rtx addr = operands[1];
+  rtx mem = gen_rtx_MEM (V16QImode, addr);
+  rtvec rv = gen_rtvec (3, addr, mem, len);
+  rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
+  emit_insn (gen_rtx_SET (dest, lxvl));
+  DONE;
 })
 
 (define_insn "*lxvl"
@@ -5734,6 +5746,34 @@
   "lxvll %x0,%1,%2"
   [(set_attr "type" "vecload")])
 
+;; For lxvrl and lxvrll, use the combiner to eliminate the shift.  The
+;; define_expand for lxvl will already incorporate the shift in generating the
+;; insn.  The lxvll buitl-in function required the user to have already done
+;; the shift.  Defining lxvrll this way, will optimize cases where the user has
+;; done the shift immediately before 

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2677-Add xvrlw support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:11a7f9ef1e49a3ab936425f51c66f6b7f094

commit 11a7f9ef1e49a3ab936425f51c66f6b7f094
Author: Michael Meissner 
Date:   Mon Aug 5 22:38:26 2024 -0400

RFC2677-Add xvrlw support.

2024-08-05  Michael Meissner  

gcc/

* config/rs6000/altivec.md (xvrlw): New insn.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.

gcc/testsuite/

* gcc.target/powerpc/vector-rotate-left.c: New test.

Diff:
---
 gcc/config/rs6000/altivec.md   | 14 +
 gcc/config/rs6000/rs6000.h |  3 ++
 .../gcc.target/powerpc/vector-rotate-left.c| 34 ++
 3 files changed, 51 insertions(+)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index aa9d8fffc901..5fa672812972 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,6 +1982,20 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; -mcpu=future adds a vector rotate left word variant.  There is no vector
+;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*xvrlw"
+  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+   (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+(match_operand:V4SI 2 "register_operand" "v,wa")))]
+  "TARGET_XVRLW"
+  "@
+   vrlw %0,%1,%2
+   xvrlw %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "altivec_vrl"
   [(set (match_operand:VI2 0 "register_operand" "=v")
 (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 6a0784855cba..a4ed3f4945de 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -590,6 +590,9 @@ extern int rs6000_vector_align[];
 /* Whether we have PADDIS support.  */
 #define TARGET_PADDIS  TARGET_FUTURE
 
+/* Whether we have XVRLW support.  */
+#define TARGET_XVRLW   TARGET_FUTURE
+
 /* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c 
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
new file mode 100644
index ..5a5f37755077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the xvrl (vector word rotate left using VSX registers insead of
+   Altivec registers is generated.  */
+
+#include 
+
+typedef vector unsigned int  v4si_t;
+
+v4si_t
+rotl_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x << n) | (x >> (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotr_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x >> n) | (x << (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotl_v4si_vector (v4si_t x, v4si_t y)
+{
+  __asm__ (" # %x0" : "+f" (x));   /* xvrlw.  */
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvrlw\M} 3  } } */

[gcc(refs/users/meissner/heads/work175-dmf)] RFC2686-Add paddis support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ae9a6032e7ad56deb8611bf8bfd02ccb67a9bc6c

commit ae9a6032e7ad56deb8611bf8bfd02ccb67a9bc6c
Author: Michael Meissner 
Date:   Mon Aug 5 22:34:51 2024 -0400

RFC2686-Add paddis support.

2024-08-05  Michael Meissner  

gcc/

* config/rs6000/constraints.md (eU): New constraint.
(eV): Likewise.
* config/rs6000/predicates.md (paddis_operand): New predicate.
(paddis_paddi_operand): Likewise.
(add_operand): Add paddis support.
* config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis 
support.
(num_insns_constant_multi): Likewise.
(print_operand): Add %B for paddis support.
* config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
(SIGNED_INTEGER_32BIT_P): Likewise.
* config/rs6000/rs6000.md (isa attribute): Add paddis support.
(enabled attribute); Likewise.
(add3): Likewise.
(adddi3 splitter): New splitter for paddis.
(movdi_internal64): Add paddis support.
(movdi splitter): New splitter for paddis.

gcc/testsuite/

* gcc.target/powerpc/prefixed-addis.c: New test.

Diff:
---
 gcc/config/rs6000/constraints.md  | 10 +++
 gcc/config/rs6000/predicates.md   | 52 +++-
 gcc/config/rs6000/rs6000.cc   | 25 ++
 gcc/config/rs6000/rs6000.h|  4 +
 gcc/config/rs6000/rs6000.md   | 96 ---
 gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 ++
 6 files changed, 197 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 277a30a82458..4d8d21fd6bbb 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,6 +222,16 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
+(define_constraint "eU"
+  "@internal integer constant that can be loaded with paddis"
+  (and (match_code "const_int")
+   (match_operand 0 "paddis_operand")))
+
+(define_constraint "eV"
+  "@internal integer constant that can be loaded with paddis + paddi"
+  (and (match_code "const_int")
+   (match_operand 0 "paddis_paddi_operand")))
+
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b325000690b5..0b7c0bf4b0f0 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,6 +369,53 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
+;; Return 1 if op is a 64-bit constant that uses the paddis instruction
+(define_predicate "paddis_operand"
+  (match_code "const_int")
+{
+  if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+  /* If addi, addis, or paddi can handle the number, don't return true.  */
+  HOST_WIDE_INT value = INTVAL (op);
+  if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+  /* If the number is too large for padds, return false.  */
+  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
+  if ((value & HOST_WIDE_INT_C(0x)) != 0)
+return false;
+
+  return true;
+})
+
+;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
+;; addi/addis/paddi instruction combination.
+(define_predicate "paddis_paddi_operand"
+  (match_code "const_int")
+{
+  if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+  /* If addi, addis, or paddi can handle the number, don't return true.  */
+  HOST_WIDE_INT value = INTVAL (op);
+  if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+  /* If the number is too large for padds, return false.  */
+  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
+  if ((value & HOST_WIDE_INT_C(0x)) == 0)
+return false;
+
+  return true;
+})
+
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1050,7 +1097,10 @@
   (if_then_else (match_code "const_int")
 (match_test "satisfies_constraint_I (op)
 || satisfies_constraint_L (op)
-|| satisfies_constraint_eI (op)")
+|| satisfies_constraint_eI (op)
+|| satisfies_constraint_eU (op)
+|| satisfies_constraint_eV (op)")
+
 (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a9501e2cefa1..c903e364628c 100644
--- a/gcc/conf

[gcc r14-10564] sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR116189]

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:ba45573c8072f06f67af22a2ca60da5f5c12beae

commit r14-10564-gba45573c8072f06f67af22a2ca60da5f5c12beae
Author: Andrew Pinski 
Date:   Sat Aug 3 09:30:57 2024 -0700

sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR116189]

This was an interesting compare debug failure to debug. The first symptom
was in gcse which would produce different order of creating 
psedu-registers. This
was caused by a different order of a hashtable walk, due to the hash table 
having different
number of entries. Which in turn was due to the number of max insn being 
different between
the 2 runs. The place max insn uid comes from was in sh_recog_treg_set_expr 
which is called
via rtx_costs and fwprop would cause rtx_costs in some cases for debug insn 
related stuff.

Build and tested for sh4-linux-gnu.

PR target/116189

gcc/ChangeLog:

* config/sh/sh.cc (sh_recog_treg_set_expr): Don't call 
make_insn_raw,
make the insn with a fake uid.

gcc/testsuite/ChangeLog:

* c-c++-common/torture/pr116189-1.c: New test.

Signed-off-by: Andrew Pinski 
(cherry picked from commit 0355c943b9e954e8f59068971d934f1b91ecb729)

Diff:
---
 gcc/config/sh/sh.cc | 12 +-
 gcc/testsuite/c-c++-common/torture/pr116189-1.c | 30 +
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index ef3c2e6791d7..d6a6e5bd88df 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -12279,7 +12279,17 @@ sh_recog_treg_set_expr (rtx op, machine_mode mode)
  have to capture its current state and restore it afterwards.  */
   recog_data_d prev_recog_data = recog_data;
 
-  rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op));
+  /* Note we can't use insn_raw here since that increases the uid
+ and could cause debug compare differences; this insn never leaves
+ this function so create a dummy one. */
+  rtx_insn* i = as_a  (rtx_alloc (INSN));
+
+  INSN_UID (i) = 1;
+  PATTERN (i) = gen_rtx_SET (get_t_reg_rtx (), op);
+  INSN_CODE (i) = -1;
+  REG_NOTES (i) = NULL;
+  INSN_LOCATION (i) = curr_insn_location ();
+  BLOCK_FOR_INSN (i) = NULL;
   SET_PREV_INSN (i) = NULL;
   SET_NEXT_INSN (i) = NULL;
 
diff --git a/gcc/testsuite/c-c++-common/torture/pr116189-1.c 
b/gcc/testsuite/c-c++-common/torture/pr116189-1.c
new file mode 100644
index ..055c563f43e5
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/torture/pr116189-1.c
@@ -0,0 +1,30 @@
+/* { dg-additional-options "-fcompare-debug" } */
+
+/* PR target/116189 */
+
+/* In the sh backend, we used to create insn in the path of rtx_costs.
+   This means sometimes the max uid for insns would be different between
+   debugging and non debugging which then would cause gcse's hashtable
+   to have different number of slots which would cause a different walk
+   for that hash table.  */
+
+extern void ff(void);
+extern short nn[8][4];
+typedef unsigned short move_table[4];
+extern signed long long ira_overall_cost;
+extern signed long long ira_load_cost;
+extern move_table *x_ira_register_move_cost[1];
+struct move { struct move *next; };
+unsigned short t;
+void emit_move_list(struct move * list, int freq, unsigned char mode, int 
regno) {
+  int cost;
+  for (; list != 0; list = list->next)
+  {
+ff();
+unsigned short aclass = t;
+cost = (nn)[mode][aclass] ;
+ira_load_cost = cost;
+cost = x_ira_register_move_cost[mode][aclass][aclass] * freq ;
+ira_overall_cost = cost;
+  }
+}

[gcc r13-8962] sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR116189]

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:73064a28689fe3799f4fb5f1bab7634df889a43e

commit r13-8962-g73064a28689fe3799f4fb5f1bab7634df889a43e
Author: Andrew Pinski 
Date:   Sat Aug 3 09:30:57 2024 -0700

sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR116189]

This was an interesting compare debug failure to debug. The first symptom
was in gcse which would produce different order of creating 
psedu-registers. This
was caused by a different order of a hashtable walk, due to the hash table 
having different
number of entries. Which in turn was due to the number of max insn being 
different between
the 2 runs. The place max insn uid comes from was in sh_recog_treg_set_expr 
which is called
via rtx_costs and fwprop would cause rtx_costs in some cases for debug insn 
related stuff.

Build and tested for sh4-linux-gnu.

PR target/116189

gcc/ChangeLog:

* config/sh/sh.cc (sh_recog_treg_set_expr): Don't call 
make_insn_raw,
make the insn with a fake uid.

gcc/testsuite/ChangeLog:

* c-c++-common/torture/pr116189-1.c: New test.

Signed-off-by: Andrew Pinski 
(cherry picked from commit 0355c943b9e954e8f59068971d934f1b91ecb729)

Diff:
---
 gcc/config/sh/sh.cc | 12 +-
 gcc/testsuite/c-c++-common/torture/pr116189-1.c | 30 +
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index 8ac20dfaa382..717123af6554 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -12279,7 +12279,17 @@ sh_recog_treg_set_expr (rtx op, machine_mode mode)
  have to capture its current state and restore it afterwards.  */
   recog_data_d prev_recog_data = recog_data;
 
-  rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op));
+  /* Note we can't use insn_raw here since that increases the uid
+ and could cause debug compare differences; this insn never leaves
+ this function so create a dummy one. */
+  rtx_insn* i = as_a  (rtx_alloc (INSN));
+
+  INSN_UID (i) = 1;
+  PATTERN (i) = gen_rtx_SET (get_t_reg_rtx (), op);
+  INSN_CODE (i) = -1;
+  REG_NOTES (i) = NULL;
+  INSN_LOCATION (i) = curr_insn_location ();
+  BLOCK_FOR_INSN (i) = NULL;
   SET_PREV_INSN (i) = NULL;
   SET_NEXT_INSN (i) = NULL;
 
diff --git a/gcc/testsuite/c-c++-common/torture/pr116189-1.c 
b/gcc/testsuite/c-c++-common/torture/pr116189-1.c
new file mode 100644
index ..055c563f43e5
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/torture/pr116189-1.c
@@ -0,0 +1,30 @@
+/* { dg-additional-options "-fcompare-debug" } */
+
+/* PR target/116189 */
+
+/* In the sh backend, we used to create insn in the path of rtx_costs.
+   This means sometimes the max uid for insns would be different between
+   debugging and non debugging which then would cause gcse's hashtable
+   to have different number of slots which would cause a different walk
+   for that hash table.  */
+
+extern void ff(void);
+extern short nn[8][4];
+typedef unsigned short move_table[4];
+extern signed long long ira_overall_cost;
+extern signed long long ira_load_cost;
+extern move_table *x_ira_register_move_cost[1];
+struct move { struct move *next; };
+unsigned short t;
+void emit_move_list(struct move * list, int freq, unsigned char mode, int 
regno) {
+  int cost;
+  for (; list != 0; list = list->next)
+  {
+ff();
+unsigned short aclass = t;
+cost = (nn)[mode][aclass] ;
+ira_load_cost = cost;
+cost = x_ira_register_move_cost[mode][aclass][aclass] * freq ;
+ira_overall_cost = cost;
+  }
+}

[gcc r12-10660] sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR116189]

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:dfacc021c9775b1563c717cf3f8114d0f874b030

commit r12-10660-gdfacc021c9775b1563c717cf3f8114d0f874b030
Author: Andrew Pinski 
Date:   Sat Aug 3 09:30:57 2024 -0700

sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR116189]

This was an interesting compare debug failure to debug. The first symptom
was in gcse which would produce different order of creating 
psedu-registers. This
was caused by a different order of a hashtable walk, due to the hash table 
having different
number of entries. Which in turn was due to the number of max insn being 
different between
the 2 runs. The place max insn uid comes from was in sh_recog_treg_set_expr 
which is called
via rtx_costs and fwprop would cause rtx_costs in some cases for debug insn 
related stuff.

Build and tested for sh4-linux-gnu.

PR target/116189

gcc/ChangeLog:

* config/sh/sh.cc (sh_recog_treg_set_expr): Don't call 
make_insn_raw,
make the insn with a fake uid.

gcc/testsuite/ChangeLog:

* c-c++-common/torture/pr116189-1.c: New test.

Signed-off-by: Andrew Pinski 
(cherry picked from commit 0355c943b9e954e8f59068971d934f1b91ecb729)

Diff:
---
 gcc/config/sh/sh.cc | 12 +-
 gcc/testsuite/c-c++-common/torture/pr116189-1.c | 30 +
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index 494e4536251d..5455c3fddaaf 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -12278,7 +12278,17 @@ sh_recog_treg_set_expr (rtx op, machine_mode mode)
  have to capture its current state and restore it afterwards.  */
   recog_data_d prev_recog_data = recog_data;
 
-  rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op));
+  /* Note we can't use insn_raw here since that increases the uid
+ and could cause debug compare differences; this insn never leaves
+ this function so create a dummy one. */
+  rtx_insn* i = as_a  (rtx_alloc (INSN));
+
+  INSN_UID (i) = 1;
+  PATTERN (i) = gen_rtx_SET (get_t_reg_rtx (), op);
+  INSN_CODE (i) = -1;
+  REG_NOTES (i) = NULL;
+  INSN_LOCATION (i) = curr_insn_location ();
+  BLOCK_FOR_INSN (i) = NULL;
   SET_PREV_INSN (i) = NULL;
   SET_NEXT_INSN (i) = NULL;
 
diff --git a/gcc/testsuite/c-c++-common/torture/pr116189-1.c 
b/gcc/testsuite/c-c++-common/torture/pr116189-1.c
new file mode 100644
index ..055c563f43e5
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/torture/pr116189-1.c
@@ -0,0 +1,30 @@
+/* { dg-additional-options "-fcompare-debug" } */
+
+/* PR target/116189 */
+
+/* In the sh backend, we used to create insn in the path of rtx_costs.
+   This means sometimes the max uid for insns would be different between
+   debugging and non debugging which then would cause gcse's hashtable
+   to have different number of slots which would cause a different walk
+   for that hash table.  */
+
+extern void ff(void);
+extern short nn[8][4];
+typedef unsigned short move_table[4];
+extern signed long long ira_overall_cost;
+extern signed long long ira_load_cost;
+extern move_table *x_ira_register_move_cost[1];
+struct move { struct move *next; };
+unsigned short t;
+void emit_move_list(struct move * list, int freq, unsigned char mode, int 
regno) {
+  int cost;
+  for (; list != 0; list = list->next)
+  {
+ff();
+unsigned short aclass = t;
+cost = (nn)[mode][aclass] ;
+ira_load_cost = cost;
+cost = x_ira_register_move_cost[mode][aclass][aclass] * freq ;
+ira_overall_cost = cost;
+  }
+}

[gcc(refs/users/meissner/heads/work175-dmf)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1bfb2eb17853bb877efc93804add17dc5dc4d15d

commit 1bfb2eb17853bb877efc93804add17dc5dc4d15d
Author: Michael Meissner 
Date:   Mon Aug 5 22:43:48 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.dmf | 449 +-
 1 file changed, 448 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
index d3f1cc6620a5..05c3847d0191 100644
--- a/gcc/ChangeLog.dmf
+++ b/gcc/ChangeLog.dmf
@@ -1,6 +1,453 @@
+ Branch work175-dmf, patch #113 
+
+RFC2677-Add xvrlw support.
+
+2024-08-05  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/altivec.md (xvrlw): New insn.
+   * config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/vector-rotate-left.c: New test.
+
+ Branch work175-dmf, patch #112 
+
+RFC2686-Add paddis support.
+
+2024-08-05  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/constraints.md (eU): New constraint.
+   (eV): Likewise.
+   * config/rs6000/predicates.md (paddis_operand): New predicate.
+   (paddis_paddi_operand): Likewise.
+   (add_operand): Add paddis support.
+   * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support.
+   (num_insns_constant_multi): Likewise.
+   (print_operand): Add %B for paddis support.
+   * config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
+   (SIGNED_INTEGER_32BIT_P): Likewise.
+   * config/rs6000/rs6000.md (isa attribute): Add paddis support.
+   (enabled attribute); Likewise.
+   (add3): Likewise.
+   (adddi3 splitter): New splitter for paddis.
+   (movdi_internal64): Add paddis support.
+   (movdi splitter): New splitter for paddis.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/prefixed-addis.c: New test.
+
+ Branch work175-dmf, patch #111 
+
+RFC2655-Add saturating subtract built-ins.
+
+This patch adds support for a saturating subtract built-in function that may be
+added to a future PowerPC processor.  Note, if it is added, the name of the
+built-in function may change before GCC 13 is released.  If the name changes,
+we will submit a patch changing the name.
+
+I also added support for providing dense math built-in functions, even though
+at present, we have not added any new built-in functions for dense math.  It is
+likely we will want to add new dense math built-in functions as the dense math
+support is fleshed out.
+
+The patches have been tested on both little and big endian systems.  Can I 
check
+it into the master branch?
+
+2024-08-05   Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support
+   for flagging invalid use of future built-in functions.
+   (rs6000_builtin_is_supported): Add support for future built-in
+   functions.
+   * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New
+   built-in function for -mcpu=future.
+   (__builtin_saturate_subtract64): Likewise.
+   * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas
+   for -mcpu=future built-ins.
+   (stanza_map): Likewise.
+   (enable_string): Likewise.
+   (struct attrinfo): Likewise.
+   (parse_bif_attrs): Likewise.
+   (write_decls): Likewise.
+   * config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
+   built-in insn declarations.
+   (sat_sub3_dot): Likewise.
+   (sat_sub3_dot2): Likewise.
+   * doc/extend.texi (Future PowerPC built-ins): New section.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/subfus-1.c: New test.
+   * gcc.target/powerpc/subfus-2.c: Likewise.
+
+ Branch work175-dmf, patch #110 
+
+RFC2656-Support load/store vector with right length.
+
+This patch adds support for new instructions that may be added to the PowerPC
+architecture in the future to enhance the load and store vector with length
+instructions.
+
+The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use
+since the count for the number of bytes must be in the top 8 bits of the GPR
+register, instead of the bottom 8 bits.  This meant that code generating these
+instructions typically had to do a shift left by 56 bits to get the count into
+the right position.  In a future version of the PowerPC architecture, new
+variants of these instructions might be added that expect the count to be in
+the bottom 8 bits of the GPR register.  These patches add this support to GCC
+if the user uses the -mcpu=future option.
+
+I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl
+future lxvll/stxvll instructions would generate these instructions on 32-bit.
+However the patterns for these instructions is only done on 64-bit systems.  So
+I added a check for 64-bit support before generating the instructions.
+
+The patches

[gcc r15-2737] vect: Allow unsigned-to-signed promotion in vect_look_through_possible_promotion [PR115707]

[Feng Xue via Gcc-cvs]

https://gcc.gnu.org/g:3c089ee5d5a86cab0b27c69b96c4354c496520ac

commit r15-2737-g3c089ee5d5a86cab0b27c69b96c4354c496520ac
Author: Feng Xue 
Date:   Mon Aug 5 15:23:56 2024 +0800

vect: Allow unsigned-to-signed promotion in 
vect_look_through_possible_promotion [PR115707]

The function fails to figure out root definition if casts involves more than
two promotions with sign change as:

long a = (long)b;   // promotion cast
 -> int b = (int)c; // promotion cast, sign change
   -> unsigned short c = ...;

For this case, the function thinks the 2nd cast has different sign as the 
1st,
so stop looking through, while "unsigned short -> integer" is a nature sign
extension.

2024-08-05 Feng Xue 

gcc/
PR tree-optimization/115707
* tree-vect-patterns.cc (vect_look_through_possible_promotion): 
Allow
unsigned-to-signed promotion.

Diff:
---
 gcc/tree-vect-patterns.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc
index 4674a16d15f4..b2c83cfd2190 100644
--- a/gcc/tree-vect-patterns.cc
+++ b/gcc/tree-vect-patterns.cc
@@ -434,7 +434,9 @@ vect_look_through_possible_promotion (vec_info *vinfo, tree 
op,
 sign of the previous promotion.  */
  if (!res
  || TYPE_PRECISION (unprom->type) == orig_precision
- || TYPE_SIGN (unprom->type) == TYPE_SIGN (op_type))
+ || TYPE_SIGN (unprom->type) == TYPE_SIGN (op_type)
+ || (TYPE_UNSIGNED (op_type)
+ && TYPE_PRECISION (op_type) < TYPE_PRECISION (unprom->type)))
{
  unprom->set_op (op, dt, caster);
  min_precision = TYPE_PRECISION (op_type);

[gcc r15-2738] vect: Add missed opcodes in vect_get_smallest_scalar_type [PR115228]

[Feng Xue via Gcc-cvs]

https://gcc.gnu.org/g:95990db02b86282249396b06f65f4f9f582bab42

commit r15-2738-g95990db02b86282249396b06f65f4f9f582bab42
Author: Feng Xue 
Date:   Mon Aug 5 15:53:19 2024 +0800

vect: Add missed opcodes in vect_get_smallest_scalar_type [PR115228]

Some opcodes are missed when determining the smallest scalar type for a
vectorizable statement. Currently, this bug does not cause any problem,
because vect_get_smallest_scalar_type is only used to compute max nunits
vectype, and even statement with missed opcode is incorrectly bypassed,
the max nunits vectype could also be rightly deduced from def statements
for operands of the statement.

In the future, if this function will be called to do other thing, we may
get something wrong. So fix it in this patch.

2024-08-05 Feng Xue 

gcc/
PR tree-optimization/115228
* tree-vect-data-refs.cc (vect_get_smallest_scalar_type): Add
missed opcodes that involve widening operation.

Diff:
---
 gcc/tree-vect-data-refs.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc
index 39fd887a96ba..5b0d548f8479 100644
--- a/gcc/tree-vect-data-refs.cc
+++ b/gcc/tree-vect-data-refs.cc
@@ -162,7 +162,10 @@ vect_get_smallest_scalar_type (stmt_vec_info stmt_info, 
tree scalar_type)
   if (gimple_assign_cast_p (assign)
  || gimple_assign_rhs_code (assign) == DOT_PROD_EXPR
  || gimple_assign_rhs_code (assign) == WIDEN_SUM_EXPR
+ || gimple_assign_rhs_code (assign) == SAD_EXPR
  || gimple_assign_rhs_code (assign) == WIDEN_MULT_EXPR
+ || gimple_assign_rhs_code (assign) == WIDEN_MULT_PLUS_EXPR
+ || gimple_assign_rhs_code (assign) == WIDEN_MULT_MINUS_EXPR
  || gimple_assign_rhs_code (assign) == WIDEN_LSHIFT_EXPR
  || gimple_assign_rhs_code (assign) == FLOAT_EXPR)
{

[gcc r15-2739] Fortran: Fix class transformational intrinsic calls [PR102689]

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:4cb07a38233aadb4b389a6e5236c95f52241b6e0

commit r15-2739-g4cb07a38233aadb4b389a6e5236c95f52241b6e0
Author: Paul Thomas 
Date:   Tue Aug 6 06:42:27 2024 +0100

Fortran: Fix class transformational intrinsic calls [PR102689]

2024-08-06  Paul Thomas  

gcc/fortran
PR fortran/102689
* trans-array.cc (get_array_ref_dim_for_loop_dim): Use the arg1
class container carried in ss->info as the seed for a lhs in
class valued transformational intrinsic calls that are not the
rhs of an assignment. Otherwise, the lhs variable expression is
taken from the loop chain. For this latter case, the _vptr and
_len fields are set.
(gfc_trans_create_temp_array): Use either the lhs expression
seeds to build a class variable that will take the returned
descriptor as its _data field. In the case that the arg1 expr.
is used, a class typespec must be built with the correct rank
and the _vptr and _len fields set. The element size is provided
for the temporary allocation and to set the descriptor span.
(gfc_array_init_size): When an intrinsic type scalar expr3 is
used in allocation of a class array, use its element size in
the descriptor dtype.
* trans-expr.cc (gfc_conv_class_to_class): Class valued
transformational intrinsics return the pointer to the array
descriptor as the _data field of a class temporary. Extract
directly and return the address of the class temporary.
(gfc_conv_procedure_call): store the expression for the first
argument of a class valued transformational intrinsic function
in the ss info class_container field. Later, use its type  as
the element type in the call to gfc_trans_create_temp_array.
(fcncall_realloc_result): Add a dtype argument and use it in
the descriptor, when available.
(gfc_trans_arrayfunc_assign): For class lhs, build a dtype with
the lhs rank and the rhs element size and use it in the call to
fcncall_realloc_result.

gcc/testsuite/
PR fortran/102689
* gfortran.dg/class_transformational_1.f90: New test for class-
valued reshape.
* gfortran.dg/class_transformational_2.f90: New test for other
class_valued transformational intrinsics.

Diff:
---
 gcc/fortran/trans-array.cc | 146 ---
 gcc/fortran/trans-expr.cc  |  57 +-
 .../gfortran.dg/class_transformational_1.f90   | 204 +
 .../gfortran.dg/class_transformational_2.f90   | 103 +++
 4 files changed, 475 insertions(+), 35 deletions(-)

diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index c93a5f1e7543..9fb0b2b398d2 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -1301,23 +1301,28 @@ get_array_ref_dim_for_loop_dim (gfc_ss *ss, int 
loop_dim)
is a class expression.  */
 
 static tree
-get_class_info_from_ss (stmtblock_t * pre, gfc_ss *ss, tree *eltype)
+get_class_info_from_ss (stmtblock_t * pre, gfc_ss *ss, tree *eltype,
+   gfc_ss **fcnss)
 {
+  gfc_ss *loop_ss = ss->loop->ss;
   gfc_ss *lhs_ss;
   gfc_ss *rhs_ss;
+  gfc_ss *fcn_ss = NULL;
   tree tmp;
   tree tmp2;
   tree vptr;
-  tree rhs_class_expr = NULL_TREE;
+  tree class_expr = NULL_TREE;
   tree lhs_class_expr = NULL_TREE;
   bool unlimited_rhs = false;
   bool unlimited_lhs = false;
   bool rhs_function = false;
+  bool unlimited_arg1 = false;
   gfc_symbol *vtab;
+  tree cntnr = NULL_TREE;
 
   /* The second element in the loop chain contains the source for the
- temporary; ie. the rhs of the assignment.  */
-  rhs_ss = ss->loop->ss->loop_chain;
+ class temporary created in gfc_trans_create_temp_array.  */
+  rhs_ss = loop_ss->loop_chain;
 
   if (rhs_ss != gfc_ss_terminator
   && rhs_ss->info
@@ -1326,28 +1331,58 @@ get_class_info_from_ss (stmtblock_t * pre, gfc_ss *ss, 
tree *eltype)
   && rhs_ss->info->data.array.descriptor)
 {
   if (rhs_ss->info->expr->expr_type != EXPR_VARIABLE)
-   rhs_class_expr
+   class_expr
  = gfc_get_class_from_expr (rhs_ss->info->data.array.descriptor);
   else
-   rhs_class_expr = gfc_get_class_from_gfc_expr (rhs_ss->info->expr);
+   class_expr = gfc_get_class_from_gfc_expr (rhs_ss->info->expr);
   unlimited_rhs = UNLIMITED_POLY (rhs_ss->info->expr);
   if (rhs_ss->info->expr->expr_type == EXPR_FUNCTION)
rhs_function = true;
 }
 
+  /* Usually, ss points to the function. When the function call is an actual
+ argument, it is instead rhs_ss because the ss chain is shifted by one.  */
+  *fcnss = fcn_ss = rhs_function ? rhs_ss : ss;
+
+  /* If this is a transformational 

[gcc(refs/users/meissner/heads/work175-tar)] Add support for the TAR register.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b4d74a7e7a00c18289476a0398faccd8414a2498

commit b4d74a7e7a00c18289476a0398faccd8414a2498
Author: Michael Meissner 
Date:   Tue Aug 6 01:47:28 2024 -0400

Add support for the TAR register.

2024-08-05  Michael Meissner  

gcc/

* config/rs6000/constraints.md (h constraint): Add TAR register to 
the
documentation.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add -mtar.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register 
support.
(alt_reg_names): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Restrict SPR registers to only
hold scalar integer modes of an appropriate size.  Add TAR register
support.
(rs6000_debug_reg_global): Print the register class that wt maps 
too.
(rs6000_init_hard_regno_mode_ok): Add TAR register support.
(rs6000_conditional_register_usage): Add TAR register support.
(print_operand): Likewise.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Add support for -mtar.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register
support.
(FIXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(enum reg_class): Likewise.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(enum r6000_reg_class_enum): Add support for the wt constraint.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(call_indirect_nonlocal_sysv): Likewise.
(call_value_indirect_nonlocal_sysv): Likewise.
(call_indirect_aix): Likewise.
(call_value_indirect_aix): Likewise.
(call_indirect_elfv2): Likewise.
(call_indirect_pcrel): Likewise.
(call_value_indirect_elfv2): Likewise.
(call_value_indirect_pcrel): Likewise.
(*sibcall_indirect_nonlocal_sysv): Likewise.
(sibcall_value_indirect_nonlocal_sysv): Likewise.
(indirect_jump): Likewise.
(@indirect_jump_nospec): Likewise.
(@tablejump_insn_normal): Likewise.
(@tablejump_insn_nospec): Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.

gcc/testsuite/

* gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR 
register.
* gcc.target/powerpc/pr51513.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-2.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
* gcc.target/powerpc/tar-register.c: New test.

Diff:
---
 gcc/config/rs6000/constraints.md   |  5 +-
 gcc/config/rs6000/rs6000-cpus.def  |  4 +-
 gcc/config/rs6000/rs6000.cc| 58 +++---
 gcc/config/rs6000/rs6000.h | 31 +++-
 gcc/config/rs6000/rs6000.md| 33 ++--
 gcc/config/rs6000/rs6000.opt   |  4 ++
 gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c|  4 +-
 gcc/testsuite/gcc.target/powerpc/pr51513.c |  4 +-
 .../gcc.target/powerpc/safe-indirect-jump-2.c  |  2 +-
 .../gcc.target/powerpc/safe-indirect-jump-3.c  |  2 +-
 gcc/testsuite/gcc.target/powerpc/tar-register.c| 34 +
 11 files changed, 138 insertions(+), 43 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042d..14f0465d7ae5 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
   "@internal A compatibility alias for @code{wa}.")
 
 (define_register_constraint "h" "SPECIAL_REGS"
-  "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+  "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or 
@code{tar}).")
 
 (define_register_constraint "c" "CTR_REGS"
   "The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
   "@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
 
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+  "The tar register, @code{tar}.")
+
 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
   "@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index e73d9ef51f8d..a7ecd38f8eef 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -64,7 +64,8 @@
  | OPTION_MASK_MODULO  \
  | OPTION_MASK_P9_MINMAX   \
   

[gcc(refs/users/meissner/heads/work175-tar)] Remove SPR alternatives for move insns.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:fa3c1d3f013263bc70f1f25cd1b00e66aba477ac

commit fa3c1d3f013263bc70f1f25cd1b00e66aba477ac
Author: Michael Meissner 
Date:   Tue Aug 6 01:51:32 2024 -0400

Remove SPR alternatives for move insns.

2024-08-05  Michael Meissner  

* config/rs6000/rs6000.md (mov_internal): Remove alternatives 
for
moving values to/from SPR registers.
(movcc_): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov_softfloat): Likewise.
(mov_hardfloat64): Likewise.
(mov_softfloat64): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.md | 114 +---
 1 file changed, 44 insertions(+), 70 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c6d818116f79..077f386ec97d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8064,16 +8064,16 @@
 
 ;; MR  LHZ/LBZLXSI*ZXSTH/STBSTXSI*XLI
 ;; XXLOR   load 0 load -1VSPLTI*#  MFVSRWZ
-;; MTVSRWZ MF%1   MT%1   NOP
+;; MTVSRWZ
 (define_insn "*mov_internal"
   [(set (match_operand:QHI 0 "nonimmediate_operand"
"=r,r, wa,m, ?Z,r,
 wa,wa,wa,v, ?v,r,
-wa,r, *c*l,  *h")
+wa")
(match_operand:QHI 1 "input_operand"
"r, m, ?Z,r, wa,i,
 wa,O, wM,wB,wS,wa,
-r, *h,r, 0"))]
+r"))]
   "gpc_reg_operand (operands[0], mode)
|| gpc_reg_operand (operands[1], mode)"
   "@
@@ -8089,22 +8089,19 @@
vspltis %0,%1
#
mfvsrwz %0,%x1
-   mtvsrwz %x0,%1
-   mf%1 %0
-   mt%0 %1
-   nop"
+   mtvsrwz %x0,%1"
   [(set_attr "type"
"*, load,  fpload,store, fpstore,   *,
 vecsimple, vecperm,   vecperm,   vecperm,   vecperm,   mfvsr,
-mtvsr, mfjmpr,mtjmpr,*")
+mtvsr")
(set_attr "length"
"*, *, *, *, *, *,
 *, *, *, *, 8, *,
-*, *, *, *")
+*")
(set_attr "isa"
"*, *, p9v,   *, p9v,   *,
 p9v,   p9v,   p9v,   p9v,   p9v,   p9v,
-p9v,   *, *, *")])
+p9v")])
 
 
 ;; Here is how to move condition codes around.  When we store CC data in
@@ -8120,9 +8117,9 @@
 
 (define_insn "*movcc_"
   [(set (match_operand:CC_any 0 "nonimmediate_operand"
-   "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
+   "=y,x,?y,y,r,r,r,r,r,m")
(match_operand:CC_any 1 "general_operand"
-   " y,r, r,O,x,y,r,I,*h,   r,m,r"))]
+   " y,r, r,O,x,y,r,I,m,r"))]
   "register_operand (operands[0], mode)
|| register_operand (operands[1], mode)"
   "@
@@ -8134,8 +8131,6 @@
mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf000
mr %0,%1
li %0,%1
-   mf%1 %0
-   mt%0 %1
lwz%U1%X1 %0,%1
stw%U0%X0 %1,%0"
   [(set_attr_alternative "type"
@@ -8149,11 +8144,9 @@
(const_string "mfcrf") (const_string "mfcr"))
   (const_string "integer")
   (const_string "integer")
-  (const_string "mfjmpr")
-  (const_string "mtjmpr")
   (const_string "load")
   (const_string "store")])
-   (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")])
+   (set_attr "length" "*,*,12,*,*,8,*,*,*,*")])
 
 ;; For floating-point, we normally deal with the floating-point registers
 ;; unless -msoft-float is used.  The sole exception is that parameter passing
@@ -8204,17 +8197,17 @@
 ;;
 ;; LWZ  LFSLXSSP   LXSSPX STFS   STXSSP
 ;; STXSSPX  STWXXLXOR  LI FMRXSCPSGNDP
-;; MR   MT  MF   NOPXXSPLTIDP
+;; MR   XXSPLTIDP
 
 (define_insn "movsf_hardfloat"
   [(set (match_operand:SF 0 "nonimmediate_operand"
 "=!r,   f, v,  wa,m, wY,
  Z, m, wa, !r,f, wa,
- !r,*c*l,  !r, *h,wa")
+ !r,wa")
(match_operand:SF 1 "input_operand"
 "m, m, wY, Z, f, v,
  wa,r, j,  j, f, wa,
- r, r, *h, 0, eP"))]
+ r, eP"))]
   "(register_operand (operands[0], SFmode)
|| register_operand (o

[gcc(refs/users/meissner/heads/work175-tar)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:fc985a4688965d55191269fc545e3774280cfc8d

commit fc985a4688965d55191269fc545e3774280cfc8d
Author: Michael Meissner 
Date:   Tue Aug 6 01:55:15 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.tar | 83 ++-
 1 file changed, 82 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
index 3a9f2525f736..74a45043315e 100644
--- a/gcc/ChangeLog.tar
+++ b/gcc/ChangeLog.tar
@@ -1,6 +1,87 @@
+ Branch work175-tar, patch #201 
+
+Remove SPR alternatives for move insns.
+
+2024-07-03  Michael Meissner  
+
+   * config/rs6000/rs6000.md (mov_internal): Remove alternatives for
+   moving values to/from SPR registers.
+   (movcc_): Likewise.
+   (movsf_hardfloat): Likewise.
+   (movsd_hardfloat): Likewise.
+   (mov_softfloat): Likewise.
+   (mov_hardfloat64): Likewise.
+   (mov_softfloat64): Likewise.
+
+ Branch work175-tar, patch #201 
+
+Add support for the TAR register.
+
+2024-07-03  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/constraints.md (h constraint): Add TAR register to the
+   documentation.
+   (wt constraint): New constraint.
+   * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add -mtar.
+   (POWERPC_MASKS): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register support.
+   (alt_reg_names): Likewise.
+   (rs6000_hard_regno_mode_ok_uncached): Restrict SPR registers to only
+   hold scalar integer modes of an appropriate size.  Add TAR register
+   support.
+   (rs6000_debug_reg_global): Print the register class that wt maps too.
+   (rs6000_init_hard_regno_mode_ok): Add TAR register support.
+   (rs6000_conditional_register_usage): Add TAR register support.
+   (print_operand): Likewise.
+   (rs6000_debugger_regno): Likewise.
+   (rs6000_opt_masks): Add support for -mtar.
+   * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register
+   support.
+   (FIXED_REGISTERS): Likewise.
+   (CALL_REALLY_USED_REGISTERS): Likewise.
+   (REG_ALLOC_ORDER): Likewise.
+   (enum reg_class): Likewise.
+   (REG_CLASS_NAMES): Likewise.
+   (REG_CLASS_CONTENTS): Likewise.
+   (enum r6000_reg_class_enum): Add support for the wt constraint.
+   * config/rs6000/rs6000.md (TAR_REGNO): New constant.
+   (call_indirect_nonlocal_sysv): Likewise.
+   (call_value_indirect_nonlocal_sysv): Likewise.
+   (call_indirect_aix): Likewise.
+   (call_value_indirect_aix): Likewise.
+   (call_indirect_elfv2): Likewise.
+   (call_indirect_pcrel): Likewise.
+   (call_value_indirect_elfv2): Likewise.
+   (call_value_indirect_pcrel): Likewise.
+   (*sibcall_indirect_nonlocal_sysv): Likewise.
+   (sibcall_value_indirect_nonlocal_sysv): Likewise.
+   (indirect_jump): Likewise.
+   (@indirect_jump_nospec): Likewise.
+   (@tablejump_insn_normal): Likewise.
+   (@tablejump_insn_nospec): Likewise.
+   * config/rs6000/rs6000.opt (-mtar): New option.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR register.
+   * gcc.target/powerpc/pr51513.c: Likewise.
+   * gcc.target/powerpc/safe-indirect-jump-2.c: Likewise.
+   * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
+   * gcc.target/powerpc/tar-register.c: New test.
+
  Branch work175-tar, baseline 
 
+Add ChangeLog.tar and update REVISION.
+
+2024-06-28  Michael Meissner  
+
+gcc/
+
+   * ChangeLog.tar: New file for branch.
+   * REVISION: Update.
+
 2024-08-01   Michael Meissner  
 
Clone branch
-

[gcc(refs/users/meissner/heads/work175-bugs)] Do not build IEEE 128-bit libstdc++ support if VSX is not available.

[Michael Meissner via Libstdc++-cvs]

https://gcc.gnu.org/g:ad50dbd3b580d8554058e3b3e360cff44bb22ce7

commit ad50dbd3b580d8554058e3b3e360cff44bb22ce7
Author: Michael Meissner 
Date:   Tue Aug 6 02:01:52 2024 -0400

Do not build IEEE 128-bit libstdc++ support if VSX is not available.

If you build a little endian compiler and select a default CPU of power5
(i.e. --with-cpu=power5), GCC cannot be built.  The reason is that both the
libgfortran and libstdc++-v3 libraries assume that all little endian powerpc
builds support IEEE 128-bit floating point.

However, if the default cpu does not support the VSX instruction set, then 
we
cannot build the IEEE 128-bit libraries.  This patch fixes the libstdc++-v3
library so if the GCC compiler does not support IEEE 128-bit floating 
point, the
IEEE 128-bit floating point libraries are not built.  A companion patch 
will fix
the libgfortran library.

I have built these patches on a little endian system, doing both normal 
builds,
and making a build with a power5 default.  There was no regression in the 
normal
builds.  I have also built a big endian GCC compiler and there was no 
regression
there.  Can I check this patch into the trunk?

2024-08-06  Michael Meissner  

libstdc++-v3/

PR target/115800
* configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on 
PowerPC
systems without VSX.
* configure: Regenerate.
* numeric_traits.h: Don't enable IEEE 128-bit on PowerPC systems 
without
VSX.

Diff:
---
 libstdc++-v3/configure| 68 ++-
 libstdc++-v3/configure.ac | 58 --
 libstdc++-v3/include/ext/numeric_traits.h |  2 +-
 3 files changed, 86 insertions(+), 42 deletions(-)

diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure
index fe525308ae28..b633df7f621f 100755
--- a/libstdc++-v3/configure
+++ b/libstdc++-v3/configure
@@ -51355,8 +51355,31 @@ $as_echo "#define _GLIBCXX_LONG_DOUBLE_COMPAT 1" 
>>confdefs.h
 case "$target" in
   powerpc*-*-linux*)
LONG_DOUBLE_COMPAT_FLAGS="$LONG_DOUBLE_COMPAT_FLAGS -mno-gnu-attribute"
-# Check for IEEE128 support in libm:
-{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for __frexpieee128 
in -lm" >&5
+   # Eliminate little endian systems without VSX
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+ #ifndef __VSX__
+ #error "IEEE 128-bit needs VSX"
+ #endif
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_ieee128_possible=yes
+else
+  ac_ieee128_possible=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+   if test $ac_ieee128_possible = yes; then
+  # Check for IEEE128 support in libm:
+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for __frexpieee128 
in -lm" >&5
 $as_echo_n "checking for __frexpieee128 in -lm... " >&6; }
 if ${ac_cv_lib_m___frexpieee128+:} false; then :
   $as_echo_n "(cached) " >&6
@@ -51401,18 +51424,18 @@ else
   ac_ldbl_ieee128_in_libc=no
 fi
 
-if test $ac_ldbl_ieee128_in_libc = yes; then
-  # Determine which long double format is the compiler's default:
-  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+  if test $ac_ldbl_ieee128_in_libc = yes; then
+# Determine which long double format is the compiler's default:
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
 int
 main ()
 {
 
-#ifndef __LONG_DOUBLE_IEEE128__
-#error compiler defaults to ibm128
-#endif
+  #ifndef __LONG_DOUBLE_IEEE128__
+  #error compiler defaults to ibm128
+  #endif
 
   ;
   return 0;
@@ -51424,21 +51447,28 @@ else
   ac_ldbl_ieee128_default=no
 fi
 rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
-  # Library objects should use default long double format.
-  if test "$ac_ldbl_ieee128_default" = yes; then
-LONG_DOUBLE_128_FLAGS="-mno-gnu-attribute"
-# Except for the ones that explicitly use these flags:
-LONG_DOUBLE_ALT128_COMPAT_FLAGS="-mabi=ibmlongdouble 
-mno-gnu-attribute -Wno-psabi"
-  else
-LONG_DOUBLE_128_FLAGS="-mno-gnu-attribute"
-LONG_DOUBLE_ALT128_COMPAT_FLAGS="-mabi=ieeelongdouble 
-mno-gnu-attribute -Wno-psabi"
-  fi
+# Library objects should use default long double format.
+if test "$ac_ldbl_ieee128_default" = yes; then
+  LONG_DOUBLE_128_FLAGS="-mno-gnu-attribute"
+  # Except for the ones that explicitly use these flags:
+  LONG_DOUBLE_ALT128_COMPAT_FLAGS="-mabi=ibmlongdouble 
-mno-gnu-attribute -Wno-psabi"
+else
+  LONG_DOUBLE_128_FLAGS="-mno-gnu-attribute"
+  LONG_DOUBLE_ALT128_COMPAT_

[gcc(refs/users/meissner/heads/work175-bugs)] Do not build IEEE 128-bit libgfortran support if VSX is not available.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7f81c7653be6f53a7025f2ec08fd2475503d6abc

commit 7f81c7653be6f53a7025f2ec08fd2475503d6abc
Author: Michael Meissner 
Date:   Tue Aug 6 01:58:42 2024 -0400

Do not build IEEE 128-bit libgfortran support if VSX is not available.

If you build a little endian compiler and select a default CPU of power5
(i.e. --with-cpu=power5), GCC cannot be built.  The reason is that both the
libgfortran and libstdc++-v3 libraries assume that all little endian powerpc
builds support IEEE 128-bit floating point.

However, if the default cpu does not support the VSX instruction set, then 
we
cannot build the IEEE 128-bit libraries.  This patch fixes the libgfortran
library so if the GCC compiler does not support IEEE 128-bit floating 
point, the
IEEE 128-bit floating point libraries are not built.  A companion patch 
will fix
the libstdc++-v3 library.

I have built these patches on a little endian system, doing both normal 
builds,
and making a build with a power5 default.  There was no regression in the 
normal
builds.  I have also built a big endian GCC compiler and there was no 
regression
there.  Can I check this patch into the trunk?

2024-08-06  Michael Meissner  

libgfortran/

PR target/115800
* configure.ac (powerpc64le*-linux*): Check to see that the compiler
uses VSX before enabling IEEE 128-bit support.
* configure: Regenerate.
* kinds-override.h (GFC_REAL_17): Add check for __VSX__.
* libgfortran.h (POWER_IEEE128): Likewise.

Diff:
---
 libgfortran/configure| 7 +--
 libgfortran/configure.ac | 3 +++
 libgfortran/kinds-override.h | 2 +-
 libgfortran/libgfortran.h| 2 +-
 4 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/libgfortran/configure b/libgfortran/configure
index 11a1bc5f0708..2708e5c7eca4 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -5981,6 +5981,9 @@ if test "x$GCC" = "xyes"; then
 #if __SIZEOF_LONG_DOUBLE__ != 16
   #error long double is double
   #endif
+  #if !defined(__VSX__)
+  #error VSX is not available
+  #endif
 int
 main ()
 {
@@ -12847,7 +12850,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12850 "configure"
+#line 12853 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -12953,7 +12956,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12956 "configure"
+#line 12959 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index cca1ea0ea970..cfaeb9717ab8 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -148,6 +148,9 @@ if test "x$GCC" = "xyes"; then
   AC_PREPROC_IFELSE(
 [AC_LANG_PROGRAM([[#if __SIZEOF_LONG_DOUBLE__ != 16
   #error long double is double
+  #endif
+  #if !defined(__VSX__)
+  #error VSX is not available
   #endif]],
  [[(void) 0;]])],
 [AM_FCFLAGS="$AM_FCFLAGS -mabi=ibmlongdouble -mno-gnu-attribute";
diff --git a/libgfortran/kinds-override.h b/libgfortran/kinds-override.h
index f6b4956c5caa..51f440e53232 100644
--- a/libgfortran/kinds-override.h
+++ b/libgfortran/kinds-override.h
@@ -30,7 +30,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If 
not, see
 #endif
 
 /* Keep these conditions on one line so grep can filter it out.  */
-#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16
+#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16 && defined(__VSX__)
 typedef _Float128 GFC_REAL_17;
 typedef _Complex _Float128 GFC_COMPLEX_17;
 #define HAVE_GFC_REAL_17
diff --git a/libgfortran/libgfortran.h b/libgfortran/libgfortran.h
index effa3732c185..70db350ba01c 100644
--- a/libgfortran/libgfortran.h
+++ b/libgfortran/libgfortran.h
@@ -104,7 +104,7 @@ typedef off_t gfc_offset;
 #endif
 
 #if defined(__powerpc64__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ \
-&& defined __GLIBC_PREREQ
+&& defined __GLIBC_PREREQ && defined(__VSX__)
 #if __GLIBC_PREREQ (2, 32)
 #define POWER_IEEE128 1
 #endif

[gcc(refs/users/meissner/heads/work175-bugs)] Do not add -mvsx when testing the float128 support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c5dfd77e08784499ba15b55ad8d482ba2faa3d72

commit c5dfd77e08784499ba15b55ad8d482ba2faa3d72
Author: Michael Meissner 
Date:   Tue Aug 6 02:05:21 2024 -0400

Do not add -mvsx when testing the float128 support.

Currently, we add -mvsx when building the float128 support in libgcc.  This
allows us to build the float128 support on a big endian system where the
default cpu is power4.  While the libgcc support can be built, given there 
is
no glibc support for float128 available.

However, adding -mvsx and building the libgcc float128 support causes 
problems
if you set the default cpu to something like a 7540, which does not have VSX
support.  The assembler complains that when the code does a ".machine 
7450", you
cannot use VSX instructions.

After patching libgcc to not build the float128 support unless the host can
support float128 normally, this patch changes the GCC tests so that it will 
only
do the IEEE 128-bit tests if the default compiler enables the VSX 
instruction
set by default.  Otherwise all of the float128 tests will fail because the
libgcc support is not available.

In addition to not doing the float128 tests when the compiler does not 
natively
support float128, this patch also removes adding -mvsx, -mfloat128, and
-mfloat128-hardware enable the support if the compiler did not natively 
enable
it.

I built little endian compilers and there were no regressions.

I built big endian compilers with the --with-cpu=power5 configure option, 
and I
verified that none of the float128 support functions are built.

I also built big endian compilers on a power9 with the --with-cpu=native
configure option, and I verified that the float128 support functions were
built, since the default compiler used the VSX instruction set.

I verified that on both sets of big endian builds, that all of the float128
tests were skipped, since there is no support for float128 in glibc and the 
GCC
compiler does not enable float128 on those systems.

Can I check these patches into the trunk assuming the original bugzilla 
author
says they fix the problem?

2024-08-06 Michael Meissner  

gcc/testsuite/

PR target/115800
PR target/113652
* gcc.target/powerpc/abs128-1.c: Remove adding -mvsx, -mfloat128, 
and
-mfloat128-hardware options to float128 test.  Add explicit checks 
for
the float128 support, rather than just using VSX as a stand in, or
assuming we can silently enable VSX if the default is power4.  For
pr99708.c, also use the correct spelling to disable the float128 
tests.
* gcc.target/powerpc/bfp/scalar-insert-exp-16.c: Likewise.
* gcc.target/powerpc/copysign128-1.c: Likewise.
* gcc.target/powerpc/divkc3-1.c: Likewise.
* gcc.target/powerpc/float128-3.c: Likewise.
* gcc.target/powerpc/float128-5.c: Likewise.
* gcc.target/powerpc/float128-complex-2.: Likewise.
* gcc.target/powerpc/float128-math.: Likewise.
* gcc.target/powerpc/inf128-1.: Likewise.
* gcc.target/powerpc/mulkc3-1.c: Likewise.
* gcc.target/powerpc/nan128-1.c: Likewise.
* gcc.target/powerpc/p9-lxvx-stxvx-3.: Likewise.
* gcc.target/powerpc/pr104253.: Likewise.
* gcc.target/powerpc/pr70669.c: Likewise.
* gcc.target/powerpc/pr79004.c: Likewise.
* gcc.target/powerpc/pr79038-1.c: Likewise.
* gcc.target/powerpc/pr81959.c: Likewise.
* gcc.target/powerpc/pr85657-1.: Likewise.
* gcc.target/powerpc/pr85657-2.c: Likewise.
* gcc.target/powerpc/pr99708.: Likewise.
* gcc.target/powerpc/signbit-1.c: Likewise.
* gcc.target/powerpc/signbit-2.c: Likewise.
* lib/target-supports.exp (check_ppc_float128_sw_available): 
Likewise.
(check_ppc_float128_hw_available): Likewise.
(check_effective_target_ppc_ieee128_ok): Likewise.
(add_options_for___float128): Likewise.
(check_effective_target___float128): Likewise.
(check_effective_target_base_quadfloat_support): Likewise.
(check_effective_target_powerpc_float128_sw_ok): Likewise.
(check_effective_target_powerpc_float128_hw_ok): Likewise.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/abs128-1.c|  3 ++-
 .../gcc.target/powerpc/bfp/scalar-insert-exp-16.c  |  1 +
 gcc/testsuite/gcc.target/powerpc/copysign128-1.c   |  3 ++-
 gcc/testsuite/gcc.target/powerpc/divkc3-1.c|  3 ++-
 gcc/testsuite/gcc.target/powerpc/float128-3.c  |  3 ++-
 gcc/testsuite/gcc.target/powerpc/float128-5.c  |  3 ++-
 .../gcc.target/powerpc/float128-complex-2.c|  2 +-
 gcc/testsuite/gcc.target/powerpc/float128-math.c   |  2 +-

[gcc(refs/users/meissner/heads/work175-bugs)] Do not add -mvsx when building libgcc float128 support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8b61a6e2de37a865dc2048c8e55c87704f20505d

commit 8b61a6e2de37a865dc2048c8e55c87704f20505d
Author: Michael Meissner 
Date:   Tue Aug 6 02:03:18 2024 -0400

Do not add -mvsx when building libgcc float128 support.

Currently, we add -mvsx when building the float128 support in libgcc.  This
allows us to build the float128 support on a big endian system where the
default cpu is power4.  While the libgcc support can be built, given there 
is
no glibc support for float128 available.

In the past, we would add -mvsx when building the float128 support in 
libgcc.
This allowed us to build the float128 support on a big endian system where 
the
default cpu is power4.  While the libgcc support can be built, given there 
is no
glibc support for float128 available.

However, adding -mvsx and building the libgcc float128 support causes 
problems
if you set the default cpu to something like a 7540, which does not have VSX
support.  The assembler complains that when the code does a ".machine 
7450", you
cannot use VSX instructions.

With these patches, the float128 libgcc support is only built if the default
compiler has VSX support.  If somebody wanted to enable the glibc support 
for
big endian, they would need to set the base cpu to power8 to enable 
building the
libgcc float128 libraries.

I built little endian compilers and there were no regressions.

I built big endian compilers with the --with-cpu=power5 configure option, 
and I
verified that none of the float128 support functions are built.

I also built big endian compilers on a power9 with the --with-cpu=native
configure option, and I verified that the float128 support functions were
built, since the default compiler used the VSX instruction set.

I verified that on both sets of big endian builds, that all of the float128
tests were skipped, since there is no support for float128 in glibc and the 
GCC
compiler does not enable float128 on those systems.

Can I check these patches into the trunk assuming the original bugzilla 
author
says they fix the problem?

2024-08-06 Michael Meissner  

libgcc/

PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not add t-float128-hw or
t-float128-p10-hw if the default compiler does not support float128.
* config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx when
building the basic float128 support.
* config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise.
* config/rs6000/t-float128-p10-hw (FP128_3_1_CFLAGS_HW): Likewise.
* configure.ac (powerpc*-*-linux*): Do not add -mvsx when testing
whether to build the float128 support.
* configure: Regenerate.

Diff:
---
 libgcc/config.host | 12 ++--
 libgcc/config/rs6000/t-float128|  8 +++-
 libgcc/config/rs6000/t-float128-hw |  3 +--
 libgcc/config/rs6000/t-float128-p10-hw |  3 +--
 libgcc/configure   |  8 +++-
 libgcc/configure.ac|  8 +++-
 6 files changed, 29 insertions(+), 13 deletions(-)

diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..261b08859a4d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
 
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
-   fi
 
-   if test $libgcc_cv_powerpc_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-hw"
-   fi
+   if test $libgcc_cv_powerpc_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-hw"
 
-   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+   tmake_file="${tmake_file} 
rs6000/t-float128-p10-hw"
+   fi
+   fi
fi
 
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index b09b5664af0e..93e78adcd624 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,13 @@ fp128_includes   = $(srcdir)/soft-fp/double.h \
  $(srcdir)/soft-fp/soft-fp.h
 
 # Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
+#
+# In the past we added -mvsx to build the float128 specific libraries with the
+# VSX instruction set.  This allowed the big endian GCC on server platforms to
+# build the float128 support.  However, is causes proble

[gcc(refs/users/meissner/heads/work175-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:306ea004fe66e562a4c1adeb5543d0e7c7cf980b

commit 306ea004fe66e562a4c1adeb5543d0e7c7cf980b
Author: Michael Meissner 
Date:   Tue Aug 6 02:08:08 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 210 -
 1 file changed, 209 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 94889013fa70..e8b978dd3d0f 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,6 +1,214 @@
+ Branch work175-bugs, patch #303 
+
+Do not add -mvsx when testing the float128 support.
+
+Currently, we add -mvsx when building the float128 support in libgcc.  This
+allows us to build the float128 support on a big endian system where the
+default cpu is power4.  While the libgcc support can be built, given there is
+no glibc support for float128 available.
+
+However, adding -mvsx and building the libgcc float128 support causes problems
+if you set the default cpu to something like a 7540, which does not have VSX
+support.  The assembler complains that when the code does a ".machine 7450", 
you
+cannot use VSX instructions.
+
+After patching libgcc to not build the float128 support unless the host can
+support float128 normally, this patch changes the GCC tests so that it will 
only
+do the IEEE 128-bit tests if the default compiler enables the VSX instruction
+set by default.  Otherwise all of the float128 tests will fail because the
+libgcc support is not available.
+
+In addition to not doing the float128 tests when the compiler does not natively
+support float128, this patch also removes adding -mvsx, -mfloat128, and
+-mfloat128-hardware enable the support if the compiler did not natively enable
+it.
+
+I built little endian compilers and there were no regressions.
+
+I built big endian compilers with the --with-cpu=power5 configure option, and I
+verified that none of the float128 support functions are built.
+
+I also built big endian compilers on a power9 with the --with-cpu=native
+configure option, and I verified that the float128 support functions were
+built, since the default compiler used the VSX instruction set.
+
+I verified that on both sets of big endian builds, that all of the float128
+tests were skipped, since there is no support for float128 in glibc and the GCC
+compiler does not enable float128 on those systems.
+
+Can I check these patches into the trunk assuming the original bugzilla author
+says they fix the problem?
+
+2024-08-06 Michael Meissner  
+
+gcc/testsuite/
+
+   PR target/115800
+   PR target/113652
+   * gcc.target/powerpc/abs128-1.c: Remove adding -mvsx, -mfloat128, and
+   -mfloat128-hardware options to float128 test.  Add explicit checks for
+   the float128 support, rather than just using VSX as a stand in, or
+   assuming we can silently enable VSX if the default is power4.  For
+   pr99708.c, also use the correct spelling to disable the float128 tests.
+   * gcc.target/powerpc/bfp/scalar-insert-exp-16.c: Likewise.
+   * gcc.target/powerpc/copysign128-1.c: Likewise.
+   * gcc.target/powerpc/divkc3-1.c: Likewise.
+   * gcc.target/powerpc/float128-3.c: Likewise.
+   * gcc.target/powerpc/float128-5.c: Likewise.
+   * gcc.target/powerpc/float128-complex-2.: Likewise.
+   * gcc.target/powerpc/float128-math.: Likewise.
+   * gcc.target/powerpc/inf128-1.: Likewise.
+   * gcc.target/powerpc/mulkc3-1.c: Likewise.
+   * gcc.target/powerpc/nan128-1.c: Likewise.
+   * gcc.target/powerpc/p9-lxvx-stxvx-3.: Likewise.
+   * gcc.target/powerpc/pr104253.: Likewise.
+   * gcc.target/powerpc/pr70669.c: Likewise.
+   * gcc.target/powerpc/pr79004.c: Likewise.
+   * gcc.target/powerpc/pr79038-1.c: Likewise.
+   * gcc.target/powerpc/pr81959.c: Likewise.
+   * gcc.target/powerpc/pr85657-1.: Likewise.
+   * gcc.target/powerpc/pr85657-2.c: Likewise.
+   * gcc.target/powerpc/pr99708.: Likewise.
+   * gcc.target/powerpc/signbit-1.c: Likewise.
+   * gcc.target/powerpc/signbit-2.c: Likewise.
+   * lib/target-supports.exp (check_ppc_float128_sw_available): Likewise.
+   (check_ppc_float128_hw_available): Likewise.
+   (check_effective_target_ppc_ieee128_ok): Likewise.
+   (add_options_for___float128): Likewise.
+   (check_effective_target___float128): Likewise.
+   (check_effective_target_base_quadfloat_support): Likewise.
+   (check_effective_target_powerpc_float128_sw_ok): Likewise.
+   (check_effective_target_powerpc_float128_hw_ok): Likewise.
+
+ Branch work175-bugs, patch #302 
+
+Do not add -mvsx when building libgcc float128 support.
+
+Currently, we add -mvsx when building the float128 support in libgcc.  This
+allows us to build the float128 support on a big endian system where the
+default cpu is power4.  While the libgcc support can be built, given there is
+no glibc

[gcc r15-2740] rs6000: Add const_vector into any_operand predicate

[HaoChen Gui via Gcc-cvs]

https://gcc.gnu.org/g:3592d3f8cc4b89ae508c747a46a626d73cb9616d

commit r15-2740-g3592d3f8cc4b89ae508c747a46a626d73cb9616d
Author: Haochen Gui 
Date:   Tue Aug 6 14:15:05 2024 +0800

rs6000: Add const_vector into any_operand predicate

gcc/
* config/rs6000/predicates.md (any_operand): Add const_vector.

Diff:
---
 gcc/config/rs6000/predicates.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index d23ce9a77a3f..cdfd400f6395 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -19,7 +19,7 @@
 
 ;; Return 1 for anything except PARALLEL.
 (define_predicate "any_operand"
-  (match_code 
"const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
+  (match_code 
"const_int,const_double,const_wide_int,const_vector,const,symbol_ref,label_ref,subreg,reg,mem"))
 
 ;; Return 1 for any PARALLEL.
 (define_predicate "any_parallel_operand"

[gcc(refs/users/meissner/heads/work175-vpair)] Add support for vector pair unary and binary operations.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c685497c72ba3fe3a42eaffc0c95d5c801b3d437

commit c685497c72ba3fe3a42eaffc0c95d5c801b3d437
Author: Michael Meissner 
Date:   Tue Aug 6 02:20:00 2024 -0400

Add support for vector pair unary and binary operations.

2024-05-06  Michael Meissner  

gcc/

* config/rs6000/rs6000-builtins.def (__builtin_vpair_*): Add new
built-in functions for vector pair support.
* config/rs6000/rs6000-protos.h (enum vpair_split_unary): New
enumeration.
(vpair_split_unary): New declaration.
(vpair_split_binary): Likewise.
* config/rs6000/rs6000.cc (vpair_split_unary): New function to split
vector pair operations.
(vpair_split_binary): Likewise.
* config/rs6000/rs6000.md (toplevel): Include vector-pair.md.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add vector-pair.md.
* config/rs6000/vector-pair.md: New file.
* doc/extend.texi (PowerPC Vector Pair Built-in Functions): Add
documentation for the new vector pair built-in functions.

gcc/testsuite/

* gcc.target/powerpc/vector-pair-1.c: New test.
* gcc.target/powerpc/vector-pair-2.c: Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtins.def|  56 
 gcc/config/rs6000/rs6000-protos.h|  12 ++
 gcc/config/rs6000/rs6000.cc  |  67 ++
 gcc/config/rs6000/rs6000.md  |   1 +
 gcc/config/rs6000/t-rs6000   |   1 +
 gcc/config/rs6000/vector-pair.md | 160 +++
 gcc/doc/extend.texi  |  51 
 gcc/testsuite/gcc.target/powerpc/vector-pair-1.c |  87 
 gcc/testsuite/gcc.target/powerpc/vector-pair-2.c |  86 
 9 files changed, 521 insertions(+)

diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index 0c3c884c1104..fddfa3cece88 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3921,3 +3921,59 @@
 
   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
 STXVP nothing {mma,pair}
+
+;; Vector pair built-in functions with float elements
+  v256 __builtin_vpair_f32_abs (v256);
+VPAIR_F32_ABS vpair_abs_v8sf2 {mma}
+
+  v256 __builtin_vpair_f32_add (v256, v256);
+VPAIR_F32_ADD vpair_add_v8sf3 {mma}
+
+  v256 __builtin_vpair_f32_div (v256, v256);
+VPAIR_F32_DIV vpair_div_v8sf3 {mma}
+
+  v256 __builtin_vpair_f32_max (v256, v256);
+VPAIR_F32_MAX vpair_smax_v8sf3 {mma}
+
+  v256 __builtin_vpair_f32_min (v256, v256);
+VPAIR_F32_MIN vpair_smin_v8sf3 {mma}
+
+  v256 __builtin_vpair_f32_mul (v256, v256);
+VPAIR_F32_MUL vpair_mul_v8sf3 {mma}
+
+  v256 __builtin_vpair_f32_nabs (v256);
+VPAIR_F32_NABS vpair_nabs_v8sf2 {mma}
+
+  v256 __builtin_vpair_f32_neg (v256);
+VPAIR_F32_NEG vpair_neg_v8sf2 {mma}
+
+  v256 __builtin_vpair_f32_sub (v256, v256);
+VPAIR_F32_SUB vpair_sub_v8sf3 {mma}
+
+;; Vector pair built-in functions with double elements
+  v256 __builtin_vpair_f64_abs (v256);
+VPAIR_F64_ABS vpair_abs_v4df2 {mma}
+
+  v256 __builtin_vpair_f64_add (v256, v256);
+VPAIR_F64_ADD vpair_add_v4df3 {mma}
+
+  v256 __builtin_vpair_f64_div (v256, v256);
+VPAIR_F64_DIV vpair_div_v4df3 {mma}
+
+  v256 __builtin_vpair_f64_max (v256, v256);
+VPAIR_F64_MAX vpair_smax_v4df3 {mma}
+
+  v256 __builtin_vpair_f64_min (v256, v256);
+VPAIR_F64_MIN vpair_smin_v4df3 {mma}
+
+  v256 __builtin_vpair_f64_mul (v256, v256);
+VPAIR_F64_MUL vpair_mul_v4df3 {mma}
+
+  v256 __builtin_vpair_f64_nabs (v256);
+VPAIR_F64_NABS vpair_nabs_v4df2 {mma}
+
+  v256 __builtin_vpair_f64_neg (v256);
+VPAIR_F64_NEG vpair_neg_v4df2 {mma}
+
+  v256 __builtin_vpair_f64_sub (v256, v256);
+VPAIR_F64_SUB vpair_sub_v4df3 {mma}
diff --git a/gcc/config/rs6000/rs6000-protos.h 
b/gcc/config/rs6000/rs6000-protos.h
index da658cd5ab2e..7b8b3b0c2377 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -161,6 +161,18 @@ extern bool rs6000_pcrel_p (void);
 extern bool rs6000_fndecl_pcrel_p (const_tree);
 extern void rs6000_output_addr_vec_elt (FILE *, int);
 
+/* If we are splitting a vector pair unary operator into two separate vector
+   operations, we need to generate a NEG if this is NABS.  */
+
+enum vpair_split_unary {
+  VPAIR_SPLIT_NORMAL,  /* No extra processing is needed.  */
+  VPAIR_SPLIT_NEGATE   /* Wrap operation with a NEG.  */
+};
+
+extern void vpair_split_unary (rtx [], machine_mode, enum rtx_code,
+  enum vpair_split_unary);
+extern void vpair_split_binary (rtx [], machine_mode, enum rtx_code);
+
 /* Different PowerPC instruction formats that are used by GCC.  There are
various other instruction formats used by the PowerPC hardware, but these
formats are not current

[gcc(refs/users/meissner/heads/work175-vpair)] Add support for vector pair fma operations.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d5b3c64e997c3a27a77d5b95f6fc3e3828a609a1

commit d5b3c64e997c3a27a77d5b95f6fc3e3828a609a1
Author: Michael Meissner 
Date:   Tue Aug 6 02:27:38 2024 -0400

Add support for vector pair fma operations.

2024-08-06  Michael Meissner  

gcc/

* config/rs6000/rs6000-builtins.def (__builtin_vpair_f32_fma): New
built-in.
(__builtin_vpair_f32_fms): Likewise.
(__builtin_vpair_f32_nfma): Likewise.
(__builtin_vpair_f32_nfms): Likewise.
(__builtin_vpair_f64_fma): Likewise.
(__builtin_vpair_f64_fms): Likewise.
(__builtin_vpair_f64_nfma): Likewise.
* config/rs6000/rs6000/rs6000-proto.h (enum vpair_split_fma): New
enumeration.
(vpair_split_fma): New declaration.
* config/rs6000/rs6000.cc (vpair_split_fma): New function to split
vector pair FMA operations.
* config/rs6000/vector-pair.md (UNSPEC_VPAIR_FMA): New unspec.
(vpair_stdname): Add UNSPEC_VPAIR_FMA.
(VPAIR_OP): Likewise.
(vpair_fma_4): New insns.
(vpair_fms_4): Likewise.
(vpair_nfma_4): Likewise.
(vpair_nfms_4): Likewise.
* doc/extend.texi (PowerPC Vector Pair Built-in Functions): 
Document new
vector pair fma built-in functions.

gcc/testsuite/

* gcc.target/powerpc/vector-pair-3.c: New test.
* gcc.target/powerpc/vector-pair-4.c: Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtins.def| 24 ++
 gcc/config/rs6000/rs6000-protos.h| 13 
 gcc/config/rs6000/rs6000.cc  | 71 ++
 gcc/config/rs6000/vector-pair.md | 96 
 gcc/doc/extend.texi  | 25 ++
 gcc/testsuite/gcc.target/powerpc/vector-pair-3.c | 57 ++
 gcc/testsuite/gcc.target/powerpc/vector-pair-4.c | 57 ++
 7 files changed, 343 insertions(+)

diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index fddfa3cece88..900e5466e6c2 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3932,6 +3932,12 @@
   v256 __builtin_vpair_f32_div (v256, v256);
 VPAIR_F32_DIV vpair_div_v8sf3 {mma}
 
+  v256 __builtin_vpair_f32_fma (v256, v256, v256);
+VPAIR_F32_FMA vpair_fma_v8sf4 {mma}
+
+  v256 __builtin_vpair_f32_fms (v256, v256, v256);
+VPAIR_F32_FMS vpair_fms_v8sf4 {mma}
+
   v256 __builtin_vpair_f32_max (v256, v256);
 VPAIR_F32_MAX vpair_smax_v8sf3 {mma}
 
@@ -3947,6 +3953,12 @@
   v256 __builtin_vpair_f32_neg (v256);
 VPAIR_F32_NEG vpair_neg_v8sf2 {mma}
 
+  v256 __builtin_vpair_f32_nfma (v256, v256, v256);
+VPAIR_F32_NFMA vpair_nfma_v8sf4 {mma}
+
+  v256 __builtin_vpair_f32_nfms (v256, v256, v256);
+VPAIR_F32_NFMS vpair_nfms_v8sf4 {mma}
+
   v256 __builtin_vpair_f32_sub (v256, v256);
 VPAIR_F32_SUB vpair_sub_v8sf3 {mma}
 
@@ -3960,6 +3972,12 @@
   v256 __builtin_vpair_f64_div (v256, v256);
 VPAIR_F64_DIV vpair_div_v4df3 {mma}
 
+  v256 __builtin_vpair_f64_fma (v256, v256, v256);
+VPAIR_F64_FMA vpair_fma_v4df4 {mma}
+
+  v256 __builtin_vpair_f64_fms (v256, v256, v256);
+VPAIR_F64_FMS vpair_fms_v4df4 {mma}
+
   v256 __builtin_vpair_f64_max (v256, v256);
 VPAIR_F64_MAX vpair_smax_v4df3 {mma}
 
@@ -3975,5 +3993,11 @@
   v256 __builtin_vpair_f64_neg (v256);
 VPAIR_F64_NEG vpair_neg_v4df2 {mma}
 
+  v256 __builtin_vpair_f64_nfma (v256, v256, v256);
+VPAIR_F64_NFMA vpair_nfma_v4df4 {mma}
+
+  v256 __builtin_vpair_f64_nfms (v256, v256, v256);
+VPAIR_F64_NFMS vpair_nfms_v4df4 {mma}
+
   v256 __builtin_vpair_f64_sub (v256, v256);
 VPAIR_F64_SUB vpair_sub_v4df3 {mma}
diff --git a/gcc/config/rs6000/rs6000-protos.h 
b/gcc/config/rs6000/rs6000-protos.h
index 7b8b3b0c2377..bab5fb437c27 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -173,6 +173,19 @@ extern void vpair_split_unary (rtx [], machine_mode, enum 
rtx_code,
   enum vpair_split_unary);
 extern void vpair_split_binary (rtx [], machine_mode, enum rtx_code);
 
+/* When we are splitting a vector pair FMA operation into two vector 
operations, we
+   may need to modify the code generated.  This enumeration encodes the
+   different choices.  */
+
+enum vpair_split_fma {
+  VPAIR_SPLIT_FMA, /* Fused multiply-add.  */
+  VPAIR_SPLIT_FMS, /* Fused multiply-subtract.  */
+  VPAIR_SPLIT_NFMA,/* Fused negate multiply-add.  */
+  VPAIR_SPLIT_NFMS /* Fused negate multiply-subtract.  */
+};
+
+extern void vpair_split_fma (rtx [], machine_mode, enum vpair_split_fma);
+
 /* Different PowerPC instruction formats that are used by GCC.  There are
various other instruction formats used by the PowerPC hardware, but these
formats 

[gcc(refs/users/meissner/heads/work175-vpair)] Add vector pair init and splat.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0f210e5f847601d966f2a1034359e7dd0cc88814

commit 0f210e5f847601d966f2a1034359e7dd0cc88814
Author: Michael Meissner 
Date:   Tue Aug 6 02:33:28 2024 -0400

Add vector pair init and splat.

2024-08-06  Michael Meissner  

gcc/

* config/rs6000/rs6000-builtins.def (__builtin_vpair_zero): New
built-in function.
(__builtin_vpair_f32_splat): Likewise.
(__builtin_vpair_f64_splat): Likewise.
* config/rs6000/vector-pair.md (UNSPEC_VPAIR_ZERO): New unspec.
(UNSPEC_VPAIR_SPLAT): Likewise.
(VPAIR_SPLAT_VMODE): New mode iterator.
(VPAIR_SPLAT_ELEMENT_TO_VMODE): New mode attribute.
(vpair_splat_name): Likewise.
(vpair_zero): New insn.
(vpair_splat_): New define_expand.
(vpair_splat__internal): New insns.

gcc/testsuite/

* gcc.target/powerpc/vector-pair-5.c: New test.
* gcc.target/powerpc/vector-pair-6.c: Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtins.def|  10 +++
 gcc/config/rs6000/vector-pair.md | 102 ++-
 gcc/doc/extend.texi  |   9 ++
 gcc/testsuite/gcc.target/powerpc/vector-pair-5.c |  56 +
 gcc/testsuite/gcc.target/powerpc/vector-pair-6.c |  56 +
 5 files changed, 232 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000-builtins.def 
b/gcc/config/rs6000/rs6000-builtins.def
index 900e5466e6c2..c31afe023d69 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3922,6 +3922,10 @@
   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
 STXVP nothing {mma,pair}
 
+;; Vector pair built-in functions.
+  v256 __builtin_vpair_zero ();
+VPAIR_ZERO vpair_zero {mma}
+
 ;; Vector pair built-in functions with float elements
   v256 __builtin_vpair_f32_abs (v256);
 VPAIR_F32_ABS vpair_abs_v8sf2 {mma}
@@ -3959,6 +3963,9 @@
   v256 __builtin_vpair_f32_nfms (v256, v256, v256);
 VPAIR_F32_NFMS vpair_nfms_v8sf4 {mma}
 
+  v256 __builtin_vpair_f32_splat (float);
+VPAIR_F32_SPLAT vpair_splat_v8sf {mma}
+
   v256 __builtin_vpair_f32_sub (v256, v256);
 VPAIR_F32_SUB vpair_sub_v8sf3 {mma}
 
@@ -3999,5 +4006,8 @@
   v256 __builtin_vpair_f64_nfms (v256, v256, v256);
 VPAIR_F64_NFMS vpair_nfms_v4df4 {mma}
 
+  v256 __builtin_vpair_f64_splat (double);
+VPAIR_F64_SPLAT vpair_splat_v4df {mma}
+
   v256 __builtin_vpair_f64_sub (v256, v256);
 VPAIR_F64_SUB vpair_sub_v4df3 {mma}
diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index 73ae46e6d40a..39b419c68146 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -38,7 +38,9 @@
UNSPEC_VPAIR_NEG
UNSPEC_VPAIR_PLUS
UNSPEC_VPAIR_SMAX
-   UNSPEC_VPAIR_SMIN])
+   UNSPEC_VPAIR_SMIN
+   UNSPEC_VPAIR_ZERO
+   UNSPEC_VPAIR_SPLAT])
 
 ;; Vector pair element ID that defines the scaler element within the vector 
pair.
 (define_c_enum "vpair_element"
@@ -98,6 +100,104 @@
 ;; Map the scalar element ID into the appropriate insn type for divide.
 (define_int_attr vpair_divtype [(VPAIR_ELEMENT_FLOAT  "vecfdiv")
(VPAIR_ELEMENT_DOUBLE "vecdiv")])
+
+;; Mode iterator for the vector modes that we provide splat operations for.
+(define_mode_iterator VPAIR_SPLAT_VMODE [V4SF V2DF])
+
+;; Map element mode to 128-bit vector mode for splat operations
+(define_mode_attr VPAIR_SPLAT_ELEMENT_TO_VMODE [(SF "V4SF")
+   (DF "V2DF")])
+
+;; Map either element mode or vector mode into the name for the splat insn.
+(define_mode_attr vpair_splat_name [(SF   "v8sf")
+   (DF   "v4df")
+   (V4SF "v8sf")
+   (V2DF "v4df")])
+
+;; Initialize a vector pair to 0
+(define_insn_and_split "vpair_zero"
+  [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+   (unspec:OO [(const_int 0)] UNSPEC_VPAIR_ZERO))]
+  "TARGET_MMA"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 1) (match_dup 3))
+   (set (match_dup 2) (match_dup 3))]
+{
+  rtx op0 = operands[0];
+
+  operands[1] = simplify_gen_subreg (V2DFmode, op0, OOmode, 0);
+  operands[2] = simplify_gen_subreg (V2DFmode, op0, OOmode, 16);
+  operands[3] = CONST0_RTX (V2DFmode);
+}
+  [(set_attr "length" "8")
+   (set_attr "type" "vecperm")])
+
+;; Create a vector pair with a value splat'ed (duplicated) to all of the
+;; elements.
+(define_expand "vpair_splat_"
+  [(use (match_operand:OO 0 "vsx_register_operand"))
+   (use (match_operand:SFDF 1 "input_operand"))]
+  "TARGET_MMA"
+{
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  machine_mode element_mode = mode;
+
+  if (op1 == CONST0_RTX (element_mode))
+{
+  emit_insn (gen_vpair_zero (op0));
+  DONE;
+}
+
+  machine_mode vector_mode = mo

[gcc(refs/users/meissner/heads/work175-vpair)] Add vector pair optimizations.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:6b2ea24a882afb4639f9ea629e527aecbe82f93c

commit 6b2ea24a882afb4639f9ea629e527aecbe82f93c
Author: Michael Meissner 
Date:   Tue Aug 6 02:35:09 2024 -0400

Add vector pair optimizations.

2024-08-06  Michael Meissner  

gcc/

* config/rs6000/vector-pair.md (vpair_add_neg_3): 
New
combiner insn to convert vector plus/neg into a minus operation.
(vpair_fma__merge): Optimize multiply, 
add/subtract, and
negation into fma operations if the user specifies to create fmas.
(vpair_fma__merge): Likewise.
(vpair_fma__merge2): Likewise.
(vpair_nfma__merge): Likewise.
(vpair_nfms__merge): Likewise.
(vpair_nfms__merge2): Likewise.

gcc/testsuite/

* gcc.target/powerpc/vector-pair-7.c: New test.
* gcc.target/powerpc/vector-pair-8.c: Likewise.
* gcc.target/powerpc/vector-pair-9.c: Likewise.
* gcc.target/powerpc/vector-pair-10.c: Likewise.
* gcc.target/powerpc/vector-pair-11.c: Likewise.
* gcc.target/powerpc/vector-pair-12xs.c: Likewise.

Diff:
---
 gcc/config/rs6000/vector-pair.md  | 224 ++
 gcc/testsuite/gcc.target/powerpc/vector-pair-10.c |  61 ++
 gcc/testsuite/gcc.target/powerpc/vector-pair-11.c |  65 +++
 gcc/testsuite/gcc.target/powerpc/vector-pair-12.c |  65 +++
 gcc/testsuite/gcc.target/powerpc/vector-pair-7.c  |  18 ++
 gcc/testsuite/gcc.target/powerpc/vector-pair-8.c  |  18 ++
 gcc/testsuite/gcc.target/powerpc/vector-pair-9.c  |  61 ++
 7 files changed, 512 insertions(+)

diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index 39b419c68146..7a81acbdc05c 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -261,6 +261,31 @@
(set (attr "type") (if_then_else (match_test " == DIV")
(const_string "")
(const_string "")))])
+
+;; Optimize vector pair add of a negative value into a subtract.
+(define_insn_and_split "*vpair_add_neg_3"
+  [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+   (unspec:OO
+[(match_operand:OO 1 "vsx_register_operand" "wa")
+ (unspec:OO
+  [(match_operand:OO 2 "vsx_register_operand" "wa")
+   (const_int VPAIR_FP_ELEMENT)]
+  UNSPEC_VPAIR_NEG)
+ (const_int VPAIR_FP_ELEMENT)]
+VPAIR_FP_BINARY))]
+  "TARGET_MMA"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+   (unspec:OO
+[(match_dup 1)
+ (match_dup 2)
+ (const_int VPAIR_FP_ELEMENT)]
+UNSPEC_VPAIR_MINUS))]
+{
+}
+  [(set_attr "length" "8")
+   (set_attr "type" "")])
 
 ;; Vector pair fused-multiply (FMA) operations.  The last argument in the
 ;; UNSPEC is a CONST_INT which identifies what the scalar element is.
@@ -354,3 +379,202 @@
 }
   [(set_attr "length" "8")
(set_attr "type" "")])
+
+;; Optimize vector pair multiply and vector pair add into vector pair fma,
+;; providing the compiler would do this optimization for scalar and vectors.
+;; Unlike most of the define_insn_and_splits, this can be done before register
+;; allocation.
+(define_insn_and_split "*vpair_fma__merge"
+  [(set (match_operand:OO 0 "vsx_register_operand" "=wa,wa")
+   (unspec:OO
+[(unspec:OO
+  [(match_operand:OO 1 "vsx_register_operand" "%wa,wa")
+   (match_operand:OO 2 "vsx_register_operand" "wa,0")
+   (const_int VPAIR_FP_ELEMENT)]
+  UNSPEC_VPAIR_MULT)
+ (match_operand:OO 3 "vsx_register_operand" "0,wa")
+ (const_int VPAIR_FP_ELEMENT)]
+UNSPEC_VPAIR_PLUS))]
+  "TARGET_MMA && flag_fp_contract_mode == FP_CONTRACT_FAST"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+   (unspec:OO
+[(match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ (const_int VPAIR_FP_ELEMENT)]
+UNSPEC_VPAIR_FMA))]
+{
+}
+  [(set_attr "length" "8")
+   (set_attr "type" "")])
+
+;; Merge multiply and subtract.
+(define_insn_and_split "*vpair_fma__merge"
+  [(set (match_operand:OO 0 "vsx_register_operand" "=wa,wa")
+   (unspec:OO
+[(unspec:OO
+  [(match_operand:OO 1 "vsx_register_operand" "%wa,wa")
+   (match_operand:OO 2 "vsx_register_operand" "wa,0")
+   (const_int VPAIR_FP_ELEMENT)]
+  UNSPEC_VPAIR_MULT)
+ (match_operand:OO 3 "vsx_register_operand" "0,wa")
+ (const_int VPAIR_FP_ELEMENT)]
+UNSPEC_VPAIR_MINUS))]
+  "TARGET_MMA && flag_fp_contract_mode == FP_CONTRACT_FAST"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+   (unspec:OO
+[(match_dup 1)
+ (match_dup 2)
+ (unspec:OO
+  [(match_dup 3)
+   (const_int VPAIR_FP_ELEMENT)]
+  UNSPEC_VPAIR_NEG)
+ (const_int VPAIR_FP_ELEMENT)]
+UNSPEC_VPAIR_FMA))]
+{
+}
+  [(set_attr "length" "8")
+   (set_attr "type" 

[gcc(refs/users/meissner/heads/work175-vpair)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:6e73367a476c64701e30e27817cd8c8b780f99c4

commit 6e73367a476c64701e30e27817cd8c8b780f99c4
Author: Michael Meissner 
Date:   Tue Aug 6 02:38:30 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.vpair | 127 +++-
 1 file changed, 126 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
index 8355bde3ebaa..dd974a3a72aa 100644
--- a/gcc/ChangeLog.vpair
+++ b/gcc/ChangeLog.vpair
@@ -1,6 +1,131 @@
+ Branch work175-vpair, patch #403 
+
+Add vector pair optimizations.
+
+2024-08-06  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/vector-pair.md (vpair_add_neg_3): New
+   combiner insn to convert vector plus/neg into a minus operation.
+   (vpair_fma__merge): Optimize multiply, add/subtract, and
+   negation into fma operations if the user specifies to create fmas.
+   (vpair_fma__merge): Likewise.
+   (vpair_fma__merge2): Likewise.
+   (vpair_nfma__merge): Likewise.
+   (vpair_nfms__merge): Likewise.
+   (vpair_nfms__merge2): Likewise.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/vector-pair-7.c: New test.
+   * gcc.target/powerpc/vector-pair-8.c: Likewise.
+   * gcc.target/powerpc/vector-pair-9.c: Likewise.
+   * gcc.target/powerpc/vector-pair-10.c: Likewise.
+   * gcc.target/powerpc/vector-pair-11.c: Likewise.
+   * gcc.target/powerpc/vector-pair-12xs.c: Likewise.
+
+ Branch work175-vpair, patch #402 
+
+Add vector pair init and splat.
+
+2024-08-06  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-builtins.def (__builtin_vpair_zero): New
+   built-in function.
+   (__builtin_vpair_f32_splat): Likewise.
+   (__builtin_vpair_f64_splat): Likewise.
+   * config/rs6000/vector-pair.md (UNSPEC_VPAIR_ZERO): New unspec.
+   (UNSPEC_VPAIR_SPLAT): Likewise.
+   (VPAIR_SPLAT_VMODE): New mode iterator.
+   (VPAIR_SPLAT_ELEMENT_TO_VMODE): New mode attribute.
+   (vpair_splat_name): Likewise.
+   (vpair_zero): New insn.
+   (vpair_splat_): New define_expand.
+   (vpair_splat__internal): New insns.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/vector-pair-5.c: New test.
+   * gcc.target/powerpc/vector-pair-6.c: Likewise.
+
+ Branch work175-vpair, patch #401 
+
+Add support for vector pair fma operations.
+
+2024-08-06  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-builtins.def (__builtin_vpair_f32_fma): New
+   built-in.
+   (__builtin_vpair_f32_fms): Likewise.
+   (__builtin_vpair_f32_nfma): Likewise.
+   (__builtin_vpair_f32_nfms): Likewise.
+   (__builtin_vpair_f64_fma): Likewise.
+   (__builtin_vpair_f64_fms): Likewise.
+   (__builtin_vpair_f64_nfma): Likewise.
+   * config/rs6000/rs6000/rs6000-proto.h (enum vpair_split_fma): New
+   enumeration.
+   (vpair_split_fma): New declaration.
+   * config/rs6000/rs6000.cc (vpair_split_fma): New function to split
+   vector pair FMA operations.
+   * config/rs6000/vector-pair.md (UNSPEC_VPAIR_FMA): New unspec.
+   (vpair_stdname): Add UNSPEC_VPAIR_FMA.
+   (VPAIR_OP): Likewise.
+   (vpair_fma_4): New insns.
+   (vpair_fms_4): Likewise.
+   (vpair_nfma_4): Likewise.
+   (vpair_nfms_4): Likewise.
+   * doc/extend.texi (PowerPC Vector Pair Built-in Functions): Document new
+   vector pair fma built-in functions.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/vector-pair-3.c: New test.
+   * gcc.target/powerpc/vector-pair-4.c: Likewise.
+
+ Branch work175-vpair, patch #400 
+
+Add support for vector pair unary and binary operations.
+
+2024-08-06  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-builtins.def (__builtin_vpair_*): Add new
+   built-in functions for vector pair support.
+   * config/rs6000/rs6000-protos.h (enum vpair_split_unary): New
+   enumeration.
+   (vpair_split_unary): New declaration.
+   (vpair_split_binary): Likewise.
+   * config/rs6000/rs6000.cc (vpair_split_unary): New function to split
+   vector pair operations.
+   (vpair_split_binary): Likewise.
+   * config/rs6000/rs6000.md (toplevel): Include vector-pair.md.
+   * config/rs6000/t-rs6000 (MD_INCLUDES): Add vector-pair.md.
+   * config/rs6000/vector-pair.md: New file.
+   * doc/extend.texi (PowerPC Vector Pair Built-in Functions): Add
+   documentation for the new vector pair built-in functions.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/vector-pair-1.c: New test.
+   * gcc.target/powerpc/vector-pair-2.c: Likewise.
+
  Branch work175-vpair, baseline 
 
+Add ChangeLog.vpair and update REVISION.
+
+2024-08-01  Michael Meissner  
+
+gcc/
+
+   * ChangeLog.vpair: New file for branch.
+   * REVISION: