[gcc r15-1992] RISC-V: Add SiFive extensions, xsfvcp and xsfcease

[Kito Cheng via Gcc-cvs]

https://gcc.gnu.org/g:3ea47ea1fcab95fd1b80acc724fdbb27fc436985

commit r15-1992-g3ea47ea1fcab95fd1b80acc724fdbb27fc436985
Author: Kito Cheng 
Date:   Tue Jul 9 15:50:57 2024 +0800

RISC-V: Add SiFive extensions, xsfvcp and xsfcease

We have already upstreamed these extensions into binutils, and now we need 
GCC
to recognize these extensions and pass them to binutils as well. We also 
plan
to upstream intrinsics in the near future. :)

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_implied_info): Add 
xsfvcp.
(riscv_ext_version_table): Add xsfvcp, xsfcease.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv.opt (riscv_sifive_subext): New.
(XSFVCP): New.
(XSFCEASE): New.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-sf-1.c: New.
* gcc.target/riscv/predef-sf-2.c: New.

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  |  8 
 gcc/config/riscv/riscv.opt   |  7 +++
 gcc/testsuite/gcc.target/riscv/predef-sf-1.c | 19 +++
 gcc/testsuite/gcc.target/riscv/predef-sf-2.c | 14 ++
 4 files changed, 48 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 3c4178c19c99..d883efa7a3ab 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -216,6 +216,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"ssstateen", "zicsr"},
   {"sstc", "zicsr"},
 
+  {"xsfvcp", "zve32x"},
+
   {NULL, NULL}
 };
 
@@ -415,6 +417,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xsfvcp",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1822,6 +1827,9 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"xventanacondops", &gcc_options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
+  {"xsfvcp",   &gcc_options::x_riscv_sifive_subext, MASK_XSFVCP},
+  {"xsfcease", &gcc_options::x_riscv_sifive_subext, MASK_XSFCEASE},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 32a0dda58439..a1d70b636382 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -507,6 +507,13 @@ int riscv_xventana_subext
 
 Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
 
+TargetVariable
+int riscv_sifive_subext
+
+Mask(XSFVCP) Var(riscv_sifive_subext)
+
+Mask(XSFCEASE) Var(riscv_sifive_subext)
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-1.c 
b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
new file mode 100644
index ..d6c07e7d9207
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfvcp -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
+#endif
+
+
+#if !defined(__riscv_xsfvcp)
+#error "__riscv_xsfvcp"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-2.c 
b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
new file mode 100644
index ..dcb746bcd260
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfcease -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xsfcease)
+#error "__riscv_xsfvcp"
+#endif
+
+  return 0;
+}

[gcc r15-1993] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]

[Li Xu via Gcc-cvs]

https://gcc.gnu.org/g:63d7d5998e3768f6e3703c29e8774e8b54af108c

commit r15-1993-g63d7d5998e3768f6e3703c29e8774e8b54af108c
Author: xuli 
Date:   Thu Jul 11 04:29:11 2024 +

RISC-V: Disable misaligned vector access in hook 
riscv_slow_unaligned_access[PR115862]

The reason is that in the following code, icode = movmisalignv8si has
already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is
allowed by targetm.slow_unaligned_access,which is contradictory.

(((icode = optab_handler (movmisalign_optab, mode))
   != CODE_FOR_nothing)
  || targetm.slow_unaligned_access (mode, align))

misaligned vector access should be enabled by -mno-vector-strict-align 
option.

PR target/115862

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable 
vector misalign.

Signed-off-by: Li Xu 

Diff:
---
 gcc/config/riscv/riscv.cc  |  5 ++-
 gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c | 52 ++
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 61fa74e93220..16b210f323e2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10269,9 +10269,10 @@ riscv_cannot_copy_insn_p (rtx_insn *insn)
 /* Implement TARGET_SLOW_UNALIGNED_ACCESS.  */
 
 static bool
-riscv_slow_unaligned_access (machine_mode, unsigned int)
+riscv_slow_unaligned_access (machine_mode mode, unsigned int)
 {
-  return riscv_slow_unaligned_access_p;
+  return VECTOR_MODE_P (mode) ? TARGET_VECTOR_MISALIGN_SUPPORTED
+ : riscv_slow_unaligned_access_p;
 }
 
 static bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
new file mode 100644
index ..3cbc3c3a0ea4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcv_zvl512b -mabi=lp64d" } */
+
+struct mallinfo2
+{
+  int arena;
+  int ordblks;
+  int smblks;
+  int hblks;
+  int hblkhd;
+  int usmblks;
+  int fsmblks;
+  int uordblks;
+  int fordblks;
+  int keepcost;
+};
+
+struct mallinfo
+{
+  int arena;
+  int ordblks;
+  int smblks;
+  int hblks;
+  int hblkhd;
+  int usmblks;
+  int fsmblks;
+  int uordblks;
+  int fordblks;
+  int keepcost;
+};
+
+struct mallinfo
+__libc_mallinfo (void)
+{
+  struct mallinfo m;
+  struct mallinfo2 m2;
+
+  m.arena = m2.arena;
+  m.ordblks = m2.ordblks;
+  m.smblks = m2.smblks;
+  m.hblks = m2.hblks;
+  m.hblkhd = m2.hblkhd;
+  m.usmblks = m2.usmblks;
+  m.fsmblks = m2.fsmblks;
+  m.uordblks = m2.uordblks;
+  m.fordblks = m2.fordblks;
+  m.keepcost = m2.keepcost;
+
+  return m;
+}
+
+/* { dg-final { scan-assembler {vle32\.v} } } */

[gcc r15-1994] fortran: Factor the evaluation of MINLOC/MAXLOC's BACK argument

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:a55d24b3cf7f4d07492bb8e6fcee557175b47ea3

commit r15-1994-ga55d24b3cf7f4d07492bb8e6fcee557175b47ea3
Author: Mikael Morin 
Date:   Thu Jul 11 21:55:58 2024 +0200

fortran: Factor the evaluation of MINLOC/MAXLOC's BACK argument

Move the evaluation of the BACK argument out of the loop in the inline code
generated for MINLOC or MAXLOC.  For that, add a new (scalar) element
associated with BACK to the scalarization loop chain, evaluate the argument
with the context of that element, and let the scalarizer do its job.

The problem was not only a missed optimisation, but also a wrong code
one in the cases where the expression associated with BACK is not free of
side-effects, making multiple evaluations observable.

The new tests check the evaluation count of the BACK argument, and try to
cover all the variations (integral or floating-point type, constant or
unknown shape, absent or scalar or array MASK) supported by the inline
implementation of the functions.  Care has been taken to not check the case
of a constant .FALSE. MASK, for which the evaluation of BACK can be elided.

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Create a new
scalar scalarization chain element if BACK is present.  Add it to
the loop.  Set the scalarization chain before evaluating the
argument.

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_5.f90: New test.
* gfortran.dg/minloc_5.f90: New test.

Diff:
---
 gcc/fortran/trans-intrinsic.cc |  10 ++
 gcc/testsuite/gfortran.dg/maxloc_5.f90 | 257 +
 gcc/testsuite/gfortran.dg/minloc_5.f90 | 257 +
 3 files changed, 524 insertions(+)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index 5ea10e840609..cadbd1774520 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5325,6 +5325,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   gfc_actual_arglist *actual;
   gfc_ss *arrayss;
   gfc_ss *maskss;
+  gfc_ss *backss;
   gfc_se arrayse;
   gfc_se maskse;
   gfc_expr *arrayexpr;
@@ -5390,6 +5391,11 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 && maskexpr->symtree->n.sym->attr.dummy
 && maskexpr->symtree->n.sym->attr.optional;
   backexpr = actual->next->next->expr;
+  if (backexpr)
+backss = gfc_get_scalar_ss (gfc_ss_terminator, backexpr);
+  else
+backss = nullptr;
+
   nonempty = NULL;
   if (maskexpr && maskexpr->rank != 0)
 {
@@ -5449,6 +5455,9 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   if (maskss)
 gfc_add_ss_to_loop (&loop, maskss);
 
+  if (backss)
+gfc_add_ss_to_loop (&loop, backss);
+
   gfc_add_ss_to_loop (&loop, arrayss);
 
   /* Initialize the loop.  */
@@ -5535,6 +5544,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   gfc_add_block_to_block (&block, &arrayse.pre);
 
   gfc_init_se (&backse, NULL);
+  backse.ss = backss;
   gfc_conv_expr_val (&backse, backexpr);
   gfc_add_block_to_block (&block, &backse.pre);
 
diff --git a/gcc/testsuite/gfortran.dg/maxloc_5.f90 
b/gcc/testsuite/gfortran.dg/maxloc_5.f90
new file mode 100644
index ..5d722450c8fb
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/maxloc_5.f90
@@ -0,0 +1,257 @@
+! { dg-do run }
+!
+! Check that the evaluation of MAXLOC's BACK argument is made only once
+! before the scalarisation loops.
+
+program p
+  implicit none
+  integer, parameter :: data10(*) = (/ 7, 4, 7, 6, 6, 4, 6, 3, 9, 8 /)
+  logical, parameter :: mask10(*) = (/ .false., .true., .false., &
+   .false., .true., .true.,  &
+   .true. , .true., .false., &
+   .false. /)
+  integer :: calls_count = 0
+  call check_int_const_shape
+  call check_int_const_shape_scalar_mask
+  call check_int_const_shape_array_mask
+  call check_int_const_shape_optional_mask_present
+  call check_int_const_shape_optional_mask_absent
+  call check_int_const_shape_empty
+  call check_int_alloc
+  call check_int_alloc_scalar_mask
+  call check_int_alloc_array_mask
+  call check_int_alloc_empty
+  call check_real_const_shape
+  call check_real_const_shape_scalar_mask
+  call check_real_const_shape_array_mask
+  call check_real_const_shape_optional_mask_present
+  call check_real_const_shape_optional_mask_absent
+  call check_real_const_shape_empty
+  call check_real_alloc
+  call check_real_alloc_scalar_mask
+  call check_real_alloc_array_mask
+  call check_real_alloc_empty
+contains
+  function get_scalar_false()
+logical :: get_scalar_false
+calls_count = calls_count + 1
+get_scalar_false = .false.
+  end function
+  subroutine check_int_const

[gcc r15-1995] RISC-V: NO_WARNING preferred else value for RVV

[YunQiang Su via Gcc-cvs]

https://gcc.gnu.org/g:c6f38e5e6d900b8ed6a4f5c126d3197946cad4dd

commit r15-1995-gc6f38e5e6d900b8ed6a4f5c126d3197946cad4dd
Author: YunQiang Su 
Date:   Thu Jul 11 20:43:54 2024 +0800

RISC-V: NO_WARNING preferred else value for RVV

PR target/115840.

In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.

The problem is that `warn_uninit` will emit a warning:
  '({anonymous})' may be used uninitialized

Let's mark this tmp var as NO_WARNING.

This problem is found when I try to build glibc with V extension.

gcc

PR target/115840
* config/riscv/riscv.cc(riscv_preferred_else_value): Mark
tmp_var as NO_WARNING.

gcc/testsuite
* gcc.dg/vect/pr115840.c: New testcase.

Diff:
---
 gcc/config/riscv/riscv.cc|  6 +-
 gcc/testsuite/gcc.dg/vect/pr115840.c | 11 +++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 16b210f323e2..d50ac611e1af 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11432,7 +11432,11 @@ riscv_preferred_else_value (unsigned ifn, tree 
vectype, unsigned int nops,
tree *ops)
 {
   if (riscv_v_ext_mode_p (TYPE_MODE (vectype)))
-return get_or_create_ssa_default_def (cfun, create_tmp_var (vectype));
+{
+  tree tmp_var = create_tmp_var (vectype);
+  TREE_NO_WARNING (tmp_var) = 1;
+  return get_or_create_ssa_default_def (cfun, tmp_var);
+}
 
   return default_preferred_else_value (ifn, vectype, nops, ops);
 }
diff --git a/gcc/testsuite/gcc.dg/vect/pr115840.c 
b/gcc/testsuite/gcc.dg/vect/pr115840.c
new file mode 100644
index ..09dc9e4eb7c2
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr115840.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-Wall -Werror" } */
+
+double loads[16];
+
+void
+foo (double loadavg[], int count)
+{
+  for (int i = 0; i < count; i++)
+loadavg[i] = loads[i] / 1.5;
+}

[gcc r15-1996] [alpha] adjust MEM alignment for block move [PR115459]

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:ccfe7151803956d178947d0afda0bd66ce097275

commit r15-1996-gccfe7151803956d178947d0afda0bd66ce097275
Author: Alexandre Oliva 
Date:   Fri Jul 12 05:42:07 2024 -0300

[alpha] adjust MEM alignment for block move [PR115459]

Before issuing loads or stores for a block move, adjust the MEM
alignments if analysis of the addresses enabled the inference of
stricter alignment.  This ensures that the MEMs are sufficiently
aligned for the corresponding insns, which avoids trouble in case of
e.g. substitutions into SUBREGs.


for  gcc/ChangeLog

PR target/115459
* config/alpha/alpha.cc (alpha_expand_block_move): Adjust
MEMs to match inferred alignment.

Diff:
---
 gcc/config/alpha/alpha.cc | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc
index a6fe95e71778..74631a416935 100644
--- a/gcc/config/alpha/alpha.cc
+++ b/gcc/config/alpha/alpha.cc
@@ -3820,6 +3820,12 @@ alpha_expand_block_move (rtx operands[])
   else if (a >= 16 && c % 2 == 0)
src_align = 16;
}
+
+  if (MEM_P (orig_src) && MEM_ALIGN (orig_src) < src_align)
+   {
+ orig_src = shallow_copy_rtx (orig_src);
+ set_mem_align (orig_src, src_align);
+   }
 }
 
   tmp = XEXP (orig_dst, 0);
@@ -3841,6 +3847,12 @@ alpha_expand_block_move (rtx operands[])
   else if (a >= 16 && c % 2 == 0)
dst_align = 16;
}
+
+  if (MEM_P (orig_dst) && MEM_ALIGN (orig_dst) < dst_align)
+   {
+ orig_dst = shallow_copy_rtx (orig_dst);
+ set_mem_align (orig_dst, dst_align);
+   }
 }
 
   ofs = 0;

[gcc r15-1997] [libstdc++] [testsuite] require dfprt on some tests

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:26dfb3f2d30f6d49ed126add9d123dcc6566385f

commit r15-1997-g26dfb3f2d30f6d49ed126add9d123dcc6566385f
Author: Alexandre Oliva 
Date:   Fri Jul 12 05:42:19 2024 -0300

[libstdc++] [testsuite] require dfprt on some tests

On a target that doesn't enable decimal float components in libgcc
(because the libc doens't define all required FE_* macros), but whose
compiler supports _Decimal* types, the effective target requirement
dfp passes, but several tests won't link because the runtime support
they depend on is missing.  State their dfprt requirement.


for  libstdc++-v3/ChangeLog

* testsuite/decimal/binary-arith.cc: Require dfprt.
* testsuite/decimal/comparison.cc: Likewise.
* testsuite/decimal/compound-assignment.cc: Likewise.
* testsuite/decimal/compound-assignment-memfunc.cc: Likewise.
* testsuite/decimal/make-decimal.cc: Likewise.
* testsuite/decimal/pr54036-1.cc: Likewise.
* testsuite/decimal/pr54036-2.cc: Likewise.
* testsuite/decimal/pr54036-3.cc: Likewise.
* testsuite/decimal/unary-arith.cc: Likewise.

Diff:
---
 libstdc++-v3/testsuite/decimal/binary-arith.cc| 2 +-
 libstdc++-v3/testsuite/decimal/comparison.cc  | 2 +-
 libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc | 2 +-
 libstdc++-v3/testsuite/decimal/compound-assignment.cc | 2 +-
 libstdc++-v3/testsuite/decimal/make-decimal.cc| 2 +-
 libstdc++-v3/testsuite/decimal/pr54036-1.cc   | 2 +-
 libstdc++-v3/testsuite/decimal/pr54036-2.cc   | 2 +-
 libstdc++-v3/testsuite/decimal/pr54036-3.cc   | 2 +-
 libstdc++-v3/testsuite/decimal/unary-arith.cc | 2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/libstdc++-v3/testsuite/decimal/binary-arith.cc 
b/libstdc++-v3/testsuite/decimal/binary-arith.cc
index c10a8b6466cb..3eeed7ea9750 100644
--- a/libstdc++-v3/testsuite/decimal/binary-arith.cc
+++ b/libstdc++-v3/testsuite/decimal/binary-arith.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 
 // ISO/IEC TR 24733  3.2.8  Binary arithmetic operators.
 
diff --git a/libstdc++-v3/testsuite/decimal/comparison.cc 
b/libstdc++-v3/testsuite/decimal/comparison.cc
index cf34c8d74bad..424dd8bd2665 100644
--- a/libstdc++-v3/testsuite/decimal/comparison.cc
+++ b/libstdc++-v3/testsuite/decimal/comparison.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 
 // ISO/IEC TR 24733  3.2.9  Comparison operators.
 
diff --git a/libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc 
b/libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc
index 817d4bb10b1e..d520af9a68d4 100644
--- a/libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc
+++ b/libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 
 // ISO/IEC TR 24733  3.2.2.6  Compound assignment (decimal32).
 // ISO/IEC TR 24733  3.2.3.6  Compound assignment (decimal64).
diff --git a/libstdc++-v3/testsuite/decimal/compound-assignment.cc 
b/libstdc++-v3/testsuite/decimal/compound-assignment.cc
index 2d3e32585698..5aa87e78a739 100644
--- a/libstdc++-v3/testsuite/decimal/compound-assignment.cc
+++ b/libstdc++-v3/testsuite/decimal/compound-assignment.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 
 // ISO/IEC TR 24733  3.2.2.6  Compound assignment (decimal32).
 // ISO/IEC TR 24733  3.2.3.6  Compound assignment (decimal64).
diff --git a/libstdc++-v3/testsuite/decimal/make-decimal.cc 
b/libstdc++-v3/testsuite/decimal/make-decimal.cc
index aa75ac89d479..560196cb305e 100644
--- a/libstdc++-v3/testsuite/decimal/make-decimal.cc
+++ b/libstdc++-v3/testsuite/decimal/make-decimal.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 // { dg-options "-Wno-pedantic" }
 
 // ISO/IEC TR 24733  3.2.5  Initialization from coefficient and exponent.
diff --git a/libstdc++-v3/testsuite/decimal/pr54036-1.cc 
b/libstdc++-v3/testsuite/decimal/pr54036-1.cc
index 508738701ca0..a07e4c351651 100644
--- a/libstdc++-v3/testsuite/decimal/pr54036-1.cc
+++ b/libstdc++-v3/testsuite/decimal/pr54036-1.cc
@@ -15,7 +15,7 @@
 // with this library;

[gcc r15-1998] aarch64: Avoid alloca in target attribute parsing

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:7bcef7532b10040bb82567136a208d0c4560767d

commit r15-1998-g7bcef7532b10040bb82567136a208d0c4560767d
Author: Richard Sandiford 
Date:   Fri Jul 12 10:30:22 2024 +0100

aarch64: Avoid alloca in target attribute parsing

The handling of the target attribute used alloca to allocate
a copy of unverified user input, which could exhaust the stack
if the input is too long.  This patch converts it to auto_vecs
instead.

I wondered about converting it to use std::string, which we
already use elsewhere, but that would be more invasive and
controversial.

gcc/
* config/aarch64/aarch64.cc (aarch64_process_one_target_attr)
(aarch64_process_target_attr): Avoid alloca.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 7f0cc47d0f07..0d41a193ec18 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19405,8 +19405,10 @@ aarch64_process_one_target_attr (char *arg_str)
   return false;
 }
 
-  char *str_to_check = (char *) alloca (len + 1);
-  strcpy (str_to_check, arg_str);
+  auto_vec buffer;
+  buffer.safe_grow (len + 1);
+  char *str_to_check = buffer.address ();
+  memcpy (str_to_check, arg_str, len + 1);
 
   /* We have something like __attribute__ ((target ("+fp+nosimd"))).
  It is easier to detect and handle it explicitly here rather than going
@@ -19569,8 +19571,10 @@ aarch64_process_target_attr (tree args)
 }
 
   size_t len = strlen (TREE_STRING_POINTER (args));
-  char *str_to_check = (char *) alloca (len + 1);
-  strcpy (str_to_check, TREE_STRING_POINTER (args));
+  auto_vec buffer;
+  buffer.safe_grow (len + 1);
+  char *str_to_check = buffer.address ();
+  memcpy (str_to_check, TREE_STRING_POINTER (args), len + 1);
 
   if (len == 0)
 {

[gcc r14-10411] RISC-V: NO_WARNING preferred else value for RVV

[YunQiang Su via Gcc-cvs]

https://gcc.gnu.org/g:cff270707f107aff207f4afa73092a2d0731b032

commit r14-10411-gcff270707f107aff207f4afa73092a2d0731b032
Author: YunQiang Su 
Date:   Thu Jul 11 20:43:54 2024 +0800

RISC-V: NO_WARNING preferred else value for RVV

PR target/115840.

In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.

The problem is that `warn_uninit` will emit a warning:
  '({anonymous})' may be used uninitialized

Let's mark this tmp var as NO_WARNING.

This problem is found when I try to build glibc with V extension.

gcc

PR target/115840
* config/riscv/riscv.cc(riscv_preferred_else_value): Mark
tmp_var as NO_WARNING.

gcc/testsuite
* gcc.dg/vect/pr115840.c: New testcase.

(cherry picked from commit c6f38e5e6d900b8ed6a4f5c126d3197946cad4dd)

Diff:
---
 gcc/config/riscv/riscv.cc|  6 +-
 gcc/testsuite/gcc.dg/vect/pr115840.c | 11 +++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a599ced658c3..8aa34267c99b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10941,7 +10941,11 @@ riscv_preferred_else_value (unsigned ifn, tree 
vectype, unsigned int nops,
tree *ops)
 {
   if (riscv_v_ext_mode_p (TYPE_MODE (vectype)))
-return get_or_create_ssa_default_def (cfun, create_tmp_var (vectype));
+{
+  tree tmp_var = create_tmp_var (vectype);
+  TREE_NO_WARNING (tmp_var) = 1;
+  return get_or_create_ssa_default_def (cfun, tmp_var);
+}
 
   return default_preferred_else_value (ifn, vectype, nops, ops);
 }
diff --git a/gcc/testsuite/gcc.dg/vect/pr115840.c 
b/gcc/testsuite/gcc.dg/vect/pr115840.c
new file mode 100644
index ..09dc9e4eb7c2
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr115840.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-Wall -Werror" } */
+
+double loads[16];
+
+void
+foo (double loadavg[], int count)
+{
+  for (int i = 0; i < count; i++)
+loadavg[i] = loads[i] / 1.5;
+}

[gcc r11-11573] libstdc++: Add missing exports for ppc64le --with-long-double-format=ibm [PR105417]

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:30ffca55041518b76cfd59877250a740a615b5ba

commit r11-11573-g30ffca55041518b76cfd59877250a740a615b5ba
Author: Jonathan Wakely 
Date:   Fri Apr 29 12:17:13 2022 +0100

libstdc++: Add missing exports for ppc64le --with-long-double-format=ibm 
[PR105417]

The --with-long-double-abi=ibm build is missing some exports that are
present in the --with-long-double-abi=ieee build. Those symbols never
should have been exported at all, but now that they have been, they
should be exported consistently by both ibm and ieee.

This simply defines them as aliases for equivalent symbols that are
already present. The abi-tag on num_get::_M_extract_int isn't really
needed, because it only uses a std::string as a local variable, not in
the return type or function parameters, so it's safe to define the
_M_extract_int[abi:cxx11] symbols as aliases for the corresponding
function without the abi-tag.

This causes some new symbols to be added to the GLIBCXX_3.4.29 version
for the ibm long double build mode, but there is no advantage to adding
them to 3.4.30 for that build. That would just create more
inconsistencies.

libstdc++-v3/ChangeLog:

PR libstdc++/105417
* config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt:
Regenerate.
* src/c++11/compatibility-ldbl-alt128.cc [_GLIBCXX_USE_DUAL_ABI]:
Define __gnu_ieee128::num_get::_M_extract_int[abi:cxx11]
symbols as aliases for corresponding symbols without abi-tag.

(cherry picked from commit bb7cf39b05a216431a431499d0c36a6034f6acc4)

Diff:
---
 .../post/powerpc64-linux-gnu/baseline_symbols.txt  | 12 
 .../src/c++11/compatibility-ldbl-alt128.cc | 36 ++
 2 files changed, 48 insertions(+)

diff --git 
a/libstdc++-v3/config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt 
b/libstdc++-v3/config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt
index 941c96eb3ff4..e1cbf6510bd1 100644
--- a/libstdc++-v3/config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt
+++ b/libstdc++-v3/config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt
@@ -548,6 +548,12 @@ 
FUNC:_ZNKSt15basic_streambufIwSt11char_traitsIwEE6getlocEv@@GLIBCXX_3.4
 FUNC:_ZNKSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4
 FUNC:_ZNKSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4
 FUNC:_ZNKSt16bad_array_length4whatEv@@CXXABI_1.3.8
+FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intB5cxx11IjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
+FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intB5cxx11IlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
+FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intB5cxx11ImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
+FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intB5cxx11ItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
+FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intB5cxx11IxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
+FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intB5cxx11IyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
 
FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
 
FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
 
FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
@@ -579,6 +585,12 @@ 
FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traits
 
FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@@GLIBCXX_IEEE128_3.4.29
 
FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@@GLIBCXX_IEEE128_3.4.29
 
FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@@GLIBCXX_IEEE128_3.4.29
+FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intB5cxx11IjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@@GLIBCXX_IEEE128_3.4.29
+FUNC:_ZNKSt17__gnu_cxx_ieee1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intB5cxx11IlEES4_S4_S4_RSt8ios_baseRSt12_Ios_I

[gcc r14-10412] libstdc++: Fix std::to_array for trivial-ish types [PR115522]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:21c8708ba638f57cf904c8af3355318d9cf0f9e0

commit r14-10412-g21c8708ba638f57cf904c8af3355318d9cf0f9e0
Author: Jonathan Wakely 
Date:   Tue Jun 18 13:27:02 2024 +0100

libstdc++: Fix std::to_array for trivial-ish types [PR115522]

Due to PR c++/85723 the std::is_trivial trait is true for types with a
deleted default constructor, so the use of std::is_trivial in
std::to_array is not sufficient to ensure the type can be trivially
default constructed then filled using memcpy.

I also forgot that a type with a deleted assignment operator can still
be trivial, so we also need to check that it's assignable because the
is_constant_evaluated() path can't use memcpy.

Replace the uses of std::is_trivial with std::is_trivially_copyable
(needed for memcpy), std::is_trivially_default_constructible (needed so
that the default construction is valid and does no work) and
std::is_copy_assignable (needed for the constant evaluation case).

libstdc++-v3/ChangeLog:

PR libstdc++/115522
* include/std/array (to_array): Workaround the fact that
std::is_trivial is not sufficient to check that a type is
trivially default constructible and assignable.
* testsuite/23_containers/array/creation/115522.cc: New test.

(cherry picked from commit 510ce5eed69ee1bea9c2c696fe3b2301e16d1486)

Diff:
---
 libstdc++-v3/include/std/array |  8 --
 .../23_containers/array/creation/115522.cc | 33 ++
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/include/std/array b/libstdc++-v3/include/std/array
index 39695471e245..8710bf75924b 100644
--- a/libstdc++-v3/include/std/array
+++ b/libstdc++-v3/include/std/array
@@ -431,7 +431,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   static_assert(is_constructible_v<_Tp, _Tp&>);
   if constexpr (is_constructible_v<_Tp, _Tp&>)
{
- if constexpr (is_trivial_v<_Tp>)
+ if constexpr (is_trivially_copyable_v<_Tp>
+ && is_trivially_default_constructible_v<_Tp>
+ && is_copy_assignable_v<_Tp>)
{
  array, _Nm> __arr;
  if (!__is_constant_evaluated() && _Nm != 0)
@@ -460,7 +462,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   static_assert(is_move_constructible_v<_Tp>);
   if constexpr (is_move_constructible_v<_Tp>)
{
- if constexpr (is_trivial_v<_Tp>)
+ if constexpr (is_trivially_copyable_v<_Tp>
+ && is_trivially_default_constructible_v<_Tp>
+ && is_copy_assignable_v<_Tp>)
{
  array, _Nm> __arr;
  if (!__is_constant_evaluated() && _Nm != 0)
diff --git a/libstdc++-v3/testsuite/23_containers/array/creation/115522.cc 
b/libstdc++-v3/testsuite/23_containers/array/creation/115522.cc
new file mode 100644
index ..37073e002bdb
--- /dev/null
+++ b/libstdc++-v3/testsuite/23_containers/array/creation/115522.cc
@@ -0,0 +1,33 @@
+// { dg-do compile { target c++20 } }
+
+// PR libstdc++/115522 std::to_array no longer works for struct which is
+// trivial but not default constructible
+
+#include 
+
+void
+test_deleted_ctor()
+{
+  struct S
+  {
+S() = delete;
+S(int) { }
+  };
+
+  S arr[1] = {{1}};
+  auto arr1 = std::to_array(arr);
+  auto arr2 = std::to_array(std::move(arr));
+}
+
+void
+test_deleted_assignment()
+{
+  struct S
+  {
+void operator=(const S&) = delete;
+  };
+
+  S arr[1] = {};
+  auto a1 = std::to_array(arr);
+  auto a2 = std::to_array(std::move(arr));
+}

[gcc r14-10413] libstdc++: Fix unwanted #pragma messages from PSTL headers [PR113376]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:d920658cbb200729b7c2ad069fa4b6498e028ff1

commit r14-10413-gd920658cbb200729b7c2ad069fa4b6498e028ff1
Author: Jonathan Wakely 
Date:   Wed Jun 12 16:47:17 2024 +0100

libstdc++: Fix unwanted #pragma messages from PSTL headers [PR113376]

When we rebased the PSTL on upstream, in r14-2109-g3162ca09dbdc2e, a
change to how _PSTL_USAGE_WARNINGS is set was missed out, but the change
to how it's tested was included. This means that the macro is always
defined, so testing it with #ifdef (instead of using #if to test its
value) doesn't work as intended.

Revert the test to use #if again, since that part of the upstream change
was unnecessary in the first place (the macro is always defined, so
there's no need to use #ifdef to avoid -Wundef warnings).

libstdc++-v3/ChangeLog:

PR libstdc++/113376
* include/pstl/pstl_config.h: Use #if instead of #ifdef to test
the _PSTL_USAGE_WARNINGS macro.

(cherry picked from commit 99a1fe6c12c733fe4923a75a79d09a66ff8abcec)

Diff:
---
 libstdc++-v3/include/pstl/pstl_config.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/pstl/pstl_config.h 
b/libstdc++-v3/include/pstl/pstl_config.h
index ccb9dd32838d..e157e4d486f6 100644
--- a/libstdc++-v3/include/pstl/pstl_config.h
+++ b/libstdc++-v3/include/pstl/pstl_config.h
@@ -177,7 +177,7 @@
 
 #define _PSTL_PRAGMA_MESSAGE_IMPL(x) 
_PSTL_PRAGMA(message(_PSTL_STRING_CONCAT(_PSTL_PRAGMA_LOCATION, x)))
 
-#if defined(_PSTL_USAGE_WARNINGS)
+#if _PSTL_USAGE_WARNINGS
 #define _PSTL_PRAGMA_MESSAGE(x) _PSTL_PRAGMA_MESSAGE_IMPL(x)
 #define _PSTL_PRAGMA_MESSAGE_POLICIES(x) _PSTL_PRAGMA_MESSAGE_IMPL(x)
 #else

[gcc r13-8908] libstdc++: Fix std::to_array for trivial-ish types [PR115522]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:08463348c5cce84dc3c64ac4fbb20e2795ee104f

commit r13-8908-g08463348c5cce84dc3c64ac4fbb20e2795ee104f
Author: Jonathan Wakely 
Date:   Tue Jun 18 13:27:02 2024 +0100

libstdc++: Fix std::to_array for trivial-ish types [PR115522]

Due to PR c++/85723 the std::is_trivial trait is true for types with a
deleted default constructor, so the use of std::is_trivial in
std::to_array is not sufficient to ensure the type can be trivially
default constructed then filled using memcpy.

I also forgot that a type with a deleted assignment operator can still
be trivial, so we also need to check that it's assignable because the
is_constant_evaluated() path can't use memcpy.

Replace the uses of std::is_trivial with std::is_trivially_copyable
(needed for memcpy), std::is_trivially_default_constructible (needed so
that the default construction is valid and does no work) and
std::is_copy_assignable (needed for the constant evaluation case).

libstdc++-v3/ChangeLog:

PR libstdc++/115522
* include/std/array (to_array): Workaround the fact that
std::is_trivial is not sufficient to check that a type is
trivially default constructible and assignable.
* testsuite/23_containers/array/creation/115522.cc: New test.

(cherry picked from commit 510ce5eed69ee1bea9c2c696fe3b2301e16d1486)

Diff:
---
 libstdc++-v3/include/std/array |  8 --
 .../23_containers/array/creation/115522.cc | 33 ++
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/include/std/array b/libstdc++-v3/include/std/array
index edcac892b52d..dd9b4a0ab038 100644
--- a/libstdc++-v3/include/std/array
+++ b/libstdc++-v3/include/std/array
@@ -426,7 +426,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   static_assert(is_constructible_v<_Tp, _Tp&>);
   if constexpr (is_constructible_v<_Tp, _Tp&>)
{
- if constexpr (is_trivial_v<_Tp>)
+ if constexpr (is_trivially_copyable_v<_Tp>
+ && is_trivially_default_constructible_v<_Tp>
+ && is_copy_assignable_v<_Tp>)
{
  array, _Nm> __arr;
  if (!__is_constant_evaluated() && _Nm != 0)
@@ -455,7 +457,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   static_assert(is_move_constructible_v<_Tp>);
   if constexpr (is_move_constructible_v<_Tp>)
{
- if constexpr (is_trivial_v<_Tp>)
+ if constexpr (is_trivially_copyable_v<_Tp>
+ && is_trivially_default_constructible_v<_Tp>
+ && is_copy_assignable_v<_Tp>)
{
  array, _Nm> __arr;
  if (!__is_constant_evaluated() && _Nm != 0)
diff --git a/libstdc++-v3/testsuite/23_containers/array/creation/115522.cc 
b/libstdc++-v3/testsuite/23_containers/array/creation/115522.cc
new file mode 100644
index ..37073e002bdb
--- /dev/null
+++ b/libstdc++-v3/testsuite/23_containers/array/creation/115522.cc
@@ -0,0 +1,33 @@
+// { dg-do compile { target c++20 } }
+
+// PR libstdc++/115522 std::to_array no longer works for struct which is
+// trivial but not default constructible
+
+#include 
+
+void
+test_deleted_ctor()
+{
+  struct S
+  {
+S() = delete;
+S(int) { }
+  };
+
+  S arr[1] = {{1}};
+  auto arr1 = std::to_array(arr);
+  auto arr2 = std::to_array(std::move(arr));
+}
+
+void
+test_deleted_assignment()
+{
+  struct S
+  {
+void operator=(const S&) = delete;
+  };
+
+  S arr[1] = {};
+  auto a1 = std::to_array(arr);
+  auto a2 = std::to_array(std::move(arr));
+}

[gcc r15-1999] s390: Align *cjump_64 and *icjump_64

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d

commit r15-1999-g56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d
Author: Stefan Schulze Frielinghaus 
Date:   Fri Jul 12 13:27:08 2024 +0200

s390: Align *cjump_64 and *icjump_64

During machine reorg we optimize backward jumps and transform insns as
e.g.

(jump_insn 118 117 119 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(label_ref 134)
(pc))) "dec_math_1.f90":204:8 discrim 1 2161 {*cjump_64}
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 134)

into

(jump_insn 118 117 432 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(pc)
(label_ref 433))) "dec_math_1.f90":204:8 discrim 1 -1
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 433)

The latter is not recognized anymore since *icjump_64 only matches
CC_REGNUM against zero.  Fixed by aligning *cjump_64 and *icjump_64.

gcc/ChangeLog:

* config/s390/s390.md (*icjump_64): Allow raw CC comparisons,
i.e., any constant integer between 0 and 15 for CC comparisons.

Diff:
---
 gcc/config/s390/s390.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 1311a5f01cf3..2555006bb4b9 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -9530,7 +9530,8 @@
 (define_insn "*icjump_64"
   [(set (pc)
 (if_then_else
-  (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
+  (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
+  (match_operand 2 
"const_int_operand" "")])
   (pc)
   (label_ref (match_operand 0 "" ""]
   ""

[gcc r15-2000] i386: Some AVX512 ternlog expansion refinements.

[Roger Sayle via Gcc-cvs]

https://gcc.gnu.org/g:6b5d263f2c90c3e22cdf576970c94bca268c5296

commit r15-2000-g6b5d263f2c90c3e22cdf576970c94bca268c5296
Author: Roger Sayle 
Date:   Fri Jul 12 12:30:56 2024 +0100

i386: Some AVX512 ternlog expansion refinements.

This patch replaces the calls to force_reg in ix86_expand_ternlog_binop
and ix86_expand_ternlog with gen_reg_rtx and emit_move_insn.
This patch also cleans up whitespace, consistently uses CONST_VECTOR_P
instead of GET_CODE and tweaks checks for ix86_ternlog_leaf_p (for
example where vpandn may take a memory operand).

2024-07-12  Roger Sayle  
Hongtao Liu  

gcc/ChangeLog
* config/i386/i386-expand.cc (ix86_broadcast_from_constant):
Use CONST_VECTOR_P instead of comparison against GET_CODE.
(ix86_gen_bcst_mem): Likewise.
(ix86_ternlog_leaf_p): Likewise.
(ix86_ternlog_operand_p): ix86_ternlog_leaf_p is always true for
vector_all_ones_operand.
(ix86_expand_ternlog_bin_op): Use CONST_VECTOR_P instead of
equality comparison against GET_CODE.  Replace call to force_reg
with gen_reg_rtx and emit_move_insn (for VEC_DUPLICATE broadcast).
Check for !register_operand instead of memory_operand.
Support CONST_VECTORs by calling force_const_mem.
(ix86_expand_ternlog): Fix indentation whitespace.
Allow ix86_ternlog_leaf_p as ix86_expand_ternlog_andnot's second
operand. Use CONST_VECTOR_P instead of equality against GET_CODE.
Use gen_reg_rtx and emit_move_insn for ~a, ~b and ~c cases.

Diff:
---
 gcc/config/i386/i386-expand.cc | 126 +
 1 file changed, 78 insertions(+), 48 deletions(-)

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index abc702d3ff27..cfcfdd94e8f0 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -613,7 +613,7 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
 return nullptr;
 
   rtx constant = get_pool_constant (XEXP (op, 0));
-  if (GET_CODE (constant) != CONST_VECTOR)
+  if (!CONST_VECTOR_P (constant))
 return nullptr;
 
   /* There could be some rtx like
@@ -623,7 +623,7 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
 {
   constant = simplify_subreg (mode, constant, GET_MODE (constant),
  0);
-  if (constant == nullptr || GET_CODE (constant) != CONST_VECTOR)
+  if (constant == nullptr || !CONST_VECTOR_P (constant))
return nullptr;
 }
 
@@ -25561,7 +25561,7 @@ static rtx
 ix86_gen_bcst_mem (machine_mode mode, rtx x)
 {
   if (!TARGET_AVX512F
-  || GET_CODE (x) != CONST_VECTOR
+  || !CONST_VECTOR_P (x)
   || (!TARGET_AVX512VL
  && (GET_MODE_SIZE (mode) != 64 || !TARGET_EVEX512))
   || !VALID_BCST_MODE_P (GET_MODE_INNER (mode))
@@ -25751,7 +25751,7 @@ ix86_ternlog_leaf_p (rtx op, machine_mode mode)
  problems splitting instructions.  */
   return register_operand (op, mode)
 || MEM_P (op)
-|| GET_CODE (op) == CONST_VECTOR
+|| CONST_VECTOR_P (op)
 || bcst_mem_operand (op, mode);
 }
 
@@ -25801,8 +25801,7 @@ ix86_ternlog_operand_p (rtx op)
   op1 = XEXP (op, 1);
   /* Prefer pxor, or one_cmpl2.  */
   if (ix86_ternlog_leaf_p (XEXP (op, 0), mode)
- && (ix86_ternlog_leaf_p (op1, mode)
- || vector_all_ones_operand (op1, mode)))
+ && ix86_ternlog_leaf_p (XEXP (op, 1), mode))
return false;
   break;
 
@@ -25822,15 +25821,20 @@ ix86_expand_ternlog_binop (enum rtx_code code, 
machine_mode mode,
   if (GET_MODE (op1) != mode)
 op1 = gen_lowpart (mode, op1);
 
-  if (GET_CODE (op0) == CONST_VECTOR)
+  if (CONST_VECTOR_P (op0))
 op0 = validize_mem (force_const_mem (mode, op0));
-  if (GET_CODE (op1) == CONST_VECTOR)
+  if (CONST_VECTOR_P (op1))
 op1 = validize_mem (force_const_mem (mode, op1));
 
-  if (memory_operand (op0, mode))
+  if (!register_operand (op0, mode))
 {
-  if (memory_operand (op1, mode))
-   op0 = force_reg (mode, op0);
+  if (!register_operand (op1, mode))
+   {
+ /* We can't use force_reg (op0, mode).  */
+ rtx reg = gen_reg_rtx (mode);
+ emit_move_insn (reg, op0);
+ op0 = reg;
+   }
   else
std::swap (op0, op1);
 }
@@ -25849,6 +25853,8 @@ ix86_expand_ternlog_andnot (machine_mode mode, rtx op0, 
rtx op1, rtx target)
   op0 = gen_rtx_NOT (mode, op0);
   if (GET_MODE (op1) != mode)
 op1 = gen_lowpart (mode, op1);
+  if (CONST_VECTOR_P (op1))
+op1 = validize_mem (force_const_mem (mode, op1));
   emit_move_insn (target, gen_rtx_AND (mode, op0, op1));
   return target;
 }
@@ -25885,9 +25891,9 @@ ix86_expand_ternlog (machine_mode mode, rtx op0, rtx 
op1, rtx op2, int idx,
 {
 case 0x00:
   if ((!op0 || !side_effects_p (op0))
-   

[gcc r15-2001] s390: Fix output template for movv1qi

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:e6680d3f392f7f7cc2a1515276213e21e9eeab1c

commit r15-2001-ge6680d3f392f7f7cc2a1515276213e21e9eeab1c
Author: Stefan Schulze Frielinghaus 
Date:   Fri Jul 12 13:40:19 2024 +0200

s390: Fix output template for movv1qi

Although for instructions MVI and MVIY it does not make a difference
whether the immediate is interpreted as signed or unsigned, GAS expects
unsigned immediates for instruction format SI_URD.

gcc/ChangeLog:

* config/s390/vector.md (mov): Fix output template for
movv1qi.

Diff:
---
 gcc/config/s390/vector.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 40de0c75a7cf..26fd505f2cd9 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -368,8 +368,8 @@
lr\t%0,%1
mvi\t%0,0
mviy\t%0,0
-   mvi\t%0,-1
-   mviy\t%0,-1
+   mvi\t%0,255
+   mviy\t%0,255
lhi\t%0,0
lhi\t%0,-1
llc\t%0,%1

[gcc r15-2002] s390: Fully exploit vgm, vgbm, vrepi

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:61715e9340ab8941d40d62158fe437e9dbe3e068

commit r15-2002-g61715e9340ab8941d40d62158fe437e9dbe3e068
Author: Stefan Schulze Frielinghaus 
Date:   Fri Jul 12 13:42:08 2024 +0200

s390: Fully exploit vgm, vgbm, vrepi

Currently instructions vgm and vrepi are utilized only for constant
vectors where the element mode equals the element mode of the
corresponding instruction.  This patch lifts this restriction by making
use of those instructions for constant vectors even if element modes
do not coincide.  For example, the constant vector

  (v2di){0x7ffe7ffe, 0x7ffe7ffe}

can be loaded via vgmf %v0,1,30.  Similar, the constant vector

  (v4si){0x, 0x, 0x, 0x}

can be loaded via vrepiq %v0,-86.

Analog, if the element mode of a constant vector is smaller than the
element mode of a corresponding instruction, we still may make use of
those instructions.  For example, the constant vector

  (v4si){0x7fff, 0xfffe, 0x7fff, 0xfffe}

can be loaded via vgmg %v0,17,46.  Similar, the constant vector

  (v4si){-1, -16643, -1, -16643}

can be loaded via vrepig %v0,-16643.

Additionally this patch enables vgm, vgbm, vrepi for partial vectors,
i.e., vectors of size less than 16 bytes.  Basically this is done by
treating a vector as a full vector resulting in replicating constants
into the ignored bits whereas vgbm sets those to zero.

Furthermore, there is no restriction to integer vectors anymore, i.e.,
supporting scalars of mode up to and including TI and TF and also
floating-point vectors.

Here are some numbers how often instructions are emitted for SPEC 2017:

w/o patch w/ patch
vgbm  140  365
vgm 1750824452
vrepi1360 2775

I expect most (maybe even all) to save us a load from the literal pool.

gcc/ChangeLog:

* config/s390/2964.md: Remove extended mnemonics for vgm.
* config/s390/3906.md: Remove extended mnemonics for vgm.
* config/s390/3931.md: Remove extended mnemonics for vgm.
* config/s390/8561.md: Remove extended mnemonics for vgm.
* config/s390/constraints.md (jKK): Remove constraint.
(jzz): Add constraint.
* config/s390/s390-protos.h (s390_contiguous_bitmask_vector_p):
Add prototype.
(s390_constant_via_vgm_p): Add prototype.
(s390_constant_via_vrepi_p): Add prototype.
* config/s390/s390.cc (s390_contiguous_bitmask_vector_p): New
function.
(s390_constant_via_vgm_vrepi_helper): New function.
(s390_constant_via_vgm_p): New function.
(s390_constant_via_vgbm_p): For the sake of symmetry rename
s390_bytemask_vector_p into s390_constant_via_vgbm_p.
(s390_bytemask_vector_p): Deal with non-integer and partial
vectors.
(s390_constant_via_vrepi_p): New function.
(s390_legitimate_constant_p): Allow partial vectors.
(legitimate_reload_constant_p): Fix indentation.
(legitimate_reload_vector_constant_p): Restrict to constraints
j00, jm1, jxx, jyy, jzz only, i.e., allow partial vectors.
(s390_expand_vec_init): Also make use of vrepi if possible.
(print_operand): Add q,p,r for vgm,vrepi,vgbm, respectively.
Remove e,s,t for constant vectors.
* config/s390/s390.md (movti): Add variants utilizing
vgbm,vgm,vrepi.
* config/s390/vector.md (mov): Adapt variants
for vgbm,vgm,vrepi for the new scheme.
(mov): Adapt variants for vgbm,vgm for the new
scheme and add vrepi variant for modes V_8,V_16,V_32,V_64.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-copysign.c: Change to non-extended
mnemonic.
* gcc.target/s390/vector/vec-genmask-1.c: Change to non-extended
mnemonic.
* gcc.target/s390/vector/vec-init-1.c: Change to non-extended
mnemonic.
* gcc.target/s390/vector/vec-vrepi-1.c: Change to non-extended
mnemonic.
* gcc.target/s390/zvector/autovec-double-quiet-uneq.c: Change to
non-extended mnemonic.
* gcc.target/s390/zvector/autovec-float-quiet-uneq.c: Change to
non-extended mnemonic.
* gcc.target/s390/zvector/vec-genmask-1.c: Change to
non-extended mnemonic.
* gcc.target/s390/zvector/vec-splat-1.c: Change to non-extended
mnemonic.
* gcc.target/s390/zvector/vec-splat-2.c: Change to non-extended
mnemonic.
* gcc.target/s390/vector/vgbm-double-1.c: New test.
* gcc.target/s390/vector/vgbm-

[gcc r15-2003] c++: Introduce USING_DECLs for non-function usings [PR114683]

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:d6bf4b1c93221118b3008a878ec508f6412dfc55

commit r15-2003-gd6bf4b1c93221118b3008a878ec508f6412dfc55
Author: Nathaniel Shead 
Date:   Thu Jun 27 11:08:15 2024 +1000

c++: Introduce USING_DECLs for non-function usings [PR114683]

With modules, a non-function using-declaration is not completely
interchangable with the declaration that it refers to; in particular,
such a using-declaration may be exported without revealing the name of
the entity it refers to.

This patch fixes this by building USING_DECLs for all using-declarations
that bind a non-function from a different scope.  These new decls can
than have purviewness and exportingness attached to them without
affecting the decl that they refer to.

We do this for all such usings, not just usings that may be revealed in
a module; this way we can verify the change in representation against
the (more comprehensive) non-modules testsuites, and in a future patch
we can use the locations of these using-decls to enhance relevant
diagnostics.

Another possible approach would be to reuse OVERLOADs for this, as is
already done within add_binding_entity for modules.  I didn't do this
because lots of code (as well as the names of the accessors) makes
assumptions that OVERLOADs refer to function overload sets, and so
splitting this up reduced semantic burden and made it easier to avoid
unintentional changes.  This did mean that we need to move out the
definitions of ovl_iterator::{purview,exporting}_p, because the
structures for module decls are declared later on in cp-tree.h.

Building USING_DECLs changed a couple of code paths when adjusting
bindings; in particular, pushdecl recognises global using-declarations
as usings now, and so checks fall through to update_binding.  To not
regress g++.dg/lookup/linkage2.C the checks for 'extern' declarations no
longer were sufficient (they don't handle 'extern "C"'); but
duplicate_decls performed all the relevant checks anyway.

Otherwise in general we strip using-decls from all lookup_* functions
where necessary.  Over time for diagnostics purposes it would probably
be good to slowly revert this (especially e.g. lookup_elaborated_type
causes some diagnostic quality regressions here) but this patch doesn't
do so to minimise churn.

This patch also tries not to build USING_DECLs when just redeclaring an
existing declaration, and instead reveals that declaration in-place.
This requires reworking some logic handling CONST_DECLs in module
streaming, since a non-using CONST_DECL may now be exported indepenently
of its containing enum.

'add_binding_entity' needs to explicitly write the names of unscoped
enumerators so that lazy loading will trigger when the name is found by
name lookup; it does this by pretending that the enum declarations are
always usings so that it doesn't double-write definitions.  By also
checking if the enumerator was marked purview/exported we can use that
to override a non-purview/non-exported TYPE_DECL and ensure it's made
visible regardless.

When reading we should get the exported flag on the enumeration
constant, and so should properly create a binding for it.  We don't need
to do anything to handle importedness as that checking is skipped for
EK_USINGs.

Some other places assume that module information for a CONST_DECL
inherits module information from its containing type.  This includes:

- get_originating_module_decl, for determining if the name was imported
  or has module attachment; I don't /think/ this change should affect
  that, so I'm leaving this untouched.

- binding_cmp, for sorting by exportedness; since now an enumerator
  could be exported without the containing decl being exported, we need
  to handle this here too.

PR c++/114683

gcc/cp/ChangeLog:

* cp-tree.h (class ovl_iterator): Move definitions of purview_p
and exporting_p to name-lookup.cc.
* module.cc (depset::hash::add_binding_entity): Strip
using-decls.  Remove workarounds.  Handle CONST_DECLs with
different purview/exported from their enum.
(enum ct_bind_flags): Remove unnecessary cbf_wrapped flag.
(module_state::write_cluster): Likewise.
(module_state::read_cluster): Build USING_DECL for non-function
usings.
(binding_cmp): Handle CONST_DECLs with different purview and/or
exported from their enum.
(set_instantiating_module): Support CONST_DECLs.
* name-lookup.cc (get_fixed_binding_slot): Strip USING_DECLs.
(name_lookup::process_binding): Strip USING_DECLs.
(name_lookup::process_module_binding): Remove workaround.
(updat

[gcc r15-2004] c++/modules: Handle redefinitions of using-decls

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:1f7a21c6e85d553e7b5114e5ca1395118478dddf

commit r15-2004-g1f7a21c6e85d553e7b5114e5ca1395118478dddf
Author: Nathaniel Shead 
Date:   Fri Jul 5 13:52:01 2024 +1000

c++/modules: Handle redefinitions of using-decls

This fixes an ICE exposed by supporting exported non-function
using-decls.  Sometimes when preparing to define a class, xref_tag will
find a using-decl belonging to a different namespace, which triggers the
checking_assert in modules handling.

Ideally I feel that 'lookup_and_check_tag' should be told whether we're
about to define the type and handle erroring on redefinitions itself to
avoid this issue (and provide better diagnostics by acknowledging the
using-declaration), but this is complicated with the current
fragmentation of definition checking.  So for this patch we just fixup
the assertion and ensure that pushdecl properly errors on the
conflicting declaration later.

gcc/cp/ChangeLog:

* decl.cc (xref_tag): Move assertion into condition.
* name-lookup.cc (check_module_override): Check for conflicting
types and using-decls.

gcc/testsuite/ChangeLog:

* g++.dg/modules/using-19_a.C: New test.
* g++.dg/modules/using-19_b.C: New test.

Signed-off-by: Nathaniel Shead 

Diff:
---
 gcc/cp/decl.cc|  6 --
 gcc/cp/name-lookup.cc | 32 +--
 gcc/testsuite/g++.dg/modules/using-19_a.C | 18 +
 gcc/testsuite/g++.dg/modules/using-19_b.C | 10 ++
 4 files changed, 54 insertions(+), 12 deletions(-)

diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc
index 4ffc9a6dad25..e7bb4fa30892 100644
--- a/gcc/cp/decl.cc
+++ b/gcc/cp/decl.cc
@@ -16737,12 +16737,14 @@ xref_tag (enum tag_types tag_code, tree name,
  if (CLASS_TYPE_P (t) && CLASSTYPE_IS_TEMPLATE (t))
maybe_tmpl = CLASSTYPE_TI_TEMPLATE (t);
 
+ /* FIXME: we should do a more precise check for redefinitions
+of a conflicting using-declaration here, as these diagnostics
+are not ideal.  */
  if (DECL_LANG_SPECIFIC (decl)
  && DECL_MODULE_IMPORT_P (decl)
- && TREE_CODE (CP_DECL_CONTEXT (decl)) == NAMESPACE_DECL)
+ && CP_DECL_CONTEXT (decl) == current_namespace)
{
  /* Push it into this TU's symbol slot.  */
- gcc_checking_assert (current_namespace == CP_DECL_CONTEXT (decl));
  if (maybe_tmpl != decl)
/* We're in the template parm binding level.
   Pushtag has logic to slide under that, but we're
diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc
index e5f8562105e1..361dc3d953d1 100644
--- a/gcc/cp/name-lookup.cc
+++ b/gcc/cp/name-lookup.cc
@@ -3782,18 +3782,30 @@ check_module_override (tree decl, tree mvec, bool 
hiding,
  /* Errors could cause there to be nothing.  */
  continue;
 
+   tree type = NULL_TREE;
if (STAT_HACK_P (bind))
- /* We do not have to check STAT_TYPE here, the xref_tag
-machinery deals with that problem. */
- bind = STAT_VISIBLE (bind);
+ {
+   /* If there was a matching STAT_TYPE here then xref_tag
+  should have found it, but we need to check anyway because
+  a conflicting using-declaration may exist.  */
+   if (STAT_TYPE_VISIBLE_P (bind))
+ type = STAT_TYPE (bind);
+   bind = STAT_VISIBLE (bind);
+ }
 
-   for (ovl_iterator iter (bind); iter; ++iter)
- if (!iter.using_p ())
-   {
- match = duplicate_decls (decl, *iter, hiding);
- if (match)
-   goto matched;
-   }
+   if (type)
+ {
+   match = duplicate_decls (decl, strip_using_decl (type), hiding);
+   if (match)
+ goto matched;
+ }
+
+   for (ovl_iterator iter (strip_using_decl (bind)); iter; ++iter)
+ {
+   match = duplicate_decls (decl, *iter, hiding);
+   if (match)
+ goto matched;
+ }
   }
 
   if (TREE_PUBLIC (scope) && TREE_PUBLIC (STRIP_TEMPLATE (decl))
diff --git a/gcc/testsuite/g++.dg/modules/using-19_a.C 
b/gcc/testsuite/g++.dg/modules/using-19_a.C
new file mode 100644
index ..693a70ce7d46
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/using-19_a.C
@@ -0,0 +1,18 @@
+// { dg-additional-options "-fmodules-ts -Wno-global-module" }
+// { dg-module-cmi M }
+
+module;
+
+namespace hidden {
+  struct S {};
+  enum E { e };
+  void f();
+}
+
+export module M;
+export namespace exposed {
+  using hidden::S;
+  using hidden::E;
+  using hidden::e;
+  using hidden::f;
+}
diff --git a/gcc/testsuite/g++.dg/modules/using-19_b.C 
b/gcc/testsuite/g++.dg/modules/using-19_b.C
new file mode 100644
index ..dbe8d9f3c01e
--- /dev/null
++

[gcc r15-2005] c++/modules: Add testcase for fixed issue with usings [PR115798]

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:13757e50ff0b4e0dccfabc67b1322a2724bf3a5c

commit r15-2005-g13757e50ff0b4e0dccfabc67b1322a2724bf3a5c
Author: Nathaniel Shead 
Date:   Fri Jul 12 22:59:19 2024 +1000

c++/modules: Add testcase for fixed issue with usings [PR115798]

This issue was fixed by r15-2003-gd6bf4b1c932211, but seems worth adding
to the testsuite.

PR c++/115798

gcc/testsuite/ChangeLog:

* g++.dg/modules/using-26_a.C: New test.
* g++.dg/modules/using-26_b.C: New test.
* g++.dg/modules/using-26_c.C: New test.

Signed-off-by: Nathaniel Shead 

Diff:
---
 gcc/testsuite/g++.dg/modules/using-26_a.C | 15 +++
 gcc/testsuite/g++.dg/modules/using-26_b.C | 10 ++
 gcc/testsuite/g++.dg/modules/using-26_c.C |  9 +
 3 files changed, 34 insertions(+)

diff --git a/gcc/testsuite/g++.dg/modules/using-26_a.C 
b/gcc/testsuite/g++.dg/modules/using-26_a.C
new file mode 100644
index ..adab83d42433
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/using-26_a.C
@@ -0,0 +1,15 @@
+// PR c++/115798
+// { dg-additional-options "-fmodules-ts" }
+// { dg-module-cmi base }
+
+module;
+#include 
+export module base;
+
+export {
+  using ::int8_t;
+}
+
+export namespace std {
+  using std::int8_t;
+}
diff --git a/gcc/testsuite/g++.dg/modules/using-26_b.C 
b/gcc/testsuite/g++.dg/modules/using-26_b.C
new file mode 100644
index ..06ed599df41e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/using-26_b.C
@@ -0,0 +1,10 @@
+// PR c++/115798
+// { dg-additional-options "-fmodules-ts" }
+// { dg-module-cmi xstd }
+
+export module xstd;
+import base;
+
+export namespace std {
+  using std::int8_t;
+}
diff --git a/gcc/testsuite/g++.dg/modules/using-26_c.C 
b/gcc/testsuite/g++.dg/modules/using-26_c.C
new file mode 100644
index ..68f45cacb82e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/using-26_c.C
@@ -0,0 +1,9 @@
+// PR c++/115798
+// { dg-additional-options "-fmodules-ts" }
+
+import xstd;
+import base;
+
+int main() {
+  static_assert(__is_same(int8_t, std::int8_t));
+}

[gcc r15-2006] [RISC-V] Avoid unnecessary sign extension after memcmp

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:ae829a27785307232e4db0df6a30ca275941b613

commit r15-2006-gae829a27785307232e4db0df6a30ca275941b613
Author: Jeff Law 
Date:   Fri Jul 12 07:53:41 2024 -0600

[RISC-V] Avoid unnecessary sign extension after memcmp

Similar to the str[n]cmp work, this adjusts the block compare expansion to 
do
its work in X mode with an appropriate lowpart extraction of the results at 
the
end of the sequence.

This has gone through my tester on rv32 and rv64, but that's it. Waiting on
pre-commit testing before moving forward.

gcc/

* config/riscv/riscv-string.cc 
(emit_memcmp_scalar_load_and_compare):
Set RESULT directly rather than using a temporary.
(emit_memcmp_scalar_result_calculation): Similarly.
(riscv_expand_block_compare_scalar): Use CONST0_RTX rather than
generating new RTL.
* config/riscv/riscv.md (cmpmemsi): Pass an X mode temporary to the
expansion routines.  If necessary extract low part of the word to 
store
in final result location.

Diff:
---
 gcc/config/riscv/riscv-string.cc | 15 ++-
 gcc/config/riscv/riscv.md| 14 --
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 4736228e6f14..80d22e87d571 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -663,9 +663,7 @@ emit_memcmp_scalar_load_and_compare (rtx result, rtx src1, 
rtx src2,
   /* Fast-path for a single byte.  */
   if (cmp_bytes == 1)
{
- rtx tmp = gen_reg_rtx (Xmode);
- do_sub3 (tmp, data1, data2);
- emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+ do_sub3 (result, data1, data2);
  emit_jump_insn (gen_jump (final_label));
  emit_barrier (); /* No fall-through.  */
  return;
@@ -702,12 +700,11 @@ emit_memcmp_scalar_result_calculation (rtx result, rtx 
data1, rtx data2)
   /* Get bytes in big-endian order and compare as words.  */
   do_bswap2 (data1, data1);
   do_bswap2 (data2, data2);
+
   /* Synthesize (data1 >= data2) ? 1 : -1 in a branchless sequence.  */
-  rtx tmp = gen_reg_rtx (Xmode);
-  emit_insn (gen_slt_3 (LTU, Xmode, Xmode, tmp, data1, data2));
-  do_neg2 (tmp, tmp);
-  do_ior3 (tmp, tmp, const1_rtx);
-  emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+  emit_insn (gen_slt_3 (LTU, Xmode, Xmode, result, data1, data2));
+  do_neg2 (result, result);
+  do_ior3 (result, result, const1_rtx);
 }
 
 /* Expand memcmp using scalar instructions (incl. Zbb).
@@ -773,7 +770,7 @@ riscv_expand_block_compare_scalar (rtx result, rtx src1, 
rtx src2, rtx nbytes)
   data1, data2,
   diff_label, final_label);
 
-  emit_insn (gen_rtx_SET (result, gen_rtx_CONST_INT (SImode, 0)));
+  emit_move_insn (result, CONST0_RTX (GET_MODE (result)));
   emit_jump_insn (gen_jump (final_label));
   emit_barrier (); /* No fall-through.  */
 
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2e2379dfca4f..5dee837a5878 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2675,9 +2675,19 @@
   operands[2], operands[3]))
 DONE;
 
-  if (riscv_expand_block_compare (operands[0], operands[1], operands[2],
+  rtx temp = gen_reg_rtx (word_mode);
+  if (riscv_expand_block_compare (temp, operands[1], operands[2],
   operands[3]))
-DONE;
+{
+  if (TARGET_64BIT)
+   {
+ temp = gen_lowpart (SImode, temp);
+ SUBREG_PROMOTED_VAR_P (temp) = 1;
+ SUBREG_PROMOTED_SET (temp, SRP_SIGNED);
+   }
+  emit_move_insn (operands[0], temp);
+  DONE;
+}
   else
 FAIL;
 })

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add SiFive extensions, xsfvcp and xsfcease

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:68a2ba4a346992f1399abb410c5fb788aa9bca25

commit 68a2ba4a346992f1399abb410c5fb788aa9bca25
Author: Kito Cheng 
Date:   Tue Jul 9 15:50:57 2024 +0800

RISC-V: Add SiFive extensions, xsfvcp and xsfcease

We have already upstreamed these extensions into binutils, and now we need 
GCC
to recognize these extensions and pass them to binutils as well. We also 
plan
to upstream intrinsics in the near future. :)

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_implied_info): Add 
xsfvcp.
(riscv_ext_version_table): Add xsfvcp, xsfcease.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv.opt (riscv_sifive_subext): New.
(XSFVCP): New.
(XSFCEASE): New.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-sf-1.c: New.
* gcc.target/riscv/predef-sf-2.c: New.

(cherry picked from commit 3ea47ea1fcab95fd1b80acc724fdbb27fc436985)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  |  8 
 gcc/config/riscv/riscv.opt   |  7 +++
 gcc/testsuite/gcc.target/riscv/predef-sf-1.c | 19 +++
 gcc/testsuite/gcc.target/riscv/predef-sf-2.c | 14 ++
 4 files changed, 48 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 3c4178c19c99..d883efa7a3ab 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -216,6 +216,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"ssstateen", "zicsr"},
   {"sstc", "zicsr"},
 
+  {"xsfvcp", "zve32x"},
+
   {NULL, NULL}
 };
 
@@ -415,6 +417,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xsfvcp",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1822,6 +1827,9 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"xventanacondops", &gcc_options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
+  {"xsfvcp",   &gcc_options::x_riscv_sifive_subext, MASK_XSFVCP},
+  {"xsfcease", &gcc_options::x_riscv_sifive_subext, MASK_XSFCEASE},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 32a0dda58439..a1d70b636382 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -507,6 +507,13 @@ int riscv_xventana_subext
 
 Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
 
+TargetVariable
+int riscv_sifive_subext
+
+Mask(XSFVCP) Var(riscv_sifive_subext)
+
+Mask(XSFCEASE) Var(riscv_sifive_subext)
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-1.c 
b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
new file mode 100644
index ..d6c07e7d9207
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfvcp -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
+#endif
+
+
+#if !defined(__riscv_xsfvcp)
+#error "__riscv_xsfvcp"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-2.c 
b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
new file mode 100644
index ..dcb746bcd260
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfcease -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xsfcease)
+#error "__riscv_xsfvcp"
+#endif
+
+  return 0;
+}

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:d39d88ed512ae6affbd2f5128b1e55d92d8f5c0a

commit d39d88ed512ae6affbd2f5128b1e55d92d8f5c0a
Author: xuli 
Date:   Thu Jul 11 04:29:11 2024 +

RISC-V: Disable misaligned vector access in hook 
riscv_slow_unaligned_access[PR115862]

The reason is that in the following code, icode = movmisalignv8si has
already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is
allowed by targetm.slow_unaligned_access,which is contradictory.

(((icode = optab_handler (movmisalign_optab, mode))
   != CODE_FOR_nothing)
  || targetm.slow_unaligned_access (mode, align))

misaligned vector access should be enabled by -mno-vector-strict-align 
option.

PR target/115862

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable 
vector misalign.

Signed-off-by: Li Xu 
(cherry picked from commit 63d7d5998e3768f6e3703c29e8774e8b54af108c)

Diff:
---
 gcc/config/riscv/riscv.cc  |  5 ++-
 gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c | 52 ++
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ce73c18f88f8..8a8826deac17 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10269,9 +10269,10 @@ riscv_cannot_copy_insn_p (rtx_insn *insn)
 /* Implement TARGET_SLOW_UNALIGNED_ACCESS.  */
 
 static bool
-riscv_slow_unaligned_access (machine_mode, unsigned int)
+riscv_slow_unaligned_access (machine_mode mode, unsigned int)
 {
-  return riscv_slow_unaligned_access_p;
+  return VECTOR_MODE_P (mode) ? TARGET_VECTOR_MISALIGN_SUPPORTED
+ : riscv_slow_unaligned_access_p;
 }
 
 static bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
new file mode 100644
index ..3cbc3c3a0ea4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcv_zvl512b -mabi=lp64d" } */
+
+struct mallinfo2
+{
+  int arena;
+  int ordblks;
+  int smblks;
+  int hblks;
+  int hblkhd;
+  int usmblks;
+  int fsmblks;
+  int uordblks;
+  int fordblks;
+  int keepcost;
+};
+
+struct mallinfo
+{
+  int arena;
+  int ordblks;
+  int smblks;
+  int hblks;
+  int hblkhd;
+  int usmblks;
+  int fsmblks;
+  int uordblks;
+  int fordblks;
+  int keepcost;
+};
+
+struct mallinfo
+__libc_mallinfo (void)
+{
+  struct mallinfo m;
+  struct mallinfo2 m2;
+
+  m.arena = m2.arena;
+  m.ordblks = m2.ordblks;
+  m.smblks = m2.smblks;
+  m.hblks = m2.hblks;
+  m.hblkhd = m2.hblkhd;
+  m.usmblks = m2.usmblks;
+  m.fsmblks = m2.fsmblks;
+  m.uordblks = m2.uordblks;
+  m.fordblks = m2.fordblks;
+  m.keepcost = m2.keepcost;
+
+  return m;
+}
+
+/* { dg-final { scan-assembler {vle32\.v} } } */

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: NO_WARNING preferred else value for RVV

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:6322f7af2b8d41d5a298af66b5200d0c6ac79191

commit 6322f7af2b8d41d5a298af66b5200d0c6ac79191
Author: YunQiang Su 
Date:   Thu Jul 11 20:43:54 2024 +0800

RISC-V: NO_WARNING preferred else value for RVV

PR target/115840.

In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.

The problem is that `warn_uninit` will emit a warning:
  '({anonymous})' may be used uninitialized

Let's mark this tmp var as NO_WARNING.

This problem is found when I try to build glibc with V extension.

gcc

PR target/115840
* config/riscv/riscv.cc(riscv_preferred_else_value): Mark
tmp_var as NO_WARNING.

gcc/testsuite
* gcc.dg/vect/pr115840.c: New testcase.

(cherry picked from commit c6f38e5e6d900b8ed6a4f5c126d3197946cad4dd)

Diff:
---
 gcc/config/riscv/riscv.cc|  6 +-
 gcc/testsuite/gcc.dg/vect/pr115840.c | 11 +++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8a8826deac17..07539b62 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11432,7 +11432,11 @@ riscv_preferred_else_value (unsigned ifn, tree 
vectype, unsigned int nops,
tree *ops)
 {
   if (riscv_v_ext_mode_p (TYPE_MODE (vectype)))
-return get_or_create_ssa_default_def (cfun, create_tmp_var (vectype));
+{
+  tree tmp_var = create_tmp_var (vectype);
+  TREE_NO_WARNING (tmp_var) = 1;
+  return get_or_create_ssa_default_def (cfun, tmp_var);
+}
 
   return default_preferred_else_value (ifn, vectype, nops, ops);
 }
diff --git a/gcc/testsuite/gcc.dg/vect/pr115840.c 
b/gcc/testsuite/gcc.dg/vect/pr115840.c
new file mode 100644
index ..09dc9e4eb7c2
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr115840.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-Wall -Werror" } */
+
+double loads[16];
+
+void
+foo (double loadavg[], int count)
+{
+  for (int i = 0; i < count; i++)
+loadavg[i] = loads[i] / 1.5;
+}

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Avoid unnecessary sign extension after memcmp

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:67116d59607d1897629deb3b95f7ccb9d4d875cb

commit 67116d59607d1897629deb3b95f7ccb9d4d875cb
Author: Jeff Law 
Date:   Fri Jul 12 07:53:41 2024 -0600

[RISC-V] Avoid unnecessary sign extension after memcmp

Similar to the str[n]cmp work, this adjusts the block compare expansion to 
do
its work in X mode with an appropriate lowpart extraction of the results at 
the
end of the sequence.

This has gone through my tester on rv32 and rv64, but that's it. Waiting on
pre-commit testing before moving forward.

gcc/

* config/riscv/riscv-string.cc 
(emit_memcmp_scalar_load_and_compare):
Set RESULT directly rather than using a temporary.
(emit_memcmp_scalar_result_calculation): Similarly.
(riscv_expand_block_compare_scalar): Use CONST0_RTX rather than
generating new RTL.
* config/riscv/riscv.md (cmpmemsi): Pass an X mode temporary to the
expansion routines.  If necessary extract low part of the word to 
store
in final result location.

(cherry picked from commit ae829a27785307232e4db0df6a30ca275941b613)

Diff:
---
 gcc/config/riscv/riscv-string.cc | 15 ++-
 gcc/config/riscv/riscv.md| 14 --
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 4736228e6f14..80d22e87d571 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -663,9 +663,7 @@ emit_memcmp_scalar_load_and_compare (rtx result, rtx src1, 
rtx src2,
   /* Fast-path for a single byte.  */
   if (cmp_bytes == 1)
{
- rtx tmp = gen_reg_rtx (Xmode);
- do_sub3 (tmp, data1, data2);
- emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+ do_sub3 (result, data1, data2);
  emit_jump_insn (gen_jump (final_label));
  emit_barrier (); /* No fall-through.  */
  return;
@@ -702,12 +700,11 @@ emit_memcmp_scalar_result_calculation (rtx result, rtx 
data1, rtx data2)
   /* Get bytes in big-endian order and compare as words.  */
   do_bswap2 (data1, data1);
   do_bswap2 (data2, data2);
+
   /* Synthesize (data1 >= data2) ? 1 : -1 in a branchless sequence.  */
-  rtx tmp = gen_reg_rtx (Xmode);
-  emit_insn (gen_slt_3 (LTU, Xmode, Xmode, tmp, data1, data2));
-  do_neg2 (tmp, tmp);
-  do_ior3 (tmp, tmp, const1_rtx);
-  emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+  emit_insn (gen_slt_3 (LTU, Xmode, Xmode, result, data1, data2));
+  do_neg2 (result, result);
+  do_ior3 (result, result, const1_rtx);
 }
 
 /* Expand memcmp using scalar instructions (incl. Zbb).
@@ -773,7 +770,7 @@ riscv_expand_block_compare_scalar (rtx result, rtx src1, 
rtx src2, rtx nbytes)
   data1, data2,
   diff_label, final_label);
 
-  emit_insn (gen_rtx_SET (result, gen_rtx_CONST_INT (SImode, 0)));
+  emit_move_insn (result, CONST0_RTX (GET_MODE (result)));
   emit_jump_insn (gen_jump (final_label));
   emit_barrier (); /* No fall-through.  */
 
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2e2379dfca4f..5dee837a5878 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2675,9 +2675,19 @@
   operands[2], operands[3]))
 DONE;
 
-  if (riscv_expand_block_compare (operands[0], operands[1], operands[2],
+  rtx temp = gen_reg_rtx (word_mode);
+  if (riscv_expand_block_compare (temp, operands[1], operands[2],
   operands[3]))
-DONE;
+{
+  if (TARGET_64BIT)
+   {
+ temp = gen_lowpart (SImode, temp);
+ SUBREG_PROMOTED_VAR_P (temp) = 1;
+ SUBREG_PROMOTED_SET (temp, SRP_SIGNED);
+   }
+  emit_move_insn (operands[0], temp);
+  DONE;
+}
   else
 FAIL;
 })

[gcc r15-2007] modula2: bootstrap fix for string and vector headers.

[Gaius Mulley via Gcc-cvs]

https://gcc.gnu.org/g:f4047a8614d2215e0d6acf071c521ac08ab1bbb2

commit r15-2007-gf4047a8614d2215e0d6acf071c521ac08ab1bbb2
Author: FX Coudert 
Date:   Fri Jul 12 15:39:50 2024 +0100

modula2: bootstrap fix for string and vector headers.

This patch fixes the include of headers ( and ) which
are included after GCC's system.h has been included.  It defines
INCLUDE_STRING before including "system.h".  This allows gcc to
bootstrap with Apple clang 15.

gcc/m2/ChangeLog:

* gm2-gcc/m2linemap.cc (INCLUDE_STRING): Define before
include of gcc-consolidation.h.
* gm2spec.cc (INCLUDE_STRING): Define before include of
system.h.
(INCLUDE_VECTOR): Ditto.

Signed-off-by: Gaius Mulley 

Diff:
---
 gcc/m2/gm2-gcc/m2linemap.cc | 2 +-
 gcc/m2/gm2spec.cc   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/m2/gm2-gcc/m2linemap.cc b/gcc/m2/gm2-gcc/m2linemap.cc
index c916ba6155af..fcf589e840f8 100644
--- a/gcc/m2/gm2-gcc/m2linemap.cc
+++ b/gcc/m2/gm2-gcc/m2linemap.cc
@@ -19,6 +19,7 @@ You should have received a copy of the GNU General Public 
License
 along with GNU Modula-2; see the file COPYING3.  If not see
 .  */
 
+#define INCLUDE_STRING
 #include "gcc-consolidation.h"
 
 /* Utilize some of the C build routines */
@@ -36,7 +37,6 @@ along with GNU Modula-2; see the file COPYING3.  If not see
 #define m2linemap_c
 #include "m2linemap.h"
 #include "m2color.h"
-#include 
 
 static int inFile = FALSE;
 
diff --git a/gcc/m2/gm2spec.cc b/gcc/m2/gm2spec.cc
index a4faf88027a2..2a4dccf8b93c 100644
--- a/gcc/m2/gm2spec.cc
+++ b/gcc/m2/gm2spec.cc
@@ -20,6 +20,8 @@ along with GNU Modula-2; see the file COPYING3.  If not see
 .  */
 
 #include "config.h"
+#define INCLUDE_STRING
+#define INCLUDE_VECTOR
 #include "system.h"
 #include "coretypes.h"
 #include "tm.h"
@@ -31,8 +33,6 @@ along with GNU Modula-2; see the file COPYING3.  If not see
 #include "gcc.h"
 #include "opts.h"
 #include "vec.h"
-#include 
-#include 
 
 #include "m2/gm2config.h"

[gcc r15-2008] rtl-ssa: Fix prev_any_insn [PR115785]

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:6e7053a641393211f52c176e540c8922288ab8db

commit r15-2008-g6e7053a641393211f52c176e540c8922288ab8db
Author: Richard Sandiford 
Date:   Fri Jul 12 15:50:36 2024 +0100

rtl-ssa: Fix prev_any_insn [PR115785]

Bit of a brown paper bag issue, but: due to the representation
of the insn chain, insn_info::prev_any_insn would sometimes skip
over instructions.  This led to an invalid update in the PR when
adding and removing instructions.

I think one of the reasons I failed to spot this when checking
the code is that m_prev_insn_or_last_debug_insn is misnamed:
it's the previous instruction *of the same type* or the last
debug instruction in a group.  The patch therefore renames it to
m_prev_sametype_or_last_debug_insn (with the term prev_sametype
already being used in some accessors).

The reason this didn't show up earlier is that (a) prev_any_insn
is rarely used directly, (b) no instructions were lost from the
def-use chains, and (c) only consecutive debug instructions were
skipped when walking the insn chain.

The chaining scheme makes prev_any_insn more complicated than
next_any_insn, prev_nondebug_insn and next_nondebug_insn, but the
object code produced is still relatively simple.

gcc/
PR rtl-optimization/115785
* rtl-ssa/insns.h (insn_info::prev_insn_or_last_debug_insn)
(insn_info::next_nondebug_or_debug_insn): Remove typedefs.
(insn_info::m_prev_insn_or_last_debug_insn): Rename to...
(insn_info::m_prev_sametype_or_last_debug_insn): ...this.
* rtl-ssa/internals.inl (insn_info::insn_info): Update after
above renaming.
(insn_info::copy_prev_from): Likewise.
(insn_info::set_prev_sametype_insn): Likewise.
(insn_info::set_last_debug_insn): Likewise.
(insn_info::clear_insn_links): Likewise.
(insn_info::has_insn_links): Likewise.
* rtl-ssa/member-fns.inl (insn_info::prev_nondebug_insn): Likewise.
(insn_info::prev_any_insn): Fix moves from non-debug to debug insns.

gcc/testsuite/
PR rtl-optimization/115785
* g++.dg/torture/pr115785.C: New test.

Diff:
---
 gcc/rtl-ssa/insns.h |  54 ++-
 gcc/rtl-ssa/internals.inl   |  13 +-
 gcc/rtl-ssa/member-fns.inl  |  25 +-
 gcc/testsuite/g++.dg/torture/pr115785.C | 696 
 4 files changed, 747 insertions(+), 41 deletions(-)

diff --git a/gcc/rtl-ssa/insns.h b/gcc/rtl-ssa/insns.h
index 80eae5eaa1ec..1304b18e085c 100644
--- a/gcc/rtl-ssa/insns.h
+++ b/gcc/rtl-ssa/insns.h
@@ -339,32 +339,6 @@ private:
   };
   using order_splay_tree = default_rootless_splay_tree;
 
-  // prev_insn_or_last_debug_insn represents a choice between two things:
-  //
-  // (1) A pointer to the previous instruction in the list that has the
-  // same is_debug_insn () value, or null if no such instruction exists.
-  //
-  // (2) A pointer to the end of a sublist of debug instructions.
-  //
-  // (2) is used if this instruction is a debug instruction and the
-  // previous instruction is not.  (1) is used otherwise.
-  //
-  // next_nondebug_or_debug_insn points to the next instruction but also
-  // records whether that next instruction is a debug instruction or a
-  // nondebug instruction.
-  //
-  // Thus the list is chained as follows:
-  //
-  // >> > > >
-  // NONDEBUG NONDEBUG DEBUG DEBUG DEBUG NONDEBUG ...
-  // <^ +-- < <  ^+--
-  //  | |||
-  //  | ++|
-  //  |   |
-  //  +---+
-  using prev_insn_or_last_debug_insn = pointer_mux;
-  using next_nondebug_or_debug_insn = pointer_mux;
-
   insn_info (bb_info *bb, rtx_insn *rtl, int cost_or_uid);
 
   static void print_uid (pretty_printer *, int);
@@ -395,9 +369,33 @@ private:
   void clear_insn_links ();
   bool has_insn_links ();
 
+  // m_prev_sametye_or_last_debug_insn represents a choice between two things:
+  //
+  // (1) A pointer to the previous instruction in the list that has the
+  // same is_debug_insn () value, or null if no such instruction exists.
+  //
+  // (2) A pointer to the end of a sublist of debug instructions.
+  //
+  // (2) is used if this instruction is a debug instruction and the
+  // previous instruction is not.  (1) is used otherwise.
+  //
+  // m_next_nondebug_or_debug_insn points to the next instruction but also
+  // records whether that next instruction is a debug instruction or a
+  // nondebug instruction.
+  //
+  // Thus the list is chained as follows:
+  //
+  // >> > > >
+ 

[gcc r15-2009] Fix Xcode 16 build break with NULL != nullptr

[Iain D Sandoe via Gcc-cvs]

https://gcc.gnu.org/g:08776bef53835ff6318ecfeade8f6c6896ffd81f

commit r15-2009-g08776bef53835ff6318ecfeade8f6c6896ffd81f
Author: Daniel Bertalan 
Date:   Tue Jul 9 23:34:46 2024 +0200

Fix Xcode 16 build break with NULL != nullptr

As of Xcode 16 beta 2 with the macOS 15 SDK, each re-inclusion of the
stddef.h header causes the NULL macro in C++ to be re-defined to an
integral constant (__null). This makes the workaround in d59a576b8
("Redefine NULL to nullptr") ineffective, as other headers that are
typically included after system.h (such as obstack.h) do include
stddef.h too.

This can be seen by running the sample below through `clang++ -E`

#include 
#define NULL nullptr
#include 
NULL

The relevant libc++ change is here:

https://github.com/llvm/llvm-project/commit/2950283dddab03c183c1be2d7de9d4999cc86131

Filed as FB14261859 to Apple and added a comment about it on LLVM PR
86843.

This fixes the cases in --enable-languages=c,c++,objc,obj-c++,rust build
where NULL being an integral constant instead of a null pointer literal
(therefore no longer implicitly converting to a pointer when used as a
template function's argument) caused issues.

gcc/value-pointer-equiv.cc:65:43: error: no viable conversion from 
`pair::type, typename 
__unwrap_ref_decay::type>' to 'const pair'

65 |   const std::pair  m_marker = std::make_pair (NULL, 
NULL);
   |   
^~~

As noted in the previous commit though, the proper solution would be to
phase out the usages of NULL in GCC's C++ source code.

gcc/analyzer/ChangeLog:

* diagnostic-manager.cc (saved_diagnostic::saved_diagnostic):
Change NULL to nullptr.
(struct null_assignment_sm_context): Likewise.
* infinite-loop.cc: Likewise.
* infinite-recursion.cc: Likewise.
* varargs.cc (va_list_state_machine::on_leak): Likewise.

gcc/rust/ChangeLog:

* metadata/rust-imports.cc (Import::try_package_in_directory):
Change NULL to nullptr.

gcc/ChangeLog:

* value-pointer-equiv.cc: Change NULL to nullptr.

Signed-off-by: Daniel Bertalan 

Diff:
---
 gcc/analyzer/diagnostic-manager.cc | 18 +-
 gcc/analyzer/infinite-loop.cc  |  2 +-
 gcc/analyzer/infinite-recursion.cc |  2 +-
 gcc/analyzer/varargs.cc|  2 +-
 gcc/rust/metadata/rust-imports.cc  |  2 +-
 gcc/value-pointer-equiv.cc |  2 +-
 6 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/gcc/analyzer/diagnostic-manager.cc 
b/gcc/analyzer/diagnostic-manager.cc
index fe943ac61c9e..51304b0795b6 100644
--- a/gcc/analyzer/diagnostic-manager.cc
+++ b/gcc/analyzer/diagnostic-manager.cc
@@ -679,12 +679,12 @@ saved_diagnostic::saved_diagnostic (const state_machine 
*sm,
   m_stmt (ploc.m_stmt),
   /* stmt_finder could be on-stack; we want our own copy that can
  outlive that.  */
-  m_stmt_finder (ploc.m_finder ? ploc.m_finder->clone () : NULL),
+  m_stmt_finder (ploc.m_finder ? ploc.m_finder->clone () : nullptr),
   m_loc (ploc.m_loc),
   m_var (var), m_sval (sval), m_state (state),
-  m_d (std::move (d)), m_trailing_eedge (NULL),
+  m_d (std::move (d)), m_trailing_eedge (nullptr),
   m_idx (idx),
-  m_best_epath (NULL), m_problem (NULL),
+  m_best_epath (nullptr), m_problem (nullptr),
   m_notes ()
 {
   /* We must have an enode in order to be able to look for paths
@@ -1800,10 +1800,10 @@ public:
stmt,
stack_depth,
sm,
-   NULL,
+   nullptr,
src_sm_val,
dst_sm_val,
-   NULL,
+   nullptr,
dst_state,
src_node));
 return false;
@@ -1993,9 +1993,9 @@ struct null_assignment_sm_context : public sm_context
m_sm,
var_new_sval,
from, to,
-   NULL,
+   nullptr,
*m_new_state,
-   NULL));
+   nullptr));
   }
 
   void set_next_state (const gimple *stmt,
@@ -2019,9 +2019,9 @@ struct null_assignment_sm_context : public sm_context
m_sm,
sval,
from, to,
-   NUL

[gcc(refs/users/meissner/heads/work171-bugs)] Disable adding -mvsx when checking for float128 support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0a9e57995990885028fc6af8a53513794890

commit 0a9e57995990885028fc6af8a53513794890
Author: Michael Meissner 
Date:   Fri Jul 12 12:00:20 2024 -0400

Disable adding -mvsx when checking for float128 support.

2024-07-12  Michael Meissner  

gcc/testsuite/

PR target/115800
PR target/113652
* lib/target-supports.exp (check_ppc_float128_sw_available): Do not 
add
-mvsx when checking for float128 support.
(check_ppc_float128_hw_available): Likewise.
(check_effective_target___float128): Likewise.

Diff:
---
 gcc/testsuite/lib/target-supports.exp | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index b7df6150bcbd..86c0913378ed 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2979,7 +2979,7 @@ proc check_ppc_float128_sw_available { } {
 || [istarget *-*-darwin*]} {
expr 0
} else {
-   set options "-mfloat128 -mvsx"
+   set options "-mfloat128"
check_runtime_nocache ppc_float128_sw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3005,7 +3005,7 @@ proc check_ppc_float128_hw_available { } {
 || [istarget *-*-darwin*]} {
expr 0
} else {
-   set options "-mfloat128 -mvsx -mfloat128-hardware -mcpu=power9"
+   set options "-mfloat128 -mcpu=power9"
check_runtime_nocache ppc_float128_hw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3947,7 +3947,7 @@ proc check_effective_target___float128 { } {
 
 proc add_options_for___float128 { flags } {
 if { [istarget powerpc*-*-linux*] } {
-   return "$flags -mfloat128 -mvsx"
+   return "$flags -mfloat128"
 }
 return "$flags"
 }
@@ -7234,7 +7234,7 @@ proc check_effective_target_powerpc_float128_sw_ok { } {
__float128 z = x + y;
return (z == 3.0q);
}
-   } "-mfloat128 -mvsx"]
+   } "-mfloat128"]
 } else {
return 0
 }

[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a2af9e19c83edeca6fa8a6502fea697715678e95

commit a2af9e19c83edeca6fa8a6502fea697715678e95
Author: Michael Meissner 
Date:   Fri Jul 12 12:01:12 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index a4a6b8aa0f70..7ae08f41109b 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,4 +1,19 @@
- Branch work171-bugs, patch #301 
+ Branch work171-bugs, patch #303 
+
+Disable adding -mvsx when checking for float128 support.
+
+2024-07-12  Michael Meissner  
+
+gcc/testsuite/
+
+   PR target/115800
+   PR target/113652
+   * lib/target-supports.exp (check_ppc_float128_sw_available): Do not add
+   -mvsx when checking for float128 support.
+   (check_ppc_float128_hw_available): Likewise.
+   (check_effective_target___float128): Likewise.
+
+ Branch work171-bugs, patch #302 
 
 Do not build IEEE 128-bit libgcc support if VSX is not available.

[gcc(refs/users/meissner/heads/work171-bugs)] Use -mcpu=native instead of -mcpu=power9 when checking for float128 hardware support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:89c9983b9157b8eb443a16561ad9a55d2cb10c66

commit 89c9983b9157b8eb443a16561ad9a55d2cb10c66
Author: Michael Meissner 
Date:   Fri Jul 12 14:12:28 2024 -0400

Use -mcpu=native instead of -mcpu=power9 when checking for float128 
hardware support.

2024-07-12  Michael Meissner  

gcc/testsuite/

PR target/115800
PR target/113652
* lib/target-supports.exp (check_ppc_float128_hw_available): Use
-mcpu=native rather than -mcpu=power9 to check if the machine has
float128 hardware support.

Diff:
---
 gcc/testsuite/lib/target-supports.exp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 86c0913378ed..ba64a1dbae87 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3005,7 +3005,7 @@ proc check_ppc_float128_hw_available { } {
 || [istarget *-*-darwin*]} {
expr 0
} else {
-   set options "-mfloat128 -mcpu=power9"
+   set options "-mfloat128 -mcpu=native"
check_runtime_nocache ppc_float128_hw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;

[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5414c9a058837198fa9da1da672e28dd84da1f1d

commit 5414c9a058837198fa9da1da672e28dd84da1f1d
Author: Michael Meissner 
Date:   Fri Jul 12 14:13:30 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 7ae08f41109b..61066c019ccd 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,17 @@
+ Branch work171-bugs, patch #304 
+
+Use -mcpu=native instead of -mcpu=power9 when checking for float128 hardware 
support.
+
+2024-07-12  Michael Meissner  
+
+gcc/testsuite/
+
+   PR target/115800
+   PR target/113652
+   * lib/target-supports.exp (check_ppc_float128_hw_available): Use
+   -mcpu=native rather than -mcpu=power9 to check if the machine has
+   float128 hardware support.
+
  Branch work171-bugs, patch #303 
 
 Disable adding -mvsx when checking for float128 support.

[gcc r15-2010] doc: remove @opindex for fconcepts-ts

[Marek Polacek via Gcc-cvs]

https://gcc.gnu.org/g:b3d4a021eff6353a099f800857d3080a7cd27003

commit r15-2010-gb3d4a021eff6353a099f800857d3080a7cd27003
Author: Marek Polacek 
Date:   Fri Jul 12 14:40:59 2024 -0400

doc: remove @opindex for fconcepts-ts

We're getting complaints from the CI system about this removed option.
I suspect I should have removed the @opindex and @itemx for it.  This
patch does that.

gcc/ChangeLog:

* doc/invoke.texi: Remove @opindex and @itemx for -fconcepts-ts.

Diff:
---
 gcc/doc/invoke.texi | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4850c7379bfa..d10796cabd69 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -3217,16 +3217,14 @@ exhaustion is signalled by throwing 
@code{std::bad_alloc}.  See also
 @samp{new (nothrow)}.
 
 @opindex fconcepts
-@opindex fconcepts-ts
 @item -fconcepts
-@itemx -fconcepts-ts
 Enable support for the C++ Concepts feature for constraining template
 arguments.  With @option{-std=c++20} and above, Concepts are part of
 the language standard, so @option{-fconcepts} defaults to on.
 
 Some constructs that were allowed by the earlier C++ Extensions for
 Concepts Technical Specification, ISO 19217 (2015), but didn't make it
-into the standard, can additionally be enabled by
+into the standard, could additionally be enabled by
 @option{-fconcepts-ts}.  The option @option{-fconcepts-ts} was deprecated
 in GCC 14 and removed in GCC 15; users are expected to convert their code
 to C++20 concepts.

[gcc r15-2011] [PR rtl-optimization/115876] Fix one of two ubsan reported issues in new ext-dce.cc code

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:a6f551d079de1d151b272bcdd3d42316857c9d4e

commit r15-2011-ga6f551d079de1d151b272bcdd3d42316857c9d4e
Author: Jeff Law 
Date:   Fri Jul 12 13:11:33 2024 -0600

[PR rtl-optimization/115876] Fix one of two ubsan reported issues in new 
ext-dce.cc code

David Binderman did a bootstrap build with ubsan enabled which triggered a 
few
errors in the new ext-dce.cc code.  This fixes the trivial case of shifting
negative values.

Bootstrapped and regression tested on x86.

Pushing to the trunk.

gcc/
PR rtl-optimization/115876
* ext-dce.cc (carry_backpropagate): Make mask and mmask unsigned.

Diff:
---
 gcc/ext-dce.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index adc9084df57d..91789d283fcd 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -374,13 +374,13 @@ binop_implies_op2_fully_live (rtx_code code)
exclusively pertain to the first operand.  */
 
 HOST_WIDE_INT
-carry_backpropagate (HOST_WIDE_INT mask, enum rtx_code code, rtx x)
+carry_backpropagate (unsigned HOST_WIDE_INT mask, enum rtx_code code, rtx x)
 {
   if (mask == 0)
 return 0;
 
   enum machine_mode mode = GET_MODE_INNER (GET_MODE (x));
-  HOST_WIDE_INT mmask = GET_MODE_MASK (mode);
+  unsigned HOST_WIDE_INT mmask = GET_MODE_MASK (mode);
   switch (code)
 {
 case PLUS:

[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:79427fed78d2531db6adc592f63d47ceaf0d5b49

commit 79427fed78d2531db6adc592f63d47ceaf0d5b49
Author: Michael Meissner 
Date:   Fri Jul 12 19:27:38 2024 -0400

Revert changes

Diff:
---
 gcc/testsuite/lib/target-supports.exp |  8 
 libgcc/config.host| 12 ++--
 libgcc/config/rs6000/t-float128   |  2 +-
 libgcc/configure  | 17 ++---
 libgcc/configure.ac   | 17 ++---
 5 files changed, 23 insertions(+), 33 deletions(-)

diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index ba64a1dbae87..b7df6150bcbd 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2979,7 +2979,7 @@ proc check_ppc_float128_sw_available { } {
 || [istarget *-*-darwin*]} {
expr 0
} else {
-   set options "-mfloat128"
+   set options "-mfloat128 -mvsx"
check_runtime_nocache ppc_float128_sw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3005,7 +3005,7 @@ proc check_ppc_float128_hw_available { } {
 || [istarget *-*-darwin*]} {
expr 0
} else {
-   set options "-mfloat128 -mcpu=native"
+   set options "-mfloat128 -mvsx -mfloat128-hardware -mcpu=power9"
check_runtime_nocache ppc_float128_hw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3947,7 +3947,7 @@ proc check_effective_target___float128 { } {
 
 proc add_options_for___float128 { flags } {
 if { [istarget powerpc*-*-linux*] } {
-   return "$flags -mfloat128"
+   return "$flags -mfloat128 -mvsx"
 }
 return "$flags"
 }
@@ -7234,7 +7234,7 @@ proc check_effective_target_powerpc_float128_sw_ok { } {
__float128 z = x + y;
return (z == 3.0q);
}
-   } "-mfloat128"]
+   } "-mfloat128 -mvsx"]
 } else {
return 0
 }
diff --git a/libgcc/config.host b/libgcc/config.host
index 261b08859a4d..9fae51d4ce7d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
 
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
+   fi
 
-   if test $libgcc_cv_powerpc_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-hw"
+   if test $libgcc_cv_powerpc_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-hw"
+   fi
 
-   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
-   tmake_file="${tmake_file} 
rs6000/t-float128-p10-hw"
-   fi
-   fi
+   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
fi
 
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index 2d93080f1174..b09b5664af0e 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,7 @@ fp128_includes= $(srcdir)/soft-fp/double.h \
  $(srcdir)/soft-fp/soft-fp.h
 
 # Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits -mfloat128 \
+FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
   -mno-float128-hardware -mno-gnu-attribute \
   -I$(srcdir)/soft-fp \
   -I$(srcdir)/config/rs6000 \
diff --git a/libgcc/configure b/libgcc/configure
index 39193456929a..a69d314374a3 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,18 +5180,13 @@ esac
 esac
 
 case ${host} in
-# Check if we can enable float128 support.  Some systems (big endian) do not
-# enable float128 by default, but they can enable it if -mfloat128 is used.
-# However, the compiler must be compiled using at least --with-cpu=power7 to
-# enable VSX support.  If we build a default big endian system without using
-# --with-cpu=power7, do not build the float128 libraries.  VSX support is
-# needed because float128 values are passed in VSX registers.
-#
-# Also check if a new glibc is being used so that __builtin_cpu_supports can be
-# used.
+# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
+# check if we have VSX (ISA 2.06) support to build the software libraries, and
+# whether the assembler can handle xsaddqp for hardware support.  Also check if
+# a new glibc is being used so that __builtin_cpu_supports can be used.
 powerpc*-*-linux*)
   saved_CFLAGS="$CFLAGS"
-  CFLAGS="$CFLAGS -mfloat128"
+  CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
   { $as_echo 

[gcc r15-2012] doc: Update GNU Modula 2 mailing list links

[Gerald Pfeifer via Gcc-cvs]

https://gcc.gnu.org/g:dd2840a45e94946cc4a831cf9a08c708f8a9e1ae

commit r15-2012-gdd2840a45e94946cc4a831cf9a08c708f8a9e1ae
Author: Gerald Pfeifer 
Date:   Sat Jul 13 01:40:15 2024 +0200

doc: Update GNU Modula 2 mailing list links

gcc:
* doc/gm2.texi (Community): Update lists.nongnu.org and
lists.gnu.org links.

Diff:
---
 gcc/doc/gm2.texi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi
index c532339fbb84..5bff9eb3829d 100644
--- a/gcc/doc/gm2.texi
+++ b/gcc/doc/gm2.texi
@@ -3014,9 +3014,9 @@ You can subscribe to the GNU Modula-2 mailing by sending 
an
 email to:
 @email{gm2-subscribe@@nongnu.org}
 or by
-@url{http://lists.nongnu.org/mailman/listinfo/gm2}.
+@url{https://lists.nongnu.org/mailman/listinfo/gm2}.
 The mailing list contents can be viewed
-@url{http://lists.gnu.org/archive/html/gm2}.
+@url{https://lists.gnu.org/archive/html/gm2}.
 
 @node Other languages, , Community, Using
 @section Other languages for GCC

[gcc(refs/users/meissner/heads/work171-bugs)] Add checks for building the IEEE 128-bit libgcc support if VSX is not available.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:097f2463d8c78602186feb731fd8732dce9f3e7c

commit 097f2463d8c78602186feb731fd8732dce9f3e7c
Author: Michael Meissner 
Date:   Fri Jul 12 20:04:37 2024 -0400

Add checks for building the IEEE 128-bit libgcc support if VSX is not 
available.

In the past, we would build libgcc and eable the float128 libraries by 
adding
-mvsx -mabi=altivec to build the support libraries.  However, this causes
problems if the default cpu is a 7450.  This patch checks to see if can 
link a
program using the options, and if we can't link the program, do not build 
the
float128 libraries.

2024-07-12  Michael Meissner  

libgcc/

PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not enable the float128 
hardware
and float128 power10 hardware support unless the basic float128 
support
is added.
* configure.ac (powerpc*-*-linux*): Check whether the linker and
assembler will be able to build the float128 libraries.
* configure: Regenerate.

Diff:
---
 libgcc/config.host  | 12 -
 libgcc/configure| 71 ++---
 libgcc/configure.ac | 17 +++--
 3 files changed, 88 insertions(+), 12 deletions(-)

diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..261b08859a4d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
 
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
-   fi
 
-   if test $libgcc_cv_powerpc_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-hw"
-   fi
+   if test $libgcc_cv_powerpc_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-hw"
 
-   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+   tmake_file="${tmake_file} 
rs6000/t-float128-p10-hw"
+   fi
+   fi
fi
 
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..bb196c8e7b84 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -1802,6 +1802,52 @@ $as_echo "$ac_res" >&6; }
   eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
 
 } # ac_fn_c_check_header_preproc
+
+# ac_fn_c_try_link LINENO
+# ---
+# Try to link conftest.$ac_ext, and return whether this succeeded.
+ac_fn_c_try_link ()
+{
+  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+  rm -f conftest.$ac_objext conftest$ac_exeext
+  if { { ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link") 2>conftest.err
+  ac_status=$?
+  if test -s conftest.err; then
+grep -v '^ *+' conftest.err >conftest.er1
+cat conftest.er1 >&5
+mv -f conftest.er1 conftest.err
+  fi
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; } && {
+test -z "$ac_c_werror_flag" ||
+test ! -s conftest.err
+   } && test -s conftest$ac_exeext && {
+test "$cross_compiling" = yes ||
+test -x conftest$ac_exeext
+   }; then :
+  ac_retval=0
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+   ac_retval=1
+fi
+  # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information
+  # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would
+  # interfere with the next link command; also delete a directory that is
+  # left behind by Apple's compiler.  We do this before executing the actions.
+  rm -rf conftest.dSYM conftest_ipa8_conftest.oo
+  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
+  as_fn_set_status $ac_retval
+
+} # ac_fn_c_try_link
 cat >config.log <<_ACEOF
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
@@ -5184,6 +5230,12 @@ case ${host} in
 # check if we have VSX (ISA 2.06) support to build the software libraries, and
 # whether the assembler can handle xsaddqp for hardware support.  Also check if
 # a new glibc is being used so that __builtin_cpu_supports can be used.
+#
+# We use AC_LINK_IFELSE to verify that the assembler will not abort if given
+# the -mvsx -mabi=altivec options to compile the float128 support with VSX.
+# Otherwise if the default CPU is something like the 7450, the assembler will
+# complain when we build the float128 support.
+
 powerpc*-*-linux*)
   saved_CFLAGS=

[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d317a05ebc91cb1da2a89d9ea9fe5f7dc0747b8a

commit d317a05ebc91cb1da2a89d9ea9fe5f7dc0747b8a
Author: Michael Meissner 
Date:   Fri Jul 12 20:06:45 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.bugs | 56 --
 1 file changed, 12 insertions(+), 44 deletions(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 61066c019ccd..f2f6f7986da8 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,49 +1,14 @@
- Branch work171-bugs, patch #304 
+ Branch work171-bugs, patch #310 
 
-Use -mcpu=native instead of -mcpu=power9 when checking for float128 hardware 
support.
-
-2024-07-12  Michael Meissner  
-
-gcc/testsuite/
-
-   PR target/115800
-   PR target/113652
-   * lib/target-supports.exp (check_ppc_float128_hw_available): Use
-   -mcpu=native rather than -mcpu=power9 to check if the machine has
-   float128 hardware support.
-
- Branch work171-bugs, patch #303 
-
-Disable adding -mvsx when checking for float128 support.
-
-2024-07-12  Michael Meissner  
-
-gcc/testsuite/
-
-   PR target/115800
-   PR target/113652
-   * lib/target-supports.exp (check_ppc_float128_sw_available): Do not add
-   -mvsx when checking for float128 support.
-   (check_ppc_float128_hw_available): Likewise.
-   (check_effective_target___float128): Likewise.
-
- Branch work171-bugs, patch #302 
-
-Do not build IEEE 128-bit libgcc support if VSX is not available.
+Add checks for building the IEEE 128-bit libgcc support if VSX is not 
available.
 
 In the past, we would build libgcc and eable the float128 libraries by adding
 -mvsx -mabi=altivec to build the support libraries.  However, this causes
-problems if the default cpu is a 7450.
-
-With this fix, in order to build the float128 support, the compiler must be
-configured to default to at least power7 to enable using the VSX register set,
-which is required for passing float128 values.
-
-If somebody wanted to enable float128 on big endian systems, they would need to
-use a compiler that defaults to at least power7.
+problems if the default cpu is a 7450.  This patch checks to see if can link a
+program using the options, and if we can't link the program, do not build the
+float128 libraries.
 
-
-2024-07-11  Michael Meissner  
+2024-07-12  Michael Meissner  
 
 libgcc/
 
@@ -52,11 +17,14 @@ libgcc/
* config.host (powerpc*-*-linux*): Do not enable the float128 hardware
and float128 power10 hardware support unless the basic float128 support
is added.
-   * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx.
-   * configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC
-   systems without VSX.
+   * configure.ac (powerpc*-*-linux*): Check whether the linker and
+   assembler will be able to build the float128 libraries.
* configure: Regenerate.
 
+ Branch work171-bugs, patch #304 was reverted 

+ Branch work171-bugs, patch #303 was reverted 

+ Branch work171-bugs, patch #302 was reverted 

+
  Branch work171-bugs, patch #301 
 
 Do not build IEEE 128-bit libstdc++ support if VSX is not available.

[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:78633b506f6673f1b3bfcd39df55933ae4f1d4eb

commit 78633b506f6673f1b3bfcd39df55933ae4f1d4eb
Author: Michael Meissner 
Date:   Fri Jul 12 20:27:11 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.bugs  | 24 +-
 libgcc/config.host  | 12 -
 libgcc/configure| 71 +++--
 libgcc/configure.ac | 17 ++---
 4 files changed, 13 insertions(+), 111 deletions(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index f2f6f7986da8..dd7b7846d905 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,26 +1,4 @@
- Branch work171-bugs, patch #310 
-
-Add checks for building the IEEE 128-bit libgcc support if VSX is not 
available.
-
-In the past, we would build libgcc and eable the float128 libraries by adding
--mvsx -mabi=altivec to build the support libraries.  However, this causes
-problems if the default cpu is a 7450.  This patch checks to see if can link a
-program using the options, and if we can't link the program, do not build the
-float128 libraries.
-
-2024-07-12  Michael Meissner  
-
-libgcc/
-
-   PR target/115800
-   PR target/113652
-   * config.host (powerpc*-*-linux*): Do not enable the float128 hardware
-   and float128 power10 hardware support unless the basic float128 support
-   is added.
-   * configure.ac (powerpc*-*-linux*): Check whether the linker and
-   assembler will be able to build the float128 libraries.
-   * configure: Regenerate.
-
+ Branch work171-bugs, patch #310 was reverted 

  Branch work171-bugs, patch #304 was reverted 

  Branch work171-bugs, patch #303 was reverted 

  Branch work171-bugs, patch #302 was reverted 

diff --git a/libgcc/config.host b/libgcc/config.host
index 261b08859a4d..9fae51d4ce7d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
 
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
+   fi
 
-   if test $libgcc_cv_powerpc_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-hw"
+   if test $libgcc_cv_powerpc_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-hw"
+   fi
 
-   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
-   tmake_file="${tmake_file} 
rs6000/t-float128-p10-hw"
-   fi
-   fi
+   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
fi
 
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index bb196c8e7b84..a69d314374a3 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -1802,52 +1802,6 @@ $as_echo "$ac_res" >&6; }
   eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
 
 } # ac_fn_c_check_header_preproc
-
-# ac_fn_c_try_link LINENO
-# ---
-# Try to link conftest.$ac_ext, and return whether this succeeded.
-ac_fn_c_try_link ()
-{
-  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
-  rm -f conftest.$ac_objext conftest$ac_exeext
-  if { { ac_try="$ac_link"
-case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
-$as_echo "$ac_try_echo"; } >&5
-  (eval "$ac_link") 2>conftest.err
-  ac_status=$?
-  if test -s conftest.err; then
-grep -v '^ *+' conftest.err >conftest.er1
-cat conftest.er1 >&5
-mv -f conftest.er1 conftest.err
-  fi
-  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-  test $ac_status = 0; } && {
-test -z "$ac_c_werror_flag" ||
-test ! -s conftest.err
-   } && test -s conftest$ac_exeext && {
-test "$cross_compiling" = yes ||
-test -x conftest$ac_exeext
-   }; then :
-  ac_retval=0
-else
-  $as_echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-   ac_retval=1
-fi
-  # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information
-  # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would
-  # interfere with the next link command; also delete a directory that is
-  # left behind by Apple's compiler.  We do this before executing the actions.
-  rm -rf conftest.dSYM conftest_ipa8_conftest.oo
-  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
-  as_fn_set_status $ac_retval
-
-} # ac_fn_c_try_link
 cat >config.log <<_ACEOF
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
@@ -5230,

[gcc(refs/users/meissner/heads/work171-bugs)] Use -mcpu=power7 if needed and not -mvsx to build float128 support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a92ecfb87c48c9a4c7a7e12d5ec1491198ea0e18

commit a92ecfb87c48c9a4c7a7e12d5ec1491198ea0e18
Author: Michael Meissner 
Date:   Fri Jul 12 20:58:20 2024 -0400

Use -mcpu=power7 if needed and not -mvsx to build float128 support.

2024-07-12  Michael Meissner  

libgcc/

PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not enable the float128 
hardware
and float128 power10 hardware support unless the basic float128 
support
is added. Add support for building the float128 support when the 
default
compiler does not enable VSX.
* config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not use -mvsx, 
instead
use FP128_CFLAGS_VSX to optionally add -mcpu=power7.
* config/rs6000/t-float128-vsx: New file.
* configure.ac (powerpc*-*-linux*): Determine if the default 
powerpc cpu
includes VSX support.
* configure: Regenerate.

Diff:
---
 libgcc/config.host  | 16 ++--
 libgcc/config/rs6000/t-float128 |  2 +-
 libgcc/config/rs6000/t-float128-vsx |  3 +++
 libgcc/configure| 29 -
 libgcc/configure.ac | 17 -
 5 files changed, 50 insertions(+), 17 deletions(-)

diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..804d12e8fd6a 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1291,15 +1291,19 @@ powerpc*-*-linux*)
esac
 
if test $libgcc_cv_powerpc_float128 = yes; then
+   if test $libgcc_cv_powerpc_vsx = no; then
+   tmake_file="${tmake_file} rs6000/t-float128-vsx"
+   fi
+
tmake_file="${tmake_file} rs6000/t-float128"
-   fi
 
-   if test $libgcc_cv_powerpc_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-hw"
-   fi
+   if test $libgcc_cv_powerpc_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-hw"
 
-   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+   tmake_file="${tmake_file} 
rs6000/t-float128-p10-hw"
+   fi
+   fi
fi
 
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index b09b5664af0e..8037a6290a82 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,7 @@ fp128_includes= $(srcdir)/soft-fp/double.h \
  $(srcdir)/soft-fp/soft-fp.h
 
 # Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
+FP128_CFLAGS_SW = -Wno-type-limits $(FLOAT128_CFLAGS_VSX) 
-mfloat128 \
   -mno-float128-hardware -mno-gnu-attribute \
   -I$(srcdir)/soft-fp \
   -I$(srcdir)/config/rs6000 \
diff --git a/libgcc/config/rs6000/t-float128-vsx 
b/libgcc/config/rs6000/t-float128-vsx
new file mode 100644
index ..c691546242d9
--- /dev/null
+++ b/libgcc/config/rs6000/t-float128-vsx
@@ -0,0 +1,3 @@
+# Add -mcpu=power7 option if the default compiler does not support VSX
+
+FLOAT128_CFLAGS_VSX= -mabi=altivec -mcpu=power7
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..ad12baf965f4 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,13 +5180,32 @@ esac
 esac
 
 case ${host} in
-# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
-# check if we have VSX (ISA 2.06) support to build the software libraries, and
-# whether the assembler can handle xsaddqp for hardware support.  Also check if
-# a new glibc is being used so that __builtin_cpu_supports can be used.
+# Test if the default compiler enables VSX.  If it does not, we need to build
+# the float128 bit support using -mcpu=power7 to enable the VSX instruction 
set.
+#
+# Also check if a new glibc is being used so that __builtin_cpu_supports can be
+# used.
 powerpc*-*-linux*)
   saved_CFLAGS="$CFLAGS"
-  CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if VSX is enabled by 
default" >&5
+$as_echo_n "checking if VSX is enabled by default... " >&6; }
+if ${libgcc_cv_powerpc_vsx+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+vector double dadd (vector double a, vector double b) { return a + b; }
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  libgcc_cv_powerpc_vsx=yes
+else
+  libgcc_cv_powerpc_vsx=no
+fi
+rm -f core conftest.err conftest.$ac_ob

[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:de57e5fc86709f9e18d9d56b599d3d13104f94be

commit de57e5fc86709f9e18d9d56b599d3d13104f94be
Author: Michael Meissner 
Date:   Fri Jul 12 20:59:30 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 21 +
 1 file changed, 21 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index dd7b7846d905..f75ce1a0c83a 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,24 @@
+ Branch work171-bugs, patch #311 
+
+Use -mcpu=power7 if needed and not -mvsx to build float128 support.
+
+2024-07-12  Michael Meissner  
+
+libgcc/
+
+   PR target/115800
+   PR target/113652
+   * config.host (powerpc*-*-linux*): Do not enable the float128 hardware
+   and float128 power10 hardware support unless the basic float128 support
+   is added. Add support for building the float128 support when the default
+   compiler does not enable VSX.
+   * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not use -mvsx, instead
+   use FP128_CFLAGS_VSX to optionally add -mcpu=power7.
+   * config/rs6000/t-float128-vsx: New file.
+   * configure.ac (powerpc*-*-linux*): Determine if the default powerpc cpu
+   includes VSX support.
+   * configure: Regenerate.
+
  Branch work171-bugs, patch #310 was reverted 

  Branch work171-bugs, patch #304 was reverted 

  Branch work171-bugs, patch #303 was reverted 

[gcc r14-10415] s390: Align *cjump_64 and *icjump_64

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:cd11413ff7c4353a3e336db415304f788d23a393

commit r14-10415-gcd11413ff7c4353a3e336db415304f788d23a393
Author: Stefan Schulze Frielinghaus 
Date:   Sat Jul 13 08:01:51 2024 +0200

s390: Align *cjump_64 and *icjump_64

During machine reorg we optimize backward jumps and transform insns as
e.g.

(jump_insn 118 117 119 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(label_ref 134)
(pc))) "dec_math_1.f90":204:8 discrim 1 2161 {*cjump_64}
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 134)

into

(jump_insn 118 117 432 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(pc)
(label_ref 433))) "dec_math_1.f90":204:8 discrim 1 -1
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 433)

The latter is not recognized anymore since *icjump_64 only matches
CC_REGNUM against zero.  Fixed by aligning *cjump_64 and *icjump_64.

gcc/ChangeLog:

* config/s390/s390.md (*icjump_64): Allow raw CC comparisons,
i.e., any constant integer between 0 and 15 for CC comparisons.

(cherry picked from commit 56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d)

Diff:
---
 gcc/config/s390/s390.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index c607dce3cf0f..202aeb39d692 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -9526,7 +9526,8 @@
 (define_insn "*icjump_64"
   [(set (pc)
 (if_then_else
-  (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
+  (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
+  (match_operand 2 
"const_int_operand" "")])
   (pc)
   (label_ref (match_operand 0 "" ""]
   ""

[gcc r14-10416] s390: Fix output template for movv1qi

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:5ade7afdefe7a5179c6a139103885c2cf911d9d0

commit r14-10416-g5ade7afdefe7a5179c6a139103885c2cf911d9d0
Author: Stefan Schulze Frielinghaus 
Date:   Sat Jul 13 08:01:59 2024 +0200

s390: Fix output template for movv1qi

Although for instructions MVI and MVIY it does not make a difference
whether the immediate is interpreted as signed or unsigned, GAS expects
unsigned immediates for instruction format SI_URD.

gcc/ChangeLog:

* config/s390/vector.md (mov): Fix output template for
movv1qi.

(cherry picked from commit e6680d3f392f7f7cc2a1515276213e21e9eeab1c)

Diff:
---
 gcc/config/s390/vector.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index ed4742d93c91..7577f979243f 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -359,8 +359,8 @@
lr\t%0,%1
mvi\t%0,0
mviy\t%0,0
-   mvi\t%0,-1
-   mviy\t%0,-1
+   mvi\t%0,255
+   mviy\t%0,255
lhi\t%0,0
lhi\t%0,-1
llc\t%0,%1

[gcc r14-10417] LoongArch: TFmode is not allowed to be stored in the float register.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:89f9342980b7976f98ba43fac6a64a7a2214b6e6

commit r14-10417-g89f9342980b7976f98ba43fac6a64a7a2214b6e6
Author: Lulu Cheng 
Date:   Thu Jul 4 10:37:26 2024 +0800

LoongArch: TFmode is not allowed to be stored in the float register.

PR target/115752

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Replace
UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
* config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr115752.c: New test.

(cherry picked from commit abeb6c8a62758faa0719e818e6e8a7db15a6793b)

Diff:
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 gcc/config/loongarch/loongarch.h  | 7 ---
 gcc/testsuite/gcc.target/loongarch/pr115752.c | 8 
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 1b6df6a43650..4b456e3ef1f5 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6705,7 +6705,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
   if (mclass == MODE_FLOAT
  || mclass == MODE_COMPLEX_FLOAT
  || mclass == MODE_VECTOR_FLOAT)
-   return size <= UNITS_PER_FPVALUE;
+   return size <= UNITS_PER_HWFPVALUE;
 
   /* Allow integer modes that fit into a single register.  We need
 to put integers into FPRs when using instructions like CVT
diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
index f7fe950f3332..6be1029bef9d 100644
--- a/gcc/config/loongarch/loongarch.h
+++ b/gcc/config/loongarch/loongarch.h
@@ -146,13 +146,6 @@ along with GCC; see the file COPYING3.  If not see
 #define UNITS_PER_HWFPVALUE \
   (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FP_REG)
 
-/* The largest size of value that can be held in floating-point
-   registers.  */
-#define UNITS_PER_FPVALUE \
-  (TARGET_SOFT_FLOAT ? 0 \
-   : TARGET_SINGLE_FLOAT ? UNITS_PER_FP_REG \
-: LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
-
 /* The number of bytes in a double.  */
 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
 
diff --git a/gcc/testsuite/gcc.target/loongarch/pr115752.c 
b/gcc/testsuite/gcc.target/loongarch/pr115752.c
new file mode 100644
index ..df4bae524f75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr115752.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+long double
+test (long double xx)
+{
+   __asm ("" :: "f"(xx)); /* { dg-error "inconsistent operand constraints in 
an 'asm'" } */
+   return xx + 1;
+}

[gcc r13-8910] LoongArch: TFmode is not allowed to be stored in the float register.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:616c3290785c204b3019e7aaff8a7d9bb425d336

commit r13-8910-g616c3290785c204b3019e7aaff8a7d9bb425d336
Author: Lulu Cheng 
Date:   Thu Jul 4 10:37:26 2024 +0800

LoongArch: TFmode is not allowed to be stored in the float register.

PR target/115752

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Replace
UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
* config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr115752.c: New test.

(cherry picked from commit abeb6c8a62758faa0719e818e6e8a7db15a6793b)

Diff:
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 gcc/config/loongarch/loongarch.h  | 7 ---
 gcc/testsuite/gcc.target/loongarch/pr115752.c | 8 
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 2238858cd6ab..be26e156beb8 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -5491,7 +5491,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
   if (mclass == MODE_FLOAT
  || mclass == MODE_COMPLEX_FLOAT
  || mclass == MODE_VECTOR_FLOAT)
-   return size <= UNITS_PER_FPVALUE;
+   return size <= UNITS_PER_HWFPVALUE;
 
   /* Allow integer modes that fit into a single register.  We need
 to put integers into FPRs when using instructions like CVT
diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
index d072522e3cfe..b1149a12aba4 100644
--- a/gcc/config/loongarch/loongarch.h
+++ b/gcc/config/loongarch/loongarch.h
@@ -202,13 +202,6 @@ along with GCC; see the file COPYING3.  If not see
 #define UNITS_PER_HWFPVALUE \
   (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FPREG)
 
-/* The largest size of value that can be held in floating-point
-   registers.  */
-#define UNITS_PER_FPVALUE \
-  (TARGET_SOFT_FLOAT ? 0 \
-   : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
-: LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
-
 /* The number of bytes in a double.  */
 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
 
diff --git a/gcc/testsuite/gcc.target/loongarch/pr115752.c 
b/gcc/testsuite/gcc.target/loongarch/pr115752.c
new file mode 100644
index ..df4bae524f75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr115752.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+long double
+test (long double xx)
+{
+   __asm ("" :: "f"(xx)); /* { dg-error "inconsistent operand constraints in 
an 'asm'" } */
+   return xx + 1;
+}