[gcc r14-10058] AVR: target/114794 - Tweak __udivmodqi4
https://gcc.gnu.org/g:a44d16efa7a508f8b8f303417d0714c39f159725 commit r14-10058-ga44d16efa7a508f8b8f303417d0714c39f159725 Author: Georg-Johann Lay Date: Sun Apr 21 14:33:50 2024 +0200 AVR: target/114794 - Tweak __udivmodqi4 libgcc/ PR target/114794 * config/avr/lib1funcs.S (__udivmodqi4): Tweak. Diff: --- libgcc/config/avr/lib1funcs.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libgcc/config/avr/lib1funcs.S b/libgcc/config/avr/lib1funcs.S index 535510ab867..af4d7d97016 100644 --- a/libgcc/config/avr/lib1funcs.S +++ b/libgcc/config/avr/lib1funcs.S @@ -1339,9 +1339,9 @@ ENDF __umulsidi3 #if defined (L_udivmodqi4) DEFUN __udivmodqi4 - sub r_rem,r_rem ; clear remainder and carry - ldi r_cnt,9 ; init loop counter - rjmp__udivmodqi4_ep ; jump to entry point + clr r_rem ; clear remainder + ldi r_cnt,8 ; init loop counter + lsl r_arg1 ; shift dividend __udivmodqi4_loop: rol r_rem ; shift dividend into remainder cp r_rem,r_arg2; compare remainder & divisor
[gcc r13-8638] AVR: target/114794 - Tweak __udivmodqi4
https://gcc.gnu.org/g:7bd8428da72a0a1d3bef4e50be4b60b981ed540d commit r13-8638-g7bd8428da72a0a1d3bef4e50be4b60b981ed540d Author: Georg-Johann Lay Date: Sun Apr 21 14:33:50 2024 +0200 AVR: target/114794 - Tweak __udivmodqi4 libgcc/ PR target/114794 * config/avr/lib1funcs.S (__udivmodqi4): Tweak. (cherry picked from commit a44d16efa7a508f8b8f303417d0714c39f159725) Diff: --- libgcc/config/avr/lib1funcs.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libgcc/config/avr/lib1funcs.S b/libgcc/config/avr/lib1funcs.S index 0870595111a..4ee651bf6ea 100644 --- a/libgcc/config/avr/lib1funcs.S +++ b/libgcc/config/avr/lib1funcs.S @@ -1339,9 +1339,9 @@ ENDF __umulsidi3 #if defined (L_udivmodqi4) DEFUN __udivmodqi4 - sub r_rem,r_rem ; clear remainder and carry - ldi r_cnt,9 ; init loop counter - rjmp__udivmodqi4_ep ; jump to entry point + clr r_rem ; clear remainder + ldi r_cnt,8 ; init loop counter + lsl r_arg1 ; shift dividend __udivmodqi4_loop: rol r_rem ; shift dividend into remainder cp r_rem,r_arg2; compare remainder & divisor
[gcc r12-10369] Testsuite, i386: Mark test as requiring ifunc
https://gcc.gnu.org/g:711506673963587572a5a97fc86809378ac76656
commit r12-10369-g711506673963587572a5a97fc86809378ac76656
Author: Francois-Xavier Coudert
Date: Mon Oct 30 15:41:10 2023 +0100
Testsuite, i386: Mark test as requiring ifunc
Test is currently failing on x86_64-apple-darwin.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr105554.c: Require ifunc.
(cherry picked from commit 7666d94db0684f04264712f3e3fdb542518960c5)
Diff:
---
gcc/testsuite/gcc.target/i386/pr105554.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/i386/pr105554.c
b/gcc/testsuite/gcc.target/i386/pr105554.c
index 08e90bb3368..e9ef494270a 100644
--- a/gcc/testsuite/gcc.target/i386/pr105554.c
+++ b/gcc/testsuite/gcc.target/i386/pr105554.c
@@ -1,5 +1,6 @@
/* PR target/105554 */
/* { dg-do compile } */
+/* { dg-require-ifunc "" } */
/* { dg-options "-O2 -Wno-psabi -mno-sse3" } */
typedef long long v4di __attribute__((__vector_size__(32)));
[gcc r12-10368] Testsuite, DWARF2: adjust regexp to match darwin output
https://gcc.gnu.org/g:57506ac6ece97188c427e075e08b8128822fcd1e
commit r12-10368-g57506ac6ece97188c427e075e08b8128822fcd1e
Author: Francois-Xavier Coudert
Date: Sun Aug 20 12:53:19 2023 +0200
Testsuite, DWARF2: adjust regexp to match darwin output
gcc/testsuite/ChangeLog:
* gcc.dg/debug/dwarf2/inline4.c: Ajdust regexp to match darwin
output.
(cherry picked from commit 94e68ce96c285e479736851f1ad8cc87c8c3ff0c)
Diff:
---
gcc/testsuite/gcc.dg/debug/dwarf2/inline4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/inline4.c
b/gcc/testsuite/gcc.dg/debug/dwarf2/inline4.c
index 2faef6e2a4f..22eb35fcf09 100644
--- a/gcc/testsuite/gcc.dg/debug/dwarf2/inline4.c
+++ b/gcc/testsuite/gcc.dg/debug/dwarf2/inline4.c
@@ -2,7 +2,7 @@
the DW_TAG_inlined_subroutine and the DW_TAG_variable for the local. */
/* { dg-options "-O -gdwarf -dA" } */
/* { dg-do compile } */
-/* { dg-final { scan-assembler
"DW_TAG_inlined_subroutine\[^\\(\]*\\(\[^\\)\]*\\)\[^\\(\]*\\(DIE
\\(0x\[0-9a-f\]*\\) DW_TAG_formal_parameter\[^\\(\]*\\(DIE \\(0x\[0-9a-f\]*\\)
DW_TAG_variable" } } */
+/* { dg-final { scan-assembler
"DW_TAG_inlined_subroutine\[^\\(\]*\(\|\\(\[^\\)\]*\\)\)\[^\\(\]*\\(DIE
\\(0x\[0-9a-f\]*\\) DW_TAG_formal_parameter\[^\\(\]*\\(DIE \\(0x\[0-9a-f\]*\\)
DW_TAG_variable" } } */
/* { dg-final { scan-assembler-times "DW_TAG_inlined_subroutine" 2 } } */
static int foo (int i)
[gcc r12-10370] Testsuite: restrict test to nonpic targets
https://gcc.gnu.org/g:0eb6f8874047f7e7f13027aaac14d3de276c5e69
commit r12-10370-g0eb6f8874047f7e7f13027aaac14d3de276c5e69
Author: Francois-Xavier Coudert
Date: Mon Dec 11 09:26:23 2023 +0100
Testsuite: restrict test to nonpic targets
The test is currently failing on x86_64-apple-darwin.
gcc/testsuite/ChangeLog:
PR testsuite/112297
* gcc.target/i386/pr100936.c: Require nonpic target.
(cherry picked from commit 02f562484c17522d79a482ac702a5fa3c2dfdd10)
Diff:
---
gcc/testsuite/gcc.target/i386/pr100936.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/i386/pr100936.c
b/gcc/testsuite/gcc.target/i386/pr100936.c
index c076cbb2405..af494946fcd 100644
--- a/gcc/testsuite/gcc.target/i386/pr100936.c
+++ b/gcc/testsuite/gcc.target/i386/pr100936.c
@@ -1,6 +1,7 @@
/* PR target/100936 */
/* { dg-do assemble } */
/* { dg-options "-O2" } */
+/* { dg-require-effective-target nonpic } */
__seg_gs int var;
[gcc r12-10371] Darwin, testsuite: -bind_at_load is deprecated
https://gcc.gnu.org/g:1cd44c5e28533963b8cc7ddcac38e1b87c7c5dd1
commit r12-10371-g1cd44c5e28533963b8cc7ddcac38e1b87c7c5dd1
Author: Francois-Xavier Coudert
Date: Sat Feb 10 12:55:29 2024 +0100
Darwin, testsuite: -bind_at_load is deprecated
gcc/testsuite/ChangeLog:
* gcc.dg/darwin-ld-2.c: Ignore warning
that -bind_at_load is deprecated.
(cherry picked from commit f88219333e85a05a98468f67d2f2190fc330044e)
Diff:
---
gcc/testsuite/gcc.dg/darwin-ld-2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/darwin-ld-2.c
b/gcc/testsuite/gcc.dg/darwin-ld-2.c
index 5de19524f0b..2a6b491da5b 100644
--- a/gcc/testsuite/gcc.dg/darwin-ld-2.c
+++ b/gcc/testsuite/gcc.dg/darwin-ld-2.c
@@ -3,6 +3,7 @@
/* { dg-options "-bind_at_load" } */
/* { dg-do link { target *-*-darwin* } } */
+/* { dg-prune-output "-bind_at_load is deprecated" } */
int main()
{
[gcc r12-10372] Darwin, testsuite: -multiply_defined is obsolete
https://gcc.gnu.org/g:d450d2b3d0b36d5f2715f204cb0ad2ff1759d3c8
commit r12-10372-gd450d2b3d0b36d5f2715f204cb0ad2ff1759d3c8
Author: Francois-Xavier Coudert
Date: Sat Feb 10 15:52:44 2024 +0100
Darwin, testsuite: -multiply_defined is obsolete
gcc/testsuite/ChangeLog:
* gcc.dg/ssp-2.c: Ignore warning that
-multiply_defined is obsolete
(cherry picked from commit 6b13e32162adf9e4f552e09c46f1de531ffa8c05)
Diff:
---
gcc/testsuite/gcc.dg/ssp-2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/ssp-2.c b/gcc/testsuite/gcc.dg/ssp-2.c
index 752fe5393f4..608ca300032 100644
--- a/gcc/testsuite/gcc.dg/ssp-2.c
+++ b/gcc/testsuite/gcc.dg/ssp-2.c
@@ -1,6 +1,7 @@
/* { dg-do run { target native } } */
/* { dg-options "-fstack-protector" } */
/* { dg-options "-fstack-protector -Wl,-multiply_defined,suppress" { target
*-*-darwin* } } */
+/* { dg-prune-output "-multiply_defined is obsolete" } */
/* { dg-require-effective-target fstack_protector } */
#include
[gcc r12-10373] libstdc++, Darwin: Do not use dev/null as the file for executables.
https://gcc.gnu.org/g:678f6bc1655d9bf4ecec06e733122823a512ee4d
commit r12-10373-g678f6bc1655d9bf4ecec06e733122823a512ee4d
Author: Iain Sandoe
Date: Tue Mar 19 10:40:50 2024 +
libstdc++, Darwin: Do not use dev/null as the file for executables.
Darwin has a separate debug linker, which is invoked when the command
line contains source files and debug is enabled.
Using /dev/null as the executable name does not, therefore, work when
debug is enabled, since the debug linker does not accept /dev/null as
a valid executable name.
The leads to incorrectly UNSUPPORTED testcases because of the unintended
error result from the test compilation.
The solution here is to use a temporary file that is deleted at the
end of the test (which is the mechanism used elsewhere)
libstdc++-v3/ChangeLog:
* testsuite/lib/libstdc++.exp (v3_target_compile): Instead of
/dev/null, use a temporary file for test executables on Darwin.
Signed-off-by: Iain Sandoe
(cherry picked from commit e47330d0742c985fd8d5fe7089aa381d34967d61)
Diff:
---
libstdc++-v3/testsuite/lib/libstdc++.exp | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/libstdc++-v3/testsuite/lib/libstdc++.exp
b/libstdc++-v3/testsuite/lib/libstdc++.exp
index 0debbea7ee1..789d0fce549 100644
--- a/libstdc++-v3/testsuite/lib/libstdc++.exp
+++ b/libstdc++-v3/testsuite/lib/libstdc++.exp
@@ -510,11 +510,41 @@ proc v3_target_compile { source dest type options } {
}
}
+# For Windows and Darwin we might want to create a temporary file.
+# Note that it needs deleting.
+set file_to_delete ""
+# Small adjustment for Windows hosts.
+if { $dest == "/dev/null"
+ && [info exists ::env(OS)] && [string match "Windows*" $::env(OS)] } {
+ if { $type == "executable" } {
+ set dest "x.exe"
+ set file_to_delete ${dest}
+ } else {
+ # Windows uses special file named "nul" as a substitute for
+ # /dev/null
+ set dest "nul"
+ }
+}
+
+# Using /dev/null as the executable name does not work on Darwin when
+# debug is enabled, since the debug linker does not accept /dev/null as
+# a valid executable name.
+if { $dest == "/dev/null" && [istarget *-*-darwin*]
+ && $type == "executable" } {
+ set dest dev-null-[pid].exe
+ set file_to_delete ${dest}
+}
+
lappend options "compiler=$cxx_final"
lappend options "timeout=[timeout_value]"
set comp_output [target_compile $source $dest $type $options]
-
+if { $type == "executable" && $file_to_delete != "" } {
+ file delete $file_to_delete
+ if { [istarget *-*-darwin*] && [file exists $file_to_delete.dSYM] } {
+ file delete -force $file_to_delete.dSYM
+ }
+}
return $comp_output
}
[gcc r12-10374] libstdc++: Sync the atomic_link_flags implementation with GCC.
https://gcc.gnu.org/g:63842c1dd7f48ed8b8284455c05ea5dfccfcd42b
commit r12-10374-g63842c1dd7f48ed8b8284455c05ea5dfccfcd42b
Author: Iain Sandoe
Date: Mon Mar 18 09:57:33 2024 +
libstdc++: Sync the atomic_link_flags implementation with GCC.
For Darwin, in order to allow uninstalled testing, we need to provide
a '-B' option pointing to each path containing an uninstalled library
that we are using (these get appended to the embedded runpaths).
This updates the version of the atomic_link_flags proc in the libstdc++
testsuite to do the same as the one in the GCC testsuite.
libstdc++-v3/ChangeLog:
* testsuite/lib/dg-options.exp (atomic_link_flags): Emit a -B
option for the path to the uninstalled libatomic.
Signed-off-by: Iain Sandoe
(cherry picked from commit 71a44faa8a4f76d68356c66c6054e6c242df820f)
Diff:
---
libstdc++-v3/testsuite/lib/dg-options.exp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libstdc++-v3/testsuite/lib/dg-options.exp
b/libstdc++-v3/testsuite/lib/dg-options.exp
index 203bb0dfed5..7269b6a4efc 100644
--- a/libstdc++-v3/testsuite/lib/dg-options.exp
+++ b/libstdc++-v3/testsuite/lib/dg-options.exp
@@ -274,7 +274,7 @@ proc atomic_link_flags { paths } {
if { [file exists "${gccpath}/libatomic/.libs/libatomic.a"]
|| [file exists
"${gccpath}/libatomic/.libs/libatomic.${shlib_ext}"] } {
append flags " -B${gccpath}/libatomic/ "
- append flags " -L${gccpath}/libatomic/.libs"
+ append flags " -B${gccpath}/libatomic/.libs"
append ld_library_path ":${gccpath}/libatomic/.libs"
}
} else {
[gcc r12-10375] testsuite, Darwin: Use the IOKit framework in framework-1.c [PR114049].
https://gcc.gnu.org/g:4c8d37badaa42e85218eb9b89aef3e4f6cf4486e
commit r12-10375-g4c8d37badaa42e85218eb9b89aef3e4f6cf4486e
Author: Iain Sandoe
Date: Mon Mar 18 10:06:44 2024 +
testsuite, Darwin: Use the IOKit framework in framework-1.c [PR114049].
The intent of the test is to show that we find a framework that
is installed in /System/Library/Frameworks when the user has added
a '-F' option. The trick is to choose some header that is present
for all the Darwin versions we support and that does not contain any
content we cannot parse. We had been using the Kernel framework for
this, but recent SDK versions have revealed that this is not suitable.
Replacing with a use of IOKit.
PR target/114049
gcc/testsuite/ChangeLog:
* gcc.dg/framework-1.c: Use an IOKit header instead of a
Kernel one.
Signed-off-by: Iain Sandoe
(cherry picked from commit 4adb1a5839e7a3310a127c1776f1f95d7edaa6ff)
Diff:
---
gcc/testsuite/gcc.dg/framework-1.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/framework-1.c
b/gcc/testsuite/gcc.dg/framework-1.c
index de4adc39868..fdec129a8fb 100644
--- a/gcc/testsuite/gcc.dg/framework-1.c
+++ b/gcc/testsuite/gcc.dg/framework-1.c
@@ -1,4 +1,10 @@
/* { dg-do compile { target *-*-darwin* } } */
/* { dg-options "-F." } */
-#include
+/* The intent of the test is to show that we find a framework that
+ is installed in /System/Library/Frameworks when the user has added
+ a '-F' option. The trick is to choose some header that is present
+ for all the Darwin versions we support and that does not contain any
+ content we cannot parse. */
+
+#include
[gcc r12-10376] libstdc++, Darwin: Handle a linker warning [PR112397].
https://gcc.gnu.org/g:77f17e405a0669db9a6c8af69bde6eb1170f48bd
commit r12-10376-g77f17e405a0669db9a6c8af69bde6eb1170f48bd
Author: Iain Sandoe
Date: Thu Feb 8 17:54:31 2024 +
libstdc++, Darwin: Handle a linker warning [PR112397].
Darwin's linker warns when we make a direct branch to code that is
in a weak definition (citing that if a different implementation of
the weak function is chosen by the dynamic linker this would be an
error).
As the analysis in the PR shows, this can happen when we have hot/
cold partitioning and there is an error path that is primarily cold
but makes use of epilogue code in the hot section. In this simple
case, we can easily deduce that the code is in fact safe; however
that is not something we can realistically implement in the linker.
Since the user-replaceable allocators are implemented using weak
definitions, this is a warning that is frequently flagged up in both
the testsuite and end-user code.
The chosen solution here is to suppress the hot/cold partitioning for
these cases (it is unlikely to impact performance much c.f. the
actual allocation).
PR target/112397
libstdc++-v3/ChangeLog:
* configure: Regenerate.
* configure.ac: Detect if we are building for Darwin.
* libsupc++/Makefile.am: If we are building for Darwin, then
suppress hot/cold partitioning for the array allocators.
* libsupc++/Makefile.in: Regenerated.
Signed-off-by: Iain Sandoe
Co-authored-by: Jonathan Wakely
(cherry picked from commit 1609fdff16f17ead37666f6d0e801800ee3d04d2)
Diff:
---
libstdc++-v3/configure | 36
libstdc++-v3/configure.ac | 7 +++
libstdc++-v3/libsupc++/Makefile.am | 8
libstdc++-v3/libsupc++/Makefile.in | 6 ++
4 files changed, 49 insertions(+), 8 deletions(-)
diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure
index bc92ce1303c..ccc23f1b352 100755
--- a/libstdc++-v3/configure
+++ b/libstdc++-v3/configure
@@ -786,6 +786,8 @@ GLIBCXX_HOSTED_TRUE
glibcxx_compiler_shared_flag
glibcxx_compiler_pic_flag
glibcxx_lt_pic_flag
+OS_IS_DARWIN_FALSE
+OS_IS_DARWIN_TRUE
enable_static
enable_shared
lt_host_flags
@@ -12191,7 +12193,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12194 "configure"
+#line 12196 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -12297,7 +12299,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12300 "configure"
+#line 12302 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -15579,6 +15581,20 @@ esac
+os_is_darwin=no
+case ${host_os} in
+ darwin*) os_is_darwin=yes ;;
+ *) ;;
+esac
+ if test x${os_is_darwin} = xyes; then
+ OS_IS_DARWIN_TRUE=
+ OS_IS_DARWIN_FALSE='#'
+else
+ OS_IS_DARWIN_TRUE='#'
+ OS_IS_DARWIN_FALSE=
+fi
+
+
if test "$enable_vtable_verify" = yes; then
predep_objects_CXX="${predep_objects_CXX}
${glibcxx_builddir}/../libgcc/vtv_start.o"
postdep_objects_CXX="${postdep_objects_CXX}
${glibcxx_builddir}/../libgcc/vtv_end.o"
@@ -15981,7 +15997,7 @@ $as_echo "$glibcxx_cv_atomic_long_long" >&6; }
# Fake what AC_TRY_COMPILE does.
cat > conftest.$ac_ext << EOF
-#line 15984 "configure"
+#line 16000 "configure"
int main()
{
typedef bool atomic_type;
@@ -16016,7 +16032,7 @@ $as_echo "$glibcxx_cv_atomic_bool" >&6; }
rm -f conftest*
cat > conftest.$ac_ext << EOF
-#line 16019 "configure"
+#line 16035 "configure"
int main()
{
typedef short atomic_type;
@@ -16051,7 +16067,7 @@ $as_echo "$glibcxx_cv_atomic_short" >&6; }
rm -f conftest*
cat > conftest.$ac_ext << EOF
-#line 16054 "configure"
+#line 16070 "configure"
int main()
{
// NB: _Atomic_word not necessarily int.
@@ -16087,7 +16103,7 @@ $as_echo "$glibcxx_cv_atomic_int" >&6; }
rm -f conftest*
cat > conftest.$ac_ext << EOF
-#line 16090 "configure"
+#line 16106 "configure"
int main()
{
typedef long long atomic_type;
@@ -16243,7 +16259,7 @@ $as_echo "mutex" >&6; }
# unnecessary for this test.
cat > conftest.$ac_ext << EOF
-#line 16246 "configure"
+#line 16262 "configure"
int main()
{
_Decimal32 d1;
@@ -16285,7 +16301,7 @@ ac_compiler_gnu=$ac_cv_cxx_compiler_gnu
# unnecessary for this test.
cat > conftest.$ac_ext << EOF
-#line 16288 "configure"
+#line 16304 "configure"
template
struct same
{ typedef T2 type; };
@@ -79293,6 +79309,10 @@ if test -z "${MAINTAINER_MODE_TRUE}" && test -z
"${MAINTAINER_MODE_FALSE}"; then
as_fn_error $? "conditional \"MAINTAINER_MODE\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${OS_IS_DARWIN_TRUE}" && test -z "${OS_IS_DARWIN_FALSE}"; then
[gcc r12-10377] libphobos, Darwin: Enable libphobos for most Darwin.
https://gcc.gnu.org/g:50dd6d3cf89214a97c13f0983bd1e87c306dff51
commit r12-10377-g50dd6d3cf89214a97c13f0983bd1e87c306dff51
Author: Iain Sandoe
Date: Mon Apr 1 13:58:20 2024 +0100
libphobos, Darwin: Enable libphobos for most Darwin.
Earlier Darwin systems can be made to work too - but they need non-
standard 'binutils', so for now these must be enabled specifically.
libphobos/ChangeLog:
* configure.tgt: Enable libphobos for Darwin >= 12.
Signed-off-by: Iain Sandoe
Diff:
---
libphobos/configure.tgt | 9 +
1 file changed, 9 insertions(+)
diff --git a/libphobos/configure.tgt b/libphobos/configure.tgt
index 0063dd23249..817d41a4d2d 100644
--- a/libphobos/configure.tgt
+++ b/libphobos/configure.tgt
@@ -27,6 +27,9 @@ case "${target}" in
*-*-dragonfly*)
LIBPHOBOS_SUPPORTED=yes
;;
+ aarch64-*-darwin2*)
+ LIBPHOBOS_SUPPORTED=yes
+ ;;
aarch64*-*-linux*)
LIBPHOBOS_SUPPORTED=yes
;;
@@ -55,6 +58,12 @@ case "${target}" in
sparc*-*-solaris2.11*)
LIBPHOBOS_SUPPORTED=yes
;;
+ *-*-darwin9* | *-*-darwin1[01]*)
+ LIBDRUNTIME_ONLY=yes
+ ;;
+ x86_64-*-darwin1[2-9]* | x86_64-*-darwin2* | i?86-*-darwin1[2-7])
+ LIBPHOBOS_SUPPORTED=yes
+ ;;
x86_64-*-freebsd* | i?86-*-freebsd*)
LIBPHOBOS_SUPPORTED=yes
;;
[gcc r12-10378] Darwin: Do not emit .macinfo when dsymutil cannot consume it.
https://gcc.gnu.org/g:8f0f24387945ef03fcd61bf978565145bfaf3493
commit r12-10378-g8f0f24387945ef03fcd61bf978565145bfaf3493
Author: Iain Sandoe
Date: Sun Mar 31 23:25:31 2024 +0100
Darwin: Do not emit .macinfo when dsymutil cannot consume it.
Some verions of dsymutil do not ignore .macinfo sections, but instead
ignore the entire debug in the file.
To avoid this total loss of debug, when we detect that the debug level
is g3 and the dsymutil version cannot support it, we reduce the level
to g2 and issue a note.
This behaviour can be overidden by -gstrict-dwarf (although the objects
will contain macinfo; dsymutil will not produce a .dSYM with it).
gcc/ChangeLog:
* config/darwin.cc (darwin_override_options): Reduce the debug
level to 2 if dsymutil cannot handle .macinfo sections.
Signed-off-by: Iain Sandoe
(cherry picked from commit 3c499f8f6f7d19b21d7047efabbe6396ee1c2cac)
Diff:
---
gcc/config/darwin.cc | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/gcc/config/darwin.cc b/gcc/config/darwin.cc
index 3cbdc97662d..6153f3c39fe 100644
--- a/gcc/config/darwin.cc
+++ b/gcc/config/darwin.cc
@@ -3376,11 +3376,6 @@ darwin_override_options (void)
global_options.x_flag_objc_abi);
}
- /* Limit DWARF to the chosen version, the linker and debug linker might not
- be able to consume newer structures. */
- if (!OPTION_SET_P (dwarf_strict))
-dwarf_strict = 1;
-
if (!OPTION_SET_P (dwarf_version))
{
/* External toolchains based on LLVM or clang 7+ have support for
@@ -3403,6 +3398,24 @@ darwin_override_options (void)
OPTION_SET_P (dwarf_split_debug_info) = 0;
}
+ /* Cases where dsymutil will exclude files with .macinfo sections; we are
+ better off forcing the debug level to 2 than completely excluding the
+ files. If strict dwarf is set, then emit the macinfo anyway. */
+ if (debug_info_level == DINFO_LEVEL_VERBOSE
+ && (!OPTION_SET_P (dwarf_strict) || dwarf_strict == 0)
+ && ((dsymutil_version.kind == CLANG && dsymutil_version.major >= 1500)
+ || (dsymutil_version.kind == LLVM && dsymutil_version.major >= 15)))
+{
+ inform (input_location,
+ "%<-g3%> is not supported by the debug linker in use (set to 2)");
+ debug_info_level = DINFO_LEVEL_NORMAL;
+}
+
+ /* Limit DWARF to the chosen version, the linker and debug linker might not
+ be able to consume newer structures. */
+ if (!OPTION_SET_P (dwarf_strict))
+dwarf_strict = 1;
+
/* Do not allow unwind tables to be generated by default for m32.
fnon-call-exceptions will override this, regardless of what we do. */
if (generating_for_darwin_version < 10
[gcc r12-10379] testsuite, Darwin: Allow for an undefined symbol [PR114036].
https://gcc.gnu.org/g:ed046c2cc0f0a2d00cc77e5e9ce5d8f71e2278c6
commit r12-10379-ged046c2cc0f0a2d00cc77e5e9ce5d8f71e2278c6
Author: Iain Sandoe
Date: Sun Mar 31 11:27:53 2024 +0100
testsuite, Darwin: Allow for an undefined symbol [PR114036].
Darwin's linker defaults to requiring all symbols to be defined at
static link time (unless specifically noted or dynamic lookuo is
enabled).
For this test, we just need to note that the symbol is expected to
be undefined.
PR testsuite/114036
gcc/testsuite/ChangeLog:
* gcc.misc-tests/gcov-14.c: Allow for 'Foo' to be undefined
on Darwin link lines.
Signed-off-by: Iain Sandoe
(cherry picked from commit ad8e34eaa870608e2b07b4e7147e6ef2944bb8b5)
Diff:
---
gcc/testsuite/gcc.misc-tests/gcov-14.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.misc-tests/gcov-14.c
b/gcc/testsuite/gcc.misc-tests/gcov-14.c
index 2bebf7e4a93..61a9191c068 100644
--- a/gcc/testsuite/gcc.misc-tests/gcov-14.c
+++ b/gcc/testsuite/gcc.misc-tests/gcov-14.c
@@ -3,7 +3,7 @@
/* { dg-do run { target native } } */
/* { dg-options "-O2 -fprofile-arcs -ftest-coverage -fgnu89-inline" } */
/* The following line arranges that Darwin has behavior like elf weak import.
*/
-/* { dg-additional-options "-flat_namespace -undefined suppress" { target
*-*-darwin* } } */
+/* { dg-additional-options "-Wl,-U,_Foo" { target *-*-darwin* } } */
/* { dg-require-weak "" } */
/* { dg-skip-if "undefined weak not supported" { { hppa*-*-hpux* } && { ! lp64
} } } */
/* { dg-skip-if "undefined weak not supported" { powerpc-ibm-aix* } } */
[gcc r14-10059] Fortran: Detect 'no implicit type' error in right place [PR103471]
https://gcc.gnu.org/g:f17d31e709af9b2d488adecd6cd040dfc1f23b04
commit r14-10059-gf17d31e709af9b2d488adecd6cd040dfc1f23b04
Author: Paul Thomas
Date: Sun Apr 21 17:24:24 2024 +0100
Fortran: Detect 'no implicit type' error in right place [PR103471]
2024-04-21 Paul Thomas
gcc/fortran
PR fortran/103471
* resolve.cc (resolve_actual_arglist): Catch variables silently
set as untyped, resetting the flag so that gfc_resolve_expr can
generate the no implicit type error.
(gfc_resolve_index_1): Block index expressions of unknown type
from being converted to default integer, avoiding the fatal
error in trans-decl.cc.
* symbol.cc (gfc_set_default_type): Remove '(symbol)' from the
'no IMPLICIT type' error message.
* trans-decl.cc (gfc_get_symbol_decl): Change fatal error locus
to that of the symbol declaration.
(gfc_trans_deferred_vars): Remove two trailing tabs.
gcc/testsuite/
PR fortran/103471
* gfortran.dg/pr103471.f90: New test.
Diff:
---
gcc/fortran/resolve.cc | 11 ++-
gcc/fortran/symbol.cc | 2 +-
gcc/fortran/trans-decl.cc | 7 ---
gcc/testsuite/gfortran.dg/pr103471.f90 | 18 ++
4 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc
index 6b3e5ba4fcb..4368627041e 100644
--- a/gcc/fortran/resolve.cc
+++ b/gcc/fortran/resolve.cc
@@ -2189,6 +2189,14 @@ resolve_actual_arglist (gfc_actual_arglist *arg,
procedure_type ptype,
? CLASS_DATA (sym)->as : sym->as;
}
+ /* These symbols are set untyped by calls to gfc_set_default_type
+with 'error_flag' = false. Reset the untyped attribute so that
+the error will be generated in gfc_resolve_expr. */
+ if (e->expr_type == EXPR_VARIABLE
+ && sym->ts.type == BT_UNKNOWN
+ && sym->attr.untyped)
+ sym->attr.untyped = 0;
+
/* Expressions are assigned a default ts.type of BT_PROCEDURE in
primary.cc (match_actual_arg). If above code determines that it
is a variable instead, it needs to be resolved as it was not
@@ -5001,7 +5009,8 @@ gfc_resolve_index_1 (gfc_expr *index, int check_scalar,
if ((index->ts.kind != gfc_index_integer_kind
&& force_index_integer_kind)
- || index->ts.type != BT_INTEGER)
+ || (index->ts.type != BT_INTEGER
+ && index->ts.type != BT_UNKNOWN))
{
gfc_clear_ts (&ts);
ts.type = BT_INTEGER;
diff --git a/gcc/fortran/symbol.cc b/gcc/fortran/symbol.cc
index 3a3b6de5cec..8f7deac1d1e 100644
--- a/gcc/fortran/symbol.cc
+++ b/gcc/fortran/symbol.cc
@@ -320,7 +320,7 @@ gfc_set_default_type (gfc_symbol *sym, int error_flag,
gfc_namespace *ns)
"; did you mean %qs?",
sym->name, &sym->declared_at, guessed);
else
- gfc_error ("Symbol %qs at %L has no IMPLICIT type(symbol)",
+ gfc_error ("Symbol %qs at %L has no IMPLICIT type",
sym->name, &sym->declared_at);
sym->attr.untyped = 1; /* Ensure we only give an error once. */
}
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index e160c5c98c1..301439baaf5 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -1797,7 +1797,8 @@ gfc_get_symbol_decl (gfc_symbol * sym)
}
if (sym->ts.type == BT_UNKNOWN)
-gfc_fatal_error ("%s at %C has no default type", sym->name);
+gfc_fatal_error ("%s at %L has no default type", sym->name,
+&sym->declared_at);
if (sym->attr.intrinsic)
gfc_internal_error ("intrinsic variable which isn't a procedure");
@@ -5214,8 +5215,8 @@ gfc_trans_deferred_vars (gfc_symbol * proc_sym,
gfc_wrapped_block * block)
tree tmp = lookup_attribute ("omp allocate",
DECL_ATTRIBUTES (n->sym->backend_decl));
tmp = TREE_VALUE (tmp);
- TREE_PURPOSE (tmp) = se.expr;
- TREE_VALUE (tmp) = align;
+ TREE_PURPOSE (tmp) = se.expr;
+ TREE_VALUE (tmp) = align;
TREE_PURPOSE (TREE_CHAIN (tmp)) = init_stmtlist;
TREE_VALUE (TREE_CHAIN (tmp)) = cleanup_stmtlist;
}
diff --git a/gcc/testsuite/gfortran.dg/pr103471.f90
b/gcc/testsuite/gfortran.dg/pr103471.f90
new file mode 100644
index 000..695446e034e
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr103471.f90
@@ -0,0 +1,18 @@
+! { dg-do compile }
+! Test the fix for PR103471 in which, rather than giving a "no IMPLICIT type"
+! message, gfortran took to ICEing. The fuzzy symbol check for 'kk'
demonstrates
+! that the error is being detected at the right place.
+!
+! Contributed by Gerhard Steinmetz
+!
+program p
+ implicit none
+ integer, parameter :: x(4) = [1,2,3,4]
+ real, extern
[gcc/aoliva/heads/testbase] (26 commits) Fortran: Detect 'no implicit type' error in right place [PR
The branch 'aoliva/heads/testbase' was updated to point to: f17d31e709a... Fortran: Detect 'no implicit type' error in right place [PR It previously pointed to: 694fa3717a9... [vxworks] avoid mangling __STDC_VERSION_LIMITS_H__ Diff: Summary of changes (added commits): --- f17d31e... Fortran: Detect 'no implicit type' error in right place [PR (*) a44d16e... AVR: target/114794 - Tweak __udivmodqi4 (*) ef23922... Revert "RISC-V: Support highpart register overlap for widen (*) d37b34f... RISC-V: Add xfail test case for incorrect overlap on v0 (*) a7d01a7... Daily bump. (*) 3afcb04... Revert "RISC-V: Fix overlap group incorrect overlap on v0" (*) f9a48fe... PR modula2/112893 full type checking between proctype and p (*) 1690e47... RISC-V: Add xfail test case for wv insn highest overlap (*) f5447ea... Revert "RISC-V: Support highest overlap for wv instructions (*) 9f10005... RISC-V: Add xfail test case for wv insn register overlap (*) 0cbeafe... Revert "RISC-V: Support one more overlap for wv instruction (*) 90ded75... Daily bump. (*) c23db3e... i386: Fix up *avx2_eq3 constraints [PR114783] (*) 2afdecc... c-family: Allow arguments with NULLPTR_TYPE as sentinels [P (*) a39983b... c: Fix ICE with -g and -std=c23 related to incomplete types (*) d86472a... libstdc++: Simplify constraints on <=> for std::reference_w (*) eed7fb1... libstdc++: Support link chains in std::chrono::tzdb::locate (*) e8f0540... Update gcc sv.po (*) 33bf8e5... internal-fn: Fix up expand_arith_overflow [PR114753] (*) 1216460... middle-end: refactory vect_recog_absolute_difference to sim (*) 9451b6c... Enable 'gcc.dg/pr114768.c' for nvptx target [PR114768] (*) ede01df... bpf: remove huge memory waste with string allocation. (*) d7190d0... bpf: support more instructions to match CO-RE relocations (*) 4d4929f... d: Fix ICE in build_deref, at d/d-codegen.cc:1650 [PR111650 (*) 9f29584... rtlanal: Fix set_noop_p for volatile loads or stores [PR114 (*) 36f4c8a... libgcc: Another __divmodbitint4 bug fix [PR114762] (*) (*) This commit already exists in another branch. Because the reference `refs/users/aoliva/heads/testbase' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc/aoliva/heads/testme] (40 commits) [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra
The branch 'aoliva/heads/testme' was updated to point to: b6144ccafe3... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra It previously pointed to: 8895abceb69... [testsuite] [arm] add effective target and options for pacb Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 8895abc... [testsuite] [arm] add effective target and options for pacb 4c6efa3... [libstdc++] introduce --disable-compat-libstdcxx-abi Summary of changes (added commits): --- b6144cc... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 0197e8f... ppc: testsuite: vec-mul requires vsx runtime 89e5150... add explicit ABI and align options to pr88233.c fe3c0a3... ppc: testsuite: pr79004 needs -mlong-double-128 2d28d2a... Request check for hw support in ppc run tests with -maltive ad51db7... decay vect tests from run to link for pr95401 106f3cf... adjust vectorization expectations for ppc costmodel 76b 8e6d181... disable ldist for test, to restore vectorizing-candidate lo 0e8ef1e... xfail fetestexcept test - ppc always uses fcmpu 4488f8d... add sqrt options and test for sqrt support in ppc tests 048689c... enable sqrt insns for cdce3.c 032f38d... add -mpowerpc-gpopt to options for sqrt insn on PowerPC 6996207... [testsuite] [ppc64] expect error on vxworks too 0cbe329... [testsuite] [arm] add effective target and options for pacb f17d31e... Fortran: Detect 'no implicit type' error in right place [PR (*) a44d16e... AVR: target/114794 - Tweak __udivmodqi4 (*) ef23922... Revert "RISC-V: Support highpart register overlap for widen (*) d37b34f... RISC-V: Add xfail test case for incorrect overlap on v0 (*) a7d01a7... Daily bump. (*) 3afcb04... Revert "RISC-V: Fix overlap group incorrect overlap on v0" (*) f9a48fe... PR modula2/112893 full type checking between proctype and p (*) 1690e47... RISC-V: Add xfail test case for wv insn highest overlap (*) f5447ea... Revert "RISC-V: Support highest overlap for wv instructions (*) 9f10005... RISC-V: Add xfail test case for wv insn register overlap (*) 0cbeafe... Revert "RISC-V: Support one more overlap for wv instruction (*) 90ded75... Daily bump. (*) c23db3e... i386: Fix up *avx2_eq3 constraints [PR114783] (*) 2afdecc... c-family: Allow arguments with NULLPTR_TYPE as sentinels [P (*) a39983b... c: Fix ICE with -g and -std=c23 related to incomplete types (*) d86472a... libstdc++: Simplify constraints on <=> for std::reference_w (*) eed7fb1... libstdc++: Support link chains in std::chrono::tzdb::locate (*) e8f0540... Update gcc sv.po (*) 33bf8e5... internal-fn: Fix up expand_arith_overflow [PR114753] (*) 1216460... middle-end: refactory vect_recog_absolute_difference to sim (*) 9451b6c... Enable 'gcc.dg/pr114768.c' for nvptx target [PR114768] (*) ede01df... bpf: remove huge memory waste with string allocation. (*) d7190d0... bpf: support more instructions to match CO-RE relocations (*) 4d4929f... d: Fix ICE in build_deref, at d/d-codegen.cc:1650 [PR111650 (*) 9f29584... rtlanal: Fix set_noop_p for volatile loads or stores [PR114 (*) 36f4c8a... libgcc: Another __divmodbitint4 bug fix [PR114762] (*) (*) This commit already exists in another branch. Because the reference `refs/users/aoliva/heads/testme' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [arm] add effective target and options for pacbti tests
https://gcc.gnu.org/g:0cbe32956b7bd3c91c90531cff119b6bd97efcc4
commit 0cbe32956b7bd3c91c90531cff119b6bd97efcc4
Author: Alexandre Oliva
Date: Sun Apr 21 17:23:46 2024 -0300
[testsuite] [arm] add effective target and options for pacbti tests
arm pac and bti tests that use -march=armv8.1-m.main get an implicit
-mthumb, that is incompatible with vxworks kernel mode. Declaring the
requirement for a 8.1-m.main-compatible toolchain is enough to avoid
those fails, because the toolchain feature test fails in kernel mode,
but taking the -march options from the standardized arch tests, after
testing for support for the corresponding effective target, makes it
generally safer, and enables us to drop skip directives and extraneous
option variants.
for gcc/testsuite/ChangeLog
* gcc.target/arm/bti-1.c: Require arch, use its opts, drop skip.
* gcc.target/arm/bti-2.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
* g++.target/arm/pac-1.C: Likewise. Drop +mve.
Diff:
---
gcc/testsuite/g++.target/arm/pac-1.C | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c | 4 ++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-1.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-2.c | 5 +++--
6 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.target/arm/pac-1.C
b/gcc/testsuite/g++.target/arm/pac-1.C
index f671a27b048..ac15ae18197 100644
--- a/gcc/testsuite/g++.target/arm/pac-1.C
+++ b/gcc/testsuite/g++.target/arm/pac-1.C
@@ -1,7 +1,8 @@
/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard -g -O0" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "-mbranch-protection=pac-ret -mfloat-abi=hard -g
-O0" } */
__attribute__((noinline)) void
fn1 (int a, int b, int c)
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
index 6a5ae92c567..c9c40f44027 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp+pacbti" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
#if (__ARM_FEATURE_BTI != 1)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
index db40b17c3b0..c26051347a2 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp" } */
#if defined (__ARM_FEATURE_BTI)
#error "Feature test macro __ARM_FEATURE_BTI should not be defined."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
index 1b25907635e..92f500c1449 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-additional-options "-march=armv8.1-m.main+pacbti+fp --save-temps
-mfloat-abi=hard" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "--save-temps -mfloat-abi=hard" } */
#if defined (__ARM_FEATURE_BTI_DEFAULT)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined."
diff --git a/gcc/testsuite/gcc.target/arm/bti-1.c
b/gcc/testsuite/gcc.target/arm/bti-1.c
index 79dd8010d2d..a34bb0842b6 100644
--- a/gcc/testsuite/gcc.target/arm/bti-1.c
+++ b/gcc/test
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [ppc64] expect error on vxworks too
https://gcc.gnu.org/g:6996207325751e10e468d03c9fe492f2ad5161f2
commit 6996207325751e10e468d03c9fe492f2ad5161f2
Author: Alexandre Oliva
Date: Sun Apr 21 17:23:52 2024 -0300
[testsuite] [ppc64] expect error on vxworks too
These ppc lp64 tests check for errors or warnings on -mno-powerpc64.
On powerpc64-*-vxworks* we get the same errors as on most other
covered platforms, but the tests did not mark them as expected for
this target. On powerpc-*-vxworks*, the tests are skipped because
lp64 is not satisfied, so I'm naming powerpc*-*-vxworks* rather than
something more specific.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr106680-1.c: Error on vxworks too.
* gcc.target/powerpc/pr106680-2.c: Likewise.
* gcc.target/powerpc/pr106680-3.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr106680-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-3.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
index d624d43230a..aadaa614cfe 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
index a9ed73726ef..f0758e30335 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
@@ -9,6 +9,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
index b642d5c7a00..bca012e2cf6 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
[gcc(refs/users/aoliva/heads/testme)] add -mpowerpc-gpopt to options for sqrt insn on PowerPC
https://gcc.gnu.org/g:032f38d814d0ba4f8713e616f21b0475d4e61937
commit 032f38d814d0ba4f8713e616f21b0475d4e61937
Author: Eric Botcazou
Date: Sun Apr 21 17:23:56 2024 -0300
add -mpowerpc-gpopt to options for sqrt insn on PowerPC
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (add_options_for_sqrt_insn): For
PowerPC targets, add -mpowerpc-gpopt option.
Diff:
---
gcc/testsuite/gcc.dg/gimplefe-28.c| 1 +
gcc/testsuite/lib/target-supports.exp | 3 +++
2 files changed, 4 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/gimplefe-28.c
b/gcc/testsuite/gcc.dg/gimplefe-28.c
index d2f6b4c5c3d..5f478b32d52 100644
--- a/gcc/testsuite/gcc.dg/gimplefe-28.c
+++ b/gcc/testsuite/gcc.dg/gimplefe-28.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target sqrt_insn } } */
/* { dg-options "-fgimple -O2" } */
/* { dg-add-options sqrt_insn } */
+/* { dg-require-effective-target sqrt_insn } */
double __GIMPLE
f1 (double x)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..ec753b19e2f 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -9260,6 +9260,9 @@ proc add_options_for_sqrt_insn { flags } {
if { [istarget arm*-*-*] } {
return [add_options_for_arm_vfp "$flags"]
}
+if { [istarget powerpc*-*-*] } {
+ return "$flags -mpowerpc-gpopt"
+}
return $flags
}
[gcc(refs/users/aoliva/heads/testme)] enable sqrt insns for cdce3.c
https://gcc.gnu.org/g:048689c644c10a99d8618bd0479f727e87e74b90
commit 048689c644c10a99d8618bd0479f727e87e74b90
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:00 2024 -0300
enable sqrt insns for cdce3.c
The test expects shrink-wrapping of the fsqrt call, but that will only
occur when there is a usable sqrt insn.
Arrange for dejagnu to add the options that enable the sqrt insn, if
one is available, and to skip the test otherwise.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Add sqrt insn options.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..218c24d38f1 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-add-options sqrt_insn } */
+/* { dg-require-effective-target sqrt_insn } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
-/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
float sqrtf (float);
float foo (float x)
[gcc(refs/users/aoliva/heads/testme)] add sqrt options and test for sqrt support in ppc tests
https://gcc.gnu.org/g:4488f8d930768029f3ca3b18709a2652462bd7c5
commit 4488f8d930768029f3ca3b18709a2652462bd7c5
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:06 2024 -0300
add sqrt options and test for sqrt support in ppc tests
Some powerpc tests that require the fsqrt insn to be enabled
explicitly use the -mpowerpc-gpopt option. This fails if the fsqrt
opcode is not available on the target machine.
Switch to dg-add-options sqrt_insn for compile tests, that adds the
option for the feature (pending approval of another patch for the same
PR), and to dg-require-effective-target sqrt_insn for execution tests.
for gcc/testsuite/ChangeLog
PR testsuite/99371
* gcc.target/powerpc/pr46728-10.c: Drop explicit
-mpowerpc-gpopt in favor of dg-require-effective-target sqrt_insn.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
* gcc.target/powerpc/pr46728-15.c: Likewise.
* gcc.target/powerpc/recip-7.c: Likewise.
* gcc.target/powerpc/pr46728-1.c: Drop explicit
-mpowerpc-gpopt in favor of dg-add-options sqrt_insn.
* gcc.target/powerpc/pr46728-2.c: Likewise.
* gcc.target/powerpc/pr46728-3.c: Likewise.
* gcc.target/powerpc/pr46728-4.c: Likewise.
* gcc.target/powerpc/pr46728-5.c: Likewise.
* gcc.target/powerpc/pr46728-7.c: Likewise.
* gcc.target/powerpc/pr46728-8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr46728-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-15.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-2.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-4.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-5.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-7.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-8.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/recip-7.c| 3 ++-
13 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
index fc2cd7d7c9c..b561d8b6e42 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt -fno-ident" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -fno-ident"
} */
+/* { dg-add-options sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..cdde53b8de0 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..62b49b14793 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..3e55fa86e0b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..472b9d5b601 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { d
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:0e8ef1e608028e5812900b717406d1901d98d4cf
commit 0e8ef1e608028e5812900b717406d1901d98d4cf
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f97dcc12cac 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:8e6d1811a6aae7902225fb37a97214c3a2fed32b
commit 8e6d1811a6aae7902225fb37a97214c3a2fed32b
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:106f3cf414881d14a285a18919bfec14d2d1ca23
commit 106f3cf414881d14a285a18919bfec14d2d1ca23
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:ad51db74dc7e057ee1d81ed09d380f65c18d1f0f
commit ad51db74dc7e057ee1d81ed09d380f65c18d1f0f
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ec753b19e2f..b55bd65bdbb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11628,7 +11628,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11658,14 +11658,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11684,7 +11684,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11697,7 +11697,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11710,7 +11710,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11734,7 +11734,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:2d28d2a79906d56cb121c5e08af68c81d7a5dea7
commit 2d28d2a79906d56cb121c5e08af68c81d7a5dea7
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:fe3c0a30e72c978dcd9a70d131b2e9cb9f90e8e0
commit fe3c0a30e72c978dcd9a70d131b2e9cb9f90e8e0
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:0197e8f80932063526f0bd7437c80c9ca420cf38
commit 0197e8f80932063526f0bd7437c80c9ca420cf38
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:89e5150772d91d129fd4a8ca6ebda361e546
commit 89e5150772d91d129fd4a8ca6ebda361e546
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the expectations to be met.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..c667a28ebfe 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fno-reg-struct-return" } */
typedef struct { double a[2]; } A;
A
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:b6144ccafe3acc445ee5b2a23000a37824923d3b
commit b6144ccafe3acc445ee5b2a23000a37824923d3b
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final { scan-assemb
[gcc r14-10061] RISC-V: Add xfail test case for highpart register overlap of vx/vf widen
https://gcc.gnu.org/g:338640fbee2977485efb6ff0f1d3c7c8220074ad
commit r14-10061-g338640fbee2977485efb6ff0f1d3c7c8220074ad
Author: Pan Li
Date: Sun Apr 21 12:34:19 2024 +0800
RISC-V: Add xfail test case for highpart register overlap of vx/vf widen
We reverted below patch for register group overlap, add the related
insn test and mark it as xfail. And we will remove the xfail
after we support the register overlap in GCC-15.
a23415d7572 RISC-V: Support highpart register overlap for widen vx/vf
instructions
The below test suites are passed.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-22.c: New test.
* gcc.target/riscv/rvv/base/pr112431-23.c: New test.
* gcc.target/riscv/rvv/base/pr112431-24.c: New test.
* gcc.target/riscv/rvv/base/pr112431-25.c: New test.
* gcc.target/riscv/rvv/base/pr112431-26.c: New test.
* gcc.target/riscv/rvv/base/pr112431-27.c: New test.
Signed-off-by: Pan Li
Diff:
---
.../gcc.target/riscv/rvv/base/pr112431-22.c| 188 +
.../gcc.target/riscv/rvv/base/pr112431-23.c| 119 +
.../gcc.target/riscv/rvv/base/pr112431-24.c| 86 ++
.../gcc.target/riscv/rvv/base/pr112431-25.c| 104
.../gcc.target/riscv/rvv/base/pr112431-26.c| 68
.../gcc.target/riscv/rvv/base/pr112431-27.c| 51 ++
6 files changed, 616 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c
new file mode 100644
index 000..ac56703c75c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c
@@ -0,0 +1,188 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
+ size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,
+ size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,
+ size_t sum15)
+{
+ return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9
++ sum10 + sum11 + sum12 + sum13 + sum14 + sum15;
+}
+
+size_t
+foo (char const *buf, size_t len)
+{
+ size_t sum = 0;
+ size_t vl = __riscv_vsetvlmax_e8m8 ();
+ size_t step = vl * 4;
+ const char *it = buf, *end = buf + len;
+ for (; it + step <= end;)
+{
+ vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+
+ asm volatile("nop" ::: "memory");
+ vint16m2_t vw0 = __riscv_vwadd_vx_i16m2 (v0, 33, vl);
+ vint16m2_t vw1 = __riscv_vwadd_vx_i16m2 (v1, 33, vl);
+ vint16m2_t vw2 = __riscv_vwadd_vx_i16m2 (v2, 33, vl);
+ vint16m2_t vw3 = __riscv_vwadd_vx_i16m2 (v3, 33, vl);
+ vint16m2_t vw4 = __riscv_vwadd_vx_i16m2 (v4, 33, vl);
+ vint16m2_t vw5 = __riscv_vwadd_vx_i16m2 (v5, 33, vl);
+ vint16m2_t vw6 = __riscv_vwadd_vx_i16m2 (v6, 33, vl);
+ vint16m2_t vw7 = __riscv_vwadd_vx_i16m2 (v7, 33, vl);
+ vint16m2_t vw8 = __riscv_vwadd_vx_i16m2 (v8, 33, vl);
+ vint16m2_t vw9 = __riscv_vwadd_vx_i16m2 (v9, 33, vl);
+ vint16m2_t vw10 = __riscv_vwadd_vx_i16m2 (v10, 33, vl);
+ vint16m2_t vw11 = __riscv_vwadd_vx_i16m2 (v11, 33, vl);
+ vint16m2_t vw12 = __riscv_vwadd_vx_i16m2 (v12, 33, vl);
+ vint16m2_t vw13 = __riscv_vwadd_vx_i16m2 (v13, 33, vl);
+ vint16m2_t vw14 = __riscv_vwadd_vx_i16m2 (v14, 33, vl);
+ vint16m2_t vw15 = __riscv_vwadd_vx_i16m2 (v15, 33, vl);
+
+ asm volatile("nop" ::: "memory");
+ size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);
+ size_t sum1 = __ri
[gcc r14-10062] Revert "RISC-V: Support widening register overlap for vf4/vf8"
https://gcc.gnu.org/g:ec78916bb37bec0cd3ede5c6263387345ce16f94
commit r14-10062-gec78916bb37bec0cd3ede5c6263387345ce16f94
Author: Pan Li
Date: Mon Apr 22 09:26:04 2024 +0800
Revert "RISC-V: Support widening register overlap for vf4/vf8"
This reverts commit 303195e2a6b6f0e8f42e0578b61f9f37c6250beb.
Diff:
---
gcc/config/riscv/vector.md | 38 ++--
.../gcc.target/riscv/rvv/base/pr112431-16.c| 68 --
.../gcc.target/riscv/rvv/base/pr112431-17.c| 51
.../gcc.target/riscv/rvv/base/pr112431-18.c| 51
4 files changed, 18 insertions(+), 190 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f620f13682c..140b4638346 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3754,45 +3754,43 @@
;; Vector Quad-Widening Sign-extend and Zero-extend.
(define_insn "@pred__vf4"
- [(set (match_operand:VQEXTI 0 "register_operand" "=vr, vr,
vr, vr, ?&vr, ?&vr")
+ [(set (match_operand:VQEXTI 0 "register_operand" "=&vr,&vr")
(if_then_else:VQEXTI
(unspec:
- [(match_operand: 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
-(match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
-(match_operand 5 "const_int_operand" "i,i,
i,i,i,i")
-(match_operand 6 "const_int_operand" "i,i,
i,i,i,i")
-(match_operand 7 "const_int_operand" "i,i,
i,i,i,i")
+ [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1")
+(match_operand 4 "vector_length_operand" " rK, rK")
+(match_operand 5 "const_int_operand" "i,i")
+(match_operand 6 "const_int_operand" "i,i")
+(match_operand 7 "const_int_operand" "i,i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_extend:VQEXTI
- (match_operand: 3 "register_operand" " W43, W43,
W86, W86, vr, vr"))
- (match_operand:VQEXTI 2 "vector_merge_operand" " vu,0,
vu,0, vu,0")))]
+ (match_operand: 3 "register_operand" " vr, vr"))
+ (match_operand:VQEXTI 2 "vector_merge_operand" " vu,0")))]
"TARGET_VECTOR"
"vext.vf4\t%0,%3%p1"
[(set_attr "type" "vext")
- (set_attr "mode" "")
- (set_attr "group_overlap" "W43,W43,W86,W86,none,none")])
+ (set_attr "mode" "")])
;; Vector Oct-Widening Sign-extend and Zero-extend.
(define_insn "@pred__vf8"
- [(set (match_operand:VOEXTI 0 "register_operand" "=vr, vr,
?&vr, ?&vr")
+ [(set (match_operand:VOEXTI 0 "register_operand" "=&vr,&vr")
(if_then_else:VOEXTI
(unspec:
- [(match_operand: 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
-(match_operand 4 "vector_length_operand" " rK, rK,
rK, rK")
-(match_operand 5 "const_int_operand" "i,i,
i,i")
-(match_operand 6 "const_int_operand" "i,i,
i,i")
-(match_operand 7 "const_int_operand" "i,i,
i,i")
+ [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1")
+(match_operand 4 "vector_length_operand" " rK, rK")
+(match_operand 5 "const_int_operand" "i,i")
+(match_operand 6 "const_int_operand" "i,i")
+(match_operand 7 "const_int_operand" "i,i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_extend:VOEXTI
- (match_operand: 3 "register_operand" " W87, W87,
vr, vr"))
- (match_operand:VOEXTI 2 "vector_merge_operand" " vu,0,
vu,0")))]
+ (match_operand: 3 "register_operand" " vr, vr"))
+ (match_operand:VOEXTI 2 "vector_merge_operand" " vu,0")))]
"TARGET_VECTOR"
"vext.vf8\t%0,%3%p1"
[(set_attr "type" "vext")
- (set_attr "mode" "")
- (set_attr "group_overlap" "W87,W87,none,none")])
+ (set_attr "mode" "")])
;; Vector Widening Add/Subtract/Multiply.
(define_insn "@pred_dual_widen_"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
deleted file mode 100644
index 98f42458883..000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
-
-#include "riscv_vector.h"
-
-size_t __attribute__ ((noinline))
-sumation (size_t sum0, size_t sum1, size_t sum2,
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:347b4d5eb8a1418393f6e406d4d052d3c6b0790e
commit 347b4d5eb8a1418393f6e406d4d052d3c6b0790e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc/aoliva/heads/testme] (3 commits) add explicit ABI and align options to pr88233.c
The branch 'aoliva/heads/testme' was updated to point to: c3999e0292d... add explicit ABI and align options to pr88233.c It previously pointed to: b6144ccafe3... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- b6144cc... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 0197e8f... ppc: testsuite: vec-mul requires vsx runtime 89e5150... add explicit ABI and align options to pr88233.c Summary of changes (added commits): --- c3999e0... add explicit ABI and align options to pr88233.c d20a933... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 347b4d5... ppc: testsuite: vec-mul requires vsx runtime
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:d20a933141e6b8dd34fb578635ccbd49abcab15e
commit d20a933141e6b8dd34fb578635ccbd49abcab15e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final { scan-assemb
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:c3999e0292deb3c5f3c8ccc8ddccc21da4ef3644
commit c3999e0292deb3c5f3c8ccc8ddccc21da4ef3644
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc r13-8640] libfortran: Fix handling of formatted separators.
https://gcc.gnu.org/g:b55a35bcc80a7402576556c2f9d161229fb220ef
commit r13-8640-gb55a35bcc80a7402576556c2f9d161229fb220ef
Author: Jerry DeLisle
Date: Sun Apr 21 20:50:26 2024 -0700
libfortran: Fix handling of formatted separators.
Backport from mainline.
PR libfortran/114304
PR libfortran/105473
libgfortran/ChangeLog:
* io/list_read.c (eat_separator): Add logic to handle spaces
preceding a comma or semicolon such that that a 'null' read
occurs without error at the end of comma or semicolon
terminated input lines. Add check and error message for ';'.
Accept tab as alternative to space.
(list_formatted_read_scalar): Treat comma as a decimal point
when specified by the decimal mode on the first item.
gcc/testsuite/ChangeLog:
* gfortran.dg/pr105473.f90: Modify for revised checks.
* gfortran.dg/pr114304-2.f90: New test.
* gfortran.dg/pr114304.f90: New test.
Diff:
---
gcc/testsuite/gfortran.dg/pr105473.f90 | 4 +-
gcc/testsuite/gfortran.dg/pr114304-2.f90 | 82 ++
gcc/testsuite/gfortran.dg/pr114304.f90 | 114 +++
libgfortran/io/list_read.c | 41 +--
4 files changed, 234 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/gfortran.dg/pr105473.f90
b/gcc/testsuite/gfortran.dg/pr105473.f90
index 2679f6bb447..863a312c794 100644
--- a/gcc/testsuite/gfortran.dg/pr105473.f90
+++ b/gcc/testsuite/gfortran.dg/pr105473.f90
@@ -9,11 +9,11 @@
n = 999; m = 777; r=1.2345
z = cmplx(0.0,0.0)
-! Check that semi-colon is allowed as separator with decimal=point.
+! Check that semi-colon is not allowed as separator with decimal=point.
ios=0
testinput = '1;17;3.14159'
read(testinput,*,decimal='point',iostat=ios) n, m, r
- if (ios /= 0) stop 1
+ if (ios /= 5010) stop 1
! Check that semi-colon allowed as a separator with decimal=point.
ios=0
diff --git a/gcc/testsuite/gfortran.dg/pr114304-2.f90
b/gcc/testsuite/gfortran.dg/pr114304-2.f90
new file mode 100644
index 000..5ef5874f528
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr114304-2.f90
@@ -0,0 +1,82 @@
+! { dg-do run }
+!
+! PR fortran/114304
+!
+! Ensure that '\t' (tab) is supported as separator in list-directed input
+! While not really standard conform, this is widely used in user input and
+! widely supported.
+!
+
+use iso_c_binding
+implicit none
+character(len=*,kind=c_char), parameter :: tab = C_HORIZONTAL_TAB
+
+! Accept '' as variant to ' ' as separator
+! Check that and are handled
+
+character(len=*,kind=c_char), parameter :: nml_str &
+ = '&inparm'//C_CARRIAGE_RETURN // C_NEW_LINE // &
+ 'first'//tab//'='//tab//' .true.'// C_NEW_LINE // &
+ ' , other'//tab//' ='//tab//'3'//tab//', 2'//tab//'/'
+
+! Check that is handled,
+
+! Note: For new line, Unix uses \n, Windows \r\n but old Apple systems used
'\r'
+!
+! Gfortran does not seem to support all \r, but the following is supported
+! since ages, ! which seems to be a gfortran extension as ifort and flang
don't like it.
+
+character(len=*,kind=c_char), parameter :: nml_str2 &
+ = '&inparm'//C_CARRIAGE_RETURN // C_NEW_LINE // &
+ 'first'//C_NEW_LINE//'='//tab//' .true.'// C_CARRIAGE_RETURN // &
+ ' , other'//tab//' ='//tab//'3'//tab//', 2'//tab//'/'
+
+character(len=*,kind=c_char), parameter :: str &
+ = tab//'1'//tab//'2,'//tab//'3'//tab//',4'//tab//','//tab//'5'//tab//'/'
+character(len=*,kind=c_char), parameter :: str2 &
+ = tab//'1'//tab//'2;'//tab//'3'//tab//';4'//tab//';'//tab//'5'//tab//'/'
+logical :: first
+integer :: other(4)
+integer :: ints(6)
+namelist /inparm/ first , other
+
+other = 1
+
+open(99, file="test.inp")
+write(99, '(a)') nml_str
+rewind(99)
+read(99,nml=inparm)
+close(99, status="delete")
+
+if (.not.first .or. any (other /= [3,2,1,1])) stop 1
+
+other = 9
+
+open(99, file="test.inp")
+write(99, '(a)') nml_str2
+rewind(99)
+read(99,nml=inparm)
+close(99, status="delete")
+
+if (.not.first .or. any (other /= [3,2,9,9])) stop 2
+
+ints = 66
+
+open(99, file="test.inp", decimal='point')
+write(99, '(a)') str
+rewind(99)
+read(99,*) ints
+close(99, status="delete")
+
+if (any (ints /= [1,2,3,4,5,66])) stop 3
+
+ints = 77
+
+open(99, file="test.inp", decimal='comma')
+write(99, '(a)') str2
+rewind(99)
+read(99,*) ints
+close(99, status="delete")
+
+if (any (ints /= [1,2,3,4,5,77])) stop 4
+end
diff --git a/gcc/testsuite/gfortran.dg/pr114304.f90
b/gcc/testsuite/gfortran.dg/pr114304.f90
new file mode 100644
index 000..2f913f1ab34
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr114304.f90
@@ -0,0 +1,114 @@
+! { dg-do run }
+!
+! PR fortran/114304
+!
+! See also PR fortran/105473
+!
+! Testing: Does list-directed reading an integer/real allow some non-integer
input?
+!
+! Note: GCC result comments before fix of this PR.
+
+ implicit none
+ call t(.
[gcc/aoliva/heads/testme] (10 commits) [testsuite] require sqrt_insn effective target where needed
The branch 'aoliva/heads/testme' was updated to point to: 650181136ad... [testsuite] require sqrt_insn effective target where needed It previously pointed to: c3999e0292d... add explicit ABI and align options to pr88233.c Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- c3999e0... add explicit ABI and align options to pr88233.c d20a933... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 347b4d5... ppc: testsuite: vec-mul requires vsx runtime fe3c0a3... ppc: testsuite: pr79004 needs -mlong-double-128 2d28d2a... Request check for hw support in ppc run tests with -maltive ad51db7... decay vect tests from run to link for pr95401 106f3cf... adjust vectorization expectations for ppc costmodel 76b 8e6d181... disable ldist for test, to restore vectorizing-candidate lo 0e8ef1e... xfail fetestexcept test - ppc always uses fcmpu 4488f8d... add sqrt options and test for sqrt support in ppc tests 048689c... enable sqrt insns for cdce3.c 032f38d... add -mpowerpc-gpopt to options for sqrt insn on PowerPC Summary of changes (added commits): --- 6501811... [testsuite] require sqrt_insn effective target where needed 387ce53... add explicit ABI and align options to pr88233.c 40cc97a... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra bd7a059... ppc: testsuite: vec-mul requires vsx runtime 762f75a... ppc: testsuite: pr79004 needs -mlong-double-128 de156d0... Request check for hw support in ppc run tests with -maltive 4aed989... decay vect tests from run to link for pr95401 9b0c52b... adjust vectorization expectations for ppc costmodel 76b 7ef3c86... disable ldist for test, to restore vectorizing-candidate lo f605eec... xfail fetestexcept test - ppc always uses fcmpu
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:f605eecb06d40c99be2d48169c5fafda2df6babb
commit f605eecb06d40c99be2d48169c5fafda2df6babb
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f97dcc12cac 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:7ef3c86bc8ac48a834a787aad1809e623def6b64
commit 7ef3c86bc8ac48a834a787aad1809e623def6b64
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:9b0c52b69c85acbceccc5676509cfc0fbb41dd52
commit 9b0c52b69c85acbceccc5676509cfc0fbb41dd52
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:4aed9893ba8413ee38770d909995f3925659b670
commit 4aed9893ba8413ee38770d909995f3925659b670
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..df5a1457cd1 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:de156d08943e343720819a9920ba7e4f67bbd8e4
commit de156d08943e343720819a9920ba7e4f67bbd8e4
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:762f75a75a192bdc4f7b056a978f9ae37b12bcf7
commit 762f75a75a192bdc4f7b056a978f9ae37b12bcf7
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:bd7a059057714d60f0b7a3db37152ae898e4a293
commit bd7a059057714d60f0b7a3db37152ae898e4a293
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:40cc97a1048c76e6f94e7b1b4a39089686ec6a84
commit 40cc97a1048c76e6f94e7b1b4a39089686ec6a84
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final { scan-assemb
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:387ce53fd3fdaeefc7dc9d603df0d66495580fbf
commit 387ce53fd3fdaeefc7dc9d603df0d66495580fbf
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:650181136ad3e9ec7be716f69b4bde29c883cd71
commit 650181136ad3e9ec7be716f69b4bde29c883cd71
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..7e9bb638106 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..5bfa2592567 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..b66d0209a5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..71a1a70c4e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc r14-10063] RISC-V: Add xfail test case for widening register overlap of vf4/vf8
https://gcc.gnu.org/g:c4fdbdac1226787b4d33046f0be189a24dac468e
commit r14-10063-gc4fdbdac1226787b4d33046f0be189a24dac468e
Author: Pan Li
Date: Mon Apr 22 10:11:25 2024 +0800
RISC-V: Add xfail test case for widening register overlap of vf4/vf8
We reverted below patch for register group overlap, add the related
insn test and mark it as xfail. And we will remove the xfail
after we support the register overlap in GCC-15.
303195e2a6b RISC-V: Support widening register overlap for vf4/vf8
The below test suites are passed.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-16.c: New test.
* gcc.target/riscv/rvv/base/pr112431-17.c: New test.
* gcc.target/riscv/rvv/base/pr112431-18.c: New test.
Signed-off-by: Pan Li
Diff:
---
.../gcc.target/riscv/rvv/base/pr112431-16.c| 68 ++
.../gcc.target/riscv/rvv/base/pr112431-17.c| 51
.../gcc.target/riscv/rvv/base/pr112431-18.c| 51
3 files changed, 170 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
new file mode 100644
index 000..42d11611d98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
+ size_t sum5, size_t sum6, size_t sum7)
+{
+ return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7;
+}
+
+size_t
+foo (char const *buf, size_t len)
+{
+ size_t sum = 0;
+ size_t vl = __riscv_vsetvlmax_e8m8 ();
+ size_t step = vl * 4;
+ const char *it = buf, *end = buf + len;
+ for (; it + step <= end;)
+{
+ vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+ vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl);
+ it += vl;
+
+ asm volatile("nop" ::: "memory");
+ vint32m4_t vw0 = __riscv_vsext_vf4_i32m4 (v0, vl);
+ vint32m4_t vw1 = __riscv_vsext_vf4_i32m4 (v1, vl);
+ vint32m4_t vw2 = __riscv_vsext_vf4_i32m4 (v2, vl);
+ vint32m4_t vw3 = __riscv_vsext_vf4_i32m4 (v3, vl);
+ vint32m4_t vw4 = __riscv_vsext_vf4_i32m4 (v4, vl);
+ vint32m4_t vw5 = __riscv_vsext_vf4_i32m4 (v5, vl);
+ vint32m4_t vw6 = __riscv_vsext_vf4_i32m4 (v6, vl);
+ vint32m4_t vw7 = __riscv_vsext_vf4_i32m4 (v7, vl);
+
+ asm volatile("nop" ::: "memory");
+ size_t sum0 = __riscv_vmv_x_s_i32m4_i32 (vw0);
+ size_t sum1 = __riscv_vmv_x_s_i32m4_i32 (vw1);
+ size_t sum2 = __riscv_vmv_x_s_i32m4_i32 (vw2);
+ size_t sum3 = __riscv_vmv_x_s_i32m4_i32 (vw3);
+ size_t sum4 = __riscv_vmv_x_s_i32m4_i32 (vw4);
+ size_t sum5 = __riscv_vmv_x_s_i32m4_i32 (vw5);
+ size_t sum6 = __riscv_vmv_x_s_i32m4_i32 (vw6);
+ size_t sum7 = __riscv_vmv_x_s_i32m4_i32 (vw7);
+
+ sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7);
+}
+ return sum;
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
new file mode 100644
index 000..9ecc62e234b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3)
+{
+ return sum0 + sum1 + sum2 + sum3;
+}
+
+size_t
+foo (char const *buf, size_t len)
+{
+ size_t sum = 0;
+ size_t vl = __riscv_vsetvlmax_e8m8 ();
+ size_t step = vl * 4;
+ const char *it = buf, *end = buf + len;
+ for (; it + step <= end;)
+{
+ vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl);
+ it += vl;
+ vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl);
+ it += vl;
+ vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl);
+ it += vl;
+ vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl);
+ it +=
[gcc r14-10064] Revert "RISC-V: Support highest-number regno overlap for widen ternary"
https://gcc.gnu.org/g:cc46b6d4f3b4edc832a319ebf5053131dada3c8c commit r14-10064-gcc46b6d4f3b4edc832a319ebf5053131dada3c8c Author: Pan Li Date: Mon Apr 22 14:10:02 2024 +0800 Revert "RISC-V: Support highest-number regno overlap for widen ternary" This reverts commit 27fde325d64447a3a0d5d550c5976e5f3fb6dc16. Diff: --- gcc/config/riscv/vector.md | 115 ++--- .../gcc.target/riscv/rvv/base/pr112431-37.c| 103 -- .../gcc.target/riscv/rvv/base/pr112431-38.c| 82 --- 3 files changed, 55 insertions(+), 245 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 140b4638346..aef8cad20a0 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -5930,30 +5930,29 @@ (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plus_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand""=&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1") -(match_operand 5 "vector_length_operand"" rK, rK, rK, rK, rK, rK, rK") -(match_operand 6 "const_int_operand"" i, i, i, i, i, i,i") -(match_operand 7 "const_int_operand"" i, i, i, i, i, i,i") -(match_operand 8 "const_int_operand"" i, i, i, i, i, i,i") + [(match_operand: 1 "vector_mask_operand" "vmWc1") +(match_operand 5 "vector_length_operand"" rK") +(match_operand 6 "const_int_operand""i") +(match_operand 7 "const_int_operand""i") +(match_operand 8 "const_int_operand""i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (any_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ"))) + (match_operand: 3 "register_operand" "r"))) (any_extend:VWEXTI - (match_operand: 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0,0")) + (match_operand: 4 "register_operand" " vr"))) + (match_operand:VWEXTI 2 "register_operand" "0")) (match_dup 2)))] "TARGET_VECTOR" - "vwmacc.vx\t%0,%z3,%4%p1" + "vwmacc.vx\t%0,%3,%4%p1" [(set_attr "type" "viwmuladd") - (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")]) + (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plussu" [(set (match_operand:VWEXTI 0 "register_operand""=&vr") @@ -5980,56 +5979,54 @@ (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plussu_scalar" - [(set (match_operand:VWEXTI 0 "register_operand""=vd, vr, vd, vr, vd, vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand""=&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1") -(match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK") -(match_operand 6 "const_int_operand" " i, i, i, i, i, i,i") -(match_operand 7 "const_int_operand" " i, i, i, i, i, i,i") -(match_operand 8 "const_int_operand" " i, i, i, i, i, i,i") + [(match_operand: 1 "vector_mask_operand" "vmWc1") +(match_operand 5 "vector_length_operand"" rK") +(match_operand 6 "const_int_operand""i") +(match_operand 7 "const_int_operand""i") +(match_operand 8 "const_int_operand""i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (sign_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "reg_or_0_operand"" rJ, rJ, rJ, rJ, rJ, rJ, rJ"))) + (match_operand: 3 "register_operand" "r"))) (zero_extend:VWEXTI - (match_operand: 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))) - (match_operand:VWEXTI 2 "register_operand"" 0, 0, 0, 0, 0, 0,0")) + (match_operand: 4 "
[gcc/aoliva/heads/testme] (10 commits) [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra
The branch 'aoliva/heads/testme' was updated to point to: edf330eeb9d... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra It previously pointed to: 650181136ad... [testsuite] require sqrt_insn effective target where needed Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 6501811... [testsuite] require sqrt_insn effective target where needed 387ce53... add explicit ABI and align options to pr88233.c 40cc97a... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra bd7a059... ppc: testsuite: vec-mul requires vsx runtime 762f75a... ppc: testsuite: pr79004 needs -mlong-double-128 de156d0... Request check for hw support in ppc run tests with -maltive 4aed989... decay vect tests from run to link for pr95401 9b0c52b... adjust vectorization expectations for ppc costmodel 76b 7ef3c86... disable ldist for test, to restore vectorizing-candidate lo f605eec... xfail fetestexcept test - ppc always uses fcmpu Summary of changes (added commits): --- edf330e... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 960142e... decay vect tests from run to link for pr95401 1dd110c... xfail fetestexcept test - ppc always uses fcmpu cef8842... [testsuite] require sqrt_insn effective target where needed c5fbace... add explicit ABI and align options to pr88233.c 25b2dc8... ppc: testsuite: vec-mul requires vsx runtime 9c266e6... ppc: testsuite: pr79004 needs -mlong-double-128 b610d91... Request check for hw support in ppc run tests with -maltive 06cec5e... adjust vectorization expectations for ppc costmodel 76b 5b0e0d4... disable ldist for test, to restore vectorizing-candidate lo
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:5b0e0d473bcd6a06a4dc4876890477a9d30582d8
commit 5b0e0d473bcd6a06a4dc4876890477a9d30582d8
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:06cec5e7261a78413d7ccfeea4c8e85b224d370f
commit 06cec5e7261a78413d7ccfeea4c8e85b224d370f
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:b610d91071d1c8887481b7f5b3ca57342911cdea
commit b610d91071d1c8887481b7f5b3ca57342911cdea
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:25b2dc8c3befb8a19584f5052db75753fcd78351
commit 25b2dc8c3befb8a19584f5052db75753fcd78351
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:9c266e6f78ee2bd8fad3b1310996ba5012a16735
commit 9c266e6f78ee2bd8fad3b1310996ba5012a16735
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:c5fbacee0313fb1b760a870964877f343bf4b90e
commit c5fbacee0313fb1b760a870964877f343bf4b90e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:cef88428efe311383bc65c47e4f6c96a8b16452a
commit cef88428efe311383bc65c47e4f6c96a8b16452a
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..7e9bb638106 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..5bfa2592567 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..b66d0209a5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..71a1a70c4e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:1dd110cf0d45a2716102a53cc42f809e29d909ae
commit 1dd110cf0d45a2716102a53cc42f809e29d909ae
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f188faa3ccf 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
+/* The ppc xfail is because of PR target/58684. */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:960142effc3218ccb3463464d3dbe3c0ce3d5280
commit 960142effc3218ccb3463464d3dbe3c0ce3d5280
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..54a55585371 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} else {
return 0
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:edf330eeb9d4832b1972516bcf6b54cd897e5fa9
commit edf330eeb9d4832b1972516bcf6b54cd897e5fa9
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..e69d9253e2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,12 +13,11 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..9ff197a7049 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,13 +12,12 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..cc3c803b49c 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assemble
[gcc r14-10065] RISC-V: Add xfail test case for highest-number regno ternary overlap
https://gcc.gnu.org/g:c7506847c020ad34eff248ab715eae238b9d1ed3
commit r14-10065-gc7506847c020ad34eff248ab715eae238b9d1ed3
Author: Pan Li
Date: Mon Apr 22 14:32:25 2024 +0800
RISC-V: Add xfail test case for highest-number regno ternary overlap
We reverted below patch for register group overlap, add the related
insn test and mark it as xfail. And we will remove the xfail
after we support the register overlap in GCC-15.
27fde325d64 RISC-V: Support highest-number regno overlap for widen ternary
The below test suites are passed.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-37.c: New test.
* gcc.target/riscv/rvv/base/pr112431-38.c: New test.
Signed-off-by: Pan Li
Diff:
---
.../gcc.target/riscv/rvv/base/pr112431-37.c| 103 +
.../gcc.target/riscv/rvv/base/pr112431-38.c| 82
2 files changed, 185 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
new file mode 100644
index 000..66e81ea905a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
@@ -0,0 +1,103 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out)
+{
+ vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4);
+ vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1);
+ vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16);
+ vint16m2_t result = __riscv_vwmacc_vx_i16m2 (accum, 16, high_eew8, 4);
+ __riscv_vse16_v_i16m2 (out, result, 4);
+}
+
+void
+foo2 (void *in, void *out)
+{
+ vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4);
+ vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1);
+ vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16);
+ vint16m4_t result = __riscv_vwmacc_vx_i16m4 (accum, 16, high_eew8, 4);
+ __riscv_vse16_v_i16m4 (out, result, 4);
+}
+
+void
+foo3 (void *in, void *out)
+{
+ vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4);
+ vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1);
+ vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16);
+ vint16m8_t result = __riscv_vwmacc_vx_i16m8 (accum, 16, high_eew8, 4);
+ __riscv_vse16_v_i16m8 (out, result, 4);
+}
+
+void
+foo4 (void *in, void *out)
+{
+ vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4);
+ vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1);
+ vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16);
+ vint16m2_t result = __riscv_vwmaccus_vx_i16m2 (accum, 16, high_eew8, 4);
+ __riscv_vse16_v_i16m2 (out, result, 4);
+}
+
+void
+foo5 (void *in, void *out)
+{
+ vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4);
+ vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1);
+ vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16);
+ vint16m4_t result = __riscv_vwmaccus_vx_i16m4 (accum, 16, high_eew8, 4);
+ __riscv_vse16_v_i16m4 (out, result, 4);
+}
+
+void
+foo6 (void *in, void *out)
+{
+ vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4);
+ vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1);
+ vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16);
+ vint16m8_t result = __riscv_vwmaccus_vx_i16m8 (accum, 16, high_eew8, 4);
+ __riscv_vse16_v_i16m8 (out, result, 4);
+}
+
+void
+foo7 (void *in, void *out)
+{
+ vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4);
+ vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1);
+ vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16);
+ vuint8m1_t high_ueew8 = __riscv_vreinterpret_v_i8m1_u8m1 (high_eew8);
+ vint16m2_t result = __riscv_vwmaccsu_vx_i16m2 (accum, 16, high_ueew8, 4);
+ __riscv_vse16_v_i16m2 (out, result, 4);
+}
+
+void
+foo8 (void *in, void *out)
+{
+ vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4);
+ vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1);
+ vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16);
+ vuint8m2_t high_ueew8 = __riscv_vreinterpret_v_i8m2_u8m2 (high_eew8);
+ vint16m4_t result = __riscv_vwmaccsu_vx_i16m4 (accum, 16, high_ueew8, 4);
+ __riscv_vse16_v_i16m4 (out, result, 4);
+}
+
+void
+foo9 (void *in, void *out)
+{
+ vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4);
+ vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1);
+ vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16);
+ vuint8m4_t high_ueew8 = __riscv_vreinterpret_v_i8m4_u8m4 (high_eew8);
+ vint16m8_t result = __riscv_vwmaccsu_vx_i16m8 (accum, 16, high_ueew8, 4);
+ __riscv_vse16_v_i16m8 (out, result, 4);
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
+/* { dg-fina
