RISC-V support
I'm looking at the RISC-V elfutils support to help the Debian folks. I see four testcases failing, same as Kurt Roeckx reported about 6 weeks ago. I'm testing on a Fedora Core 29 system. I found a trivial bug in backends/riscv_corenote.c. It has ".offset = 1" but this is a byte offset not a register offset, so it needs to be ".offset = 8" instead. I also added in the missing PC support. These two fixes then require a fix for tests/run-readelf-mixed-corenote.sh because the eu-readelf output is now more correct than before. There is also a missing backends/riscv_retval.c file. I have an initial implementation for this, but I haven't implemented the support for structures with one or two float fields yet, as this gets a little complicated. With these patches, I now see two failures. One is a glibc bug that Andreas Schwab already fixed, where _start fails to terminate the unwind chain. I just don't have this patch on my system. The other failure is the same glibc bug in __thread_start, which apparently isn't fixed yet, and needs the same fix Andreas already added to _start. So with the appropriate glibc fixes, the elfutils testsuite should run without error on a riscv64/lp64d system using the patches I have. There is a problem here though. The riscv support was written to try to handle both 32-bit and 64-bit targets with a single elfutils backend. But I have 6 ABIs I need to (theoretically) handle in riscv_retval.c. The return_value_location function doesn't take any ebl or elf pointer, so I can't handle it there. I can handle it in riscv_init.c by checking ebl and elf pointers there, and calling an appropriate function, but I'm not sure if that is OK. Currently, none of the *_init.c files are using the elf pointer argument. I noticed another problem which is that riscv_corenote.c is only correct for riscv64, because it assumes that registers are 64-bits. But I see that sparc has a solution for that, so I will have to take a closer look at that and see if I can make it work for riscv. I unfortunately can't test the 32-bit riscv support. We don't have working upstream support for 32-bit linux yet. I can only test the 64-bit LP64D riscv support. I haven't contributed to elfutils before. So I'm looking for advice on how to proceed. I can send out my work in progress patches if that is useful. I probably should try to chop them up a bit first. I think I have 3 parts at the moment. One part should be OK, and one part needs more work to be complete (but maybe incomplete is OK?), and one part I haven't written yet. Jim
[PATCH] RISC-V: Improve riscv64 core file support.
This fixes two problems. The offset for x1 is changed from 1 to 8 because this
is a byte offset not a register skip count. Support for reading the PC value
is added. This requires changing the testsuite to match the new readelf
output for coredumps.
Signed-off-by: Jim Wilson
---
backends/ChangeLog | 5 +
backends/riscv_corenote.c | 9 +++-
tests/ChangeLog | 4
tests/run-readelf-mixed-corenote.sh | 34 ++---
4 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/backends/ChangeLog b/backends/ChangeLog
index e2a02812..c8234072 100644
--- a/backends/ChangeLog
+++ b/backends/ChangeLog
@@ -1,3 +1,8 @@
+2018-12-27 Jim Wilson
+
+ * riscv_corenote.c (prstatus_regs): Change offset from 1 to 8.
+ (PRSTATUS_REGSET_ITEMS): New.
+
2018-11-06 Mark Wielaard
* x86_64_symbol.c (x86_64_section_type_name): New function.
diff --git a/backends/riscv_corenote.c b/backends/riscv_corenote.c
index 37cce7e3..afb84bee 100644
--- a/backends/riscv_corenote.c
+++ b/backends/riscv_corenote.c
@@ -53,8 +53,15 @@
static const Ebl_Register_Location prstatus_regs[] =
{
-{ .offset = 1, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
+{ .offset = 8, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
};
#define PRSTATUS_REGS_SIZE (32 * 8)
+#define PRSTATUS_REGSET_ITEMS \
+ {\
+.name = "pc", .type = ELF_T_ADDR, .format = 'x', \
+.offset = offsetof (struct EBLHOOK(prstatus), pr_reg[0]), \
+.group = "register", .pc_register = true \
+ }
+
#include "linux-core-note.c"
diff --git a/tests/ChangeLog b/tests/ChangeLog
index 1382e40a..71b24e09 100644
--- a/tests/ChangeLog
+++ b/tests/ChangeLog
@@ -1,3 +1,7 @@
+2018-12-27 Jim Wilson
+
+ * run-readelf-mixed-corenote.sh: Update with new riscv64 output.
+
2018-12-02 Mark Wielaard
* testfile_gnu_props.32le.o.bz2: New testfile.
diff --git a/tests/run-readelf-mixed-corenote.sh
b/tests/run-readelf-mixed-corenote.sh
index 07cfc39c..c960f1d6 100755
--- a/tests/run-readelf-mixed-corenote.sh
+++ b/tests/run-readelf-mixed-corenote.sh
@@ -660,23 +660,23 @@ Note segment of 1408 bytes at offset 0x388:
sighold: <>
pid: 6801, ppid: 1155, pgrp: 6801, sid: 1155
utime: 0.00, stime: 0.11, cutime: 0.00, cstime: 0.00
-fpvalid: 0
-ra:0x9a000104 sp:0x4000251c
-gp:0x28003fff9812 tp:0xd128
-t0: 5764607523571106577 t1: -432345563690696255
-t2: -5764607522497362661 s0: 5764607523034235171
-s1: -6629298650415654894 a0: 72057594037928196
-a1: -6341068275337658368 a2: -5188146769657096173
-a3:1073715219 a4: 8646911284551352320
-a5: 8646911285625067538 a6: 1729382256911463510
-a7: 536876397 s2: -1152921504606846976
-s3: 1152921505322686797 s4: 536871337
-s5: -3458764513820540928 s6: -9223372036138925403
-s7: 715843991 s8: -2594073385365405696
-s9: 4611686019143218592 s10:715850259
-s11:715850393 t3: -432345564227567616
-t4:144115188075856379 t5:216172782113783808
-t6: 1152921504606846976
+pc: 0x0001049a, fpvalid: 0
+ra:0x00251c9a sp:0x003fff981240
+gp:0x00012828 tp:0x002311d0
+t0: 137439068496 t1: 137439288314
+t2: 74672 s0: 274871095888
+s1: 66724 a0: 1
+a1: 274871096232 a2: 274871096248
+a3: 0 a4: 274871095928
+a5: 305419896 a6: 137440357656
+a7: 0 s2: 183254994416
+s3: 137439062288 s4: 0
+s5: 183257703888 s6: 183256061824
+s7: 0 s8: 183252656348
+s9: 183257666368 s10: 183257700608
+s11:0 t3:130042
+t4: 2 t5: 3
+t6: 15632
CORE 136 PRPSINFO
state: 0, sname: R, zomb: 0, nice: 0, flag: 0x00400600
uid: 0, gid: 0, pid: 6801, ppid: 1155, pgrp: 6801, sid: 1155
--
2.19.2
[PATCH] RISC-V: Add initial return value location support.
Started with the aarch64 support and modified it for RISC-V. The flattened
structure support hasn't been written yet, but the rest of it should be
correct for the LP64D ABI. We have potentially 6 different ABIs to support,
so this requires checking elf header flags in riscv_init when setting the hook.
Signed-off-by: Jim Wilson
---
backends/ChangeLog | 8 ++
backends/Makefile.am| 2 +-
backends/riscv_init.c | 10 +-
backends/riscv_retval.c | 251
4 files changed, 269 insertions(+), 2 deletions(-)
create mode 100644 backends/riscv_retval.c
diff --git a/backends/ChangeLog b/backends/ChangeLog
index c8234072..637aa8c2 100644
--- a/backends/ChangeLog
+++ b/backends/ChangeLog
@@ -1,5 +1,13 @@
2018-12-27 Jim Wilson
+ * Makefile.am (riscv_SRCS): Add riscv_retval.c.
+ * riscv_init.c: Include libelfP.h.
+ (riscv_return_value_location_lp64d): Declare.
+ (riscv_init): Delete unused attribute from elf parameter. Register
+ riscv_return_value_location_lp64d hook if 64-bit ELF and 64-bit FP
+ registers.
+ * riscv_retval.c: New file.
+
* riscv_corenote.c (prstatus_regs): Change offset from 1 to 8.
(PRSTATUS_REGSET_ITEMS): New.
diff --git a/backends/Makefile.am b/backends/Makefile.am
index 9d340425..fedeb93a 100644
--- a/backends/Makefile.am
+++ b/backends/Makefile.am
@@ -132,7 +132,7 @@ libebl_bpf_pic_a_SOURCES = $(bpf_SRCS)
am_libebl_bpf_pic_a_OBJECTS = $(bpf_SRCS:.c=.os)
riscv_SRCS = riscv_init.c riscv_symbol.c riscv_cfi.c riscv_regs.c \
-riscv_initreg.c riscv_corenote.c
+riscv_initreg.c riscv_corenote.c riscv_retval.c
libebl_riscv_pic_a_SOURCES = $(riscv_SRCS)
am_libebl_riscv_pic_a_OBJECTS = $(riscv_SRCS:.c=.os)
diff --git a/backends/riscv_init.c b/backends/riscv_init.c
index 8b7ce8b5..ecee2910 100644
--- a/backends/riscv_init.c
+++ b/backends/riscv_init.c
@@ -33,12 +33,16 @@
#define RELOC_PREFIX R_RISCV_
#include "libebl_CPU.h"
+#include "libelfP.h"
+
/* This defines the common reloc hooks based on riscv_reloc.def. */
#include "common-reloc.c"
+extern __typeof (EBLHOOK (return_value_location))
+ riscv_return_value_location_lp64d attribute_hidden;
const char *
-riscv_init (Elf *elf __attribute__ ((unused)),
+riscv_init (Elf *elf,
GElf_Half machine __attribute__ ((unused)),
Ebl *eh,
size_t ehlen)
@@ -59,6 +63,10 @@ riscv_init (Elf *elf __attribute__ ((unused)),
HOOK (eh, machine_flag_check);
HOOK (eh, set_initial_registers_tid);
HOOK (eh, core_note);
+ if (eh->class == ELFCLASS64
+ && ((elf->state.elf64.ehdr->e_flags & EF_RISCV_FLOAT_ABI)
+ == EF_RISCV_FLOAT_ABI_DOUBLE))
+eh->return_value_location = riscv_return_value_location_lp64d;
return MODVERSION;
}
diff --git a/backends/riscv_retval.c b/backends/riscv_retval.c
new file mode 100644
index ..35b6010b
--- /dev/null
+++ b/backends/riscv_retval.c
@@ -0,0 +1,251 @@
+/* Function return value location for Linux/RISC-V ABI.
+ Copyright (C) 2018 Sifive, Inc.
+ Copyright (C) 2013 Red Hat, Inc.
+ This file is part of elfutils.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of either
+
+ * the GNU Lesser General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at
+ your option) any later version
+
+ or
+
+ * the GNU General Public License as published by the Free
+ Software Foundation; either version 2 of the License, or (at
+ your option) any later version
+
+ or both in parallel, as here.
+
+ elfutils is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received copies of the GNU General Public License and
+ the GNU Lesser General Public License along with this program. If
+ not, see <http://www.gnu.org/licenses/>. */
+
+#ifdef HAVE_CONFIG_H
+# include
+#endif
+
+#include
+#include
+
+#include
+#include
+
+#define BACKEND riscv_
+#include "libebl_CPU.h"
+
+static int
+dwarf_bytesize_aux (Dwarf_Die *die, Dwarf_Word *sizep)
+{
+ int bits;
+ if (((bits = 8 * dwarf_bytesize (die)) < 0
+ && (bits = dwarf_bitsize (die)) < 0)
+ || bits % 8 != 0)
+return -1;
+
+ *sizep = bits / 8;
+ return 0;
+}
+
+static int
+pass_in_gpr_lp64 (const Dwarf_Op **locp, Dwarf_Word size)
+{
+ static const Dwarf_Op loc[] =
+{
+ { .atom = DW_OP_reg10 }, { .atom = DW_OP_piece, .number = 8 },
+ { .atom = DW_OP_reg11 }, { .atom = DW_OP_piece, .number = 8 }
+};
+
+ *locp = loc;
+ return size <= 8 ? 1 : 4;
+}
+
+static int
+pass_by_ref (const Dwarf_Op **locp)
+{
+ static const Dw
[PATCH] RISC-V: Add untested 32-bit core file support.
This conflicts with the previoues two patches. Adds 32-bit support exactly the
same way that the sparc backend handles 32- and 64-bit core file support. The
64-bit core file support was tested and still works same as before.
Signed-off-by: Jim Wilson
---
backends/ChangeLog | 11 +
backends/Makefile.am| 2 +-
backends/riscv64_corenote.c | 2 ++
backends/riscv_corenote.c | 45 +++--
backends/riscv_init.c | 7 +-
5 files changed, 53 insertions(+), 14 deletions(-)
create mode 100644 backends/riscv64_corenote.c
diff --git a/backends/ChangeLog b/backends/ChangeLog
index 637aa8c2..58a1b775 100644
--- a/backends/ChangeLog
+++ b/backends/ChangeLog
@@ -1,5 +1,16 @@
2018-12-27 Jim Wilson
+ * Makefile.am (riscv_SRCS): Add riscv64_corenote.c.
+ * riscv64_corenote.c: New file.
+ * riscv_corenote.c (BITS): New.
+ (BACKEND): Conditional on BITS.
+ (ULONG, UID_T, GID_T, ALIGN_ULONG, ALIGN_UID_T, ALIGN_GID_T): Likewise.
+ (TYPE_ULONG, TYPE_UID_T, TYPE_GID_T): Likewise.
+ (prstatus_regs): Use BITS/8 instead of 8.
+ (PRSTATUS_REGS_SIZE): Likewise.
+ * riscv_init.c (riscv64_core_note): Declare.
+ (riscv_init): If ELFCLASS64 then use riscv64_core_note hook.
+
* Makefile.am (riscv_SRCS): Add riscv_retval.c.
* riscv_init.c: Include libelfP.h.
(riscv_return_value_location_lp64d): Declare.
diff --git a/backends/Makefile.am b/backends/Makefile.am
index fedeb93a..2126a2ec 100644
--- a/backends/Makefile.am
+++ b/backends/Makefile.am
@@ -132,7 +132,7 @@ libebl_bpf_pic_a_SOURCES = $(bpf_SRCS)
am_libebl_bpf_pic_a_OBJECTS = $(bpf_SRCS:.c=.os)
riscv_SRCS = riscv_init.c riscv_symbol.c riscv_cfi.c riscv_regs.c \
-riscv_initreg.c riscv_corenote.c riscv_retval.c
+riscv_initreg.c riscv_corenote.c riscv64_corenote.c riscv_retval.c
libebl_riscv_pic_a_SOURCES = $(riscv_SRCS)
am_libebl_riscv_pic_a_OBJECTS = $(riscv_SRCS:.c=.os)
diff --git a/backends/riscv64_corenote.c b/backends/riscv64_corenote.c
new file mode 100644
index ..dbcb89d9
--- /dev/null
+++ b/backends/riscv64_corenote.c
@@ -0,0 +1,2 @@
+#define BITS 64
+#include "riscv_corenote.c"
diff --git a/backends/riscv_corenote.c b/backends/riscv_corenote.c
index afb84bee..b728903f 100644
--- a/backends/riscv_corenote.c
+++ b/backends/riscv_corenote.c
@@ -35,27 +35,48 @@
#include
#include
-#define BACKENDriscv_
+#ifndef BITS
+# define BITS 32
+# define BACKEND riscv_
+#else
+# define BITS 64
+# define BACKEND riscv64_
+#endif
+
#include "libebl_CPU.h"
-#defineULONG uint64_t
+#if BITS == 32
+# define ULONG uint32_t
+# define UID_T uint16_t
+# define GID_T uint16_t
+# define ALIGN_ULONG 4
+# define ALIGN_UID_T 2
+# define ALIGN_GID_T 2
+# define TYPE_ULONGELF_T_WORD
+# define TYPE_UID_TELF_T_HALF
+# define TYPE_GID_TELF_T_HALF
+#else
+# define ULONG uint64_t
+# define UID_T uint32_t
+# define GID_T uint32_t
+# define ALIGN_ULONG 8
+# define ALIGN_UID_T 4
+# define ALIGN_GID_T 4
+# define TYPE_ULONGELF_T_XWORD
+# define TYPE_UID_TELF_T_WORD
+# define TYPE_GID_TELF_T_WORD
+#endif
+
#define PID_T int32_t
-#defineUID_T uint32_t
-#defineGID_T uint32_t
-#define ALIGN_ULONG8
#define ALIGN_PID_T4
-#define ALIGN_UID_T4
-#define ALIGN_GID_T4
-#define TYPE_ULONG ELF_T_XWORD
#define TYPE_PID_T ELF_T_SWORD
-#define TYPE_UID_T ELF_T_WORD
-#define TYPE_GID_T ELF_T_WORD
+
static const Ebl_Register_Location prstatus_regs[] =
{
-{ .offset = 8, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
+{ .offset = BITS/8, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
};
-#define PRSTATUS_REGS_SIZE (32 * 8)
+#define PRSTATUS_REGS_SIZE (32 * (BITS/8))
#define PRSTATUS_REGSET_ITEMS \
{\
diff --git a/backends/riscv_init.c b/backends/riscv_init.c
index ecee2910..3398c104 100644
--- a/backends/riscv_init.c
+++ b/backends/riscv_init.c
@@ -41,6 +41,8 @@
extern __typeof (EBLHOOK (return_value_location))
riscv_return_value_location_lp64d attribute_hidden;
+extern __typeof (EBLHOOK (core_note)) riscv64_core_note attribute_hidden;
+
const char *
riscv_init (Elf *elf,
GElf_Half machine __attribute__ ((unused)),
@@ -62,7 +64,10 @@ riscv_init (Elf *elf,
HOOK (eh, check_special_symbol);
HOOK (eh, machine_flag_check);
HOOK (eh, set_initial_registers_tid);
- HOOK (eh, core_not
Re: RISC-V support
On Tue, Jan 8, 2019 at 5:52 AM Mark Wielaard wrote: > The _start one seems to be: > https://sourceware.org/bugzilla/show_bug.cgi?id=23125 > So that is fixed with glibc 2.29. > > Do you have a bug for the second issue with __thread_start? https://sourceware.org/bugzilla/show_bug.cgi?id=24040 I plan to write a patch for it, if Andreas Schwab doesn't get to it first, but the Fedora koji package server was down for a few weeks which prevented me from installing the packages I needed to do this work. It is back up and I am looking at this now. > It would be nice to have some riscv setup for our buildbot. Do you > happen to have recommendations for something like that? Any distro that > gets regular toolchain updates? Is a libvirt/qemu setup reliable enough > or would you recommend trying to get real hardware? I've been using Fedora, but Debian and OpenSuse are both usable too. Fedora is just a little more convenient for me as they have images I can download and boot, and a git tree for building a kernel with NBD support which makes the HiFive Unleashed much more stable than when using the SDcard for the root file system. Plus I used to work for Cygnus/Red Hat so maybe I am a little biased. QEMU works too. There are some known bugs in the RISC-V qemu FP support, I wouldn't use it for numerical work. If you stress the system you might find some bugs, but overall it is certainly usable. I used qemu for my gdb work, because it was easier to try kernel patches that way, and I didn't want to risk trying untested kernel patches on my main RISC-V development system. The linux distro folks are using qemu for builds also, to supplement the builds on hardware, as they have limited numbers of boards at present. There is only one ASIC option for running linux that I know of at this time, and that is the SiFive HiFive Unleashed. It is faster than qemu running on a fast x86_64 machine. It is stable if you don't use the SDcard for anything other than booting. I've hit 60 days of uptime on my board, running a patched 4.15 kernel. There are also FPGA options, but these are more complicated and probably more expensive than using the HiFive Unleashed. I expect that more hardware options will be available in the future. Jim
Re: [PATCH] RISC-V: Add initial return value location support.
On Thu, Jan 10, 2019 at 4:26 AM Mark Wielaard wrote: > The comments explain things well, but it would be good to have official > references to the calling convention and DWARF register mappings. > The calling convention is explained in: > > https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#procedure-calling-convention > But I couldn't find an official DWARF register mapping. > If you have references I like to add them to the code. There is an issue asking us to add DWARF register mappings. This was filed before gdb was upstream and so some the comments are out of date, but most of the info is still correct. https://github.com/riscv/riscv-elf-psabi-doc/issues/70 I guess I should put that on my to do list to finish this now. Jim
Re: [PATCH] RISC-V: Add initial return value location support.
On Thu, Jan 10, 2019 at 4:26 AM Mark Wielaard wrote: > We really should add a non-native test, so it is easier to test on > other arches. But currently only aarch64 has one (run-funcretval.sh). > I'll see if I can extend that to other arches. Then we can also see if > we can get the aggregates correct. RISC-V will require additional types for full coverage. I've been adding extra types to my local copy of the testcase .c file as I implement them, but I still have a ways to go before this is finished, and a few too many things on my to do list. Jim
Re: [PATCH] RISC-V: Add untested 32-bit core file support.
On Sat, Jan 12, 2019 at 2:29 PM Mark Wielaard wrote:
> I don't really like adding code that cannot be tested. But it does look
> the 32-bit port isn't far off, just waiting for the next linux/glibc
> release to settle the time_t ABI. And the code does look correct.
> Except for...
We don't expect 32-bit desktop linux distros, but there are folks that
want 32-bit embedded linux. A few companies have gotten it working,
but only Andes is trying to upstream patches so far, and as you
mentioned that is waiting for the time_t ABI. Meanwhile, it should be
possible to build a busy-box style 32-bit linux system, using an old
obsolete pre-upstream glibc port, but that isn't useful for real
development work.
> > static const Ebl_Register_Location prstatus_regs[] =
> >{
> > -{ .offset = 8, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
> > +{ .offset = BITS/8, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
> >};
>
> Should that be .bits = BITS ?
Yes, sorry, I was looking at the offset field and completely missed
the bits member at the end. Do you want me to submit an updated
patch?
Jim
Re: RISC-V support
On Sat, Jan 12, 2019 at 3:21 PM Kurt Roeckx wrote: > > But how many are actually used? Which does Debian support? > > I'm not at all an export of mips, I really don't know that much > about it. It depends on how you count ABIs, but yes there have unfortunately been a lot of them over the years. As a practical matter, you should only need support for the (old) 32 bit ABI with pic support, the n32 ABI (which is 32-bit types on a 64-bit machine like the x86_64 x32 ABI), and the (new) 64-bit ABI. Those are the only ones that gcc supports for linux and other POSIX operating systems. These exist in both big-endian and little-endian forms. There are a bunch of other ABIs or ABI variants that were only ever supported for embedded systems, or were used on old pre-shared library systems, or were never implemented in FSF GCC. So you can ignore all of those. Jim
Re: RISC-V support
On Sat, Jan 12, 2019 at 5:23 PM Kurt Roeckx wrote: > O32 really has at least the following variants: > - O32 FP32 > - O32 FPXX > - O32 FP64 > - O32 FP64A The FPXX and FP64A stuff is new, after I stopped tracking MIPS stuff, so I hadn't noticed it. I see why they added these, but if you count soft-float, single-float, no-float, and a now deprecated 64-bit FP reg mode, there are 8 different ways to handle FP code for o32. Crazy. Most of them aren't relevant to linux though. And I suppose 20-30 years from now RISC-V may have the same problem. Jim
Re: [PATCH] RISC-V: Add initial return value location support.
On Thu, Jan 10, 2019 at 4:26 AM Mark Wielaard wrote: > https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#procedure-calling-convention > But I couldn't find an official DWARF register mapping. > If you have references I like to add them to the code. This document now has a chapter for DWARF info, with just one table to specify the DWARF register mapping. https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#dwarf-register-numbers Jim
Re: RISC-V disassembler
On 9/7/19 2:18 AM, Ulrich Drepper wrote: I'll check in the attached patch which implements a disassembler for RISC-V. It also fixes a problem in the x86 disassember, exposed through the additions needed for RISC-V. Since aside rth, who added the BPF disassembler, no one beside me ever worked on that code I will push the changes as soon as I can. There are some binary bz2 files missing at the end of the patch, but if you are committing this yourself that is probably OK. There is a testfile45.expect.bz2 that doesn't look like it is supposed to be part of the patch set. You probably don't want to commit that one. There is a testcase for riscv64 but not for riscv32, though the code does look like it correctly handles rv32 versus rv64 decodes. A testcase for rv32 would be a nice improvement. Otherwise, it looks pretty good at a first glance, and I'm not planning to do a full review. Seems to handle the obvious tricky cases correctly. It doesn't support rv128 or the q (quadfloat) extension, but then I don't know of anyone using them, and binutils probably doesn't handle them correctly either. We have binutils patches for the draft V (vector) and B (bit manipulation) extensions in branches in the github.com riscv repos, but these are still changing instruction mnemonics and encodings, so not ready for official trees yet. We just need to remember that we have another disassembler to update when the V and/or B extensions are finalized. There are also new CSR registers being added regularly, for extensions, and for hardware features like the draft CLIC interrupt controller spec, so that is another thing that will need occasional updates. Jim
