[PATCH v1 1/8] Move ARM PL011 UART driver

[Kinsey Moore]

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am| 2 --
 bsps/arm/raspberrypi/console/console-config.c  | 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h | 2 +-
 bsps/arm/xen/console/console.c | 2 +-
 bsps/headers.am| 2 ++
 bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/libchip}/arm-pl011.h  | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am   | 2 +-
 spec/build/bsps/arm/grp.yml| 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml| 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml   | 1 -
 spec/build/bsps/arm/xen/bspxen.yml | 1 -
 spec/build/bsps/obj.yml| 3 +++
 16 files changed, 13 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..27d02bbe39 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..0ed99ec86e 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..446bd2c3b8 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..825574a5a9 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -110,6 +110,8 @@ include_libchip_HEADERS += 
../../bsps/include/libchip/mc68681.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550_p.h
 include_libchip_HEADERS += ../../bsps/include/libchip/open_eth.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011-regs.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011.h
 include_libchip_HEADERS += ../../bsps/include/libchip/rtc.h
 include_libchip_HEADERS += ../../bsps/include/libchip/serial.h
 include_libchip_HEADERS += ../../bsps/include/libchip/sersupp.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/libchip/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/libchip/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h b/bsps/include/libchip/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/libchip/arm-pl011.h
index 49ff413581..947c254bd8 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/libchip/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..39225e8349 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ b/bsps/shared/dev/serial/arm-pl011.c
@@

[PATCH v1 0/8] AArch64 port and BSPs

[Kinsey Moore]

This patch set includes changes to move several required drivers
into bsps/shared so that they can be used by both AArch32(known in RTEMS
as "arm") and AArch64 as well as possibly other future architectures.
The changes made in breaking out these drivers have been tested on 10 or
so affected BSPs under both the old autotools build system and the new
waf build system.

In addition to the AArch64 port itself, this patch set includes a pair
of sample BSPs that run on QEMU and demonstrate use of the two available
multilib variants: lp64 and ilp32. These BSPs are only configurable
under the waf build system. The port and these BSPs do not currently
support SMP, even though there is some SMP-related code currently in
place.

Look for related patch sets for rtems-doc and rtems-tools following
shortly.


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[PATCH v1 5/8] bsps/shared: Add PSCI-based bspreset implementation

[Kinsey Moore]

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-psci.c | 48 +++
 1 file changed, 48 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-psci.c

diff --git a/bsps/shared/start/bspreset-psci.c 
b/bsps/shared/start/bspreset-psci.c
new file mode 100644
index 00..33dd38e814
--- /dev/null
+++ b/bsps/shared/start/bspreset-psci.c
@@ -0,0 +1,48 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v1 6/8] score: Add AArch64 port

[Kinsey Moore]

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   2 +-
 .../cpu/aarch64/aarch64-context-validate.S| 295 ++
 .../aarch64-context-volatile-clobber.S|  90 +++
 .../cpu/aarch64/aarch64-exception-default.S   | 407 +
 .../cpu/aarch64/aarch64-exception-default.c   |  39 ++
 .../aarch64/aarch64-exception-frame-print.c   |  96 +++
 .../cpu/aarch64/aarch64-exception-interrupt.S | 306 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  48 ++
 cpukit/score/cpu/aarch64/cpu.c| 196 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 101 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  90 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  81 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 548 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  34 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  81 +++
 spec/build/cpukit/cpuaarch64.yml  |  32 +
 spec/build/cpukit/librtemscpu.yml |   2 +
 18 files changed, 2581 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..8c15eee569 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,7 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+#if CPU_SIZEOF_POINTER == 4 || CPU_SIZEOF_POINTER == 8
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..afd339ad85
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,295 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+
+#define FRAME_OFFSET_X4 0
+#define FRAME_OFFSET_X5 8
+#define FRAME_OFFSET_X6 16
+#define FRAME_OFFSET_X7 24
+#define FRAME_OFFSET_X8 32
+#define FRAME_OFFSET_X9 40
+#define FRAME_OFFSET_X10 48
+#define FRAME_OFFSET_X11 56
+#define FRAME_OFFSET_LR 64
+
+#ifdef AARCH64_MULTILIB_VFP
+  #define FRAME_OFFSET_V8 72
+  #define FRAME_OFFSET_V9 88
+  #def

[PATCH v1 8/8] bsps: Add Cortex-A53 ILP32 BSP variant

[Kinsey Moore]

ed/dev/serial/console-termios.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/bspgetworkarea-default.c
+- bsps/shared/start/bspreset-psci.c
+- bsps/shared/start/sbrk.c
+- bsps/shared/irq/irq-arm-gicv3.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/clock/clock-arm-generic-timer.c
+- bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
+type: build
diff --git a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
index 06c3a91265..ee99200b18 100644
--- a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
+++ b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
@@ -46,7 +46,7 @@ links:
 - role: build-dependency
   uid: ../../opto2
 - role: build-dependency
-  uid: linkcmds
+  uid: linkcmds_lp64
 - role: build-dependency
   uid: ../../bspopts
 source:
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..9f6872215a
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,68 @@
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   * POSSIBILITY OF SUCH DAMAGE.
+   */
+
+  MEMORY {
+RAM   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_LOAD_OFFSET}, LENGTH 
= ${BSP_A53_RAM_LENGTH} - ${BSP_A53_LOAD_OFFSET} - ${BSP_A53_NOCACHE_LENGTH}
+NOCACHE   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_RAM_LENGTH} - 
${BSP_A53_NOCACHE_LENGTH}, LENGTH = ${BSP_A53_NOCACHE_LENGTH}
+  }
+
+  REGION_ALIAS ("REGION_START",  RAM);
+  REGION_ALIAS ("REGION_VECTOR", RAM);
+  REGION_ALIAS ("REGION_TEXT",   RAM);
+  REGION_ALIAS ("REGION_TEXT_LOAD",  RAM);
+  REGION_ALIAS ("REGION_RODATA", RAM);
+  REGION_ALIAS ("REGION_RODATA_LOAD",RAM);
+  REGION_ALIAS ("REGION_DATA",   RAM);
+  REGION_ALIAS ("REGION_DATA_LOAD",  RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT",  RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA",  RAM);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_BSS",RAM);
+  REGION_ALIAS ("REGION_WORK",   RAM);
+  REGION_ALIAS ("REGION_STACK",  RAM);
+  REGION_ALIAS ("REGION_NOCACHE",NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+
+  bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? 
bsp_stack_exception_size : 1024;
+
+  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? 
bsp_section_rwbarrier_align : 1M;
+
+  bsp_vector_table_in_start_section = 1;
+
+  OUTPUT_FORMAT ("elf32-littleaarch64")
+  OUTPUT_ARCH (aarch64:ilp32)
+
+  INCLUDE linkcmds.base
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
similarity index 97%
rename from spec/build/bsps/aarch64/a53/linkcmds.yml
rename to spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
index 23c99f693a..33732a7fbb 100644
--- a/spec/build/bsps/aarch64/a53/linkcmds.yml
+++ b/spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
@@ -57,6 +57,9 @@ content: |
 
   bsp_vector_table_in_start_section = 1;
 
+  OUTPUT_FORMAT ("elf64-littleaarch64&qu

[PATCH v1 2/8] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

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[PATCH v1 7/8] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  61 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  59 ++
 bsps/aarch64/a53/include/tm27.h   |  38 ++
 bsps/aarch64/a53/start/bspstart.c |  41 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  42 ++
 bsps/aarch64/include/bsp/irq-arch.h   |  42 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 612 ++
 .../clock/clock-arm-generic-timer-aarch64.c   | 102 +++
 .../shared/irq/irq-arm-gicv3-aarch64.c|  50 ++
 bsps/aarch64/shared/start/linkcmds.base   | 450 +
 bsps/aarch64/shared/start/start.S | 217 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  14 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  70 ++
 spec/build/bsps/aarch64/a53/linkcmds.yml  |  65 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  15 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  15 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  15 +
 spec/build/bsps/aarch64/a53/optramori.yml |  15 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  53 ++
 spec/build/bsps/aarch64/start.yml |  11 +
 23 files changed, 2411 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/irq-arch.h
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..1a3c8fe8b0
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,61 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_context = {
+  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
+  .regs = (volatile pl011 *) BSP_A53_QEMU_VPL011_BASE,
+  .initial_baud = 115200
+};
+
+const console_device console_device_table[] = {
+  {
+.device_file = "/dev/ttyS0",
+.probe = console_device_probe_default,
+.hand

[PATCH v1 4/8] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

nclude/bsp/arm-pl111-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-release-id.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/armv7m-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/clock-armv7m.h
+include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/irq-arch.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/linker-symbols.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-dma.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-emc.h
diff --git a/bsps/arm/include/bsp/irq-arch.h b/bsps/arm/include/bsp/irq-arch.h
new file mode 100644
index 00..c902f68953
--- /dev/null
+++ b/bsps/arm/include/bsp/irq-arch.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_IRQ_ARCH_H
+#define LIBBSP_ARM_SHARED_IRQ_ARCH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+void bsp_interrupt_dispatch( void );
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_IRQ_ARCH_H */
diff --git a/bsps/arm/lpc24xx/irq/irq-dispatch.c 
b/bsps/arm/lpc24xx/irq/irq-dispatch.c
index 66d05fdf9d..7baa527595 100644
--- a/bsps/arm/lpc24xx/irq/irq-dispatch.c
+++ b/bsps/arm/lpc24xx/irq/irq-dispatch.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/arm/lpc32xx/irq/irq.c b/bsps/arm/lpc32xx/irq/irq.c
index eac32b..f0c1f4f548 100644
--- a/bsps/arm/lpc32xx/irq/irq.c
+++ b/bsps/arm/lpc32xx/irq/irq.c
@@ -23,6 +23,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/raspberrypi/irq/irq.c b/bsps/arm/raspberrypi/irq/irq.c
index 835cdf97d9..1e5e4735b3 100644
--- a/bsps/arm/raspberrypi/irq/irq.c
+++ b/bsps/arm/raspberrypi/irq/irq.c
@@ -25,6 +25,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/rtl22xx/irq/irq.c b/bsps/arm/rtl22xx/irq/irq.c
index 83e140bd7b..7f94958105 100644
--- a/bsps/arm/rtl22xx/irq/irq.c
+++ b/bsps/arm/rtl22xx/irq/irq.c
@@ -13,6 +13,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
new file mode 100644
index 00..bff1256533
--- /dev/null
+++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
@@ -0,0 +1,47 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 

[PATCH v1 3/8] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  1 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  3 +-
 .../clock/clock-arm-generic-timer-aarch32.c   | 68 +++
 bsps/arm/xen/headers.am   |  1 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  3 +-
 bsps/arm/xilinx-zynqmp/headers.am |  1 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  3 +-
 bsps/include/bsp/clock-arm-generic-timer.h| 65 ++
 .../clock/clock-arm-generic-timer.c}  | 65 --
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  4 +-
 spec/build/bsps/arm/xen/bspxen.yml|  4 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  4 +-
 18 files changed, 171 insertions(+), 66 deletions(-)
 create mode 100644 bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/bsp/clock-arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/clock/clock-arm-generic-timer.c} (71%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..76c1607871 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,4 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+include_bsp_HEADERS += 
../../../../../../bsps/include/bsp/clock-arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..ff5edaf5a1 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -58,7 +59,7 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return intr[1] + MAGIC_IRQ_OFFSET;
 }
 
-void arm_generic_timer_get_config(
+void aarch_generic_timer_get_config(
   uint32_t *frequency,
   uint32_t *irq
 )
diff --git a/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
new file mode 100644
index 00..c9d26945ea
--- /dev/null
+++ b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
@@ -0,0 +1,68 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t aarch_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  return arm_cp15_get_counter_pl1_virtual_compare_value();
+#else
+  return arm_cp15_get_counter_pl1_physical_compare_value();
+#endif
+}
+
+void aarch_gt_clock_set_compare_value(uint64_t cva

[PATCH v1 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..26d88ea 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,7 +34,7 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
+The ARMv5 and later instruction sets have the count leading zeroes ``clz`` 
instruction which
 could be used to speed up the find first bit operation.  The use of this
 instruction should significantly speed up the scheduling associated with a
 thread blocking.  This is currently not used.
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -196,11 +196,11 @@ Symmetric Multiprocessing
 
 SMP is supported on ARMv7-A.  Available platforms are
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v1 2/2] Add AArch64 documentation

[Kinsey Moore]

---
 cpu-supplement/aarch64.rst | 129 +
 user/bsps/aarch64/a53.rst  |  26 
 user/bsps/bsps-aarch64.rst |   2 +-
 3 files changed, 156 insertions(+), 1 deletion(-)
 create mode 100644 cpu-supplement/aarch64.rst
 create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..b23f7dc
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,129 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
+
+AArch64 Specific Information
+
+
+This chapter discusses the dependencies of the
+*ARM AArch64 architecture*
+(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
+of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
+use a static configuration which is set up during system start.  SMP is not
+supported.
+
+**Architecture Documents**
+
+For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
+(http://infocenter.arm.com/).
+
+CPU Model Dependent Features
+
+
+This section presents the set of features which vary across ARM AArch64
+implementations and are of importance to RTEMS.  The set of CPU model feature
+macros are defined in the file 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+based upon the particular CPU model flags specified on the compilation command
+line.
+
+CPU Model Name
+--
+
+The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
+level of this CPU model.  See in 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+for the values.
+
+Floating Point Unit and SIMD
+
+
+The Advanced SIMD (NEON) and Floating-point instruction set extension is
+supported and expected to be present since all ARMv8-A CPUs are expected to
+support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
+(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
+such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
+
+Multilibs
+=
+
+The following multilib variants are available:
+
+#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and 
pointers
+
+#. ``LP64``: AArch64 instruction set and registers using 64bit long int and 
pointers
+
+Use for example the following GCC options:
+
+.. code-block:: shell
+
+-mcpu=cortex-a53 -mabi=ilp32
+
+to build an application or BSP for the ARMv8-A architecture and tune the code
+for a Cortex-A53 processor.  It is important to select the correct ABI.
+
+Calling Conventions
+===
+
+Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
+(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
+
+Memory Model
+
+
+A flat 64-bit or 32-bit memory model is supported depending on the selected 
multilib
+variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
+for a flat memory model is handled.
+
+Interrupt Processing
+
+
+The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
+configuration signals only sampled at reset.  The ARMv8 architecture has four
+exception types: 
+
+- Synchronous Exception
+
+- Interrupt (IRQ)
+
+- Fast Interrupt (FIQ)
+
+- System Error Exception
+
+Of these types only the synchronous and IRQ exceptions have explicit operating
+system support.  It is intentional that the FIQ is not supported by the 
operating
+system.  Without operating system support for the FIQ it is not necessary to
+disable them during critical sections of the system.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
+zero corresponds to interrupts enabled.  Level one corresponds to interrupts
+disabled.
+
+Interrupt Stack
+---
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+Default Fatal Error Processing
+==
+
+The default fatal error handler for this architecture performs the following
+actions:
+
+- disables operating system supported interrupts (IRQ),
+
+- places the error code in ``x0``, and
+
+- executes an infinite loop to simulate a halt processor instruction.
+
+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.
+
+Thread-Local Storage
+
+
+Thread-local storage is supported.
diff --git a/user/bsps/aarch64/a53.rst b/user/bsps/aarch64/a53.rst
new file mode 100644
index 000..0052773
--- /dev/null
+++ b/user/bsps/aarch64/a53.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 2020 Kinsey Moore, On-Line Applications Research Corporation 
(OAR)
+
+.. _BSP_aarch64_qemu_a53_

[PATCH v1 1/2] tester: Add a53_lp64_qemu.ini

[Kinsey Moore]

---
 tester/rtems/testing/bsps/a53_lp64_qemu.ini | 38 +
 1 file changed, 38 insertions(+)
 create mode 100644 tester/rtems/testing/bsps/a53_lp64_qemu.ini

diff --git a/tester/rtems/testing/bsps/a53_lp64_qemu.ini 
b/tester/rtems/testing/bsps/a53_lp64_qemu.ini
new file mode 100644
index 000..f29ab13
--- /dev/null
+++ b/tester/rtems/testing/bsps/a53_lp64_qemu.ini
@@ -0,0 +1,38 @@
+#
+# RTEMS Tools Project (http://www.rtems.org/)
+# Copyright 2020 Kinsey Moore(kinsey.mo...@oarcorp.com)
+# All rights reserved.
+#
+# This file is part of the RTEMS Tools package in 'rtems-tools'.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# The AArch64 Cortex-A53 LP64 BSP.
+#
+[a53_lp64_qemu]
+bsp   = a53_lp64_qemu
+arch  = aarch64
+tester= %{_rtscripts}/qemu.cfg
+bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
virt,gic_version=3 -cpu cortex-a53 -m 4096
-- 
2.20.1

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[PATCH v1 2/2] tester: Add a53_ilp32_qemu.ini

[Kinsey Moore]

---
 tester/rtems/testing/bsps/a53_ilp32_qemu.ini | 38 
 1 file changed, 38 insertions(+)
 create mode 100644 tester/rtems/testing/bsps/a53_ilp32_qemu.ini

diff --git a/tester/rtems/testing/bsps/a53_ilp32_qemu.ini 
b/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
new file mode 100644
index 000..6dfc883
--- /dev/null
+++ b/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
@@ -0,0 +1,38 @@
+#
+# RTEMS Tools Project (http://www.rtems.org/)
+# Copyright 2020 Kinsey Moore(kinsey.mo...@oarcorp.com)
+# All rights reserved.
+#
+# This file is part of the RTEMS Tools package in 'rtems-tools'.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# The AArch64 Cortex-A53 ILP32 BSP.
+#
+[a53_ilp32_qemu]
+bsp   = a53_ilp32_qemu
+arch  = aarch64
+tester= %{_rtscripts}/qemu.cfg
+bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
virt,gic_version=3 -cpu cortex-a53 -m 4096
-- 
2.20.1

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RE: [PATCH v1 6/8] score: Add AArch64 port

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Friday, September 25, 2020 11:20
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v1 6/8] score: Add AArch64 port

On 25/09/2020 17:27, Kinsey Moore wrote:

> diff --git a/cpukit/include/rtems/score/tls.h 
> b/cpukit/include/rtems/score/tls.h
> index 65a49d87be..8c15eee569 100644
> --- a/cpukit/include/rtems/score/tls.h
> +++ b/cpukit/include/rtems/score/tls.h
> @@ -85,7 +85,7 @@ typedef struct TLS_Thread_control_block {
> struct TLS_Thread_control_block *tcb;
>   #else /* !__i386__ */
> TLS_Dynamic_thread_vector *dtv;
> -#if CPU_SIZEOF_POINTER == 4
> +#if CPU_SIZEOF_POINTER == 4 || CPU_SIZEOF_POINTER == 8
> uintptr_t reserved;
>   #endif
>   #endif /* __i386__ */
Are you sure this is correct? TLS_Dynamic_thread_vector *dtv; is 8 bytes in 
this case.
[] 
Dropping this change causes sptls01 to fail. This was added pretty early in the 
implementation, so I've just had to go back and refresh my memories of the 
reasoning behind it which still may not be entirely accurate. Sptls01 fails 
without this patch because under AArch64/LP64, gcc and gdb expect a 16 byte 
offset to the TLS data segment. If this patch is not present, the TCB is half 
the size it needs to be and so getting a TLS variable address ends up indexing 
into the TCB+TLS data segment at a compiler-expected offset that does not 
correspond to the actual data layout. I adjusted this to match the compiler's 
offset expectations. There may be a better way to fix this issue, but this is 
the most appropriate location I could find that made the most sense. The 
biggest worry I have here is that this may break other architectures that also 
have 8 byte pointers. When I fix the file headers, I'll see if I can make this 
more specific to AArch64.

Kinsey
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[PATCH v2 1/8] Move ARM PL011 UART driver

[Kinsey Moore]

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am| 2 --
 bsps/arm/raspberrypi/console/console-config.c  | 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h | 2 +-
 bsps/arm/xen/console/console.c | 2 +-
 bsps/headers.am| 2 ++
 bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/libchip}/arm-pl011.h  | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am   | 2 +-
 spec/build/bsps/arm/grp.yml| 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml| 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml   | 1 -
 spec/build/bsps/arm/xen/bspxen.yml | 1 -
 spec/build/bsps/obj.yml| 3 +++
 16 files changed, 13 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..27d02bbe39 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..0ed99ec86e 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..446bd2c3b8 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..825574a5a9 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -110,6 +110,8 @@ include_libchip_HEADERS += 
../../bsps/include/libchip/mc68681.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550_p.h
 include_libchip_HEADERS += ../../bsps/include/libchip/open_eth.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011-regs.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011.h
 include_libchip_HEADERS += ../../bsps/include/libchip/rtc.h
 include_libchip_HEADERS += ../../bsps/include/libchip/serial.h
 include_libchip_HEADERS += ../../bsps/include/libchip/sersupp.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/libchip/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/libchip/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h b/bsps/include/libchip/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/libchip/arm-pl011.h
index 49ff413581..947c254bd8 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/libchip/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..39225e8349 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ b/bsps/shared/dev/serial/arm-pl011.c
@@

[PATCH v2 4/8] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

nclude/bsp/arm-pl111-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-release-id.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/armv7m-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/clock-armv7m.h
+include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/irq-arch.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/linker-symbols.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-dma.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-emc.h
diff --git a/bsps/arm/include/bsp/irq-arch.h b/bsps/arm/include/bsp/irq-arch.h
new file mode 100644
index 00..b3be1bc10b
--- /dev/null
+++ b/bsps/arm/include/bsp/irq-arch.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARM
+ *
+ * @brief ARM IRQ definitions
+ */
+
+/*
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_IRQ_ARCH_H
+#define LIBBSP_ARM_SHARED_IRQ_ARCH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+void bsp_interrupt_dispatch( void );
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_IRQ_ARCH_H */
diff --git a/bsps/arm/lpc24xx/irq/irq-dispatch.c 
b/bsps/arm/lpc24xx/irq/irq-dispatch.c
index 66d05fdf9d..7baa527595 100644
--- a/bsps/arm/lpc24xx/irq/irq-dispatch.c
+++ b/bsps/arm/lpc24xx/irq/irq-dispatch.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/arm/lpc32xx/irq/irq.c b/bsps/arm/lpc32xx/irq/irq.c
index eac32b..f0c1f4f548 100644
--- a/bsps/arm/lpc32xx/irq/irq.c
+++ b/bsps/arm/lpc32xx/irq/irq.c
@@ -23,6 +23,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/raspberrypi/irq/irq.c b/bsps/arm/raspberrypi/irq/irq.c
index 835cdf97d9..1e5e4735b3 100644
--- a/bsps/arm/raspberrypi/irq/irq.c
+++ b/bsps/arm/raspberrypi/irq/irq.c
@@ -25,6 +25,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/rtl22xx/irq/irq.c b/bsps/arm/rtl22xx/irq/irq.c
index 83e140bd7b..7f94958105 100644
--- a/bsps/arm/rtl22xx/irq/irq.c
+++ b/bsps/arm/rtl22xx/irq/irq.c
@@ -13,6 +13,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
new file mode 100644
index 00..a26c254787
--- /dev/null
+++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific IRQ handlers.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE

[PATCH v2 3/8] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  1 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  3 +-
 .../clock/clock-arm-generic-timer-aarch32.c   | 76 +++
 bsps/arm/xen/headers.am   |  1 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  3 +-
 bsps/arm/xilinx-zynqmp/headers.am |  1 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  3 +-
 bsps/include/bsp/clock-arm-generic-timer.h| 73 ++
 .../clock/clock-arm-generic-timer.c}  | 65 
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  4 +-
 spec/build/bsps/arm/xen/bspxen.yml|  4 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  4 +-
 18 files changed, 187 insertions(+), 66 deletions(-)
 create mode 100644 bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/bsp/clock-arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/clock/clock-arm-generic-timer.c} (71%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..76c1607871 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,4 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+include_bsp_HEADERS += 
../../../../../../bsps/include/bsp/clock-arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..ff5edaf5a1 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -58,7 +59,7 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return intr[1] + MAGIC_IRQ_OFFSET;
 }
 
-void arm_generic_timer_get_config(
+void aarch_generic_timer_get_config(
   uint32_t *frequency,
   uint32_t *irq
 )
diff --git a/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
new file mode 100644
index 00..70509e2a86
--- /dev/null
+++ b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific clock driver functions.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t aarch_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  return arm_cp15_get_counter_pl1_virtual_compare_value();
+#e

[PATCH v2 2/2] Add AArch64 documentation

[Kinsey Moore]

r the LP64
+multilib variant, the the TCB is 16 bytes in size instead of 8 bytes.
diff --git a/user/bsps/aarch64/a53.rst b/user/bsps/aarch64/a53.rst
new file mode 100644
index 000..0052773
--- /dev/null
+++ b/user/bsps/aarch64/a53.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 2020 Kinsey Moore, On-Line Applications Research Corporation 
(OAR)
+
+.. _BSP_aarch64_qemu_a53_ilp32:
+.. _BSP_aarch64_qemu_a53_lp64:
+
+Qemu A53
+
+
+This BSP supports two variants, `qemu_a53_ilp32` and `qemu-a53_lp64`. The basic
+hardware initialization is performed by the BSP.
+
+Boot via ELF
+
+The executable image is booted by Qemu in ELF format.
+
+Clock Driver
+
+
+The clock driver uses the `ARM Generic Timer`.
+
+Console Driver
+--
+
+The console driver supports the default Qemu emulated ARM PL011 PrimeCell UART.
diff --git a/user/bsps/bsps-aarch64.rst b/user/bsps/bsps-aarch64.rst
index 4b2e749..319310e 100644
--- a/user/bsps/bsps-aarch64.rst
+++ b/user/bsps/bsps-aarch64.rst
@@ -5,4 +5,4 @@
 aarch64 (AArch64)
 *
 
-There are no AArch64 BSPs yet.
+.. include:: aarch64/a53.rst
-- 
2.20.1

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[PATCH v2 2/8] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

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[PATCH v2 5/8] bsps/shared: Add PSCI-based bspreset implementation

[Kinsey Moore]

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-psci.c | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-psci.c

diff --git a/bsps/shared/start/bspreset-psci.c 
b/bsps/shared/start/bspreset-psci.c
new file mode 100644
index 00..215be5c9b5
--- /dev/null
+++ b/bsps/shared/start/bspreset-psci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP reset hook.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v2 8/8] bsps: Add Cortex-A53 ILP32 BSP variant

[Kinsey Moore]

c
+- bsps/aarch64/a53/start/bspstarthooks.c
+- bsps/shared/dev/getentropy/getentropy-cpucounter.c
+- bsps/shared/dev/serial/console-termios-init.c
+- bsps/shared/dev/serial/console-termios.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/bspgetworkarea-default.c
+- bsps/shared/start/bspreset-psci.c
+- bsps/shared/start/sbrk.c
+- bsps/shared/irq/irq-arm-gicv3.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/clock/clock-arm-generic-timer.c
+- bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
+type: build
diff --git a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
index cda7450cb8..05f1dc71c4 100644
--- a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
+++ b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
@@ -49,7 +49,7 @@ links:
 - role: build-dependency
   uid: ../../opto2
 - role: build-dependency
-  uid: linkcmds
+  uid: linkcmds_lp64
 - role: build-dependency
   uid: ../../bspopts
 source:
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..ed585f1950
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,71 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   * POSSIBILITY OF SUCH DAMAGE.
+   */
+
+  MEMORY {
+RAM   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_LOAD_OFFSET}, LENGTH 
= ${BSP_A53_RAM_LENGTH} - ${BSP_A53_LOAD_OFFSET} - ${BSP_A53_NOCACHE_LENGTH}
+NOCACHE   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_RAM_LENGTH} - 
${BSP_A53_NOCACHE_LENGTH}, LENGTH = ${BSP_A53_NOCACHE_LENGTH}
+  }
+
+  REGION_ALIAS ("REGION_START",  RAM);
+  REGION_ALIAS ("REGION_VECTOR", RAM);
+  REGION_ALIAS ("REGION_TEXT",   RAM);
+  REGION_ALIAS ("REGION_TEXT_LOAD",  RAM);
+  REGION_ALIAS ("REGION_RODATA", RAM);
+  REGION_ALIAS ("REGION_RODATA_LOAD",RAM);
+  REGION_ALIAS ("REGION_DATA",   RAM);
+  REGION_ALIAS ("REGION_DATA_LOAD",  RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT",  RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA",  RAM);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_BSS",RAM);
+  REGION_ALIAS ("REGION_WORK",   RAM);
+  REGION_ALIAS ("REGION_STACK",  RAM);
+  REGION_ALIAS ("REGION_NOCACHE",NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+
+  bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? 
bsp_stack_exception_size : 1024;
+
+  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? 
bsp_section_rwbarrier_align : 1M;
+
+  bsp_vector_table_in_start_section = 1;
+
+  OUTPUT_FORMAT ("elf32-littleaarch64")
+  OUTPUT_ARCH (aarch64:ilp32)
+
+  INCLUDE linkcmds.base
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
similarity index 97%
rename from spec/build/bsps/aarch64/a53/linkcmds.yml
renam

[PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  69 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  67 ++
 bsps/aarch64/a53/include/tm27.h   |  46 ++
 bsps/aarch64/a53/start/bspstart.c |  49 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  50 ++
 bsps/aarch64/include/bsp/irq-arch.h   |  50 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 612 ++
 .../clock/clock-arm-generic-timer-aarch64.c   | 110 
 .../shared/irq/irq-arm-gicv3-aarch64.c|  58 ++
 bsps/aarch64/shared/start/linkcmds.base   | 450 +
 bsps/aarch64/shared/start/start.S | 219 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  17 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  73 +++
 spec/build/bsps/aarch64/a53/linkcmds.yml  |  68 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  18 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramori.yml |  18 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  56 ++
 spec/build/bsps/aarch64/start.yml |  14 +
 23 files changed, 2504 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/irq-arch.h
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..d9fffb1e0c
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64A53
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_context = {
+  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
+  .regs = (volatile pl011 *) BSP_A53_QEMU_VPL011_BASE,
+  .initial_baud = 115200
+};
+
+const console_device console_device_table[] = {
+  {

[PATCH v2 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..26d88ea 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,7 +34,7 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
+The ARMv5 and later instruction sets have the count leading zeroes ``clz`` 
instruction which
 could be used to speed up the find first bit operation.  The use of this
 instruction should significantly speed up the scheduling associated with a
 thread blocking.  This is currently not used.
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -196,11 +196,11 @@ Symmetric Multiprocessing
 
 SMP is supported on ARMv7-A.  Available platforms are
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v2 6/8] score: Add AArch64 port

[Kinsey Moore]

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   4 +-
 .../cpu/aarch64/aarch64-context-validate.S| 305 ++
 .../aarch64-context-volatile-clobber.S| 100 
 .../cpu/aarch64/aarch64-exception-default.S   | 418 +
 .../cpu/aarch64/aarch64-exception-default.c   |  50 ++
 .../aarch64/aarch64-exception-frame-print.c   | 108 
 .../cpu/aarch64/aarch64-exception-interrupt.S | 317 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  48 ++
 cpukit/score/cpu/aarch64/cpu.c| 196 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 100 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  89 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  83 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 549 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  42 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  83 +++
 spec/build/cpukit/cpuaarch64.yml  |  35 ++
 spec/build/cpukit/librtemscpu.yml |   2 +
 18 files changed, 2662 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..66961f0083 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,9 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+/* gcc under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS
+ * data segment and indexes into it accordingly for TLS variable addresses */
+#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8)
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..31c8d5571c
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief Implementation of _CPU_Context_validate
+ *
+ * This file implements _CPU_Context_validate for use in spcontext01.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+

RE: [PATCH v2 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

It was already an odd hybrid of a marked up list and a grammatical list that I 
noticed while I was working on the AArch64 documentation. I figured I'd push it 
one way or the other since mixing the constructs looks weird, but I can drop 
the changes unrelated to AArch64 if you prefer.

Kinsey

-Original Message-
From: Sebastian Huber  
Sent: Monday, September 28, 2020 23:36
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 1/2] cpu-supplement: Fix formatting and missing words

On 28/09/2020 17:25, Kinsey Moore wrote:

> @@ -196,11 +196,11 @@ Symmetric Multiprocessing
>   
>   SMP is supported on ARMv7-A.  Available platforms are
>   
> -- Altera Cyclone V,
> +- Altera Cyclone V
>   
> -- NXP i.MX 7, and
> +- NXP i.MX 7
>   
> -- Xilinx Zynq.
> +- Xilinx Zynq

What is the reason for this change?


If you change the formatting like this, then it should be

"Available platforms are:"

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RE: [PATCH v2 2/2] Add AArch64 documentation

[Kinsey Moore]

There are some rudimentary pieces of SMP support in the port itself, but it is 
certainly not complete and is untested. That work is planned for the next phase 
of development at which point I'll update the BSPs to support that as well if 
they require any changes at all.

Kinsey

-Original Message-
From: Sebastian Huber  
Sent: Monday, September 28, 2020 23:40
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 2/2] Add AArch64 documentation

On 28/09/2020 17:25, Kinsey Moore wrote:

> +Symmetric Multiprocessing
> +=
> +
> +SMP is not currently supported on ARMv8-A.
Is this a limitation of the CPU port or just a missing BSP support?
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RE: [PATCH v2 1/8] Move ARM PL011 UART driver

[Kinsey Moore]

I'll include this change in the next version of the patch.

Kinsey

-Original Message-
From: Sebastian Huber  
Sent: Tuesday, September 29, 2020 05:59
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 1/8] Move ARM PL011 UART driver

On 28/09/2020 17:24, Kinsey Moore wrote:

> This UART driver is now needed for BSPs other than ARM.
> ---
>   bsps/arm/headers.am| 2 --
>   bsps/arm/raspberrypi/console/console-config.c  | 2 +-
>   bsps/arm/realview-pbx-a9/include/bsp/console.h | 2 +-
>   bsps/arm/xen/console/console.c | 2 +-
>   bsps/headers.am| 2 ++
>   bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h | 0
>   bsps/{arm/include/bsp => include/libchip}/arm-pl011.h  | 2 +-

For me this libchip inline stuff is a legacy thing. If you really want to 
change the include path, then I suggest to move the serial driver header files 
to:

bsps/shared/include/dev/serial

This is in line with cpukit/include/dev/serial and the source location 
bsps/shared/dev/serial.

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RE: [PATCH v2 2/8] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Tuesday, September 29, 2020 06:09
To: Kinsey Moore ; RTEMS 
Subject: Re: [PATCH v2 2/8] spec: Add missing spintrcritical24 definition

On 28/09/2020 17:24, Kinsey Moore wrote:

> ---
>   spec/build/bsps/tstnointrcrit.yml | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/spec/build/bsps/tstnointrcrit.yml 
> b/spec/build/bsps/tstnointrcrit.yml
> index 0460aaabb3..46f7d974c8 100644
> --- a/spec/build/bsps/tstnointrcrit.yml
> +++ b/spec/build/bsps/tstnointrcrit.yml
> @@ -24,6 +24,7 @@ actions:
>   spintrcritical21: exclude
>   spintrcritical22: exclude
>   spintrcritical23: exclude
> +spintrcritical24: exclude
>   build-type: option
>   copyrights:
>   - Copyright (C) 2020 embedded brains GmbH 
> (http://www.embedded-brains.de)

I changed the test support for critical sections recently. Now, this test 
framework part is used:

https://docs.rtems.org/branches/master/eng/test-framework.html#interrupt-tests

Could you please run the spintrcritical* tests also on the new port. My 
intention was to be able to run these tests on Qemu.

[] 
I'll make sure these are working before I push the next patch version.

Kinsey
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RE: [PATCH v2 3/8] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Tuesday, September 29, 2020 06:22
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 3/8] bsps: Break out AArch32 portions of GPT driver

On 28/09/2020 17:24, Kinsey Moore wrote:

>   create mode 100644 bsps/include/bsp/clock-arm-generic-timer.h
>   rename bsps/{arm/shared/clock/clock-generic-timer.c => 
> shared/clock/clock-arm-generic-timer.c} (71%)

I would add it as:

bsps/shared/dev/clock/arm-generic-timer.c

bsps/include/dev/clock/arm-generic-timer.h

[] 
Your comment on the pl011 adjustments specified bsps/shared/include/dev while 
this comment mentions bsps/include/dev. Which is the preferred location?

Kinsey
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RE: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Tuesday, September 29, 2020 06:49
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

On 28/09/2020 17:24, Kinsey Moore wrote:

> diff --git a/bsps/aarch64/shared/start/linkcmds.base 
> b/bsps/aarch64/shared/start/linkcmds.base
> new file mode 100644
> index 00..f67404ab62
> --- /dev/null
> +++ b/bsps/aarch64/shared/start/linkcmds.base
> @@ -0,0 +1,450 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +
> +/**
> + * @file
> + *
> + * @ingroup bsp_linker
> + *
> + * @brief Linker command base file.
> + */
> +
> +/*
> + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
> + * Written by Kinsey Moore
This looks like a modified copy of bsps/arm/shared/start/linkcmds.base. 
Are there significant differences or could we share this linker script on arm 
and aarch64?
[] 
They are similar and could probably share large sections, but a single base 
linker script is not shareable between arm and aarch64 due to aarch64 multilibs 
needing different OUTPUT_FORMAT and OUTPUT_ARCH directives as well as having 
differing setups for their various respective exception stacks.

Kinsey
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RE: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Thursday, October 1, 2020 00:05
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

On 30/09/2020 22:04, Kinsey Moore wrote:
> -Original Message-
> From: Sebastian Huber
> Sent: Tuesday, September 29, 2020 06:49
> To: Kinsey Moore;devel@rtems.org
> Subject: Re: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP
> 
> On 28/09/2020 17:24, Kinsey Moore wrote:
> 
>> diff --git a/bsps/aarch64/shared/start/linkcmds.base
>> b/bsps/aarch64/shared/start/linkcmds.base
>> new file mode 100644
>> index 00..f67404ab62
>> --- /dev/null
>> +++ b/bsps/aarch64/shared/start/linkcmds.base
>> @@ -0,0 +1,450 @@
>> +/* SPDX-License-Identifier: BSD-2-Clause */
>> +
>> +/**
>> + * @file
>> + *
>> + * @ingroup bsp_linker
>> + *
>> + * @brief Linker command base file.
>> + */
>> +
>> +/*
>> + * Copyright (C) 2020 On-Line Applications Research Corporation 
>> +(OAR)
>> + * Written by Kinsey Moore
> This looks like a modified copy of bsps/arm/shared/start/linkcmds.base.
> Are there significant differences or could we share this linker script on arm 
> and aarch64?
> []
> They are similar and could probably share large sections, but a single base 
> linker script is not shareable between arm and aarch64 due to aarch64 
> multilibs needing different OUTPUT_FORMAT and OUTPUT_ARCH directives as well 
> as having differing setups for their various respective exception stacks.

Can't this be solved via an INCLUDE similar to linkcmds.armv4 and 
linkcmds.armv7m?

[] 
If 32-bit ARM isn't broken by having the extra SUBALIGN(4) here and there, then 
they can share a single base include. Otherwise, it will have to be 3 or 4 
different includes. I'll have to setup a test environment to see if one of the 
ARM QEMU BSPs is affected.

Kinsey
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[PATCH v3 02/10] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

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[PATCH v3 03/10] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  4 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  3 +-
 .../shared/clock/arm-generic-timer-aarch32.c  | 76 +++
 bsps/arm/xen/headers.am   |  4 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  3 +-
 bsps/arm/xilinx-zynqmp/headers.am |  4 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  3 +-
 bsps/include/dev/clock/arm-generic-timer.h| 76 +++
 .../dev/clock/arm-generic-timer.c}| 65 
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  6 +-
 spec/build/bsps/arm/xen/bspxen.yml|  6 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  6 +-
 18 files changed, 205 insertions(+), 66 deletions(-)
 create mode 100644 bsps/arm/shared/clock/arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/dev/clock/arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/dev/clock/arm-generic-timer.c} (71%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..9863f34300 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,7 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+
+include_dev_clockdir = $(includedir)/dev/clock
+include_dev_clock_HEADERS =
+include_dev_clock_HEADERS += 
../../../../../../bsps/include/dev/clock/arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..ff4b204790 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -58,7 +59,7 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return intr[1] + MAGIC_IRQ_OFFSET;
 }
 
-void arm_generic_timer_get_config(
+void aarch_generic_timer_get_config(
   uint32_t *frequency,
   uint32_t *irq
 )
diff --git a/bsps/arm/shared/clock/arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
new file mode 100644
index 00..8ce65ee5ad
--- /dev/null
+++ b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific clock driver functions.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t aarch_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRT

[PATCH v3 01/10] Move ARM PL011 UART driver

[Kinsey Moore]

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am  | 2 --
 bsps/arm/raspberrypi/console/console-config.c| 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h   | 2 +-
 bsps/arm/xen/console/console.c   | 2 +-
 bsps/headers.am  | 5 +
 .../{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c   | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am | 2 +-
 spec/build/bsps/arm/grp.yml  | 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml  | 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml | 1 -
 spec/build/bsps/arm/xen/bspxen.yml   | 1 -
 spec/build/bsps/obj.yml  | 5 +
 16 files changed, 18 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..6b8eb80aa4 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..2019fc2509 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..05eceae438 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..aaf13284bd 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,11 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HEADERS += ../../bsps/include/bsp/utility.h
 
+include_dev_serialdir = $(includedir)/dev/serial
+include_dev_serial_HEADERS =
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011-regs.h
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h
+
 include_grlibdir = $(includedir)/grlib
 include_grlib_HEADERS =
 include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/dev/serial/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/dev/serial/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h 
b/bsps/include/dev/serial/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/dev/serial/arm-pl011.h
index 49ff413581..c7e65656a3 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/dev/serial/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..c3cbab6f3e 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ b/bsps/shared/dev/serial/arm-pl011

[PATCH v3 04/10] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

644
--- a/bsps/arm/realview-pbx-a9/include/tm27.h
+++ b/bsps/arm/realview-pbx-a9/include/tm27.h
@@ -36,6 +36,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
new file mode 100644
index 00..2a86201208
--- /dev/null
+++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific IRQ handlers.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+void aarch_interrupt_handler_dispatch(rtems_vector_number vector)
+{
+  uint32_t psr = _ARMV4_Status_irq_enable();
+  bsp_interrupt_handler_dispatch(vector);
+
+  _ARMV4_Status_restore(psr);
+}
+
+void aarch_interrupt_facility_set_exception_handler(void)
+{
+  arm_cp15_set_exception_handler(
+ARM_EXCEPTION_IRQ,
+_ARMV4_Exception_interrupt
+  );
+}
+
+void bsp_interrupt_dispatch(void)
+{
+  gicv3_interrupt_dispatch();
+}
diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/arm/shared/irq/irq-gic.c
index 42ae6c4d7d..1a401b67b6 100644
--- a/bsps/arm/shared/irq/irq-gic.c
+++ b/bsps/arm/shared/irq/irq-gic.c
@@ -12,7 +12,7 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#include 
+#include 
 
 #include 
 
diff --git a/bsps/arm/xen/include/bsp/irq.h b/bsps/arm/xen/include/bsp/irq.h
index dc09e52373..a147a1c079 100644
--- a/bsps/arm/xen/include/bsp/irq.h
+++ b/bsps/arm/xen/include/bsp/irq.h
@@ -34,7 +34,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/include/tm27.h b/bsps/arm/xen/include/tm27.h
index 2fc4afa4f2..4c1dfaa213 100644
--- a/bsps/arm/xen/include/tm27.h
+++ b/bsps/arm/xen/include/tm27.h
@@ -33,6 +33,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h 
b/bsps/arm/xilinx-zynq/include/bsp/irq.h
index edea29b7df..e707337fa1 100644
--- a/bsps/arm/xilinx-zynq/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h
@@ -40,7 +40,7 @@
 #include 
 
 #include 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynq/include/tm27.h 
b/bsps/arm/xilinx-zynq/include/tm27.h
index 885b97a30c..7fc8dd7edd 100644
--- a/bsps/arm/xilinx-zynq/include/tm27.h
+++ b/bsps/arm/xilinx-zynq/include/tm27.h
@@ -44,6 +44,6 @@
  * @brief Interrupt Mechanisms for tm27 test
  */
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h 
b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
index 73567da011..6496d2312e 100644
--- a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynqmp/include/tm27.h 
b/bsps/arm/xilinx-zynqmp/include/tm27.h
index 0f02a3b195..14214fe151 100644
--- a/bsps/arm/xilinx-zynqmp/include/tm27.h
+++ b/bsps/arm/xilinx-zynqmp/include/tm27.h
@@ -49,6 +49,6 @@
  * @brief Interrupt Mechanisms for tm27 test
  */
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/headers.am b/bsps/headers.am
index aaf13284bd..b433c2d8d4 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,13 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HE

[PATCH v3 06/10] bsps/arm: Break out linker script for AArch64

[Kinsey Moore]

. += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.);
-   bsp_section_work_end = .;
-   } > REGION_WORK AT > REGION_WORK
-   bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin;
-
-   .stack : ALIGN_WITH_INPUT {
-   /*
-* The stack section will occupy the remaining REGION_STACK 
region and may
-* contain the task stacks.  Depending on the region 
distribution this
-* section may be of zero size.
-*/
-   bsp_section_stack_begin = .;
-   . += ORIGIN (REGION_STACK) + LENGTH (REGION_STACK) - ABSOLUTE 
(.);
-   bsp_section_stack_end = .;
-   } > REGION_STACK AT > REGION_STACK
-   bsp_section_stack_size = bsp_section_stack_end - 
bsp_section_stack_begin;
-
-   .nocache : ALIGN_WITH_INPUT {
-   bsp_section_nocache_begin = .;
-   *(SORT_BY_ALIGNMENT (SORT_BY_NAME (.bsp_nocache*)))
-   bsp_section_nocache_end = .;
-   } > REGION_NOCACHE AT > REGION_NOCACHE_LOAD
-   bsp_section_nocache_size = bsp_section_nocache_end - 
bsp_section_nocache_begin;
-   bsp_section_nocache_load_begin = LOADADDR (.nocache);
-   bsp_section_nocache_load_end = bsp_section_nocache_load_begin + 
bsp_section_nocache_size;
-
-   .nocachenoload (NOLOAD) : ALIGN_WITH_INPUT {
-   bsp_section_nocachenoload_begin = .;
-   *(SORT_BY_ALIGNMENT (SORT_BY_NAME (.bsp_noload_nocache*)))
-   bsp_section_nocacheheap_begin = .;
-   . += ORIGIN (REGION_NOCACHE) + LENGTH (REGION_NOCACHE) - 
ABSOLUTE (.);
-   bsp_section_nocacheheap_end = .;
-   bsp_section_nocachenoload_end = .;
-   } > REGION_NOCACHE AT > REGION_NOCACHE
-   bsp_section_nocacheheap_size = bsp_section_nocacheheap_end - 
bsp_section_nocacheheap_begin;
-   bsp_section_nocachenoload_size = bsp_section_nocachenoload_end - 
bsp_section_nocachenoload_begin;
-
-   /* FIXME */
-   RamBase = ORIGIN (REGION_WORK);
-   RamSize = LENGTH (REGION_WORK);
-   RamEnd = RamBase + RamSize;
-   WorkAreaBase = bsp_section_work_begin;
-   HeapSize = 0;
-
-   /* Stabs debugging sections.  */
-   .stab  0 : { *(.stab) }
-   .stabstr   0 : { *(.stabstr) }
-   .stab.excl 0 : { *(.stab.excl) }
-   .stab.exclstr  0 : { *(.stab.exclstr) }
-   .stab.index0 : { *(.stab.index) }
-   .stab.indexstr 0 : { *(.stab.indexstr) }
-   .comment   0 : { *(.comment) }
-   /* DWARF debug sections.
-  Symbols in the DWARF debugging sections are relative to the beginning
-  of the section so we begin them at 0.  */
-   /* DWARF 1 */
-   .debug  0 : { *(.debug) }
-   .line   0 : { *(.line) }
-   /* GNU DWARF 1 extensions */
-   .debug_srcinfo  0 : { *(.debug_srcinfo) }
-   .debug_sfnames  0 : { *(.debug_sfnames) }
-   /* DWARF 1.1 and DWARF 2 */
-   .debug_aranges  0 : { *(.debug_aranges) }
-   .debug_pubnames 0 : { *(.debug_pubnames) }
-   /* DWARF 2 */
-   .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
-   .debug_abbrev   0 : { *(.debug_abbrev) }
-   .debug_line 0 : { *(.debug_line) }
-   .debug_frame0 : { *(.debug_frame) }
-   .debug_str  0 : { *(.debug_str) }
-   .debug_loc  0 : { *(.debug_loc) }
-   .debug_macinfo  0 : { *(.debug_macinfo) }
-   /* SGI/MIPS DWARF 2 extensions */
-   .debug_weaknames 0 : { *(.debug_weaknames) }
-   .debug_funcnames 0 : { *(.debug_funcnames) }
-   .debug_typenames 0 : { *(.debug_typenames) }
-   .debug_varnames  0 : { *(.debug_varnames) }
-   /* DWARF 3 */
-   .debug_pubtypes 0 : { *(.debug_pubtypes) }
-   .debug_ranges   0 : { *(.debug_ranges) }
-   /* DWARF extension */
-   .debug_macro0 : { *(.debug_macro) }
-   .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP 
(*(.gnu.attributes)) }
-   .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
-   /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
-
-   /*
-* This is a RTEMS specific section to catch all unexpected input
-* sections.  In case you get an error like
-*   "section `.unexpected_sections' will not fit in region
-*   `UNEXPECTED_SECTIONS'"
-* you have to figure out the offending input section and add it to the
-* appropriate output section definition above.
-*/
-   .unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS
-}
+INCLUDE linkcmds-aarch.base
diff --git a/bsps/shared/start/linkcmds-aarch.base 
b/bsps/shared/start/linkcmds-aarch.base
new file mode 100644
index 00..e69461a434
--- /dev/null
+++ b/bsps/shared/start/linkcmds-aarch.base
@@ -0,0 +1,420 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @

[PATCH v3 08/10] score: Add AArch64 port

[Kinsey Moore]

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   6 +-
 .../cpu/aarch64/aarch64-context-validate.S| 305 ++
 .../aarch64-context-volatile-clobber.S| 100 
 .../cpu/aarch64/aarch64-exception-default.S   | 490 
 .../cpu/aarch64/aarch64-exception-default.c   |  50 ++
 .../aarch64/aarch64-exception-frame-print.c   | 108 
 .../cpu/aarch64/aarch64-exception-interrupt.S | 322 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  47 ++
 cpukit/score/cpu/aarch64/cpu.c| 197 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 100 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  89 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  83 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 554 ++
 .../cpu/aarch64/include/rtems/score/cpu_irq.h |  50 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  42 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  83 +++
 spec/build/cpukit/cpuaarch64.yml  |  36 ++
 spec/build/cpukit/librtemscpu.yml |   2 +
 19 files changed, 2797 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu_irq.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..57063990e7 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,11 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+/*
+ * GCC under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS
+ * data segment and indexes into it accordingly for TLS variable addresses.
+ */
+#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8)
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..31c8d5571c
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief Implementation of _CPU_Context_validate
+ *
+ * This file implements _CPU_Context_validate for use in spcontext01.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWAR

[PATCH v3 05/10] bsps/shared: Add PSCI-based bspreset implementation

[Kinsey Moore]

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-arm-psci.c | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-arm-psci.c

diff --git a/bsps/shared/start/bspreset-arm-psci.c 
b/bsps/shared/start/bspreset-arm-psci.c
new file mode 100644
index 00..215be5c9b5
--- /dev/null
+++ b/bsps/shared/start/bspreset-arm-psci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP reset hook.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

[PATCH v3 10/10] bsps: Add Cortex-A53 ILP32 BSP variant

[Kinsey Moore]

This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
---
 bsps/aarch64/shared/start/start.S | 16 +
 spec/build/bsps/aarch64/a53/abi.yml   |  7 +-
 .../bsps/aarch64/a53/bspa53ilp32qemu.yml  | 19 +
 .../build/bsps/aarch64/a53/linkcmds_ilp32.yml | 71 +++
 4 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml

diff --git a/bsps/aarch64/shared/start/start.S 
b/bsps/aarch64/shared/start/start.S
index f60e840137..f4c62b2b6c 100644
--- a/bsps/aarch64/shared/start/start.S
+++ b/bsps/aarch64/shared/start/start.S
@@ -101,19 +101,31 @@ _start:
  * Get current per-CPU control and store it in PL1 only Thread ID
  * Register (TPIDRPRW).
  */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_Per_CPU_Information
+#else
ldr x1, =_Per_CPU_Information
+#endif
add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
mcr p15, 0, x1, c13, c0, 4
 
 #endif
 
/* Calculate interrupt stack area end for current processor */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_ISR_Stack_size
+#else
ldr x1, =_ISR_Stack_size
+#endif
 #ifdef RTEMS_SMP
add x3, x7, #1
mul x1, x1, x3
 #endif
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w2, =_ISR_Stack_area_begin
+#else
ldr x2, =_ISR_Stack_area_begin
+#endif
add x3, x1, x2
 
/* Save original DAIF value */
@@ -135,7 +147,11 @@ _start:
 * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) 
uses SP0
*/
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =bsp_stack_exception_size
+#else
ldr x1, =bsp_stack_exception_size
+#endif
/* Switch to SP0 and set exception stack */
msr spsel, #0
mov sp, x3
diff --git a/spec/build/bsps/aarch64/a53/abi.yml 
b/spec/build/bsps/aarch64/a53/abi.yml
index 894839aa24..b65c10981e 100644
--- a/spec/build/bsps/aarch64/a53/abi.yml
+++ b/spec/build/bsps/aarch64/a53/abi.yml
@@ -8,7 +8,12 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - -mcpu=cortex-a53
-default-by-variant: []
+default-by-variant:
+- value:
+  - -mcpu=cortex-a53
+  - -mabi=ilp32
+  variants:
+  - aarch64/a53_ilp32_qemu
 enabled-by: true
 links: []
 name: ABI_FLAGS
diff --git a/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
new file mode 100644
index 00..019e97fcb3
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: aarch64
+bsp: a53_ilp32_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+cppflags: []
+enabled-by: true
+family: a53
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds_ilp32
+source: []
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..ed585f1950
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,71 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDIN

[PATCH v3 09/10] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  69 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  67 ++
 bsps/aarch64/a53/include/tm27.h   |  46 ++
 bsps/aarch64/a53/start/bspstart.c |  49 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  50 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 616 ++
 .../shared/clock/arm-generic-timer-aarch64.c  | 110 
 .../shared/irq/irq-arm-gicv3-aarch64.c|  64 ++
 bsps/aarch64/shared/start/linkcmds.base   |  46 ++
 bsps/aarch64/shared/start/start.S | 219 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  17 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  19 +
 spec/build/bsps/aarch64/a53/grp.yml   |  42 ++
 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml |  71 ++
 spec/build/bsps/aarch64/a53/obj.yml   |  37 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  18 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramori.yml |  18 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  44 ++
 spec/build/bsps/aarch64/grp.yml   |  25 +
 spec/build/bsps/aarch64/start.yml |  14 +
 25 files changed, 2101 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/grp.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
 create mode 100644 spec/build/bsps/aarch64/a53/obj.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/grp.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..1854909c98
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64A53
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_conte

[PATCH v3 07/10] spmsgq_err01: Use correct max values and fix 64bit

[Kinsey Moore]

Fix spmsgq_err01 on systems with 64-bit pointers and correct max value
mismatches and inaccuracies that are more noticable on 64-bit systems.
---
 testsuites/sptests/spmsgq_err01/init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/testsuites/sptests/spmsgq_err01/init.c 
b/testsuites/sptests/spmsgq_err01/init.c
index c68d30da16..9a6a8855be 100644
--- a/testsuites/sptests/spmsgq_err01/init.c
+++ b/testsuites/sptests/spmsgq_err01/init.c
@@ -101,7 +101,7 @@ rtems_task Init(
   /* not enough memory for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-SIZE_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
+UINT_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
 1,
 RTEMS_DEFAULT_ATTRIBUTES,
 &Queue_id[ 1 ]
@@ -116,8 +116,8 @@ rtems_task Init(
   /* too large a request for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-INT_MAX,
-INT_MAX,
+UINT_MAX,
+SIZE_MAX - sizeof( uintptr_t ) + 1 - sizeof( CORE_message_queue_Buffer ),
 RTEMS_DEFAULT_ATTRIBUTES,
 &Queue_id[ 1 ]
   );
-- 
2.20.1

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[PATCH v3 2/2] Add AArch64 documentation

[Kinsey Moore]

r the LP64
+multilib variant, the the TCB is 16 bytes in size instead of 8 bytes.
diff --git a/user/bsps/aarch64/a53.rst b/user/bsps/aarch64/a53.rst
new file mode 100644
index 000..0052773
--- /dev/null
+++ b/user/bsps/aarch64/a53.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 2020 Kinsey Moore, On-Line Applications Research Corporation 
(OAR)
+
+.. _BSP_aarch64_qemu_a53_ilp32:
+.. _BSP_aarch64_qemu_a53_lp64:
+
+Qemu A53
+
+
+This BSP supports two variants, `qemu_a53_ilp32` and `qemu-a53_lp64`. The basic
+hardware initialization is performed by the BSP.
+
+Boot via ELF
+
+The executable image is booted by Qemu in ELF format.
+
+Clock Driver
+
+
+The clock driver uses the `ARM Generic Timer`.
+
+Console Driver
+--
+
+The console driver supports the default Qemu emulated ARM PL011 PrimeCell UART.
diff --git a/user/bsps/bsps-aarch64.rst b/user/bsps/bsps-aarch64.rst
index 4b2e749..319310e 100644
--- a/user/bsps/bsps-aarch64.rst
+++ b/user/bsps/bsps-aarch64.rst
@@ -5,4 +5,4 @@
 aarch64 (AArch64)
 *
 
-There are no AArch64 BSPs yet.
+.. include:: aarch64/a53.rst
-- 
2.20.1

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[PATCH v3 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..ac9e8c6 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,10 +34,10 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
-could be used to speed up the find first bit operation.  The use of this
-instruction should significantly speed up the scheduling associated with a
-thread blocking.  This is currently not used.
+The ARMv5 and later instruction sets have the count leading zeroes ``clz``
+instruction which could be used to speed up the find first bit operation. The
+use of this instruction should significantly speed up the scheduling associated
+with a thread blocking.  This is currently not used.
 
 Floating Point Unit
 ---
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -194,13 +194,13 @@ actions:
 Symmetric Multiprocessing
 =
 
-SMP is supported on ARMv7-A.  Available platforms are
+SMP is supported on ARMv7-A.  Available platforms are:
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v4 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..ac9e8c6 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,10 +34,10 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
-could be used to speed up the find first bit operation.  The use of this
-instruction should significantly speed up the scheduling associated with a
-thread blocking.  This is currently not used.
+The ARMv5 and later instruction sets have the count leading zeroes ``clz``
+instruction which could be used to speed up the find first bit operation. The
+use of this instruction should significantly speed up the scheduling associated
+with a thread blocking.  This is currently not used.
 
 Floating Point Unit
 ---
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -194,13 +194,13 @@ actions:
 Symmetric Multiprocessing
 =
 
-SMP is supported on ARMv7-A.  Available platforms are
+SMP is supported on ARMv7-A.  Available platforms are:
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v4 2/2] Add AArch64 documentation

[Kinsey Moore]

---
 cpu-supplement/aarch64.rst | 134 +
 user/bsps/aarch64/a53.rst  |  26 +++
 user/bsps/bsps-aarch64.rst |   2 +-
 3 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 cpu-supplement/aarch64.rst
 create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..178ea10
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,134 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
+
+AArch64 Specific Information
+
+
+This chapter discusses the dependencies of the
+*ARM AArch64 architecture*
+(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
+of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
+use a static configuration which is set up during system start.  SMP is not
+supported.
+
+**Architecture Documents**
+
+For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
+(http://infocenter.arm.com/).
+
+CPU Model Dependent Features
+
+
+This section presents the set of features which vary across ARM AArch64
+implementations and are of importance to RTEMS.  The set of CPU model feature
+macros are defined in the file 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+based upon the particular CPU model flags specified on the compilation command
+line.
+
+CPU Model Name
+--
+
+The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
+level of this CPU model.  See in 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+for the values.
+
+Floating Point Unit and SIMD
+
+
+The Advanced SIMD (NEON) and Floating-point instruction set extension is
+supported and expected to be present since all ARMv8-A CPUs are expected to
+support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
+(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
+such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
+
+Multilibs
+=
+
+The following multilib variants are available:
+
+#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and 
pointers
+
+#. ``LP64``: AArch64 instruction set and registers using 64bit long int and 
pointers
+
+Use for example the following GCC options:
+
+.. code-block:: shell
+
+-mcpu=cortex-a53 -mabi=ilp32
+
+to build an application or BSP for the ARMv8-A architecture and tune the code
+for a Cortex-A53 processor.  It is important to select the correct ABI.
+
+Calling Conventions
+===
+
+Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
+(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
+
+Memory Model
+
+
+A flat 64-bit or 32-bit memory model is supported depending on the selected 
multilib
+variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
+for a flat memory model is handled.
+
+Interrupt Processing
+
+
+The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
+configuration signals only sampled at reset.  The ARMv8 architecture has four
+exception types: 
+
+- Synchronous Exception
+
+- Interrupt (IRQ)
+
+- Fast Interrupt (FIQ)
+
+- System Error Exception
+
+Of these types only the synchronous and IRQ exceptions have explicit operating
+system support.  It is intentional that the FIQ is not supported by the 
operating
+system.  Without operating system support for the FIQ it is not necessary to
+disable them during critical sections of the system.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
+zero corresponds to interrupts enabled.  Level one corresponds to interrupts
+disabled.
+
+Interrupt Stack
+---
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+Default Fatal Error Processing
+==
+
+The default fatal error handler for this architecture performs the following
+actions:
+
+- disables operating system supported interrupts (IRQ),
+
+- places the error code in ``x0``, and
+
+- executes an infinite loop to simulate a halt processor instruction.
+
+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.
+
+Thread-Local Storage
+
+
+Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I
+which is not explcitly stated, but can be inferred from the behavior of GCC and
+*Addenda to, and Errata in, the ABI for the Arm® Architecture*
+(https://developer.arm.com/documentation/ihi0045/g). This alters expectations
+for the size of the TLS Thread Control Block (TCB) such that, under the LP64

RE: [PATCH v3 06/10] bsps/arm: Break out linker script for AArch64

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Monday, October 5, 2020 02:11
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v3 06/10] bsps/arm: Break out linker script for AArch64

On 04/10/2020 06:18, Kinsey Moore wrote:

> This breaks out the common section of the ARM linker script that is 
> usable by AArch64 BSPs to avoid duplication of the vast majority. To 
> do so, it was necessary to add a new linker path at bsps/shared/start.
Sorry, I didn't consider that using a linker script shared by different 
architectures requires a new library path in the build. I think in this case I 
would prefer a copy and paste linkcmds.base. One for arm and one for aarch64.
[] 
Oh well, on the plus side, undoing this change will be much more trivial than 
doing/testing it was in the first place.

Kinsey
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RE: [PATCH v3 2/2] Add AArch64 documentation

[Kinsey Moore]

-Original Message-
From: Gedare Bloom  
Sent: Monday, October 5, 2020 10:19
To: Kinsey Moore 
Cc: devel@rtems.org
Subject: Re: [PATCH v3 2/2] Add AArch64 documentation

On Mon, Oct 5, 2020 at 9:13 AM Gedare Bloom  wrote:
>
> On Sat, Oct 3, 2020 at 10:23 PM Kinsey Moore  wrote:
> >
> > ---
> >  cpu-supplement/aarch64.rst | 134 
> > +
> >  user/bsps/aarch64/a53.rst  |  26 +++
> >  user/bsps/bsps-aarch64.rst |   2 +-
> >  3 files changed, 161 insertions(+), 1 deletion(-)  create mode 
> > 100644 cpu-supplement/aarch64.rst  create mode 100644 
> > user/bsps/aarch64/a53.rst
> >
> > diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst 
> > new file mode 100644 index 000..178ea10
> > --- /dev/null
> > +++ b/cpu-supplement/aarch64.rst
> > @@ -0,0 +1,134 @@
> > +.. SPDX-License-Identifier: CC-BY-SA-4.0
> > +
> > +.. Copyright (C) 1988, 2020 On-Line Applications Research 
> > +Corporation (OAR)
> > +
> > +AArch64 Specific Information
> > +
> > +
> > +This chapter discusses the dependencies of the *ARM AArch64 
> > +architecture*
> > +(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) 
> > +in this port of RTEMS.  The ARMv8-A versions are supported by 
> > +RTEMS.  Processors with a MMU use a static configuration which is 
> > +set up during system start.  SMP is not supported.
> > +
> > +**Architecture Documents**
> > +
> > +For information on the ARM AArch64 architecture refer to the *ARM 
> > +Infocenter* (http://infocenter.arm.com/).
> > +
> > +CPU Model Dependent Features
> > +
> > +
> > +This section presents the set of features which vary across ARM 
> > +AArch64 implementations and are of importance to RTEMS.  The set of 
> > +CPU model feature macros are defined in the file 
> > +:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
> > +based upon the particular CPU model flags specified on the 
> > +compilation command line.
> > +
> > +CPU Model Name
> > +--
> > +
> > +The macro ``CPU_MODEL_NAME`` is a string which designates the 
> > +architectural level of this CPU model.  See in 
> > +:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
> > +for the values.
> > +
> > +Floating Point Unit and SIMD
> > +
> > +
> > +The Advanced SIMD (NEON) and Floating-point instruction set 
> > +extension is supported and expected to be present since all ARMv8-A 
> > +CPUs are expected to support it as per the *ARMv8-A Programmer's 
> > +Guide Chapter 7 introduction* 
> > +(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon).
> >  As such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
> > +
> > +Multilibs
> > +=
> > +
> > +The following multilib variants are available:
> > +
> > +#. ``ILP32``: AArch64 instruction set and registers using 32bit 
> > +long int and pointers
> > +
> > +#. ``LP64``: AArch64 instruction set and registers using 64bit long 
> > +int and pointers
> > +
> > +Use for example the following GCC options:
> > +
> > +.. code-block:: shell
> > +
> > +-mcpu=cortex-a53 -mabi=ilp32
> > +
> > +to build an application or BSP for the ARMv8-A architecture and 
> > +tune the code for a Cortex-A53 processor.  It is important to select the 
> > correct ABI.
> > +
> > +Calling Conventions
> > +===
> > +
> > +Please refer to the *Procedure Call Standard for the ARM 64-bit 
> > +Architecture* 
> > (https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
> > +
> > +Memory Model
> > +
> > +
> > +A flat 64-bit or 32-bit memory model is supported depending on the 
> > +selected multilib variant.  All AArch64 CPU variants support a 
> > +built-in MMU for which basic initialization for a flat memory model is 
> > handled.
> > +
> > +Interrupt Processing
> > +
> > +
> > +The Reset Vector is determined using RVBAR and is Read-Only. RVBAR 
> > +is set using configuration signals only sampled at reset.  The 
> > +ARMv8 architecture has four exception types:
> > +
> > +- Synchronous Exception
> > +
> > +- Interrupt (IRQ)
> > +
> > +- Fast Interrupt (FIQ)
> > +
> > +- System Error Exception
> > +
> > +Of these types only the synchronous and IRQ e

RE: [PATCH v3 04/10] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Monday, October 5, 2020 08:10
To: j...@rtems.org
Cc: Kinsey Moore ; rtems-de...@rtems.org 

Subject: Re: [PATCH v3 04/10] bsps: Break out AArch32 GICv3 support

On 05/10/2020 14:27, Joel Sherrill wrote:

>
>
> On Mon, Oct 5, 2020 at 2:04 AM Sebastian Huber 
>  <mailto:sebastian.hu...@embedded-brains.de>> wrote:
>
> On 04/10/2020 06:18, Kinsey Moore wrote:
>
> > +/**
> > + * This architecture-specific function sets the exception
> vector for handling
> > + * IRQs.
> > + */
> > +void aarch_interrupt_facility_set_exception_handler(void);
> What are the rules for using an aarch prefix instead of an arm prefix?
>
>
> I haven't talked to Kinsey about this but I would assume based on the 
> terminology I see in ARM documentation.
>
> + arm - only 32-bit. Now referred to as aarch32 or A32
> + aarch64 - only 64-bit. AKA A64
> + aarch - shared across 32 and 64 bit modes.
>
> Looks like Microsoft also uses ARM32 and ARM64
Linux uses "arm" and "arm64". You find some aarch32 stuff in "arch/arm64" but 
not in "arch/arm". I think we should do the same. 
Existing and shared stuff between "arm" and "aarch64" should just use "arm".
[] 
Joel was correct as to my reasoning behind using that prefix. It sounds like 
arm_ is the preferred prefix for shared code in that vein, so I'll swap the 
relevant patches over to that instead of aarch_.

Kinsey
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[PATCH v4 3/9] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  4 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  1 +
 .../shared/clock/arm-generic-timer-aarch32.c  | 76 +++
 bsps/arm/xen/headers.am   |  4 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  1 +
 bsps/arm/xilinx-zynqmp/headers.am |  4 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  1 +
 bsps/include/dev/clock/arm-generic-timer.h| 76 +++
 .../dev/clock/arm-generic-timer.c}| 43 +--
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  6 +-
 spec/build/bsps/arm/xen/bspxen.yml|  6 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  6 +-
 18 files changed, 191 insertions(+), 52 deletions(-)
 create mode 100644 bsps/arm/shared/clock/arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/dev/clock/arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/dev/clock/arm-generic-timer.c} (79%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..9863f34300 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,7 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+
+include_dev_clockdir = $(includedir)/dev/clock
+include_dev_clock_HEADERS =
+include_dev_clock_HEADERS += 
../../../../../../bsps/include/dev/clock/arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..9f610d1ff5 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
diff --git a/bsps/arm/shared/clock/arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
new file mode 100644
index 00..d242c116ac
--- /dev/null
+++ b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific clock driver functions.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t arm_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  return arm_cp15_get_counter_pl1_virtual_compare_value();
+#else
+  return arm_cp15_get_counter_pl1_physical_compare_value();
+#endif
+}
+
+void arm_gt_clock_set_compare_value(uint64_t cval)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  arm_cp15_set_counter_pl1_virtual_compa

[PATCH v4 9/9] bsps: Add Cortex-A53 ILP32 BSP variant

[Kinsey Moore]

This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
---
 bsps/aarch64/shared/start/start.S | 16 +
 spec/build/bsps/aarch64/a53/abi.yml   |  7 +-
 .../bsps/aarch64/a53/bspa53ilp32qemu.yml  | 19 +
 .../build/bsps/aarch64/a53/linkcmds_ilp32.yml | 71 +++
 4 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml

diff --git a/bsps/aarch64/shared/start/start.S 
b/bsps/aarch64/shared/start/start.S
index f60e840137..f4c62b2b6c 100644
--- a/bsps/aarch64/shared/start/start.S
+++ b/bsps/aarch64/shared/start/start.S
@@ -101,19 +101,31 @@ _start:
  * Get current per-CPU control and store it in PL1 only Thread ID
  * Register (TPIDRPRW).
  */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_Per_CPU_Information
+#else
ldr x1, =_Per_CPU_Information
+#endif
add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
mcr p15, 0, x1, c13, c0, 4
 
 #endif
 
/* Calculate interrupt stack area end for current processor */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_ISR_Stack_size
+#else
ldr x1, =_ISR_Stack_size
+#endif
 #ifdef RTEMS_SMP
add x3, x7, #1
mul x1, x1, x3
 #endif
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w2, =_ISR_Stack_area_begin
+#else
ldr x2, =_ISR_Stack_area_begin
+#endif
add x3, x1, x2
 
/* Save original DAIF value */
@@ -135,7 +147,11 @@ _start:
 * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) 
uses SP0
*/
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =bsp_stack_exception_size
+#else
ldr x1, =bsp_stack_exception_size
+#endif
/* Switch to SP0 and set exception stack */
msr spsel, #0
mov sp, x3
diff --git a/spec/build/bsps/aarch64/a53/abi.yml 
b/spec/build/bsps/aarch64/a53/abi.yml
index 894839aa24..b65c10981e 100644
--- a/spec/build/bsps/aarch64/a53/abi.yml
+++ b/spec/build/bsps/aarch64/a53/abi.yml
@@ -8,7 +8,12 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - -mcpu=cortex-a53
-default-by-variant: []
+default-by-variant:
+- value:
+  - -mcpu=cortex-a53
+  - -mabi=ilp32
+  variants:
+  - aarch64/a53_ilp32_qemu
 enabled-by: true
 links: []
 name: ABI_FLAGS
diff --git a/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
new file mode 100644
index 00..019e97fcb3
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: aarch64
+bsp: a53_ilp32_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+cppflags: []
+enabled-by: true
+family: a53
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds_ilp32
+source: []
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..ed585f1950
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,71 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDIN

[PATCH v4 1/9] Move ARM PL011 UART driver

[Kinsey Moore]

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am  | 2 --
 bsps/arm/raspberrypi/console/console-config.c| 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h   | 2 +-
 bsps/arm/xen/console/console.c   | 2 +-
 bsps/headers.am  | 5 +
 .../{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c   | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am | 2 +-
 spec/build/bsps/arm/grp.yml  | 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml  | 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml | 1 -
 spec/build/bsps/arm/xen/bspxen.yml   | 1 -
 spec/build/bsps/obj.yml  | 5 +
 16 files changed, 18 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..6b8eb80aa4 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..2019fc2509 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..05eceae438 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..aaf13284bd 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,11 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HEADERS += ../../bsps/include/bsp/utility.h
 
+include_dev_serialdir = $(includedir)/dev/serial
+include_dev_serial_HEADERS =
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011-regs.h
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h
+
 include_grlibdir = $(includedir)/grlib
 include_grlib_HEADERS =
 include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/dev/serial/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/dev/serial/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h 
b/bsps/include/dev/serial/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/dev/serial/arm-pl011.h
index 49ff413581..c7e65656a3 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/dev/serial/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..c3cbab6f3e 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ b/bsps/shared/dev/serial/arm-pl011

[PATCH v5 2/2] Add AArch64 documentation

[Kinsey Moore]

---
 cpu-supplement/aarch64.rst | 134 +
 user/bsps/aarch64/a53.rst  |  26 +++
 user/bsps/bsps-aarch64.rst |   2 +-
 3 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 cpu-supplement/aarch64.rst
 create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..b76895b
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,134 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
+
+AArch64 Specific Information
+
+
+This chapter discusses the dependencies of the
+*ARM AArch64 architecture*
+(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
+of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
+use a static configuration which is set up during system start.  SMP is not
+supported.
+
+**Architecture Documents**
+
+For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
+(http://infocenter.arm.com/).
+
+CPU Model Dependent Features
+
+
+This section presents the set of features which vary across ARM AArch64
+implementations and are of importance to RTEMS.  The set of CPU model feature
+macros are defined in the file 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+based upon the particular CPU model flags specified on the compilation command
+line.
+
+CPU Model Name
+--
+
+The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
+level of this CPU model.  See in 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+for the values.
+
+Floating Point Unit and SIMD
+
+
+The Advanced SIMD (NEON) and Floating-point instruction set extension is
+supported and expected to be present since all ARMv8-A CPUs are expected to
+support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
+(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
+such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
+
+Multilibs
+=
+
+The following multilib variants are available:
+
+#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and 
pointers
+
+#. ``LP64``: AArch64 instruction set and registers using 64bit long int and 
pointers
+
+Use for example the following GCC options:
+
+.. code-block:: shell
+
+-mcpu=cortex-a53 -mabi=ilp32
+
+to build an application or BSP for the ARMv8-A architecture and tune the code
+for a Cortex-A53 processor.  It is important to select the correct ABI.
+
+Calling Conventions
+===
+
+Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
+(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
+
+Memory Model
+
+
+A flat 64-bit or 32-bit memory model is supported depending on the selected 
multilib
+variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
+for a flat memory model is handled.
+
+Interrupt Processing
+
+
+The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
+configuration signals only sampled at reset.  The ARMv8 architecture has four
+exception types: 
+
+- Synchronous Exception
+
+- Interrupt (IRQ)
+
+- Fast Interrupt (FIQ)
+
+- System Error Exception
+
+Of these types only the synchronous and IRQ exceptions have explicit operating
+system support.  It is intentional that the FIQ is not supported by the 
operating
+system.  Without operating system support for the FIQ it is not necessary to
+disable them during critical sections of the system.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
+zero corresponds to interrupts enabled.  Level one corresponds to interrupts
+disabled.
+
+Interrupt Stack
+---
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+Default Fatal Error Processing
+==
+
+The default fatal error handler for this architecture performs the following
+actions:
+
+- disables operating system supported interrupts (IRQ),
+
+- places the error code in ``x0``, and
+
+- executes an infinite loop to simulate a halt processor instruction.
+
+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.
+
+Thread-Local Storage
+
+
+Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I
+which is not explcitly stated, but can be inferred from the behavior of GCC and
+*Addenda to, and Errata in, the ABI for the Arm® Architecture*
+(https://developer.arm.com/documentation/ihi0045/g). This alters expectations
+for the size of the TLS Thread Control Block (TCB) such that, under the LP64

[PATCH v4 4/9] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

644
--- a/bsps/arm/realview-pbx-a9/include/tm27.h
+++ b/bsps/arm/realview-pbx-a9/include/tm27.h
@@ -36,6 +36,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
new file mode 100644
index 00..b805199ba9
--- /dev/null
+++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific IRQ handlers.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+void arm_interrupt_handler_dispatch(rtems_vector_number vector)
+{
+  uint32_t psr = _ARMV4_Status_irq_enable();
+  bsp_interrupt_handler_dispatch(vector);
+
+  _ARMV4_Status_restore(psr);
+}
+
+void arm_interrupt_facility_set_exception_handler(void)
+{
+  arm_cp15_set_exception_handler(
+ARM_EXCEPTION_IRQ,
+_ARMV4_Exception_interrupt
+  );
+}
+
+void bsp_interrupt_dispatch(void)
+{
+  gicv3_interrupt_dispatch();
+}
diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/arm/shared/irq/irq-gic.c
index 42ae6c4d7d..1a401b67b6 100644
--- a/bsps/arm/shared/irq/irq-gic.c
+++ b/bsps/arm/shared/irq/irq-gic.c
@@ -12,7 +12,7 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#include 
+#include 
 
 #include 
 
diff --git a/bsps/arm/xen/include/bsp/irq.h b/bsps/arm/xen/include/bsp/irq.h
index dc09e52373..a147a1c079 100644
--- a/bsps/arm/xen/include/bsp/irq.h
+++ b/bsps/arm/xen/include/bsp/irq.h
@@ -34,7 +34,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/include/tm27.h b/bsps/arm/xen/include/tm27.h
index 2fc4afa4f2..4c1dfaa213 100644
--- a/bsps/arm/xen/include/tm27.h
+++ b/bsps/arm/xen/include/tm27.h
@@ -33,6 +33,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h 
b/bsps/arm/xilinx-zynq/include/bsp/irq.h
index edea29b7df..e707337fa1 100644
--- a/bsps/arm/xilinx-zynq/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h
@@ -40,7 +40,7 @@
 #include 
 
 #include 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynq/include/tm27.h 
b/bsps/arm/xilinx-zynq/include/tm27.h
index 885b97a30c..7fc8dd7edd 100644
--- a/bsps/arm/xilinx-zynq/include/tm27.h
+++ b/bsps/arm/xilinx-zynq/include/tm27.h
@@ -44,6 +44,6 @@
  * @brief Interrupt Mechanisms for tm27 test
  */
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h 
b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
index 73567da011..6496d2312e 100644
--- a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynqmp/include/tm27.h 
b/bsps/arm/xilinx-zynqmp/include/tm27.h
index 0f02a3b195..14214fe151 100644
--- a/bsps/arm/xilinx-zynqmp/include/tm27.h
+++ b/bsps/arm/xilinx-zynqmp/include/tm27.h
@@ -49,6 +49,6 @@
  * @brief Interrupt Mechanisms for tm27 test
  */
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/headers.am b/bsps/headers.am
index aaf13284bd..b433c2d8d4 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,13 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HEADERS += ../../bsps/inclu

[PATCH v5 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..ac9e8c6 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,10 +34,10 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
-could be used to speed up the find first bit operation.  The use of this
-instruction should significantly speed up the scheduling associated with a
-thread blocking.  This is currently not used.
+The ARMv5 and later instruction sets have the count leading zeroes ``clz``
+instruction which could be used to speed up the find first bit operation. The
+use of this instruction should significantly speed up the scheduling associated
+with a thread blocking.  This is currently not used.
 
 Floating Point Unit
 ---
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -194,13 +194,13 @@ actions:
 Symmetric Multiprocessing
 =
 
-SMP is supported on ARMv7-A.  Available platforms are
+SMP is supported on ARMv7-A.  Available platforms are:
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v4 2/9] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
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[PATCH v4 8/9] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  69 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  67 ++
 bsps/aarch64/a53/include/tm27.h   |  46 ++
 bsps/aarch64/a53/start/bspstart.c |  49 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  50 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 616 ++
 .../shared/clock/arm-generic-timer-aarch64.c  | 110 
 .../shared/irq/irq-arm-gicv3-aarch64.c|  64 ++
 bsps/aarch64/shared/start/linkcmds.base   | 425 
 bsps/aarch64/shared/start/start.S | 219 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  17 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  19 +
 spec/build/bsps/aarch64/a53/grp.yml   |  42 ++
 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml |  71 ++
 spec/build/bsps/aarch64/a53/obj.yml   |  37 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  18 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramori.yml |  18 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  45 ++
 spec/build/bsps/aarch64/grp.yml   |  24 +
 spec/build/bsps/aarch64/start.yml |  14 +
 25 files changed, 2480 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/grp.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
 create mode 100644 spec/build/bsps/aarch64/a53/obj.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/grp.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..1854909c98
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64A53
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_conte

[PATCH v4 6/9] spmsgq_err01: Use correct max values and fix 64bit

[Kinsey Moore]

Fix spmsgq_err01 on systems with 64-bit pointers and correct max value
mismatches and inaccuracies that are more noticable on 64-bit systems.
---
 testsuites/sptests/spmsgq_err01/init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/testsuites/sptests/spmsgq_err01/init.c 
b/testsuites/sptests/spmsgq_err01/init.c
index c68d30da16..cb1a82c0e1 100644
--- a/testsuites/sptests/spmsgq_err01/init.c
+++ b/testsuites/sptests/spmsgq_err01/init.c
@@ -101,7 +101,7 @@ rtems_task Init(
   /* not enough memory for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-SIZE_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
+UINT32_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
 1,
 RTEMS_DEFAULT_ATTRIBUTES,
 &Queue_id[ 1 ]
@@ -116,8 +116,8 @@ rtems_task Init(
   /* too large a request for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-INT_MAX,
-INT_MAX,
+UINT32_MAX,
+SIZE_MAX - sizeof( uintptr_t ) + 1 - sizeof( CORE_message_queue_Buffer ),
 RTEMS_DEFAULT_ATTRIBUTES,
 &Queue_id[ 1 ]
   );
-- 
2.20.1

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[PATCH v4 5/9] bsps/shared: Add PSCI-based bspreset implementation

[Kinsey Moore]

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-arm-psci.c | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-arm-psci.c

diff --git a/bsps/shared/start/bspreset-arm-psci.c 
b/bsps/shared/start/bspreset-arm-psci.c
new file mode 100644
index 00..215be5c9b5
--- /dev/null
+++ b/bsps/shared/start/bspreset-arm-psci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP reset hook.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v4 7/9] score: Add AArch64 port

[Kinsey Moore]

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   6 +-
 .../cpu/aarch64/aarch64-context-validate.S| 305 ++
 .../aarch64-context-volatile-clobber.S| 100 
 .../cpu/aarch64/aarch64-exception-default.S   | 490 
 .../cpu/aarch64/aarch64-exception-default.c   |  50 ++
 .../aarch64/aarch64-exception-frame-print.c   | 108 
 .../cpu/aarch64/aarch64-exception-interrupt.S | 322 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  47 ++
 cpukit/score/cpu/aarch64/cpu.c| 197 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 100 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  89 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  83 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 554 ++
 .../cpu/aarch64/include/rtems/score/cpu_irq.h |  50 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  42 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  83 +++
 spec/build/cpukit/cpuaarch64.yml  |  36 ++
 spec/build/cpukit/librtemscpu.yml |   2 +
 19 files changed, 2797 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu_irq.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..57063990e7 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,11 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+/*
+ * GCC under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS
+ * data segment and indexes into it accordingly for TLS variable addresses.
+ */
+#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8)
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..31c8d5571c
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief Implementation of _CPU_Context_validate
+ *
+ * This file implements _CPU_Context_validate for use in spcontext01.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWAR

[PATCH v1] tester: Prevent crash with json output

[Kinsey Moore]

This fixes an issue with json report output that causes a crash due to
the incorrect object member being accessed for test-too-long. This also
changes treatment of fatal errors to match how they are displayed in the
tester log output and changes "fatal error" to "fatal-error" to better
match the naming of all the other failure types.
---
 tester/rt/report.py | 2 +-
 tester/rt/test.py   | 9 ++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/tester/rt/report.py b/tester/rt/report.py
index 5f871dc..be8df74 100644
--- a/tester/rt/report.py
+++ b/tester/rt/report.py
@@ -194,7 +194,7 @@ class report(object):
 status = 'passed'
 self.passed += 1
 elif fatal:
-status = 'fatal error'
+status = 'fatal-error'
 self.failed += 1
 elif timeout:
 status = 'timeout'
diff --git a/tester/rt/test.py b/tester/rt/test.py
index fa9ddf5..9b157e9 100644
--- a/tester/rt/test.py
+++ b/tester/rt/test.py
@@ -235,7 +235,7 @@ def generate_json_report(args, reports, start_time, 
end_time,
 json_log['summary']['indeterminate_count'] = reports.indeterminate
 json_log['summary']['benchmark_count'] = reports.benchmark
 json_log['summary']['timeout_count'] = reports.timeouts
-json_log['summary']['too_long_count'] = reports.too_long
+json_log['summary']['test-too-long_count'] = reports.test_too_long
 json_log['summary']['invalid_count'] = reports.invalids
 json_log['summary']['wrong-version_count'] = reports.wrong_version
 json_log['summary']['wrong-build_count'] = reports.wrong_build
@@ -247,7 +247,7 @@ def generate_json_report(args, reports, start_time, 
end_time,
 
 result_types = [
 'failed', 'user-input', 'expected-fail', 'indeterminate',
-'benchmark', 'timeout', 'too-long', 'invalid', 'wrong-version',
+'benchmark', 'timeout', 'test-too-long', 'invalid', 
'wrong-version',
 'wrong-build', 'wrong-tools'
 ]
 json_results = {}
@@ -257,6 +257,9 @@ def generate_json_report(args, reports, start_time, 
end_time,
 # collate results for JSON log
 for name in reports.results:
 result_type = reports.results[name]['result']
+# map fatal-error on to failed since the report adds both to the 
failed count
+if result_type == "fatal-error":
+result_type = "failed"
 test_parts = name.split("/")
 test_category = test_parts[-2]
 test_name = test_parts[-1]
@@ -305,7 +308,7 @@ def generate_junit_report(args, reports, start_time, 
end_time,
 junit_prop['indeterminate_count'] = reports.indeterminate
 junit_prop['benchmark_count'] = reports.benchmark
 junit_prop['timeout_count'] = reports.timeouts
-junit_prop['too_long_count'] = reports.too_long
+junit_prop['test-too-long_count'] = reports.test_too_long
 junit_prop['invalid_count'] = reports.invalids
 junit_prop['wrong-version_count'] = reports.wrong_version
 junit_prop['wrong-build_count'] = reports.wrong_build
-- 
2.20.1

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RE: [PATCH v1] tester: Prevent crash with json output

[Kinsey Moore]

From: Joel Sherrill 
Sent: Monday, October 5, 2020 17:03
To: Chris Johns 
Cc: Kinsey Moore ; rtems-de...@rtems.org 

Subject: Re: [PATCH v1] tester: Prevent crash with json output



On Mon, Oct 5, 2020 at 4:57 PM Chris Johns 
mailto:chr...@rtems.org>> wrote:
On 6/10/20 7:41 am, Kinsey Moore wrote:
> This fixes an issue with json report output that causes a crash due to
> the incorrect object member being accessed for test-too-long. This also
> changes treatment of fatal errors to match how they are displayed in the
> tester log output and changes "fatal error" to "fatal-error" to better
> match the naming of all the other failure types.
> ---
>  tester/rt/report.py | 2 +-
>  tester/rt/test.py   | 9 ++---
>  2 files changed, 7 insertions(+), 4 deletions(-)

OK to push. Thanks.

I'm OK to push this but should it also have a  ticket and go to 5?

I'm sure that's the question Kinsey wants to hear. :)
[]
This was necessary due to a change that didn’t go into 5, so it really 
shouldn’t go into 5, either

Kinsey
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RE: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp

[Kinsey Moore]

Is it possible that the application was only started on the first core instead 
of all cores? Is it possible to check the execution state of the other cores?

Kinsey

From: Joel Sherrill 
Sent: Tuesday, October 6, 2020 08:11
To: small...@aliyun.com
Cc: Gedare Bloom ; devel ; Kinsey Moore 

Subject: Re: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp

Maybe Kinsey has an idea.

On Tue, Oct 6, 2020 at 1:29 AM small...@aliyun.com<mailto:small...@aliyun.com> 
mailto:small...@aliyun.com>> wrote:
The board is Ultra96 board with JTAG boot.
And yes, there is a bspsmp.c in rtems-5.1\bsps\arm\xilinx-zynqmp\start\


small...@aliyun.com<mailto:small...@aliyun.com>

From: Gedare Bloom<mailto:ged...@rtems.org>
Date: 2020-10-06 00:16
To: small...@aliyun.com<mailto:small...@aliyun.com>
CC: devel<mailto:devel@rtems.org>
Subject: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp
It should, I believe. The bsp has bspsmp.c file.

How did you configure (../rtems/configure)?

What board/target do you run it on?

On Mon, Oct 5, 2020 at 2:24 AM small...@aliyun.com<mailto:small...@aliyun.com> 
mailto:small...@aliyun.com>> wrote:
>
> Hi, all
> I compile rtems 5.1 with bsp xilinx-zynqmp. The single core mode is ok.
> But I can not use 2 or 3 or 4 cores of this bsp.
> After analysing the source code, I found there is no code to address smp 
> condition. Does rtems 5.1 indeed not support smp mode for xilinx-zynqmp bsp?
>
> 
> small...@aliyun.com<mailto:small...@aliyun.com>
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RE: [PATCH] testsuites/samples/fileio - Increase of stack size

[Kinsey Moore]

I'm not sure it's specifically a GCC10 issue, but I've encountered something 
like this before (I think it was GCC8 or GCC9).
https://github.com/ISI-apex/rtems/commit/edd6d90c3ad21393dd0de93056f371c7abc89b78

I thought I'd sent in a patch for this or at least created a ticket, but I 
can't find either at the moment.

Kinsey

-Original Message-
From: devel  On Behalf Of Frank Kühndel
Sent: Friday, October 9, 2020 09:06
To: j...@rtems.org
Cc: rtems-de...@rtems.org 
Subject: Re: [PATCH] testsuites/samples/fileio - Increase of stack size

Hi Joel,

Sebastian is the opinion its a "GCC 10 issue".

On 10/9/20 3:32 PM, Joel Sherrill wrote:
> This is interesting. When I teach RTEMS classes, I always run this 
> application and the last time, this BSP was the one used. It was a 
> rare case of all Zynq users with no LEON users. :)
> 
> What version of RTEMS and how did you configure it? 

Version is the newest, I think 6:

remote.origin.url=git://git.rtems.org/rtems.git

The branch bases on origin/master.
The preceding commit was:
commit 558a19d3adff6a3ecf678f94408b48beccbbc9fb (origin/master, origin/HEAD, 
master)

The config.ini is

[arm/realview_pbx_a9_qemu]
RTEMS_DEBUG = True
RTEMS_NETWORKING = True
RTEMS_POSIX_API = True
RTEMS_SMP = True
BUILD_TESTS = True

> 
> This sounds like it may need a ticket since it likely needs to be 
> included on the 5 branch.pa 

I can open a ticket for 5 and 6 if you like.

Greetings
Frank

> 
> I don't doubt it crashed. Just want details so we can apply the patch 
> properly.
> 
> --joel
> 
> On Fri, Oct 9, 2020 at 8:07 AM Frank Kuehndel 
>  > wrote:
> 
> When I use the 'shell' from the fileio sample with the command below:
> 
>    env QEMU_AUDIO_DRV="none" \
>    qemu-system-arm -no-reboot -net none -nographic -M
> realview-pbx-a9 -m 256M \
>    -kernel 
> build/arm/realview_pbx_a9_qemu/testsuites/samples/fileio.exe
> 
> The executable crashes with an "BLOWN STACK!!!" as soon as I try to
> login
> as 'root' with password. (The logins without password work fine.)
> Increasing
> the stack size of the affected thread a bit solves the issue. Hence,
> I suggest this patch.
> ---
>  testsuites/samples/fileio/init.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/testsuites/samples/fileio/init.c
> b/testsuites/samples/fileio/init.c
> index 86b34b99dd..c552d33613 100644
> --- a/testsuites/samples/fileio/init.c
> +++ b/testsuites/samples/fileio/init.c
> @@ -630,7 +630,7 @@ static void fileio_start_shell(void)
>    printf(" =\n");
>    rtems_shell_init(
>      "SHLL",                          /* task_name */
> -    RTEMS_MINIMUM_STACK_SIZE * 4,    /* task_stacksize */
> +    RTEMS_MINIMUM_STACK_SIZE * 5,    /* task_stacksize */
>      100,                             /* task_priority */
>      "/dev/foobar",                   /* devname */
>      /* device is currently ignored by the shell if it is not a pty */
> -- 
> 2.26.2
> 
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RE: aarch64/a53_ilp32_qemu: implicit declaration of function 'truncl'

[Kinsey Moore]

On Sat, Oct 10, 2020 at 8:13 AM Sebastian Huber 
mailto:sebastian.hu...@embedded-brains.de>> 
wrote:
On 10/10/2020 15:11, Sebastian Huber wrote:

> Hello Kinsey,
>
> the new aarch64/a53_ilp32_qemu produces a lot of warnings like this:
>
> ../../../testsuites/psxtests/psxhdrs/math/truncl.c:45:12: warning:
> implicit declaration of function 'truncl'
> [-Wimplicit-function-declaration]
> ../../../testsuites/psxtests/psxhdrs/math/truncl.c:45:12: warning:
> incompatible implicit declaration of built-in function 'truncl'
>
> Is this a known issue?

It is likely that this is because some/many architectures do not
have long double support in newlib. Or have a true long double
type. This will require a newlib discussion.


There is also this warning:

cpukit/libmisc/stackchk/check.c:455:5: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]

This is probably an error. Could you please fix the warnings specific to
the new BSPs.

This looks like code being sloppy that isn't the fault of this BSP. It is
just one where sizeof(int) != sizeof(void *).

Kinsey.. likely solution is to replace the cast/type with intptr_t or uintptr_t.

[]
Sorry, I didn’t see these when I was developing. I’ll work up some patches for 
them.

Kinsey
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[PATCH] score/aarch64: Size saved SP register for ABI

[Kinsey Moore]

This ensures that the saved SP register is sized appropriately depending
on the chosen ABI and prevents a warning in the libmisc stack checker.
---
 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index da2140a2a8..b33f6a1c85 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -489,7 +489,10 @@ typedef struct {
 #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
   uint32_t _register_lr_top;
 #endif
-  uint64_t register_sp;
+  uintptr_t register_sp;
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+  uint32_t _register_sp_top;
+#endif
   void *register_pc;
 #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
   uint32_t _register_pc_top;
-- 
2.20.1

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RE: [PATCH] score/aarch64: Size saved SP register for ABI

[Kinsey Moore]

From: Hesham Almatary 
Sent: Thursday, October 22, 2020 14:51
To: Kinsey Moore 
Cc: devel@rtems.org
Subject: Re: [PATCH] score/aarch64: Size saved SP register for ABI



On Thu, 22 Oct 2020 at 20:07, Kinsey Moore 
mailto:kinsey.mo...@oarcorp.com>> wrote:
This ensures that the saved SP register is sized appropriately depending
on the chosen ABI and prevents a warning in the libmisc stack checker.
---
 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index da2140a2a8..b33f6a1c85 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -489,7 +489,10 @@ typedef struct {
 #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
   uint32_t _register_lr_top;
 #endif
-  uint64_t register_sp;
+  uintptr_t register_sp;
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+  uint32_t _register_sp_top;
Won’t uintptr_t work here (and for all of the other integer registers) as well 
and consequently we get rid of all of such multiarch  ifdefs?

It doesn’t get rid of the multiarch ifdefs, it would just move them to the 
offsets #define block above and into the assembly for generating the stack 
frame. I’d much rather have the exception frame be a static size and avoid 
adjusting the assembly and offsets based on ABI since from the machine’s 
perspective it’s still a 64bit pointer even if C and C++ view it as a 32bit 
pointer.


Kinsey
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[PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds
was previously present on LP64 builds and causes no issues within RTEMS,
but causes relocation/alignment issues when building libbsd. This
restricts those alignment changes to ILP32 builds.
---
 bsps/aarch64/shared/start/linkcmds.base| 6 --
 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/bsps/aarch64/shared/start/linkcmds.base 
b/bsps/aarch64/shared/start/linkcmds.base
index 450c3ba2a9..4bf5b10746 100644
--- a/bsps/aarch64/shared/start/linkcmds.base
+++ b/bsps/aarch64/shared/start/linkcmds.base
@@ -43,6 +43,8 @@ STARTUP (start.o)
 
 bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 16;
 
+bsp_set_align = DEFINED (bsp_set_align) ? bsp_set_align : 8;
+
 bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? 
bsp_stack_exception_size : 0;
 bsp_stack_exception_size = ALIGN (bsp_stack_exception_size, bsp_stack_align);
 
@@ -243,7 +245,7 @@ SECTIONS {
.got : ALIGN_WITH_INPUT {
*(.got.plt) *(.igot.plt) *(.got) *(.igot)
} > REGION_RODATA AT > REGION_RODATA_LOAD
-   .rtemsroset : ALIGN_WITH_INPUT SUBALIGN(4) {
+   .rtemsroset : ALIGN_WITH_INPUT SUBALIGN(bsp_set_align) {
/* Special FreeBSD linker set sections */
__start_set_sysctl_set = .;
*(set_sysctl_*);
@@ -297,7 +299,7 @@ SECTIONS {
.data1 : ALIGN_WITH_INPUT {
*(.data1)
} > REGION_DATA AT > REGION_DATA_LOAD
-   .rtemsrwset : ALIGN_WITH_INPUT SUBALIGN(4) {
+   .rtemsrwset : ALIGN_WITH_INPUT SUBALIGN(bsp_set_align) {
KEEP (*(SORT(.rtemsrwset.*)))
bsp_section_data_end = .;
} > REGION_DATA AT > REGION_DATA_LOAD
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
index ed585f1950..085c9c707c 100644
--- a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -60,6 +60,7 @@ content: |
 
   OUTPUT_FORMAT ("elf32-littleaarch64")
   OUTPUT_ARCH (aarch64:ilp32)
+  bsp_set_align = 4;
 
   INCLUDE linkcmds.base
 copyrights:
-- 
2.20.1

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[PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

[Kinsey Moore]

These files are required for libbsd to build against the AArch64 A53
BSPs.
---
 spec/build/bsps/aarch64/grp.yml | 4 
 1 file changed, 4 insertions(+)

diff --git a/spec/build/bsps/aarch64/grp.yml b/spec/build/bsps/aarch64/grp.yml
index 4b5f998a12..e0a8e607a5 100644
--- a/spec/build/bsps/aarch64/grp.yml
+++ b/spec/build/bsps/aarch64/grp.yml
@@ -5,6 +5,10 @@ copyrights:
 enabled-by: true
 includes: []
 install:
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/arm/include/bsp/linker-symbols.h
+  - bsps/arm/include/bsp/start.h
 - destination: ${BSP_INCLUDEDIR}/dev/clock
   source:
   - bsps/include/dev/clock/arm-generic-timer.h
-- 
2.20.1

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[PATCH rtems-libbsd] Update arm64/aarch64 support

[Kinsey Moore]

---
 freebsd/sys/arm64/arm64/in_cksum.c| 243 +++
 freebsd/sys/arm64/include/machine/armreg.h| 665 ++
 freebsd/sys/arm64/include/machine/cpu.h   | 203 ++
 freebsd/sys/arm64/include/machine/cpufunc.h   | 153 
 freebsd/sys/arm64/include/machine/in_cksum.h  |  83 +++
 .../ck/include/gcc/aarch64/ck_pr_llsc.h   | 352 +
 .../ck/include/gcc/aarch64/ck_pr_lse.h| 298 
 libbsd.py |  21 +
 rtemsbsd/include/machine/frame.h  |   1 +
 9 files changed, 2019 insertions(+)
 create mode 100644 freebsd/sys/arm64/arm64/in_cksum.c
 create mode 100644 freebsd/sys/arm64/include/machine/armreg.h
 create mode 100644 freebsd/sys/arm64/include/machine/cpu.h
 create mode 100644 freebsd/sys/arm64/include/machine/cpufunc.h
 create mode 100644 freebsd/sys/arm64/include/machine/in_cksum.h
 create mode 100644 freebsd/sys/contrib/ck/include/gcc/aarch64/ck_pr_llsc.h
 create mode 100644 freebsd/sys/contrib/ck/include/gcc/aarch64/ck_pr_lse.h
 create mode 100644 rtemsbsd/include/machine/frame.h

diff --git a/freebsd/sys/arm64/arm64/in_cksum.c 
b/freebsd/sys/arm64/arm64/in_cksum.c
new file mode 100644
index ..9f92f2ff
--- /dev/null
+++ b/freebsd/sys/arm64/arm64/in_cksum.c
@@ -0,0 +1,243 @@
+#include 
+
+/* $NetBSD: in_cksum.c,v 1.7 1997/09/02 13:18:15 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1988, 1992, 1993
+ * The Regents of the University of California.  All rights reserved.
+ * Copyright (c) 1996
+ * Matt Thomas 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *may be used to endorse or promote products derived from this software
+ *without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)in_cksum.c  8.1 (Berkeley) 6/10/93
+ */
+
+#include  /* RCS ID & Copyright macro defns */
+__FBSDID("$FreeBSD$");
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Checksum routine for Internet Protocol family headers
+ *(Portable Alpha version).
+ *
+ * This routine is very heavily used in the network
+ * code and should be modified for each CPU to be as fast as possible.
+ */
+
+#define ADDCARRY(x)  (x > 65535 ? x -= 65535 : x)
+#define REDUCE32 \
+{\
+   q_util.q = sum;   \
+   sum = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3];  \
+}
+#define REDUCE16 \
+{\
+   q_util.q = sum;   \
+   l_util.l = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \
+   sum = l_util.s[0] + l_util.s[1];  \
+   ADDCARRY(sum);\
+}
+
+static const u_int32_t in_masks[] = {
+   /*0 bytes*/ /*1 byte*/  /*2 bytes*/ /*3 bytes*/
+   0x, 0x00FF, 0x, 0x00FF, /* offset 0 */
+   0x, 0xFF00, 0x0000, 0xFF00, /* offset 1 */
+   0x, 0x00FF, 0x, 0x, /* offset 2 */
+   0x, 0xFF00, 0xFF00, 0xFF00, /* offset 3 */
+};
+
+union l_util {
+   u

RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Friday, November 13, 2020 04:26
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

>On 12/11/2020 14:32, Kinsey Moore wrote:
>
>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds 
>> was previously present on LP64 builds and causes no issues within 
>> RTEMS, but causes relocation/alignment issues when building libbsd. 
>> This restricts those alignment changes to ILP32 builds.
>The SUBALIGN() is currently only used on aarch64 in RTEMS. Why is it 
>necessary? The PowerPC port for example uses a single linkcmds.base for the 
>32-bit and 64-bit without a SUBALIGN().

The SUBALIGN was necessary because the default alignment was 8 bytes and the 
ILP32 code would fail during initialization while iterating over the linker 
sets since the upper half-word of every address was zeroed out and was being 
treated as another init call. Is there a preferred way to accomplish this that 
doesn't involve SUBALIGN?

Given my experience with AArch64, I would expect the PowerPC linker script to 
need to do the same though upon review it obviously doesn't. The difference may 
be due to a bug in the ILP32 portions of the AArch64 toolchain since it's 
relatively new.

Kinsey
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RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Friday, November 13, 2020 08:16
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

>On 13/11/2020 15:13, Kinsey Moore wrote:
>
>> -Original Message-
>> From: Sebastian Huber
>> Sent: Friday, November 13, 2020 04:26
>> To: Kinsey Moore;devel@rtems.org
>> Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32
>>
>>> On 12/11/2020 14:32, Kinsey Moore wrote:
>>>
>>>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 
>>>> builds was previously present on LP64 builds and causes no issues 
>>>> within RTEMS, but causes relocation/alignment issues when building libbsd.
>>>> This restricts those alignment changes to ILP32 builds.
>>> The SUBALIGN() is currently only used on aarch64 in RTEMS. Why is it 
>>> necessary? The PowerPC port for example uses a single linkcmds.base for the 
>>> 32-bit and 64-bit without a SUBALIGN().
>> The SUBALIGN was necessary because the default alignment was 8 bytes and the 
>> ILP32 code would fail during initialization while iterating over the linker 
>> sets since the upper half-word of every address was zeroed out and was being 
>> treated as another init call. Is there a preferred way to accomplish this 
>> that doesn't involve SUBALIGN?
>
> Why can't you remove all the SUBALIGN() from the linker script?
>
> For example
>
> aarch64-rtems6-ld --verbose | grep SUBALIGN
>
> has no output.

That output is specifically for LP64 AArch64. ILP32 linker scripts have 
different OUTPUT_ARCH and OUTPUT_FORMAT directives. I wasn't able to get 
aarch64-rtems6-ld to output an ILP32 default linker script.

Kinsey
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RE: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Friday, November 13, 2020 04:23
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

On 12/11/2020 14:32, Kinsey Moore wrote:
>>   install:
>> +- destination: ${BSP_INCLUDEDIR}/bsp
>> +  source:
>> +  - bsps/arm/include/bsp/linker-symbols.h
>> +  - bsps/arm/include/bsp/start.h
>>   - destination: ${BSP_INCLUDEDIR}/dev/clock
>> source:
>> - bsps/include/dev/clock/arm-generic-timer.h
> This is a bit strange. You install files which are not used to build the BSP?

They are used by bspstart.c and bspstarthooks.c so they're used to build the 
BSP, but they're only required for some external applications and libraries 
which is why they weren't already being installed. This matches how ARM, 
RISC-V, and other BSPs install start.h and linker-symbols.h.

Kinsey
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RE: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Saturday, November 14, 2020 06:23
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

>On 13/11/2020 16:04, Kinsey Moore wrote:
>
>> -Original Message-
>> From: Sebastian Huber
>> Sent: Friday, November 13, 2020 04:23
>> To: Kinsey Moore;devel@rtems.org
>> Subject: Re: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build 
>> properly
>>
>> On 12/11/2020 14:32, Kinsey Moore wrote:
>>>>install:
>>>> +- destination: ${BSP_INCLUDEDIR}/bsp
>>>> +  source:
>>>> +  - bsps/arm/include/bsp/linker-symbols.h
>>>> +  - bsps/arm/include/bsp/start.h
>>>>- destination: ${BSP_INCLUDEDIR}/dev/clock
>>>>  source:
>>>>  - bsps/include/dev/clock/arm-generic-timer.h
>>> This is a bit strange. You install files which are not used to build the 
>>> BSP?
>> They are used by bspstart.c and bspstarthooks.c so they're used to build the 
>> BSP, but they're only required for some external applications and libraries 
>> which is why they weren't already being installed. This matches how ARM, 
>> RISC-V, and other BSPs install start.h and linker-symbols.h.
> How did you add "bsps/arm/include" to the include path used for the
> aarch64 BSPs?

Ah, sorry. I was missing the point you were trying to make. Those files are 
similar enough that it would allow compilation, but you're right. Those are the 
wrong file paths. I'll update the patch.

Kinsey
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RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Saturday, November 14, 2020 06:24
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

>On 13/11/2020 15:53, Kinsey Moore wrote:
>
>>>> -Original Message-
>>>> From: Sebastian Huber
>>>> Sent: Friday, November 13, 2020 04:26
>>>> To: Kinsey Moore;devel@rtems.org
>>>> Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to 
>>>> ILP32
>>>>
>>>>> On 12/11/2020 14:32, Kinsey Moore wrote:
>>>>>
>>>>>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 
>>>>>> builds was previously present on LP64 builds and causes no issues 
>>>>>> within RTEMS, but causes relocation/alignment issues when building 
>>>>>> libbsd.
>>>>>> This restricts those alignment changes to ILP32 builds.
>>>>> The SUBALIGN() is currently only used on aarch64 in RTEMS. Why is it 
>>>>> necessary? The PowerPC port for example uses a single linkcmds.base for 
>>>>> the 32-bit and 64-bit without a SUBALIGN().
>>>> The SUBALIGN was necessary because the default alignment was 8 bytes and 
>>>> the ILP32 code would fail during initialization while iterating over the 
>>>> linker sets since the upper half-word of every address was zeroed out and 
>>>> was being treated as another init call. Is there a preferred way to 
>>>> accomplish this that doesn't involve SUBALIGN?
>>> Why can't you remove all the SUBALIGN() from the linker script?
>>>
>>> For example
>>>
>>> aarch64-rtems6-ld --verbose | grep SUBALIGN
>>>
>>> has no output.
>> That output is specifically for LP64 AArch64. ILP32 linker scripts have 
>> different OUTPUT_ARCH and OUTPUT_FORMAT directives. I wasn't able to get 
>> aarch64-rtems6-ld to output an ILP32 default linker script.
>What happens if you remove all the SUBALIGN() stuff from the linker script?

The LP64 multilib variant works just fine, but the ILP32 variant crashes during 
init on a null pointer since the elements of the linker set are aligned on 8 
byte boundaries and the iteration occurs for 4 byte pointers.

Kinsey
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RE: [PATCH rtems-tools] bsps/a53_*: Fix typo in qemu options

[Kinsey Moore]

Odd, "gic_version" works just fine in the version of qemu-system-aarch64 in the 
Debian package repos which is what I've been testing against. As you've 
provided in the patch, the official option name is "gic-version" and that also 
works. Just out of curiosity, does this cause Qemu to fail for you?

Either way, this change looks good to me.

Kinsey

-Original Message-
From: devel  On Behalf Of Vijay Kumar Banerjee
Sent: Saturday, November 14, 2020 14:51
To: devel@rtems.org
Subject: [PATCH rtems-tools] bsps/a53_*: Fix typo in qemu options

---
 tester/rtems/testing/bsps/a53_ilp32_qemu.ini | 2 +-  
tester/rtems/testing/bsps/a53_lp64_qemu.ini  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/tester/rtems/testing/bsps/a53_ilp32_qemu.ini 
b/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
index 6dfc883..3beba06 100644
--- a/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
+++ b/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
@@ -35,4 +35,4 @@
 bsp   = a53_ilp32_qemu
 arch  = aarch64
 tester= %{_rtscripts}/qemu.cfg
-bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
virt,gic_version=3 -cpu cortex-a53 -m 4096
+bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
+virt,gic-version=3 -cpu cortex-a53 -m 4096
diff --git a/tester/rtems/testing/bsps/a53_lp64_qemu.ini 
b/tester/rtems/testing/bsps/a53_lp64_qemu.ini
index f29ab13..1b89284 100644
--- a/tester/rtems/testing/bsps/a53_lp64_qemu.ini
+++ b/tester/rtems/testing/bsps/a53_lp64_qemu.ini
@@ -35,4 +35,4 @@
 bsp   = a53_lp64_qemu
 arch  = aarch64
 tester= %{_rtscripts}/qemu.cfg
-bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
virt,gic_version=3 -cpu cortex-a53 -m 4096
+bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
+virt,gic-version=3 -cpu cortex-a53 -m 4096
--
2.21.1

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[PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

[Kinsey Moore]

These files are required for libbsd to build against the AArch64 A53
BSPs.
---
 spec/build/bsps/aarch64/grp.yml | 4 
 1 file changed, 4 insertions(+)

diff --git a/spec/build/bsps/aarch64/grp.yml b/spec/build/bsps/aarch64/grp.yml
index 4b5f998a12..1b8dc1c629 100644
--- a/spec/build/bsps/aarch64/grp.yml
+++ b/spec/build/bsps/aarch64/grp.yml
@@ -5,6 +5,10 @@ copyrights:
 enabled-by: true
 includes: []
 install:
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/aarch64/include/bsp/linker-symbols.h
+  - bsps/aarch64/include/bsp/start.h
 - destination: ${BSP_INCLUDEDIR}/dev/clock
   source:
   - bsps/include/dev/clock/arm-generic-timer.h
-- 
2.20.1

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[PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds
was previously present on LP64 builds and causes no issues within RTEMS,
but causes relocation/alignment issues when building libbsd. This
restricts those alignment changes to ILP32 builds.
---
 bsps/aarch64/shared/start/linkcmds.base| 6 --
 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/bsps/aarch64/shared/start/linkcmds.base 
b/bsps/aarch64/shared/start/linkcmds.base
index 450c3ba2a9..4bf5b10746 100644
--- a/bsps/aarch64/shared/start/linkcmds.base
+++ b/bsps/aarch64/shared/start/linkcmds.base
@@ -43,6 +43,8 @@ STARTUP (start.o)
 
 bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 16;
 
+bsp_set_align = DEFINED (bsp_set_align) ? bsp_set_align : 8;
+
 bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? 
bsp_stack_exception_size : 0;
 bsp_stack_exception_size = ALIGN (bsp_stack_exception_size, bsp_stack_align);
 
@@ -243,7 +245,7 @@ SECTIONS {
.got : ALIGN_WITH_INPUT {
*(.got.plt) *(.igot.plt) *(.got) *(.igot)
} > REGION_RODATA AT > REGION_RODATA_LOAD
-   .rtemsroset : ALIGN_WITH_INPUT SUBALIGN(4) {
+   .rtemsroset : ALIGN_WITH_INPUT SUBALIGN(bsp_set_align) {
/* Special FreeBSD linker set sections */
__start_set_sysctl_set = .;
*(set_sysctl_*);
@@ -297,7 +299,7 @@ SECTIONS {
.data1 : ALIGN_WITH_INPUT {
*(.data1)
} > REGION_DATA AT > REGION_DATA_LOAD
-   .rtemsrwset : ALIGN_WITH_INPUT SUBALIGN(4) {
+   .rtemsrwset : ALIGN_WITH_INPUT SUBALIGN(bsp_set_align) {
KEEP (*(SORT(.rtemsrwset.*)))
bsp_section_data_end = .;
} > REGION_DATA AT > REGION_DATA_LOAD
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
index ed585f1950..085c9c707c 100644
--- a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -60,6 +60,7 @@ content: |
 
   OUTPUT_FORMAT ("elf32-littleaarch64")
   OUTPUT_ARCH (aarch64:ilp32)
+  bsp_set_align = 4;
 
   INCLUDE linkcmds.base
 copyrights:
-- 
2.20.1

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RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Monday, November 16, 2020 07:35
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

>On 16/11/2020 14:15, Kinsey Moore wrote:
>
>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds 
>> was previously present on LP64 builds and causes no issues within 
>> RTEMS, but causes relocation/alignment issues when building libbsd. 
>> This restricts those alignment changes to ILP32 builds.
>
> Please check it in if you think it is necessary.
>
> What troubles me a bit is that these SUBALIGN() stuff is present at all.
>
> It also troubles me that the splinkersets01 test case didn't catch this 
> problem.

That test was what originally caught the problem during development of the A53 
BSP. This patch isn't the addition of a fix for the alignment problems, it's an 
adjustment of the original fix to be compatible with libbsd's use of 
rtemsroset/rtemsrwset linker sections.

Kinsey
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RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Monday, November 16, 2020 07:44
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

> On 16/11/2020 14:40, Kinsey Moore wrote:
>
>> -Original Message-
>> From: Sebastian Huber
>> Sent: Monday, November 16, 2020 07:35
>> To: Kinsey Moore;devel@rtems.org
>> Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32
>>
>>> On 16/11/2020 14:15, Kinsey Moore wrote:
>>>
>>>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 
>>>> builds was previously present on LP64 builds and causes no issues 
>>>> within RTEMS, but causes relocation/alignment issues when building libbsd.
>>>> This restricts those alignment changes to ILP32 builds.
>>> Please check it in if you think it is necessary.
>>>
>>> What troubles me a bit is that these SUBALIGN() stuff is present at all.
>>>
>>> It also troubles me that the splinkersets01 test case didn't catch this 
>>> problem.
>> That test was what originally caught the problem during development of the 
>> A53 BSP. This patch isn't the addition of a fix for the alignment problems, 
>> it's an adjustment of the original fix to be compatible with libbsd's use of 
>> rtemsroset/rtemsrwset linker sections.
> So, this SUBALIGN() is just a workaround for some other problem? It would be 
> good to document this known issue somewhere, for example a ticket. Is this an 
> upstream problem in GCC or the GNU linker?

Yes, SUBALIGN() is the workaround for ILP32 defaulting to 8 byte alignment in 
the rtemsroset and rtemsrwset linker sections because RTEMS expects them to 
default to 4 byte alignment when using 4 byte pointers. I suspect it's an issue 
in the GNU linker, but I haven't had a chance to track down the root cause. 
This patch is necessary because while RTEMS works fine with 4 byte alignment in 
those sections in the context of 8 byte pointers, libbsd puts things other than 
pointers in those sections and requires the alignment of those sections to 
exactly match the pointer size.

I'll open a ticket for documentation purposes.

Kinsey
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RE: [PATCH 5/8] libtest: Allow assert checks during test begin

[Kinsey Moore]

-Original Message-
From: devel  On Behalf Of Sebastian Huber
Sent: Friday, November 13, 2020 04:08
To: devel@rtems.org
Subject: [PATCH 5/8] libtest: Allow assert checks during test begin

> Allow assert checks in test begin actions and setup fixture methods.
> ---
>  cpukit/include/rtems/test.h |  2 +-
>  cpukit/libtest/t-test.c | 29 +
>  2 files changed, 18 insertions(+), 13 deletions(-)

This patch appears to have broken ttest01.exe for arm/xilinx-zynq as well as 
aarch64 targets. I suspect it has also broken other arm targets. I tried 
looking into the failure, but I'm unfamiliar with the test framework in use.

Test output from arm/xilinx-zynq:
$ qemu-system-arm -no-reboot -nographic -serial null -serial mon:stdio -machine 
xilinx-zynq-a9 -m 4096 -kernel 
build/arm/xilinx_zynq_a9_qemu/testsuites/libtests/ttest01.exe


*** BEGIN OF TEST TTEST 1 ***
*** TEST VERSION: 6.0.0.46bf926570503dec3d70a8f09d12e461fd7e0914
*** TEST STATE: EXPECTED_PASS
*** TEST BUILD:
*** TEST TOOLS: 10.2.1 20200918 (RTEMS 6, RSB 
748525234945de047196f9974b866f8595efd66e, Newlib 749cbcc)
A:ttest01
S:Platform:RTEMS
S:Compiler:*
S:Version:*
S:BSP:*
S:RTEMS_DEBUG:*
S:RTEMS_MULTIPROCESSING:*
S:RTEMS_POSIX_API:*
S:RTEMS_PROFILING:*
S:RTEMS_SMP:*
B:zalloc_auto
P:0:0:UI1:test-malloc.c:35
P:1:0:UI1:test-malloc.c:36
P:2:0:UI1:test-malloc.c:26
E:zalloc_auto:N:3:F:0:D:0.001000
B:wrong_step
P:0:0:UI1:test-plan.c:6
F:1:0:UI1:test-plan.c:7:planned step (2)
E:wrong_step:N:2:F:1:D:0.001000
B:verbosity_changes
F:3:0:UI1:test-verbosity.c:12:normal: check fails -> with output
P:4:0:UI1:test-verbosity.c:14
F:5:0:UI1:test-verbosity.c:15:verbose: check fails -> with output
E:verbosity_changes:N:6:F:3:D:0.001000
B:timer
P:0:0:UI1:test-rtems.c:26
P:1:0:UI1:test-rtems.c:29
P:2:0:UI1:test-rtems.c:39
P:3:0:ISR:test-rtems.c:14
P:4:0:ISR:test-rtems.c:15
P:5:0:UI1:test-rtems.c:44
P:6:0:UI1:test-rtems.c:45
P:7:0:UI1:test-rtems.c:48
E:timer:N:8:F:0:D:0.001000
B:time_to_string
P:0:0:UI1:test-time.c:11
P:1:0:UI1:test-time.c:12
P:2:0:UI1:test-time.c:13
P:3:0:UI1:test-time.c:14
P:4:0:UI1:test-time.c:17
P:5:0:UI1:test-time.c:18
E:time_to_string:N:6:F:0:D:0.001000
B:time
P:0:0:UI1:test-time.c:55
P:1:0:UI1:test-time.c:56
P:2:0:UI1:test-time.c:57
P:3:0:UI1:test-time.c:58
P:4:0:UI1:test-time.c:61
P:5:0:UI1:test-time.c:63
P:6:0:UI1:test-time.c:64
P:7:0:UI1:test-time.c:67
P:8:0:UI1:test-time.c:69
P:9:0:UI1:test-time.c:70
P:10:0:UI1:test-time.c:73
P:11:0:UI1:test-time.c:75
P:12:0:UI1:test-time.c:76
P:13:0:UI1:test-time.c:79
P:14:0:UI1:test-time.c:81
P:15:0:UI1:test-time.c:82
P:16:0:UI1:test-time.c:85
P:17:0:UI1:test-time.c:87
P:18:0:UI1:test-time.c:88
P:19:0:UI1:test-time.c:91
P:20:0:UI1:test-time.c:93
P:21:0:UI1:test-time.c:94
P:22:0:UI1:test-time.c:97
P:23:0:UI1:test-time.c:99
P:24:0:UI1:test-time.c:100
P:25:0:UI1:test-time.c:103
P:26:0:UI1:test-time.c:105
P:27:0:UI1:test-time.c:106
P:28:0:UI1:test-time.c:109
P:29:0:UI1:test-time.c:111
P:30:0:UI1:test-time.c:112
P:31:0:UI1:test-time.c:115
P:32:0:UI1:test-time.c:117
P:33:0:UI1:test-time.c:118
P:34:0:UI1:test-time.c:121
P:35:0:UI1:test-time.c:123
P:36:0:UI1:test-time.c:124
P:37:0:UI1:test-time.c:127
P:38:0:UI1:test-time.c:129
P:39:0:UI1:test-time.c:130
E:time:N:40:F:0:D:0.001000
B:ticks
P:0:0:UI1:test-time.c:147
P:1:0:UI1:test-time.c:151
P:2:0:UI1:test-time.c:152
P:3:0:UI1:test-time.c:172
P:4:0:UI1:test-time.c:173
P:5:0:UI1:test-time.c:174
P:6:0:UI1:test-time.c:175
E:ticks:N:7:F:0:D:0.001000
B:tick
P:0:0:UI1:test-time.c:44
E:tick:N:1:F:0:D:0.001000
B:test_psx_success
P:0:0:UI1:test-psx.c:31
F:1:0:UI1:test-psx.c:32:-1 == 0, 0
F:*:0:UI1:test-psx.c:34:-1 == 0, 0
P:2:0:UI1:test-psx.c:35
F:3:0:UI1:test-psx.c:36:-1 == 0, 0
E:
*** FATAL ***
fatal source: 9 (RTEMS_FATAL_SOURCE_EXCEPTION)

R0   = 0xfff8 R8  = 0x
R1   = 0x0030 R9  = 0x00116d79
R2   = 0x00207798 R10 = 0x0002
R3   = 0x0001 R11 = 0x00204378
R4   = 0x R12 = 0x
R5   = 0xffecb9a8 SP  = 0x00207700
R6   = 0x0030 LR  = 0x001108b3
R7   = 0x0013465a PC  = 0x00119f6c
CPSR = 0x600f0173 VEC = 0x0004
FPEXC = 0x4000
FPSCR = 0x
D00 = 0x
D01 = 0x
D02 = 0x
D03 = 0x
D04 = 0x
D05 = 0x
D06 = 0x
D07 = 0x
D08 = 0x
D09 = 0x
D10 = 0x
D11 = 0x
D12 = 0x
D13 = 0x
D14 = 0x
D15 = 0x
D16 = 0x
D17 = 0x
D18 = 0x
D19 = 0x
D20 = 0x
D21 = 0x
D22 = 0x
D23 = 0x
D24 = 0x
D25 = 0x
D26 = 0x
D27 = 0x
D28 = 0x
D29 = 0x
D30 = 0x
D31 = 0x
RTEMS version: 6.0.0.46bf926570503dec3d70a8f09d12e461fd7e0914
RTEMS tools:

RE: [PATCH] libtest: Fix undefined setjmp() behaviour

[Kinsey Moore]

-Original Message-
From: devel  On Behalf Of Sebastian Huber
Sent: Monday, November 23, 2020 03:19
To: devel@rtems.org
Subject: [PATCH] libtest: Fix undefined setjmp() behaviour

> Bug was introduced by 78baeb757957fa0807c30e6c4d21ae99c9639e6a.
>
> Update #3199.
> ---
>  cpukit/include/rtems/test.h |   3 +-
>  cpukit/libtest/t-test.c | 110 +++-
>  2 files changed, 60 insertions(+), 53 deletions(-)

This fixes the bug for me, thanks!

Kinsey
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[PATCH] wscript: Apply test state expectations correctly

[Kinsey Moore]

The variety of expected test states are not currently applied to tests
with names containing '-' correctly due to a failure to replace '-' with
'_' before adding the CPPFLAGS to the environment for that test. This
ensures that all additions of CPPFLAGS have that replacement performed
so that the CPPFLAGS are applied properly during compilation.
---
 wscript | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wscript b/wscript
index 5ad93de453..f5b7629b3b 100755
--- a/wscript
+++ b/wscript
@@ -723,7 +723,7 @@ class OptionItem(Item):
 print("{} = {}".format(self.data["name"], value))
 
 def _do_append_test_cppflags(self, conf, name, state):
-conf.env.append_value("TEST_" + name.upper() + "_CPPFLAGS", state)
+conf.env.append_value("TEST_" + name.upper().replace("-", "_") + 
"_CPPFLAGS", state)
 
 def _append_test_cppflags(self, conf, cic, value, arg):
 self._do_append_test_cppflags(conf, arg, value)
-- 
2.20.1

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[PATCH] score/aarch64: Resolve warning in exception dump

[Kinsey Moore]

This resolves a warning in the exception frame dump for AArch64 relating
to a missized printf format specifier.
---
 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c 
b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
index cd919c3214..59b5d06032 100644
--- a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
+++ b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
@@ -65,7 +65,7 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame 
*frame )
 "X11  = 0x%016" PRIx64  " X28  = 0x%016" PRIx64 "\n"
 "X12  = 0x%016" PRIx64  " FP   = 0x%016" PRIx64 "\n"
 "X13  = 0x%016" PRIx64  " LR   = 0x%016" PRIxPTR "\n"
-"X14  = 0x%016" PRIx64  " SP   = 0x%016" PRIx64 "\n"
+"X14  = 0x%016" PRIx64  " SP   = 0x%016" PRIxPTR "\n"
 "X15  = 0x%016" PRIx64  " PC   = 0x%016" PRIxPTR "\n"
 "X16  = 0x%016" PRIx64  " DAIF = 0x%016" PRIx64 "\n"
 "VEC  = 0x%016" PRIxPTR " CPSR = 0x%016" PRIx64 "\n"
@@ -84,7 +84,7 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame 
*frame )
 frame->register_x11, frame->register_x28,
 frame->register_x12, frame->register_fp,
 frame->register_x13, (intptr_t)frame->register_lr,
-frame->register_x14, frame->register_sp,
+frame->register_x14, (intptr_t)frame->register_sp,
 frame->register_x15, (intptr_t)frame->register_pc,
 frame->register_x16, frame->register_daif,
 (intptr_t) frame->vector, frame->register_cpsr,
-- 
2.20.1

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[PATCH] Add CGEM definitions for ZynqMP

[Kinsey Moore]

---
 rtemsbsd/include/bsp/nexus-devices.h   |  7 +++
 rtemsbsd/include/machine/rtems-bsd-nexus-bus.h | 16 
 2 files changed, 23 insertions(+)

diff --git a/rtemsbsd/include/bsp/nexus-devices.h 
b/rtemsbsd/include/bsp/nexus-devices.h
index 630572a8..51bca3aa 100644
--- a/rtemsbsd/include/bsp/nexus-devices.h
+++ b/rtemsbsd/include/bsp/nexus-devices.h
@@ -100,6 +100,13 @@ RTEMS_BSD_DRIVER_XILINX_ZYNQ_SLCR;
 RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM0(ZYNQ_IRQ_ETHERNET_0);
 RTEMS_BSD_DRIVER_E1000PHY;
 
+#elif defined(LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_H)
+
+#include 
+
+RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM0(ZYNQMP_IRQ_ETHERNET_0);
+RTEMS_BSD_DRIVER_E1000PHY;
+
 #elif defined(LIBBSP_ARM_ATSAM_BSP_H)
 
 RTEMS_BSD_DRIVER_USB;
diff --git a/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h 
b/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
index ff545dc0..f1ca66d7 100644
--- a/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
+++ b/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
@@ -371,6 +371,22 @@ extern "C" {
   #define RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM1(_irq)   \
 RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(1, 0xe000c000, _irq)
 #endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM1 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM0)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM0(_irq)\
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(0, 0xff0b, _irq)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM0 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM1)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM1(_irq)   \
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(1, 0xff0c, _irq)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM1 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM2)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM2(_irq)\
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(2, 0xff0d, _irq)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM2 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3(_irq)   \
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(3, 0xff0e, _irq)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3 */
 
 /*
  * Designware/Synopsys Ethernet MAC Controller.
-- 
2.20.1

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[PATCH] spec/a53: Set conditionally failing test state

[Kinsey Moore]

The spintrcritical03-05 and psx12 tests are known to fail on Qemu when
the host system is heavily loaded. A single run of Qemu per core
during a testsuite run tends to yield positive results, but any
additional load on a system will result in test failures.

This patch also applies the correct expected test state for intermittent
failures so that those tests will still build.
---
 spec/build/bsps/aarch64/a53/tsta53.yml | 36 --
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/spec/build/bsps/aarch64/a53/tsta53.yml 
b/spec/build/bsps/aarch64/a53/tsta53.yml
index a40cc8671c..9135fac7f4 100644
--- a/spec/build/bsps/aarch64/a53/tsta53.yml
+++ b/spec/build/bsps/aarch64/a53/tsta53.yml
@@ -12,20 +12,28 @@ actions:
 spmisc01: exclude
 
 # tests that are passing intermittently
-spcpucounter01: exclude
-rtmonuse: exclude
-sp37: exclude
-sp68: exclude
-sp04: exclude
-sp20: exclude
-sp69: exclude
-rtmonusxtimes01: exclude
-spedfsched02: exclude
-psxtimes01: exclude
-sprmsched01: exclude
-sptimecounter02: exclude
-sptimecounter04: exclude
-ttest02: exclude
+spcpucounter01: indeterminate
+rtmonuse: indeterminate
+sp37: indeterminate
+sp68: indeterminate
+sp04: indeterminate
+sp20: indeterminate
+sp69: indeterminate
+rtmonusxtimes01: indeterminate
+spedfsched02: indeterminate
+spedfsched04: indeterminate
+psxtimes01: indeterminate
+sprmsched01: indeterminate
+sptimecounter02: indeterminate
+sptimecounter04: indeterminate
+ttest02: indeterminate
+
+# tests that pass nominally, but fail under Qemu when the host is under
+# heavy load
+psx12: indeterminate
+spintrcritical03: indeterminate
+spintrcritical04: indeterminate
+spintrcritical05: indeterminate
 build-type: option
 copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
-- 
2.20.1

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[PATCH] tester: Report fatal-error test states as failures

[Kinsey Moore]

Tests resulting in the fatal-error state are counted as failures, but
are not currently reported in the text summary. This has already been
fixed for JSON output.
---
 tester/rt/report.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tester/rt/report.py b/tester/rt/report.py
index be8df74..0e19edc 100644
--- a/tester/rt/report.py
+++ b/tester/rt/report.py
@@ -321,6 +321,7 @@ class report(object):
 if self.failed:
 l += ['Failures:']
 l += show_state(self.results, 'failed', self.name_max_len)
+l += show_state(self.results, 'fatal-error', self.name_max_len)
 if self.user_input:
 l += ['User Input:']
 l += show_state(self.results, 'user-input', self.name_max_len)
-- 
2.20.1

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[PATCH v1 2/3] bsps: Move ARM GICv2 driver to bsps/shared

[Kinsey Moore]

This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
---
 ...-gicv3-aarch64.c => irq-arm-gicvx-aarch64.c} |  2 +-
 ...-gicv3-aarch32.c => irq-arm-gicvx-aarch32.c} |  2 +-
 bsps/include/dev/irq/arm-gic-irq.h  |  4 ++--
 .../irq-gic.c => shared/dev/irq/arm-gicv2.c}| 17 +++--
 bsps/shared/dev/irq/arm-gicv3.c |  2 +-
 .../lib/libbsp/arm/altera-cyclone-v/Makefile.am |  3 ++-
 c/src/lib/libbsp/arm/imx/Makefile.am|  3 ++-
 .../lib/libbsp/arm/realview-pbx-a9/Makefile.am  |  3 ++-
 c/src/lib/libbsp/arm/xen/Makefile.am|  3 ++-
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am|  3 ++-
 c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 ++-
 spec/build/bsps/aarch64/a53/obj.yml |  2 +-
 .../arm/altera-cyclone-v/bspalteracyclonev.yml  |  3 ++-
 spec/build/bsps/arm/imx/bspimx.yml  |  3 ++-
 .../arm/realview-pbx-a9/bsprealviewpbxa9.yml|  3 ++-
 spec/build/bsps/arm/xen/bspxen.yml  |  3 ++-
 spec/build/bsps/arm/xilinx-zynq/obj.yml |  3 ++-
 .../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml  |  3 ++-
 18 files changed, 33 insertions(+), 32 deletions(-)
 rename bsps/aarch64/shared/irq/{irq-arm-gicv3-aarch64.c => 
irq-arm-gicvx-aarch64.c} (98%)
 rename bsps/arm/shared/irq/{irq-arm-gicv3-aarch32.c => 
irq-arm-gicvx-aarch32.c} (98%)
 rename bsps/{arm/shared/irq/irq-gic.c => shared/dev/irq/arm-gicv2.c} (95%)

diff --git a/bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c 
b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
similarity index 98%
rename from bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
rename to bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
index fe74bf46bd..67839118e1 100644
--- a/bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
+++ b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
@@ -60,5 +60,5 @@ void arm_interrupt_facility_set_exception_handler(void)
 
 void bsp_interrupt_dispatch(void)
 {
-  gicv3_interrupt_dispatch();
+  gicvx_interrupt_dispatch();
 }
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
similarity index 98%
rename from bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
rename to bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
index b805199ba9..b9267aecba 100644
--- a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
+++ b/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
@@ -57,5 +57,5 @@ void arm_interrupt_facility_set_exception_handler(void)
 
 void bsp_interrupt_dispatch(void)
 {
-  gicv3_interrupt_dispatch();
+  gicvx_interrupt_dispatch();
 }
diff --git a/bsps/include/dev/irq/arm-gic-irq.h 
b/bsps/include/dev/irq/arm-gic-irq.h
index a97191faca..d63fce32d1 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -122,10 +122,10 @@ void arm_interrupt_facility_set_exception_handler(void);
 void arm_interrupt_handler_dispatch(rtems_vector_number vector);
 
 /**
- * This is the GICv3 interrupt dispatcher that is to be called from the
+ * This is the GICv1/GICv2/GICv3 interrupt dispatcher that is to be called 
from the
  * architecture-specific implementation of the IRQ handler.
  */
-void gicv3_interrupt_dispatch(void);
+void gicvx_interrupt_dispatch(void);
 
 static inline uint32_t arm_gic_irq_processor_count(void)
 {
diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/shared/dev/irq/arm-gicv2.c
similarity index 95%
rename from bsps/arm/shared/irq/irq-gic.c
rename to bsps/shared/dev/irq/arm-gicv2.c
index 1a401b67b6..cba8982764 100644
--- a/bsps/arm/shared/irq/irq-gic.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -14,10 +14,6 @@
 
 #include 
 
-#include 
-
-#include 
-
 #include 
 #include 
 #include 
@@ -53,7 +49,7 @@
 #define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE
 #endif
 
-void bsp_interrupt_dispatch(void)
+void gicvx_interrupt_dispatch(void)
 {
   volatile gic_cpuif *cpuif = GIC_CPUIF;
   uint32_t icciar = cpuif->icciar;
@@ -61,11 +57,7 @@ void bsp_interrupt_dispatch(void)
   rtems_vector_number spurious = 1023;
 
   if (vector != spurious) {
-uint32_t psr = _ARMV4_Status_irq_enable();
-
-bsp_interrupt_handler_dispatch(vector);
-
-_ARMV4_Status_restore(psr);
+arm_interrupt_handler_dispatch(vector);
 
 cpuif->icceoir = icciar;
   }
@@ -117,10 +109,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
   uint32_t id_count = get_id_count(dist);
   uint32_t id;
 
-  arm_cp15_set_exception_handler(
-ARM_EXCEPTION_IRQ,
-_ARMV4_Exception_interrupt
-  );
+  arm_interrupt_facility_set_exception_handler();
 
   for (id = 0; id < id_count; id += 32) {
 #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index ad39872eb0..da19300b15 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -134,7 +134,7 @@
 #define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE)
 #define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *) 
((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16

[PATCH v1 1/3] bsps: Move zynq-uart to bsps/shared

[Kinsey Moore]

This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to
accomodate use by AArch64 BSPs.
---
 bsps/arm/headers.am| 2 --
 bsps/arm/xilinx-zynq/console/console-config.c  | 2 +-
 bsps/arm/xilinx-zynq/console/console-init.c| 2 +-
 bsps/arm/xilinx-zynq/console/debug-console.c   | 2 +-
 bsps/arm/xilinx-zynq/include/bsp.h | 2 +-
 bsps/arm/xilinx-zynq/start/bspreset.c  | 2 +-
 bsps/arm/xilinx-zynqmp/console/console-config.c| 2 +-
 bsps/headers.am| 2 ++
 .../include/bsp => include/dev/serial}/zynq-uart-regs.h| 0
 bsps/{arm/include/bsp => include/dev/serial}/zynq-uart.h   | 7 +++
 bsps/{arm/shared => shared/dev}/serial/zynq-uart-polled.c  | 4 ++--
 bsps/{arm/shared => shared/dev}/serial/zynq-uart.c | 4 ++--
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am   | 4 ++--
 c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 4 ++--
 spec/build/bsps/arm/grp.yml| 2 --
 spec/build/bsps/arm/xilinx-zynq/obj.yml| 2 --
 spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml  | 2 --
 spec/build/bsps/obj.yml| 4 
 18 files changed, 27 insertions(+), 22 deletions(-)
 rename bsps/{arm/include/bsp => include/dev/serial}/zynq-uart-regs.h (100%)
 rename bsps/{arm/include/bsp => include/dev/serial}/zynq-uart.h (93%)
 rename bsps/{arm/shared => shared/dev}/serial/zynq-uart-polled.c (98%)
 rename bsps/{arm/shared => shared/dev}/serial/zynq-uart.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index bff9a16fc8..a4d6dfa09e 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -31,8 +31,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/lpc-i2s.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-lcd.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-timer.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/start.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/zynq-uart-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/zynq-uart.h
 
 include_libcpudir = $(includedir)/libcpu
 include_libcpu_HEADERS =
diff --git a/bsps/arm/xilinx-zynq/console/console-config.c 
b/bsps/arm/xilinx-zynq/console/console-config.c
index 7e28716bbe..0581247a2d 100644
--- a/bsps/arm/xilinx-zynq/console/console-config.c
+++ b/bsps/arm/xilinx-zynq/console/console-config.c
@@ -26,7 +26,7 @@
  */
 
 #include 
-#include 
+#include 
 
 zynq_uart_context zynq_uart_instances[2] = {
   {
diff --git a/bsps/arm/xilinx-zynq/console/console-init.c 
b/bsps/arm/xilinx-zynq/console/console-init.c
index 72ba27006c..a3659e3906 100644
--- a/bsps/arm/xilinx-zynq/console/console-init.c
+++ b/bsps/arm/xilinx-zynq/console/console-init.c
@@ -28,7 +28,7 @@
 #include 
 
 #include 
-#include 
+#include 
 
 rtems_status_code console_initialize(
   rtems_device_major_number major,
diff --git a/bsps/arm/xilinx-zynq/console/debug-console.c 
b/bsps/arm/xilinx-zynq/console/debug-console.c
index 809fd6830d..0e9b756f30 100644
--- a/bsps/arm/xilinx-zynq/console/debug-console.c
+++ b/bsps/arm/xilinx-zynq/console/debug-console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 
 #include 
 
diff --git a/bsps/arm/xilinx-zynq/include/bsp.h 
b/bsps/arm/xilinx-zynq/include/bsp.h
index 6c2759ce50..fde8d03130 100644
--- a/bsps/arm/xilinx-zynq/include/bsp.h
+++ b/bsps/arm/xilinx-zynq/include/bsp.h
@@ -54,7 +54,7 @@
 
 #include 
 #include 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynq/start/bspreset.c 
b/bsps/arm/xilinx-zynq/start/bspreset.c
index e0c81ca2ef..3e797a137e 100644
--- a/bsps/arm/xilinx-zynq/start/bspreset.c
+++ b/bsps/arm/xilinx-zynq/start/bspreset.c
@@ -27,7 +27,7 @@
 
 #include 
 #include 
-#include 
+#include 
 
 void bsp_reset(void)
 {
diff --git a/bsps/arm/xilinx-zynqmp/console/console-config.c 
b/bsps/arm/xilinx-zynqmp/console/console-config.c
index a525f9c565..fb0b003c83 100644
--- a/bsps/arm/xilinx-zynqmp/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp/console/console-config.c
@@ -35,7 +35,7 @@
 #include 
 
 #include 
-#include 
+#include 
 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index b433c2d8d4..8147745711 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -32,6 +32,8 @@ include_dev_serialdir = $(includedir)/dev/serial
 include_dev_serial_HEADERS =
 include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011-regs.h
 include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart-regs.h
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart.h
 
 include_grlibdir = $(includedir)/grlib
 include_grlib_HEADERS =
diff --git a/bsps/arm/include/bsp/zynq-uart-regs.h 
b/bsps/include/dev/se

[PATCH v1 3/3] Add AArch64 ZynpMP BSP

[Kinsey Moore]

This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC
(ZynqMP) family of chips. It is configured to be usable on the Qemu
ZCU102 machine definition and should be almost trivially portable to
ZynqMP development boards and custom hardware. It is also configured to
be usable with libbsd.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  | 134 ++
 bsps/aarch64/xilinx-zynqmp/include/bsp.h  |  81 +++
 bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h  |  72 ++
 bsps/aarch64/xilinx-zynqmp/include/tm27.h |  46 ++
 bsps/aarch64/xilinx-zynqmp/start/bspstart.c   |  49 +++
 .../xilinx-zynqmp/start/bspstarthooks.c   |  50 +++
 spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml |  22 +++
 .../aarch64/xilinx-zynqmp/bspqemuilp32.yml|  21 +++
 .../aarch64/xilinx-zynqmp/bspqemulp64.yml |  21 +++
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |  44 ++
 .../aarch64/xilinx-zynqmp/linkcmds_ilp32.yml  |  72 ++
 .../aarch64/xilinx-zynqmp/linkcmds_lp64.yml   |  71 ++
 spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml |  37 +
 .../bsps/aarch64/xilinx-zynqmp/optclkuart.yml |  20 +++
 .../aarch64/xilinx-zynqmp/optconminor.yml |  15 ++
 .../bsps/aarch64/xilinx-zynqmp/optloadoff.yml |  18 +++
 .../aarch64/xilinx-zynqmp/optnocachelen.yml   |  18 +++
 .../bsps/aarch64/xilinx-zynqmp/optramlen.yml  |  18 +++
 .../bsps/aarch64/xilinx-zynqmp/optramori.yml  |  18 +++
 .../bsps/aarch64/xilinx-zynqmp/tstqemu.yml|  56 
 20 files changed, 883 insertions(+)
 create mode 100644 bsps/aarch64/xilinx-zynqmp/console/console.c
 create mode 100644 bsps/aarch64/xilinx-zynqmp/include/bsp.h
 create mode 100644 bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
 create mode 100644 bsps/aarch64/xilinx-zynqmp/include/tm27.h
 create mode 100644 bsps/aarch64/xilinx-zynqmp/start/bspstart.c
 create mode 100644 bsps/aarch64/xilinx-zynqmp/start/bspstarthooks.c
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/bspqemuilp32.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/bspqemulp64.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optclkuart.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optconminor.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/tstqemu.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
new file mode 100644
index 00..7bd85626d9
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64XilinxZynqMP
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+
+static zynq_uart_context zynqmp_uart_instances[2] = {
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
+ 

RE: BSP_CONSOLE_MINOR option for Zynq board with new build system

[Kinsey Moore]

-Original Message-
From: devel  On Behalf Of Sebastian Huber
Sent: Wednesday, December 2, 2020 06:46
To: jan.som...@dlr.de; devel@rtems.org
Subject: Re: BSP_CONSOLE_MINOR option for Zynq board with new build system

> Hello Jan,
>
>> On 02/12/2020 11:19, jan.som...@dlr.de wrote:
>> I forgot to follow up with this until I ran into the same thing again.
>> Your patch works and solves the problem.
>> Would you be so kind to push it to master?
>
> I think this should be fixed along with the new aarch64 BSP for Zynq:
>
> https://lists.rtems.org/pipermail/devel/2020-December/063576.html

I'll include a patch with this fix in my next patch set since I'm shuffling 
things around anyway.

Kinsey
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[PATCH v2 2/4] samples/unlimited: Prevent compile error

[Kinsey Moore]

For architectures with relatively large minimum stack sizes, ensure that
the init task stack size is at least the minimum stack size to prevent a
configuration error during compilation.
---
 testsuites/samples/unlimited/system.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/testsuites/samples/unlimited/system.h 
b/testsuites/samples/unlimited/system.h
index 2624a696df..dafbf9f92e 100644
--- a/testsuites/samples/unlimited/system.h
+++ b/testsuites/samples/unlimited/system.h
@@ -12,6 +12,7 @@
  */
 
 #include 
+#include 
 
 /* functions */
 
@@ -50,7 +51,7 @@ extern void test3(void);
 #define TASK_ALLOCATION_SIZE (5)
 #define CONFIGURE_UNLIMITED_OBJECTS
 #define CONFIGURE_UNLIMITED_ALLOCATION_SIZE TASK_ALLOCATION_SIZE
-#define CONFIGURE_INIT_TASK_STACK_SIZE (8 * 1024)
+#define CONFIGURE_INIT_TASK_STACK_SIZE MAX(8 * 1024, 
CONFIGURE_MINIMUM_TASK_STACK_SIZE)
 
 
 #include 
-- 
2.20.1

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[PATCH v2 1/4] zynq-uart: Fix set_attributes implementation

[Kinsey Moore]

The zynq-uart set_attributes implementation was configured to always
return false which causes spconsole01 to fail. This restores the
disabled implementation which sets the baud rate registers
appropriately and allows spconsole01 to pass. This also expands the
set_attributes functionality to allow setting of the stop bits,
character width, and parity.
---
 bsps/include/dev/serial/zynq-uart.h   |  5 ++
 bsps/shared/dev/serial/zynq-uart-polled.c |  2 +-
 bsps/shared/dev/serial/zynq-uart.c| 62 +--
 3 files changed, 63 insertions(+), 6 deletions(-)

diff --git a/bsps/include/dev/serial/zynq-uart.h 
b/bsps/include/dev/serial/zynq-uart.h
index 2c0f250a3a..e3e8cae6fd 100644
--- a/bsps/include/dev/serial/zynq-uart.h
+++ b/bsps/include/dev/serial/zynq-uart.h
@@ -78,6 +78,11 @@ void zynq_uart_write_polled(
   */
 void zynq_uart_reset_tx_flush(zynq_uart_context *ctx);
 
+int zynq_cal_baud_rate(uint32_t  baudrate,
+   uint32_t* brgr,
+   uint32_t* bauddiv,
+   uint32_t  modereg);
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/bsps/shared/dev/serial/zynq-uart-polled.c 
b/bsps/shared/dev/serial/zynq-uart-polled.c
index a1b51ea521..442431d502 100644
--- a/bsps/shared/dev/serial/zynq-uart-polled.c
+++ b/bsps/shared/dev/serial/zynq-uart-polled.c
@@ -40,7 +40,7 @@ uint32_t zynq_uart_input_clock(void)
   return ZYNQ_CLOCK_UART;
 }
 
-static int zynq_cal_baud_rate(uint32_t  baudrate,
+int zynq_cal_baud_rate(uint32_t  baudrate,
   uint32_t* brgr,
   uint32_t* bauddiv,
   uint32_t  modereg)
diff --git a/bsps/shared/dev/serial/zynq-uart.c 
b/bsps/shared/dev/serial/zynq-uart.c
index 41adb196ab..e2b614c270 100644
--- a/bsps/shared/dev/serial/zynq-uart.c
+++ b/bsps/shared/dev/serial/zynq-uart.c
@@ -142,25 +142,77 @@ static bool zynq_uart_set_attributes(
   const struct termios *term
 )
 {
-#if 0
-  volatile zynq_uart *regs = zynq_uart_get_regs(minor);
+  zynq_uart_context *ctx = (zynq_uart_context *) context;
+  volatile zynq_uart *regs = ctx->regs;
   uint32_t brgr = 0;
   uint32_t bauddiv = 0;
+  uint32_t mode = 0;
   int rc;
 
   rc = zynq_cal_baud_rate(115200, &brgr, &bauddiv, regs->mode);
   if (rc != 0)
 return rc;
 
+  /*
+   * Configure the mode register
+   */
+  mode |= ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL);
+
+  /*
+   * Parity
+   */
+
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE);
+  if (term->c_cflag & PARENB) {
+if (!(term->c_cflag & PARODD))
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD);
+else
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN);
+  }
+
+  /*
+   * Character Size
+   */
+
+  if (term->c_cflag & CSIZE) {
+switch (term->c_cflag & CSIZE) {
+  case CS5:
+   return false;
+  case CS6:
+   mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_6);
+   break;
+  case CS7:
+   mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_7);
+   break;
+  case CS8:
+   mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
+   break;
+}
+  } else {
+/* default to 9600,8,N,1 */
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
+  }
+
+  /*
+   * Stop Bits
+   */
+
+  if (term->c_cflag & CSTOPB) {
+/* 2 stop bits */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_2);
+  } else {
+/* 1 stop bit */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_1);
+  }
+
+
   regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
+  regs->mode = mode;
   regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
   regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
   regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
 
   return true;
-#else
-  return false;
-#endif
 }
 
 const rtems_termios_device_handler zynq_uart_handler = {
-- 
2.20.1

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[PATCH v2 4/4] spec/optconminor: Fix value type

[Kinsey Moore]

The option for defining the console minor should be an integer, not a
boolean.
---
 spec/build/bsps/optconminor.yml | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/spec/build/bsps/optconminor.yml b/spec/build/bsps/optconminor.yml
index 55074c6dac..486eb92d33 100644
--- a/spec/build/bsps/optconminor.yml
+++ b/spec/build/bsps/optconminor.yml
@@ -1,15 +1,16 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 actions:
-- get-boolean: null
-- define-condition: null
+- get-integer: null
+- define: null
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
+default: 1
 default-by-variant: []
 description: |
   minor number of console device
 enabled-by: true
+format: '{}'
 links: []
 name: BSP_CONSOLE_MINOR
 type: build
-- 
2.20.1

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[PATCH v2 3/4] Add AArch64 ZynpMP BSP

[Kinsey Moore]

This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC
(ZynqMP) family of chips. It is configured to be usable on the Qemu
ZCU102 machine definition and should be almost trivially portable to
ZynqMP development boards and custom hardware. It is also configured to
be usable with libbsd.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  | 134 ++
 bsps/aarch64/xilinx-zynqmp/include/bsp.h  |  74 ++
 bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h  |  72 ++
 bsps/aarch64/xilinx-zynqmp/include/tm27.h |  46 ++
 bsps/aarch64/xilinx-zynqmp/start/bspstart.c   |  49 +++
 .../xilinx-zynqmp/start/bspstarthooks.c   |  51 +++
 spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml |  22 +++
 .../aarch64/xilinx-zynqmp/bspqemuilp32.yml|  21 +++
 .../aarch64/xilinx-zynqmp/bspqemulp64.yml |  21 +++
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |  44 ++
 .../aarch64/xilinx-zynqmp/linkcmds_ilp32.yml  |  72 ++
 .../aarch64/xilinx-zynqmp/linkcmds_lp64.yml   |  71 ++
 spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml |  37 +
 .../bsps/aarch64/xilinx-zynqmp/optclkuart.yml |  20 +++
 .../bsps/aarch64/xilinx-zynqmp/optloadoff.yml |  18 +++
 .../aarch64/xilinx-zynqmp/optnocachelen.yml   |  18 +++
 .../bsps/aarch64/xilinx-zynqmp/optramlen.yml  |  18 +++
 .../bsps/aarch64/xilinx-zynqmp/optramori.yml  |  18 +++
 .../bsps/aarch64/xilinx-zynqmp/tstqemu.yml|  53 +++
 spec/build/bsps/arm/xilinx-zynq/grp.yml   |   2 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |   2 +-
 .../bsps/arm/xilinx-zynqmp/optconminor.yml|  15 --
 .../{arm/xilinx-zynq => }/optconminor.yml |   0
 23 files changed, 861 insertions(+), 17 deletions(-)
 create mode 100644 bsps/aarch64/xilinx-zynqmp/console/console.c
 create mode 100644 bsps/aarch64/xilinx-zynqmp/include/bsp.h
 create mode 100644 bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
 create mode 100644 bsps/aarch64/xilinx-zynqmp/include/tm27.h
 create mode 100644 bsps/aarch64/xilinx-zynqmp/start/bspstart.c
 create mode 100644 bsps/aarch64/xilinx-zynqmp/start/bspstarthooks.c
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/bspqemuilp32.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/bspqemulp64.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optclkuart.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/tstqemu.yml
 delete mode 100644 spec/build/bsps/arm/xilinx-zynqmp/optconminor.yml
 rename spec/build/bsps/{arm/xilinx-zynq => }/optconminor.yml (100%)

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
new file mode 100644
index 00..a22a194782
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64XilinxZynqMP
+ *
+ * @brief This source file contains this BSP's console configuration.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF T

[PATCH v3] samples/unlimited: Prevent compile error

[Kinsey Moore]

For architectures with relatively large minimum stack sizes, this test
breaks during compilation due to a static check. The init task stack
size should not need to be set for this test.
---
 testsuites/samples/unlimited/system.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/testsuites/samples/unlimited/system.h 
b/testsuites/samples/unlimited/system.h
index 2624a696df..4138b658fe 100644
--- a/testsuites/samples/unlimited/system.h
+++ b/testsuites/samples/unlimited/system.h
@@ -50,7 +50,6 @@ extern void test3(void);
 #define TASK_ALLOCATION_SIZE (5)
 #define CONFIGURE_UNLIMITED_OBJECTS
 #define CONFIGURE_UNLIMITED_ALLOCATION_SIZE TASK_ALLOCATION_SIZE
-#define CONFIGURE_INIT_TASK_STACK_SIZE (8 * 1024)
 
 
 #include 
-- 
2.20.1

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[PATCH v3] zynq-uart: Fix set_attributes implementation

[Kinsey Moore]

The zynq-uart set_attributes implementation was configured to always
return false which causes spconsole01 to fail. This restores the
disabled implementation which sets the baud rate registers
appropriately and allows spconsole01 to pass. This also expands the
set_attributes functionality to allow setting of the stop bits,
character width, and parity.
---
 bsps/include/dev/serial/zynq-uart.h   |  7 +++
 bsps/shared/dev/serial/zynq-uart-polled.c |  2 +-
 bsps/shared/dev/serial/zynq-uart.c| 64 +--
 3 files changed, 67 insertions(+), 6 deletions(-)

diff --git a/bsps/include/dev/serial/zynq-uart.h 
b/bsps/include/dev/serial/zynq-uart.h
index 2c0f250a3a..0eb1dd5f29 100644
--- a/bsps/include/dev/serial/zynq-uart.h
+++ b/bsps/include/dev/serial/zynq-uart.h
@@ -78,6 +78,13 @@ void zynq_uart_write_polled(
   */
 void zynq_uart_reset_tx_flush(zynq_uart_context *ctx);
 
+int zynq_cal_baud_rate(
+  uint32_t  baudrate,
+  uint32_t* brgr,
+  uint32_t* bauddiv,
+  uint32_t  modereg
+);
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/bsps/shared/dev/serial/zynq-uart-polled.c 
b/bsps/shared/dev/serial/zynq-uart-polled.c
index a1b51ea521..442431d502 100644
--- a/bsps/shared/dev/serial/zynq-uart-polled.c
+++ b/bsps/shared/dev/serial/zynq-uart-polled.c
@@ -40,7 +40,7 @@ uint32_t zynq_uart_input_clock(void)
   return ZYNQ_CLOCK_UART;
 }
 
-static int zynq_cal_baud_rate(uint32_t  baudrate,
+int zynq_cal_baud_rate(uint32_t  baudrate,
   uint32_t* brgr,
   uint32_t* bauddiv,
   uint32_t  modereg)
diff --git a/bsps/shared/dev/serial/zynq-uart.c 
b/bsps/shared/dev/serial/zynq-uart.c
index 41adb196ab..39e2e65924 100644
--- a/bsps/shared/dev/serial/zynq-uart.c
+++ b/bsps/shared/dev/serial/zynq-uart.c
@@ -142,25 +142,79 @@ static bool zynq_uart_set_attributes(
   const struct termios *term
 )
 {
-#if 0
-  volatile zynq_uart *regs = zynq_uart_get_regs(minor);
+  zynq_uart_context *ctx = (zynq_uart_context *) context;
+  volatile zynq_uart *regs = ctx->regs;
   uint32_t brgr = 0;
   uint32_t bauddiv = 0;
+  uint32_t mode = 0;
   int rc;
 
   rc = zynq_cal_baud_rate(115200, &brgr, &bauddiv, regs->mode);
   if (rc != 0)
 return rc;
 
+  /*
+   * Configure the mode register
+   */
+  mode |= ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL);
+
+  /*
+   * Parity
+   */
+
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE);
+  if (term->c_cflag & PARENB) {
+if (!(term->c_cflag & PARODD)) {
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD);
+} else {
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN);
+}
+  }
+
+  /*
+   * Character Size
+   */
+
+  if (term->c_cflag & CSIZE) {
+switch (term->c_cflag & CSIZE)
+{
+case CS6:
+  mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_6);
+  break;
+case CS7:
+  mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_7);
+  break;
+case CS8:
+  mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
+  break;
+default:
+  return false;
+}
+  } else {
+/* default to 9600,8,N,1 */
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
+  }
+
+  /*
+   * Stop Bits
+   */
+
+  if (term->c_cflag & CSTOPB) {
+/* 2 stop bits */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_2);
+  } else {
+/* 1 stop bit */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_1);
+  }
+
+
   regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
+  regs->mode = mode;
   regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
   regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
   regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
 
   return true;
-#else
-  return false;
-#endif
 }
 
 const rtems_termios_device_handler zynq_uart_handler = {
-- 
2.20.1

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RE: [PATCH v3] zynq-uart: Fix set_attributes implementation

[Kinsey Moore]

From: Gedare Bloom 
Sent: Thursday, December 3, 2020 10:43
To: Sebastian Huber 
Cc: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v3] zynq-uart: Fix set_attributes implementation



On Thu, Dec 3, 2020 at 8:32 AM Sebastian Huber 
mailto:sebastian.hu...@embedded-brains.de>> 
wrote:
On 03/12/2020 16:25, Kinsey Moore wrote:

> The zynq-uart set_attributes implementation was configured to always
> return false which causes spconsole01 to fail. This restores the
> disabled implementation which sets the baud rate registers
> appropriately and allows spconsole01 to pass. This also expands the
> set_attributes functionality to allow setting of the stop bits,
> character width, and parity.

The patch is fine from my point of view.

The coding style is not in line with the RTEMS Project guidelines.
Should we even review patches with respect to the coding style?

I don't keep it strict in the bsps/ area.

Hopefully, we can make tools help us ;)

I was mostly trying to match similar code in the same area of the codebase, but 
I’ll do some cleanup as per Gedare’s other email and submit a hopefully final 
version. I look forward to having a pre-commit hook that yells at me for 
improper code formatting (or just fixes it blindly).

Kinsey
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RE: [PATCH v3] zynq-uart: Fix set_attributes implementation

[Kinsey Moore]

From: Gedare Bloom 
Sent: Thursday, December 3, 2020 12:51
To: Kinsey Moore 
Cc: devel@rtems.org
Subject: Re: [PATCH v3] zynq-uart: Fix set_attributes implementation

On Thu, Dec 3, 2020 at 9:46 AM Gedare Bloom 
mailto:ged...@rtems.org>> wrote:

On Thu, Dec 3, 2020 at 8:25 AM Kinsey Moore 
mailto:kinsey.mo...@oarcorp.com>> wrote:

+{
+case CS6:
+  mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_6);
+  break;
+case CS7:
+  mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_7);
+  break;
+case CS8:
  case 0:
+  mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
+  break;
+default:
+  return false;
One more thing, I think this default case is dead code and can be removed.

That’s there to catch use of character size 5 which isn’t supported by the 
Cadence/Zynq UART driver.

Kinsey
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[PATCH v4] zynq-uart: Fix set_attributes implementation

[Kinsey Moore]

The zynq-uart set_attributes implementation was configured to always
return false which causes spconsole01 to fail. This restores the
disabled implementation which sets the baud rate registers
appropriately and allows spconsole01 to pass. This also expands the
set_attributes functionality to allow setting of the stop bits,
character width, and parity.
---
 bsps/include/dev/serial/zynq-uart.h   |  7 +++
 bsps/shared/dev/serial/zynq-uart-polled.c |  2 +-
 bsps/shared/dev/serial/zynq-uart.c| 56 +--
 3 files changed, 59 insertions(+), 6 deletions(-)

diff --git a/bsps/include/dev/serial/zynq-uart.h 
b/bsps/include/dev/serial/zynq-uart.h
index 2c0f250a3a..0eb1dd5f29 100644
--- a/bsps/include/dev/serial/zynq-uart.h
+++ b/bsps/include/dev/serial/zynq-uart.h
@@ -78,6 +78,13 @@ void zynq_uart_write_polled(
   */
 void zynq_uart_reset_tx_flush(zynq_uart_context *ctx);
 
+int zynq_cal_baud_rate(
+  uint32_t  baudrate,
+  uint32_t* brgr,
+  uint32_t* bauddiv,
+  uint32_t  modereg
+);
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/bsps/shared/dev/serial/zynq-uart-polled.c 
b/bsps/shared/dev/serial/zynq-uart-polled.c
index a1b51ea521..442431d502 100644
--- a/bsps/shared/dev/serial/zynq-uart-polled.c
+++ b/bsps/shared/dev/serial/zynq-uart-polled.c
@@ -40,7 +40,7 @@ uint32_t zynq_uart_input_clock(void)
   return ZYNQ_CLOCK_UART;
 }
 
-static int zynq_cal_baud_rate(uint32_t  baudrate,
+int zynq_cal_baud_rate(uint32_t  baudrate,
   uint32_t* brgr,
   uint32_t* bauddiv,
   uint32_t  modereg)
diff --git a/bsps/shared/dev/serial/zynq-uart.c 
b/bsps/shared/dev/serial/zynq-uart.c
index 41adb196ab..8f17d3ca65 100644
--- a/bsps/shared/dev/serial/zynq-uart.c
+++ b/bsps/shared/dev/serial/zynq-uart.c
@@ -142,25 +142,71 @@ static bool zynq_uart_set_attributes(
   const struct termios *term
 )
 {
-#if 0
-  volatile zynq_uart *regs = zynq_uart_get_regs(minor);
+  zynq_uart_context *ctx = (zynq_uart_context *) context;
+  volatile zynq_uart *regs = ctx->regs;
   uint32_t brgr = 0;
   uint32_t bauddiv = 0;
+  uint32_t mode = 0;
   int rc;
 
   rc = zynq_cal_baud_rate(115200, &brgr, &bauddiv, regs->mode);
   if (rc != 0)
 return rc;
 
+  /*
+   * Configure the mode register
+   */
+  mode |= ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL);
+
+  /*
+   * Parity
+   */
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE);
+  if (term->c_cflag & PARENB) {
+if (!(term->c_cflag & PARODD)) {
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD);
+} else {
+  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN);
+}
+  }
+
+  /*
+   * Character Size
+   */
+  switch (term->c_cflag & CSIZE)
+  {
+  case CS5:
+return false;
+  case CS6:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_6);
+break;
+  case CS7:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_7);
+break;
+  case CS8:
+  default:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
+break;
+  }
+
+  /*
+   * Stop Bits
+   */
+  if (term->c_cflag & CSTOPB) {
+/* 2 stop bits */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_2);
+  } else {
+/* 1 stop bit */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_1);
+  }
+
   regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
+  regs->mode = mode;
   regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
   regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
   regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
 
   return true;
-#else
-  return false;
-#endif
 }
 
 const rtems_termios_device_handler zynq_uart_handler = {
-- 
2.20.1

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[PATCH v1] spec: Move zynq-uart into its own object

[Kinsey Moore]

Currently, zynq-uart code is always built and has some requirements for
BSPs that use it. Instead of making all BSPs satisfy that requirement or
working around it by setting defaults, this moves the zynq-uart code
into its own spec build object so it can be included if needed.
---
 bsps/include/dev/serial/zynq-uart.h   |  4 
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |  2 ++
 spec/build/bsps/arm/xilinx-zynq/grp.yml   |  2 ++
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  2 ++
 spec/build/bsps/obj.yml   |  4 
 spec/build/bsps/objdevserialzynq.yml  | 19 +++
 6 files changed, 25 insertions(+), 8 deletions(-)
 create mode 100644 spec/build/bsps/objdevserialzynq.yml

diff --git a/bsps/include/dev/serial/zynq-uart.h 
b/bsps/include/dev/serial/zynq-uart.h
index 0eb1dd5f29..220d9b7717 100644
--- a/bsps/include/dev/serial/zynq-uart.h
+++ b/bsps/include/dev/serial/zynq-uart.h
@@ -60,10 +60,6 @@ extern const rtems_termios_device_handler zynq_uart_handler;
 
 #define ZYNQ_UART_DEFAULT_BAUD 115200
 
-#ifndef ZYNQ_CLOCK_UART
-#define ZYNQ_CLOCK_UART 1
-#endif
-
 void zynq_uart_initialize(rtems_termios_device_context *base);
 
 int zynq_uart_read_polled(rtems_termios_device_context *base);
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml 
b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
index 499947eddf..552723c61c 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
@@ -31,6 +31,8 @@ links:
   uid: ../../obj
 - role: build-dependency
   uid: ../../objirq
+- role: build-dependency
+  uid: ../../objdevserialzynq
 - role: build-dependency
   uid: ../../optcachedata
 - role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml 
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 47f38ebcfd..a0580619f0 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -55,6 +55,8 @@ links:
   uid: ../../obj
 - role: build-dependency
   uid: ../../objirq
+- role: build-dependency
+  uid: ../../objdevserialzynq
 - role: build-dependency
   uid: linkcmds
 - role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml 
b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index 0704c691b2..95cbc51436 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -67,6 +67,8 @@ links:
   uid: ../../obj
 - role: build-dependency
   uid: ../../objirq
+- role: build-dependency
+  uid: ../../objdevserialzynq
 - role: build-dependency
   uid: ../../opto2
 - role: build-dependency
diff --git a/spec/build/bsps/obj.yml b/spec/build/bsps/obj.yml
index 7ea560b47d..a454783d51 100644
--- a/spec/build/bsps/obj.yml
+++ b/spec/build/bsps/obj.yml
@@ -52,8 +52,6 @@ install:
   source:
   - bsps/include/dev/serial/arm-pl011-regs.h
   - bsps/include/dev/serial/arm-pl011.h
-  - bsps/include/dev/serial/zynq-uart-regs.h
-  - bsps/include/dev/serial/zynq-uart.h
 - destination: ${BSP_INCLUDEDIR}/rtems/zilog
   source:
   - bsps/include/rtems/zilog/z8036.h
@@ -96,8 +94,6 @@ source:
 - bsps/shared/dev/serial/ns16550.c
 - bsps/shared/dev/serial/ns16550-context.c
 - bsps/shared/dev/serial/serprobe.c
-- bsps/shared/dev/serial/zynq-uart.c
-- bsps/shared/dev/serial/zynq-uart-polled.c
 - bsps/shared/start/bootcard.c
 - bsps/shared/rtems-version.c
 type: build
diff --git a/spec/build/bsps/objdevserialzynq.yml 
b/spec/build/bsps/objdevserialzynq.yml
new file mode 100644
index 00..e890ebc459
--- /dev/null
+++ b/spec/build/bsps/objdevserialzynq.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/serial
+  source:
+  - bsps/include/dev/serial/zynq-uart-regs.h
+  - bsps/include/dev/serial/zynq-uart.h
+links: []
+source:
+- bsps/shared/dev/serial/zynq-uart.c
+- bsps/shared/dev/serial/zynq-uart-polled.c
+type: build
-- 
2.20.1

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