Re: [rtems commit] libdl: Add support to import base image TLS symbols
On 14.09.23 23:56, Chris Johns wrote: On 14/9/2023 7:33 pm, Sebastian Huber wrote: On 14.09.23 10:51, Chris Johns wrote: On 14/9/2023 5:58 pm, Sebastian Huber wrote: On 14.09.23 09:38, Chris Johns wrote: The issue I faced was no score interface to get the TLS base for a thread to determine a symbol's offset. If we had that and something to say if TLS is supported libdl would be easy to fix. Why don't we add this interface if it simplifies things? Yes please, that would be good. I do not know the TSL support well enough to do a decent job of it. Which interface do you need? A define that says TLS is support for an arch? A call that returns the base address for an arch? I have added some in libdl: https://git.rtems.org/rtems/tree/cpukit/libdl/rtl-tls.c however having this in score would mean a new arch does not break libdl. Yes, this should be definitely added to the CPU port. What is the purpose of rtems_rtl_tls_get_base()? It seems to be unused. It is used by the symbol table loader so is referenced in the symbol table generated code ... https://git.rtems.org/rtems-tools/tree/linkers/rtems-syms.cpp#n66 https://git.rtems.org/rtems-tools/tree/linkers/rtems-syms.cpp#n319 A TLS symbol is an offset into the TLS area. I encountered two problems. First I could not find a way to equate a TLS symbol offset to a label in asm or C and second the offsets move with each link phase and with the 2 stage linking the offsets move. As a result the offset needs to be computer at runtime. To do this the base image TLS symbols each get a small piece of code that determines the offset at runtime. The symbol table in the target contains the TLS area offset in an arch ABI specific format. The relocs know how to handle the offset the symbol holds. It would be really nice to have a Doxygen comment for rtems_rtl_tls_get_base() which contains this information. There are also no test cases for this function. Without test cases it is easy to break something without knowing it. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/2] libdl: Use _CPU_Get_TLS_thread_pointer()
Update #4920.
---
cpukit/libdl/rtl-tls.c | 73 --
1 file changed, 6 insertions(+), 67 deletions(-)
diff --git a/cpukit/libdl/rtl-tls.c b/cpukit/libdl/rtl-tls.c
index 95ca47fe6a..7eb12831eb 100644
--- a/cpukit/libdl/rtl-tls.c
+++ b/cpukit/libdl/rtl-tls.c
@@ -13,6 +13,8 @@
/*
* COPYRIGHT (c) 2023 Chris Johns
*
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -41,74 +43,11 @@
#include "rtl-tls.h"
-/*
- * The cpukit/score should provide a call for any arch that
- * supports TLS. This code is here until that happens if it
- * happens.
- */
-
-/*
- * Pasted in from:
- *
- *
https://android.googlesource.com/platform/bionic/+/refs/heads/main/libc/platform/bionic/tls.h
- *
- * Note, "#pragma once" has been removed
- */
-/*
- * Copyright (C) 2008 The Android Open Source Project
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * * Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in
- *the documentation and/or other materials provided with the
- *distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-#if defined(__aarch64__)
-# define __get_tls() ({ void** __val; __asm__("mrs %0, tpidr_el0" :
"=r"(__val)); __val; })
-#elif defined(__arm__)
-# define __get_tls() ({ void** __val; __asm__("mrc p15, 0, %0, c13, c0, 3" :
"=r"(__val)); __val; })
-#elif defined(__i386__)
-# define __get_tls() ({ void** __val; __asm__("movl %%gs:0, %0" :
"=r"(__val)); __val; })
-#elif defined(__riscv)
-# define __get_tls() ({ void** __val; __asm__("mv %0, tp" : "=r"(__val));
__val; })
-#elif defined(__x86_64__)
-# define __get_tls() ({ void** __val; __asm__("mov %%fs:0, %0" : "=r"(__val));
__val; })
-#elif defined(__sparc__)
-#include
-# define __get_tls() ({ void** __val; register uintptr_t g7 __asm__( "g7" );
__val = (void**) g7; __val; })
-#elif defined(__powerpc__)
-#include
-# define __get_tls() ({ void** __val; register uintptr_t tp __asm__( "2" );
__val = (void**) tp; __val; })
-#elif defined(__m68k__) || defined(__v850__) || defined(__microblaze__)
-/* No TLS support */
-# define __get_tls() (void*) 0UL
-#else
-#error unsupported architecture
-#endif
-
-#if defined(__get_tls)
+#include
+#include
+#include
void* rtems_rtl_tls_get_base (void)
{
- return (void*) __get_tls();
+ return _CPU_Get_TLS_thread_pointer (&_Thread_Get_executing()->Registers);
}
-
-#endif
--
2.35.3
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[PATCH 1/2] score: Add _CPU_Get_TLS_thread_pointer()
Add _CPU_Get_TLS_thread_pointer() to get the thread pointer which is
used to get the address of thread-local storage objects associated with
a thread.
Update #4920.
---
.../cpu/aarch64/include/rtems/score/cpuimpl.h | 7
.../cpu/arm/include/rtems/score/cpuimpl.h | 7
.../cpu/bfin/include/rtems/score/cpuimpl.h| 8 +
.../cpu/i386/include/rtems/score/cpuimpl.h| 7
.../cpu/lm32/include/rtems/score/cpuimpl.h| 8 +
.../cpu/m68k/include/rtems/score/cpuimpl.h| 7
.../microblaze/include/rtems/score/cpuimpl.h | 7
.../cpu/mips/include/rtems/score/cpuimpl.h| 8 +
.../cpu/moxie/include/rtems/score/cpuimpl.h | 8 +
.../cpu/nios2/include/rtems/score/cpuimpl.h | 7
.../cpu/no_cpu/include/rtems/score/cpuimpl.h | 16 +
.../cpu/or1k/include/rtems/score/cpuimpl.h| 8 +
.../cpu/powerpc/include/rtems/score/cpuimpl.h | 7
.../cpu/riscv/include/rtems/score/cpuimpl.h | 7
.../cpu/sh/include/rtems/score/cpuimpl.h | 8 +
.../cpu/sparc/include/rtems/score/cpuimpl.h | 7
.../cpu/sparc64/include/rtems/score/cpuimpl.h | 8 +
.../cpu/v850/include/rtems/score/cpuimpl.h| 8 +
.../cpu/x86_64/include/rtems/score/cpuimpl.h | 8 +
testsuites/sptests/sptls01/init.c | 33 +++
20 files changed, 184 insertions(+)
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
index b520e8bffb..095c5db5b9 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
@@ -174,6 +174,13 @@ static inline void _CPU_Use_thread_local_storage(
);
}
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->thread_id;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
index f9b40889f5..04d23f0ea7 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
@@ -178,6 +178,13 @@ static inline void _CPU_Use_thread_local_storage(
#endif
}
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->thread_id;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
index aaf34a3ce0..5a445d9420 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
@@ -72,6 +72,14 @@ static inline void _CPU_Use_thread_local_storage(
(void) context;
}
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
index ba5d820016..da38ecacf7 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
@@ -112,6 +112,13 @@ static inline void _CPU_Use_thread_local_storage(
);
}
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) &context->gs;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
index 870640864c..70a1db1d4d 100644
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
@@ -71,6 +71,14 @@ static inline void _CPU_Use_thread_local_storage(
(void) context;
}
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
index 4bee157215..521e9fc4c2 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
@@ -95,6 +95,13 @@ static inline void _CPU_Use_thread_local_storage(
(void) context;
}
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->thread_pointer;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
index 4e315e856d..760ebbfbbb 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
@@ -100,6 +100,13 @@ static inline void _CPU_Use_thread_local_storage(
(void) context;
}
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
[PATCH 3/6] bsps/leon3: Make GPTIMER fall back mandatory
Update #4954.
---
bsps/sparc/leon3/clock/ckinit.c | 35 ++--
bsps/sparc/leon3/include/bsp/leon3.h | 4
bsps/sparc/leon3/start/cpucounter.c | 2 +-
3 files changed, 3 insertions(+), 38 deletions(-)
diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index eea4649fa3..d800f01e4a 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -69,19 +69,6 @@ static struct timecounter leon3_tc;
static void leon3_tc_tick_default(void)
{
-#if !defined(RTEMS_SMP)
- SPARC_Counter *counter;
- rtems_interrupt_level level;
-
- counter = &_SPARC_Counter;
- rtems_interrupt_local_disable(level);
-
- grlib_store_32(&LEON3_IrqCtrl_Regs->iclear, counter->pending_mask);
- counter->accumulated += counter->interval;
-
- rtems_interrupt_local_enable(level);
-#endif
-
rtems_timecounter_tick();
}
@@ -238,29 +225,11 @@ static void leon3_clock_use_gptimer(
gptimer_timer *timer
)
{
-#ifdef RTEMS_SMP
/*
- * The GR712RC for example has no timestamp unit in the interrupt
- * controller. At least on SMP configurations we must use a second timer
- * in free running mode for the timecounter. The timer is initialized by
- * leon3_counter_initialize().
+ * As a fall back, use a second timer in free-running mode for the
+ * timecounter. The timer is initialized by leon3_counter_initialize().
*/
tc->tc_get_timecount = _SPARC_Get_timecount_down;
-#else
- SPARC_Counter *counter;
-
- counter = &_SPARC_Counter;
- counter->read_isr_disabled = _SPARC_Counter_read_clock_isr_disabled;
- counter->read = _SPARC_Counter_read_clock;
- counter->counter_register = &timer->tcntval;
- counter->pending_register = &LEON3_IrqCtrl_Regs->ipend;
- counter->pending_mask = UINT32_C(1) << clkirq;
- counter->accumulated = rtems_configuration_get_microseconds_per_tick();
- counter->interval = rtems_configuration_get_microseconds_per_tick();
-
- tc->tc_get_timecount = _SPARC_Get_timecount_clock;
-#endif
-
tc->tc_frequency = LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER,
rtems_timecounter_install(tc);
diff --git a/bsps/sparc/leon3/include/bsp/leon3.h
b/bsps/sparc/leon3/include/bsp/leon3.h
index fdb43b5817..84790b590f 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -188,11 +188,7 @@ static inline uint32_t leon3_get_cpu_count( const irqamp
*regs )
* @brief This constant defines the index of the GPTIMER timer used by the
* CPU counter if the CPU counter uses the GPTIMER.
*/
-#if defined(RTEMS_SMP)
#define LEON3_COUNTER_GPTIMER_INDEX ( LEON3_CLOCK_INDEX + 1 )
-#else
-#define LEON3_COUNTER_GPTIMER_INDEX LEON3_CLOCK_INDEX
-#endif
/**
* @brief This constant defines the frequency set by the boot loader of the
diff --git a/bsps/sparc/leon3/start/cpucounter.c
b/bsps/sparc/leon3/start/cpucounter.c
index a6db7677a3..374e43c9b1 100644
--- a/bsps/sparc/leon3/start/cpucounter.c
+++ b/bsps/sparc/leon3/start/cpucounter.c
@@ -89,7 +89,7 @@ static void leon3_counter_use_gptimer(SPARC_Counter *counter,
gptimer *gpt)
counter->read = _SPARC_Counter_read_down;
counter->counter_register = &timer->tcntval;
- /* Make timer free running */
+ /* Make timer free-running */
grlib_store_32(&timer->trldval, 0x);
grlib_store_32(&timer->tctrl, GPTIMER_TCTRL_EN | GPTIMER_TCTRL_RS);
--
2.35.3
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[PATCH 1/6] bsps/leon3: Optional IRQ(A)MP timestamp support
This is necessary to run the tests on SIS with profiling enabled.
Update #4954.
---
bsps/include/bsp/fatal.h| 1 -
bsps/sparc/leon3/clock/ckinit.c | 6 ++
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h
index 4b7d0f6ced..1726bfea54 100644
--- a/bsps/include/bsp/fatal.h
+++ b/bsps/include/bsp/fatal.h
@@ -91,7 +91,6 @@ typedef enum {
LEON3_FATAL_CLOCK_INITIALIZATION,
LEON3_FATAL_INVALID_CACHE_CONFIG_BOOT_PROCESSOR,
LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR,
- LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT,
/* LPC24XX fatal codes */
LPC24XX_FATAL_PL111_SET_UP = BSP_FATAL_CODE_BLOCK(3),
diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index c335652a56..cff2991e60 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -196,11 +196,9 @@ static void leon3_clock_use_up_counter(struct timecounter
*tc)
tc->tc_frequency = leon3_up_counter_frequency();
#if defined(RTEMS_PROFILING)
- if (irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs) == NULL) {
-bsp_fatal(LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT);
+ if (irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs) != NULL) {
+leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init;
}
-
- leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init;
#endif
rtems_timecounter_install(tc);
--
2.35.3
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[PATCH 2/6] sparc: Move CPU counter implementation
Enable a BSP-specific CPU counter implementation.
Update #4954.
---
bsps/sparc/erc32/clock/ckinit.c | 9 +--
.../sparc/include/bsp/sparc-counter.h | 57 +--
bsps/sparc/leon2/clock/ckinit.c | 8 +--
bsps/sparc/leon3/clock/ckinit.c | 6 +-
bsps/sparc/leon3/start/cpucounter.c | 4 +-
.../sparc/shared/start}/sparc-counter-asm.S | 28 -
cpukit/score/cpu/sparc/cpu_asm.S | 6 +-
.../score/cpu/sparc/include/rtems/score/cpu.h | 26 +
.../cpu/sparc/include/rtems/score/cpuimpl.h | 7 +++
spec/build/bsps/sparc/erc32/bsperc32.yml | 2 +
spec/build/bsps/sparc/leon2/obj.yml | 2 +
spec/build/bsps/sparc/leon3/obj.yml | 2 +
spec/build/cpukit/cpusparc.yml| 2 -
13 files changed, 83 insertions(+), 76 deletions(-)
rename cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h =>
bsps/sparc/include/bsp/sparc-counter.h (69%)
rename {cpukit/score/cpu/sparc => bsps/sparc/shared/start}/sparc-counter-asm.S
(86%)
diff --git a/bsps/sparc/erc32/clock/ckinit.c b/bsps/sparc/erc32/clock/ckinit.c
index 83cafb73c3..a3009efce8 100644
--- a/bsps/sparc/erc32/clock/ckinit.c
+++ b/bsps/sparc/erc32/clock/ckinit.c
@@ -23,10 +23,11 @@
*/
#include
+#include
#include
#include
#include
-#include
+#include
extern int CLOCK_SPEED;
@@ -46,7 +47,7 @@ static void erc32_clock_init( void )
rtems_timecounter_install(tc);
}
-uint32_t _CPU_Counter_frequency(void)
+uint32_t _CPU_Counter_frequency( void )
{
return ERC32_REAL_TIME_CLOCK_FREQUENCY;
}
@@ -56,7 +57,7 @@ static void erc32_clock_at_tick( void )
SPARC_Counter *counter;
rtems_interrupt_level level;
- counter = &_SPARC_Counter_mutable;
+ counter = &_SPARC_Counter;
rtems_interrupt_local_disable(level);
ERC32_Clear_interrupt( ERC32_INTERRUPT_REAL_TIME_CLOCK );
@@ -83,7 +84,7 @@ static void erc32_clock_initialize_early( void )
ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO
);
- counter = &_SPARC_Counter_mutable;
+ counter = &_SPARC_Counter;
counter->read_isr_disabled = _SPARC_Counter_read_clock_isr_disabled;
counter->read = _SPARC_Counter_read_clock;
counter->counter_register = &ERC32_MEC.Real_Time_Clock_Counter,
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h
b/bsps/sparc/include/bsp/sparc-counter.h
similarity index 69%
rename from cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h
rename to bsps/sparc/include/bsp/sparc-counter.h
index d9be984179..a659aa98c5 100644
--- a/cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h
+++ b/bsps/sparc/include/bsp/sparc-counter.h
@@ -33,8 +33,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTEMS_SCORE_SPARCIMPL_H
-#define _RTEMS_SCORE_SPARCIMPL_H
+#ifndef _BSP_SPARC_COUNTER_H
+#define _BSP_SPARC_COUNTER_H
#include
@@ -44,13 +44,6 @@ extern "C" {
struct timecounter;
-/*
- * Provides a mutable alias to _SPARC_Counter for use in
- * _SPARC_Counter_initialize(). The _SPARC_Counter and _SPARC_Counter_mutable
- * are defined via the SPARC_COUNTER_DEFINITION define.
- */
-extern SPARC_Counter _SPARC_Counter_mutable;
-
void _SPARC_Counter_at_tick_clock( void );
CPU_Counter_ticks _SPARC_Counter_read_default( void );
@@ -73,33 +66,35 @@ uint32_t _SPARC_Get_timecount_clock( struct timecounter * );
uint32_t _SPARC_Get_timecount_asr23( struct timecounter * );
+typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void );
+
/*
- * Defines the _SPARC_Counter and _SPARC_Counter_mutable global variables.
- * Place this define in the global file scope of the CPU counter support file
- * of the BSP.
+ * The SPARC processors supported by RTEMS have no built-in CPU counter
+ * support. We have to use some hardware counter module for this purpose, for
+ * example the GPTIMER instance used by the clock driver. The BSP must provide
+ * an implementation of the CPU counter read function. This allows the use of
+ * dynamic hardware enumeration.
*/
+typedef struct {
+ SPARC_Counter_readread_isr_disabled;
+ SPARC_Counter_readread;
+ volatile const CPU_Counter_ticks *counter_register;
+ volatile const uint32_t *pending_register;
+ uint32_t pending_mask;
+ CPU_Counter_ticks accumulated;
+ CPU_Counter_ticks interval;
+} SPARC_Counter;
+
+extern SPARC_Counter _SPARC_Counter;
+
#define SPARC_COUNTER_DEFINITION \
- __asm__ ( \
-"\t.global\t_SPARC_Counter\n" \
-"\t.global\t_SPARC_Counter_mutable\n" \
-"\t.section\t.data._SPARC_Counter,\"aw\",@progbits\n" \
-"\t.align\t4\n" \
-"\t.type\t_SPARC_Counter, #object\n" \
-"\t.size\t_SPARC_Counter, 28\n" \
-"_SPARC_Counter:\n" \
-"_SPARC_Counter_mutable:\n" \
-"\t.long\t_SPARC_Counter_read_default\n" \
-"\t.long\t_SPARC_Counter_read_default\n" \
-"\t.long\t0\n" \
-"\t.long\t0\n" \
-"\t.long\t0\n" \
-"\t.long\t0\n" \
-
[PATCH 0/6] sparc: Simplify clock drivers and CPU counter
Sebastian Huber (6):
bsps/leon3: Optional IRQ(A)MP timestamp support
sparc: Move CPU counter implementation
bsps/leon3: Make GPTIMER fall back mandatory
bsps/leon3: Simplify clock and CPU counter
bsps/leon3: Use custom CPU counter implementation
bsps/leon3: Use DSU time tag for GR712RC
bsps/include/bsp/fatal.h | 1 -
bsps/sparc/erc32/clock/ckinit.c | 9 +-
.../sparc/include/bsp/sparc-counter.h | 67 +++---
bsps/sparc/leon2/clock/ckinit.c | 8 +-
bsps/sparc/leon3/clock/ckinit.c | 163 ++
bsps/sparc/leon3/include/bsp/leon3.h | 37 ++-
bsps/sparc/leon3/start/cpucounter.c | 210 ++
.../sparc/shared/start}/sparc-counter-asm.S | 54 ++---
cpukit/score/cpu/sparc/cpu_asm.S | 6 +-
.../score/cpu/sparc/include/rtems/score/cpu.h | 26 +--
.../cpu/sparc/include/rtems/score/cpuimpl.h | 7 +
spec/build/bsps/sparc/erc32/bsperc32.yml | 2 +
spec/build/bsps/sparc/leon2/obj.yml | 2 +
spec/build/bsps/sparc/leon3/grp.yml | 2 +
spec/build/bsps/sparc/leon3/optdsubase.yml| 18 ++
spec/build/cpukit/cpusparc.yml| 2 -
16 files changed, 319 insertions(+), 295 deletions(-)
rename cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h =>
bsps/sparc/include/bsp/sparc-counter.h (59%)
rename {cpukit/score/cpu/sparc => bsps/sparc/shared/start}/sparc-counter-asm.S
(83%)
create mode 100644 spec/build/bsps/sparc/leon3/optdsubase.yml
--
2.35.3
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 4/6] bsps/leon3: Simplify clock and CPU counter
Share the timecounter instance between the clock and the CPU counter.
This greatly simplifies the clock driver since we have to do the device
selection only in one place, the CPU counter support.
Update #4954.
---
bsps/sparc/leon3/clock/ckinit.c | 130 +--
bsps/sparc/leon3/include/bsp/leon3.h | 9 ++
bsps/sparc/leon3/start/cpucounter.c | 46 +++---
3 files changed, 62 insertions(+), 123 deletions(-)
diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index d800f01e4a..c77fd23aff 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -16,7 +16,7 @@
* COPYRIGHT (c) 2004.
* Gaisler Research.
*
- * Copyright (C) 2014, 2018 embedded brains GmbH & Co. KG
+ * Copyright (C) 2014, 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -47,13 +47,8 @@
#include
#include
#include
-#include
#include
-#if !defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
-#include
-#endif
-
/* The LEON3 BSP Timer driver can rely on the Driver Manager if the
* DrvMgr is initialized during startup. Otherwise the classic driver
* must be used.
@@ -65,17 +60,26 @@
/* LEON3 Timer system interrupt number */
static int clkirq;
-static struct timecounter leon3_tc;
+#if defined(RTEMS_PROFILING) && \
+ (defined(LEON3_HAS_ASR_22_23_UP_COUNTER) || \
+ defined(LEON3_PROBE_ASR_22_23_UP_COUNTER) || \
+ defined(LEON3_IRQAMP_PROBE_TIMESTAMP))
+
+#define LEON3_CLOCK_PROBE_IRQAMP_TIMESTAMP
+
+#define IRQMP_TIMESTAMP_S1_S2 ((1U << 25) | (1U << 26))
static void leon3_tc_tick_default(void)
{
rtems_timecounter_tick();
}
-#if defined(RTEMS_PROFILING)
static void (*leon3_tc_tick)(void) = leon3_tc_tick_default;
-#define IRQMP_TIMESTAMP_S1_S2 ((1U << 25) | (1U << 26))
+static void leon3_tc_do_tick(void)
+{
+ (*leon3_tc_tick)();
+}
static void leon3_tc_tick_irqmp_timestamp(void)
{
@@ -124,16 +128,12 @@ static void leon3_tc_tick_irqmp_timestamp_init(void)
rtems_timecounter_tick();
}
-#endif /* RTEMS_PROFILING */
-
+#else
static void leon3_tc_do_tick(void)
{
-#if defined(RTEMS_PROFILING)
- (*leon3_tc_tick)();
-#else
- leon3_tc_tick_default();
-#endif
+ rtems_timecounter_tick();
}
+#endif
#define Adjust_clkirq_for_node() do { clkirq += LEON3_CLOCK_INDEX; } while(0)
@@ -175,74 +175,9 @@ static void
bsp_clock_handler_install(rtems_interrupt_handler isr)
#define Clock_driver_support_set_interrupt_affinity(online_processors) \
bsp_interrupt_set_affinity(clkirq, online_processors)
-#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER) || \
- defined(LEON3_PROBE_ASR_22_23_UP_COUNTER)
-static void leon3_clock_use_up_counter(struct timecounter *tc)
-{
- tc->tc_get_timecount = _SPARC_Get_timecount_asr23;
- tc->tc_frequency = leon3_up_counter_frequency();
-
-#if defined(RTEMS_PROFILING)
- if (irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs) != NULL) {
-leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init;
- }
-#endif
-
- rtems_timecounter_install(tc);
-}
-#endif
-
-#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
-static void leon3_clock_use_irqamp_timestamp(
- struct timecounter *tc,
- irqamp_timestamp *irqmp_ts
-)
-{
- tc->tc_get_timecount = _SPARC_Get_timecount_up;
-#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
- tc->tc_frequency = leon3_processor_local_bus_frequency();
-#else
- tc->tc_frequency = ambapp_freq_get(ambapp_plb(), LEON3_Timer_Adev);
-#endif
-
-#if defined(RTEMS_PROFILING)
- leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init;
-#endif
-
- /*
- * At least one TSISEL field must be non-zero to enable the timestamp
- * counter. Use an arbitrary interrupt source.
- */
- grlib_store_32(&irqmp_ts->itstmpc, IRQAMP_ITSTMPC_TSISEL(1));
-
- rtems_timecounter_install(tc);
-}
-#endif
-
-#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
-static void leon3_clock_use_gptimer(
- struct timecounter *tc,
- gptimer_timer *timer
-)
-{
- /*
- * As a fall back, use a second timer in free-running mode for the
- * timecounter. The timer is initialized by leon3_counter_initialize().
- */
- tc->tc_get_timecount = _SPARC_Get_timecount_down;
- tc->tc_frequency = LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER,
-
- rtems_timecounter_install(tc);
-}
-#endif
-
static void leon3_clock_initialize(void)
{
-#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
- irqamp_timestamp *irqmp_ts;
-#endif
gptimer_timer *timer;
- struct timecounter *tc;
timer = &LEON3_Timer_Regs->timer[LEON3_CLOCK_INDEX];
@@ -255,36 +190,13 @@ static void leon3_clock_initialize(void)
GPTIMER_TCTRL_EN | GPTIMER_TCTRL_RS | GPTIMER_TCTRL_LD | GPTIMER_TCTRL_IE
);
- tc = &leon3_tc;
- tc->tc_counter_mask = 0x;
- tc->tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
-
-#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
- leon3_up_counter_enable();
- leon3_clock_use_up_counter(tc);
-#else
[PATCH 6/6] bsps/leon3: Use DSU time tag for GR712RC
Update #4954.
---
bsps/sparc/leon3/include/bsp/leon3.h | 2 +-
bsps/sparc/leon3/start/cpucounter.c| 63 +++---
spec/build/bsps/sparc/leon3/grp.yml| 2 +
spec/build/bsps/sparc/leon3/optdsubase.yml | 18 +++
4 files changed, 78 insertions(+), 7 deletions(-)
create mode 100644 spec/build/bsps/sparc/leon3/optdsubase.yml
diff --git a/bsps/sparc/leon3/include/bsp/leon3.h
b/bsps/sparc/leon3/include/bsp/leon3.h
index 4ee5531941..449e40c406 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -326,7 +326,7 @@ typedef struct {
*/
uint32_t software_counter;
-#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
+#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER) && !defined(LEON3_DSU_BASE)
/**
* @brief This member may reference a hardware counter register.
*/
diff --git a/bsps/sparc/leon3/start/cpucounter.c
b/bsps/sparc/leon3/start/cpucounter.c
index dbb1797a89..ed8ee5f616 100644
--- a/bsps/sparc/leon3/start/cpucounter.c
+++ b/bsps/sparc/leon3/start/cpucounter.c
@@ -61,7 +61,39 @@ CPU_Counter_ticks _CPU_Counter_read(void)
RTEMS_ALIAS( _CPU_Counter_read )
uint32_t _SPARC_Counter_read_ISR_disabled( void );
-#else /* !LEON3_HAS_ASR_22_23_UP_COUNTER */
+#elif defined(LEON3_DSU_BASE)
+
+static uint32_t leon3_read_dsu_time_tag(void)
+{
+ uint32_t value;
+ volatile uint32_t *reg;
+
+ /* Use a load with a forced cache miss */
+ reg = (uint32_t *) (LEON3_DSU_BASE + 8);
+ __asm__ volatile (
+"\tlda\t[%1]1, %0"
+: "=&r"(value)
+: "r"(reg)
+ );
+ return value << 2;
+}
+
+static uint32_t leon3_timecounter_get_dsu_time_tag(
+ struct timecounter *tc
+)
+{
+ return leon3_read_dsu_time_tag();
+}
+
+CPU_Counter_ticks _CPU_Counter_read(void)
+{
+ return leon3_read_dsu_time_tag();
+}
+
+RTEMS_ALIAS(_CPU_Counter_read)
+uint32_t _SPARC_Counter_read_ISR_disabled(void);
+
+#else /* !LEON3_HAS_ASR_22_23_UP_COUNTER && !LEON3_DSU_BASE */
/*
* This is a workaround for:
@@ -103,7 +135,7 @@ static uint32_t leon3_timecounter_get_counter_up(struct
timecounter *base)
}
#endif
-#endif /* LEON3_HAS_ASR_22_23_UP_COUNTER */
+#endif /* LEON3_HAS_ASR_22_23_UP_COUNTER || LEON3_DSU_BASE */
static uint32_t leon3_timecounter_get_dummy(struct timecounter *base)
{
@@ -139,7 +171,22 @@ static void leon3_counter_use_up_counter(leon3_timecounter
*tc)
}
#endif
-#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
+#if defined(LEON3_DSU_BASE)
+static void leon3_counter_use_dsu_time_tag(leon3_timecounter *tc)
+{
+ uint32_t frequency;
+
+ tc->base.tc_get_timecount = leon3_timecounter_get_dsu_time_tag;
+#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
+ frequency = leon3_processor_local_bus_frequency();
+#else
+ frequency = ambapp_freq_get(ambapp_plb(), LEON3_IrqCtrl_Adev);
+#endif
+ tc->base.tc_frequency = frequency << 2;
+}
+#endif
+
+#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP) && !defined(LEON3_DSU_BASE)
static void leon3_counter_use_irqamp_timestamp(
leon3_timecounter *tc,
irqamp_timestamp *irqmp_ts
@@ -158,7 +205,7 @@ static void leon3_counter_use_irqamp_timestamp(
}
#endif
-#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
+#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER) && !defined(LEON3_DSU_BASE)
static void leon3_counter_use_gptimer(
leon3_timecounter *tc,
gptimer *gpt
@@ -190,7 +237,11 @@ static void leon3_counter_initialize(void)
leon3_up_counter_enable();
leon3_counter_use_up_counter(&leon3_timecounter_instance);
-#else /* !LEON3_HAS_ASR_22_23_UP_COUNTER */
+#elif defined(LEON3_DSU_BASE)
+
+ leon3_counter_use_dsu_time_tag(&leon3_timecounter_instance);
+
+#else /* !LEON3_HAS_ASR_22_23_UP_COUNTER && !LEON3_DSU_BASE */
#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
irqamp_timestamp *irqmp_ts;
@@ -231,7 +282,7 @@ static void leon3_counter_initialize(void)
}
#endif
-#endif /* LEON3_HAS_ASR_22_23_UP_COUNTER */
+#endif /* LEON3_HAS_ASR_22_23_UP_COUNTER || LEON3_DSU_BASE */
}
RTEMS_SYSINIT_ITEM(
diff --git a/spec/build/bsps/sparc/leon3/grp.yml
b/spec/build/bsps/sparc/leon3/grp.yml
index d708a65735..a995ccc60a 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -38,6 +38,8 @@ links:
uid: optasrupcnt
- role: build-dependency
uid: optasrupcntprobe
+- role: build-dependency
+ uid: optdsubase
- role: build-dependency
uid: optgptimerbase
- role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optdsubase.yml
b/spec/build/bsps/sparc/leon3/optdsubase.yml
new file mode 100644
index 00..f528f0ca07
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optdsubase.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2023 embedded brains GmbH & Co. KG
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+default:
+- enabled-by: sparc/gr712rc
+ value: 0x9000
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: LEON3_DSU_BASE
+description: |
+ This option defines t
[PATCH 5/6] bsps/leon3: Use custom CPU counter implementation
Merge the timecounter and CPU counter support for the leon3 BSP family.
Remove now unused functions from the CPU counter support of the erc32
and leon3 BSPs.
Update #4954.
---
bsps/sparc/include/bsp/sparc-counter.h | 12 --
bsps/sparc/leon3/clock/ckinit.c | 2 +-
bsps/sparc/leon3/include/bsp/leon3.h| 26 +++-
bsps/sparc/leon3/start/cpucounter.c | 157 ++--
bsps/sparc/shared/start/sparc-counter-asm.S | 26
spec/build/bsps/sparc/leon3/obj.yml | 2 -
6 files changed, 135 insertions(+), 90 deletions(-)
diff --git a/bsps/sparc/include/bsp/sparc-counter.h
b/bsps/sparc/include/bsp/sparc-counter.h
index a659aa98c5..aba21e3cb1 100644
--- a/bsps/sparc/include/bsp/sparc-counter.h
+++ b/bsps/sparc/include/bsp/sparc-counter.h
@@ -48,24 +48,12 @@ void _SPARC_Counter_at_tick_clock( void );
CPU_Counter_ticks _SPARC_Counter_read_default( void );
-CPU_Counter_ticks _SPARC_Counter_read_up( void );
-
-CPU_Counter_ticks _SPARC_Counter_read_down( void );
-
CPU_Counter_ticks _SPARC_Counter_read_clock_isr_disabled( void );
CPU_Counter_ticks _SPARC_Counter_read_clock( void );
-CPU_Counter_ticks _SPARC_Counter_read_asr23( void );
-
-uint32_t _SPARC_Get_timecount_up( struct timecounter * );
-
-uint32_t _SPARC_Get_timecount_down( struct timecounter * );
-
uint32_t _SPARC_Get_timecount_clock( struct timecounter * );
-uint32_t _SPARC_Get_timecount_asr23( struct timecounter * );
-
typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void );
/*
diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index c77fd23aff..d530f260a8 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -196,7 +196,7 @@ static void leon3_clock_initialize(void)
}
#endif
- rtems_timecounter_install(&leon3_timecounter_instance);
+ rtems_timecounter_install(&leon3_timecounter_instance.base);
}
#define Clock_driver_support_initialize_hardware() \
diff --git a/bsps/sparc/leon3/include/bsp/leon3.h
b/bsps/sparc/leon3/include/bsp/leon3.h
index a5eecdded7..4ee5531941 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2014, 2021 embedded brains GmbH & Co. KG
+ * Copyright (C) 2014, 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -312,12 +312,34 @@ static inline uint32_t leon3_up_counter_frequency( void )
extern apbuart *leon3_debug_uart;
#endif
+/**
+ * @brief Represents the LEON3-specific timecounter.
+ */
+typedef struct {
+ /**
+ * @brief This member contains the base timecounter.
+ */
+ struct timecounter base;
+
+ /**
+ * @brief This member provides a software fall-back counter.
+ */
+ uint32_t software_counter;
+
+#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
+ /**
+ * @brief This member may reference a hardware counter register.
+ */
+ volatile uint32_t *counter_register;
+#endif
+} leon3_timecounter;
+
/**
* @brief Provides the LEON3-specific timecounter.
*
* It is also used by the CPU counter implementation.
*/
-extern struct timecounter leon3_timecounter_instance;
+extern leon3_timecounter leon3_timecounter_instance;
/** @} */
diff --git a/bsps/sparc/leon3/start/cpucounter.c
b/bsps/sparc/leon3/start/cpucounter.c
index 61b767568d..dbb1797a89 100644
--- a/bsps/sparc/leon3/start/cpucounter.c
+++ b/bsps/sparc/leon3/start/cpucounter.c
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2014, 2018 embedded brains GmbH & Co. KG
+ * Copyright (C) 2014, 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -41,78 +41,143 @@
#include
#include
-struct timecounter leon3_timecounter_instance = {
- .tc_counter_mask = 0x,
- .tc_frequency = 10,
- .tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER
+#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER) || \
+ defined(LEON3_PROBE_ASR_22_23_UP_COUNTER)
+static uint32_t leon3_timecounter_get_processor_up_counter(
+ struct timecounter *tc
+)
+{
+ return leon3_up_counter_low();
+}
+#endif
+
+#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
+
+CPU_Counter_ticks _CPU_Counter_read(void)
+{
+ return leon3_up_counter_low();
+}
+
+RTEMS_ALIAS( _CPU_Counter_read )
+uint32_t _SPARC_Counter_read_ISR_disabled( void );
+
+#else /* !LEON3_HAS_ASR_22_23_UP_COUNTER */
+
+/*
+ * This is a workaround for:
+ * https://gcc.gnu.org/bugzilla//show_bug.cgi?id=69027
+ */
+__asm__ (
+ "\t.section\t\".text\"\n"
+ "\t.align\t4\n"
+ "\t.globl\t_CPU_Counter_read\n"
+ "\t.globl\t_SPARC_Counter_read_ISR_disabled\n"
+ "\t.type\t_CPU_Counter_read, #function\n"
+ "\t.type\t_SPARC_Counter_read_ISR_disabled, #function\n"
+ "_CPU_Counter_read:\n"
+ "_SPARC_Counter_read_ISR_disabled:\n"
+ "\tsethi\t%hi(leon3_timeco
Re: Outdated list of BSPs in rtems-tools/config
It will be difficult to replace how well the PowerPC motor controllers work for motor control when the canned, pre-written eTPU code do what you need. It's a great architecture, the DMA chain is well thought out. There is a Bosch "GTM" Generic Timer IP module that is intended to replace the eTPU. I'll look at that to see how close it comes to providing the clean support for motor control coupled to a general purpose processor that the eTPU / PowerPC has. When I see "IP" in a "chip" description I get nervous - I assume Bosch is selling "IP" and the integration is up to the licensor. That said, ARM works well. > On Sep 14, 2023, at 15:22 , o...@c-mauderer.de wrote: > > Hello Peter, > > Am 13.09.23 um 19:22 schrieb Peter Dufault: >>> On Jul 25, 2023, at 10:14 , Joel Sherrill wrote: >>> >>> Most of those are recent and from a lot of different people. GSoC, Kinsey, >>> you, Vijay or Chris, Karel, etc. But I wonder about that phycore_mpc5554. I >>> think it has been around a LONG time. >>> >> I'm cleaning my in-box, and I missed a reference to te Phycore-MPC5554 BSP >> in July. >> I am the one who added the Phycore-mpc5554 as a minor refinement to the >> Freescale MPC55xx embedded board BSPs developed by "eb". >> It *is* time to retire the Phytec board as that board is no longer available. >> But, I hope we can keep it around for a while as I now need to work on a >> follow-up to that BSP. > > That thread was not about retiring or deprecating BSPs. It was about some > missing BSPs in the rtems-tools/config files. So if it is still necessary, I > don't think the BSP should be removed. > >> One of my clients uses the Phycore-MPC5554. They missed the end-of life >> announcement for that board. They need to quickly update to something very >> compatible, and a BSP based on the PHYTEC MPC5674F will work, the MPC5674F >> has all the functionality they require without software changes. >> I'd like to keep the Phycore-MPC5554 BSP alive and kicking while I develop >> equivalent MPC5674F support. > > OK for me. > >> A related question. I think "eb" has a "gwlcfm" target that uses this NXP >> architecture in one of their products. "eb", are you planning another >> "gwlcfm", or are you done with that, and what platform would you move to? >> I'd like to learn about an architecture that works as well as the old >> Motorola architecture does without custom FPGA programming. > > I think it's possible that a new batch of the gwlcfm hardware will be > manufactured in the next few years. But it's quite unlikely that the software > will get an upgrade. > > The question about a good architecture is quite difficult because it's always > quite application specific. > > For RTEMS work that I do, usually a customer already selected a chip (most of > the time some ARM). Therefore, I can't pick a platform that often. For > eb-projects, we usually use NXP or ST chips. On the NXP it would be i.MX or > now also i.MXRT and for ST it's one of the many STM32 chips. > > Personally I would like to play a bit with Risc-V chips. But I haven't found > any time yet. Additionally, it seems that there are still not that many > manufacturers that produce Risc-V chips. > > >> If I leave the old Motorola PowerPC's architecture targeted at engine >> control, I will miss how the ADC DMA chain works together with the eTPU and >> also schedules the output so cleanly do background motor control, and other >> timing intensive applications, so that the main CPU is free to e.g. run >> RTEMS (and in my case position servo control). > > Difficult. Best bet is some NXP chip because they have quite some peripherals > that are still based on the Motorola chips. But I think you know these chips > already and it seems that they are not a good enough replacement. Otherwise, > you wouldn't ask. > > At the moment a lot of chips start to provide two different ARM cores. One > bigger (often Cortex-A; sometimes multicore) and one smaller one (most of the > time Cortex-M). I haven't used both CPUs of these dual CPU systems yet. But > in theory they should allow some quite nice division of tasks: The small CPU > can handle the timing intensive application (maybe with some bare metal > code). The second CPU can handle higher level control and communication. It > would be interesting to implement something like that. > > Best regards > > Christian > >> Peter >> - >> Peter Dufault >> HD Associates, Inc. Software and System Engineering >> ___ >> devel mailing list >> devel@rtems.org >> http://lists.rtems.org/mailman/listinfo/devel Peter - Peter Dufault HD Associates, Inc. Software and System Engineering signature.asc Description: Message signed with OpenPGP ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Outdated list of BSPs in rtems-tools/config
> On Sep 14, 2023, at 15:22 , o...@c-mauderer.de wrote: > > At the moment a lot of chips start to provide two different ARM cores. One > bigger (often Cortex-A; sometimes multicore) and one smaller one (most of the > time Cortex-M). I haven't used both CPUs of these dual CPU systems yet. But > in theory they should allow some quite nice division of tasks: The small CPU > can handle the timing intensive application (maybe with some bare metal > code). The second CPU can handle higher level control and communication. It > would be interesting to implement something like that. I have thought about this. It's more hand-coding for the control loops, but it's traditional coding. Not everyone thinks the eTPU/PowerPC architecture is as well-designed as I do - "Way too complicated!" is the feedback I get. Peter - Peter Dufault HD Associates, Inc. Software and System Engineering signature.asc Description: Message signed with OpenPGP ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
