[PATCH 00/13] Add BSP for Arm Fixed Virtual Platform

2020-12-22 Thread Sebastian Huber 
This patch set adds a BSP to support the Arm Fixed Virtual Platform.
Only the Cortex-R52 processor configuration is supported by the BSP.  It
should be easy to add support for other variants if needed.

The patch set consolidates the low-level initialization and moves the
architecture-specific (Armv7-AR and later) initialization from
BSP-specific routines to start.S.  This was tested on the following Qemu
BSPs:

* aarch64/xilinx_zynqmp_ilp32

* aarch64/xilinx_zynqmp_lp64

* arm/fvp_cortex_r52

* arm/realview_pbx_a9_qemu

* arm/xilinx_zynq_a9_qemu

Sebastian Huber (13):
  libdebugger: Fix for Armv8-R
  bsps: Fix includes
  arm: Add header file for AArch32 System Registers
  arm: Add support for Arm PMSAv8-32
  bsps/arm: Set VBAR in start.S
  bsps/arm: Invalidate branch predictors earlier
  bsps/arm: Remove optional start hook arguments
  bsps/arm: Add arm-data-cache-loop-set-way.h
  bsps/arm: Clear SCTLR[M, I, A, C] in start.S
  bsps/arm: Invalidate TLB in start.S
  bsps: Use header file for GIC architecture support
  bsps/arm: Rely on initialized vector table
  arm/fvp: New BSP

 .../dev/irq/arm-gic-arch.h}   |21 +-
 .../altera-cyclone-v/start/bspstarthooks.c| 2 -
 bsps/arm/beagle/start/bspstarthooks.c | 4 -
 bsps/arm/fvp/console/console.c|83 +
 bsps/arm/fvp/console/printk-support.c |47 +
 bsps/arm/fvp/include/bsp.h|70 +
 bsps/arm/fvp/include/bsp/irq.h|47 +
 bsps/arm/fvp/include/bsp/semihosting.h|   130 +
 bsps/arm/fvp/include/tm27.h   | 1 +
 bsps/arm/fvp/start/bspreset.c |48 +
 bsps/arm/fvp/start/bspsmp.c   |49 +
 bsps/arm/fvp/start/bspstart.c |66 +
 bsps/arm/fvp/start/bspstarthooks.c|97 +
 bsps/arm/fvp/start/pmsa-sections.c|56 +
 bsps/arm/headers.am   | 1 -
 bsps/arm/imx/start/bspstarthooks.c| 1 -
 bsps/arm/include/bsp/arm-a8core-start.h   |55 -
 bsps/arm/include/bsp/arm-a9mpcore-start.h |29 +-
 bsps/arm/include/bsp/start.h  |13 +-
 .../dev/cache/arm-data-cache-loop-set-way.h   |96 +
 .../dev/irq/arm-gic-arch.h}   |27 +-
 bsps/arm/raspberrypi/start/bspsmp_init.c  | 5 +-
 bsps/arm/raspberrypi/start/bspstarthooks.c|52 +-
 .../shared/cache/cache-v7ar-disable-data.S|71 +-
 bsps/arm/shared/start/start.S |   142 +-
 bsps/arm/xen/start/bspstarthooks.c| 2 -
 bsps/arm/xilinx-zynq/start/bspstarthooks.c|36 -
 bsps/arm/xilinx-zynqmp/start/bspstarthooks.c  |43 +-
 bsps/include/dev/irq/arm-gic-irq.h|13 -
 bsps/shared/dev/irq/arm-gicv2.c   | 1 +
 bsps/shared/dev/irq/arm-gicv3.c   | 7 +
 .../libbsp/arm/altera-cyclone-v/Makefile.am   | 1 -
 c/src/lib/libbsp/arm/imx/Makefile.am  | 1 -
 .../libbsp/arm/realview-pbx-a9/Makefile.am| 1 -
 c/src/lib/libbsp/arm/xen/Makefile.am  | 1 -
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am  | 1 -
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  | 1 -
 cpukit/libdebugger/rtems-debugger-arm.c   | 7 +
 .../score/cpu/arm/aarch32-psma-init-default.c |60 +
 cpukit/score/cpu/arm/aarch32-psma-init.c  |   194 +
 .../arm/include/rtems/score/aarch32-pmsa.h|   314 +
 .../rtems/score/aarch32-system-registers.h| 14657 
 spec/build/bsps/aarch64/a53/obj.yml   | 1 -
 spec/build/bsps/aarch64/grp.yml   | 1 +
 spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | 1 -
 .../altera-cyclone-v/bspalteracyclonev.yml| 1 -
 spec/build/bsps/arm/fvp/abi.yml   |20 +
 spec/build/bsps/arm/fvp/bspcortexr52.yml  |19 +
 spec/build/bsps/arm/fvp/grp.yml   |58 +
 spec/build/bsps/arm/fvp/linkcmds.yml  |53 +
 spec/build/bsps/arm/fvp/obj.yml   |44 +
 spec/build/bsps/arm/fvp/objsmp.yml|16 +
 spec/build/bsps/arm/fvp/optdevbegin.yml   |22 +
 spec/build/bsps/arm/fvp/optdevsize.yml|18 +
 spec/build/bsps/arm/fvp/optdrambegin.yml  |22 +
 spec/build/bsps/arm/fvp/optdramsize.yml   |23 +
 spec/build/bsps/arm/fvp/optnullsize.yml   |21 +
 spec/build/bsps/arm/grp.yml   | 2 +-
 spec/build/bsps/arm/imx/bspimx.yml| 1 -
 spec/build/bsps/arm/optgiccpuif.yml   |19 +
 spec/build/bsps/arm/optgicdist.yml|19 +
 spec/build/bsps/arm/optgicredist.yml  |19 +
 spec/build/bsps/arm/optgicspicount.yml|17 +
 spec/build/bsps/arm/optgtfreq.yml | 5 +-
 .../arm/realview-pbx-a9/bsprealviewpbxa9.yml  | 1 -
 spec/build/bsps/arm/xen/bspxen.yml| 1 -
 spec/build/bsps/arm/xilinx-zynq/obj.yml   | 1 -
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 1 -

[PATCH 01/13] libdebugger: Fix for Armv8-R

2020-12-22 Thread Sebastian Huber 
This architecture variant has no MMU.

Update #4202.
---
 cpukit/libdebugger/rtems-debugger-arm.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/cpukit/libdebugger/rtems-debugger-arm.c 
b/cpukit/libdebugger/rtems-debugger-arm.c
index 106cbe8b8a..ba01a860c8 100644
--- a/cpukit/libdebugger/rtems-debugger-arm.c
+++ b/cpukit/libdebugger/rtems-debugger-arm.c
@@ -1678,6 +1678,7 @@ target_exception_data_abort(void)
 }
 
 #if ARM_CP15
+#if __ARM_ARCH_PROFILE == 'A'
 /**
  * The init value for the text section.
  */
@@ -1701,6 +1702,12 @@ rtems_debugger_target_set_mmu(void)
text_end,
ARMV7_MMU_DATA_READ_WRITE_CACHED);
 }
+#else
+static void
+rtems_debugger_target_set_mmu(void)
+{
+}
+#endif
 
 static void
 rtems_debugger_target_set_vectors(void)
-- 
2.26.2

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[PATCH 02/13] bsps: Fix includes

2020-12-22 Thread Sebastian Huber 
Update #4202.
---
 bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c | 1 -
 bsps/shared/dev/irq/arm-gicv3.c | 6 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c 
b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
index 5caf717bf1..4c26ec3c2b 100644
--- a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
+++ b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
@@ -36,7 +36,6 @@
 
 #include 
 #include 
-#include 
 
 void arm_interrupt_handler_dispatch(rtems_vector_number vector)
 {
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 65b049cd5a..77128adb5b 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -31,6 +31,12 @@
 #include 
 #include 
 
+#ifdef ARM_MULTILIB_ARCH_V4
+#include 
+#else
+#include 
+#endif
+
 #define PRIORITY_DEFAULT 127
 
 #define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
-- 
2.26.2

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[PATCH 06/13] bsps/arm: Invalidate branch predictors earlier

2020-12-22 Thread Sebastian Huber 
Make sure the branch predictors are invalidated before the first branch
is executed.

Update #4202.
---
 bsps/arm/include/bsp/arm-a9mpcore-start.h|  2 --
 bsps/arm/raspberrypi/start/bspstarthooks.c   |  1 -
 bsps/arm/shared/start/start.S| 11 +++
 bsps/arm/xilinx-zynq/start/bspstarthooks.c   |  1 -
 bsps/arm/xilinx-zynqmp/start/bspstarthooks.c |  1 -
 5 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/bsps/arm/include/bsp/arm-a9mpcore-start.h 
b/bsps/arm/include/bsp/arm-a9mpcore-start.h
index 2a64ffc1d6..98d1a2e295 100644
--- a/bsps/arm/include/bsp/arm-a9mpcore-start.h
+++ b/bsps/arm/include/bsp/arm-a9mpcore-start.h
@@ -140,8 +140,6 @@ BSP_START_TEXT_SECTION static inline void 
arm_a9mpcore_start_hook_0(void)
 (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
   uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
 
-  arm_cp15_branch_predictor_invalidate_all();
-
   if (cpu_id == 0) {
 arm_a9mpcore_start_scu_enable(scu);
   }
diff --git a/bsps/arm/raspberrypi/start/bspstarthooks.c 
b/bsps/arm/raspberrypi/start/bspstarthooks.c
index c46c4f5cbf..b050cb695e 100644
--- a/bsps/arm/raspberrypi/start/bspstarthooks.c
+++ b/bsps/arm/raspberrypi/start/bspstarthooks.c
@@ -110,7 +110,6 @@ void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
 rtems_cache_invalidate_entire_data();
   }
   rtems_cache_invalidate_entire_instruction();
-  arm_cp15_branch_predictor_invalidate_all();
   arm_cp15_tlb_invalidate();
   arm_cp15_flush_prefetch_buffer();
 
diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index 9ebc2818e5..f4880dfcf0 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -181,6 +181,17 @@ _start:
mov r13, #0
 #endif
 
+#if __ARM_ARCH >= 7
+   /*
+* Write to BPIALL (Branch Predictor Invalidate All) to invalidate all
+* branch predictors.  There is no need to use BPIALLIS (Branch
+* Predictor Invalidate All, Inner Shareable) since this code is
+* executed on all processors used by RTEMS.
+*/
+   mov r0, #0
+   mcr p15, 0, r0, c7, c5, 6
+#endif
+
 #ifdef RTEMS_SMP
/* Read MPIDR and get current processor index */
mrc p15, 0, r7, c0, c0, 5
diff --git a/bsps/arm/xilinx-zynq/start/bspstarthooks.c 
b/bsps/arm/xilinx-zynq/start/bspstarthooks.c
index a0f0fbacf6..0fc2a2590d 100644
--- a/bsps/arm/xilinx-zynq/start/bspstarthooks.c
+++ b/bsps/arm/xilinx-zynq/start/bspstarthooks.c
@@ -66,7 +66,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
* are required there.
*/
   arm_cp15_data_cache_invalidate_all_levels();
-  arm_cp15_branch_predictor_invalidate_all();
   arm_cp15_tlb_invalidate();
   arm_cp15_flush_prefetch_buffer();
   arm_a9mpcore_start_hook_0();
diff --git a/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c 
b/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
index 9ab8d965f3..bc3f0fbe5e 100644
--- a/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
+++ b/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
@@ -72,7 +72,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
* are required there.
*/
   arm_cp15_data_cache_invalidate_all_levels();
-  arm_cp15_branch_predictor_invalidate_all();
   arm_cp15_tlb_invalidate();
   arm_cp15_flush_prefetch_buffer();
 }
-- 
2.26.2

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[PATCH 07/13] bsps/arm: Remove optional start hook arguments

2020-12-22 Thread Sebastian Huber 
The start hook arguments are not used by a BSP.  Removing them avoids
the need for a stack during the very early system initialization.

Update #4202.
---
 bsps/arm/include/bsp/start.h  | 13 ++--
 bsps/arm/shared/start/start.S | 63 +++
 2 files changed, 28 insertions(+), 48 deletions(-)

diff --git a/bsps/arm/include/bsp/start.h b/bsps/arm/include/bsp/start.h
index 0a5ce2ab62..b5d1de942c 100644
--- a/bsps/arm/include/bsp/start.h
+++ b/bsps/arm/include/bsp/start.h
@@ -45,15 +45,6 @@ extern "C" {
 
 #define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data")))
 
-/*
-* Many ARM boot loaders pass arguments to loaded OS kernel
-*/
-#ifdef BSP_START_HOOKS_WITH_LOADER_ARGS
-#define BSP_START_HOOKS_LOADER_ARGS int saved_psr, int saved_machid, int 
saved_dtb_adr
-#else
-#define BSP_START_HOOKS_LOADER_ARGS void
-#endif
-
 /**
 * @brief System start entry.
 */
@@ -66,7 +57,7 @@ void _start(void);
 * stack pointers are initialized but before the copying of the exception
 * vectors.
 */
-void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS);
+void bsp_start_hook_0(void);
 
 /**
 * @brief Start entry hook 1.
@@ -74,7 +65,7 @@ void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS);
 * This hook will be called from the start entry code after copying of the
 * exception vectors but before the call to boot_card().
 */
-void bsp_start_hook_1(BSP_START_HOOKS_LOADER_ARGS);
+void bsp_start_hook_1(void);
 
 /**
  * @brief Similar to standard memcpy().
diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index f4880dfcf0..92b11ee45e 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -159,12 +159,11 @@ _start:
 
/*
 * We do not save the context since we do not return to the boot
-* loader but preserve r1 and r2 to allow access to bootloader 
parameters
+* loader.  Boot loaders may pass the device tree in r2.  Do not touch
+* r2 until bsp_fdt_copy() is called.
 */
-#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
-   mov r5, r1  /* machine type number or ~0 for DT boot */
-   mov r6, r2  /* physical address of ATAGs or DTB */
-#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
+
+#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
mov r0, #0
mov r1, #0
mov r2, #0
@@ -215,8 +214,8 @@ _start:
add r3, r7, #1
mul r1, r1, r3
 #endif
-   ldr r2, =_ISR_Stack_area_begin
-   add r3, r1, r2
+   ldr r0, =_ISR_Stack_area_begin
+   add r3, r1, r0
 
/* Save original CPSR value */
mrs r4, cpsr
@@ -235,35 +234,35 @@ _start:
mov sp, r3
sub r3, r3, r1
 
-   ldr r2, =bsp_start_hyp_vector_table_begin
-   mcr p15, 4, r2, c12, c0, 0
+   ldr r0, =bsp_start_hyp_vector_table_begin
+   mcr p15, 4, r0, c12, c0, 0
 
-   mov r2, #0
-   mcr p15, 4, r2, c1, c1, 0
-   mcr p15, 4, r2, c1, c1, 2
-   mcr p15, 4, r2, c1, c1, 3
+   mov r0, #0
+   mcr p15, 4, r0, c1, c1, 0
+   mcr p15, 4, r0, c1, c1, 2
+   mcr p15, 4, r0, c1, c1, 3
 /*
  * HSCTLR.TE
  * optional start of hypervisor handlers in Thumb mode
  * orr r0, #(1 << 30)
  */
-   mcr p15, 4, r2, c1, c0, 0   /* HSCTLR */
-   mrc p15, 4, r2, c1, c1, 1   /* HDCR */
-   and r2, #0x1f   /* Preserve HPMN */
-   mcr p15, 4, r2, c1, c1, 1   /* HDCR */
+   mcr p15, 4, r0, c1, c0, 0   /* HSCTLR */
+   mrc p15, 4, r0, c1, c1, 1   /* HDCR */
+   and r0, #0x1f   /* Preserve HPMN */
+   mcr p15, 4, r0, c1, c1, 1   /* HDCR */
 
/* Prepare SVC mode for eret */
-   mrs r2, cpsr
-   bic r2, r2, #ARM_PSR_M_MASK
-   orr r2, r2, #ARM_PSR_M_SVC
-   msr spsr_cxsf, r2
-
-   adr r2, .L_hyp_to_svc_return
-   .inst 0xe12ef302/* msr ELR_hyp, r2 */
-   mov r2, sp
+   mrs r0, cpsr
+   bic r0, r0, #ARM_PSR_M_MASK
+   orr r0, r0, #ARM_PSR_M_SVC
+   msr spsr_cxsf, r0
+
+   ldr r0, =.L_hyp_to_svc_return
+   .inst 0xe12ef300/* msr ELR_hyp, r0 */
+   mov r0, sp
.inst 0xe160006e/* eret */
 .L_hyp_to_svc_return:
-   mov sp, r2
+   mov sp, r0
 
 .L_skip_hyp_svc_switch:
 #endif /* BSP_START_IN_HYP_SUPPORT */
@@ -320,7 +319,7 @@ _start:
cmp r7, #0
bne 1f
 #endif
-   mov r0, r6
+   mov r0, r2
bl  bsp_fdt_copy
 1:
 #endif
@@ -413,7 +412,6 @@ _start:
 * instruction as a very limited address range of 2KiB.  Use a bx to
 * the start hook 0 address instead corrected by the address offset.
 */
-
ldr lr, =bsp_start_hook_0_done
mov r0, pc
ldr r1, =.Lget_absolute_pc
@@ -421,11 +419,6 @@ _start:
sub

[PATCH 05/13] bsps/arm: Set VBAR in start.S

2020-12-22 Thread Sebastian Huber 
Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to ealier handle exceptions in RTEMS.

Set the VBAR to the normal vector table in start.S for the main
processor.  Secondary processors set it in bsp_start_hook_0().

Update #4202.
---
 bsps/arm/beagle/start/bspstarthooks.c|  4 --
 bsps/arm/headers.am  |  1 -
 bsps/arm/imx/start/bspstarthooks.c   |  1 -
 bsps/arm/include/bsp/arm-a8core-start.h  | 55 
 bsps/arm/include/bsp/arm-a9mpcore-start.h| 27 ++
 bsps/arm/raspberrypi/start/bspsmp_init.c |  3 ++
 bsps/arm/raspberrypi/start/bspstarthooks.c   |  3 --
 bsps/arm/shared/start/start.S| 28 +-
 bsps/arm/xen/start/bspstarthooks.c   |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstarthooks.c |  2 -
 spec/build/bsps/arm/grp.yml  |  1 -
 11 files changed, 33 insertions(+), 94 deletions(-)
 delete mode 100644 bsps/arm/include/bsp/arm-a8core-start.h

diff --git a/bsps/arm/beagle/start/bspstarthooks.c 
b/bsps/arm/beagle/start/bspstarthooks.c
index 2efa3042a8..38f2903d4d 100644
--- a/bsps/arm/beagle/start/bspstarthooks.c
+++ b/bsps/arm/beagle/start/bspstarthooks.c
@@ -15,9 +15,6 @@
 #include 
 #include 
 #include 
-#include 
-
-#include 
 
 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 {
@@ -25,7 +22,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 
 BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
 {
-  arm_a8core_start_hook_1();
   bsp_start_copy_sections();
   beagle_setup_mmu_and_cache();
   bsp_start_clear_bss();
diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index a4d6dfa09e..92af7e1059 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -10,7 +10,6 @@ include_HEADERS += ../../../../../bsps/arm/include/uart.h
 
 include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a8core-start.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-clock.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-regs.h
diff --git a/bsps/arm/imx/start/bspstarthooks.c 
b/bsps/arm/imx/start/bspstarthooks.c
index d35374e360..f2ea7b4863 100644
--- a/bsps/arm/imx/start/bspstarthooks.c
+++ b/bsps/arm/imx/start/bspstarthooks.c
@@ -102,7 +102,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 
 BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
 {
-  arm_a9mpcore_start_set_vector_base();
   bsp_start_copy_sections();
   setup_mmu_and_cache();
   bsp_start_clear_bss();
diff --git a/bsps/arm/include/bsp/arm-a8core-start.h 
b/bsps/arm/include/bsp/arm-a8core-start.h
deleted file mode 100644
index d9b7274018..00
--- a/bsps/arm/include/bsp/arm-a8core-start.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- *  @file
- *
- *  @ingroup RTEMSBSPsARMShared
- *
- *  @brief A8CORE_START Support
- */
-
-/*
- * Copyright (c) 2014 Chris Johns .  All rights reserved.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_ARM_SHARED_ARM_A8CORE_START_H
-#define LIBBSP_ARM_SHARED_ARM_A8CORE_START_H
-
-#include 
-
-#include 
-#include 
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-BSP_START_TEXT_SECTION static inline void 
arm_a8core_start_set_vector_base(void)
-{
-  /*
-   * Do not use bsp_vector_table_begin == 0, since this will get optimized 
away.
-  */
-  if (bsp_vector_table_end != bsp_vector_table_size) {
-uint32_t ctrl;
-
-arm_cp15_set_vector_base_address(bsp_vector_table_begin);
-
-ctrl = arm_cp15_get_control();
-ctrl &= ~ARM_CP15_CTRL_V;
-arm_cp15_set_control(ctrl);
-  }
-}
-
-BSP_START_TEXT_SECTION static inline void arm_a8core_start_hook_1(void)
-{
-  arm_a8core_start_set_vector_base();
-}
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_SHARED_ARM_A8CORE_START_H */
diff --git a/bsps/arm/include/bsp/arm-a9mpcore-start.h 
b/bsps/arm/include/bsp/arm-a9mpcore-start.h
index 5f870acec7..2a64ffc1d6 100644
--- a/bsps/arm/include/bsp/arm-a9mpcore-start.h
+++ b/bsps/arm/include/bsp/arm-a9mpcore-start.h
@@ -37,27 +37,6 @@
 extern "C" {
 #endif /* __cplusplus */
 
-BSP_START_TEXT_SECTION static inline void
-arm_a9mpcore_start_set_vector_base(void)
-{
-  /*
-   * Do not use bsp_vector_table_begin == 0, since this will get optimized 
away.
-  */
-  if (bsp_vector_table_end != bsp_vector_table_size) {
-uint32_t ctrl;
-
-/*
- * For now we assume that every Cortex-A9 MPCore has the Security 
Extensions.
- * Later it might be necessary to evaluate the ID_PFR1 register.
- */
-arm_cp15_set_vector_base_address(bsp_vector_table_begin);
-
-ctrl = arm_cp15_get_control();
-ctrl &= ~ARM_CP15_CTRL_V;
-arm_cp15_set_control(ctrl);
-  }
-}
-
 BSP_START_TEXT_SECTION

[PATCH 08/13] bsps/arm: Add arm-data-cache-loop-set-way.h

2020-12-22 Thread Sebastian Huber 
This makes it possible to reuse this loop.

Update #4202.
---
 .../dev/cache/arm-data-cache-loop-set-way.h   | 96 +++
 .../shared/cache/cache-v7ar-disable-data.S| 71 ++
 2 files changed, 105 insertions(+), 62 deletions(-)
 create mode 100644 bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h

diff --git a/bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h 
b/bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h
new file mode 100644
index 00..f5dc792aa2
--- /dev/null
+++ b/bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h
@@ -0,0 +1,96 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2018 embedded brains GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+.macro ARM_DATA_CACHE_LOOP_SET_WAY CRM
+
+   /* Get cache levels (LoC) from CLIDR */
+   mrc p15, 1, r1, c0, c0, 1
+   mov r2, r1, lsr #24
+   andsr2, r2, #0x7
+   beq 5f
+
+   /* Start with level 0 */
+   mov r3, #0
+
+   /* Flush level specified by r3 */
+1:
+
+   /* Check cache type and skip this level if there is no data cache */
+   add r4, r3, r3, lsl #1
+   lsr r5, r1, r4
+   and r5, r5, #0x7
+   cmp r5, #2
+   blt 4f
+
+   /* Read CCSIDR */
+   lsl r4, r3, #1
+   mcr p15, 2, r4, c0, c0, 0
+   isb
+   mrc p15, 1, r5, c0, c0, 0
+
+   /* Get cache line power */
+   and r6, r5, #0x7
+   add r6, r6, #4
+
+   /* Get ways minus one */
+   mov r7, #0x3ff
+   andsr7, r7, r5, lsr #3
+
+   /* Get way shift */
+   clz r8, r7
+
+   /* Get sets minus one */
+   mov r9, #0x7fff
+   andsr9, r9, r5, lsr #13
+
+   /* Loop over ways */
+2:
+   mov r10, r9
+
+   /* Loop over sets */
+3:
+   orr r11, r4, r7, lsl r8
+   orr r11, r11, r10, lsl r6
+
+   /* Cache operation by set and way */
+   mcr p15, 0, r11, c7, \CRM, 2
+
+   subsr10, r10, #1
+   bge 3b
+   subsr7, r7, #1
+   bge 2b
+
+   /* Next level */
+4:
+   add r3, r3, #1
+   cmp r2, r3
+   bgt 1b
+
+   /* Done */
+5:
+
+.endm
diff --git a/bsps/arm/shared/cache/cache-v7ar-disable-data.S 
b/bsps/arm/shared/cache/cache-v7ar-disable-data.S
index 543a3fdaf4..a5b4b7a3d1 100644
--- a/bsps/arm/shared/cache/cache-v7ar-disable-data.S
+++ b/bsps/arm/shared/cache/cache-v7ar-disable-data.S
@@ -27,7 +27,9 @@
 
 #include 
 
-#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 65 || __ARM_ARCH_PROFILE == 82)
+#include 
+
+#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 'A' || __ARM_ARCH_PROFILE == 'R')
.globl  rtems_cache_disable_data
 
.syntax unified
@@ -53,68 +55,13 @@ FUNCTION_ENTRY(rtems_cache_disable_data)
mcr p15, 0, r1, c1, c0, 0
isb
 
-   /* Get cache levels (LoC) from CLIDR */
-   mrc p15, 1, r1, c0, c0, 1
-   mov r2, r1, lsr #24
-   andsr2, r2, #0x7
-   beq .Ldone
-
-   /* Start with level 0 */
-   mov r3, #0
-
-.Lflush_level:
-   /* Flush level specified by r3 */
-
-   /* Check cache type */
-   add r4, r3, r3, lsl #1
-   lsr r5, r1, r4
-   and r5, r5, #0x7
-   cmp r5, #2
-   blt .Lno_data_cache
-
-   /* Read CCSIDR */
-   lsl r4, r3, #1
-   mcr p15, 2, r4, c0, c0, 0
-   isb
-   mrc p15, 1, r5, c0, c0, 0
-
-   /* Get cache line power */
-   and r6, r5, #0x7
-   add r6, r6, #4
-
-   /* Get ways minus one */
-   mov r7, #0x3ff
-   andsr7, r7, r5, lsr #3
-
-   /* Get way shift *

[PATCH 12/13] bsps/arm: Rely on initialized vector table

2020-12-22 Thread Sebastian Huber 
The arm_cp15_set_exception_handler() is a complicated function which
should be avoided if possible.

Update #4202.
---
 bsps/arm/include/dev/irq/arm-gic-arch.h | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/bsps/arm/include/dev/irq/arm-gic-arch.h 
b/bsps/arm/include/dev/irq/arm-gic-arch.h
index fe981da4f7..c9931be61a 100644
--- a/bsps/arm/include/dev/irq/arm-gic-arch.h
+++ b/bsps/arm/include/dev/irq/arm-gic-arch.h
@@ -37,7 +37,6 @@
 #ifndef _RTEMS_DEV_IRQ_ARM_GIC_ARM_H
 #define _RTEMS_DEV_IRQ_ARM_GIC_ARM_H
 
-#include 
 #include 
 #include 
 
@@ -55,10 +54,10 @@ static inline void 
arm_interrupt_handler_dispatch(rtems_vector_number vector)
 
 static inline void arm_interrupt_facility_set_exception_handler(void)
 {
-  arm_cp15_set_exception_handler(
-ARM_EXCEPTION_IRQ,
-_ARMV4_Exception_interrupt
-  );
+  /*
+   * There is no need to install _ARMV4_Exception_interrupt() since this
+   * handler is already set by start.S.
+   */
 }
 
 #ifdef __cplusplus
-- 
2.26.2

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[PATCH 04/13] arm: Add support for Arm PMSAv8-32

2020-12-22 Thread Sebastian Huber 
Update #4202.
---
 .../score/cpu/arm/aarch32-psma-init-default.c |  60 
 cpukit/score/cpu/arm/aarch32-psma-init.c  | 194 +++
 .../arm/include/rtems/score/aarch32-pmsa.h| 314 ++
 spec/build/cpukit/cpuarm.yml  |   2 +
 4 files changed, 570 insertions(+)
 create mode 100644 cpukit/score/cpu/arm/aarch32-psma-init-default.c
 create mode 100644 cpukit/score/cpu/arm/aarch32-psma-init.c
 create mode 100644 cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h

diff --git a/cpukit/score/cpu/arm/aarch32-psma-init-default.c 
b/cpukit/score/cpu/arm/aarch32-psma-init-default.c
new file mode 100644
index 00..da710d77fc
--- /dev/null
+++ b/cpukit/score/cpu/arm/aarch32-psma-init-default.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARMPMSAv8
+ *
+ * @brief This source file contains the implementation of
+ *   _AArch32_PMSA_Initialize_default().
+ */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+
+#if __ARM_ARCH >= 8 && __ARM_ARCH_PROFILE == 'R'
+
+void _AArch32_PMSA_Initialize_default( void )
+{
+  _AArch32_PMSA_Initialize(
+AARCH32_PMSA_MEM_ATTR(
+  AARCH32_PMSA_MEM_ATTR_DEFAULT_CACHED,
+  AARCH32_PMSA_MEM_ATTR_DEFAULT_UNCACHED,
+  AARCH32_PMSA_MEM_ATTR_DEFAULT_DEVICE,
+  0
+),
+0,
+_AArch32_PMSA_Sections,
+_AArch32_PMSA_Section_count
+  );
+}
+
+#endif
diff --git a/cpukit/score/cpu/arm/aarch32-psma-init.c 
b/cpukit/score/cpu/arm/aarch32-psma-init.c
new file mode 100644
index 00..de75d2a733
--- /dev/null
+++ b/cpukit/score/cpu/arm/aarch32-psma-init.c
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARMPMSAv8
+ *
+ * @brief This source file contains the implementation of
+ *   _AArch32_PMSA_Initialize().
+ */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+
+#if __ARM_ARCH >= 8 && __ARM_ARCH_PROFILE == 'R'
+
+#include 
+#include 
+
+#define AARCH32_PSMA_REGION_MAX \
+  ( ( AARCH32_MPUIR_REGION_MASK >> AARCH32_MPUIR_REGION_SHIFT ) + 1 )
+
+typedef struct {
+  uint32_t base;
+  uint32_t l

[PATCH 11/13] bsps: Use header file for GIC architecture support

2020-12-22 Thread Sebastian Huber 
This avoids a function call overhead in the interrupt dispatching.

Update #4202.
---
 .../dev/irq/arm-gic-arch.h}   | 20 ---
 .../dev/irq/arm-gic-arch.h}   | 18 ++---
 bsps/include/dev/irq/arm-gic-irq.h| 13 
 bsps/shared/dev/irq/arm-gicv2.c   |  1 +
 bsps/shared/dev/irq/arm-gicv3.c   |  1 +
 .../libbsp/arm/altera-cyclone-v/Makefile.am   |  1 -
 c/src/lib/libbsp/arm/imx/Makefile.am  |  1 -
 .../libbsp/arm/realview-pbx-a9/Makefile.am|  1 -
 c/src/lib/libbsp/arm/xen/Makefile.am  |  1 -
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am  |  1 -
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  1 -
 spec/build/bsps/aarch64/a53/obj.yml   |  1 -
 spec/build/bsps/aarch64/grp.yml   |  1 +
 spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml |  1 -
 .../altera-cyclone-v/bspalteracyclonev.yml|  1 -
 spec/build/bsps/arm/grp.yml   |  1 +
 spec/build/bsps/arm/imx/bspimx.yml|  1 -
 .../arm/realview-pbx-a9/bsprealviewpbxa9.yml  |  1 -
 spec/build/bsps/arm/xen/bspxen.yml|  1 -
 spec/build/bsps/arm/xilinx-zynq/obj.yml   |  1 -
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  1 -
 21 files changed, 36 insertions(+), 33 deletions(-)
 rename bsps/aarch64/{shared/irq/irq-arm-gicvx-aarch64.c => 
include/dev/irq/arm-gic-arch.h} (84%)
 rename bsps/arm/{shared/irq/irq-arm-gicvx-aarch32.c => 
include/dev/irq/arm-gic-arch.h} (84%)

diff --git a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c 
b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
similarity index 84%
rename from bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
rename to bsps/aarch64/include/dev/irq/arm-gic-arch.h
index 4c26ec3c2b..c3332faf42 100644
--- a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
+++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
@@ -34,10 +34,18 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include 
+#ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
+#define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
+
+#include 
+
 #include 
 
-void arm_interrupt_handler_dispatch(rtems_vector_number vector)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
 {
   uint32_t interrupt_level = _CPU_ISR_Get_level();
   AArch64_interrupt_enable(1);
@@ -45,7 +53,7 @@ void arm_interrupt_handler_dispatch(rtems_vector_number 
vector)
   _CPU_ISR_Set_level(interrupt_level);
 }
 
-void arm_interrupt_facility_set_exception_handler(void)
+static inline void arm_interrupt_facility_set_exception_handler(void)
 {
   AArch64_set_exception_handler(
 AARCH64_EXCEPTION_SPx_IRQ,
@@ -56,3 +64,9 @@ void arm_interrupt_facility_set_exception_handler(void)
 _AArch64_Exception_interrupt_nest
   );
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */
diff --git a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c 
b/bsps/arm/include/dev/irq/arm-gic-arch.h
similarity index 84%
rename from bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
rename to bsps/arm/include/dev/irq/arm-gic-arch.h
index 7c0462d04d..fe981da4f7 100644
--- a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
+++ b/bsps/arm/include/dev/irq/arm-gic-arch.h
@@ -34,12 +34,18 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#ifndef _RTEMS_DEV_IRQ_ARM_GIC_ARM_H
+#define _RTEMS_DEV_IRQ_ARM_GIC_ARM_H
+
 #include 
-#include 
 #include 
 #include 
 
-void arm_interrupt_handler_dispatch(rtems_vector_number vector)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
 {
   uint32_t psr = _ARMV4_Status_irq_enable();
   bsp_interrupt_handler_dispatch(vector);
@@ -47,10 +53,16 @@ void arm_interrupt_handler_dispatch(rtems_vector_number 
vector)
   _ARMV4_Status_restore(psr);
 }
 
-void arm_interrupt_facility_set_exception_handler(void)
+static inline void arm_interrupt_facility_set_exception_handler(void)
 {
   arm_cp15_set_exception_handler(
 ARM_EXCEPTION_IRQ,
 _ARMV4_Exception_interrupt
   );
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTEMS_DEV_IRQ_ARM_GIC_ARM_H */
diff --git a/bsps/include/dev/irq/arm-gic-irq.h 
b/bsps/include/dev/irq/arm-gic-irq.h
index 5270331624..5ce9d54684 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -97,19 +97,6 @@ static inline rtems_status_code 
arm_gic_irq_generate_software_irq(
   return sc;
 }
 
-/**
- * This architecture-specific function sets the exception vector for handling
- * IRQs.
- */
-void arm_interrupt_facility_set_exception_handler(void);
-
-/**
- * This architecture-specific function dispatches a triggered IRQ.
- *
- * @param[in] vector The vector on which the IRQ occurred.
- */
-void arm_interrupt_handler_dispatch(rtems_vector_number vector);
-
 uint32_t arm_gic_irq_processor_count(void);
 
 void arm_gic_irq_initialize_secondary_cpu(void);
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index 7498

[PATCH 13/13] arm/fvp: New BSP

2020-12-22 Thread Sebastian Huber 
This BSP supports the Arm Fixed Virtual Platform.  Only the Cortex-R52
processor configuration is supported by the BSP.  It should be easy to
add support for other variants if needed.

Update #4202.
---
 bsps/arm/fvp/console/console.c   |  83 +++
 bsps/arm/fvp/console/printk-support.c|  47 
 bsps/arm/fvp/include/bsp.h   |  70 
 bsps/arm/fvp/include/bsp/irq.h   |  47 
 bsps/arm/fvp/include/bsp/semihosting.h   | 130 +++
 bsps/arm/fvp/include/tm27.h  |   1 +
 bsps/arm/fvp/start/bspreset.c|  48 +
 bsps/arm/fvp/start/bspsmp.c  |  49 +
 bsps/arm/fvp/start/bspstart.c|  66 
 bsps/arm/fvp/start/bspstarthooks.c   |  97 +
 bsps/arm/fvp/start/pmsa-sections.c   |  56 ++
 spec/build/bsps/arm/fvp/abi.yml  |  20 
 spec/build/bsps/arm/fvp/bspcortexr52.yml |  19 
 spec/build/bsps/arm/fvp/grp.yml  |  58 ++
 spec/build/bsps/arm/fvp/linkcmds.yml |  53 +
 spec/build/bsps/arm/fvp/obj.yml  |  44 
 spec/build/bsps/arm/fvp/objsmp.yml   |  16 +++
 spec/build/bsps/arm/fvp/optdevbegin.yml  |  22 
 spec/build/bsps/arm/fvp/optdevsize.yml   |  18 
 spec/build/bsps/arm/fvp/optdrambegin.yml |  22 
 spec/build/bsps/arm/fvp/optdramsize.yml  |  23 
 spec/build/bsps/arm/fvp/optnullsize.yml  |  21 
 spec/build/bsps/arm/optgiccpuif.yml  |  19 
 spec/build/bsps/arm/optgicdist.yml   |  19 
 spec/build/bsps/arm/optgicredist.yml |  19 
 spec/build/bsps/arm/optgicspicount.yml   |  17 +++
 spec/build/bsps/arm/optgtfreq.yml|   5 +-
 spec/build/cpukit/optsmp.yml |   1 +
 28 files changed, 1089 insertions(+), 1 deletion(-)
 create mode 100644 bsps/arm/fvp/console/console.c
 create mode 100644 bsps/arm/fvp/console/printk-support.c
 create mode 100644 bsps/arm/fvp/include/bsp.h
 create mode 100644 bsps/arm/fvp/include/bsp/irq.h
 create mode 100644 bsps/arm/fvp/include/bsp/semihosting.h
 create mode 100644 bsps/arm/fvp/include/tm27.h
 create mode 100644 bsps/arm/fvp/start/bspreset.c
 create mode 100644 bsps/arm/fvp/start/bspsmp.c
 create mode 100644 bsps/arm/fvp/start/bspstart.c
 create mode 100644 bsps/arm/fvp/start/bspstarthooks.c
 create mode 100644 bsps/arm/fvp/start/pmsa-sections.c
 create mode 100644 spec/build/bsps/arm/fvp/abi.yml
 create mode 100644 spec/build/bsps/arm/fvp/bspcortexr52.yml
 create mode 100644 spec/build/bsps/arm/fvp/grp.yml
 create mode 100644 spec/build/bsps/arm/fvp/linkcmds.yml
 create mode 100644 spec/build/bsps/arm/fvp/obj.yml
 create mode 100644 spec/build/bsps/arm/fvp/objsmp.yml
 create mode 100644 spec/build/bsps/arm/fvp/optdevbegin.yml
 create mode 100644 spec/build/bsps/arm/fvp/optdevsize.yml
 create mode 100644 spec/build/bsps/arm/fvp/optdrambegin.yml
 create mode 100644 spec/build/bsps/arm/fvp/optdramsize.yml
 create mode 100644 spec/build/bsps/arm/fvp/optnullsize.yml
 create mode 100644 spec/build/bsps/arm/optgiccpuif.yml
 create mode 100644 spec/build/bsps/arm/optgicdist.yml
 create mode 100644 spec/build/bsps/arm/optgicredist.yml
 create mode 100644 spec/build/bsps/arm/optgicspicount.yml

diff --git a/bsps/arm/fvp/console/console.c b/bsps/arm/fvp/console/console.c
new file mode 100644
index 00..b8714c60c4
--- /dev/null
+++ b/bsps/arm/fvp/console/console.c
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+
+#include 
+#include

[PATCH 10/13] bsps/arm: Invalidate TLB in start.S

2020-12-22 Thread Sebastian Huber 
Update #4202.
---
 bsps/arm/raspberrypi/start/bspsmp_init.c | 2 --
 bsps/arm/raspberrypi/start/bspstarthooks.c   | 3 ---
 bsps/arm/shared/start/start.S| 9 +
 bsps/arm/xilinx-zynq/start/bspstarthooks.c   | 4 
 bsps/arm/xilinx-zynqmp/start/bspstarthooks.c | 7 +--
 5 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/bsps/arm/raspberrypi/start/bspsmp_init.c 
b/bsps/arm/raspberrypi/start/bspsmp_init.c
index a4dd470287..eed5b44fa9 100644
--- a/bsps/arm/raspberrypi/start/bspsmp_init.c
+++ b/bsps/arm/raspberrypi/start/bspsmp_init.c
@@ -74,8 +74,6 @@ void rpi_start_rtems_on_secondary_processor(void)
 (uint32_t *) bsp_translation_table_base
   );
 
-  arm_cp15_tlb_invalidate();
-
   ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
   ctrl &= ~ARM_CP15_CTRL_V;
   arm_cp15_set_control(ctrl);
diff --git a/bsps/arm/raspberrypi/start/bspstarthooks.c 
b/bsps/arm/raspberrypi/start/bspstarthooks.c
index 60ff098be7..c6f76f24b8 100644
--- a/bsps/arm/raspberrypi/start/bspstarthooks.c
+++ b/bsps/arm/raspberrypi/start/bspstarthooks.c
@@ -67,9 +67,6 @@ raspberrypi_mmu_config_table[] = {
 
 void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
 {
-  arm_cp15_tlb_invalidate();
-  _ARM_Instruction_synchronization_barrier();
-
   /* Clear Translation Table Base Control Register */
   arm_cp15_set_translation_table_base_control_register(0);
 
diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index 0a3d4288cd..3ba8844549 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -432,6 +432,15 @@ _start:
 */
mov r0, #0
mcr p15, 0, r0, c7, c5, 0
+
+#if __ARM_ARCH >= 7 && __ARM_ARCH_PROFILE == 'A'
+   /*
+* Invalidate the TLB using ITLBIALL (Instruction TLB Invalidate All).
+*/
+   mov r0, #0
+   mcr p15, 0, r0, c8, c7, 0
+   isb
+#endif
 #endif
 
/*
diff --git a/bsps/arm/xilinx-zynq/start/bspstarthooks.c 
b/bsps/arm/xilinx-zynq/start/bspstarthooks.c
index 25cf96abdb..c67ed4f93e 100644
--- a/bsps/arm/xilinx-zynq/start/bspstarthooks.c
+++ b/bsps/arm/xilinx-zynq/start/bspstarthooks.c
@@ -31,12 +31,8 @@
 #include 
 #include 
 
-#include 
-
 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 {
-  arm_cp15_tlb_invalidate();
-  _ARM_Instruction_synchronization_barrier()
   arm_a9mpcore_start_hook_0();
 }
 
diff --git a/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c 
b/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
index 0e844bc105..ef76563a38 100644
--- a/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
+++ b/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
@@ -30,17 +30,12 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
-
 #include 
 #include 
 
-#include 
-
 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 {
-  arm_cp15_tlb_invalidate();
-  _ARM_Instruction_synchronization_barrier();
+  /* Nothing to do */
 }
 
 BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
-- 
2.26.2

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[PATCH 09/13] bsps/arm: Clear SCTLR[M, I, A, C] in start.S

2020-12-22 Thread Sebastian Huber 
Initialize the data and unified cache levels.  Invalidate the
instruction cache levels.

Update #4202.
---
 .../altera-cyclone-v/start/bspstarthooks.c|  2 -
 bsps/arm/raspberrypi/start/bspstarthooks.c| 47 +--
 bsps/arm/shared/start/start.S | 37 ++-
 bsps/arm/xilinx-zynq/start/bspstarthooks.c| 37 ++-
 bsps/arm/xilinx-zynqmp/start/bspstarthooks.c  | 39 ++-
 5 files changed, 43 insertions(+), 119 deletions(-)

diff --git a/bsps/arm/altera-cyclone-v/start/bspstarthooks.c 
b/bsps/arm/altera-cyclone-v/start/bspstarthooks.c
index d3ba05626b..d1d21350f0 100644
--- a/bsps/arm/altera-cyclone-v/start/bspstarthooks.c
+++ b/bsps/arm/altera-cyclone-v/start/bspstarthooks.c
@@ -35,8 +35,6 @@
 
 BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
 {
-  arm_cp15_instruction_cache_invalidate();
-  arm_cp15_data_cache_invalidate_all_levels();
   arm_a9mpcore_start_hook_0();
 }
 
diff --git a/bsps/arm/raspberrypi/start/bspstarthooks.c 
b/bsps/arm/raspberrypi/start/bspstarthooks.c
index b050cb695e..60ff098be7 100644
--- a/bsps/arm/raspberrypi/start/bspstarthooks.c
+++ b/bsps/arm/raspberrypi/start/bspstarthooks.c
@@ -67,57 +67,14 @@ raspberrypi_mmu_config_table[] = {
 
 void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
 {
-  uint32_t sctlr_val;
-#ifdef RTEMS_SMP
-  uint32_t cpu_index_self = _SMP_Get_current_processor();
-#endif /* RTEMS_SMP */
-
-  sctlr_val = arm_cp15_get_control();
-
-  /*
-   * Current U-boot loader seems to start kernel image
-   * with I and D caches on and MMU enabled.
-   * If RTEMS application image finds that cache is on
-   * during startup then disable caches.
-   */
-  if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
-if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
-  /*
-   * If the data cache is on then ensure that it is clean
-   * before switching off to be extra carefull.
-   */
-#ifdef RTEMS_SMP
-  if (cpu_index_self != 0) {
-arm_cp15_data_cache_clean_level(0);
-arm_cp15_cache_invalidate_level(0, 0);
-  } else
-#endif /* RTEMS_SMP */
-  {
-rtems_cache_flush_entire_data();
-rtems_cache_invalidate_entire_data();
-  }
-}
-arm_cp15_flush_prefetch_buffer();
-sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | 
ARM_CP15_CTRL_A);
-arm_cp15_set_control(sctlr_val);
-  }
-#ifdef RTEMS_SMP
-  if (cpu_index_self != 0) {
-arm_cp15_cache_invalidate_level(0, 0);
-  } else
-#endif /* RTEMS_SMP */
-  {
-rtems_cache_invalidate_entire_data();
-  }
-  rtems_cache_invalidate_entire_instruction();
   arm_cp15_tlb_invalidate();
-  arm_cp15_flush_prefetch_buffer();
+  _ARM_Instruction_synchronization_barrier();
 
   /* Clear Translation Table Base Control Register */
   arm_cp15_set_translation_table_base_control_register(0);
 
 #ifdef RTEMS_SMP
-  if (cpu_index_self == 0) {
+  if (_SMP_Get_current_processor() == 0) {
 rpi_ipi_initialize();
   } else {
 rpi_start_rtems_on_secondary_processor();
diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index 92b11ee45e..0a3d4288cd 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -31,6 +31,8 @@
 #include 
 #include 
 
+#include 
+
/* Global symbols */
.globl  _start
.globl  bsp_start_hook_0_done
@@ -390,15 +392,46 @@ _start:
 #if (__ARM_ARCH >= 7 && __ARM_ARCH_PROFILE == 'A') || __ARM_ARCH >= 8
/*
 * Set VBAR to the vector table in the start section and make sure
-* SCTLR[V] is cleared.  Afterwards, exceptions are handled by RTEMS.
+* SCTLR[M, I, A, C, V] are cleared.  Afterwards, exceptions are
+* handled by RTEMS.
 */
ldr r0, =bsp_start_vector_table_begin
dsb
mcr p15, 0, r0, c12, c0, 0
mrc p15, 0, r0, c1, c0, 0
-   bic r1, r0, #0x2000
+   bic r1, r0, #0x2800
+   bic r1, r1, #0x7
mcr p15, 0, r1, c1, c0, 0
isb
+
+   /* Check previous SCTLR[C] and initialize data caches */
+   tst r0, #0x4
+   bne .Lclean_invalidate_data_caches
+
+   /*
+* Invalidate the sets and ways of all data or unified cache levels
+* using DCISW (Data Cache line Invalidate by Set/Way).
+*/
+   ARM_DATA_CACHE_LOOP_SET_WAY c6
+   b   .Ldata_caches_initialized
+
+.Lclean_invalidate_data_caches:
+
+   /*
+* Clean and invalidate the sets and ways of all data or unified cache
+* levels using DCCISW (Data Cache line Clean and Invalidate by
+* Set/Way).
+*/
+   ARM_DATA_CACHE_LOOP_SET_WAY c14
+
+.Ldata_caches_initialized:
+
+   /*
+* Invalidate the instruction cache levels using ICIALLU (Instruction
+* Cache Invalidate All to PoU).
+*/
+   mov r0, #0
+   mcr p15, 0, r0, c7, c5, 0
 #endif
 
/*
diff --git a/bsps/arm/xilinx-zynq

Re: [PATCH v3 2/2] libtests/ofw01: Added a test for RTEMS OFW

2020-12-22 Thread Christian Mauderer 

Hello Niteesh,

On 19/12/2020 16:57, Niteesh G. S. wrote:

Hello Christian,

On Sat, Dec 19, 2020 at 7:11 PM Christian Mauderer > wrote:


Hello Niteesh,

sorry, I somehow forget to check that patch set. I'll do it in the next
few days.

No problem, please take your time :).


I have a problem with the patches on a non-fdt-BSP: The test doesn't 
link. I tried it with the xilinx_zynq_a9_qemu BSP.


Basically the bsp_fdt_get() is missing on that BSP. To work arround 
that, it is possible to change the return statement in the 
__wrap_bsp_fdt_get to:



#ifdef BSP_FDT_IS_SUPPORTED
  return __real_bsp_fdt_get();
#else
 return some_bin;
#endif

Note that in the no-fdt-bsp-case, it has to return a valid FDT because 
otherwise the ofw initialization fails.


I tested that modified version on xilinx_zynq_a9_qemu and on BBB and it 
seems to work fine. If you are OK with this modification (and no one 
objects in the next two days) I'll push the patches with this modification.




If you are on vacation, enjoy your vacations :)


Thanks. It wouldn't be reasonable to travel during a pandemic and I 
don't like traveling anyway. Therefore it's a quiet and relaxing 
vacation ;-)


Best regards

Christian



Thanks,
Niteesh.


Best regards

Christian

On 17/12/2020 12:15, Niteesh G. S. wrote:
 > ping.
 >
 >
 > On Fri, Dec 4, 2020 at 1:41 PM G S Niteesh Babu
mailto:niteesh...@gmail.com>
 > >> wrote:
 >
 >     This commit adds a basic test that tests all the implemented
 >     RTEMS OFW functions.
 >     ---
 >       spec/build/testsuites/libtests/grp.yml   |   2 +
 >       spec/build/testsuites/libtests/ofw01.yml |  21 +++
 >       testsuites/libtests/ofw01/init.c         | 197
+++
 >       testsuites/libtests/ofw01/ofw01.doc      |  29 
 >       testsuites/libtests/ofw01/ofw01.scn      |   2 +
 >       testsuites/libtests/ofw01/some.c         |  72 +
 >       testsuites/libtests/ofw01/some.dts       |  76 +
 >       testsuites/libtests/ofw01/some.h         |  15 ++
 >       8 files changed, 414 insertions(+)
 >       create mode 100644 spec/build/testsuites/libtests/ofw01.yml
 >       create mode 100644 testsuites/libtests/ofw01/init.c
 >       create mode 100644 testsuites/libtests/ofw01/ofw01.doc
 >       create mode 100644 testsuites/libtests/ofw01/ofw01.scn
 >       create mode 100644 testsuites/libtests/ofw01/some.c
 >       create mode 100644 testsuites/libtests/ofw01/some.dts
 >       create mode 100644 testsuites/libtests/ofw01/some.h
 >
 >     diff --git a/spec/build/testsuites/libtests/grp.yml
 >     b/spec/build/testsuites/libtests/grp.yml
 >     index aff46c9f8f..82c2288e2f 100644
 >     --- a/spec/build/testsuites/libtests/grp.yml
 >     +++ b/spec/build/testsuites/libtests/grp.yml
 >     @@ -316,6 +316,8 @@ links:
 >         uid: write
 >       - role: build-dependency
 >         uid: writev
 >     +- role: build-dependency
 >     +  uid: ofw01
 >       type: build
 >       use-after:
 >       - rtemstest
 >     diff --git a/spec/build/testsuites/libtests/ofw01.yml
 >     b/spec/build/testsuites/libtests/ofw01.yml
 >     new file mode 100644
 >     index 00..8517c58bad
 >     --- /dev/null
 >     +++ b/spec/build/testsuites/libtests/ofw01.yml
 >     @@ -0,0 +1,21 @@
 >     +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 >     +build-type: test-program
 >     +cflags: []
 >     +copyrights:
 >     +- Copyright (C) 2020 Niteesh G S
 >     +cppflags: []
 >     +cxxflags: []
 >     +enabled-by: true
 >     +features: c cprogram
 >     +includes: []
 >     +ldflags:
 >     +- -Wl,--wrap=bsp_fdt_get
 >     +links: []
 >     +source:
 >     +- testsuites/libtests/ofw01/init.c
 >     +- testsuites/libtests/ofw01/some.c
 >     +stlib: []
 >     +target: testsuites/libtests/ofw01.exe
 >     +type: build
 >     +use-after: []
 >     +use-before: []
 >     diff --git a/testsuites/libtests/ofw01/init.c
 >     b/testsuites/libtests/ofw01/init.c
 >     new file mode 100644
 >     index 00..105c52c50e
 >     --- /dev/null
 >     +++ b/testsuites/libtests/ofw01/init.c
 >     @@ -0,0 +1,197 @@
 >     +/* SPDX-License-Identifier: BSD-2-Clause */
 >     +
 >     +/*
 >     + * Copyright (C) <2020> Niteesh G S mailto:niteesh...@gmail.com>
 >     >>
 >     + *
 >     + * Redistribution and use in source and binary forms, with
or without
 >     + * modification, are permitted provided that the following
conditions
 >     + * are met:

Re: [rtems-bsp-builder] 2020-12-21 07:39:31: Profile(s): everything

2020-12-22 Thread Sebastian Huber 

On 22/12/2020 10:53, j...@rtems.org wrote:


Failures Report
===
  No failures

Time to remove the old build system?

--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
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Re: [PATCH] user: Mention use of LLVM

2020-12-22 Thread Joel Sherrill 
On Tue, Dec 22, 2020, 12:18 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:

> ---
>  user/tracing/eventrecording.rst | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/user/tracing/eventrecording.rst
> b/user/tracing/eventrecording.rst
> index 27e929c..4867db8 100644
> --- a/user/tracing/eventrecording.rst
> +++ b/user/tracing/eventrecording.rst
> @@ -179,6 +179,10 @@ extra support for the
>  `Linux Trace Toolkit Next Generation (LTTng) `_.
> This
>  format can be analysed using `babeltrace `_ or
>  `Eclipse Trace Compass `_.
> +The command line tool :file:`rtems-record-lttng` optionally uses
> +`LLVM `_ to translate target addresses to
> functions and
> +source file locations.  Make sure you have the LLVM development package
> +installed when you build the RTEMS Tools to enable this feature.
>

Are the llvm development tools an RSB package that should be mentioned? How
does one get them?

And then should rtems-tools always be built with llvm?

>
>  For example, to get the event records from the record server running on
> the
>  target use:
> --
> 2.26.2
>
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>
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Re: [rtems-bsp-builder] 2020-12-21 07:39:31: Profile(s): everything

2020-12-22 Thread Joel Sherrill 
On Tue, Dec 22, 2020, 8:14 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:

> On 22/12/2020 10:53, j...@rtems.org wrote:
>
> > Failures Report
> > ===
> >   No failures
> Time to remove the old build system?
>

If the bsp tester had been converted to waf.

This was not my script which builds every bsp with waf and autoconf

>
> --
> embedded brains GmbH
> Herr Sebastian HUBER
> Dornierstr. 4
> 82178 Puchheim
> Germany
> email: sebastian.hu...@embedded-brains.de
> phone: +49-89-18 94 741 - 16
> fax:   +49-89-18 94 741 - 08
>
> Registergericht: Amtsgericht München
> Registernummer: HRB 157899
> Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
> Unsere Datenschutzerklärung finden Sie hier:
> https://embedded-brains.de/datenschutzerklaerung/
>
>
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Re: [rtems-bsp-builder] 2020-12-21 07:39:31: Profile(s): everything

2020-12-22 Thread Sebastian Huber 

On 22/12/2020 17:00, Joel Sherrill wrote:



On Tue, Dec 22, 2020, 8:14 AM Sebastian Huber 
> wrote:


On 22/12/2020 10:53, j...@rtems.org  wrote:

> Failures Report
> ===
>   No failures
Time to remove the old build system?


If the bsp tester had been converted to waf.

This was not my script which builds every bsp with waf and autoconf
Maintaining the old build system needs time and this time is not 
available to convert existing tools to use the new build system.


--
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Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
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Re: [rtems-bsp-builder] 2020-12-21 07:39:31: Profile(s): everything

2020-12-22 Thread Joel Sherrill 
On Tue, Dec 22, 2020, 10:28 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:

> On 22/12/2020 17:00, Joel Sherrill wrote:
>
> >
> > On Tue, Dec 22, 2020, 8:14 AM Sebastian Huber
> >  > > wrote:
> >
> > On 22/12/2020 10:53, j...@rtems.org  wrote:
> >
> > > Failures Report
> > > ===
> > >   No failures
> > Time to remove the old build system?
> >
> >
> > If the bsp tester had been converted to waf.
> >
> > This was not my script which builds every bsp with waf and autoconf
> Maintaining the old build system needs time and this time is not
> available to convert existing tools to use the new build system.
>

I don't understand this statement. The rtems-bsp-builder was added to
rtems-tools in 2016.  It, along with rtems-tester, are the key linchpins in
the tier definitions and their enforcement.

This needs to be updated.

>
> --
> embedded brains GmbH
> Herr Sebastian HUBER
> Dornierstr. 4
> 82178 Puchheim
> Germany
> email: sebastian.hu...@embedded-brains.de
> phone: +49-89-18 94 741 - 16
> fax:   +49-89-18 94 741 - 08
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Re: [PATCH v3 2/2] libtests/ofw01: Added a test for RTEMS OFW

2020-12-22 Thread Niteesh G. S. 
Hello Christian,

On Tue, Dec 22, 2020 at 6:33 PM Christian Mauderer 
wrote:

> Hello Niteesh,
>
> On 19/12/2020 16:57, Niteesh G. S. wrote:
> > Hello Christian,
> >
> > On Sat, Dec 19, 2020 at 7:11 PM Christian Mauderer  > > wrote:
> >
> > Hello Niteesh,
> >
> > sorry, I somehow forget to check that patch set. I'll do it in the
> next
> > few days.
> >
> > No problem, please take your time :).
>
> I have a problem with the patches on a non-fdt-BSP: The test doesn't
> link. I tried it with the xilinx_zynq_a9_qemu BSP.
>


> Basically the bsp_fdt_get() is missing on that BSP. To work arround
> that, it is possible to change the return statement in the
> __wrap_bsp_fdt_get to:
>
>
>  #ifdef BSP_FDT_IS_SUPPORTED
>return __real_bsp_fdt_get();
>  #else
>   return some_bin;
>  #endif
>
I am sorry for not testing it on a non-fdt-BSP, I totally forgot about this
part though
you mentioned it in the previous patch.


> Note that in the no-fdt-bsp-case, it has to return a valid FDT because
> otherwise the ofw initialization fails.
>
> I tested that modified version on xilinx_zynq_a9_qemu and on BBB and it
> seems to work fine. If you are OK with this modification (and no one
> objects in the next two days) I'll push the patches with this modification.
>

Please push if no one objects.


> > If you are on vacation, enjoy your vacations :)
>
> Thanks. It wouldn't be reasonable to travel during a pandemic and I
> don't like traveling anyway.

+1

> Therefore it's a quiet and relaxing
> vacation ;-)
>

:)


Thanks,
Niteesh.

> Best regards
>
> Christian
>
> >
> > Thanks,
> > Niteesh.
> >
> >
> > Best regards
> >
> > Christian
> >
> > On 17/12/2020 12:15, Niteesh G. S. wrote:
> >  > ping.
> >  >
> >  >
> >  > On Fri, Dec 4, 2020 at 1:41 PM G S Niteesh Babu
> > mailto:niteesh...@gmail.com>
> >  > >>
> wrote:
> >  >
> >  > This commit adds a basic test that tests all the implemented
> >  > RTEMS OFW functions.
> >  > ---
> >  >   spec/build/testsuites/libtests/grp.yml   |   2 +
> >  >   spec/build/testsuites/libtests/ofw01.yml |  21 +++
> >  >   testsuites/libtests/ofw01/init.c | 197
> > +++
> >  >   testsuites/libtests/ofw01/ofw01.doc  |  29 
> >  >   testsuites/libtests/ofw01/ofw01.scn  |   2 +
> >  >   testsuites/libtests/ofw01/some.c |  72 +
> >  >   testsuites/libtests/ofw01/some.dts   |  76 +
> >  >   testsuites/libtests/ofw01/some.h |  15 ++
> >  >   8 files changed, 414 insertions(+)
> >  >   create mode 100644 spec/build/testsuites/libtests/ofw01.yml
> >  >   create mode 100644 testsuites/libtests/ofw01/init.c
> >  >   create mode 100644 testsuites/libtests/ofw01/ofw01.doc
> >  >   create mode 100644 testsuites/libtests/ofw01/ofw01.scn
> >  >   create mode 100644 testsuites/libtests/ofw01/some.c
> >  >   create mode 100644 testsuites/libtests/ofw01/some.dts
> >  >   create mode 100644 testsuites/libtests/ofw01/some.h
> >  >
> >  > diff --git a/spec/build/testsuites/libtests/grp.yml
> >  > b/spec/build/testsuites/libtests/grp.yml
> >  > index aff46c9f8f..82c2288e2f 100644
> >  > --- a/spec/build/testsuites/libtests/grp.yml
> >  > +++ b/spec/build/testsuites/libtests/grp.yml
> >  > @@ -316,6 +316,8 @@ links:
> >  > uid: write
> >  >   - role: build-dependency
> >  > uid: writev
> >  > +- role: build-dependency
> >  > +  uid: ofw01
> >  >   type: build
> >  >   use-after:
> >  >   - rtemstest
> >  > diff --git a/spec/build/testsuites/libtests/ofw01.yml
> >  > b/spec/build/testsuites/libtests/ofw01.yml
> >  > new file mode 100644
> >  > index 00..8517c58bad
> >  > --- /dev/null
> >  > +++ b/spec/build/testsuites/libtests/ofw01.yml
> >  > @@ -0,0 +1,21 @@
> >  > +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
> >  > +build-type: test-program
> >  > +cflags: []
> >  > +copyrights:
> >  > +- Copyright (C) 2020 Niteesh G S
> >  > +cppflags: []
> >  > +cxxflags: []
> >  > +enabled-by: true
> >  > +features: c cprogram
> >  > +includes: []
> >  > +ldflags:
> >  > +- -Wl,--wrap=bsp_fdt_get
> >  > +links: []
> >  > +source:
> >  > +- testsuites/libtests/ofw01/init.c
> >  > +- testsuites/libtests/ofw01/some.c
> >  > +stlib: []
> >  > +target: testsuites/libtests/ofw01.exe
> >  > +type: build
> >  > +use-after: []
> >  > +use-before: []
> >  > diff --git a/testsuites/libtests/ofw

Re: [PATCH] user: Mention use of LLVM

2020-12-22 Thread Sebastian Huber 

On 22/12/2020 16:59, Joel Sherrill wrote:




On Tue, Dec 22, 2020, 12:18 AM Sebastian Huber 
> wrote:


---
 user/tracing/eventrecording.rst | 4 
 1 file changed, 4 insertions(+)

diff --git a/user/tracing/eventrecording.rst
b/user/tracing/eventrecording.rst
index 27e929c..4867db8 100644
--- a/user/tracing/eventrecording.rst
+++ b/user/tracing/eventrecording.rst
@@ -179,6 +179,10 @@ extra support for the
 `Linux Trace Toolkit Next Generation (LTTng) >`_. This
 format can be analysed using `babeltrace >`_ or
 `Eclipse Trace Compass >`_.
+The command line tool :file:`rtems-record-lttng` optionally uses
+`LLVM >`_ to
translate target addresses to functions and
+source file locations.  Make sure you have the LLVM development
package
+installed when you build the RTEMS Tools to enable this feature.


Are the llvm development tools an RSB package that should be 
mentioned? How does one get them?
There is an RSB package for this, but it didn't work for me. I use the 
package from my Linux distribution.


And then should rtems-tools always be built with llvm?

I think this would be a bit of an overkill for an optional feature.

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Dornierstr. 4
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Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

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Re: [rtems-bsp-builder] 2020-12-21 07:39:31: Profile(s): everything

2020-12-22 Thread Sebastian Huber 

On 22/12/2020 18:54, Joel Sherrill wrote:




On Tue, Dec 22, 2020, 10:28 AM Sebastian Huber 
> wrote:


On 22/12/2020 17:00, Joel Sherrill wrote:

>
> On Tue, Dec 22, 2020, 8:14 AM Sebastian Huber
> mailto:sebastian.hu...@embedded-brains.de>
> >> wrote:
>
>     On 22/12/2020 10:53, j...@rtems.org 
> wrote:
>
>     > Failures Report
>     > ===
>     >   No failures
>     Time to remove the old build system?
>
>
> If the bsp tester had been converted to waf.
>
> This was not my script which builds every bsp with waf and autoconf
Maintaining the old build system needs time and this time is not
available to convert existing tools to use the new build system.


I don't understand this statement. The rtems-bsp-builder was added to 
rtems-tools in 2016.  It, along with rtems-tester, are the key 
linchpins in the tier definitions and their enforcement.

I have too many loose ends to deal with at the moment.

--
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Herr Sebastian HUBER
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Germany
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phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

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Re: [PATCH v1] zynq: Add support for SDHCI devices

2020-12-22 Thread Sebastian Huber 

On 21/12/2020 22:27, Kinsey Moore wrote:


---
  libbsd.py |   1 +
  rtemsbsd/include/bsp/nexus-devices.h  |   3 +
  .../include/machine/rtems-bsd-nexus-bus.h |  29 ++
  rtemsbsd/sys/dev/sdhci/arasan_sdhci.c | 343 ++
  4 files changed, 376 insertions(+)
  create mode 100644 rtemsbsd/sys/dev/sdhci/arasan_sdhci.c

Looks good.

--
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email: sebastian.hu...@embedded-brains.de
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Re: microzed board boot from a sd card

2020-12-22 Thread Chris Johns 
Hi Xiaomin,

Welcome to RTEMS.

On 16/12/20 6:08 am, Xiaomin (Jasmine) wrote:
> Hi, there,
> 
> I followed this article:
> 
> https://devel.rtems.org/wiki/Boards/Zynq%20-%20Zedboard
> 
> 
> for development. It basically gets the boot img file from a tftp server. It
> worked very well for me.
> 
> Now I am done with the development. I'd like to boot with my image file on the
> SD card itself, not getting the img file through tftp anymore.
> 
> How should I modify the uenv.txt file to do that? 

I am sorry I do not have the exact command you need, it depends on the
formatting used on the SD card. My approach to solving these types of problems
is to boot the board and stop the boot early via the keyboard and then play with
the uboot commands until I find something that works. This typically means being
able to list the directory of the executable you want to run and then actually
running it. Once you have those command you can place them in the uenv.txt
config file.

I hope this helps.

Chris
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RE: [PATCH 00/13] Add BSP for Arm Fixed Virtual Platform

2020-12-22 Thread Kinsey Moore 
This patch set looks good though it looks like patch 02 should probably have 
been merged into patch 11.

Kinsey

-Original Message-
From: devel  On Behalf Of Sebastian Huber
Sent: Tuesday, December 22, 2020 07:01
To: devel@rtems.org
Subject: [PATCH 00/13] Add BSP for Arm Fixed Virtual Platform

This patch set adds a BSP to support the Arm Fixed Virtual Platform.
Only the Cortex-R52 processor configuration is supported by the BSP.  It
should be easy to add support for other variants if needed.

The patch set consolidates the low-level initialization and moves the
architecture-specific (Armv7-AR and later) initialization from
BSP-specific routines to start.S.  This was tested on the following Qemu
BSPs:

* aarch64/xilinx_zynqmp_ilp32

* aarch64/xilinx_zynqmp_lp64

* arm/fvp_cortex_r52

* arm/realview_pbx_a9_qemu

* arm/xilinx_zynq_a9_qemu

Sebastian Huber (13):
  libdebugger: Fix for Armv8-R
  bsps: Fix includes
  arm: Add header file for AArch32 System Registers
  arm: Add support for Arm PMSAv8-32
  bsps/arm: Set VBAR in start.S
  bsps/arm: Invalidate branch predictors earlier
  bsps/arm: Remove optional start hook arguments
  bsps/arm: Add arm-data-cache-loop-set-way.h
  bsps/arm: Clear SCTLR[M, I, A, C] in start.S
  bsps/arm: Invalidate TLB in start.S
  bsps: Use header file for GIC architecture support
  bsps/arm: Rely on initialized vector table
  arm/fvp: New BSP

 .../dev/irq/arm-gic-arch.h}   |21 +-
 .../altera-cyclone-v/start/bspstarthooks.c| 2 -
 bsps/arm/beagle/start/bspstarthooks.c | 4 -
 bsps/arm/fvp/console/console.c|83 +
 bsps/arm/fvp/console/printk-support.c |47 +
 bsps/arm/fvp/include/bsp.h|70 +
 bsps/arm/fvp/include/bsp/irq.h|47 +
 bsps/arm/fvp/include/bsp/semihosting.h|   130 +
 bsps/arm/fvp/include/tm27.h   | 1 +
 bsps/arm/fvp/start/bspreset.c |48 +
 bsps/arm/fvp/start/bspsmp.c   |49 +
 bsps/arm/fvp/start/bspstart.c |66 +
 bsps/arm/fvp/start/bspstarthooks.c|97 +
 bsps/arm/fvp/start/pmsa-sections.c|56 +
 bsps/arm/headers.am   | 1 -
 bsps/arm/imx/start/bspstarthooks.c| 1 -
 bsps/arm/include/bsp/arm-a8core-start.h   |55 -
 bsps/arm/include/bsp/arm-a9mpcore-start.h |29 +-
 bsps/arm/include/bsp/start.h  |13 +-
 .../dev/cache/arm-data-cache-loop-set-way.h   |96 +
 .../dev/irq/arm-gic-arch.h}   |27 +-
 bsps/arm/raspberrypi/start/bspsmp_init.c  | 5 +-
 bsps/arm/raspberrypi/start/bspstarthooks.c|52 +-
 .../shared/cache/cache-v7ar-disable-data.S|71 +-
 bsps/arm/shared/start/start.S |   142 +-
 bsps/arm/xen/start/bspstarthooks.c| 2 -
 bsps/arm/xilinx-zynq/start/bspstarthooks.c|36 -
 bsps/arm/xilinx-zynqmp/start/bspstarthooks.c  |43 +-
 bsps/include/dev/irq/arm-gic-irq.h|13 -
 bsps/shared/dev/irq/arm-gicv2.c   | 1 +
 bsps/shared/dev/irq/arm-gicv3.c   | 7 +
 .../libbsp/arm/altera-cyclone-v/Makefile.am   | 1 -
 c/src/lib/libbsp/arm/imx/Makefile.am  | 1 -
 .../libbsp/arm/realview-pbx-a9/Makefile.am| 1 -
 c/src/lib/libbsp/arm/xen/Makefile.am  | 1 -
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am  | 1 -
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  | 1 -
 cpukit/libdebugger/rtems-debugger-arm.c   | 7 +
 .../score/cpu/arm/aarch32-psma-init-default.c |60 +
 cpukit/score/cpu/arm/aarch32-psma-init.c  |   194 +
 .../arm/include/rtems/score/aarch32-pmsa.h|   314 +
 .../rtems/score/aarch32-system-registers.h| 14657 
 spec/build/bsps/aarch64/a53/obj.yml   | 1 -
 spec/build/bsps/aarch64/grp.yml   | 1 +
 spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | 1 -
 .../altera-cyclone-v/bspalteracyclonev.yml| 1 -
 spec/build/bsps/arm/fvp/abi.yml   |20 +
 spec/build/bsps/arm/fvp/bspcortexr52.yml  |19 +
 spec/build/bsps/arm/fvp/grp.yml   |58 +
 spec/build/bsps/arm/fvp/linkcmds.yml  |53 +
 spec/build/bsps/arm/fvp/obj.yml   |44 +
 spec/build/bsps/arm/fvp/objsmp.yml|16 +
 spec/build/bsps/arm/fvp/optdevbegin.yml   |22 +
 spec/build/bsps/arm/fvp/optdevsize.yml|18 +
 spec/build/bsps/arm/fvp/optdrambegin.yml  |22 +
 spec/build/bsps/arm/fvp/optdramsize.yml   |23 +
 spec/build/bsps/arm/fvp/optnullsize.yml   |21 +
 spec/build/bsps/arm/grp.yml   | 2 +-
 spec/build/bsps/arm/imx/bspimx.yml| 1 -
 spec/build/bsps/arm/optgiccpuif.yml   |19 +
 spec/build/bsps/arm/optgicdist.yml|19 +
 spec/build/bsps/arm/optgicredist.yml  |19 +
 spec/build/bsps/arm/optgicspicount.yml

Re: microzed board boot from a sd card

2020-12-22 Thread Xiaomin (Jasmine) 
Hi, Chris,

Thanks for your reply. I will study it more and see if I can figure it out.
thanks.

Regards,
Xiaomin

On Tue, Dec 22, 2020 at 1:41 PM Chris Johns  wrote:

> Hi Xiaomin,
>
> Welcome to RTEMS.
>
> On 16/12/20 6:08 am, Xiaomin (Jasmine) wrote:
> > Hi, there,
> >
> > I followed this article:
> >
> > https://devel.rtems.org/wiki/Boards/Zynq%20-%20Zedboard
> > 
> >
> > for development. It basically gets the boot img file from a tftp server.
> It
> > worked very well for me.
> >
> > Now I am done with the development. I'd like to boot with my image file
> on the
> > SD card itself, not getting the img file through tftp anymore.
> >
> > How should I modify the uenv.txt file to do that?
>
> I am sorry I do not have the exact command you need, it depends on the
> formatting used on the SD card. My approach to solving these types of
> problems
> is to boot the board and stop the boot early via the keyboard and then
> play with
> the uboot commands until I find something that works. This typically means
> being
> able to list the directory of the executable you want to run and then
> actually
> running it. Once you have those command you can place them in the uenv.txt
> config file.
>
> I hope this helps.
>
> Chris
>
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