Re: Fwd: New Defects reported by Coverity Scan for RTEMS
On 08/12/2020 19:10, Gedare Bloom wrote:
Hi all,
I get a text report on new defects from Coverity. I don't know how I
managed to sign up for it, and I'm not sure I can get it sent to any
list automatically, but here is the current updated new defects. Just
looks like two new ones related to static assertions.
-- Forwarded message -
From: mailto:scan-ad...@coverity.com>>
Date: Mon, Dec 7, 2020 at 7:38 AM
Subject: New Defects reported by Coverity Scan for RTEMS
To: mailto:ged...@gwmail.gwu.edu>>
Hi,
Please find the latest report on new defect(s) introduced to RTEMS
found with Coverity Scan.
1 new defect(s) introduced to RTEMS found with Coverity Scan.
10 defect(s), reported by Coverity Scan earlier, were marked fixed in
the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 1470570: (PARSE_ERROR)
/cpukit/include/rtems/confdefs/inittask.h: 110 in ()
/cpukit/include/rtems/confdefs/inittask.h: 110 in ()
*** CID 1470570: (PARSE_ERROR)
/cpukit/include/rtems/confdefs/inittask.h: 110 in ()
104 */
105 #pragma GCC diagnostic push
106 #pragma GCC diagnostic ignored "-Waddress"
107 #pragma GCC diagnostic ignored "-Wpragmas"
108 #pragma GCC diagnostic ignored "-Wtautological-pointer-compare"
109
>>> CID 1470570: (PARSE_ERROR)
>>> type of cast must be integral
110 RTEMS_STATIC_ASSERT(
111 CONFIGURE_INIT_TASK_ENTRY_POINT != NULL,
112 CONFIGURE_INIT_TASK_ENTRY_POINT_MUST_NOT_BE_NULL
113 );
114
115 #pragma GCC diagnostic pop
/cpukit/include/rtems/confdefs/inittask.h: 110 in ()
104 */
105 #pragma GCC diagnostic push
106 #pragma GCC diagnostic ignored "-Waddress"
107 #pragma GCC diagnostic ignored "-Wpragmas"
108 #pragma GCC diagnostic ignored "-Wtautological-pointer-compare"
109
>>> CID 1470570: (PARSE_ERROR)
>>> expression must be an integral constant expression
110 RTEMS_STATIC_ASSERT(
111 CONFIGURE_INIT_TASK_ENTRY_POINT != NULL,
112 CONFIGURE_INIT_TASK_ENTRY_POINT_MUST_NOT_BE_NULL
113 );
114
115 #pragma GCC diagnostic pop
I checked an example code with three compilers and noticed no standard
related warnings. I can ask on a C/C++ mailing list if the code is
standard compliant. It could be Coverity bug.
#include
void f(void);
static_assert(f != NULL, "f");
constexpr bool g()
{
return f != NULL;
}
extern const bool b;
const bool b = g();
arm-rtems6-g++ -Wall -Wextra -pedantic -std=c++11 -S -o - test.cc
.cpu arm7tdmi
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 2
.eabi_attribute 30, 6
.eabi_attribute 34, 0
.eabi_attribute 18, 4
.file "test.cc"
test.cc:5:17: warning: the address of 'void f()' will never be NULL
[-Waddress]
5 | static_assert(f != NULL, "f");
| ^
test.cc: In function 'constexpr bool g()':
test.cc:9:12: warning: the address of 'void f()' will never be NULL
[-Waddress]
9 | return f != NULL;
| ^
.text
.global b
.section .rodata
.type b, %object
.size b, 1
b:
.byte 1
.ident "GCC: (GNU) 10.2.1 20201203 (RTEMS 6, RSB
ff6b2320ed34abab48751022085912217f42590d, Newlib 7fa8405)"
g++ -Wall -Wextra -pedantic -std=c++11 -S -o - test.cc
.file "test.cc"
test.cc:5:17: warning: the address of ‘void f()’ will never be NULL
[-Waddress]
static_assert(f != NULL, "f");
^
test.cc: In function ‘constexpr bool g()’:
test.cc:9:12: warning: the address of ‘void f()’ will never be NULL
[-Waddress]
return f != NULL;
^
.text
.globl b
.section .rodata
.type b, @object
.size b, 1
b:
.byte 1
.ident "GCC: (SUSE Linux) 7.5.0"
.section .note.GNU-stack,"",@progbits
clang -Wall -Wextra -pedantic -std=c++11 -S -o - test.cc
test.cc:5:15: warning: comparison of function 'f' not equal to a null
pointer is always true [-Wtautological-pointer-compare]
static_assert(f != NULL, "f");
^
test.cc:5:15: note: prefix with the address-of operator to silence this
warning
static_assert(f != NULL, "f");
^
&
test.cc:9:10: warning: comparison of function 'f' not equal to a null
pointer is always true [-Wtautological-pointer-compare]
return f != NULL;
^
test.cc:9:10: note: prefix with the address-of operator to silence this
warning
return f != NULL;
^
&
.text
.file "test.cc"
.type b,@object # @b
.section .rodata,"a",@progbits
.globl b
b:
.
Re: Fwd: New Defects reported by Coverity Scan for RTEMS
On 09/12/2020 10:11, Sebastian Huber wrote:
On 08/12/2020 19:10, Gedare Bloom wrote:
Hi all,
I get a text report on new defects from Coverity. I don't know how I
managed to sign up for it, and I'm not sure I can get it sent to any
list automatically, but here is the current updated new defects. Just
looks like two new ones related to static assertions.
-- Forwarded message -
From: mailto:scan-ad...@coverity.com>>
Date: Mon, Dec 7, 2020 at 7:38 AM
Subject: New Defects reported by Coverity Scan for RTEMS
To: mailto:ged...@gwmail.gwu.edu>>
Hi,
Please find the latest report on new defect(s) introduced to RTEMS
found with Coverity Scan.
1 new defect(s) introduced to RTEMS found with Coverity Scan.
10 defect(s), reported by Coverity Scan earlier, were marked fixed in
the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 1470570: (PARSE_ERROR)
/cpukit/include/rtems/confdefs/inittask.h: 110 in ()
/cpukit/include/rtems/confdefs/inittask.h: 110 in ()
*** CID 1470570: (PARSE_ERROR)
/cpukit/include/rtems/confdefs/inittask.h: 110 in ()
104 */
105 #pragma GCC diagnostic push
106 #pragma GCC diagnostic ignored "-Waddress"
107 #pragma GCC diagnostic ignored "-Wpragmas"
108 #pragma GCC diagnostic ignored "-Wtautological-pointer-compare"
109
>>> CID 1470570: (PARSE_ERROR)
>>> type of cast must be integral
110 RTEMS_STATIC_ASSERT(
111 CONFIGURE_INIT_TASK_ENTRY_POINT != NULL,
112 CONFIGURE_INIT_TASK_ENTRY_POINT_MUST_NOT_BE_NULL
113 );
114
115 #pragma GCC diagnostic pop
/cpukit/include/rtems/confdefs/inittask.h: 110 in ()
104 */
105 #pragma GCC diagnostic push
106 #pragma GCC diagnostic ignored "-Waddress"
107 #pragma GCC diagnostic ignored "-Wpragmas"
108 #pragma GCC diagnostic ignored "-Wtautological-pointer-compare"
109
>>> CID 1470570: (PARSE_ERROR)
>>> expression must be an integral constant expression
110 RTEMS_STATIC_ASSERT(
111 CONFIGURE_INIT_TASK_ENTRY_POINT != NULL,
112 CONFIGURE_INIT_TASK_ENTRY_POINT_MUST_NOT_BE_NULL
113 );
114
115 #pragma GCC diagnostic pop
I checked an example code with three compilers and noticed no standard
related warnings. I can ask on a C/C++ mailing list if the code is
standard compliant. It could be Coverity bug.
#include
void f(void);
static_assert(f != NULL, "f");
constexpr bool g()
{
return f != NULL;
}
extern const bool b;
const bool b = g();
arm-rtems6-g++ -Wall -Wextra -pedantic -std=c++11 -S -o - test.cc
.cpu arm7tdmi
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 2
.eabi_attribute 30, 6
.eabi_attribute 34, 0
.eabi_attribute 18, 4
.file "test.cc"
test.cc:5:17: warning: the address of 'void f()' will never be NULL
[-Waddress]
5 | static_assert(f != NULL, "f");
| ^
test.cc: In function 'constexpr bool g()':
test.cc:9:12: warning: the address of 'void f()' will never be NULL
[-Waddress]
9 | return f != NULL;
| ^
.text
.global b
.section .rodata
.type b, %object
.size b, 1
b:
.byte 1
.ident "GCC: (GNU) 10.2.1 20201203 (RTEMS 6, RSB
ff6b2320ed34abab48751022085912217f42590d, Newlib 7fa8405)"
g++ -Wall -Wextra -pedantic -std=c++11 -S -o - test.cc
.file "test.cc"
test.cc:5:17: warning: the address of ‘void f()’ will never be NULL
[-Waddress]
static_assert(f != NULL, "f");
^
test.cc: In function ‘constexpr bool g()’:
test.cc:9:12: warning: the address of ‘void f()’ will never be NULL
[-Waddress]
return f != NULL;
^
.text
.globl b
.section .rodata
.type b, @object
.size b, 1
b:
.byte 1
.ident "GCC: (SUSE Linux) 7.5.0"
.section .note.GNU-stack,"",@progbits
clang -Wall -Wextra -pedantic -std=c++11 -S -o - test.cc
test.cc:5:15: warning: comparison of function 'f' not equal to a null
pointer is always true [-Wtautological-pointer-compare]
static_assert(f != NULL, "f");
^
test.cc:5:15: note: prefix with the address-of operator to silence
this warning
static_assert(f != NULL, "f");
^
&
test.cc:9:10: warning: comparison of function 'f' not equal to a null
pointer is always true [-Wtautological-pointer-compare]
return f != NULL;
^
test.cc:9:10: note: prefix with the address-of operator to silence
this warning
return f != NULL;
^
&
.text
.file "test.cc"
.type b,@object # @b
.section .ro
RTEMS Tester: Set Timeout in *.ini?
Hello,
I have some tests which run a bit longer than the default 180s timeout
of the RTEMS Tester. Can I change the default timeout in the *.ini
files? This didn't work:
[fvp_cortex_r52x1]
bsp = fvp_cortex_r52
arch = arm
tester = %{_rtscripts}/run.cfg
bsp_run_cmd = FVP_BaseR_Cortex-R52x1
bsp_run_opts = -C bp.vis.disable_visualisation=1 -a
timeout = 600
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
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CMake support
Hello, I was wondering whether CMake support or an example is available or will be added in the future. We are using a framework which has different abstraction layers for OSes like (embedded) Linux, RTEMS and FreeRTOS, but we would like to use the same build system to build applications and right now CMake is our favourite because other tools like the Catch2 test framework are also built with CMake and there is a lot more documentation available for CMake. I set up a blinky example for a STM32 Nucleo board and had a look at the raw commands used to build the application and I have not seen anything special that requires waf explicitly. I was hoping that I could also build the same application with CMake, eg. with the following command sequence (with RTEMS_INST being the location where RTEMS was installed) mkdir build cd build cmake .. -D -DOS_FSFW=rtems -DRTEMS_INST=$RTEMS_INST cmake --build . I also had another question about a specific flag used when linking RTEMS executables. The link command for the example application is the following: arm-rtems6-gcc -mthumb -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -I=$RTEMS_INST/arm-rtems6/stm32h7/lib/include -MMD -B$RTEMS_INST/arm-rtems6/stm32h7/lib -Wl,--gc-sections init.c.1.o led.c.1.o stm32h7xx_nucleo.c.1.o -o blinky-test.elf -Wl,-Bstatic -Wl,-Bdynamic -qrtems Can anyone tell me the meaning of the -q flag? I did not find anything by running arm-rtems6-gcc --help Kind Regards Robin ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: CMake support
Hello Robin, you can use whatever build system you want to build your applications. You can use pkgconfig to get the necessary flags for a particular BSP installation. On 09/12/2020 13:50, Robin Müller wrote: I also had another question about a specific flag used when linking RTEMS executables. The link command for the example application is the following: arm-rtems6-gcc -mthumb -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -I=$RTEMS_INST/arm-rtems6/stm32h7/lib/include -MMD -B$RTEMS_INST/arm-rtems6/stm32h7/lib -Wl,--gc-sections init.c.1.o led.c.1.o stm32h7xx_nucleo.c.1.o -o blinky-test.elf -Wl,-Bstatic -Wl,-Bdynamic -qrtems Can anyone tell me the meaning of the -q flag? I did not find anything by running arm-rtems6-gcc --help This flag selects the right GCC specification for RTEMS. It is necessary, just use it. If you want to know how it works, you have to learn the GCC specification format. For a start you can use "arm-rtems6-gcc -dumpspecs". -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/2] cpukit/aarch64: Use hex consistently for offsets
Both patches are fine although I am not sure if changes like @@ -189,7 +189,7 @@ curr_el_spx_irq_get_pc:/* The current PC is now in LR */ * current SP. */ curr_el_spx_fiq: - stp x0, lr, [sp, #-16]! /* Push x0,lr on to the stack */ + stp x0, lr, [sp, #-0x10]! /* Push x0,lr on to the stack */ bl curr_el_spx_fiq_get_pc /* Get current execution address */ curr_el_spx_fiq_get_pc:/* The current PC is now in LR */ JUMP_HANDLER really improve readability. It it is always the same 16, then maybe a define could be used. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] bsps: Print CPU in default fatal error extension
--- bsps/shared/start/bspfatal-default.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/bsps/shared/start/bspfatal-default.c b/bsps/shared/start/bspfatal-default.c index f5f7e58812..0289dbda63 100644 --- a/bsps/shared/start/bspfatal-default.c +++ b/bsps/shared/start/bspfatal-default.c @@ -26,9 +26,16 @@ void bsp_fatal_extension( printk( "\n" "*** FATAL ***\n" - "fatal source: %i (%s)\n", + "fatal source: %i (%s)\n" + #ifdef RTEMS_SMP +"CPU: %" PRIu32 "\n" + #endif + , source, rtems_fatal_source_text( source ) + #ifdef RTEMS_SMP +, rtems_scheduler_get_processor() + #endif ); #endif -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/2] bsps: Fix GICv3 arm_gic_trigger_sgi()
Use the targets parameter to determine the targets of the SGI. Update #4202. --- bsps/shared/dev/irq/arm-gicv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index db10371c72..569c7610c4 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -356,7 +356,7 @@ void arm_gic_trigger_sgi( uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr)) | ICC_SGIR_INTID(vector) | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr)) - | ICC_SGIR_CPU_TARGET_LIST(1); + | ICC_SGIR_CPU_TARGET_LIST(targets); #ifndef ARM_MULTILIB_ARCH_V4 value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr)); #endif -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/2] bsps: Add SMP support to ARM GICv3
Update #4202.
---
bsps/shared/dev/irq/arm-gicv3.c | 56 +++--
1 file changed, 33 insertions(+), 23 deletions(-)
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index da19300b15..db10371c72 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -131,8 +131,17 @@
#endif /* ARM_MULTILIB_ARCH_V4 */
-#define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE)
-#define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *)
((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16
+static volatile gic_redist *gicv3_get_redist(uint32_t cpu_index)
+{
+ return (volatile gic_redist *)
+(BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x2);
+}
+
+static volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
+{
+ return (volatile gic_sgi_ppi *)
+(BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x2 + 0x1);
+}
void gicvx_interrupt_dispatch(void)
{
@@ -149,30 +158,29 @@ void gicvx_interrupt_dispatch(void)
void bsp_interrupt_vector_enable(rtems_vector_number vector)
{
- volatile gic_dist *dist = ARM_GIC_DIST;
- volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI;
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- /* TODO(kmoore) This could use some cleanup and integration
- * Vectors below 32 are currently routed through the redistributor */
if (vector >= 32) {
+volatile gic_dist *dist = ARM_GIC_DIST;
gic_id_enable(dist, vector);
} else {
+volatile gic_sgi_ppi *sgi_ppi =
+ gicv3_get_sgi_ppi(_SMP_Get_current_processor());
sgi_ppi->icspiser[0] = 1 << (vector % 32);
}
}
void bsp_interrupt_vector_disable(rtems_vector_number vector)
{
- volatile gic_dist *dist = ARM_GIC_DIST;
- volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI;
-
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
if (vector >= 32) {
+volatile gic_dist *dist = ARM_GIC_DIST;
gic_id_disable(dist, vector);
} else {
+volatile gic_sgi_ppi *sgi_ppi =
+ gicv3_get_sgi_ppi(_SMP_Get_current_processor());
sgi_ppi->icspicer[0] = 1 << (vector % 32);
}
}
@@ -187,21 +195,22 @@ static inline uint32_t get_id_count(volatile gic_dist
*dist)
return id_count;
}
-static void init_cpu_interface(void)
+static void gicv3_init_cpu_interface(void)
{
+ uint32_t cpu_index = _SMP_Get_current_processor();
uint32_t sre_value = 0x7;
WRITE_SR(ICC_SRE, sre_value);
WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff));
WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0));
- volatile gic_redist *redist = ARM_GIC_REDIST;
+ volatile gic_redist *redist = gicv3_get_redist(cpu_index);
uint32_t waker = redist->icrwaker;
uint32_t waker_mask = GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP;
waker &= ~waker_mask;
redist->icrwaker = waker;
/* Set interrupt group to 1NS for SGI/PPI interrupts routed through the
redistributor */
- volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI;
+ volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
sgi_ppi->icspigrpr[0] = 0x;
sgi_ppi->icspigrpmodr[0] = 0;
for (int id = 0; id < 32; id++) {
@@ -243,7 +252,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
gic_id_set_targets(dist, id, 0x01);
}
- init_cpu_interface();
+ gicv3_init_cpu_interface();
return RTEMS_SUCCESSFUL;
}
@@ -256,8 +265,7 @@ BSP_START_TEXT_SECTION void
arm_gic_irq_initialize_secondary_cpu(void)
/* Wait */
}
-#error modify init_cpu_interface to use correct offsets for each CPU
- init_cpu_interface();
+ gicv3_init_cpu_interface();
}
#endif
@@ -269,12 +277,13 @@ rtems_status_code arm_gic_irq_set_priority(
rtems_status_code sc = RTEMS_SUCCESSFUL;
if (bsp_interrupt_is_valid_vector(vector)) {
-if (vector < 32) {
- volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI;
- sgi_ppi->icspiprior[vector] = priority;
-} else {
+if (vector >= 32) {
volatile gic_dist *dist = ARM_GIC_DIST;
gic_id_set_priority(dist, vector, priority);
+} else {
+ volatile gic_sgi_ppi *sgi_ppi =
+gicv3_get_sgi_ppi(_SMP_Get_current_processor());
+ sgi_ppi->icspiprior[vector] = priority;
}
} else {
sc = RTEMS_INVALID_ID;
@@ -291,12 +300,13 @@ rtems_status_code arm_gic_irq_get_priority(
rtems_status_code sc = RTEMS_SUCCESSFUL;
if (bsp_interrupt_is_valid_vector(vector)) {
-if (vector < 32) {
- volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI;
- *priority = sgi_ppi->icspiprior[vector];
-} else {
+if (vector >= 32) {
volatile gic_dist *dist = ARM_GIC_DIST;
*priority = gic_id_get_priority(dist, vector);
+} else {
+ volatile gic_sgi_ppi *sgi_ppi =
+gicv3_get_sgi_ppi(_SMP_Get_current_processor());
+ *priority = sgi_ppi->icspiprior[vector];
}
} else {
sc = RTEMS_INVALID_ID;
--
2.26.2
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[PATCH] eng: Requirements counting shall start at zero
From: Frank Kühndel --- eng/req/req-for-req.rst | 8 1 file changed, 8 insertions(+) diff --git a/eng/req/req-for-req.rst b/eng/req/req-for-req.rst index 9225e95..8345e35 100644 --- a/eng/req/req-for-req.rst +++ b/eng/req/req-for-req.rst @@ -308,6 +308,14 @@ spec:/classic/task/create-err-invname ... +If requirements or the YAML files which contain them are to be numbered, +the numbering shall start with 0. For example: + +.. code-block:: none + +weak-alias-0.yml +weak-alias-1.yml + Conflict Free Requirements -- -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
RE: [PATCH 1/2] bsps: Add SMP support to ARM GICv3
-Original Message- From: devel On Behalf Of Sebastian Huber Sent: Wednesday, December 9, 2020 07:35 To: devel@rtems.org Subject: [PATCH 1/2] bsps: Add SMP support to ARM GICv3 > Update #4202. > --- > bsps/shared/dev/irq/arm-gicv3.c | 56 +++-- > 1 file changed, 33 insertions(+), 23 deletions(-) Looks good to me. Kinsey ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] eng: Requirements counting shall start at zero
Hi Frank, I plan to generate numbered test sources - should these also be numbered from 0? E.g. tr-model-events-mgr-n.c - I was going to have `n` range from 1..N -- should I adopt the same convention as you suggest for consistency? Regards, Andrew > On 9 Dec 2020, at 13:36, Frank Kuehndel > wrote: > > From: Frank Kühndel > > --- > eng/req/req-for-req.rst | 8 > 1 file changed, 8 insertions(+) > > diff --git a/eng/req/req-for-req.rst b/eng/req/req-for-req.rst > index 9225e95..8345e35 100644 > --- a/eng/req/req-for-req.rst > +++ b/eng/req/req-for-req.rst > @@ -308,6 +308,14 @@ spec:/classic/task/create-err-invname > > ... > > +If requirements or the YAML files which contain them are to be numbered, > +the numbering shall start with 0. For example: > + > +.. code-block:: none > + > +weak-alias-0.yml > +weak-alias-1.yml > + > Conflict Free Requirements > -- > > -- > 2.26.2 > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel Andrew Butterfield Tel: +353-1-896-2517 Fax: +353-1-677-2204 Lero@TCD, Head of Software Foundations & Verification Research Group School of Computer Science and Statistics, Room G.39, O'Reilly Institute, Trinity College, University of Dublin http://www.scss.tcd.ie/Andrew.Butterfield/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] eng: Requirements counting shall start at zero
Hello Andrew, On 09/12/2020 14:47, Andrew Butterfield wrote: I plan to generate numbered test sources - should these also be numbered from 0? E.g. tr-model-events-mgr-n.c - I was going to have `n` range from 1..N -- should I adopt the same convention as you suggest for consistency? if we agree on this change, then the test file numbering should also start from 0. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: RTEMS Tester: Set Timeout in *.ini?
On 09/12/2020 13:46, Sebastian Huber wrote:
Hello,
I have some tests which run a bit longer than the default 180s timeout
of the RTEMS Tester. Can I change the default timeout in the *.ini
files? This didn't work:
[fvp_cortex_r52x1]
bsp = fvp_cortex_r52
arch = arm
tester = %{_rtscripts}/run.cfg
bsp_run_cmd = FVP_BaseR_Cortex-R52x1
bsp_run_opts = -C bp.vis.disable_visualisation=1 -a
timeout = 600
Also what is the difference between these to two options:
# Defaults
timeout: none, none, '180' # seconds
max_test_period: none, none, '300' # seconds
If I set --timeout=600 on the command line I get a test too long error
after 300 seconds.
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Re: CMake support
Thank you Sebastian. I'm looking at building the example erc32 application and the blinky executable right now. There is the issue that determining the BSP path,tool binary determination, all the checking etc.. bleeds into the application CMakeLists.txt but there is probably a good way to extract that checking into an external file. It might even possible to make this generic. Maybe this would also be interesting for the QuickStart guide or the examples in general so if you are interested I could submit a patch for this (if everything works out as expected). Kind Regards Robin On Wed, 9 Dec 2020 at 13:59, Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > Hello Robin, > > you can use whatever build system you want to build your applications. > You can use pkgconfig to get the necessary flags for a particular BSP > installation. > > On 09/12/2020 13:50, Robin Müller wrote: > > I also had another question about a specific flag used when linking > > RTEMS executables. > > The link command for the example application is the following: > > > > arm-rtems6-gcc -mthumb -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard > > -I=$RTEMS_INST/arm-rtems6/stm32h7/lib/include -MMD > > -B$RTEMS_INST/arm-rtems6/stm32h7/lib -Wl,--gc-sections init.c.1.o > > led.c.1.o stm32h7xx_nucleo.c.1.o -o blinky-test.elf -Wl,-Bstatic > > -Wl,-Bdynamic -qrtems > > > > Can anyone tell me the meaning of the -q flag? I did not find anything > > by running arm-rtems6-gcc --help > > This flag selects the right GCC specification for RTEMS. It is > necessary, just use it. > > If you want to know how it works, you have to learn the GCC > specification format. For a start you can use "arm-rtems6-gcc -dumpspecs". > > -- > embedded brains GmbH > Herr Sebastian HUBER > Dornierstr. 4 > 82178 Puchheim > Germany > email: sebastian.hu...@embedded-brains.de > phone: +49-89-18 94 741 - 16 > fax: +49-89-18 94 741 - 08 > > Registergericht: Amtsgericht München > Registernummer: HRB 157899 > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler > Unsere Datenschutzerklärung finden Sie hier: > https://embedded-brains.de/datenschutzerklaerung/ > > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
RE: [PATCH 2/2] bsps: Fix GICv3 arm_gic_trigger_sgi()
-Original Message- From: devel On Behalf Of Sebastian Huber Sent: Wednesday, December 9, 2020 07:35 To: devel@rtems.org Subject: [PATCH 2/2] bsps: Fix GICv3 arm_gic_trigger_sgi() Use the targets parameter to determine the targets of the SGI. Update #4202. --- bsps/shared/dev/irq/arm-gicv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index db10371c72..569c7610c4 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -356,7 +356,7 @@ void arm_gic_trigger_sgi( uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr)) | ICC_SGIR_INTID(vector) | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr)) - | ICC_SGIR_CPU_TARGET_LIST(1); + | ICC_SGIR_CPU_TARGET_LIST(targets); Does the tm27 test still function on the Cortex-R52 or the generic A53 BSP after this change? The GICv2 implementation uses the filter to decide which CPU to send to since the target is set to 0 for that test. I don't see a defined behavior in the documentation for GICv3 of an all-zero target list since the filter isn't being taken into account here. Kinsey ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: CMake support
On Wed, Dec 9, 2020 at 8:06 AM Robin Müller wrote: > Thank you Sebastian. I'm looking at building the example erc32 application > and the blinky executable right now. There is the issue > that determining the BSP path,tool binary determination, all the checking > etc.. bleeds into the application CMakeLists.txt but there is > probably a good way to extract that checking into an external file. It > might even possible to make this generic. > > Maybe this would also be interesting for the QuickStart guide or the > examples in general so if you are interested > I could submit a patch for this (if everything works out as expected). > We haven't discussed it as openly as we probably should have but we are quite agnostic to the build system used by user applications. We all have our preferences and settled on waf for use wth RTEMS going forward. But the rtems-examples show how to do applications with the old application Makefile infrastructure and waf. If we had a hello world with cmake, that would be good. As I read this thread, this morning, it occurred to me that the Users Manual needs a chapter on build systems for end user applications. It needs to cover fetching the settings from the pkgconfig files and using waf, old Makefile infrastructure, etc. Guidance on using cmake, scons, meson, Eclipse managed builds, and Visual Studio would probably be of benefit. Or at least someone may care about each build system. Likely no one individual cares about more than one or two. :) A contribution would be welcomed as it would help others tread the same path. In the end, you just need to invoke the right compiler and linker with the right arguments. Assume they are magic strings per BSP and just make sure your build system produces equivalent invocations to say the build of hello world in rtems-examples. There isn't much beyond that. --joel > > Kind Regards > Robin > > On Wed, 9 Dec 2020 at 13:59, Sebastian Huber < > sebastian.hu...@embedded-brains.de> wrote: > >> Hello Robin, >> >> you can use whatever build system you want to build your applications. >> You can use pkgconfig to get the necessary flags for a particular BSP >> installation. >> >> On 09/12/2020 13:50, Robin Müller wrote: >> > I also had another question about a specific flag used when linking >> > RTEMS executables. >> > The link command for the example application is the following: >> > >> > arm-rtems6-gcc -mthumb -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard >> > -I=$RTEMS_INST/arm-rtems6/stm32h7/lib/include -MMD >> > -B$RTEMS_INST/arm-rtems6/stm32h7/lib -Wl,--gc-sections init.c.1.o >> > led.c.1.o stm32h7xx_nucleo.c.1.o -o blinky-test.elf -Wl,-Bstatic >> > -Wl,-Bdynamic -qrtems >> > >> > Can anyone tell me the meaning of the -q flag? I did not find anything >> > by running arm-rtems6-gcc --help >> >> This flag selects the right GCC specification for RTEMS. It is >> necessary, just use it. >> >> If you want to know how it works, you have to learn the GCC >> specification format. For a start you can use "arm-rtems6-gcc -dumpspecs". >> >> -- >> embedded brains GmbH >> Herr Sebastian HUBER >> Dornierstr. 4 >> 82178 Puchheim >> Germany >> email: sebastian.hu...@embedded-brains.de >> phone: +49-89-18 94 741 - 16 >> fax: +49-89-18 94 741 - 08 >> >> Registergericht: Amtsgericht München >> Registernummer: HRB 157899 >> Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler >> Unsere Datenschutzerklärung finden Sie hier: >> https://embedded-brains.de/datenschutzerklaerung/ >> >> ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 2/2] bsps: Fix GICv3 arm_gic_trigger_sgi()
On 09/12/2020 15:14, Kinsey Moore wrote: -Original Message- From: devel On Behalf Of Sebastian Huber Sent: Wednesday, December 9, 2020 07:35 To: devel@rtems.org Subject: [PATCH 2/2] bsps: Fix GICv3 arm_gic_trigger_sgi() Use the targets parameter to determine the targets of the SGI. Update #4202. --- bsps/shared/dev/irq/arm-gicv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index db10371c72..569c7610c4 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -356,7 +356,7 @@ void arm_gic_trigger_sgi( uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr)) | ICC_SGIR_INTID(vector) | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr)) - | ICC_SGIR_CPU_TARGET_LIST(1); + | ICC_SGIR_CPU_TARGET_LIST(targets); Does the tm27 test still function on the Cortex-R52 or the generic A53 BSP after this change? The GICv2 implementation uses the filter to decide which CPU to send to since the target is set to 0 for that test. I don't see a defined behavior in the documentation for GICv3 of an all-zero target list since the filter isn't being taken into account here. Kinsey Ok, I will test this. Maybe we have to change rtems_status_code sc = arm_gic_irq_generate_software_irq( ARM_GIC_TM27_IRQ_HIGH, ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, 0 ); assert(sc == RTEMS_SUCCESSFUL); to rtems_status_code sc = arm_gic_irq_generate_software_irq( ARM_GIC_TM27_IRQ_HIGH, ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, arm_cp15_get_multiprocessor_affinity() & 0xff ); assert(sc == RTEMS_SUCCESSFUL); -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()
Use the targets parameter to determine the targets of the SGI.
Update #4202.
---
v2: Fix tm27 test support.
bsps/include/dev/irq/arm-gic-tm27.h | 8
bsps/shared/dev/irq/arm-gicv3.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/bsps/include/dev/irq/arm-gic-tm27.h
b/bsps/include/dev/irq/arm-gic-tm27.h
index 95f3077716..8edacc39e4 100644
--- a/bsps/include/dev/irq/arm-gic-tm27.h
+++ b/bsps/include/dev/irq/arm-gic-tm27.h
@@ -79,8 +79,8 @@ static inline void Cause_tm27_intr(void)
{
rtems_status_code sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_LOW,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
-0
+ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+1
);
assert(sc == RTEMS_SUCCESSFUL);
}
@@ -94,8 +94,8 @@ static inline void Lower_tm27_intr(void)
{
rtems_status_code sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_HIGH,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
-0
+ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+1
);
assert(sc == RTEMS_SUCCESSFUL);
}
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index db10371c72..569c7610c4 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -356,7 +356,7 @@ void arm_gic_trigger_sgi(
uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
| ICC_SGIR_INTID(vector)
| ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
- | ICC_SGIR_CPU_TARGET_LIST(1);
+ | ICC_SGIR_CPU_TARGET_LIST(targets);
#ifndef ARM_MULTILIB_ARCH_V4
value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
#endif
--
2.26.2
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[PATCH 1/5] arm: Support Armv8 in
Update #4202.
---
.../score/cpu/arm/include/rtems/score/arm.h | 21 +--
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/cpukit/score/cpu/arm/include/rtems/score/arm.h
b/cpukit/score/cpu/arm/include/rtems/score/arm.h
index f753dd60ed..b1e4b07a37 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/arm.h
@@ -1,7 +1,9 @@
/**
* @file
*
- * @brief ARM Assembler Support API
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This header file provides defines derived from ARM multilib defines.
*/
/*
@@ -26,8 +28,9 @@ extern "C" {
/**
* @addtogroup RTEMSScoreCPUARM
+ *
+ * @{
*/
-/**@{**/
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#define CPU_MODEL_NAME "ARMv7M"
@@ -40,10 +43,7 @@ extern "C" {
#define ARM_MULTILIB_ARCH_V4
#endif
-#if defined(__ARM_ARCH_7A__) \
- || defined(__ARM_ARCH_7R__) \
- || defined(__ARM_ARCH_7M__) \
- || defined(__ARM_ARCH_7EM__)
+#if __ARM_ARCH >= 7
#define ARM_MULTILIB_HAS_WFI
#define ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
#define ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
@@ -51,18 +51,17 @@ extern "C" {
#ifndef ARM_DISABLE_THREAD_ID_REGISTER_USE
#if defined(__ARM_ARCH_7A__) \
-|| defined(__ARM_ARCH_7R__)
+|| defined(__ARM_ARCH_7R__) \
+|| __ARM_ARCH >= 8
#define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
#endif
#endif
-#if defined(__ARM_ARCH_7A__)
+#if defined(__ARM_ARCH_7A__) || __ARM_ARCH >= 8
#define ARM_MULTILIB_CACHE_LINE_MAX_64
#endif
-#if defined(__ARM_ARCH_7A__) \
- || defined(__ARM_ARCH_7M__) \
- || defined(__ARM_ARCH_7EM__)
+#if __ARM_ARCH >= 7
#define ARM_MULTILIB_HAS_CPACR
#endif
--
2.26.2
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[PATCH 0/5] Support for Armv8-R (AArch32)
Sebastian Huber (5):
arm: Support Armv8 in
arm/cache-cp15: Support Armv8
bsps/arm: Unify ARM Generic Timer options
bsps/arm: Support system level ARM Generic Timer
bsps/arm: Move BSP_START_IN_HYP_SUPPORT option
bsps/arm/shared/cache/cache-cp15.c| 25 +--
bsps/shared/dev/clock/arm-generic-timer.c | 13 +-
.../score/cpu/arm/include/rtems/score/arm.h | 21
.../optgentmrfreq.yml => optgtfreq.yml} | 9 ---
spec/build/bsps/arm/optgtsysbase.yml | 19 ++
spec/build/bsps/arm/optgtsyscntcr.yml | 20 +++
.../optgentmrusevirt.yml => optgtusevirt.yml} | 3 ++-
.../optenhyp.yml => optstarthyp.yml} | 3 ++-
spec/build/bsps/arm/raspberrypi/grp.yml | 2 +-
spec/build/bsps/arm/xen/bspxen.yml| 2 +-
spec/build/bsps/arm/xen/optgentmrusevirt.yml | 15 ---
.../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 8 +++---
12 files changed, 88 insertions(+), 52 deletions(-)
rename spec/build/bsps/arm/{xilinx-zynqmp/optgentmrfreq.yml => optgtfreq.yml}
(67%)
create mode 100644 spec/build/bsps/arm/optgtsysbase.yml
create mode 100644 spec/build/bsps/arm/optgtsyscntcr.yml
rename spec/build/bsps/arm/{xilinx-zynqmp/optgentmrusevirt.yml =>
optgtusevirt.yml} (71%)
rename spec/build/bsps/arm/{raspberrypi/optenhyp.yml => optstarthyp.yml} (74%)
delete mode 100644 spec/build/bsps/arm/xen/optgentmrusevirt.yml
--
2.26.2
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[PATCH 4/5] bsps/arm: Support system level ARM Generic Timer
Update #4202.
---
bsps/shared/dev/clock/arm-generic-timer.c | 13 -
spec/build/bsps/arm/optgtsysbase.yml | 19 +++
spec/build/bsps/arm/optgtsyscntcr.yml | 20
3 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644 spec/build/bsps/arm/optgtsysbase.yml
create mode 100644 spec/build/bsps/arm/optgtsyscntcr.yml
diff --git a/bsps/shared/dev/clock/arm-generic-timer.c
b/bsps/shared/dev/clock/arm-generic-timer.c
index f0f29e706f..3046c53a46 100644
--- a/bsps/shared/dev/clock/arm-generic-timer.c
+++ b/bsps/shared/dev/clock/arm-generic-timer.c
@@ -138,11 +138,22 @@ CPU_Counter_ticks _CPU_Counter_read(void)
return (uint32_t) arm_gt_clock_get_count();
}
+static void arm_gt_system_init(void)
+{
+#ifdef ARM_GENERIC_TIMER_SYSTEM_BASE
+ volatile uint32_t *cntcr;
+
+ cntcr = (volatile uint32_t *) ARM_GENERIC_TIMER_SYSTEM_BASE;
+ *cntcr = ARM_GENERIC_TIMER_SYSTEM_CNTCR;
+#endif
+}
+
static void arm_gt_clock_early_init(void)
{
uint32_t frequency;
- arm_gt_clock_set_control(0x3);
+ arm_gt_system_init();
+ arm_gt_clock_set_control(0x3);
arm_generic_timer_get_config(
&frequency,
&arm_gt_clock_instance.irq
diff --git a/spec/build/bsps/arm/optgtsysbase.yml
b/spec/build/bsps/arm/optgtsysbase.yml
new file mode 100644
index 00..9f684baedc
--- /dev/null
+++ b/spec/build/bsps/arm/optgtsysbase.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 709033984
+default-by-variant:
+- value: 2856517632
+ variants:
+ - arm/fvp_cortex_r52
+description: |
+ Defines the base address of the memory-mapped system level ARM Generic Timer.
+format: '{:#010x}'
+enabled-by: true
+links: []
+name: ARM_GENERIC_TIMER_SYSTEM_BASE
+type: build
diff --git a/spec/build/bsps/arm/optgtsyscntcr.yml
b/spec/build/bsps/arm/optgtsyscntcr.yml
new file mode 100644
index 00..6278bf0f53
--- /dev/null
+++ b/spec/build/bsps/arm/optgtsyscntcr.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 1
+default-by-variant:
+- value: 257
+ variants:
+ - arm/fvp_cortex_r52
+description: |
+ Defines the initialization value of the CNTCR register of the memory-mapped
+ system level ARM Generic Timer.
+format: '{:#010x}'
+enabled-by: true
+links: []
+name: ARM_GENERIC_TIMER_SYSTEM_CNTCR
+type: build
--
2.26.2
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[PATCH 3/5] bsps/arm: Unify ARM Generic Timer options
Update #4202.
---
.../optgentmrfreq.yml => optgtfreq.yml} | 9 +
.../optgentmrusevirt.yml => optgtusevirt.yml} | 3 ++-
spec/build/bsps/arm/xen/bspxen.yml| 2 +-
spec/build/bsps/arm/xen/optgentmrusevirt.yml | 15 ---
.../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml| 8
5 files changed, 12 insertions(+), 25 deletions(-)
rename spec/build/bsps/arm/{xilinx-zynqmp/optgentmrfreq.yml => optgtfreq.yml}
(67%)
rename spec/build/bsps/arm/{xilinx-zynqmp/optgentmrusevirt.yml =>
optgtusevirt.yml} (71%)
delete mode 100644 spec/build/bsps/arm/xen/optgentmrusevirt.yml
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optgentmrfreq.yml
b/spec/build/bsps/arm/optgtfreq.yml
similarity index 67%
rename from spec/build/bsps/arm/xilinx-zynqmp/optgentmrfreq.yml
rename to spec/build/bsps/arm/optgtfreq.yml
index a31630ebd6..adfacfaed2 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optgentmrfreq.yml
+++ b/spec/build/bsps/arm/optgtfreq.yml
@@ -1,14 +1,15 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
-- get-boolean: null
-- define-condition: null
+- get-integer: null
+- format-and-define: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: false
+default: null
default-by-variant: []
description: |
- ARM generic timer frequency in Hz
+ Defines the frequency in Hz of the ARM Generic Timer.
+format: '{}'
enabled-by: true
links: []
name: ARM_GENERIC_TIMER_FREQ
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optgentmrusevirt.yml
b/spec/build/bsps/arm/optgtusevirt.yml
similarity index 71%
rename from spec/build/bsps/arm/xilinx-zynqmp/optgentmrusevirt.yml
rename to spec/build/bsps/arm/optgtusevirt.yml
index 794f66244b..b443cc1d32 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optgentmrusevirt.yml
+++ b/spec/build/bsps/arm/optgtusevirt.yml
@@ -8,7 +8,8 @@ copyrights:
default: false
default-by-variant: []
description: |
- Use virtual ARM generic timer
+ If set to true, then the clock driver uses the Virtual Timer of the ARM
+ Generic Timer, otherwise it uses the Physical Timer (EL1).
enabled-by: true
links: []
name: ARM_GENERIC_TIMER_USE_VIRTUAL
diff --git a/spec/build/bsps/arm/xen/bspxen.yml
b/spec/build/bsps/arm/xen/bspxen.yml
index 3784315acd..1a3db8d172 100644
--- a/spec/build/bsps/arm/xen/bspxen.yml
+++ b/spec/build/bsps/arm/xen/bspxen.yml
@@ -28,7 +28,7 @@ links:
- role: build-dependency
uid: abi
- role: build-dependency
- uid: optgentmrusevirt
+ uid: ../optgtusevirt
- role: build-dependency
uid: optgentmunmask
- role: build-dependency
diff --git a/spec/build/bsps/arm/xen/optgentmrusevirt.yml
b/spec/build/bsps/arm/xen/optgentmrusevirt.yml
deleted file mode 100644
index cfcc9e86d3..00
--- a/spec/build/bsps/arm/xen/optgentmrusevirt.yml
+++ /dev/null
@@ -1,15 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-boolean: null
-- define-condition: null
-build-type: option
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
-description: |
- use virtual ARM generic timer
-enabled-by: true
-links: []
-name: ARM_GENERIC_TIMER_USE_VIRTUAL
-type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index 95cbc51436..b8cc1c043c 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -29,6 +29,10 @@ links:
uid: abi
- role: build-dependency
uid: objsmp
+- role: build-dependency
+ uid: ../optgtfreq
+- role: build-dependency
+ uid: ../optgtusevirt
- role: build-dependency
uid: optcachedata
- role: build-dependency
@@ -41,10 +45,6 @@ links:
uid: optconirq
- role: build-dependency
uid: ../../optconminor
-- role: build-dependency
- uid: optgentmrfreq
-- role: build-dependency
- uid: optgentmrusevirt
- role: build-dependency
uid: optint0len
- role: build-dependency
--
2.26.2
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[PATCH 2/5] arm/cache-cp15: Support Armv8
Update #4202.
---
bsps/arm/shared/cache/cache-cp15.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/bsps/arm/shared/cache/cache-cp15.c
b/bsps/arm/shared/cache/cache-cp15.c
index cdce02425f..9a58146277 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -22,17 +22,16 @@
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
-#if defined(__ARM_ARCH_7A__)
-/* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */
-#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
+#ifdef ARM_MULTILIB_CACHE_LINE_MAX_64
+ #define CPU_MAXIMAL_CACHE_ALIGNMENT 64
#endif
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
-#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 65 || __ARM_ARCH_PROFILE == 82)
-#define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA
+#if __ARM_ARCH >= 7
+ #define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA
#endif
static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
@@ -51,9 +50,9 @@ _CPU_cache_flush_data_range(
d_addr,
n_bytes
);
- #if !defined(__ARM_ARCH_7A__)
+#if __ARM_ARCH < 7
arm_cp15_drain_write_buffer();
- #endif
+#endif
_ARM_Data_synchronization_barrier();
}
@@ -109,22 +108,22 @@ static inline void _CPU_cache_unfreeze_instruction(void)
static inline void _CPU_cache_flush_entire_data(void)
{
_ARM_Data_synchronization_barrier();
- #if defined(__ARM_ARCH_7A__)
+#if __ARM_ARCH >= 7
arm_cp15_data_cache_clean_all_levels();
- #else
+#else
arm_cp15_data_cache_clean_and_invalidate();
arm_cp15_drain_write_buffer();
- #endif
+#endif
_ARM_Data_synchronization_barrier();
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
- #if defined(__ARM_ARCH_7A__)
+#if __ARM_ARCH >= 7
arm_cp15_data_cache_invalidate_all_levels();
- #else
+#else
arm_cp15_data_cache_invalidate();
- #endif
+#endif
}
static inline void _CPU_cache_enable_data(void)
--
2.26.2
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[PATCH 5/5] bsps/arm: Move BSP_START_IN_HYP_SUPPORT option
Clarify documentation.
Update #4202.
---
.../bsps/arm/{raspberrypi/optenhyp.yml => optstarthyp.yml} | 3 ++-
spec/build/bsps/arm/raspberrypi/grp.yml| 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
rename spec/build/bsps/arm/{raspberrypi/optenhyp.yml => optstarthyp.yml} (74%)
diff --git a/spec/build/bsps/arm/raspberrypi/optenhyp.yml
b/spec/build/bsps/arm/optstarthyp.yml
similarity index 74%
rename from spec/build/bsps/arm/raspberrypi/optenhyp.yml
rename to spec/build/bsps/arm/optstarthyp.yml
index b9b9cb89ae..d21db5ad4f 100644
--- a/spec/build/bsps/arm/raspberrypi/optenhyp.yml
+++ b/spec/build/bsps/arm/optstarthyp.yml
@@ -8,7 +8,8 @@ copyrights:
default: true
default-by-variant: []
description: |
- Support start of BSP in ARM HYP mode
+ If set to true, then the a system start in hypervisor mode (EL2) is
+ supported, otherwise it is unsupported.
enabled-by: true
links: []
name: BSP_START_IN_HYP_SUPPORT
diff --git a/spec/build/bsps/arm/raspberrypi/grp.yml
b/spec/build/bsps/arm/raspberrypi/grp.yml
index e28f387c8d..4a86c5c688 100644
--- a/spec/build/bsps/arm/raspberrypi/grp.yml
+++ b/spec/build/bsps/arm/raspberrypi/grp.yml
@@ -16,7 +16,7 @@ links:
- role: build-dependency
uid: objsmp
- role: build-dependency
- uid: optenhyp
+ uid: ../optstarthyp
- role: build-dependency
uid: opti2ciomode
- role: build-dependency
--
2.26.2
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RE: [PATCH 0/5] Support for Armv8-R (AArch32)
These changes look good to me.
Kinsey
-Original Message-
From: devel On Behalf Of Sebastian Huber
Sent: Wednesday, December 9, 2020 10:44
To: devel@rtems.org
Subject: [PATCH 0/5] Support for Armv8-R (AArch32)
Sebastian Huber (5):
arm: Support Armv8 in
arm/cache-cp15: Support Armv8
bsps/arm: Unify ARM Generic Timer options
bsps/arm: Support system level ARM Generic Timer
bsps/arm: Move BSP_START_IN_HYP_SUPPORT option
bsps/arm/shared/cache/cache-cp15.c| 25 +--
bsps/shared/dev/clock/arm-generic-timer.c | 13 +-
.../score/cpu/arm/include/rtems/score/arm.h | 21
.../optgentmrfreq.yml => optgtfreq.yml} | 9 ---
spec/build/bsps/arm/optgtsysbase.yml | 19 ++
spec/build/bsps/arm/optgtsyscntcr.yml | 20 +++
.../optgentmrusevirt.yml => optgtusevirt.yml} | 3 ++-
.../optenhyp.yml => optstarthyp.yml} | 3 ++-
spec/build/bsps/arm/raspberrypi/grp.yml | 2 +-
spec/build/bsps/arm/xen/bspxen.yml| 2 +-
spec/build/bsps/arm/xen/optgentmrusevirt.yml | 15 ---
.../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 8 +++---
12 files changed, 88 insertions(+), 52 deletions(-) rename
spec/build/bsps/arm/{xilinx-zynqmp/optgentmrfreq.yml => optgtfreq.yml} (67%)
create mode 100644 spec/build/bsps/arm/optgtsysbase.yml
create mode 100644 spec/build/bsps/arm/optgtsyscntcr.yml
rename spec/build/bsps/arm/{xilinx-zynqmp/optgentmrusevirt.yml =>
optgtusevirt.yml} (71%) rename spec/build/bsps/arm/{raspberrypi/optenhyp.yml
=> optstarthyp.yml} (74%) delete mode 100644
spec/build/bsps/arm/xen/optgentmrusevirt.yml
--
2.26.2
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RE: [PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()
-Original Message-
From: devel On Behalf Of Sebastian Huber
Sent: Wednesday, December 9, 2020 10:33
To: devel@rtems.org
Subject: [PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()
> Use the targets parameter to determine the targets of the SGI.
>
> Update #4202.
> ---
> v2: Fix tm27 test support.
>
> bsps/include/dev/irq/arm-gic-tm27.h | 8
> bsps/shared/dev/irq/arm-gicv3.c | 2 +-
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/bsps/include/dev/irq/arm-gic-tm27.h
> b/bsps/include/dev/irq/arm-gic-tm27.h
> index 95f3077716..8edacc39e4 100644
> --- a/bsps/include/dev/irq/arm-gic-tm27.h
> +++ b/bsps/include/dev/irq/arm-gic-tm27.h
> @@ -79,8 +79,8 @@ static inline void Cause_tm27_intr(void) {
>rtems_status_code sc = arm_gic_irq_generate_software_irq(
> ARM_GIC_TM27_IRQ_LOW,
> -ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
> -0
> +ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
> +1
>);
>assert(sc == RTEMS_SUCCESSFUL);
> }
> @@ -94,8 +94,8 @@ static inline void Lower_tm27_intr(void) {
>rtems_status_code sc = arm_gic_irq_generate_software_irq(
> ARM_GIC_TM27_IRQ_HIGH,
> -ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
> -0
> +ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
> +1
These changes will work on core 0, but will fail if running on any other core
which is a change in behavior for this test.
> diff --git a/bsps/shared/dev/irq/arm-gicv3.c
> b/bsps/shared/dev/irq/arm-gicv3.c index db10371c72..569c7610c4 100644
> --- a/bsps/shared/dev/irq/arm-gicv3.c
> +++ b/bsps/shared/dev/irq/arm-gicv3.c
> @@ -356,7 +356,7 @@ void arm_gic_trigger_sgi(
>uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
> | ICC_SGIR_INTID(vector)
> | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
> - | ICC_SGIR_CPU_TARGET_LIST(1);
> + | ICC_SGIR_CPU_TARGET_LIST(targets);
I think my processor filter todo just above this code will need to be addressed
along with this change for correct behavior on non-core 0 runs of tm27.
Kinsey
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Re: [rtems-docs commit] c-user: Generate Timer Manager documentation
On 9/12/20 7:20 pm, Sebastian Huber wrote: > Module:rtems-docs > Branch:master > Commit:d716c79070901195912526c6e49d43defad00bdd > Changeset: > http://git.rtems.org/rtems-docs/commit/?id=d716c79070901195912526c6e49d43defad00bdd > > Author:Sebastian Huber > Date: Wed Dec 2 08:17:12 2020 +0100 > > c-user: Generate Timer Manager documentation > > The documentation is a consolidation of the comments in Doxygen markup > and the documentation sources in Sphinx markup. The documentation was > transfered to interface specification items. The documentation source > files were generated from the items by a script. > > Update #3993. > > --- > > c-user/timer/directives.rst | 992 > ++ > c-user/timer/introduction.rst | 57 ++- > 2 files changed, 674 insertions(+), 375 deletions(-) > > diff --git a/c-user/timer/directives.rst b/c-user/timer/directives.rst > index d9b9877..d65f263 100644 > --- a/c-user/timer/directives.rst > +++ b/c-user/timer/directives.rst > @@ -1,463 +1,729 @@ > .. SPDX-License-Identifier: CC-BY-SA-4.0 > > +.. Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) > .. Copyright (C) 1988, 2008 On-Line Applications Research Corporation (OAR) > > +.. This file is part of the RTEMS quality process and was automatically > +.. generated. If you find something that needs to be fixed or > +.. worded better please post a report or patch to an RTEMS mailing list > +.. or raise a bug report: > +.. > +.. https://docs.rtems.org/branches/master/user/support/bugs.html > +.. > +.. For information on updating and regenerating please refer to: > +.. > +.. https://docs.rtems.org/branches/master/eng/req/howto.html > + We need a solution. I would prefer we resolve this before we add any more instances of these links. Suggestions? Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: CMake support
On 10/12/20 1:18 am, Joel Sherrill wrote: > As I read this thread, this morning, it occurred to me that the Users > Manual needs a chapter on build systems for end user applications. > It needs to cover fetching the settings from the pkgconfig files and using > waf, old Makefile infrastructure, etc. Guidance on using cmake, scons, > meson, Eclipse managed builds, and Visual Studio would probably be > of benefit. Or at least someone may care about each build system. Likely > no one individual cares about more than one or two. :) +1 In this section ... https://docs.rtems.org/branches/master/user/exe/executables.html#building-an-application Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [rtems-docs commit] c-user: Generate Timer Manager documentation
On 10/12/2020 03:24, Chris Johns wrote: On 9/12/20 7:20 pm, Sebastian Huber wrote: Module:rtems-docs Branch:master Commit:d716c79070901195912526c6e49d43defad00bdd Changeset: http://git.rtems.org/rtems-docs/commit/?id=d716c79070901195912526c6e49d43defad00bdd Author:Sebastian Huber Date: Wed Dec 2 08:17:12 2020 +0100 c-user: Generate Timer Manager documentation The documentation is a consolidation of the comments in Doxygen markup and the documentation sources in Sphinx markup. The documentation was transfered to interface specification items. The documentation source files were generated from the items by a script. Update #3993. --- c-user/timer/directives.rst | 992 ++ c-user/timer/introduction.rst | 57 ++- 2 files changed, 674 insertions(+), 375 deletions(-) diff --git a/c-user/timer/directives.rst b/c-user/timer/directives.rst index d9b9877..d65f263 100644 --- a/c-user/timer/directives.rst +++ b/c-user/timer/directives.rst @@ -1,463 +1,729 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 +.. Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) .. Copyright (C) 1988, 2008 On-Line Applications Research Corporation (OAR) +.. This file is part of the RTEMS quality process and was automatically +.. generated. If you find something that needs to be fixed or +.. worded better please post a report or patch to an RTEMS mailing list +.. or raise a bug report: +.. +.. https://docs.rtems.org/branches/master/user/support/bugs.html +.. +.. For information on updating and regenerating please refer to: +.. +.. https://docs.rtems.org/branches/master/eng/req/howto.html + We need a solution. I would prefer we resolve this before we add any more instances of these links. I understand that cross-document links are a problem, however, these two links are in comments and thus don't show up in the generated documents. A link to the bug reporting should always point to the latest information since there is only one bug reporting procedure in the project at a time. The link to the howto could be branch-specific. Suggestions? We could add a script which performs some post processing after creation the of the release branches. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()
On 10/12/2020 00:26, Kinsey Moore wrote:
-Original Message-
From: devel On Behalf Of Sebastian Huber
Sent: Wednesday, December 9, 2020 10:33
To:devel@rtems.org
Subject: [PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()
Use the targets parameter to determine the targets of the SGI.
Update #4202.
---
v2: Fix tm27 test support.
bsps/include/dev/irq/arm-gic-tm27.h | 8
bsps/shared/dev/irq/arm-gicv3.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/bsps/include/dev/irq/arm-gic-tm27.h
b/bsps/include/dev/irq/arm-gic-tm27.h
index 95f3077716..8edacc39e4 100644
--- a/bsps/include/dev/irq/arm-gic-tm27.h
+++ b/bsps/include/dev/irq/arm-gic-tm27.h
@@ -79,8 +79,8 @@ static inline void Cause_tm27_intr(void) {
rtems_status_code sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_LOW,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
-0
+ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+1
);
assert(sc == RTEMS_SUCCESSFUL);
}
@@ -94,8 +94,8 @@ static inline void Lower_tm27_intr(void) {
rtems_status_code sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_HIGH,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
-0
+ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+1
These changes will work on core 0, but will fail if running on any other core
which is a change in behavior for this test.
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index db10371c72..569c7610c4 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -356,7 +356,7 @@ void arm_gic_trigger_sgi(
uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
| ICC_SGIR_INTID(vector)
| ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
- | ICC_SGIR_CPU_TARGET_LIST(1);
+ | ICC_SGIR_CPU_TARGET_LIST(targets);
I think my processor filter todo just above this code will need to be addressed
along with this change for correct behavior on non-core 0 runs of tm27.
Yes, I thought about non-core 0 test runs too, however, I guess a lot
more things will pop up if someone does this the first time. We could
replace the 1 with an 1 << (arm_cp15_get_multiprocessor_affinity() & 0xff).
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
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[PATCH v3 1/2] bsps: Fix GICv3 arm_gic_trigger_sgi()
Use the targets parameter to determine the targets of the SGI. Change
targets parameter type to 32-bit to ease the parameter passing. GICv3
supports up to 16 targets.
Update #4202.
---
v2: Fix tm27 test support.
v3: Use arm_cp15_get_multiprocessor_affinity() to determine the tm27 SGI
target.
bsps/arm/shared/start/arm-a9mpcore-smp.c | 2 +-
bsps/include/dev/irq/arm-gic-irq.h | 4 ++--
bsps/include/dev/irq/arm-gic-tm27.h | 9 +
bsps/shared/dev/irq/arm-gicv2.c | 2 +-
bsps/shared/dev/irq/arm-gicv3.c | 4 ++--
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/bsps/arm/shared/start/arm-a9mpcore-smp.c
b/bsps/arm/shared/start/arm-a9mpcore-smp.c
index dd0512648c..5527cd2fa9 100644
--- a/bsps/arm/shared/start/arm-a9mpcore-smp.c
+++ b/bsps/arm/shared/start/arm-a9mpcore-smp.c
@@ -60,6 +60,6 @@ void _CPU_SMP_Send_interrupt( uint32_t target_processor_index
)
arm_gic_irq_generate_software_irq(
ARM_GIC_IRQ_SGI_0,
ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
-(uint8_t) (1U << target_processor_index)
+1U << target_processor_index
);
}
diff --git a/bsps/include/dev/irq/arm-gic-irq.h
b/bsps/include/dev/irq/arm-gic-irq.h
index d63fce32d1..ae0a68f7bb 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -88,13 +88,13 @@ typedef enum {
void arm_gic_trigger_sgi(
rtems_vector_number vector,
arm_gic_irq_software_irq_target_filter filter,
- uint8_t targets
+ uint32_t targets
);
static inline rtems_status_code arm_gic_irq_generate_software_irq(
rtems_vector_number vector,
arm_gic_irq_software_irq_target_filter filter,
- uint8_t targets
+ uint32_t targets
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
diff --git a/bsps/include/dev/irq/arm-gic-tm27.h
b/bsps/include/dev/irq/arm-gic-tm27.h
index 95f3077716..bfec3b22e0 100644
--- a/bsps/include/dev/irq/arm-gic-tm27.h
+++ b/bsps/include/dev/irq/arm-gic-tm27.h
@@ -31,6 +31,7 @@
#include
#include
+#include
#define MUST_WAIT_FOR_INTERRUPT 1
@@ -79,8 +80,8 @@ static inline void Cause_tm27_intr(void)
{
rtems_status_code sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_LOW,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
-0
+ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+1U << (arm_cp15_get_multiprocessor_affinity() & 0xff)
);
assert(sc == RTEMS_SUCCESSFUL);
}
@@ -94,8 +95,8 @@ static inline void Lower_tm27_intr(void)
{
rtems_status_code sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_HIGH,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
-0
+ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+1U << (arm_cp15_get_multiprocessor_affinity() & 0xff)
);
assert(sc == RTEMS_SUCCESSFUL);
}
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index cba8982764..9560a90d6b 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -261,7 +261,7 @@ void bsp_interrupt_get_affinity(
void arm_gic_trigger_sgi(
rtems_vector_number vector,
arm_gic_irq_software_irq_target_filter filter,
- uint8_t targets
+ uint32_t targets
)
{
volatile gic_dist *dist = ARM_GIC_DIST;
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index db10371c72..2bedaefcef 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -340,7 +340,7 @@ void bsp_interrupt_get_affinity(
void arm_gic_trigger_sgi(
rtems_vector_number vector,
arm_gic_irq_software_irq_target_filter filter,
- uint8_t targets
+ uint32_t targets
)
{
/* TODO(kmoore) Handle filter:
@@ -356,7 +356,7 @@ void arm_gic_trigger_sgi(
uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
| ICC_SGIR_INTID(vector)
| ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
- | ICC_SGIR_CPU_TARGET_LIST(1);
+ | ICC_SGIR_CPU_TARGET_LIST(targets);
#ifndef ARM_MULTILIB_ARCH_V4
value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
#endif
--
2.26.2
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[PATCH v3 2/2] bsps: Remove ARM GIC SGI target filter
Remove the target filter for software-generated interrupts since this
feature is not supported by the affinity routing in GICv3.
Update #4202.
---
bsps/arm/shared/start/arm-a9mpcore-smp.c | 1 -
bsps/include/dev/irq/arm-gic-irq.h | 15 ++-
bsps/include/dev/irq/arm-gic-tm27.h | 2 --
bsps/shared/dev/irq/arm-gicv2.c | 8 ++--
bsps/shared/dev/irq/arm-gicv3.c | 10 +-
5 files changed, 5 insertions(+), 31 deletions(-)
diff --git a/bsps/arm/shared/start/arm-a9mpcore-smp.c
b/bsps/arm/shared/start/arm-a9mpcore-smp.c
index 5527cd2fa9..9bde1815c0 100644
--- a/bsps/arm/shared/start/arm-a9mpcore-smp.c
+++ b/bsps/arm/shared/start/arm-a9mpcore-smp.c
@@ -59,7 +59,6 @@ void _CPU_SMP_Send_interrupt( uint32_t target_processor_index
)
{
arm_gic_irq_generate_software_irq(
ARM_GIC_IRQ_SGI_0,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
1U << target_processor_index
);
}
diff --git a/bsps/include/dev/irq/arm-gic-irq.h
b/bsps/include/dev/irq/arm-gic-irq.h
index ae0a68f7bb..34bf34353e 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -79,28 +79,17 @@ void bsp_interrupt_get_affinity(
Processor_mask *affinity
);
-typedef enum {
- ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
- ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF,
- ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF
-} arm_gic_irq_software_irq_target_filter;
-
-void arm_gic_trigger_sgi(
- rtems_vector_number vector,
- arm_gic_irq_software_irq_target_filter filter,
- uint32_t targets
-);
+void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets);
static inline rtems_status_code arm_gic_irq_generate_software_irq(
rtems_vector_number vector,
- arm_gic_irq_software_irq_target_filter filter,
uint32_t targets
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
if (vector <= ARM_GIC_IRQ_SGI_15) {
-arm_gic_trigger_sgi(vector, filter, targets);
+arm_gic_trigger_sgi(vector, targets);
} else {
sc = RTEMS_INVALID_ID;
}
diff --git a/bsps/include/dev/irq/arm-gic-tm27.h
b/bsps/include/dev/irq/arm-gic-tm27.h
index bfec3b22e0..ca3663a0f8 100644
--- a/bsps/include/dev/irq/arm-gic-tm27.h
+++ b/bsps/include/dev/irq/arm-gic-tm27.h
@@ -80,7 +80,6 @@ static inline void Cause_tm27_intr(void)
{
rtems_status_code sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_LOW,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
1U << (arm_cp15_get_multiprocessor_affinity() & 0xff)
);
assert(sc == RTEMS_SUCCESSFUL);
@@ -95,7 +94,6 @@ static inline void Lower_tm27_intr(void)
{
rtems_status_code sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_HIGH,
-ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
1U << (arm_cp15_get_multiprocessor_affinity() & 0xff)
);
assert(sc == RTEMS_SUCCESSFUL);
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index 9560a90d6b..bd614bc1d8 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -258,15 +258,11 @@ void bsp_interrupt_get_affinity(
_Processor_mask_From_uint32_t(affinity, targets, 0);
}
-void arm_gic_trigger_sgi(
- rtems_vector_number vector,
- arm_gic_irq_software_irq_target_filter filter,
- uint32_t targets
-)
+void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
{
volatile gic_dist *dist = ARM_GIC_DIST;
- dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
+ dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(0)
| GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
| GIC_DIST_ICDSGIR_NSATT
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 2bedaefcef..520a728170 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -337,16 +337,8 @@ void bsp_interrupt_get_affinity(
_Processor_mask_From_uint32_t(affinity, targets, 0);
}
-void arm_gic_trigger_sgi(
- rtems_vector_number vector,
- arm_gic_irq_software_irq_target_filter filter,
- uint32_t targets
-)
+void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
{
- /* TODO(kmoore) Handle filter:
- * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
- * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF,
- * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF */
#ifndef ARM_MULTILIB_ARCH_V4
uint64_t mpidr;
#else
--
2.26.2
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