-----Original Message-----
From: devel <devel-boun...@rtems.org> On Behalf Of Sebastian Huber
Sent: Wednesday, December 9, 2020 10:33
To: devel@rtems.org
Subject: [PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()
> Use the targets parameter to determine the targets of the SGI.
>
> Update #4202.
> ---
> v2: Fix tm27 test support.
>
> bsps/include/dev/irq/arm-gic-tm27.h | 8 ++++----
> bsps/shared/dev/irq/arm-gicv3.c | 2 +-
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/bsps/include/dev/irq/arm-gic-tm27.h
> b/bsps/include/dev/irq/arm-gic-tm27.h
> index 95f3077716..8edacc39e4 100644
> --- a/bsps/include/dev/irq/arm-gic-tm27.h
> +++ b/bsps/include/dev/irq/arm-gic-tm27.h
> @@ -79,8 +79,8 @@ static inline void Cause_tm27_intr(void) {
> rtems_status_code sc = arm_gic_irq_generate_software_irq(
> ARM_GIC_TM27_IRQ_LOW,
> - ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
> - 0
> + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
> + 1
> );
> assert(sc == RTEMS_SUCCESSFUL);
> }
> @@ -94,8 +94,8 @@ static inline void Lower_tm27_intr(void) {
> rtems_status_code sc = arm_gic_irq_generate_software_irq(
> ARM_GIC_TM27_IRQ_HIGH,
> - ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
> - 0
> + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
> + 1
These changes will work on core 0, but will fail if running on any other core
which is a change in behavior for this test.
> diff --git a/bsps/shared/dev/irq/arm-gicv3.c
> b/bsps/shared/dev/irq/arm-gicv3.c index db10371c72..569c7610c4 100644
> --- a/bsps/shared/dev/irq/arm-gicv3.c
> +++ b/bsps/shared/dev/irq/arm-gicv3.c
> @@ -356,7 +356,7 @@ void arm_gic_trigger_sgi(
> uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
> | ICC_SGIR_INTID(vector)
> | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
> - | ICC_SGIR_CPU_TARGET_LIST(1);
> + | ICC_SGIR_CPU_TARGET_LIST(targets);
I think my processor filter todo just above this code will need to be addressed
along with this change for correct behavior on non-core 0 runs of tm27.
Kinsey
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