[PATCH 1/6] Patches for the OR1k CPU handling and definitions
From: Jakob Viketoft
---
cpukit/score/cpu/or1k/cpu.c | 18 +-
cpukit/score/cpu/or1k/rtems/score/cpu.h | 47 ++---
cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 244 --
3 files changed, 251 insertions(+), 58 deletions(-)
diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
index 3cf6f6b..c52c48b 100644
--- a/cpukit/score/cpu/or1k/cpu.c
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -34,26 +34,20 @@ void _CPU_Initialize(void)
* @brief Sets the hardware interrupt level by the level value.
*
* @param[in] level for or1k can only range over two values:
- * 0 (enable interrupts) and 1 (disable interrupts). In future
- * implementations if fast context switch is implemented, the level
- * can range from 0 to 15. @see OpenRISC architecture manual.
- *
+ * 0 (enable interrupts) and 1 (disable interrupts).
*/
void _CPU_ISR_Set_level(uint32_t level)
{
uint32_t sr = 0;
- level = (level > 0)? 1 : 0;
-
- /* map level bit to or1k interrupt enable/disable bit in sr register */
- level <<= CPU_OR1K_SPR_SR_SHAMT_IEE;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
- if (level == 0){ /* Enable all interrupts */
+ if (level > 0) {
+/* Interrupts disable */
+sr &= ~(CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE);
+ } else {
+/* Interrupts enable */
sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
-
- } else{
-sr &= ~CPU_OR1K_SPR_SR_IEE;
}
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h
b/cpukit/score/cpu/or1k/rtems/score/cpu.h
index 7364343..740bdda 100644
--- a/cpukit/score/cpu/or1k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
@@ -6,6 +6,9 @@
* This include file contains macros pertaining to the Opencores
* or1k processor family.
*
+ * COPYRIGHT (c) 2016 ÅAC Microtec AB
+ * Jakob Viketoft
+ * David Hennerström
* COPYRIGHT (c) 2014 Hesham ALMatary
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
@@ -505,25 +508,14 @@ static inline uint32_t or1k_interrupt_disable( void )
uint32_t sr;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
- _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE));
-
- return sr;
-}
-
-static inline void or1k_interrupt_enable(uint32_t level)
-{
- uint32_t sr;
-
- /* Enable interrupts and restore rs */
- sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
- _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~(CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+ return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1;
}
#define _CPU_ISR_Disable( _level ) \
_level = or1k_interrupt_disable()
-
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
@@ -531,6 +523,20 @@ static inline void or1k_interrupt_enable(uint32_t level)
*
*/
+static inline void or1k_interrupt_enable(uint32_t level)
+{
+ uint32_t sr;
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ if (level > 0) {
+/* Effectively disable interrupts */
+_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~(CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+return;
+ }
+
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr | (CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+}
+
#define _CPU_ISR_Enable( _level ) \
or1k_interrupt_enable( _level )
@@ -545,7 +551,7 @@ static inline void or1k_interrupt_enable(uint32_t level)
#define _CPU_ISR_Flash( _level ) \
do{ \
_CPU_ISR_Enable( _level ); \
- _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \
+ or1k_interrupt_disable(); \
} while(0)
/*
@@ -795,16 +801,9 @@ typedef uint16_t Priority_bit_map_Word;
typedef struct {
uint32_t r[32];
- /* The following registers must be saved if we have
- fast context switch disabled and nested interrupt
- levels are enabled.
- */
-#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED
- uint32_t epcr; /* exception PC register */
- uint32_t eear; /* exception effective address register */
- uint32_t esr; /* exception supervision register */
-#endif
-
+ uint32_t epcr; /* Exception PC register */
+ uint32_t eear; /* Exception effective address register */
+ uint32_t esr; /* Exception supervision register */
} CPU_Exception_frame;
/**
diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
index 98bbe41..995f3ee 100644
--- a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
+++ b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
@@ -4,6 +4,9 @@
* @brief OR1K utility
*/
/*
+ * COPYRIGHT (c) 2014-2015 ÅAC Microtec AB
+ * Karol Gugala
+ * Jakob Viketoft
* COPYRIGHT (c) 2014 Hesham ALMatary
*
* The license and distribution terms for this file may be
@@ -26,8 +29,8 @@
#define SPR_GRP7_PERF_CTR (7 << SPR_GRP_SHAMT)
#define SPR_GRP8_PWR_MNG (8 << SPR_GRP_SHAMT)
[PATCH 2/6] OR1k exception handling and start code
From: Jakob Viketoft - Correct start vector table. - Add proper init of registers and caches - Add more information on unhandled exceptions - Use defines instead of hardcoded values for readability --- c/src/lib/libbsp/or1k/generic_or1k/start/start.S | 258 +--- cpukit/score/cpu/or1k/or1k-exception-default.c |1 + cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 11 +- cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 220 - 4 files changed, 343 insertions(+), 147 deletions(-) diff --git a/c/src/lib/libbsp/or1k/generic_or1k/start/start.S b/c/src/lib/libbsp/or1k/generic_or1k/start/start.S index 26991c8..7a182df 100644 --- a/c/src/lib/libbsp/or1k/generic_or1k/start/start.S +++ b/c/src/lib/libbsp/or1k/generic_or1k/start/start.S @@ -1,11 +1,16 @@ /* * Copyright (c) 2014-2015 Hesham ALMatary + * Copyright (c) 2014-2016 ÅAC Microtec AB + * Jakob Viketoft * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE */ #include +#include + + .extern _ISR_Handler /* The following macro defines the first instructions every exception * should execute before jumping to its handler function from the @@ -16,34 +21,22 @@ */ #define EXCEPTION_SETUP(vector) \ l.nop ;\ - l.addi r1, r1, -200 ;\ - l.sw0(r1), r3; \ + /* Add space for redzone and make space on the current stack \ + * (from the interrupted thread) */ \ + l.addi r1, r1, -(REDZONE_SIZE + EX_FRAME_SIZE); \ + l.swOR1K_EC_GPR3(r1), r3; \ l.addi r3, r0, vector; \ l.j _ISR_Handler; \ l.nop .extern boot_card - .extern bsp_section_bss_begin - .extern bsp_section_bss_end - - .extern bsp_start_vector_table_end - .extern bsp_start_vector_table_size - .extern bsp_vector_table_size - .extern bsp_section_stack_begin - - .extern exception_frame_save - .extern _OR1K_Exception_Process .extern _OR1K_Exception_default - .extern rtems_clock_tick - .extern _exit - .extern printk - .extern bsp_interrupt_handler_default /* Global symbols */ .global _start .global bsp_start_vector_table_begin -/* Popualte HW vector table */ +/* Populate HW vector table */ .section .vector, "ax" @@ -61,7 +54,7 @@ _dPageFault: EXCEPTION_SETUP(3) .org 0x400 -_iPageFaule: +_iPageFault: EXCEPTION_SETUP(4) .org 0x500 @@ -105,18 +98,74 @@ _trap: EXCEPTION_SETUP(14) .org 0xF00 -_undef1: +_res_future1: EXCEPTION_SETUP(15) -.org 0x1500 -_undef2: +.org 0x1000 +_res_future2: EXCEPTION_SETUP(16) -.org 0x1900 -_undef3: +.org 0x1100 +_res_future3: EXCEPTION_SETUP(17) +.org 0x1200 +_res_future4: + EXCEPTION_SETUP(18) + +.org 0x1300 +_res_future5: + EXCEPTION_SETUP(19) + +.org 0x1400 +_res_future6: + EXCEPTION_SETUP(20) + +.org 0x1500 +_res_impspec1: + EXCEPTION_SETUP(21) + +.org 0x1600 +_res_impspec2: + EXCEPTION_SETUP(22) + +.org 0x1700 +_res_impspec3: + EXCEPTION_SETUP(23) + +.org 0x1800 +_res_impspec4: + EXCEPTION_SETUP(24) + +.org 0x1900 +_res_custom1: + EXCEPTION_SETUP(25) + +.org 0x1A00 +_res_custom2: + EXCEPTION_SETUP(26) + +.org 0x1B00 +_res_custom3: + EXCEPTION_SETUP(27) + +.org 0x1C00 +_res_custom4: + EXCEPTION_SETUP(28) + +.org 0x1D00 +_res_custom5: + EXCEPTION_SETUP(29) + +.org 0x1E00 +_res_custom6: + EXCEPTION_SETUP(30) + .org 0x1F00 +_res_custom7: + EXCEPTION_SETUP(31) + +.org 0x2000 bsp_start_vector_table_begin: @@ -127,7 +176,7 @@ bsp_start_vector_table_begin: .word _OR1K_Exception_default /* Instruction Page Fault */ .word _OR1K_Exception_default /* Tick timer */ .word _OR1K_Exception_default /* Alignment */ - .word _OR1K_Exception_default /* Undefiend Instruction */ + .word _OR1K_Exception_default /* Undefined Instruction */ .word _OR1K_Exception_default /* External Interrupt */ .word _OR1K_Exception_default /* Data TLB Miss */ .word _OR1K_Exception_default /* Instruction TLB Miss */ @@ -135,8 +184,22 @@ bsp_start_vector_table_begin: .word _OR1K_Exception_default /* System Call */ .word _OR1K_Exception_default /* Floating Point Exception */ .word _OR1K_Exception_default /* Trap */ - .word _OR1K_Exception_default /* Reserver for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for implementation-specific */ .word _OR1K_Exception_default /* Reserved for implementation-specific */ + .word _OR1K_Exception
[PATCH 4/6] generic_or1k BSP clock driver correction
From: Jakob Viketoft
- Improve the clock driver to use RTEMS default tick period
or the on the one supplied by the application
- Avoid rewriting the timer settings, since all we need is to clear the
interrupt
- Remove any mention of or1ksim in favour of generic_or1k
---
.../lib/libbsp/or1k/generic_or1k/clock/clockdrv.c | 105 ++--
1 file changed, 51 insertions(+), 54 deletions(-)
diff --git a/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c
b/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c
index e01d2e5..2dc914a 100644
--- a/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c
+++ b/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c
@@ -3,13 +3,15 @@
*
* @ingroup bsp_clock
*
- * @brief or1k clock support.
+ * @brief generic_or1k clock support.
*/
/*
* generic_or1k Clock driver
*
* COPYRIGHT (c) 2014-2015 Hesham ALMatary
+ * Copyright (c) 2014-2016 ÅAC Microtec AB
+ * Jakob Viketoft
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -25,35 +27,30 @@
#include
/* The number of clock cycles before generating a tick timer interrupt. */
-#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 0x09ED9
-#define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS 10
+#define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS (10 /
OR1K_BSP_CLOCK_FREQ)
-static struct timecounter or1ksim_tc;
-
-/* CPU counter */
+static struct timecounter generic_or1k_tc;
static CPU_Counter_ticks cpu_counter_ticks;
+static uint32_t timer_counts_per_clock_tick;
-/* This prototype is added here to Avoid warnings */
+/* These prototypes are added here to avoid warnings */
void Clock_isr(void *arg);
+static uint32_t generic_or1k_get_timecount(struct timecounter *tc);
static void generic_or1k_clock_at_tick(void)
{
- uint32_t TTMR;
+ uint32_t ttmr;
- /* For TTMR register,
- * The least significant 28 bits are the number of clock cycles
- * before generating a tick timer interrupt. While the most
- * significant 4 bits are used for mode configuration, tick timer
- * interrupt enable and pending interrupts status.
- */
- TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
- (TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK)
- ) & ~(CPU_OR1K_SPR_TTMR_IP);
+ /* Get TTMR value */
+ ttmr = _OR1K_mfspr(CPU_OR1K_SPR_TTMR);
- _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
- _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
+ /* Clear interrupt */
+ ttmr &= ~(CPU_OR1K_SPR_TTMR_IP);
- cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT;
+ /* Write it back */
+ _OR1K_mtspr(CPU_OR1K_SPR_TTMR, ttmr);
+
+ cpu_counter_ticks += timer_counts_per_clock_tick;
}
static void generic_or1k_clock_handler_install(
@@ -61,35 +58,19 @@ static void generic_or1k_clock_handler_install(
proc_ptr old_isr
)
{
- rtems_status_code sc = RTEMS_SUCCESSFUL;
old_isr = NULL;
_CPU_ISR_install_vector(OR1K_EXCEPTION_TICK_TIMER,
new_isr,
old_isr);
-
- if (sc != RTEMS_SUCCESSFUL) {
-rtems_fatal_error_occurred(0xdeadbeef);
- }
-}
-
-static uint32_t or1ksim_get_timecount(struct timecounter *tc)
-{
- uint32_t ticks_since_last_timer_interrupt;
-
- ticks_since_last_timer_interrupt = _OR1K_mfspr(CPU_OR1K_SPR_TTCR);
-
- return cpu_counter_ticks + ticks_since_last_timer_interrupt;
-}
-
-CPU_Counter_ticks _CPU_Counter_read(void)
-{
- return or1ksim_get_timecount(NULL);
}
static void generic_or1k_clock_initialize(void)
{
- uint64_t frequency = (10 / OR1K_CLOCK_CYCLE_TIME_NANOSECONDS);
- uint32_t TTMR;
+ uint32_t ttmr;
+
+ /* Calculate timer value for given time per clock tick */
+ timer_counts_per_clock_tick = (1000 *
rtems_configuration_get_microseconds_per_tick()) /
+OR1K_CLOCK_CYCLE_TIME_NANOSECONDS;
/* For TTMR register,
* The least significant 28 bits are the number of clock cycles
@@ -101,36 +82,52 @@ static void generic_or1k_clock_initialize(void)
/* FIXME: Long interval should pass since initializing the tick timer
* registers fires exceptions dispite interrupts has not been enabled yet.
*/
- TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
- (0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK)
- ) & ~(CPU_OR1K_SPR_TTMR_IP);
+ ttmr = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
+ (timer_counts_per_clock_tick & CPU_OR1K_SPR_TTMR_TP_MASK)) &
+~(CPU_OR1K_SPR_TTMR_IP);
- _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
+ _OR1K_mtspr(CPU_OR1K_SPR_TTMR, ttmr);
_OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
+ /* Initialize CPU Counter */
+ cpu_counter_ticks = 0;
+
/* Initialize timecounter */
- or1ksim_tc.tc_get_timecount = or1ksim_get_timecount;
- or1ksim_tc.tc_counter_mask = 0x;
- or1ksim_tc.tc_frequency = frequency;
- or1ksim_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
- rtems_timecounter_install(&or1ksim_tc);
+ generic_or1k_t
[PATCH 3/6] Improve OR1k context handling
From: Jakob Viketoft
---
cpukit/score/cpu/or1k/or1k-context-initialize.c | 13 ++-
cpukit/score/cpu/or1k/or1k-context-switch.S | 113 ---
2 files changed, 69 insertions(+), 57 deletions(-)
diff --git a/cpukit/score/cpu/or1k/or1k-context-initialize.c
b/cpukit/score/cpu/or1k/or1k-context-initialize.c
index a7205e3..d37458e 100644
--- a/cpukit/score/cpu/or1k/or1k-context-initialize.c
+++ b/cpukit/score/cpu/or1k/or1k-context-initialize.c
@@ -29,13 +29,22 @@ void _CPU_Context_Initialize(
void *tls_area
)
{
- /* Decrement 200 byte to account for red-zone */
- uint32_t stack = ((uint32_t) stack_area_begin) - 200;
+ /* Decrement to account for redzone */
+ uint32_t stack = ((uint32_t) stack_area_begin) - REDZONE_SIZE;
uint32_t sr;
uint32_t stack_high = stack + stack_area_size;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+ /* Make sure we will adhere to the requested level */
+ if (new_level > 0) {
+/* Interrupts disable in our local sr */
+sr &= ~(CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE);
+ } else {
+/* Interrupts enable in our local sr */
+sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
+ }
+
memset(context, 0, sizeof(*context));
context->r1 = stack_high;
diff --git a/cpukit/score/cpu/or1k/or1k-context-switch.S
b/cpukit/score/cpu/or1k/or1k-context-switch.S
index 91521e4..2a98cac 100644
--- a/cpukit/score/cpu/or1k/or1k-context-switch.S
+++ b/cpukit/score/cpu/or1k/or1k-context-switch.S
@@ -22,93 +22,96 @@ PUBLIC(_CPU_Context_restore_fp)
PUBLIC(_CPU_Context_save_fp)
SYM(_CPU_Context_switch):
- l.sw 0(r3),r1
- l.sw 4(r3),r2
- l.sw 8(r3),r3
- l.sw 12(r3),r4
- l.sw 16(r3),r5
- l.sw 20(r3),r6
- l.sw 24(r3),r7
- l.sw 28(r3),r8
- l.sw 32(r3),r9
- /* Skip r10 as it's preserved to be used by TLS */
- /* The following set if registers are preserved across function calls */
- l.sw 52(r3),r14
- l.sw 60(r3),r16
- l.sw 68(r3),r18
- l.sw 76(r3),r20
- l.sw 84(r3),r22
- l.sw 92(r3),r24
- l.sw 100(r3),r26
- l.sw 108(r3),r28
- l.sw 116(r3),r30
+ l.swOR1K_CC_GPR1(r3), r1
+ l.swOR1K_CC_GPR2(r3), r2
+ l.swOR1K_CC_GPR3(r3), r3
+ l.swOR1K_CC_GPR4(r3), r4
+ l.swOR1K_CC_GPR5(r3), r5
+ l.swOR1K_CC_GPR6(r3), r6
+ l.swOR1K_CC_GPR7(r3), r7
+ l.swOR1K_CC_GPR8(r3), r8
+ l.swOR1K_CC_GPR9(r3), r9
+ /* The following set of registers are preserved across function calls
+ * (callee-saved) */
+ l.swOR1K_CC_GPR10(r3), r10
+ l.swOR1K_CC_GPR12(r3), r12
+ l.swOR1K_CC_GPR14(r3), r14
+ l.swOR1K_CC_GPR16(r3), r16
+ l.swOR1K_CC_GPR18(r3), r18
+ l.swOR1K_CC_GPR20(r3), r20
+ l.swOR1K_CC_GPR22(r3), r22
+ l.swOR1K_CC_GPR24(r3), r24
+ l.swOR1K_CC_GPR26(r3), r26
+ l.swOR1K_CC_GPR28(r3), r28
+ l.swOR1K_CC_GPR30(r3), r30
/* Supervision Register */
- l.mfspr r13,r0, CPU_OR1K_SPR_SR
- l.sw 124(r3),r13
+ l.mfspr r13, r0, CPU_OR1K_SPR_SR
+ l.swOR1K_CC_SR(r3), r13
/* EPCR */
l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
- l.sw 128(r3), r13 /* epcr */
+ l.swOR1K_CC_EPCR0(r3), r13
/* EEAR */
l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
- l.sw 132(r3), r13 /* eear */
+ l.swOR1K_CC_EEAR0(r3), r13
/* ESR */
l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
- l.sw 136(r3), r13 /* esr */
+ l.swOR1K_CC_ESR0(r3), r13
SYM(restore):
- l.lwz r13,124(r4)
- l.mtspr r0,r13, CPU_OR1K_SPR_SR
-
- /* Exception level related registers */
+ l.lwz r13, OR1K_CC_SR(r4)
+ l.mtspr r0, r13, CPU_OR1K_SPR_SR
/* EPCR */
- l.lwz r13, 128(r4)
+ l.lwz r13, OR1K_CC_EPCR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
/* EEAR */
- l.lwz r13, 132(r4)
+ l.lwz r13, OR1K_CC_EEAR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
/* ESR */
- l.lwz r13, 136(r4)
+ l.lwz r13, OR1K_CC_ESR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
- l.lwz r1,0(r4)
- l.lwz r2,4(r4)
- l.lwz r3,8(r4)
+ l.lwz r1, OR1K_CC_GPR1(r4)
+ l.lwz r2, OR1K_CC_GPR2(r4)
+ l.lwz r3, OR1K_CC_GPR3(r4)
/* Skip r4 as it contains the current buffer address */
- l.lwz r5,16(r4)
- l.lwz r6,20(r4)
- l.lwz r7,24(r4)
- l.lwz r8,28(r4)
- l.lwz r9,32(r4)
- l.lwz r14,52(r4)
- l.lwz r16,60(r4)
- l.lwz r18,68(r4)
- l.lwz r20,76(r4)
- l.lwz r22,84(r4)
- l.lwz r24,92(r4)
- l.lwz r26,100(r4)
- l.lwz r28,108(r4)
- l.lwz r30,116(r4)
-
- l.lwz r4,12(r4)
-
- l.jr r9
+ l.lwz r5, OR1K_CC_GPR5(r4)
+ l.lwz r6, OR1K_CC_GPR6(r4)
+ l.lwz r7, OR1K_CC_GPR7(r4)
+ l.lwz r8, OR1K_CC_GPR8(r4)
+ l.lwz r9, OR1K_CC_GPR9(r4)
+ l.lwz r10, OR1K_CC_GPR10(r4)
+ l.lwz r12, OR1K_CC_GPR12(r4)
+ l.lwz r14, OR1K_CC_GPR14(r4)
+ l.lwz r16, OR1K_CC_GPR16(r4)
+ l.lwz r18, OR1K_CC_GPR18(r4)
+ l.lwz r20, OR1K_CC_GPR20(r4)
+ l.lwz r22, OR1K_CC_GPR22(r4)
+ l.lwz r24, OR1K_CC_GPR24(r4)
+ l.lwz r26, OR1K_CC_GPR26(r4)
+ l.lwz r28, OR1K_CC_GPR28(r4)
+ l.lwz r30, OR1K_CC_GPR30(r4)
+
+ l.lwz r4, OR1K_CC_GPR4(r4)
+
+ l.jrr9
[PATCH 6/6] OR1k cache invalidate additions
From: Jakob Viketoft
---
c/src/lib/libcpu/or1k/shared/cache/cache.c | 86 ++--
1 file changed, 67 insertions(+), 19 deletions(-)
diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c
b/c/src/lib/libcpu/or1k/shared/cache/cache.c
index d17fec2..49f5ca9 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
@@ -4,9 +4,14 @@
* COPYRIGHT (c) 1989-2006
* On-Line Applications Research Corporation (OAR).
*
+ * Copyright (c) 2014 ÅAC Microtec AB
+ * Contributor(s):
+ * Karol Gugala
+ *
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
+ *
*/
#include
@@ -14,13 +19,15 @@
#include
#include
#include
+#include
static inline void _CPU_OR1K_Cache_enable_data(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
+
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
@@ -30,7 +37,7 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
static inline void _CPU_OR1K_Cache_disable_data(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
@@ -43,7 +50,7 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
static inline void _CPU_OR1K_Cache_enable_instruction(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
@@ -79,7 +86,8 @@ static inline void _CPU_OR1K_Cache_data_block_prefetch(const
void *d_addr)
static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
@@ -89,7 +97,8 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const
void *d_addr)
static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
@@ -99,7 +108,8 @@ static inline void
_CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
@@ -109,7 +119,8 @@ static inline void
_CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
@@ -120,7 +131,8 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const
void *d_addr)
static inline void _CPU_OR1K_Cache_instruction_block_prefetch
(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
@@ -131,7 +143,8 @@ static inline void
_CPU_OR1K_Cache_instruction_block_prefetch
static inline void _CPU_OR1K_Cache_instruction_block_invalidate
(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
@@ -142,7 +155,8 @@ static inline void
_CPU_OR1K_Cache_instruction_block_invalidate
static inline void _CPU_OR1K_Cache_instruction_block_lock
(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
@@ -152,9 +166,11 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
/* Implement RTEMS cache manager functions */
-void _CPU_cache_flush_1_data_line(const void *d_addr)
+void _CPU_cache_flush_1_data_line
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_CPU_OR1K_Cache_data_block_flush(d_addr);
@@ -164,9 +180,11 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
_ISR_Enable(level);
}
-void _CPU_cache_invalidate_1_data_line(const void *d_addr)
+void _CPU_cache_invalidate_1_data_line
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_CPU_OR1K_Cache_data_block_invalidate(d_addr);
@@ -184,9 +202,11 @@ void _CPU_cache_unfreeze_data(void)
/* Do nothing */
}
-void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
+void _CPU_cache_invalidate_1_instruction_line
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
@@ -206,17 +226,45 @@ void _CPU_cache_unfreeze_instruction(void)
void _CPU_cache_flush_entire_data(void)
{
-
+ int addr;
+
+ /* We have only 0 level cache so we do not need to invalidate others */
+ for (addr = _CPU_cache_get_data_cache_size(0);
+ addr > 0;
+ addr -= CPU_DATA_CACHE_ALIGNMENT) {
+_CPU_OR1K_Cache_data
[PATCH 5/6] OR1k shared and generic_or1k BSP link script rewrite
From: Jakob Viketoft
- Rewrote the link scripts to make more sense and to correct
the weird stack calculations previously made
---
.../lib/libbsp/or1k/generic_or1k/startup/linkcmds | 12 +-
.../libbsp/or1k/shared/include/linker-symbols.h|8 +-
c/src/lib/libbsp/or1k/shared/startup/linkcmds.base | 370
3 files changed, 151 insertions(+), 239 deletions(-)
diff --git a/c/src/lib/libbsp/or1k/generic_or1k/startup/linkcmds
b/c/src/lib/libbsp/or1k/generic_or1k/startup/linkcmds
index cef99d3..3a34186 100644
--- a/c/src/lib/libbsp/or1k/generic_or1k/startup/linkcmds
+++ b/c/src/lib/libbsp/or1k/generic_or1k/startup/linkcmds
@@ -8,16 +8,22 @@
/*
* COPYRIGHT (c) 2014 Hesham ALMatary
+ * Copyright (c) 2015 ÅAC Microtec AB
+ *Jakob Viketoft
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE
*/
+/* Set up system characteristics */
+HeapSize = 0;
+StackSize = 16K;
+
MEMORY
{
- VECTOR_RAM (AIW) : ORIGIN = 0x0 , LENGTH = 8260
- RAM : org = 0x2048, l = 0x1FFDFB8
+ VECTOR_RAM (AIW): ORIGIN = 0x, LENGTH = 8K + 128
+ RAM : ORIGIN = 0x2080, LENGTH = 32M - 8K - 128
UNEXPECTED_SECTIONS : ORIGIN = 0x, LENGTH = 0
}
@@ -35,7 +41,5 @@ REGION_ALIAS ("REGION_BSS", RAM);
REGION_ALIAS ("REGION_WORK", RAM);
REGION_ALIAS ("REGION_STACK", RAM);
-bsp_section_vector_begin = 0;
-bsp_section_stack_begin = 0x1FFDFB8;
INCLUDE linkcmds.base
diff --git a/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h
b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h
index f0f8377..bae619a 100644
--- a/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h
+++ b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h
@@ -1,5 +1,5 @@
-#ifndef LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H
-#define LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H
+#ifndef LIBBSP_OR1K_SHARED_LINKER_SYMBOLS_H
+#define LIBBSP_OR1K_SHARED_LINKER_SYMBOLS_H
#ifdef __cplusplus
extern "C" {
@@ -59,10 +59,6 @@ LINKER_SYMBOL(bsp_section_stack_begin)
LINKER_SYMBOL(bsp_section_stack_end)
LINKER_SYMBOL(bsp_section_stack_size)
-LINKER_SYMBOL(bsp_vector_table_begin)
-LINKER_SYMBOL(bsp_vector_table_end)
-LINKER_SYMBOL(bsp_vector_table_size)
-
LINKER_SYMBOL(bsp_start_vector_table_begin)
LINKER_SYMBOL(bsp_start_vector_table_end)
LINKER_SYMBOL(bsp_start_vector_table_size)
diff --git a/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base
b/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base
index 31bb92d..1d40668 100644
--- a/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base
+++ b/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base
@@ -8,6 +8,8 @@
/*
* COPYRIGHT (c) 2014 Hesham ALMatary
+ * COPYRIGHT (c) 2015 ÅAC Microtec
+ *Jakob Viketoft
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -19,35 +21,49 @@ OUTPUT_ARCH (or1k)
ENTRY (_start)
/*
- * Global symbols that may be defined externally
+ * The memory map looks like this:
+ * ++ <- low memory
+ * | .vector| exception vectors and exception
+ * || handler's table
+ * ++
+ * | .start | entry point (setup) code
+ * ++
+ * | .text |
+ * |init|
+ * |fini|
+ * |ctor list | the ctor and dtor lists are for
+ * |dtor list | C++ support
+ * |eh_frame|
+ * |etext |
+ * ++
+ * | .tdata | TLS data
+ * ++
+ * | .tbss | TLS bss
+ * ++
+ * | .data | initialized data goes here
+ * ++
+ * | .bss | section cleared by entry code
+ * ++
+ * | .stack |
+ * ++ <- high memory (top of stack)
*/
-bsp_start_vector_table_begin = 0x1F00;
-bsp_vector_table_size = DEFINED (bsp_vector_table_size) ? bsp_vector_table_size
-: 8260;
-/* 8192 for raw vector table, and 17 * 4 for handlers vector. */
+/* Make sure we have predefined some crucial variables */
+StackSize = DEFINED (StackSize) ? StackSize : 16K;
+HeapSize = DEFINED (HeapSize) ? HeapSize : 0;
-bsp_section_xbarrier_align = DEFINED (bsp_section_xbarrier_align) ?
bsp_section_xbarrier_align : 1;
-bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ?
bsp_section_robarrier_align : 1;
-bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ?
bsp_section_rwbarrier_align : 1;
-
-bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 8;
-
-bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0;
-bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
-
-bsp_processor_count = DEFINED (bsp_processor_count) ? b
Re: [PATCH] testsuits: Fixed typo in fileio.doc
Please re-send without the signed-off-by line. Also, the first line of your commit message was fine. The extra line is redundant to it. On Sat, Feb 20, 2016 at 1:27 AM, punitvara wrote: > This patch basically fixes some typo in document file. > > Signed-off: Punit Vara > --- > testsuites/samples/fileio/fileio.doc | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/testsuites/samples/fileio/fileio.doc > b/testsuites/samples/fileio/fileio.doc > index 0a43601..95d50b1 100644 > --- a/testsuites/samples/fileio/fileio.doc > +++ b/testsuites/samples/fileio/fileio.doc > @@ -22,17 +22,17 @@ A sample session might look like this: > - start this system > > - select "p" (part_table_initialize) to read in the partition table of > -first harddisk, enter the device name "/dev/hda", when prompted > +first hard disk, enter the device name "/dev/hda", when prompted > > - select "f" (fsmount) to try to mount the partitions > - /dev/hda1../dev/hdc4 to corresponding mount points. Non-existant > + /dev/hda1../dev/hdc4 to corresponding mount points. Non-existent >partitions will report an error, but will not abort the tests > > - select "w" (write file) to create a new file on the mounted disk (or >in the IMFS). Enter the file name (e.g. "/mnt/hda1/test_1M.txt"), >the file size (e.g. 64K or 2M) and the buffer size to use for the >write calls (e.g. 32 or 4K). Then the sample will try to write the > - corresponding file and print the time consumed and data rate achived. > + corresponding file and print the time consumed and data rate achieved. > > - select "r" (read file) to read a file (without displaying the >contents). It has similar parameters as "write file", but does not > -- > 2.7.1 > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/6] Patches for the OR1k CPU handling and definitions
Hi Jakob,
I should have mentioned yesterday that you ought to open one or more
tickets on our Trac (devel.rtems.org) and then reference those tickets
in your commit messages using e.g. "updates #" or "fixes #".
Also, if your test cases are suitably generic and useful, you might
consider providing them as separate contributions to improve RTEMS
test suite.
> diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h
> b/cpukit/score/cpu/or1k/rtems/score/cpu.h
> index 7364343..740bdda 100644
> --- a/cpukit/score/cpu/or1k/rtems/score/cpu.h
> +++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
...
> @@ -385,6 +574,17 @@ static inline void _OR1K_Sync_pipeline( void )
> #define _OR1KSIM_CPU_Halt() \
> asm volatile ("l.nop 0xc")
>
> +static inline uint32_t _OR1K_Find_First_One(uint32_t value)
Probably should be using _OR1K_Find_first_one() -- see also
https://devel.rtems.org/wiki/Developer/Coding/NamingRules
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 6/6] OR1k cache invalidate additions
On Sat, Feb 20, 2016 at 3:34 AM, wrote:
> From: Jakob Viketoft
>
> ---
> c/src/lib/libcpu/or1k/shared/cache/cache.c | 86
> ++--
> 1 file changed, 67 insertions(+), 19 deletions(-)
>
> diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c
> b/c/src/lib/libcpu/or1k/shared/cache/cache.c
> index d17fec2..49f5ca9 100644
> --- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
> +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
> @@ -4,9 +4,14 @@
> * COPYRIGHT (c) 1989-2006
> * On-Line Applications Research Corporation (OAR).
> *
> + * Copyright (c) 2014 ÅAC Microtec AB
> + * Contributor(s):
> + * Karol Gugala
> + *
> * The license and distribution terms for this file may be
> * found in the file LICENSE in this distribution or at
> * http://www.rtems.org/license/LICENSE.
> + *
> */
>
> #include
> @@ -14,13 +19,15 @@
> #include
> #include
> #include
> +#include
>
> static inline void _CPU_OR1K_Cache_enable_data(void)
> {
>uint32_t sr;
> - ISR_Level level;
> + ISR_Level level;
>
>_ISR_Disable (level);
> +
>sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
>_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
>
> @@ -30,7 +37,7 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
> static inline void _CPU_OR1K_Cache_disable_data(void)
> {
>uint32_t sr;
> - ISR_Level level;
> + ISR_Level level;
>
>_ISR_Disable (level);
>
> @@ -43,7 +50,7 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
> static inline void _CPU_OR1K_Cache_enable_instruction(void)
> {
>uint32_t sr;
> - ISR_Level level;
> + ISR_Level level;
>
>_ISR_Disable (level);
>
> @@ -79,7 +86,8 @@ static inline void
> _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
>
> static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
> @@ -89,7 +97,8 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const
> void *d_addr)
>
> static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
> @@ -99,7 +108,8 @@ static inline void
> _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
>
> static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
> @@ -109,7 +119,8 @@ static inline void
> _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
>
> static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
> @@ -120,7 +131,8 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const
> void *d_addr)
> static inline void _CPU_OR1K_Cache_instruction_block_prefetch
> (const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
> @@ -131,7 +143,8 @@ static inline void
> _CPU_OR1K_Cache_instruction_block_prefetch
> static inline void _CPU_OR1K_Cache_instruction_block_invalidate
> (const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
> @@ -142,7 +155,8 @@ static inline void
> _CPU_OR1K_Cache_instruction_block_invalidate
> static inline void _CPU_OR1K_Cache_instruction_block_lock
> (const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
> @@ -152,9 +166,11 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
>
> /* Implement RTEMS cache manager functions */
>
> -void _CPU_cache_flush_1_data_line(const void *d_addr)
> +void _CPU_cache_flush_1_data_line
> +(const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_CPU_OR1K_Cache_data_block_flush(d_addr);
> @@ -164,9 +180,11 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
>_ISR_Enable(level);
> }
>
> -void _CPU_cache_invalidate_1_data_line(const void *d_addr)
> +void _CPU_cache_invalidate_1_data_line
> +(const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_CPU_OR1K_Cache_data_block_invalidate(d_addr);
> @@ -184,9 +202,11 @@ void _CPU_cache_unfreeze_data(void)
>/* Do nothing */
> }
>
> -void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
> +void _CPU_cache_invalidate_1_instruction_line
> +(const void *d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
>_ISR_Disable (level);
>
>_CPU_OR1K_Cache_instruction_block_invalidat
[PATCH] testsuits: Fixed typo in fileio.doc
This patch basically fixes some typo in document file. --- testsuites/samples/fileio/fileio.doc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testsuites/samples/fileio/fileio.doc b/testsuites/samples/fileio/fileio.doc index 0a43601..95d50b1 100644 --- a/testsuites/samples/fileio/fileio.doc +++ b/testsuites/samples/fileio/fileio.doc @@ -22,17 +22,17 @@ A sample session might look like this: - start this system - select "p" (part_table_initialize) to read in the partition table of -first harddisk, enter the device name "/dev/hda", when prompted +first hard disk, enter the device name "/dev/hda", when prompted - select "f" (fsmount) to try to mount the partitions - /dev/hda1../dev/hdc4 to corresponding mount points. Non-existant + /dev/hda1../dev/hdc4 to corresponding mount points. Non-existent partitions will report an error, but will not abort the tests - select "w" (write file) to create a new file on the mounted disk (or in the IMFS). Enter the file name (e.g. "/mnt/hda1/test_1M.txt"), the file size (e.g. 64K or 2M) and the buffer size to use for the write calls (e.g. 32 or 4K). Then the sample will try to write the - corresponding file and print the time consumed and data rate achived. + corresponding file and print the time consumed and data rate achieved. - select "r" (read file) to read a file (without displaying the contents). It has similar parameters as "write file", but does not -- 2.7.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
RE: [PATCH 1/6] Patches for the OR1k CPU handling and definitions
Hello Gedare,
From: devel [devel-boun...@rtems.org] on behalf of Gedare Bloom
[ged...@rtems.org]
Sent: Saturday, February 20, 2016 14:23
To: jakob.viket...@gmail.com
Cc: rtems-de...@rtems.org
Subject: Re: [PATCH 1/6] Patches for the OR1k CPU handling and definitions
>Hi Jakob,
>
>I should have mentioned yesterday that you ought to open one or more
>tickets on our Trac (devel.rtems.org) and then reference those tickets
>in your commit messages using e.g. "updates #" or "fixes #".
Right-oh. Feel like I'll be spamming the list with the same patches all over
again, but I'll get to it.
>Also, if your test cases are suitably generic and useful, you might
>consider providing them as separate contributions to improve RTEMS
>test suite.
I have considered that, but at the moment at least they're not in a clean
enough state to be presentable as such, but we might contribute something
later. In essence it's expansions on current tests (notably ticker), but still.
>> diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h
>> b/cpukit/score/cpu/or1k/rtems/score/cpu.h
>> index 7364343..740bdda 100644
>> --- a/cpukit/score/cpu/or1k/rtems/score/cpu.h
>> +++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
>...
>> @@ -385,6 +574,17 @@ static inline void _OR1K_Sync_pipeline( void )
>> #define _OR1KSIM_CPU_Halt() \
>> asm volatile ("l.nop 0xc")
>>
>> +static inline uint32_t _OR1K_Find_First_One(uint32_t value)
>Probably should be using _OR1K_Find_first_one() -- see also
>https://devel.rtems.org/wiki/Developer/Coding/NamingRules
Ok, I thought we followed the naming used earlier in the file, but looking at
the rules, the camelcase shouldn't have passed either. :) If I had done it from
scratch, I probably would have preferred an entire lower-case function name,
but as it is I thought I'd go along with what's already there (and at least
partly reviewed). Does this mean I should adjust some of the other names as
well, or just this one?
Thanks for checking!
>___
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Jakob Viketoft
Senior Engineer in RTL and embedded software
ÅAC Microtec AB
Dag Hammarskjölds väg 48
SE-751 83 Uppsala, Sweden
T: +46 702 80 95 97
http://www.aacmicrotec.com
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RE: [PATCH 6/6] OR1k cache invalidate additions
From: devel [devel-boun...@rtems.org] on behalf of Gedare Bloom
[ged...@rtems.org]
Sent: Saturday, February 20, 2016 14:35
To: jakob.viket...@gmail.com
Cc: rtems-de...@rtems.org
Subject: Re: [PATCH 6/6] OR1k cache invalidate additions
>On Sat, Feb 20, 2016 at 3:34 AM, wrote:
>> From: Jakob Viketoft
>
>When breaking lines in expressions, leave the first and last line empty,
>for (
>addr = ...();
>addr > 0;
>addr -= ...
>) {
>...
>}
Didn't see that. Will fix.
>> +_CPU_OR1K_Cache_data_block_flush((void*) addr);
>Casting int to void* is not a great idea. Consider using uintptr_t instead.
Oh, there was a number of other void-casts already there, so I didn't react to
this. I'll take a look at those too, then.
Jakob Viketoft
Senior Engineer in RTL and embedded software
ÅAC Microtec AB
Dag Hammarskjölds väg 48
SE-751 83 Uppsala, Sweden
T: +46 702 80 95 97
http://www.aacmicrotec.com
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Re: [PATCH 1/6] Patches for the OR1k CPU handling and definitions
On Sat, Feb 20, 2016 at 3:22 PM, Jakob Viketoft
wrote:
> Hello Gedare,
>
> From: devel [devel-boun...@rtems.org] on behalf of Gedare Bloom
> [ged...@rtems.org]
> Sent: Saturday, February 20, 2016 14:23
> To: jakob.viket...@gmail.com
> Cc: rtems-de...@rtems.org
> Subject: Re: [PATCH 1/6] Patches for the OR1k CPU handling and definitions
>
>>Hi Jakob,
>>
>>I should have mentioned yesterday that you ought to open one or more
>>tickets on our Trac (devel.rtems.org) and then reference those tickets
>>in your commit messages using e.g. "updates #" or "fixes #".
>
> Right-oh. Feel like I'll be spamming the list with the same patches all over
> again, but I'll get to it.
>
>>Also, if your test cases are suitably generic and useful, you might
>>consider providing them as separate contributions to improve RTEMS
>>test suite.
>
> I have considered that, but at the moment at least they're not in a clean
> enough state to be presentable as such, but we might contribute something
> later. In essence it's expansions on current tests (notably ticker), but
> still.
>
>>> diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h
>>> b/cpukit/score/cpu/or1k/rtems/score/cpu.h
>>> index 7364343..740bdda 100644
>>> --- a/cpukit/score/cpu/or1k/rtems/score/cpu.h
>>> +++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
>>...
>>> @@ -385,6 +574,17 @@ static inline void _OR1K_Sync_pipeline( void )
>>> #define _OR1KSIM_CPU_Halt() \
>>> asm volatile ("l.nop 0xc")
>>>
>>> +static inline uint32_t _OR1K_Find_First_One(uint32_t value)
>>Probably should be using _OR1K_Find_first_one() -- see also
>>https://devel.rtems.org/wiki/Developer/Coding/NamingRules
>
> Ok, I thought we followed the naming used earlier in the file, but looking at
> the rules, the camelcase shouldn't have passed either. :) If I had done it
> from scratch, I probably would have preferred an entire lower-case function
> name, but as it is I thought I'd go along with what's already there (and at
> least partly reviewed). Does this mean I should adjust some of the other
> names as well, or just this one?
>
You may adjust the others if they violate the pattern
_Package_Method_name() that is used in the score API. Sometimes things
slip through review.
> Thanks for checking!
>
>>___
>>devel mailing list
>>devel@rtems.org
>>http://lists.rtems.org/mailman/listinfo/devel
>
> Jakob Viketoft
> Senior Engineer in RTL and embedded software
>
> ÅAC Microtec AB
> Dag Hammarskjölds väg 48
> SE-751 83 Uppsala, Sweden
>
> T: +46 702 80 95 97
> http://www.aacmicrotec.com
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[PATCH 1/8] or1k: Add further defines and helper functions in header file
From: Jakob Viketoft Close #2596. --- cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 244 +-- 1 file changed, 222 insertions(+), 22 deletions(-) diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h index 98bbe41..0eefd0a 100644 --- a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h +++ b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h @@ -4,6 +4,9 @@ * @brief OR1K utility */ /* + * COPYRIGHT (c) 2014-2015 ÅAC Microtec AB + * Karol Gugala + * Jakob Viketoft * COPYRIGHT (c) 2014 Hesham ALMatary * * The license and distribution terms for this file may be @@ -26,8 +29,8 @@ #define SPR_GRP7_PERF_CTR (7 << SPR_GRP_SHAMT) #define SPR_GRP8_PWR_MNG (8 << SPR_GRP_SHAMT) #define SPR_GRP9_PIC (9 << SPR_GRP_SHAMT) -#define SPR_GPR10_TICK_TMR (10 << SPR_GRP_SHAMT) -#define SPR_GPR11_FPU (11 << SPR_GRP_SHAMT) +#define SPR_GRP10_TICK_TMR (10 << SPR_GRP_SHAMT) +#define SPR_GRP11_FPU (11 << SPR_GRP_SHAMT) /* SPR registers definitions */ @@ -196,8 +199,8 @@ #define CPU_OR1K_SPR_PICSR (SPR_GRP9_PIC + 2) /* Group10: Tick Timer registers */ -#define CPU_OR1K_SPR_TTMR (SPR_GPR10_TICK_TMR + 0) -#define CPU_OR1K_SPR_TTCR (SPR_GPR10_TICK_TMR + 1) +#define CPU_OR1K_SPR_TTMR (SPR_GRP10_TICK_TMR + 0) +#define CPU_OR1K_SPR_TTCR (SPR_GRP10_TICK_TMR + 1) /* Shift amount macros for bits position in Supervision Register */ #define CPU_OR1K_SPR_SR_SHAMT_SM (0) @@ -258,6 +261,114 @@ /*Context ID (Fast Context Switching) */ #define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) +/* + * Bit definitions for the Version Register + * + */ +#define CPU_OR1K_SPR_VR_VER 0xff00 /* Processor version */ +#define CPU_OR1K_SPR_VR_CFG 0x00ff /* Processor configuration */ +#define CPU_OR1K_SPR_VR_RES 0xffc0 /* Reserved */ +#define CPU_OR1K_SPR_VR_REV 0x003f /* Processor revision */ + +#define CPU_OR1K_SPR_VR_VER_OFF 24 +#define CPU_OR1K_SPR_VR_CFG_OFF 16 +#define CPU_OR1K_SPR_VR_REV_OFF 0 + +/* + * Bit definitions for the Unit Present Register + * + */ +#define CPU_OR1K_SPR_UPR_UP0x0001 /* UPR present */ +#define CPU_OR1K_SPR_UPR_DCP 0x0002 /* Data cache present */ +#define CPU_OR1K_SPR_UPR_ICP 0x0004 /* Instruction cache present */ +#define CPU_OR1K_SPR_UPR_DMP 0x0008 /* Data MMU present */ +#define CPU_OR1K_SPR_UPR_IMP 0x0010 /* Instruction MMU present */ +#define CPU_OR1K_SPR_UPR_MP0x0020 /* MAC present */ +#define CPU_OR1K_SPR_UPR_DUP 0x0040 /* Debug unit present */ +#define CPU_OR1K_SPR_UPR_PCUP 0x0080 /* Performance counters unit present */ +#define CPU_OR1K_SPR_UPR_PMP 0x0100 /* Power management present */ +#define CPU_OR1K_SPR_UPR_PICP 0x0200 /* PIC present */ +#define CPU_OR1K_SPR_UPR_TTP 0x0400 /* Tick timer present */ +#define CPU_OR1K_SPR_UPR_RES 0x00fe /* Reserved */ +#define CPU_OR1K_SPR_UPR_CUP 0xff00 /* Context units present */ + +/* + * Bit definitions for the CPU configuration register + * + */ +#define CPU_OR1K_SPR_CPUCFGR_NSGF 0x000f /* Number of shadow GPR files */ +#define CPU_OR1K_SPR_CPUCFGR_CGF0x0010 /* Custom GPR file */ +#define CPU_OR1K_SPR_CPUCFGR_OB32S 0x0020 /* ORBIS32 supported */ +#define CPU_OR1K_SPR_CPUCFGR_OB64S 0x0040 /* ORBIS64 supported */ +#define CPU_OR1K_SPR_CPUCFGR_OF32S 0x0080 /* ORFPX32 supported */ +#define CPU_OR1K_SPR_CPUCFGR_OF64S 0x0100 /* ORFPX64 supported */ +#define CPU_OR1K_SPR_CPUCFGR_OV64S 0x0200 /* ORVDX64 supported */ +#define CPU_OR1K_SPR_CPUCFGR_RES0xfc00 /* Reserved */ + +/* + * Bit definitions for the Debug configuration register and other + * constants. + * + */ +#define CPU_OR1K_SPR_DCFGR_NDP 0x0007 /* Number of matchpoints mask */ +#define CPU_OR1K_SPR_DCFGR_NDP1 0x /* One matchpoint supported */ +#define CPU_OR1K_SPR_DCFGR_NDP2 0x0001 /* Two matchpoints supported */ +#define CPU_OR1K_SPR_DCFGR_NDP3 0x0002 /* Three matchpoints supported */ +#define CPU_OR1K_SPR_DCFGR_NDP4 0x0003 /* Four matchpoints supported */ +#define CPU_OR1K_SPR_DCFGR_NDP5 0x0004 /* Five matchpoints supported */ +#define CPU_OR1K_SPR_DCFGR_NDP6 0x0005 /* Six matchpoints supported */ +#define CPU_OR1K_SPR_DCFGR_NDP7 0x0006 /* Seven matchpoints supported */ +#define CPU_OR1K_SPR_DCFGR_NDP8 0x0007 /* Eight matchpoints supported */ +#define CPU_OR1K_SPR_DCFGR_WPCI 0x0008 /* Watchpoint counters implemented */ + +/* + * Bit definitions for Data Cache Control register + * + */ +#define CPU_OR1K_SPR_DCCR_EW 0x00ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + * + */ +#define CPU_OR1K_SPR_ICCR_EW 0x00ff /* Enable ways */ + +/* + *
[PATCH 3/8] OR1k exception handling and start code
From: Jakob Viketoft - Correct start vector table. - Add proper init of registers and caches - Add more information on unhandled exceptions - Use defines instead of hardcoded values for readability Close #2598 --- c/src/lib/libbsp/or1k/generic_or1k/start/start.S | 258 ++--- cpukit/score/cpu/or1k/or1k-exception-default.c | 1 + cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 11 +- cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 220 +- 4 files changed, 343 insertions(+), 147 deletions(-) diff --git a/c/src/lib/libbsp/or1k/generic_or1k/start/start.S b/c/src/lib/libbsp/or1k/generic_or1k/start/start.S index 26991c8..7a182df 100644 --- a/c/src/lib/libbsp/or1k/generic_or1k/start/start.S +++ b/c/src/lib/libbsp/or1k/generic_or1k/start/start.S @@ -1,11 +1,16 @@ /* * Copyright (c) 2014-2015 Hesham ALMatary + * Copyright (c) 2014-2016 ÅAC Microtec AB + * Jakob Viketoft * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE */ #include +#include + + .extern _ISR_Handler /* The following macro defines the first instructions every exception * should execute before jumping to its handler function from the @@ -16,34 +21,22 @@ */ #define EXCEPTION_SETUP(vector) \ l.nop ;\ - l.addi r1, r1, -200 ;\ - l.sw0(r1), r3; \ + /* Add space for redzone and make space on the current stack \ + * (from the interrupted thread) */ \ + l.addi r1, r1, -(REDZONE_SIZE + EX_FRAME_SIZE); \ + l.swOR1K_EC_GPR3(r1), r3; \ l.addi r3, r0, vector; \ l.j _ISR_Handler; \ l.nop .extern boot_card - .extern bsp_section_bss_begin - .extern bsp_section_bss_end - - .extern bsp_start_vector_table_end - .extern bsp_start_vector_table_size - .extern bsp_vector_table_size - .extern bsp_section_stack_begin - - .extern exception_frame_save - .extern _OR1K_Exception_Process .extern _OR1K_Exception_default - .extern rtems_clock_tick - .extern _exit - .extern printk - .extern bsp_interrupt_handler_default /* Global symbols */ .global _start .global bsp_start_vector_table_begin -/* Popualte HW vector table */ +/* Populate HW vector table */ .section .vector, "ax" @@ -61,7 +54,7 @@ _dPageFault: EXCEPTION_SETUP(3) .org 0x400 -_iPageFaule: +_iPageFault: EXCEPTION_SETUP(4) .org 0x500 @@ -105,18 +98,74 @@ _trap: EXCEPTION_SETUP(14) .org 0xF00 -_undef1: +_res_future1: EXCEPTION_SETUP(15) -.org 0x1500 -_undef2: +.org 0x1000 +_res_future2: EXCEPTION_SETUP(16) -.org 0x1900 -_undef3: +.org 0x1100 +_res_future3: EXCEPTION_SETUP(17) +.org 0x1200 +_res_future4: + EXCEPTION_SETUP(18) + +.org 0x1300 +_res_future5: + EXCEPTION_SETUP(19) + +.org 0x1400 +_res_future6: + EXCEPTION_SETUP(20) + +.org 0x1500 +_res_impspec1: + EXCEPTION_SETUP(21) + +.org 0x1600 +_res_impspec2: + EXCEPTION_SETUP(22) + +.org 0x1700 +_res_impspec3: + EXCEPTION_SETUP(23) + +.org 0x1800 +_res_impspec4: + EXCEPTION_SETUP(24) + +.org 0x1900 +_res_custom1: + EXCEPTION_SETUP(25) + +.org 0x1A00 +_res_custom2: + EXCEPTION_SETUP(26) + +.org 0x1B00 +_res_custom3: + EXCEPTION_SETUP(27) + +.org 0x1C00 +_res_custom4: + EXCEPTION_SETUP(28) + +.org 0x1D00 +_res_custom5: + EXCEPTION_SETUP(29) + +.org 0x1E00 +_res_custom6: + EXCEPTION_SETUP(30) + .org 0x1F00 +_res_custom7: + EXCEPTION_SETUP(31) + +.org 0x2000 bsp_start_vector_table_begin: @@ -127,7 +176,7 @@ bsp_start_vector_table_begin: .word _OR1K_Exception_default /* Instruction Page Fault */ .word _OR1K_Exception_default /* Tick timer */ .word _OR1K_Exception_default /* Alignment */ - .word _OR1K_Exception_default /* Undefiend Instruction */ + .word _OR1K_Exception_default /* Undefined Instruction */ .word _OR1K_Exception_default /* External Interrupt */ .word _OR1K_Exception_default /* Data TLB Miss */ .word _OR1K_Exception_default /* Instruction TLB Miss */ @@ -135,8 +184,22 @@ bsp_start_vector_table_begin: .word _OR1K_Exception_default /* System Call */ .word _OR1K_Exception_default /* Floating Point Exception */ .word _OR1K_Exception_default /* Trap */ - .word _OR1K_Exception_default /* Reserver for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for future use */ + .word _OR1K_Exception_default /* Reserved for implementation-specific */ .word _OR1K_Exception_default /* Reserved for implementation-specific */ + .word _OR1
[PATCH 2/8] or1k: Fix inconsistencies in _ISR_enable/disable/flash
From: Jakob Viketoft
Close #2597
---
cpukit/score/cpu/or1k/cpu.c | 18 +
cpukit/score/cpu/or1k/rtems/score/cpu.h | 47 -
2 files changed, 29 insertions(+), 36 deletions(-)
diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
index 3cf6f6b..c52c48b 100644
--- a/cpukit/score/cpu/or1k/cpu.c
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -34,26 +34,20 @@ void _CPU_Initialize(void)
* @brief Sets the hardware interrupt level by the level value.
*
* @param[in] level for or1k can only range over two values:
- * 0 (enable interrupts) and 1 (disable interrupts). In future
- * implementations if fast context switch is implemented, the level
- * can range from 0 to 15. @see OpenRISC architecture manual.
- *
+ * 0 (enable interrupts) and 1 (disable interrupts).
*/
void _CPU_ISR_Set_level(uint32_t level)
{
uint32_t sr = 0;
- level = (level > 0)? 1 : 0;
-
- /* map level bit to or1k interrupt enable/disable bit in sr register */
- level <<= CPU_OR1K_SPR_SR_SHAMT_IEE;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
- if (level == 0){ /* Enable all interrupts */
+ if (level > 0) {
+/* Interrupts disable */
+sr &= ~(CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE);
+ } else {
+/* Interrupts enable */
sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
-
- } else{
-sr &= ~CPU_OR1K_SPR_SR_IEE;
}
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h
b/cpukit/score/cpu/or1k/rtems/score/cpu.h
index 7364343..740bdda 100644
--- a/cpukit/score/cpu/or1k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
@@ -6,6 +6,9 @@
* This include file contains macros pertaining to the Opencores
* or1k processor family.
*
+ * COPYRIGHT (c) 2016 ÅAC Microtec AB
+ * Jakob Viketoft
+ * David Hennerström
* COPYRIGHT (c) 2014 Hesham ALMatary
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
@@ -505,25 +508,14 @@ static inline uint32_t or1k_interrupt_disable( void )
uint32_t sr;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
- _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE));
-
- return sr;
-}
-
-static inline void or1k_interrupt_enable(uint32_t level)
-{
- uint32_t sr;
-
- /* Enable interrupts and restore rs */
- sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
- _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~(CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+ return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1;
}
#define _CPU_ISR_Disable( _level ) \
_level = or1k_interrupt_disable()
-
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
@@ -531,6 +523,20 @@ static inline void or1k_interrupt_enable(uint32_t level)
*
*/
+static inline void or1k_interrupt_enable(uint32_t level)
+{
+ uint32_t sr;
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ if (level > 0) {
+/* Effectively disable interrupts */
+_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~(CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+return;
+ }
+
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr | (CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+}
+
#define _CPU_ISR_Enable( _level ) \
or1k_interrupt_enable( _level )
@@ -545,7 +551,7 @@ static inline void or1k_interrupt_enable(uint32_t level)
#define _CPU_ISR_Flash( _level ) \
do{ \
_CPU_ISR_Enable( _level ); \
- _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \
+ or1k_interrupt_disable(); \
} while(0)
/*
@@ -795,16 +801,9 @@ typedef uint16_t Priority_bit_map_Word;
typedef struct {
uint32_t r[32];
- /* The following registers must be saved if we have
- fast context switch disabled and nested interrupt
- levels are enabled.
- */
-#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED
- uint32_t epcr; /* exception PC register */
- uint32_t eear; /* exception effective address register */
- uint32_t esr; /* exception supervision register */
-#endif
-
+ uint32_t epcr; /* Exception PC register */
+ uint32_t eear; /* Exception effective address register */
+ uint32_t esr; /* Exception supervision register */
} CPU_Exception_frame;
/**
--
2.1.4
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[PATCH 4/8] Improve OR1k context handling
From: Jakob Viketoft
Close #2599
---
cpukit/score/cpu/or1k/or1k-context-initialize.c | 13 ++-
cpukit/score/cpu/or1k/or1k-context-switch.S | 113
2 files changed, 69 insertions(+), 57 deletions(-)
diff --git a/cpukit/score/cpu/or1k/or1k-context-initialize.c
b/cpukit/score/cpu/or1k/or1k-context-initialize.c
index a7205e3..d37458e 100644
--- a/cpukit/score/cpu/or1k/or1k-context-initialize.c
+++ b/cpukit/score/cpu/or1k/or1k-context-initialize.c
@@ -29,13 +29,22 @@ void _CPU_Context_Initialize(
void *tls_area
)
{
- /* Decrement 200 byte to account for red-zone */
- uint32_t stack = ((uint32_t) stack_area_begin) - 200;
+ /* Decrement to account for redzone */
+ uint32_t stack = ((uint32_t) stack_area_begin) - REDZONE_SIZE;
uint32_t sr;
uint32_t stack_high = stack + stack_area_size;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+ /* Make sure we will adhere to the requested level */
+ if (new_level > 0) {
+/* Interrupts disable in our local sr */
+sr &= ~(CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE);
+ } else {
+/* Interrupts enable in our local sr */
+sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
+ }
+
memset(context, 0, sizeof(*context));
context->r1 = stack_high;
diff --git a/cpukit/score/cpu/or1k/or1k-context-switch.S
b/cpukit/score/cpu/or1k/or1k-context-switch.S
index 91521e4..2a98cac 100644
--- a/cpukit/score/cpu/or1k/or1k-context-switch.S
+++ b/cpukit/score/cpu/or1k/or1k-context-switch.S
@@ -22,93 +22,96 @@ PUBLIC(_CPU_Context_restore_fp)
PUBLIC(_CPU_Context_save_fp)
SYM(_CPU_Context_switch):
- l.sw 0(r3),r1
- l.sw 4(r3),r2
- l.sw 8(r3),r3
- l.sw 12(r3),r4
- l.sw 16(r3),r5
- l.sw 20(r3),r6
- l.sw 24(r3),r7
- l.sw 28(r3),r8
- l.sw 32(r3),r9
- /* Skip r10 as it's preserved to be used by TLS */
- /* The following set if registers are preserved across function calls */
- l.sw 52(r3),r14
- l.sw 60(r3),r16
- l.sw 68(r3),r18
- l.sw 76(r3),r20
- l.sw 84(r3),r22
- l.sw 92(r3),r24
- l.sw 100(r3),r26
- l.sw 108(r3),r28
- l.sw 116(r3),r30
+ l.swOR1K_CC_GPR1(r3), r1
+ l.swOR1K_CC_GPR2(r3), r2
+ l.swOR1K_CC_GPR3(r3), r3
+ l.swOR1K_CC_GPR4(r3), r4
+ l.swOR1K_CC_GPR5(r3), r5
+ l.swOR1K_CC_GPR6(r3), r6
+ l.swOR1K_CC_GPR7(r3), r7
+ l.swOR1K_CC_GPR8(r3), r8
+ l.swOR1K_CC_GPR9(r3), r9
+ /* The following set of registers are preserved across function calls
+ * (callee-saved) */
+ l.swOR1K_CC_GPR10(r3), r10
+ l.swOR1K_CC_GPR12(r3), r12
+ l.swOR1K_CC_GPR14(r3), r14
+ l.swOR1K_CC_GPR16(r3), r16
+ l.swOR1K_CC_GPR18(r3), r18
+ l.swOR1K_CC_GPR20(r3), r20
+ l.swOR1K_CC_GPR22(r3), r22
+ l.swOR1K_CC_GPR24(r3), r24
+ l.swOR1K_CC_GPR26(r3), r26
+ l.swOR1K_CC_GPR28(r3), r28
+ l.swOR1K_CC_GPR30(r3), r30
/* Supervision Register */
- l.mfspr r13,r0, CPU_OR1K_SPR_SR
- l.sw 124(r3),r13
+ l.mfspr r13, r0, CPU_OR1K_SPR_SR
+ l.swOR1K_CC_SR(r3), r13
/* EPCR */
l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
- l.sw 128(r3), r13 /* epcr */
+ l.swOR1K_CC_EPCR0(r3), r13
/* EEAR */
l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
- l.sw 132(r3), r13 /* eear */
+ l.swOR1K_CC_EEAR0(r3), r13
/* ESR */
l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
- l.sw 136(r3), r13 /* esr */
+ l.swOR1K_CC_ESR0(r3), r13
SYM(restore):
- l.lwz r13,124(r4)
- l.mtspr r0,r13, CPU_OR1K_SPR_SR
-
- /* Exception level related registers */
+ l.lwz r13, OR1K_CC_SR(r4)
+ l.mtspr r0, r13, CPU_OR1K_SPR_SR
/* EPCR */
- l.lwz r13, 128(r4)
+ l.lwz r13, OR1K_CC_EPCR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
/* EEAR */
- l.lwz r13, 132(r4)
+ l.lwz r13, OR1K_CC_EEAR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
/* ESR */
- l.lwz r13, 136(r4)
+ l.lwz r13, OR1K_CC_ESR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
- l.lwz r1,0(r4)
- l.lwz r2,4(r4)
- l.lwz r3,8(r4)
+ l.lwz r1, OR1K_CC_GPR1(r4)
+ l.lwz r2, OR1K_CC_GPR2(r4)
+ l.lwz r3, OR1K_CC_GPR3(r4)
/* Skip r4 as it contains the current buffer address */
- l.lwz r5,16(r4)
- l.lwz r6,20(r4)
- l.lwz r7,24(r4)
- l.lwz r8,28(r4)
- l.lwz r9,32(r4)
- l.lwz r14,52(r4)
- l.lwz r16,60(r4)
- l.lwz r18,68(r4)
- l.lwz r20,76(r4)
- l.lwz r22,84(r4)
- l.lwz r24,92(r4)
- l.lwz r26,100(r4)
- l.lwz r28,108(r4)
- l.lwz r30,116(r4)
-
- l.lwz r4,12(r4)
-
- l.jr r9
+ l.lwz r5, OR1K_CC_GPR5(r4)
+ l.lwz r6, OR1K_CC_GPR6(r4)
+ l.lwz r7, OR1K_CC_GPR7(r4)
+ l.lwz r8, OR1K_CC_GPR8(r4)
+ l.lwz r9, OR1K_CC_GPR9(r4)
+ l.lwz r10, OR1K_CC_GPR10(r4)
+ l.lwz r12, OR1K_CC_GPR12(r4)
+ l.lwz r14, OR1K_CC_GPR14(r4)
+ l.lwz r16, OR1K_CC_GPR16(r4)
+ l.lwz r18, OR1K_CC_GPR18(r4)
+ l.lwz r20, OR1K_CC_GPR20(r4)
+ l.lwz r22, OR1K_CC_GPR22(r4)
+ l.lwz r24, OR1K_CC_GPR24(r4)
+ l.lwz r26, OR1K_CC_GPR26(r4)
+ l.lwz r28, OR1K_CC_GPR28(r4)
+ l.lwz r30, OR1K_CC_GPR30(r4)
+
+ l.lwz r4, OR1K_CC_GPR4(r4)
+
+ l.
[PATCH 5/8] generic_or1k BSP clock driver correction
From: Jakob Viketoft
- Improve the clock driver to use RTEMS default tick period
or the on the one supplied by the application
- Avoid rewriting the timer settings, since all we need is to clear the
interrupt
- Remove any mention of or1ksim in favour of generic_or1k
Close #2600
---
.../lib/libbsp/or1k/generic_or1k/clock/clockdrv.c | 109 ++---
1 file changed, 51 insertions(+), 58 deletions(-)
diff --git a/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c
b/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c
index e01d2e5..60eec98 100644
--- a/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c
+++ b/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c
@@ -3,13 +3,15 @@
*
* @ingroup bsp_clock
*
- * @brief or1k clock support.
+ * @brief generic_or1k clock support.
*/
/*
* generic_or1k Clock driver
*
* COPYRIGHT (c) 2014-2015 Hesham ALMatary
+ * Copyright (c) 2014-2016 ÅAC Microtec AB
+ * Jakob Viketoft
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -25,35 +27,30 @@
#include
/* The number of clock cycles before generating a tick timer interrupt. */
-#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 0x09ED9
-#define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS 10
+#define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS (10 /
OR1K_BSP_CLOCK_FREQ)
-static struct timecounter or1ksim_tc;
-
-/* CPU counter */
+static struct timecounter generic_or1k_tc;
static CPU_Counter_ticks cpu_counter_ticks;
+static uint32_t timer_counts_per_clock_tick;
-/* This prototype is added here to Avoid warnings */
+/* These prototypes are added here to avoid warnings */
void Clock_isr(void *arg);
+static uint32_t generic_or1k_get_timecount(struct timecounter *tc);
static void generic_or1k_clock_at_tick(void)
{
- uint32_t TTMR;
+ uint32_t ttmr;
- /* For TTMR register,
- * The least significant 28 bits are the number of clock cycles
- * before generating a tick timer interrupt. While the most
- * significant 4 bits are used for mode configuration, tick timer
- * interrupt enable and pending interrupts status.
- */
- TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
- (TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK)
- ) & ~(CPU_OR1K_SPR_TTMR_IP);
+ /* Get TTMR value */
+ ttmr = _OR1K_mfspr(CPU_OR1K_SPR_TTMR);
- _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
- _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
+ /* Clear interrupt */
+ ttmr &= ~(CPU_OR1K_SPR_TTMR_IP);
- cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT;
+ /* Write it back */
+ _OR1K_mtspr(CPU_OR1K_SPR_TTMR, ttmr);
+
+ cpu_counter_ticks += timer_counts_per_clock_tick;
}
static void generic_or1k_clock_handler_install(
@@ -61,35 +58,19 @@ static void generic_or1k_clock_handler_install(
proc_ptr old_isr
)
{
- rtems_status_code sc = RTEMS_SUCCESSFUL;
old_isr = NULL;
_CPU_ISR_install_vector(OR1K_EXCEPTION_TICK_TIMER,
new_isr,
old_isr);
-
- if (sc != RTEMS_SUCCESSFUL) {
-rtems_fatal_error_occurred(0xdeadbeef);
- }
-}
-
-static uint32_t or1ksim_get_timecount(struct timecounter *tc)
-{
- uint32_t ticks_since_last_timer_interrupt;
-
- ticks_since_last_timer_interrupt = _OR1K_mfspr(CPU_OR1K_SPR_TTCR);
-
- return cpu_counter_ticks + ticks_since_last_timer_interrupt;
-}
-
-CPU_Counter_ticks _CPU_Counter_read(void)
-{
- return or1ksim_get_timecount(NULL);
}
static void generic_or1k_clock_initialize(void)
{
- uint64_t frequency = (10 / OR1K_CLOCK_CYCLE_TIME_NANOSECONDS);
- uint32_t TTMR;
+ uint32_t ttmr;
+
+ /* Calculate timer value for given time per clock tick */
+ timer_counts_per_clock_tick = (1000 *
rtems_configuration_get_microseconds_per_tick()) /
+OR1K_CLOCK_CYCLE_TIME_NANOSECONDS;
/* For TTMR register,
* The least significant 28 bits are the number of clock cycles
@@ -97,40 +78,52 @@ static void generic_or1k_clock_initialize(void)
* significant 4 bits are used for mode configuration, tick timer
* interrupt enable and pending interrupts status.
*/
+ ttmr = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
+ (timer_counts_per_clock_tick & CPU_OR1K_SPR_TTMR_TP_MASK)) &
+~(CPU_OR1K_SPR_TTMR_IP);
- /* FIXME: Long interval should pass since initializing the tick timer
- * registers fires exceptions dispite interrupts has not been enabled yet.
- */
- TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
- (0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK)
- ) & ~(CPU_OR1K_SPR_TTMR_IP);
-
- _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
+ _OR1K_mtspr(CPU_OR1K_SPR_TTMR, ttmr);
_OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
+ /* Initialize CPU Counter */
+ cpu_counter_ticks = 0;
+
/* Initialize timecounter */
- or1ksim_tc.tc_get_timecount = or1ksim_get_timecount;
- or1ksim_tc.tc_counter_mask = 0x;
- or1ksim_tc.tc_frequency
[PATCH 6/8] OR1k shared and generic_or1k BSP link script rewrite
From: Jakob Viketoft
- Rewrote the link scripts to make more sense and to correct
the weird stack calculations previously made
Close #2601
---
.../lib/libbsp/or1k/generic_or1k/startup/linkcmds | 12 +-
.../libbsp/or1k/shared/include/linker-symbols.h| 8 +-
c/src/lib/libbsp/or1k/shared/startup/linkcmds.base | 370 -
3 files changed, 151 insertions(+), 239 deletions(-)
diff --git a/c/src/lib/libbsp/or1k/generic_or1k/startup/linkcmds
b/c/src/lib/libbsp/or1k/generic_or1k/startup/linkcmds
index cef99d3..3a34186 100644
--- a/c/src/lib/libbsp/or1k/generic_or1k/startup/linkcmds
+++ b/c/src/lib/libbsp/or1k/generic_or1k/startup/linkcmds
@@ -8,16 +8,22 @@
/*
* COPYRIGHT (c) 2014 Hesham ALMatary
+ * Copyright (c) 2015 ÅAC Microtec AB
+ *Jakob Viketoft
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE
*/
+/* Set up system characteristics */
+HeapSize = 0;
+StackSize = 16K;
+
MEMORY
{
- VECTOR_RAM (AIW) : ORIGIN = 0x0 , LENGTH = 8260
- RAM : org = 0x2048, l = 0x1FFDFB8
+ VECTOR_RAM (AIW): ORIGIN = 0x, LENGTH = 8K + 128
+ RAM : ORIGIN = 0x2080, LENGTH = 32M - 8K - 128
UNEXPECTED_SECTIONS : ORIGIN = 0x, LENGTH = 0
}
@@ -35,7 +41,5 @@ REGION_ALIAS ("REGION_BSS", RAM);
REGION_ALIAS ("REGION_WORK", RAM);
REGION_ALIAS ("REGION_STACK", RAM);
-bsp_section_vector_begin = 0;
-bsp_section_stack_begin = 0x1FFDFB8;
INCLUDE linkcmds.base
diff --git a/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h
b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h
index f0f8377..bae619a 100644
--- a/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h
+++ b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h
@@ -1,5 +1,5 @@
-#ifndef LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H
-#define LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H
+#ifndef LIBBSP_OR1K_SHARED_LINKER_SYMBOLS_H
+#define LIBBSP_OR1K_SHARED_LINKER_SYMBOLS_H
#ifdef __cplusplus
extern "C" {
@@ -59,10 +59,6 @@ LINKER_SYMBOL(bsp_section_stack_begin)
LINKER_SYMBOL(bsp_section_stack_end)
LINKER_SYMBOL(bsp_section_stack_size)
-LINKER_SYMBOL(bsp_vector_table_begin)
-LINKER_SYMBOL(bsp_vector_table_end)
-LINKER_SYMBOL(bsp_vector_table_size)
-
LINKER_SYMBOL(bsp_start_vector_table_begin)
LINKER_SYMBOL(bsp_start_vector_table_end)
LINKER_SYMBOL(bsp_start_vector_table_size)
diff --git a/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base
b/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base
index 31bb92d..1d40668 100644
--- a/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base
+++ b/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base
@@ -8,6 +8,8 @@
/*
* COPYRIGHT (c) 2014 Hesham ALMatary
+ * COPYRIGHT (c) 2015 ÅAC Microtec
+ *Jakob Viketoft
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -19,35 +21,49 @@ OUTPUT_ARCH (or1k)
ENTRY (_start)
/*
- * Global symbols that may be defined externally
+ * The memory map looks like this:
+ * ++ <- low memory
+ * | .vector| exception vectors and exception
+ * || handler's table
+ * ++
+ * | .start | entry point (setup) code
+ * ++
+ * | .text |
+ * |init|
+ * |fini|
+ * |ctor list | the ctor and dtor lists are for
+ * |dtor list | C++ support
+ * |eh_frame|
+ * |etext |
+ * ++
+ * | .tdata | TLS data
+ * ++
+ * | .tbss | TLS bss
+ * ++
+ * | .data | initialized data goes here
+ * ++
+ * | .bss | section cleared by entry code
+ * ++
+ * | .stack |
+ * ++ <- high memory (top of stack)
*/
-bsp_start_vector_table_begin = 0x1F00;
-bsp_vector_table_size = DEFINED (bsp_vector_table_size) ? bsp_vector_table_size
-: 8260;
-/* 8192 for raw vector table, and 17 * 4 for handlers vector. */
+/* Make sure we have predefined some crucial variables */
+StackSize = DEFINED (StackSize) ? StackSize : 16K;
+HeapSize = DEFINED (HeapSize) ? HeapSize : 0;
-bsp_section_xbarrier_align = DEFINED (bsp_section_xbarrier_align) ?
bsp_section_xbarrier_align : 1;
-bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ?
bsp_section_robarrier_align : 1;
-bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ?
bsp_section_rwbarrier_align : 1;
-
-bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 8;
-
-bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0;
-bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
-
-bsp_processor_count = DEFINED (bsp_processor
[PATCH 8/8] Added an interrupt handler to generic_or1k BSP
From: Jakob Viketoft
Update #2603
---
c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c | 61
1 file changed, 54 insertions(+), 7 deletions(-)
diff --git a/c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c
b/c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c
index c3c4d6d..ef69f54 100644
--- a/c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c
+++ b/c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c
@@ -8,6 +8,8 @@
/*
* Copyright (c) 2014 Hesham ALMatary
+ * Copyright (c) 2015 ÅAC Microtec AB
+ *Jakob Viketoft
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -16,27 +18,72 @@
#include
#include
+#include
-/* Almost all of the jobs that the following functions should
- * do are implemented in cpukit
- */
+static int or1k_external_interrupt_handler(rtems_vector_number vector)
+{
+ uint32_t picsr;
+ uint32_t int_num;
+
+ /* Get picsr */
+ picsr = _OR1K_mfspr(CPU_OR1K_SPR_PICSR);
+
+ /* Make sure we have a pending interrupt */
+ assert(picsr != 0);
+
+ /* Go through all set interrupts in a round-robin style */
+ while (picsr) {
+/* Find pending interrupt with lowest number */
+int_num = _OR1K_Find_first_one(picsr);
+
+/* Adjust vector number with a start from 0 */
+int_num--;
+
+/* Call the interrupt handler */
+bsp_interrupt_handler_dispatch((rtems_vector_number) int_num);
+
+/* Clear the interrupt */
+picsr &= ~(1 << int_num);
+_OR1K_mtspr(CPU_OR1K_SPR_PICSR, picsr);
+ }
+
+ return 0;
+}
void bsp_interrupt_handler_default(rtems_vector_number vector)
{
-printk("spurious interrupt: %u\n", vector);
+ printk("Unhandled interrupt, number: %u\n", vector);
}
rtems_status_code bsp_interrupt_facility_initialize()
{
- return 0;
+ /* Install exception handler for external interrupt exception */
+ _CPU_ISR_install_vector(OR1K_EXCEPTION_IRQ, or1k_external_interrupt_handler,
NULL);
+
+ /* Clear all pending interrupts */
+ _OR1K_mtspr(CPU_OR1K_SPR_PICSR, 0);
+
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
{
- return 0;
+ uint32_t picmr;
+
+ picmr = _OR1K_mfspr(CPU_OR1K_SPR_PICMR);
+ picmr |= (1 << vector);
+ _OR1K_mtspr(CPU_OR1K_SPR_PICMR, picmr);
+
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
- return 0;
+ uint32_t picmr;
+
+ picmr = _OR1K_mfspr(CPU_OR1K_SPR_PICMR);
+ picmr &= ~(1 << vector);
+ _OR1K_mtspr(CPU_OR1K_SPR_PICMR, picmr);
+
+ return RTEMS_SUCCESSFUL;
}
--
2.1.4
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[PATCH 7/8] OR1k cache flush/invalidate additions
From: Jakob Viketoft
Close #2602
---
c/src/lib/libcpu/or1k/shared/cache/cache.c | 129 +
1 file changed, 94 insertions(+), 35 deletions(-)
diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c
b/c/src/lib/libcpu/or1k/shared/cache/cache.c
index d17fec2..02e4aab 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
@@ -4,9 +4,14 @@
* COPYRIGHT (c) 1989-2006
* On-Line Applications Research Corporation (OAR).
*
+ * Copyright (c) 2014 ÅAC Microtec AB
+ * Contributor(s):
+ * Karol Gugala
+ *
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
+ *
*/
#include
@@ -14,13 +19,15 @@
#include
#include
#include
+#include
static inline void _CPU_OR1K_Cache_enable_data(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
+
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
@@ -30,7 +37,7 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
static inline void _CPU_OR1K_Cache_disable_data(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
@@ -43,7 +50,7 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
static inline void _CPU_OR1K_Cache_enable_instruction(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
@@ -66,95 +73,109 @@ static inline void
_CPU_OR1K_Cache_disable_instruction(void)
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_prefetch
+(const uintptr_t d_addr)
{
ISR_Level level;
_ISR_Disable (level);
- _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr);
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_flush
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr);
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_invalidate
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr);
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_writeback
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr);
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_lock
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr);
_ISR_Enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_prefetch
-(const void *d_addr)
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
+ _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr);
_ISR_Enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_invalidate
-(const void *d_addr)
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
+ _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr);
_ISR_Enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_lock
-(const void *d_addr)
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
+ _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr);
_ISR_Enable(level);
}
/* Implement RTEMS cache manager functions */
-void _CPU_cache_flush_1_data_line(const void *d_addr)
+void _CPU_cache_flush_1_data_line
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_CPU_OR1K_Cache_data_block_flush(d_addr);
@@ -164,9 +185,11 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
_ISR_Enable(level);
}
-void _CPU_cache_invalidate_1_data_line(const void *d_addr)
+void _CPU_cache_invalidate_1_data_line
+(const uintptr_t d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_CPU_OR1K_Cache_data_block_invalidate(d_addr);
@@ -184,9 +207,11 @@ void
RE: [PATCH 8/8] Added an interrupt handler to generic_or1k BSP
I hadn't really intended this to be part of the series, but rather a
stand-alone addition, but apparently I stod on the wrong commit when generating
the series and didn't notice before sending out the first e-mail. Oh well, it's
late on a Saturday... ;)
/Jakob
Jakob Viketoft
Senior Engineer in RTL and embedded software
ÅAC Microtec AB
Dag Hammarskjölds väg 48
SE-751 83 Uppsala, Sweden
T: +46 702 80 95 97
http://www.aacmicrotec.com
From: jakob.viket...@gmail.com [jakob.viket...@gmail.com]
Sent: Sunday, February 21, 2016 00:02
To: devel@rtems.org
Cc: Jakob Viketoft
Subject: [PATCH 8/8] Added an interrupt handler to generic_or1k BSP
From: Jakob Viketoft
Update #2603
---
c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c | 61
1 file changed, 54 insertions(+), 7 deletions(-)
diff --git a/c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c
b/c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c
index c3c4d6d..ef69f54 100644
--- a/c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c
+++ b/c/src/lib/libbsp/or1k/generic_or1k/irq/irq.c
@@ -8,6 +8,8 @@
/*
* Copyright (c) 2014 Hesham ALMatary
+ * Copyright (c) 2015 ÅAC Microtec AB
+ *Jakob Viketoft
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -16,27 +18,72 @@
#include
#include
+#include
-/* Almost all of the jobs that the following functions should
- * do are implemented in cpukit
- */
+static int or1k_external_interrupt_handler(rtems_vector_number vector)
+{
+ uint32_t picsr;
+ uint32_t int_num;
+
+ /* Get picsr */
+ picsr = _OR1K_mfspr(CPU_OR1K_SPR_PICSR);
+
+ /* Make sure we have a pending interrupt */
+ assert(picsr != 0);
+
+ /* Go through all set interrupts in a round-robin style */
+ while (picsr) {
+/* Find pending interrupt with lowest number */
+int_num = _OR1K_Find_first_one(picsr);
+
+/* Adjust vector number with a start from 0 */
+int_num--;
+
+/* Call the interrupt handler */
+bsp_interrupt_handler_dispatch((rtems_vector_number) int_num);
+
+/* Clear the interrupt */
+picsr &= ~(1 << int_num);
+_OR1K_mtspr(CPU_OR1K_SPR_PICSR, picsr);
+ }
+
+ return 0;
+}
void bsp_interrupt_handler_default(rtems_vector_number vector)
{
-printk("spurious interrupt: %u\n", vector);
+ printk("Unhandled interrupt, number: %u\n", vector);
}
rtems_status_code bsp_interrupt_facility_initialize()
{
- return 0;
+ /* Install exception handler for external interrupt exception */
+ _CPU_ISR_install_vector(OR1K_EXCEPTION_IRQ, or1k_external_interrupt_handler,
NULL);
+
+ /* Clear all pending interrupts */
+ _OR1K_mtspr(CPU_OR1K_SPR_PICSR, 0);
+
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
{
- return 0;
+ uint32_t picmr;
+
+ picmr = _OR1K_mfspr(CPU_OR1K_SPR_PICMR);
+ picmr |= (1 << vector);
+ _OR1K_mtspr(CPU_OR1K_SPR_PICMR, picmr);
+
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
- return 0;
+ uint32_t picmr;
+
+ picmr = _OR1K_mfspr(CPU_OR1K_SPR_PICMR);
+ picmr &= ~(1 << vector);
+ _OR1K_mtspr(CPU_OR1K_SPR_PICMR, picmr);
+
+ return RTEMS_SUCCESSFUL;
}
--
2.1.4
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compilation error
hello everyone please can someone help me with this error on compilation on this link http://pastebin.com/S0ACw08M ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: compilation error
Look at the detailed log for more information but you are likely missing the Python development package for your host OS. There are instructions for using apt,yum, etc to install them in the RSB manual. If that doesn't help you find it, post your host OS for help. hello everyone please can someone help me with this error on compilation on this link http://pastebin.com/S0ACw08M ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Regarding GSOC 2016 BSP for BBB
On Fri, Feb 19, 2016 at 11:47 PM, Martin Galvan wrote: > CAN, USB and I2C still need to be developed. We're currently using the AM335x > StarterWare code and it works fine; you may want to base your work on it. > Keep an eye open for licensing issues, though. Thank you Martin. I started looking previous year work of BBB as well as Rpi work for I2c and SPI . May I know whether are you going to mentor for beagle bone black bsp this year ? ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
