From: Jakob Viketoft <jakob.viket...@aacmicrotec.com>
Close #2597
---
cpukit/score/cpu/or1k/cpu.c | 18 +++++--------
cpukit/score/cpu/or1k/rtems/score/cpu.h | 47 ++++++++++++++++-----------------
2 files changed, 29 insertions(+), 36 deletions(-)
diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
index 3cf6f6b..c52c48b 100644
--- a/cpukit/score/cpu/or1k/cpu.c
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -34,26 +34,20 @@ void _CPU_Initialize(void)
* @brief Sets the hardware interrupt level by the level value.
*
* @param[in] level for or1k can only range over two values:
- * 0 (enable interrupts) and 1 (disable interrupts). In future
- * implementations if fast context switch is implemented, the level
- * can range from 0 to 15. @see OpenRISC architecture manual.
- *
+ * 0 (enable interrupts) and 1 (disable interrupts).
*/
void _CPU_ISR_Set_level(uint32_t level)
{
uint32_t sr = 0;
- level = (level > 0)? 1 : 0;
-
- /* map level bit to or1k interrupt enable/disable bit in sr register */
- level <<= CPU_OR1K_SPR_SR_SHAMT_IEE;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
- if (level == 0){ /* Enable all interrupts */
+ if (level > 0) {
+ /* Interrupts disable */
+ sr &= ~(CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE);
+ } else {
+ /* Interrupts enable */
sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
-
- } else{
- sr &= ~CPU_OR1K_SPR_SR_IEE;
}
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h
b/cpukit/score/cpu/or1k/rtems/score/cpu.h
index 7364343..740bdda 100644
--- a/cpukit/score/cpu/or1k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
@@ -6,6 +6,9 @@
* This include file contains macros pertaining to the Opencores
* or1k processor family.
*
+ * COPYRIGHT (c) 2016 ÅAC Microtec AB <www.aacmicrotec.com>
+ * Jakob Viketoft <jakob.viket...@aacmicrotec.com>
+ * David Hennerström <david.hennerst...@aacmicrotec.com>
* COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmat...@gmail.com>
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
@@ -505,25 +508,14 @@ static inline uint32_t or1k_interrupt_disable( void )
uint32_t sr;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
- _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE));
-
- return sr;
-}
-
-static inline void or1k_interrupt_enable(uint32_t level)
-{
- uint32_t sr;
-
- /* Enable interrupts and restore rs */
- sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
- _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~(CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+ return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1;
}
#define _CPU_ISR_Disable( _level ) \
_level = or1k_interrupt_disable()
-
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
@@ -531,6 +523,20 @@ static inline void or1k_interrupt_enable(uint32_t level)
*
*/
+static inline void or1k_interrupt_enable(uint32_t level)
+{
+ uint32_t sr;
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ if (level > 0) {
+ /* Effectively disable interrupts */
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~(CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+ return;
+ }
+
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr | (CPU_OR1K_SPR_SR_TEE |
CPU_OR1K_SPR_SR_IEE)));
+}
+
#define _CPU_ISR_Enable( _level ) \
or1k_interrupt_enable( _level )
@@ -545,7 +551,7 @@ static inline void or1k_interrupt_enable(uint32_t level)
#define _CPU_ISR_Flash( _level ) \
do{ \
_CPU_ISR_Enable( _level ); \
- _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \
+ or1k_interrupt_disable(); \
} while(0)
/*
@@ -795,16 +801,9 @@ typedef uint16_t Priority_bit_map_Word;
typedef struct {
uint32_t r[32];
- /* The following registers must be saved if we have
- fast context switch disabled and nested interrupt
- levels are enabled.
- */
-#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED
- uint32_t epcr; /* exception PC register */
- uint32_t eear; /* exception effective address register */
- uint32_t esr; /* exception supervision register */
-#endif
-
+ uint32_t epcr; /* Exception PC register */
+ uint32_t eear; /* Exception effective address register */
+ uint32_t esr; /* Exception supervision register */
} CPU_Exception_frame;
/**
--
2.1.4
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