[PATCH] score: Rework global construction
Ensure that the global construction is performed in the context of the
first initialization thread. On SMP this was not guaranteed in the
previous implementation.
---
cpukit/posix/src/pthreadinitthreads.c | 17 +++-
cpukit/rtems/src/taskinitusers.c | 13 ++-
cpukit/score/Makefile.am | 1 +
cpukit/score/include/rtems/score/threadimpl.h | 10 +++
cpukit/score/src/threadglobalconstruction.c| 94 ++
cpukit/score/src/threadhandler.c | 84 +--
testsuites/psxtests/Makefile.am| 4 +
testsuites/psxtests/configure.ac | 9 ++-
testsuites/psxtests/psxglobalcon01/Makefile.am | 19 +
testsuites/psxtests/psxglobalcon01/init.cc | 58 +
.../psxtests/psxglobalcon01/psxglobalcon01.doc | 12 +++
.../psxtests/psxglobalcon01/psxglobalcon01.scn | 2 +
testsuites/psxtests/psxglobalcon02/Makefile.am | 19 +
testsuites/psxtests/psxglobalcon02/init.cc | 73 +
.../psxtests/psxglobalcon02/psxglobalcon02.doc | 12 +++
.../psxtests/psxglobalcon02/psxglobalcon02.scn | 2 +
16 files changed, 343 insertions(+), 86 deletions(-)
create mode 100644 cpukit/score/src/threadglobalconstruction.c
create mode 100644 testsuites/psxtests/psxglobalcon01/Makefile.am
create mode 100644 testsuites/psxtests/psxglobalcon01/init.cc
create mode 100644 testsuites/psxtests/psxglobalcon01/psxglobalcon01.doc
create mode 100644 testsuites/psxtests/psxglobalcon01/psxglobalcon01.scn
create mode 100644 testsuites/psxtests/psxglobalcon02/Makefile.am
create mode 100644 testsuites/psxtests/psxglobalcon02/init.cc
create mode 100644 testsuites/psxtests/psxglobalcon02/psxglobalcon02.doc
create mode 100644 testsuites/psxtests/psxglobalcon02/psxglobalcon02.scn
diff --git a/cpukit/posix/src/pthreadinitthreads.c
b/cpukit/posix/src/pthreadinitthreads.c
index ad8906b..bc97aaf 100644
--- a/cpukit/posix/src/pthreadinitthreads.c
+++ b/cpukit/posix/src/pthreadinitthreads.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
void _POSIX_Threads_Initialize_user_threads_body(void)
{
@@ -43,13 +44,18 @@ void _POSIX_Threads_Initialize_user_threads_body(void)
posix_initialization_threads_table *user_threads;
pthread_t thread_id;
pthread_attr_t attr;
+ boolregister_global_construction;
+ void *(*thread_entry)(void *);
user_threads = Configuration_POSIX_API.User_initialization_threads_table;
maximum = Configuration_POSIX_API.number_of_initialization_threads;
- if ( !user_threads || maximum == 0 )
+ if ( !user_threads )
return;
+ register_global_construction =
+Configuration_RTEMS_API.number_of_initialization_tasks == 0;
+
/*
* Be careful .. if the default attribute set changes, this may need to.
*
@@ -68,10 +74,17 @@ void _POSIX_Threads_Initialize_user_threads_body(void)
eno = pthread_attr_setstacksize(&attr, user_threads[ index ].stack_size);
_Assert( eno == 0 );
+if ( register_global_construction ) {
+ register_global_construction = false;
+ thread_entry = (void *(*)(void *)) _Thread_Global_construction;
+} else {
+ thread_entry = user_threads[ index ].thread_entry;
+}
+
eno = pthread_create(
&thread_id,
&attr,
- user_threads[ index ].thread_entry,
+ thread_entry,
NULL
);
if ( eno )
diff --git a/cpukit/rtems/src/taskinitusers.c b/cpukit/rtems/src/taskinitusers.c
index 51fb474..c7bc4b3 100644
--- a/cpukit/rtems/src/taskinitusers.c
+++ b/cpukit/rtems/src/taskinitusers.c
@@ -48,6 +48,8 @@ void _RTEMS_tasks_Initialize_user_tasks_body( void )
rtems_id id;
rtems_status_code return_value;
rtems_initialization_tasks_table *user_tasks;
+ bool register_global_construction;
+ rtems_task_entry entry_point;
/*
* Move information into local variables
@@ -61,6 +63,8 @@ void _RTEMS_tasks_Initialize_user_tasks_body( void )
if ( !user_tasks )
return;
+ register_global_construction = true;
+
/*
* Now iterate over the initialization tasks and create/start them.
*/
@@ -76,9 +80,16 @@ void _RTEMS_tasks_Initialize_user_tasks_body( void )
if ( !rtems_is_status_successful( return_value ) )
_Terminate( INTERNAL_ERROR_RTEMS_API, true, return_value );
+if ( register_global_construction ) {
+ register_global_construction = false;
+ entry_point = (rtems_task_entry) _Thread_Global_construction;
+} else {
+ entry_point = user_tasks[ index ].entry_point;
+}
+
return_value = rtems_task_start(
id,
- user_tasks[ index ].entry_point,
+ entry_point,
user_tasks[ index ].argument
);
if ( !rtems_is_status_successful(
Prototype for Init in confdefs.h
Hello,
what was the reason for this change?
commit d8b74dbebd341073f0c5b03e589d3fcd349745d1
Author: Chris Johns
Date: Tue Apr 28 06:39:24 2009 +
2009-04-28 Chris Johns
* sapi/include/confdefs.h: Add a prototype for Init with C linkage
and define Init task command line arguments if confdefs.h provides
an Init entry point.
diff --git a/cpukit/ChangeLog b/cpukit/ChangeLog
index 9432abc..477ce23 100644
--- a/cpukit/ChangeLog
+++ b/cpukit/ChangeLog
@@ -1,3 +1,9 @@
+2009-04-28 Chris Johns
+
+ * sapi/include/confdefs.h: Add a prototype for Init with C linkage
+ and define Init task command line arguments if confdefs.h provides
+ an Init entry point.
+
2009-04-15 Ralf Corsepius
* configure.ac: Disable LIBSHELL for unix targets.
diff --git a/cpukit/sapi/include/confdefs.h b/cpukit/sapi/include/confdefs.h
index 7f7a1ca..b50ff01 100644
--- a/cpukit/sapi/include/confdefs.h
+++ b/cpukit/sapi/include/confdefs.h
@@ -518,7 +518,16 @@ rtems_fs_init_functions_trtems_fs_init_helper =
#endif
#ifndef CONFIGURE_INIT_TASK_ENTRY_POINT
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+rtems_task Init (rtems_task_argument );
+ #ifdef __cplusplus
+ }
+ #endif
#define CONFIGURE_INIT_TASK_ENTRY_POINT Init
+ extern const char* bsp_boot_cmdline;
+ #define CONFIGURE_INIT_TASK_ARGUMENTS ((rtems_task_argument)
&bsp_boot_cmdline)
#endif
#ifndef CONFIGURE_INIT_TASK_INITIAL_MODES
This differs from the POSIX_Init treatment in the same file. For C++ this
forces you to use a global Init function. In C you can also define Init as
static. This is a bit confusing. At least Init and POSIX_Init should use
similar definitions.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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Re: [PATCH 2/8] Move Mongoose-V specific devices into BSP.
If it helps, I have not heard of anyone using the Mongoose V in years. If it's still around and being used in a new project, I'm not aware of it . Alan On 10/9/14 3:50 PM, "Joel Sherrill" wrote: > >On 10/9/2014 2:47 PM, Gedare Bloom wrote: >> I didn't read this, but you should consider doing some style cleanup >> too (as a separate commit) >Noted. > >FWIW I didn't change any code file contents except to note that a .h >file moved from libcpu/ to bsp/. > >The big problem here is that when we did the BSP, we thought the >Mongoose-V on-CPU IP modules might show up again. They haven't >and moving them makes it clear they were specific to this single case. > >--joel >> On Thu, Oct 9, 2014 at 2:39 PM, Joel Sherrill >> wrote: >>> Putting the duart in libcpu was very optimistic and presumptuous. >>> It has never been used again on another SoC and is BSP specific. >>> --- >>> c/src/lib/libbsp/mips/genmongoosev/Makefile.am | 7 +- >>> c/src/lib/libbsp/mips/genmongoosev/README | 54 +- >>> .../libbsp/mips/genmongoosev/consoe/README.mguart | 100 +++ >>> .../lib/libbsp/mips/genmongoosev/console/conscfg.c | 2 +- >>> .../lib/libbsp/mips/genmongoosev/console/mg5uart.c | 917 >>>+ >>> .../lib/libbsp/mips/genmongoosev/console/mg5uart.h | 98 +++ >>> .../libbsp/mips/genmongoosev/console/mg5uart_reg.c | 58 ++ >>> c/src/lib/libbsp/mips/genmongoosev/include/bsp.h | 2 +- >>> .../libbsp/mips/genmongoosev/include/mongoose-v.h | 306 +++ >>> .../lib/libbsp/mips/genmongoosev/irq/vectorisrs.c | 2 +- >>> c/src/lib/libbsp/mips/genmongoosev/preinstall.am | 20 + >>> .../libbsp/mips/genmongoosev/startup/bspstart.c| 2 +- >>> .../libbsp/mips/genmongoosev/startup/gdb-support.c | 2 +- >>> c/src/lib/libcpu/mips/Makefile.am | 21 - >>> .../lib/libcpu/mips/mongoosev/duart/README.mguart | 101 --- >>> c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c| 917 >>>- >>> c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h| 98 --- >>> .../lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c | 58 -- >>> .../lib/libcpu/mips/mongoosev/include/mongoose-v.h | 306 --- >>> c/src/lib/libcpu/mips/preinstall.am| 14 - >>> 20 files changed, 1562 insertions(+), 1523 deletions(-) >>> create mode 100644 >>>c/src/lib/libbsp/mips/genmongoosev/console/README.mguart >>> create mode 100644 >>>c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.c >>> create mode 100644 >>>c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.h >>> create mode 100644 >>>c/src/lib/libbsp/mips/genmongoosev/console/mg5uart_reg.c >>> create mode 100644 >>>c/src/lib/libbsp/mips/genmongoosev/include/mongoose-v.h >>> delete mode 100644 c/src/lib/libcpu/mips/mongoosev/duar/README.mguart >>> delete mode 100644 c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c >>> delete mode 100644 c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h >>> delete mode 100644 c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c >>> delete mode 100644 >>>c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h >>> >>> diff --git a/c/src/lib/libbsp/mips/genmongoosev/Makefile.am >>>b/c/src/lib/libbsp/mips/genmongoosev/Makefile.am >>> index fe21df4..a99fd56 100644 >>> --- a/c/src/lib/libbsp/mips/genmongoosev/Makefile.am >>> ++ b/c/src/lib/libbsp/mips/genmongoosev/Makefile.am >>> @@ -16,6 +16,11 @@ include_bsp_HEADERS += include/irq.h >>> >>> nodist_include_HEADERS = include/bspopts.h >>> nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h >>> +nodist_include_bsp_HEADERS += include/lr33000.h >>> +nodist_include_bsp_HEADERS += include/lr333x0.h >>> +nodist_include_bsp_HEADERS += include/mongoose-v.h >>> +nodist_include_bsp_HEADERS += include/r3000.h >>> +nodist_include_bsp_HEADERS += console/mg5uart.h >>> DISTCLEANFILES = include/bspopts.h >>> noinst_PROGRAMS = >>> >>> @@ -47,6 +52,7 @@ libbsp_a_SOURCES += clock/clockdrv.c >>> libbsp_a_SOURCES += ../../shared/clockdrv_shell.h >>> # console >>> libbsp_a_SOURCES += console/conscfg.c >>> +libbsp_a_SOURCES += console/mg5uart.c >>> libbsp_a_SOURCES += ../../shared/console.c >>> libbsp_a_SOURCES += ../../shared/console_select.c >>> libbsp_a_SOURCES += ../../shared/console_control.c >>> @@ -75,7 +81,6 @@ gdbstub_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) >>> >>> libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel >>> libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel >>> -libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mongoosev/duart.rel >>> >>> include $(srcdir)/preinstall.am >>> include $(top_srcdir)/../../../../automake/local.am >>> diff --git a/c/src/lib/libbsp/mips/genmongoosev/README >>>b/c/src/lib/libbsp/mips/genmongoosev/README >>> index 97db696..87f57a9 100644 >>> --- a/c/src/lib/libbsp/mips/genmongoosev/README >>> +++ b/c/src/lib/libbsp/mips/genmongoosev/README >>> @@ -1,6 +1,56 @@ >>> BSP supporting the on-CPU capabilities of the Synova Mongoose-V. >>> -This BSP assumes that basic HW initializatio
smpfatal08 fails to build
Smpfatal08 fails to build on the head with the following configuration:
../rtems/configure --target=sparc-rtems4.11 \
--enable-maintainer-mode --enable-rtemsbsp=leon3 --disable-networking \
--enable-tests --enable-rtems-debug --enable-smp CFLAGS_FOR_BUILD="-O0"\
--prefix=${HOME}/smp/bsp-install
gmake[6]: Entering directory
`/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/testsuites/smptests/smpfatal08'
sparc-rtems4.11-gcc -B../../../../../leon3/lib/ -specs bsp_specs -qrtems
-DHAVE_CONFIG_H -I.
-I../../../../../../../rtems/c/src/../../testsuites/smptests/smpfatal08 -I..
-I../../../../../../../rtems/c/src/../../testsuites/smptests/../support/include
-mcpu=cypress -msoft-float -O2 -g -ffunction-sections -fdata-sections -Wall
-Wmissing-prototypes -Wimplicit-function-declaration -Wstrict-prototypes
-Wnested-externs -MT init.o -MD -MP -MF .deps/init.Tpo -c -o init.o
../../../../../../../rtems/c/src/../../testsuites/smptests/smpfatal08/init.c
mv -f .deps/init.Tpo .deps/init.Po
sparc-rtems4.11-gcc -B../../../../../leon3/lib/ -specs bsp_specs -qrtems
-mcpu=cypress -msoft-float -O2 -g -ffunction-sections -fdata-sections -Wall
-Wmissing-prototypes -Wimplicit-function-declaration -Wstrict-prototypes
-Wnested-externs -Wl,--gc-sections -mcpu=cypress -msoft-float -o
smpfatal08.exe init.o
../../../../../leon3/lib/librtemsbsp.a(libbsp_a-bspsmp.o): In function
`_CPU_SMP_Get_current_processor':
/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/lib/libbsp/sparc/leon3/../../../../../.././leon3/lib/include/rtems/score/sparc.h:370:
multiple definition of `_CPU_SMP_Get_current_processor'
init.o:/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/testsuites/smptests/smpfatal08/../../../../../../../rtems/c/src/../../testsuites/smptests/smpfatal08/init.c:64:
first defined here
../../../../../leon3/lib/librtemsbsp.a(libbsp_a-bspsmp.o): In function
`bsp_start_on_secondary_processor':
/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/lib/libbsp/sparc/leon3/../../../../../../../../rtems/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c:44:
multiple definition of `bsp_start_on_secondary_processor'
init.o:/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/testsuites/smptests/smpfatal08/../../../../../../../rtems/c/src/../../testsuites/smptests/smpfatal08/init.c:36:
first defined here
../../../../../leon3/lib/librtemsbsp.a(libbsp_a-bspsmp.o): In function
`_CPU_SMP_Initialize':
/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/lib/libbsp/sparc/leon3/../../../../../../../../rtems/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c:55:
multiple definition of `_CPU_SMP_Initialize'
init.o:/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/testsuites/smptests/smpfatal08/../../../../../../../rtems/c/src/../../testsuites/smptests/smpfatal08/init.c:43:
first defined here
../../../../../leon3/lib/librtemsbsp.a(libbsp_a-bspsmp.o): In function
`_CPU_SMP_Start_processor':
/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/lib/libbsp/sparc/leon3/../../../../../../../../rtems/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c:67:
multiple definition of `_CPU_SMP_Start_processor'
init.o:/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/testsuites/smptests/smpfatal08/../../../../../../../rtems/c/src/../../testsuites/smptests/smpfatal08/init.c:50:
first defined here
../../../../../leon3/lib/librtemsbsp.a(libbsp_a-bspsmp.o): In function
`_CPU_SMP_Finalize_initialization':
/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/lib/libbsp/sparc/leon3/../../../../../../../../rtems/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c:78:
multiple definition of `_CPU_SMP_Finalize_initialization'
init.o:/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/testsuites/smptests/smpfatal08/../../../../../../../rtems/c/src/../../testsuites/smptests/smpfatal08/init.c:53:
first defined here
../../../../../leon3/lib/librtemsbsp.a(libbsp_a-bspsmp.o): In function
`_CPU_SMP_Send_interrupt':
/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/lib/libbsp/sparc/leon3/../../../../../../../../rtems/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c:87:
multiple definition of `_CPU_SMP_Send_interrupt'
init.o:/home/jennifer/smp/b-leon3smp/sparc-rtems4.11/c/leon3/testsuites/smptests/smpfatal08/../../../../../../../rtems/c/src/../../testsuites/smptests/smpfatal08/init.c:75:
first defined here
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Re: [PATCH 2/8] Move Mongoose-V specific devices into BSP.
On October 10, 2014 7:26:39 AM CDT, "Cudmore, Alan P. (GSFC-5820)" wrote: >If it helps, I have not heard of anyone using the Mongoose V in years. >If it's still around and being used in a new project, I'm not aware of >it . We have discussed cleaning out old bsps after 4.11. This would put the Mongoose high on the list to me. Thanks >Alan > > >On 10/9/14 3:50 PM, "Joel Sherrill" wrote: > >> >>On 10/9/2014 2:47 PM, Gedare Bloom wrote: >>> I didn't read this, but you should consider doing some style cleanup >>> too (as a separate commit) >>Noted. >> >>FWIW I didn't change any code file contents except to note that a .h >>file moved from libcpu/ to bsp/. >> >>The big problem here is that when we did the BSP, we thought the >>Mongoose-V on-CPU IP modules might show up again. They haven't >>and moving them makes it clear they were specific to this single case. >> >>--joel >>> On Thu, Oct 9, 2014 at 2:39 PM, Joel Sherrill >>> wrote: Putting the duart in libcpu was very optimistic and presumptuous. It has never been used again on another SoC and is BSP specific. --- c/src/lib/libbsp/mips/genmongoosev/Makefile.am | 7 +- c/src/lib/libbsp/mips/genmongoosev/README | 54 +- .../libbsp/mips/genmongoosev/consoe/README.mguart | 100 +++ .../lib/libbsp/mips/genmongoosev/console/conscfg.c | 2 +- .../lib/libbsp/mips/genmongoosev/console/mg5uart.c | 917 + .../lib/libbsp/mips/genmongoosev/console/mg5uart.h | 98 +++ .../libbsp/mips/genmongoosev/console/mg5uart_reg.c | 58 ++ c/src/lib/libbsp/mips/genmongoosev/include/bsp.h | 2 +- .../libbsp/mips/genmongoosev/include/mongoose-v.h | 306 +++ .../lib/libbsp/mips/genmongoosev/irq/vectorisrs.c | 2 +- c/src/lib/libbsp/mips/genmongoosev/preinstall.am | 20 + .../libbsp/mips/genmongoosev/startup/bspstart.c| 2 +- .../libbsp/mips/genmongoosev/startup/gdb-support.c | 2 +- c/src/lib/libcpu/mips/Makefile.am | 21 - .../lib/libcpu/mips/mongoosev/duart/README.mguart | 101 --- c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c| 917 - c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h| 98 --- .../lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c | 58 -- .../lib/libcpu/mips/mongoosev/include/mongoose-v.h | 306 --- c/src/lib/libcpu/mips/preinstall.am| 14 - 20 files changed, 1562 insertions(+), 1523 deletions(-) create mode 100644 c/src/lib/libbsp/mips/genmongoosev/console/README.mguart create mode 100644 c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.c create mode 100644 c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.h create mode 100644 c/src/lib/libbsp/mips/genmongoosev/console/mg5uart_reg.c create mode 100644 c/src/lib/libbsp/mips/genmongoosev/include/mongoose-v.h delete mode 100644 >c/src/lib/libcpu/mips/mongoosev/duar/README.mguart delete mode 100644 c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c delete mode 100644 c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h delete mode 100644 >c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c delete mode 100644 c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h diff --git a/c/src/lib/libbsp/mips/genmongoosev/Makefile.am b/c/src/lib/libbsp/mips/genmongoosev/Makefile.am index fe21df4..a99fd56 100644 --- a/c/src/lib/libbsp/mips/genmongoosev/Makefile.am ++ b/c/src/lib/libbsp/mips/genmongoosev/Makefile.am @@ -16,6 +16,11 @@ include_bsp_HEADERS += include/irq.h nodist_include_HEADERS = include/bspopts.h nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h +nodist_include_bsp_HEADERS += include/lr33000.h +nodist_include_bsp_HEADERS += include/lr333x0.h +nodist_include_bsp_HEADERS += include/mongoose-v.h +nodist_include_bsp_HEADERS += include/r3000.h +nodist_include_bsp_HEADERS += console/mg5uart.h DISTCLEANFILES = include/bspopts.h noinst_PROGRAMS = @@ -47,6 +52,7 @@ libbsp_a_SOURCES += clock/clockdrv.c libbsp_a_SOURCES += ../../shared/clockdrv_shell.h # console libbsp_a_SOURCES += console/conscfg.c +libbsp_a_SOURCES += console/mg5uart.c libbsp_a_SOURCES += ../../shared/console.c libbsp_a_SOURCES += ../../shared/console_select.c libbsp_a_SOURCES += ../../shared/console_control.c @@ -75,7 +81,6 @@ gdbstub_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel libbsp_a_LIBADD += >../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel -libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mongoosev/duart.rel include $(srcdir)/preinstall.am include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/mips/genmongoosev/README b/c/src/lib/libbsp/mips/g
[PATCH 1/2] libcpu/or1k: Fix warnings.
--- c/src/lib/libcpu/or1k/shared/cache/cache.c | 16 c/src/lib/libcpu/or1k/shared/cache/cache_.h | 1 + 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c index 039be36..d38b572 100644 --- a/c/src/lib/libcpu/or1k/shared/cache/cache.c +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c @@ -71,7 +71,7 @@ static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr) _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uint32_t) d_addr); _ISR_Enable(level); } @@ -81,7 +81,7 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr) ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uint32_t) d_addr); _ISR_Enable(level); } @@ -91,7 +91,7 @@ static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr) ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uint32_t) d_addr); _ISR_Enable(level); } @@ -101,7 +101,7 @@ static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr) ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uint32_t) d_addr); _ISR_Enable(level); } @@ -111,7 +111,7 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr) ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uint32_t) d_addr); _ISR_Enable(level); } @@ -122,7 +122,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_prefetch ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uint32_t) d_addr); _ISR_Enable(level); } @@ -133,7 +133,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_invalidate ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uint32_t) d_addr); _ISR_Enable(level); } @@ -144,7 +144,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uint32_t) d_addr); _ISR_Enable(level); } diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h index 5f08410..0ea939f 100644 --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h @@ -6,6 +6,7 @@ #define __OR1K_CACHE_H #include +#include #endif /* end of include file */ -- 1.9.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/2] libbsp/or1ksim: Fix warnings.
---
c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c | 2 +-
c/src/lib/libbsp/or1k/or1ksim/console/uart.c | 15 +++
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c
b/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c
index ad49d07..4169a11 100644
--- a/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c
+++ b/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c
@@ -137,8 +137,8 @@ CPU_Counter_ticks _CPU_Counter_difference(
#define Clock_driver_support_install_isr(isr, old_isr) \
do { \
-or1ksim_clock_handler_install(isr, old_isr); \
old_isr = NULL;\
+or1ksim_clock_handler_install(isr, old_isr); \
} while (0)
#define Clock_driver_support_shutdown_hardware() or1ksim_clock_cleanup()
diff --git a/c/src/lib/libbsp/or1k/or1ksim/console/uart.c
b/c/src/lib/libbsp/or1k/or1ksim/console/uart.c
index 7ceca81..31cdce6 100644
--- a/c/src/lib/libbsp/or1k/or1ksim/console/uart.c
+++ b/c/src/lib/libbsp/or1k/or1ksim/console/uart.c
@@ -21,6 +21,14 @@
#include
#include
+static void uart_initialize(int minor);
+static int uart_first_open(int major, int minor, void *arg);
+static int uart_last_close(int major, int minor, void *arg);
+static int uart_read_polled(int minor);
+static ssize_t uart_write(int minor, const char *buf, size_t len);
+static void uart_write_polled(int minor, char c);
+static int uart_set_attributes(int minor, const struct termios *t);
+
static rtems_vector_number uart_get_irq_number(const console_tbl *ct)
{
return ct->ulIntVector;
@@ -86,10 +94,9 @@ static int uart_last_close(int major, int minor, void *arg)
return 0;
}
-static char uart_read_polled(int minor)
+static int uart_read_polled(int minor)
{
unsigned char lsr;
- char c;
/* Get a character when avaiable */
do {
@@ -120,7 +127,7 @@ static void uart_write_polled(int minor, char c)
} while ( (lsr & transmit_finished) != transmit_finished );
}
-static ssize_t uart_write_support_polled(
+static ssize_t uart_write(
int minor,
const char *s,
size_t n
@@ -145,7 +152,7 @@ const console_fns or1ksim_uart_fns = {
.deviceFirstOpen = uart_first_open,
.deviceLastClose = uart_last_close,
.deviceRead = uart_read_polled,
- .deviceWrite = uart_write_support_polled,
+ .deviceWrite = uart_write,
.deviceInitialize = uart_initialize,
.deviceWritePolled = uart_write_polled,
.deviceSetAttributes = uart_set_attributes,
--
1.9.3
___
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devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: How to send a shutdown signal to QEMU from RTEMS?
On Wed, Oct 8, 2014 at 4:20 PM, Joel Sherrill wrote: > > On 10/8/2014 12:15 AM, Sebastian Huber wrote: > > On 07/10/14 15:53, Hesham Moustafa wrote: > >> Hi, > >> > >> I want to send shutdown signal from RTEMS to qemu. Joel said that > >> qemu-system-i386 does so; can anyone refers me to how to implement that > for > >> qemu-system-or32 (openrisc)? > > This is target dependent. Some targets implement the registers of the > reset > > module. The easiest thing to figure this out is looking at the Qemu > sources. > > > We need to ask Christian. There is a command line option to qemu > which turns on "exit on reset" (--no-reboot). If the simulated target > hardware has a way to reset it from software, the target specific > simulation > can honor the command line option and just exit rather than start over. > > We use this on at least the pc386. > > Would you please provide the related QEMU code so that I can try to imitate for or1k? > The questions for Christian are: > > + Does the or1ksim have a software reset capability? If not, can we > add one? > > There is a single assembly instruction that shutdowns the whole or1ksim simulator process. We can use it from RTEMS. The question is where is the best place to put in this instruction? It's BSP related, and I was thinking of _CPU_Fatal_Halt, but it's not BSP related. However only or1ksim simulator recognizes this instruction, and it has no effect on other (future) target (QEMU, FPGA board, etc). > + Can qemu be modified to support this? > > It should only be a few lines of code in qemu and one write to the > magic location in the BSP. > > It will be of great value in speeding the testing procedure. > > -- > Joel Sherrill, Ph.D. Director of Research & Development > joel.sherr...@oarcorp.comOn-Line Applications Research > Ask me about RTEMS: a free RTOS Huntsville AL 35805 > Support Available(256) 722-9985 > > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/2] libcpu/or1k: Fix warnings.
Just one note, I prefer to see addresses cast to uintptr_t. On Fri, Oct 10, 2014 at 12:44 PM, Hesham ALMatary wrote: > --- > c/src/lib/libcpu/or1k/shared/cache/cache.c | 16 > c/src/lib/libcpu/or1k/shared/cache/cache_.h | 1 + > 2 files changed, 9 insertions(+), 8 deletions(-) > > diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c > b/c/src/lib/libcpu/or1k/shared/cache/cache.c > index 039be36..d38b572 100644 > --- a/c/src/lib/libcpu/or1k/shared/cache/cache.c > +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c > @@ -71,7 +71,7 @@ static inline void > _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr) > >_ISR_Disable (level); > > - _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr); > + _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uint32_t) d_addr); > >_ISR_Enable(level); > } > @@ -81,7 +81,7 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const > void *d_addr) > ISR_Level level; >_ISR_Disable (level); > > - _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr); > + _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uint32_t) d_addr); > >_ISR_Enable(level); > } > @@ -91,7 +91,7 @@ static inline void > _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr) > ISR_Level level; >_ISR_Disable (level); > > - _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr); > + _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uint32_t) d_addr); > >_ISR_Enable(level); > } > @@ -101,7 +101,7 @@ static inline void > _CPU_OR1K_Cache_data_block_writeback(const void *d_addr) > ISR_Level level; >_ISR_Disable (level); > > - _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr); > + _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uint32_t) d_addr); > >_ISR_Enable(level); > } > @@ -111,7 +111,7 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const > void *d_addr) > ISR_Level level; >_ISR_Disable (level); > > - _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr); > + _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uint32_t) d_addr); > >_ISR_Enable(level); > } > @@ -122,7 +122,7 @@ static inline void > _CPU_OR1K_Cache_instruction_block_prefetch > ISR_Level level; >_ISR_Disable (level); > > - _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr); > + _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uint32_t) d_addr); > >_ISR_Enable(level); > } > @@ -133,7 +133,7 @@ static inline void > _CPU_OR1K_Cache_instruction_block_invalidate > ISR_Level level; >_ISR_Disable (level); > > - _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr); > + _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uint32_t) d_addr); > >_ISR_Enable(level); > } > @@ -144,7 +144,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock > ISR_Level level; >_ISR_Disable (level); > > - _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr); > + _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uint32_t) d_addr); > >_ISR_Enable(level); > } > diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h > b/c/src/lib/libcpu/or1k/shared/cache/cache_.h > index 5f08410..0ea939f 100644 > --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h > +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h > @@ -6,6 +6,7 @@ > #define __OR1K_CACHE_H > > #include > +#include > > #endif > /* end of include file */ > -- > 1.9.3 > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: How to send a shutdown signal to QEMU from RTEMS?
On 10/10/2014 11:56 AM, Hesham Moustafa wrote: > > > On Wed, Oct 8, 2014 at 4:20 PM, Joel Sherrill > mailto:joel.sherr...@oarcorp.com>> wrote: > > > On 10/8/2014 12:15 AM, Sebastian Huber wrote: > > On 07/10/14 15:53, Hesham Moustafa wrote: > >> Hi, > >> > >> I want to send shutdown signal from RTEMS to qemu. Joel said that > >> qemu-system-i386 does so; can anyone refers me to how to > implement that for > >> qemu-system-or32 (openrisc)? > > This is target dependent. Some targets implement the registers > of the reset > > module. The easiest thing to figure this out is looking at the > Qemu sources. > > > We need to ask Christian. There is a command line option to qemu > which turns on "exit on reset" (--no-reboot). If the simulated target > hardware has a way to reset it from software, the target specific > simulation > can honor the command line option and just exit rather than start > over. > > We use this on at least the pc386. > > Would you please provide the related QEMU code so that I can try to > imitate for or1k? Bring Christian in on this. There has to be defined a hardware way to shutdown. It can be as simple as a new "IO device" which has a single register. When you write to it, the simulator just does an orderly shutdown. But if the or1k HW already has some defined HW mechanism to request a reset, then we need to know that so that the simulator can exit or restart when that is touched properly. The qemu code is complex but it centers around qemu_system_reset_request() as best I can tell. > > The questions for Christian are: > > + Does the or1ksim have a software reset capability? If not, can we > add one? > > There is a single assembly instruction that shutdowns the whole > or1ksim simulator process. We can use it from RTEMS. The question is > where is the best place to put in this instruction? It's BSP related, > and I was thinking of _CPU_Fatal_Halt, but it's not BSP related. > However only or1ksim simulator recognizes this instruction, and it has > no effect on other (future) target (QEMU, FPGA board, etc). > > + Can qemu be modified to support this? > > It should only be a few lines of code in qemu and one write to the > magic location in the BSP. > > It will be of great value in speeding the testing procedure. > > -- > Joel Sherrill, Ph.D. Director of Research & Development > joel.sherr...@oarcorp.comOn-Line Applications Research > Ask me about RTEMS: a free RTOS Huntsville AL 35805 > Support Available(256) 722-9985 > > -- Joel Sherrill, Ph.D. Director of Research & Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/2] libcpu/or1k: Fix warnings.
On 10/10/2014 12:04 PM, Gedare Bloom wrote: > Just one note, I prefer to see addresses cast to uintptr_t. +1 Assuming sizeof(void *) == sizeof(uint32_t) can be a problem in the future. If the value is used more than once, it often makes sense to declare a local variable of the proper type. > On Fri, Oct 10, 2014 at 12:44 PM, Hesham ALMatary > wrote: >> --- >> c/src/lib/libcpu/or1k/shared/cache/cache.c | 16 >> c/src/lib/libcpu/or1k/shared/cache/cache_.h | 1 + >> 2 files changed, 9 insertions(+), 8 deletions(-) >> >> diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c >> b/c/src/lib/libcpu/or1k/shared/cache/cache.c >> index 039be36..d38b572 100644 >> --- a/c/src/lib/libcpu/or1k/shared/cache/cache.c >> +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c >> @@ -71,7 +71,7 @@ static inline void >> _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr) >> >>_ISR_Disable (level); >> >> - _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr); >> + _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uint32_t) d_addr); >> >>_ISR_Enable(level); >> } >> @@ -81,7 +81,7 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const >> void *d_addr) >> ISR_Level level; >>_ISR_Disable (level); >> >> - _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr); >> + _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uint32_t) d_addr); >> >>_ISR_Enable(level); >> } >> @@ -91,7 +91,7 @@ static inline void >> _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr) >> ISR_Level level; >>_ISR_Disable (level); >> >> - _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr); >> + _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uint32_t) d_addr); >> >>_ISR_Enable(level); >> } >> @@ -101,7 +101,7 @@ static inline void >> _CPU_OR1K_Cache_data_block_writeback(const void *d_addr) >> ISR_Level level; >>_ISR_Disable (level); >> >> - _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr); >> + _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uint32_t) d_addr); >> >>_ISR_Enable(level); >> } >> @@ -111,7 +111,7 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const >> void *d_addr) >> ISR_Level level; >>_ISR_Disable (level); >> >> - _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr); >> + _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uint32_t) d_addr); >> >>_ISR_Enable(level); >> } >> @@ -122,7 +122,7 @@ static inline void >> _CPU_OR1K_Cache_instruction_block_prefetch >> ISR_Level level; >>_ISR_Disable (level); >> >> - _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr); >> + _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uint32_t) d_addr); >> >>_ISR_Enable(level); >> } >> @@ -133,7 +133,7 @@ static inline void >> _CPU_OR1K_Cache_instruction_block_invalidate >> ISR_Level level; >>_ISR_Disable (level); >> >> - _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr); >> + _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uint32_t) d_addr); >> >>_ISR_Enable(level); >> } >> @@ -144,7 +144,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock >> ISR_Level level; >>_ISR_Disable (level); >> >> - _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr); >> + _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uint32_t) d_addr); >> >>_ISR_Enable(level); >> } >> diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h >> b/c/src/lib/libcpu/or1k/shared/cache/cache_.h >> index 5f08410..0ea939f 100644 >> --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h >> +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h >> @@ -6,6 +6,7 @@ >> #define __OR1K_CACHE_H >> >> #include >> +#include >> >> #endif >> /* end of include file */ >> -- >> 1.9.3 >> >> ___ >> devel mailing list >> devel@rtems.org >> http://lists.rtems.org/mailman/listinfo/devel > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel -- Joel Sherrill, Ph.D. Director of Research & Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/2] libcpu/or1k: Fix warnings.
--- c/src/lib/libcpu/or1k/shared/cache/cache.c | 16 c/src/lib/libcpu/or1k/shared/cache/cache_.h | 1 + 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c index 039be36..afc8859 100644 --- a/c/src/lib/libcpu/or1k/shared/cache/cache.c +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c @@ -71,7 +71,7 @@ static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr) _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr); _ISR_Enable(level); } @@ -81,7 +81,7 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr) ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr); _ISR_Enable(level); } @@ -91,7 +91,7 @@ static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr) ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr); _ISR_Enable(level); } @@ -101,7 +101,7 @@ static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr) ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr); _ISR_Enable(level); } @@ -111,7 +111,7 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr) ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr); _ISR_Enable(level); } @@ -122,7 +122,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_prefetch ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr); _ISR_Enable(level); } @@ -133,7 +133,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_invalidate ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr); _ISR_Enable(level); } @@ -144,7 +144,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock ISR_Level level; _ISR_Disable (level); - _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr); + _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr); _ISR_Enable(level); } diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h index 5f08410..0ea939f 100644 --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h @@ -6,6 +6,7 @@ #define __OR1K_CACHE_H #include +#include #endif /* end of include file */ -- 1.9.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
sis build failure with SMP enabled
Hi Any thoughts on how to address this? gmake[6]: Entering directory `/home/joel/rtems-4.11-work/b-sis/sparc-rtems4.11/c/sis/testsuites/smptests/smpcache01' sparc-rtems4.11-gcc -B../../../../../sis/lib/ -specs bsp_specs -qrtems -mcpu=cypress -O2 -g -ffunction-sections -fdata-sections -Wall -Wmissing-prototypes -Wimplicit-function-declaration -Wstrict-prototypes -Wnested-externs -Wl,--gc-sections -mcpu=cypress -o smpcache01.exe init.o init.o: In function `test_func_test': /home/joel/rtems-4.11-work/b-sis/sparc-rtems4.11/c/sis/testsuites/smptests/smpcache01/../../../../../../../rtems/c/src/../../testsuites/smptests/smpcache01/init.c:114: undefined reference to `_Cache_manager_Send_smp_msg' init.o: In function `test_func_isrdisabled_test': /home/joel/rtems-4.11-work/b-sis/sparc-rtems4.11/c/sis/testsuites/smptests/smpcache01/../../../../../../../rtems/c/src/../../testsuites/smptests/smpcache01/init.c:132: undefined reference to `_Cache_manager_Send_smp_msg' init.o: In function `test_func_giant_taken_test': -- Joel Sherrill, Ph.D. Director of Research & Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Prototype for Init in confdefs.h
On 10/10/2014 9:17 pm, Sebastian Huber wrote:
Hello,
what was the reason for this change?
Maybe commit 2549b4d9a83d310e32329255a5a02604eb9e028b ?
commit d8b74dbebd341073f0c5b03e589d3fcd349745d1
Author: Chris Johns
Date: Tue Apr 28 06:39:24 2009 +
2009-04-28 Chris Johns
* sapi/include/confdefs.h: Add a prototype for Init with C
linkage
and define Init task command line arguments if confdefs.h
provides
an Init entry point.
diff --git a/cpukit/ChangeLog b/cpukit/ChangeLog
index 9432abc..477ce23 100644
--- a/cpukit/ChangeLog
+++ b/cpukit/ChangeLog
@@ -1,3 +1,9 @@
+2009-04-28 Chris Johns
+
+ * sapi/include/confdefs.h: Add a prototype for Init with C linkage
+ and define Init task command line arguments if confdefs.h provides
+ an Init entry point.
+
2009-04-15 Ralf Corsepius
* configure.ac: Disable LIBSHELL for unix targets.
diff --git a/cpukit/sapi/include/confdefs.h
b/cpukit/sapi/include/confdefs.h
index 7f7a1ca..b50ff01 100644
--- a/cpukit/sapi/include/confdefs.h
+++ b/cpukit/sapi/include/confdefs.h
@@ -518,7 +518,16 @@ rtems_fs_init_functions_trtems_fs_init_helper =
#endif
#ifndef CONFIGURE_INIT_TASK_ENTRY_POINT
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+rtems_task Init (rtems_task_argument );
+ #ifdef __cplusplus
+ }
+ #endif
#define CONFIGURE_INIT_TASK_ENTRY_POINT Init
+ extern const char* bsp_boot_cmdline;
+ #define CONFIGURE_INIT_TASK_ARGUMENTS ((rtems_task_argument)
&bsp_boot_cmdline)
#endif
#ifndef CONFIGURE_INIT_TASK_INITIAL_MODES
This differs from the POSIX_Init treatment in the same file. For C++
this forces you to use a global Init function. In C you can also define
Init as static. This is a bit confusing.
Why not provide CONFIGURE_INIT_TASK_ENTRY_POINT and it can be whatever
linkage you like ?
I think the 'extern "C"' is not needed because there is another around
everything. I do not think nesting them makes the code more C than C. :)
At least Init and POSIX_Init should use similar definitions.
Sure.
I never use either constructs and use 'main'.
Chris
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