On October 10, 2014 7:26:39 AM CDT, "Cudmore, Alan P. (GSFC-5820)"
<alan.p.cudm...@nasa.gov> wrote:
>If it helps, I have not heard of anyone using the Mongoose V in years.
>If it's still around and being used in a new project, I'm not aware of
>it .
We have discussed cleaning out old bsps after 4.11. This would put the Mongoose
high on the list to me.
Thanks
>Alan
>
>
>On 10/9/14 3:50 PM, "Joel Sherrill" <joel.sherr...@oarcorp.com> wrote:
>
>>
>>On 10/9/2014 2:47 PM, Gedare Bloom wrote:
>>> I didn't read this, but you should consider doing some style cleanup
>>> too (as a separate commit)
>>Noted.
>>
>>FWIW I didn't change any code file contents except to note that a .h
>>file moved from libcpu/ to bsp/.
>>
>>The big problem here is that when we did the BSP, we thought the
>>Mongoose-V on-CPU IP modules might show up again. They haven't
>>and moving them makes it clear they were specific to this single case.
>>
>>--joel
>>> On Thu, Oct 9, 2014 at 2:39 PM, Joel Sherrill
>>><joel.sherr...@oarcorp.com> wrote:
>>>> Putting the duart in libcpu was very optimistic and presumptuous.
>>>> It has never been used again on another SoC and is BSP specific.
>>>> ---
>>>> c/src/lib/libbsp/mips/genmongoosev/Makefile.am | 7 +-
>>>> c/src/lib/libbsp/mips/genmongoosev/README | 54 +-
>>>> .../libbsp/mips/genmongoosev/consoe/README.mguart | 100 +++
>>>> .../lib/libbsp/mips/genmongoosev/console/conscfg.c | 2 +-
>>>> .../lib/libbsp/mips/genmongoosev/console/mg5uart.c | 917
>>>>+++++++++++++++++++++
>>>> .../lib/libbsp/mips/genmongoosev/console/mg5uart.h | 98 +++
>>>> .../libbsp/mips/genmongoosev/console/mg5uart_reg.c | 58 ++
>>>> c/src/lib/libbsp/mips/genmongoosev/include/bsp.h | 2 +-
>>>> .../libbsp/mips/genmongoosev/include/mongoose-v.h | 306 +++++++
>>>> .../lib/libbsp/mips/genmongoosev/irq/vectorisrs.c | 2 +-
>>>> c/src/lib/libbsp/mips/genmongoosev/preinstall.am | 20 +
>>>> .../libbsp/mips/genmongoosev/startup/bspstart.c | 2 +-
>>>> .../libbsp/mips/genmongoosev/startup/gdb-support.c | 2 +-
>>>> c/src/lib/libcpu/mips/Makefile.am | 21 -
>>>> .../lib/libcpu/mips/mongoosev/duart/README.mguart | 101 ---
>>>> c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c | 917
>>>>---------------------
>>>> c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h | 98 ---
>>>> .../lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c | 58 --
>>>> .../lib/libcpu/mips/mongoosev/include/mongoose-v.h | 306 -------
>>>> c/src/lib/libcpu/mips/preinstall.am | 14 -
>>>> 20 files changed, 1562 insertions(+), 1523 deletions(-)
>>>> create mode 100644
>>>>c/src/lib/libbsp/mips/genmongoosev/console/README.mguart
>>>> create mode 100644
>>>>c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.c
>>>> create mode 100644
>>>>c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.h
>>>> create mode 100644
>>>>c/src/lib/libbsp/mips/genmongoosev/console/mg5uart_reg.c
>>>> create mode 100644
>>>>c/src/lib/libbsp/mips/genmongoosev/include/mongoose-v.h
>>>> delete mode 100644
>c/src/lib/libcpu/mips/mongoosev/duar/README.mguart
>>>> delete mode 100644 c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
>>>> delete mode 100644 c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h
>>>> delete mode 100644
>c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c
>>>> delete mode 100644
>>>>c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
>>>>
>>>> diff --git a/c/src/lib/libbsp/mips/genmongoosev/Makefile.am
>>>>b/c/src/lib/libbsp/mips/genmongoosev/Makefile.am
>>>> index fe21df4..a99fd56 100644
>>>> --- a/c/src/lib/libbsp/mips/genmongoosev/Makefile.am
>>>> ++ b/c/src/lib/libbsp/mips/genmongoosev/Makefile.am
>>>> @@ -16,6 +16,11 @@ include_bsp_HEADERS += include/irq.h
>>>>
>>>> nodist_include_HEADERS = include/bspopts.h
>>>> nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
>>>> +nodist_include_bsp_HEADERS += include/lr33000.h
>>>> +nodist_include_bsp_HEADERS += include/lr333x0.h
>>>> +nodist_include_bsp_HEADERS += include/mongoose-v.h
>>>> +nodist_include_bsp_HEADERS += include/r3000.h
>>>> +nodist_include_bsp_HEADERS += console/mg5uart.h
>>>> DISTCLEANFILES = include/bspopts.h
>>>> noinst_PROGRAMS =
>>>>
>>>> @@ -47,6 +52,7 @@ libbsp_a_SOURCES += clock/clockdrv.c
>>>> libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
>>>> # console
>>>> libbsp_a_SOURCES += console/conscfg.c
>>>> +libbsp_a_SOURCES += console/mg5uart.c
>>>> libbsp_a_SOURCES += ../../shared/console.c
>>>> libbsp_a_SOURCES += ../../shared/console_select.c
>>>> libbsp_a_SOURCES += ../../shared/console_control.c
>>>> @@ -75,7 +81,6 @@ gdbstub_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
>>>>
>>>> libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
>>>> libbsp_a_LIBADD +=
>../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
>>>> -libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mongoosev/duart.rel
>>>>
>>>> include $(srcdir)/preinstall.am
>>>> include $(top_srcdir)/../../../../automake/local.am
>>>> diff --git a/c/src/lib/libbsp/mips/genmongoosev/README
>>>>b/c/src/lib/libbsp/mips/genmongoosev/README
>>>> index 97db696..87f57a9 100644
>>>> --- a/c/src/lib/libbsp/mips/genmongoosev/README
>>>> +++ b/c/src/lib/libbsp/mips/genmongoosev/README
>>>> @@ -1,6 +1,56 @@
>>>> BSP supporting the on-CPU capabilities of the Synova Mongoose-V.
>>>> -This BSP assumes that basic HW initialization is performed by
>>>> -PMON.
>>>> +The Synova Mongoose-V is a radiation hardened derivative of the
>>>> +LSI 33K with on-CPU peripherals.
>>>> +
>>>> +This BSP assumes that basic HW initialization is performed by
>PMON.
>>>> +
>>>> +Status
>>>> +======
>>>> +Per-task floating point enable/disable is supported for both
>immediate
>>>> +and deferred FPU context swaps.
>>>> +
>>>> +Interrupt Levels are adapted reasonably well to the MIPS interrupt
>>>> +model. Bit 0 of the int level is a global enable/disable,
>>>>corresponding
>>>> +to bit 0 of the processor's SR register. Bits 1 thru 6 are
>configured
>>>> +as masks for the Int0 thru Int5 interrupts. The 2 software
>interrupt
>>>> +bits are always enabled by default. Each task maintains its own
>>>> +Interrupt Level setting, reconfiguring the SR register's interrupt
>>>>bits
>>>> +whenever scheduled in. The software ints, though not addressable
>via
>>>> +the various Interrupt Level functions, are maintained on a
>per-task
>>>> +basis, so if software manipulates them drectly, things should
>behave
>>>>as
>>>> +expected. At the time of these udpates, the Interrupt Level was
>only
>>>>8
>>>> +bits, and completely supporting the global enable, software ints
>and
>>>>the
>>>> +hardware ints would require 9 bits. When more than 8 bits are
>>>> +available, there is no reason the software interrupts could not be
>>>>added
>>>> +to the Interrupt Level.
>>>> +
>>>> +While supporting the Int0 thru Int5 bits in this way doesn't seem
>>>> +wonderfully useful, it does increase the level of compliance with
>the
>>>> +RTEMS spec.
>>>> +
>>>> +Interrupt Level 0 corresponds to interrupts globally enabled,
>software
>>>> +ints enabled and Int0 thru Int5 enabled. If values other than 0
>are
>>>> +supplied, they should be formulated to impose the desired bitmask.
>>>> +Interrupt priority is not a strong concept on this bsp, it is
>provided
>>>> +only by the order in which interrupts are checked.
>>>> +
>>>> +If during the vectoring of an interrupt, others arrive, they will
>all
>>>>be
>>>> +processed in accordance with their ordering in SR & the peripheral
>>>> +register. For example, if while we're vectoring Int4, Int3 and
>Int5
>>>>are
>>>> +asserted, Int3 ill be serviced before Int5. The peripheral
>>>>interrupts
>>>> +are individually vectored as a consequence of Int5 being asserted,
>>>> +however Int5 is not itself vectored. Within the set of peripheral
>>>> +interrupts, bit 0 is vectored first, 31 is last.
>>>> +
>>>> +Interrupts are not nested for MIPS1 or MIPS3 processors, but are
>>>> +processed serially as possible. On an unloaded 50 task RTEMS
>program,
>>>> +runnning on a 12mhz MIPS1 processor, worst-case latencies of 100us
>>>>were
>>>> +observed, the average being down at 60us or below.
>>>> +
>>>> +
>>>> +These features are principally a consequence of fixes and tweaks
>to
>>>>the
>>>> +MIPS1and MIPS3 processor support, and should be equally effective
>on
>>>> +both levels of MIPS processors for any of their bsp's.
>>>>
>>>> Address Map
>>>> ===========
>>>> diff --git
>a/c/src/lib/libbsp/mips/genmongoosev/console/README.mguart
>>>>b/c/src/lib/libbsp/mips/genmongoosev/console/README.mguart
>>>> new file mode 100644
>>>> index 0000000..7c6a290
>>>> --- /dev/null
>>>> +++ b/c/src/lib/libbsp/mips/genmongoosev/console/README.mguart
>>>> @@ -0,0 +1,100 @@
>>>> +Configuration Table Use
>>>> +=======================
>>>> +
>>>> +sDeviceName
>>>> +
>>>> + The name of this device.
>>>> +
>>>> +deviceType
>>>> +
>>>> + This field must be SERIAL_MG5UART.
>>>> +
>>>> +pDeviceFns
>>>> +
>>>> + The device interface control table. This may be:
>>>> + + mg5uart_fns for interrupt driven IO
>>>> + + mg5uart_fns_polled for polled IO
>>>> +
>>>> +deviceProbe
>>>> +
>>>> + This is the address of the routine which probes to see if the
>>>>device
>>>> + is present.
>>>> +
>>>> +pDeviceFlow
>>>> +
>>>> + This field is ignored as hardware flow control is not currently
>>>>supported.
>>>> +
>>>> +ulMargin
>>>> +
>>>> + This is currently unused.
>>>> +
>>>> +ulHysteresis
>>>> +
>>>> + This is currently unused.
>>>> +
>>>> +pDeviceParams
>>>> +
>>>> + This is set to the default settings.
>>>> +
>>>> +ulCtrlPort1
>>>> +
>>>> + This field is the address of the command register shared by
>both
>>>>ports.
>>>> +
>>>> +ulCtrlPort2
>>>> +
>>>> + This field is the address of the port being used.
>>>> +
>>>> +ulDataPort
>>>> +
>>>> + This field is set to MG5UART_PORTA or MG5UART_PORTB.
>>>> +
>>>> +getRegister
>>>> +setRegister
>>>> +
>>>> + These do NOT follow standard conventions and are ignored.
>>>> + The register address routines are hard-coded as this is
>>>> + an on-CPU part and assumed to provide a 32-bit wide interface.
>>>> +
>>>> +getData
>>>> +
>>>> + This is address of the RX buffer register.
>>>> +
>>>> +setData
>>>> +
>>> + This is address of the TX buffer register.
>>>> +
>>>> +ulClock
>>>> +
>>>> + baudRate Clock
>>>> +
>>>> +ulIntVector
>>>> +
>>>> + This is the interrupt vector number associated with this chip.
>>>> +
>>>> +Example:
>>>> +
>>>> +#if (CONSOLE_USE_INTERRUPTS)
>>>> +#define MG5UART_FUNCTIONS &mg5uart_fns
>>>> +#else
>>>> +#define MG5UART_FUNCTIONS &mg5uart_fns_polled
>>>> +#endif
>>>> +
>>>> +{
>>>> + "/dev/com0", /* sDeviceName */
>>>> + SERIAL_MG5UART, /* deviceType */
>>>> + MG5UART_FUNCTIONS, /* pDeviceFns */
>>>> + NULL, /* deviceProbe, assume
>it
>>>>is there */
>>>> + NULL, /* pDeviceFlw */
>>>> + 16, /* ulMargin */
>>>> + 8, /* ulHysteresis */
>>>> + (void *) NULL, /* NULL */ /* pDeviceParams */
>>>> + MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, /* ulCtrlPort1 */
>>>> + MONGOOSEV_UART0_BASE, /* ulCtrlPort2 */
>>>> + MG5UART_UART0, /* ulDataPort */
>>>> + mg5uart_get_register, /* getRegister */
>>>> + mg5uart_set_register, /* setRegister */
>>>> + NULL, /* unused */ /* getData */
>>>> NULL, /* unused */ /* setData */
>>>> + 12000000, /* ulClock */
>>>> + MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR /* ulIntVector -- base
>for
>>>>port */
>>>> +}
>>>> diff --git a/c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c
>>>>b/c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c
>>>> index 61ac56e..87df736 100644
>>>> --- a/c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c
>>>> +++ b/c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c
>>>> @@ -21,7 +21,7 @@
>>>> #include <bsp/irq.h>
>>>>
>>>> #include <libchip/serial.h>
>>>> -#include <libchip/mg5uart.h>
>>>> +#include <bsp/mg5uart.h>
>>>>
>>>> /* #define CONSOLE_USE_INTERRUPTS */
>>>>
>>>> diff --git a/c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.c
>>>>b/c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.c
>>>> new file mode 100644
>>>> index 0000000..8c4177a
>>>> --- /dev/null
>>>> +++ b/c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.c
>>>> @@ -0,0 +1,917 @@
>>>> +/**
>>>> + * @file
>>>> + *
>>>> + * This file contains the termios TTY driver for the UART foun
>>>> + * on the Synova Mongoose-V.
>>>> + */
>>>> +
>>>> +/*
>>>> + * COPYRIGHT () 1989-2012.
>>>> + * On-Line Applications Research Corporation (OAR).
>>>> + *
>>>> + * The license and distribution terms for this file may be
>>>> + * found in the file LICENSE in this ditribution or at
>>>> + * http://www.rtems.org/license/LICENSE.
>>>> + */
>>>> +
>>>> +#include <rtems.h>
>>>> +#include <rtems/libio.h>
>>>> +#include <rtems/score/sysstate.h>
>>>> +#include <stdlib.h>
>>>> +
>>>> +#include <libchip/serial.h>
>>>> +#include <libchip/sersupp.h>
>>>> +#include <bsp/mg5uart.h>
>>>> +#include <bsp/mongoose-v.h>
>>>> +
>>>> +#include <bsp/irq.h>
>>>> +#include <bsp.h>
>>>> +
>>>> +/*
>>>> + * Indices of registers
>>>> + */
>>>> +
>>>> +/*
>>>> + * Per chip context control
>>>> + */
>>>> +
>>>> +typedef struct _mg5uart_context
>>>> +{
>>>> + int mate;
>>>> +} mg5uart_context;
>>>> +
>>>> +/*
>>>> + * Define MG5UART_STATIC to nothing while debugging so the entry
>>>>points
>>>> + * will show up in the symbol table.
>>>> + */
>>>> +
>>>> +#define MG5UART_STATIC
>>>> +
>>>> +/* #define MG5UART_STATIC static */
>>>> +
>>>> +
>>>> +
>>>> +#define MG5UART_SETREG( _base, _register, _value ) \
>>>> + MONGOOSEV_WRITE_REGISTER( _base, _register, _value )
>>>> +
>>>> +#define MG5UART_GETREG( _base, _register ) \
>>>> + MONGOOSEV_READ_REGISTER( _base, _register )
>>>> +
>>>> +
>>>> +/*
>>>> + * Console Device Driver Support Functions
>>>> + */
>>>> +
>>>> +MG5UART_STATIC int mg5art_baud_rate(
>>>> + int minor,
>>>> + uint32_t baud,
>>>> + uint32_t *code
>>>> +);
>>>> +
>>>> +MG5UART_STATIC void mg5uart_enable_interrupts(
>>>> + int minor,
>>>> + int mask
>>>> +);
>>>> +
>>>> +/*
>>>> + * mg5uart_isr_XXX
>>>> + *
>>>> + * This is the single interrupt entry point which parcels
>interrupts
>>>> + * out to the handlers for specific sources and makes sure that
>the
>>>> + * shared handler gets the right arguments.
>>>> + *
>>>> + * NOTE: Yes .. this is ugly but it provides 5 interrupt source
>>>> + * wrappers which are nearly functionally identical.
>>>> + */
>>>> +
>>>> +
>>>> +extern void mips_default_isr(int vector);
>>>> +
>>>> +#define __ISR(_TYPE, _OFFSET) \
>>>> + MG5UART_STATIC void mg5uart_process_isr_ ## _TYPE ( \
>>>> + int minor \
>>>> + ); \
>>>> + \
>>>> + MG5UART_STATIC rtems_isr mg5uart_isr_ ## _TYPE ( \
>>>> + void *arg \
>>>> + ) \
>>>> + { \
>>>> + rtems_vector_number vectr = (rtems_vector_number) arg; \
>>>> + int minor; \
>>>> + \
>>>> + for(minor=0 ; minor<Console_Port_Count ; minor++) { \
>>>> + if( Console_Port_Tbl[minor]->deviceType == SERIAL_MG5UART &&
>\
>>>> + vector == Console_Por_Tbl[minor]->ulIntVector + _OFFSET
>)
>>>>{ \
>>>> + mg5uart_process_isr_ ## _TYPE (mino); \
>>>> + return; \
>>>> + } \
>>>> + } \
>>>> + mips_default_isr( vector ); \
>>>> + }
>>>> +
>>>> +__ISR(rx_frame_error, MG5UART_IRQ_RX_FRAME_ERRO)
>>>> +__ISR(rx_overrun_error, MG5UART_IRQ_RX_OVERRUN_ERROR)
>>>> +__ISR(tx_empty, MG5UART_IRQ_TX_EMPTY)
>>>> +__ISR(tx_ready, MG5UART_IRQ_TX_READY)
>>>> +__ISR(rx_ready, MG5UART_IRQ_RX_READY)
>>>> +
>>>> +/*
>>>> + * mg5uart_set_attributes
>>>> + *
>>>> + * This function sets the UART channel to reflect the requested
>>>>termios
>>>> + * port settings.
>>>> + */
>>>> +
>>>> +MG5UART_STATIC int mg5uart_set_attributes(
>>>> + int minor,
>>>> + const struct termios *t
>>>> +)
>>>> +{
>>>> + uint32_t pMG5UART_port;
>>>> + uint32_t pMG5UART;
>>>> + uint32_t cmd, cmdSave;
>>>> + uint32_t baudcmd;
>>>> + uint32_t shift;
>>>> + rtems_interrupt_level Irql;
>>>> +
>>>> + pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
>>>> + pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
>>>> +
>>>> + /*
>>>> + * Set the baud rate
>>>> + */
>>>> +
>>>> + if (mg5uart_baud_rate( minor, t->c_cflag, &baudcmd ) == -1)
>>>> + return -1;
>>>> +
>>>> + /*
>>>> + * Base settings
>>>> + */
>>>> +
>>>> + /*
>>>> + * Base settings
>>>> + */
>>>> +
>>>> + cmd = MONGOOSEV_UART_CMD_RX_ENABLE |
>MONGOOSEV_UART_CMD_TX_ENABLE;
>>>> +
>>>> + /*
>>>> + * Parity
>>>> + */
>>>> +
>>>> + if (t->c_cflag & PARENB) {
>>>> + cmd |= MONGOOSEV_UART_CMD_PARITY_ENABLE;
>>>> + if (t->c_cflag & PARODD)
>>>> + cmd |= MONGOOSEV_UART_CMD_PARITY_ODD;
>>>> + else
>>>> + cmd |= MONGOOSEV_UART_CMD_PARITY_EVEN;
>>>> + } else {
>>>> + cmd |= MONGOOSEV_UART_CMD_PARITY_DISABLE;
>>>> + }
>>>> +
>>>> + /*
>>>> + * Character Size
>>>> + */
>>>> +
>>>> + if (t->c_cflag & CSIZE) {
>>>> + switch (t->c_cflag & CSIZE) {
>>>> + case CS5:
>>>> + case CS6:
>>>> + case CS7:
>>>> + return -1;
>>>> + break;
>>>> + case CS8:
>>>> + /* Mongoose-V only supports CS8 */
>>>> + break;
>>>> +
>>>> + }
>>>> + } /* else default to CS8 */
>>>> +
>>>> + /*
>>>> + * Stop Bits
>>>> + */
>>>> +
>>>> +#if 0
>>>> + if (t->c_cflag & CSTOPB) {
>>>> + /* 2 stop bits not supported by Mongoose-V uart */
>>>> + return -1;
>>>> + }
>>>> +#endif
>>>> +
>>>> + /*
>>>> + * XXX what about CTS/RTS
>>>> + */
>>>> +
>>>> + /* XXX */
>>>> +
>>>> + /*
>>>> + * Now write the registers
>>>> + */
>>>> +
>>>> + if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
>>>> + shift = MONGOOSEV_UART0_CMD_SHIFT;
>>>> + else
>>>> + shift = MONGOOSEV_UART1_CMD_SHIFT;
>>>> +
>>>> +
>>>> +
>>>> + rtems_interrupt_disable(Irql);
>>>> +
>>>> + cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REISTER );
>>>> +
>>>> + MG5UART_SETREG( pMG5UART,
>>>> + MG5UART_COMMAND_REGISTER,
>>>> + (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS <<
>>>>shift)) | (cmd << shift) );
>>>> +
>>>> + MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
>>>> +
>>>> + rtems_interrupt_enable(Irql);
>>>> + return 0;
>>>> +}
>>>> +
>>>> +/*
>>>> + * mg5uart_initialize_context
>>> + *
>>>> + * This function sets the default values of the per port context
>>>>structure.
>>>> + */
>>>> +
>>>> +MG5UART_STATIC void mg5uart_initialize_context(
>>>> + int minor,
>>>> + mg5uart_context *pmg5uartContext
>>>> +)
>>>> +{
>>>> + int port;
>>>> + unsigned int pMG5UART;
>>> + unsigned int pMG5UART_port;
>>>> +
>>>> + pMG5UART = Console_Port_Tbl[minor]->uCtrlPort1;
>>>> + pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
>>>> +
>>>> + pmg5uatContext->mate = -1;
>>>> +
>>>> + for (port=0 ; port<Console_Port_Count ; port++ )
>>>> + if ( Console_Port_Tbl[port]->ulCtrlPort1 == pMG5UART &&
>>>> + Conole_Port_Tbl[port]->ulCtrlPort2 != pMG5UART_port ) {
>>>> + pmg5uartContext->mate = port;
>>>> + break;
>>>> + }
>>>> + }
>>>> +
>>>> +}
>>>> +
>>>> +/*
>>>> + * mg5uart_init
>>>> + *
>>>> + * This function initializes the DUART to a quiecsent state.
>>>> + */
>>>> +
>>>> +MG5UART_STATIC void mg5uart_init(int minor)
>>>> +{
>>>> + uint32_t pMG5UART_port;
>>>> + uint32_t pMG5UART;
>>>> + uint32_t cmdSave;
>>>> + uint32_t shift;
>>>> +
>>>> + mg5uart_context *pmg5uartContext;
>>>> +
>>>> + pmg5uartContext = (mg5uart_contxt *)
>>>>malloc(sizeof(mg5uart_context));
>>>> +
>>>> + Console_Port_Data[minor].pDeviceContext = (void
>*)pmg5uartContext;
>>>> +
>>>> + mg5uart_initialize_context( minor, pmg5uartContext );
>>>> +
>>>> + pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
>>>> + pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
>>>> +
>>>> + if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
>>>> + shift = MONGOOSEV_UART0_CMD_SHIFT;
>>>> + else
>>>> + shift = MONGOOSEV_UART1_CMD_SHIFT;
>>>> +
>>>> + /*
>>>> + * Disable the uart and leave this port disabled.
>>>> + */
>>>> +
>>>> + cmdSave = MG5UART_GETREG(pMG5UART, MG5UART_COMMAND_REGISTER) &
>>>>~(MONGOOSEV_UART_ALL_STATUS_BITS << shift);
>>>> +
>>>> + MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmdSave );
>>>> +
>>>> + /*
>>>> + * Disable interrupts on RX and TX for this port
>>>> + */
>>>> + mg5uart_enable_interrupts( minor, MG5UART_DISABLE_ALL );
>>>> +}
>>>> +
>>>> +/*
>>>> + * mg5uart_open
>>>> + *
>>>> + * This function opens a port for communication.
>>>> + *
>>>> + * Default state is 9600 baud, 8 bits, No parity, and 1 stop bit.
>>>> + */
>>>> +
>>>> +MG5UART_STATIC int mg5uart_open(
>>>> + int major,
>>>> + int minor,
>>>> + void *arg
>>>> +)
>>>> +{
>>>> + uint32_t pMG5UART;
>>>> + uint32_t pMG5UART_port;
>>>> + uint32_t vector;
>>>> + uint32_t cmd, cmdSave;
>>>> + uint32_t baudcmd;
>>>> + uint32_t shift;
>>>> +
>>>> + rtems_interrupt_level Irql;
>>>> +
>>>> + pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
>>>> + pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
>>>> + vector = Console_Port_Tbl[minor]->ulIntVector;
>>>> +
>>>> + if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
>>>> + shift = MONGOOSEV_UART0_CMD_SHIFT;
>>>> + else
>>>> + shift = MONGOOSEV_UART1_CMD_SHIFT;
>>>> +
>>>> +
>>>> + /* XXX default baud rate could be from configuration table */
>>>> +
>>>> + (void) mg5uart_baud_rate( minor, B19200, &baudcmd );
>>>> +
>>>> + /*
>>>> + * Set the DUART channel to a default useable state
>>>> + * B19200, 8Nx since there is no stop bit control.
>>>> + */
>>>> +
>>>> + cmd = MONGOOSEV_UART_CMD_TX_ENABLE |
>MONGOOSEV_UART_CMD_RX_ENABLE;
>>>> +
>>>> + rtems_interrupt_disable(Irql);
>>>> +
>>>> + cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
>>>> +
>>>> + MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
>>>> +
>>>> + MG5URT_SETREG( pMG5UART,
>>>> + MG5UART_COMMAND_REGISTER,
>>>> + cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS
><<
>>>>shift)) | (cmd << shift) );
>>>> +
>>>> + rtems_interrupt_enable(Irql);
>>>> +
>>>> + return RTEMS_SUCCESSFUL;
>>>> +}
>>>> +
>>>> +/*
>>>> + * mg5uart_close
>>>> + *
>>>> + * This function shuts down the requested port.
>>>> + */
>>>> +
>>>> +MG5UART_STATIC int mg5uart_close(
>>>> + int major,
>>>> + int minor,
>>>> + void *arg
>>>> +)
>>>> +{
>>>> + uint32_t pMG5UART;
>>>> + uint32_t pMG5UART_port;
>>>> + uint32_t cmd, cmdSave;
>>>> + uint32_t shift;
>>>> + rtems_interrupt_level Irql;
>>>> +
>>>> + pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
>>>> + pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
>>>> +
>>>> + /*
>>>> + * Disable interrupts from this channel and then disable it
>>>>totally.
>>>> + */
>>>> +
>>>> + /* XXX interrupts */
>>>> +
>>>> + cmd = MONGOOSEV_UART_CMD_TX_DISABLE |
>MONGOOSEV_UART_CMD_RX_DISABLE;
>>>> +
>>>> + if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
>>>> + shift = MONGOOSEV_UART0_CMD_SHIFT;
>>>> + else
>>>> + shift = MONGOOSEV_UART1_CMD_SHIFT;
>>>> +
>>>> +
>>>> + rtems_interrupt_disable(Irql);
>>>> + cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
>>>> +
>>>> + MG5UART_SETREG( pMG5UART,
>>>> + MG5UART_COMMAND_REGISTER,
>>>> + (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS <<
>>>>shift)) | (cmd << shift) );
>>>> + rtems_interrupt_enable(Irql);
>>>> +
>>>> + return(RTEMS_SUCCESSFUL);
>>>> +}
>>>> +
>>>> +
>>>> +
>>>> +
>>>> +/*
>>>> + * mg5uart_write_polled
>>>> + *
>>>> + * This routine polls out the requested character.
>>>> + */
>>>> +
>>>> +MG5UART_STATIC void mg5uart_write_polled(
>>>> + int minor,
>>>> + char c
>>>> +)
>>>> +{
>>>> + uint32_t pMG5UART;
>>>> + uint32_t pMG5UART_port;
>>>> + uint32_t status;
>>>> + int shift;
>>>> + int timeout;
>>>> +
>>>> + pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
>>>> + pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
>>>> +
>>>> + if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
>>>> + shift = MONGOOSEV_UART0_IRQ_SHIFT;
>>>> + else
>>>> + shift = MONGOOSEV_UART1_IRQ_SHIFT;
>>>> +
>>>> + /*
>>>> + * wait for transmitter holding register to be empty
>>>> + */
>>>> + timeout = 2000;
>>>> +
>>>> + while( --timeout )
>>>> + {
>>>> + status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >>
>>>>shift;
>>>> +
>>>> + *
>>>> + if ( (status & (MONGOOSEV_UART_TX_READY |
>>>>MONGOOSEV_UART_TX_EMPTY)) ==
>>>> + (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY) )
>>>> + break;
>>>> + */
>>>> +
>>>> + if((status & (MONGOOSEV_UART_TX_READY |
>>>>MONGOOSEV_UART_TX_EMPTY)) )
>>>> + break;
>>>> +
>>>> + /*
>>>> + * Yield while we wait
>>>> + */
>>>> +
>>>> +#if 0
>>>> + if(_System_state_Is_up(_System_state_Get()))
>>>> + {
>>>> + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
>>>> + }
>>>> +#endif
>>>> + }
>>>> +
>>>> + /*
>>>> + * transmit character
>>>> + */
>>>> +
>>>> + MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, c);
>>>> +}
>>>> +
>>>> +MG5UART_STATIC void mg5uart_process_isr_rx_error(
>>>> + int minor,
>>>> + uint32_t mask
>>>> +)
>>>> +{
>>>> + uint32_t pMG5UART;
>>>> + int shift;
>>>> +
>>>> + pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
>>>> +
>>>> + if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
>>>> + shift = MONGOOSEV_UART0_IRQ_SHIFT;
>>>> + else
>>>> + shift = MONGOOSEV_UART1_IRQ_SHIFT;
>>>> +
>>>> + /* now clear the error */
>>>> +
>>>> + MG5UART_SETREG(
>>>> + pMG5UART,
>>>> + MG5UART_STATUS_REGISTER,
>>>> + mask << shift );
>>>> +}
>>>> +
>>>> +
>>>> +MG5UART_STATIC void mg5uart_process_isr_rx_frame_error(
>>>> + int minor
>>>> +)
>>>> +{
>>>> + mg5uart_process_isr_rx_error( minor,
>MONGOOSEV_UART_RX_FRAME_ERROR
>>>>);
>>>> +}
>>>> +
>>>> +MG5UART_STATIC void mg5uart_process_isr_rx_overrun_error(
>>>> + int minor
>>>> +)
>>>> +{
>>>> + mg5uart_process_isr_rx_error( minor,
>>>>MONGOOSEV_UART_RX_OVERRUN_ERROR );
>>> +}
>>>> +
>>>> +
>>>> +
>>>> +
>>>> +
>>>> +
>>>> +
>>>> +
>>>> +MG5UART_STATIC void m5uart_process_tx_isr(
>>>> + int minor,
>>>> + uint32_t source
>>>> +)
>>>> +{
>>>> + uint32_t pMG5UART;
>>>> + int shift;
>>>> +
>>>> + pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
>>>> +
>>>> + mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
>>>> +
>>>> + if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
>>>> + shift = MONGOOSEV_UART0_IRQ_SHIFT;
>>>> + else
>>>> + shift = MONGOOSEV_UART1_IRQ_SHIFT;
>>>> +
>>>> + MG5UART_SETREG(
>>>> + pMG5UART,
>>>> + MG5UART_STATUS_REGISTER,
>>>> + source << shift );
>>>> +
>>>> + if( rtems_termios_dequeue_characters(
>>>>Console_Port_Data[minor].termios_data, 1) )
>>>> + {
>>>> + mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL);
>>>> + return;
>>>> + }
>>>> +
>>>> + /*
>>>> + * There are no more characters to transmit. The tx
>interrupts
>>>>are be cleared
>>>> + * by writing data to the uart, so just disable the tx
>interrupt
>>>>sources.
>>>> + */
>>>> +
>>>> + Console_Port_Data[minor].bActive = FALSE;
>>>> +
>>>> + /* mg5uart_enable_interrupts(minor,
>MG5UART_ENABLE_ALL_EXCEPT_TX);
>>>>*/
>>>> +}
>>>> +
>>>> +
>>>> +
>>>> +MG5UART_STATIC void mg5uart_process_isr_tx_empty(
>>>> + int minor
>>>> +)
>>>> +{
>>>> + /* mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_EMPTY ); */
>>>> +}
>>>> +
>>>> +MG5UART_STATIC void mg5uart_process_isr_tx_ready(
>>>> + int minor
>>>> +)
>>>> +{
>>>> + mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_READY );
>>>> +}
>>>> +
>>>> +
>>>> +
>>>> +
>>>> +
>>>> +MG5UART_STATIC void mg5uart_process_isr_rx_ready(
>>>> + int minor
>>>> +)
>>>> +{
>>>> + uint32_t pMG5UART_port;
>>>> + char c;
>>>> +
>>>> + pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
>>>> +
>>>> + /* reading the RX buffer automatically resets the interrupt flag
>*/
>>>> +
>>>> + c = (char) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
>>>> +
>>>> + rtems_termios_enqueue_raw_characters(
>>>> + Console_Port_Data[minor].termios_data,
>>>> + &c, 1 ;
>>>> +}
>>>> +
>>>> +static rtems_irq_connect_data mg5uart_rx_frame_error_cd = { \
>>> + 0, /* filled in at initialization */
>>>> + mg5uart_isr_rx_frame_error, /* filled in at initialization */
>>>> + NULL, /* (void *) minor */
>>>> + NULL,
>>>> + NULL,
>>>> + NULL
>>>> +};
>>>> +
>>>> +static rtems_irq_connect_data mg5uart_rx_overrun_error_cd = { \
>>>> + 0, /* filled in at initialization */
>>>> + mg5uart_isr_rx_overrun_error, /* filled in at initialization
>*/
>>>> + NULL, /* (void *) minor */
>>>> + NULL,
>>>> + NULL,
>>>> + NULL
>>>> +};
>>>> +
>>>> +static rtems_irq_connect_data mg5uart_tx_empty_cd = { \
>>>> + 0, /* filled in at initializaion */
>>>> + mg5uart_isr_tx_empty, /* filled in at initialization */
>>>> + NULL,id *) minor */
>>>> + NULL,
>>>> + NULL,
>>>> + NULL
>>>> +};
>>>> +
>>>> +static rtems_irq_connect_data mg5uart_tx_ready_cd = { \
>>>> + 0, /* filled in at initialization */
>>>> + mg5uart_isr_tx_ready, /* filled in at initialization */
>>>> + NULL, /* (void *) minor */
>>>> + NULL,
>>>> + NULL,
>>>> NULL
>>>> +};
>>>> +
>>>> +static rtems_irq_connect_data mg5uart_rx_ready_cd = { \
>>>> + 0, /* filled in at initialization */
>>>> + mg5uart_isr_rx_ready, /* filled in at initialization */
>>>> + NULL, /* (void *) minor */
>>>> + NULL,
>>>> + NULL,
>>>> + NUL
>>>> +};
>>>> +
>>>> +
>>>> +/*
>>>> + * mg5uart_initialize_interrupts
>>>> + *
>>>> + * This routine initializes the console's receive and transmit
>>>> + * ring buffers and loads the appropriate vectors to handle the
>>>>interrupts.
>>>> + */
>>>> +
>>>> +MG5UART_STATIC void mg5uart_initialize_interrupts(int minor)
>>>> +{
>>>> + unsigned long v;
>>>> + mg5uart_init(minor);
>>>> +
>>>> + Console_Port_Data[minor].bActive = FALSE;
>>>> + v = Console_Port_Tbl[minor]->ulIntVector;
>>>> +
>>>> + mg5uart_rx_frame_error_cd.name = v +
>MG5UART_IRQ_RX_FRAME_ERROR;
>>>> + mg5uart_rx_overrun_error_cd.name = v +
>>>>MG5UART_IRQ_RX_OVERRUN_ERROR;
>>>> + mg5uart_tx_empty_cd.name = v + MG5UART_IRQ_TX_EMPTY;
>>>> + mg5uart_tx_ready_cd.name = v + MG5UART_IRQ_TX_READY;
>>>> + mg5uart_rx_ready_cd.name = v + MG5UART_IRQ_RX_READY;
>>>> +
>>>> + mg5uart_rx_frame_error_cd.handle = (void
>>>>*)mg5uart_rx_frame_error_cd.name;
>>>> + mg5uart_rx_overrun_error_cd.handle = (void
>>>>*)mg5uart_rx_overrun_error_cd.name;
>>>> + mg5uart_tx_empty_cd.handle = (void
>>>>*)mg5uart_tx_empty_cd.name;
>>>> + mg5uart_tx_ready_cd.handle = (void
>>>>*)mg5uart_tx_ready_cd.name;
>>>> + mg5uart_rx_ready_cd.handle = (void
>>>>*)mg5uart_rx_ready_cd.name;
>>>> +
>>>> +
>>>> + BSP_install_rtems_irq_handler( &mg5uart_rx_frame_error_cd );
>>>> + BSP_install_rtems_irq_handler( &mg5uart_rx_overrun_error_cd );
>>>> + BSP_install_rtems_irq_handler( &mg5uart_tx_empty_cd );
>>>> + BSP_install_rtems_irq_handler( &mg5uart_tx_ready_cd );
>>>> + BSP_istall_rtems_irq_handler( &mg5uart_rx_ready_cd );
>>>> +
>>>> + mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
>>>> +}
>>>> +
>>>> +/*
>>>> + * mg5uart_write_support_int
>>>> + *
>>>> + * Console Termios output entry point when using interrupt driven
>>>>output.
>>>> + */
>>>> +
>>>> +MG5UART_STATIC int mg5uart_write_support_int(
>>>> + int minor,
>>>> + const char *buf,
>>>> + size_t len
>>>> +)
>>>> +{
>>>> + uint32_t pMG5UART
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