Re: [apache/tvm-rfcs] [RFC] UMA Universal Modular Accelerator Interface (PR #60)
@cgerum thanks for detailed analysis! Im wondering whether should we provide an optional partitioning hook as well -- so then it can be anything and let the default be a Sequential of MergeComposite, AnnotateTarget, MergeCompilerRegions, ParititionGraph. WDYT ? -- Reply to this email directly or view it on GitHub: https://github.com/apache/tvm-rfcs/pull/60#issuecomment-1067853618 You are receiving this because you are subscribed to this thread. Message ID:
Re: [apache/tvm] [RFC][Tracking Issue] Pipeline Executor For Compute graph pipeline (#8596)
> thanks @masahi for the follow up, I am also looking forward a chance to do a > demo after all patch upstream done. Hi @huajsj, do you have any plan to do a demo with compiling deep learning models such as [https://tvm.apache.org/docs/how_to/compile_models/from_tensorflow.html#sphx-glr-how-to-compile-models-from-tensorflow-py](url)? -- Reply to this email directly or view it on GitHub: https://github.com/apache/tvm/issues/8596#issuecomment-1067928253 You are receiving this because you are subscribed to this thread. Message ID:
[Apache TVM Discuss] [Meetup] Next TVM Community Meeting March 16
Looks like we have one agenda item for tomorrow: Type-directed Relay fuzzing library. Let's plan to meet to discuss this one. --- [Visit Topic](https://discuss.tvm.apache.org/t/next-tvm-community-meeting-march-16/12298/2) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/fb9c36c81b7be08f2e7ad6d74e3fb9b4962d532b551d667d5ff605c31c44d400).
[Apache TVM Discuss] [Development/pre-RFC] [RFC] Verification and (possibly) program synthesis of expression rewriting rules
Currently, TVM uses the following way to define expression simplifying rules:
https://github.com/apache/tvm/blob/f5e0c102057641d88f06ad865d5a1d4e99bd70d7/src/arith/rewrite_simplify.cc
This approach is error-prone and not scalable:
1. The rewrite rules were added manually, the number of possible rewriting
rules might be too large and not maintainable.
2. Lack verification of rewriting rules, we only have unittests: which can not
cover all possible cases.
3. The order of rewrite matters, which is not considered here.
For 2, we can use existing SMT solvers such as Z3, for the issue introduced in
https://github.com/apache/tvm/pull/10610, we can try finding a counter-example
with Z3:
```python
>>> from z3 import *
>>> x = BitVec('x', 32)
>>> y = BitVec('y', 32)
>>> c1 = BitVec('c1', 32)
>>> c2 = BitVec('c2', 32)
>>> solve(x > 0, y > 0, c1 > 0, c2 > 0, c2 % c1 == 0, (x * c1 + y) % c2 != (x %
>>> (c2 / c1)) * c1 + y, y < c1)
[y = 79521, x = 201523190, c1 = 1909062, c2 = 1956788550]
```
where `BitVec(..., 32)` means int32.
We can write tests for all these rewriting rules either on C++ side or Python
side.
How to automatically generate rewrite rules remains a research problem, program
synthesis ([rosette](https://github.com/emina/rosette)) and equality saturation
([egg](https://github.com/egraphs-good/egg),
[ruler](https://github.com/uwplse/ruler)) might help here. However, we need to
define the optimization target of rewriting (make it simpler? can we formulate
the level of "simple"? etc).
---
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[Apache TVM Discuss] [Development/pre-RFC] [RFC] Verification and (possibly) program synthesis of expression rewriting rules
Halide people did something like that https://dl.acm.org/doi/10.1145/3428234 --- [Visit Topic](https://discuss.tvm.apache.org/t/rfc-verification-and-possibly-program-synthesis-of-expression-rewriting-rules/12319/2) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/f17100a147374ff4826ce9136cf809e6e6b14c7c1ff20506b18aaa67cb3d952f).
