Re: [PATCH 3/3] ethdev: import and export data variables for MSVC
On Tue, 12 Mar 2024 00:51:48 -0700 Tyler Retzlaff wrote: > diff --git a/lib/ethdev/rte_ethdev_export.h b/lib/ethdev/rte_ethdev_export.h > new file mode 100644 > index 000..7887bee > --- /dev/null > +++ b/lib/ethdev/rte_ethdev_export.h > @@ -0,0 +1,23 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2024 Microsoft Corporation > + */ > + > +#ifndef _RTE_ETHDEV_EXPORT_H_ > +#define _RTE_ETHDEV_EXPORT_H_ > + > +/** > + * @file > + * > + * Import / Export macros for ethdev data variables. > + */ > + > +#include > + > +#ifndef __rte_ethdev_export > +#define __rte_ethdev_export __rte_declare_import > +#else > +#undef __rte_ethdev_export > +#define __rte_ethdev_export __rte_declare_export > +#endif > + > +#endif Why not put this in rte_ethdev_core.h rather than a new file?? Patch needs to be resubmitted anyway because it fails github build from missing C++ guards.
RE: [PATCH] eal/x86: cache queried CPU flags
> > Hi Bruce, > > Why x86/rte_cpuflags.c is not using rte_getauxval() ? > > I don't see any such DPDK function, unless I'm missing something? I do see a > linux function which includes hw capability flags. I suspect the reasons we > don't use that are: > > 1. Lack of awareness of it (at least on my end! :-)) 2. Originally when we > added > flags for new instruction sets we may have >needed to support their detection on platforms where the kernel/libc was >too old to be aware of them. > 3. It's linux only, so we'd still need these cpuid calls for other OS's >anyway. > > Therefore, I don't see any benefit in using that function over what we do now. > Is there some benefit that you see that makes you think it would be > worthwhile switching? > Agree, all these are good reasons to avoid it. getauxval() reads these values from process stack (ELF loader places it there), so it's a relatively fast way of finding cpu features. I'm wondering if a similar mechanism is available in FreeBSD and Windows. If so, it might be beneficial to have a common API for such functions. But as you mentioned, if the kernel isn't aware of the feature it may fail.
Re: [PATCH 00/16] remove use of VLAs for Windows built code
On Wed, 17 Apr 2024 16:41:43 -0700 Tyler Retzlaff wrote: > As per guidance technical board meeting 2024/04/17. This series > removes the use of VLAs from code built for Windows for all 3 > toolchains. If there are additional opportunities to convert VLAs > to regular C arrays please provide the details for incorporation > into the series. > > MSVC does not support VLAs, replace VLAs with standard C arrays > or alloca(). alloca() is available for all toolchain/platform > combinations officially supported by DPDK. > > Tyler Retzlaff (16): > eal: include header required for alloca > hash: remove use of VLAs for Windows built code > ethdev: remove use of VLAs for Windows built code > gro: remove use of VLAs for Windows built code > latencystats: remove use of VLAs for Windows built code > lpm: remove use of VLAs for Windows built code > rcu: remove use of VLAs for Windows built code > app/testpmd: remove use of VLAs for Windows built code > test: remove use of VLAs for Windows built code > common/idpf: remove use of VLAs for Windows built code > net/i40e: remove use of VLAs for Windows built code > net/ice: remove use of VLAs for Windows built code > net/ixgbe: remove use of VLAs for Windows built code > common/mlx5: remove use of VLAs for Windows built code > net/mlx5: remove use of VLAs for Windows built code > build: enable vla warnings on Windows built code > > app/test-pmd/cmdline.c| 2 +- > app/test-pmd/cmdline_flow.c | 9 +++-- > app/test-pmd/config.c | 16 + > app/test-pmd/shared_rxq_fwd.c | 2 +- > app/test/test.c | 2 +- > app/test/test_cmdline_string.c| 2 +- > app/test/test_cryptodev.c | 32 +- > app/test/test_cryptodev_blockcipher.c | 4 +-- > app/test/test_cryptodev_crosscheck.c | 2 +- > app/test/test_dmadev.c| 9 +++-- > app/test/test_hash.c | 8 ++--- > app/test/test_mempool.c | 25 +++--- > app/test/test_reassembly_perf.c | 4 +-- > app/test/test_reorder.c | 48 > +++ > app/test/test_service_cores.c | 9 +++-- > app/test/test_thash.c | 7 ++-- > config/meson.build| 4 +++ > drivers/common/idpf/idpf_common_rxtx.c| 2 +- > drivers/common/idpf/idpf_common_rxtx_avx512.c | 6 ++-- > drivers/common/mlx5/mlx5_common.h | 4 +-- > drivers/common/mlx5/mlx5_devx_cmds.c | 7 ++-- > drivers/net/i40e/i40e_testpmd.c | 5 ++- > drivers/net/ice/ice_rxtx.c| 2 +- > drivers/net/ixgbe/ixgbe_ethdev.c | 5 +-- > drivers/net/ixgbe/ixgbe_rxtx_vec_common.h | 2 +- > drivers/net/mlx5/mlx5.c | 5 ++- > drivers/net/mlx5/mlx5_flow.c | 6 ++-- > lib/eal/linux/include/rte_os.h| 1 + > lib/eal/windows/include/rte_os.h | 1 + > lib/ethdev/rte_ethdev.c | 9 ++--- > lib/gro/rte_gro.c | 4 +-- > lib/hash/rte_cuckoo_hash.c| 4 +-- > lib/hash/rte_thash.c | 2 +- > lib/latencystats/rte_latencystats.c | 2 +- > lib/lpm/rte_lpm.h | 2 +- > lib/rcu/rte_rcu_qsbr.c| 6 ++-- > 36 files changed, 137 insertions(+), 123 deletions(-) Looks good: Series-Acked-by: Stephen Hemminger Series needs to be rebased to current master, some parts have changed.
Re: [PATCH v5] devtools: add .clang-format file
On Thu, 16 May 2024 08:20:51 +
Abdullah Ömer Yamaç wrote:
> clang-format is a tool to format C/C++/Objective-C code. It can be used
> to reformat code to match a given coding style, or to ensure that code
> adheres to a specific coding style. It helps to maintain a consistent
> coding style across the DPDK codebase.
>
> .clang-format file overrides the default style options provided by
> clang-format and large set of IDEs and text editors support it.
>
> Signed-off-by: Abdullah Ömer Yamaç
> ---
> .clang-format | 149 ++
> 1 file changed, 149 insertions(+)
> create mode 100644 .clang-format
>
> diff --git a/.clang-format b/.clang-format
> new file mode 100644
> index 00..5f86e1be79
> --- /dev/null
> +++ b/.clang-format
> @@ -0,0 +1,149 @@
> +---
> +BasedOnStyle: LLVM
Looks good but any new file in DPDK needs a SPDX license header.
Not sure why, but it seems to be indenting somethings to much.
Example:
Before clang-format:
static struct rte_vdev_driver pmd_pcap_drv = {
.probe = pmd_pcap_probe,
.remove = pmd_pcap_remove,
};
After clang-format:
static struct rte_vdev_driver pmd_pcap_drv = {
.probe = pmd_pcap_probe,
.remove = pmd_pcap_remove,
};
[PATCH v9] eal: add build-time option to omit trace
Some applications want to omit the trace feature.
Either to reduce the memory footprint, to reduce the exposed attack
surface, or for other reasons.
This patch adds an option in rte_config.h to include or omit trace in the
build. Trace is included by default.
Omitting trace works by omitting all trace points.
For API and ABI compatibility, the trace feature itself remains.
Furthermore, a public function to determine if trace is build time enabled
is added; mainly for the benefit of the dpdk-test application.
Signed-off-by: Morten Brørup
Acked-by: Stephen Hemminger
Acked-by: Jerin Jacob
---
v9:
* Assume library and application are built with same rte_config.h.
* Renamed internal function __rte_trace_point_generic_is_enabled() to
rte_trace_feature_is_enabled(), which is public. (Jerin Jacob)
* Removed changes that became superfluous with the above change.
v8:
* Added Stephen's Ack to v4, forgot to carry over.
v7:
* Updated version.map to not export __rte_trace_feature_is_enabled for
Windows target.
v6:
* Removed test_trace_perf.c changes; they don't compile for Windows
target, and are superfluous.
v5:
* Added public function rte_trace_feature_is_enabled(), to test if trace
is build time enabled in both the DPDK and the application. Use in test
application instead of private function. (Jerin Jacob)
v4:
* Added check for generic trace enabled when registering trace points, in
RTE_INIT. (Jerin Jacob)
* Test application uses function instead of macro to check if generic
trace is enabled. (Jerin Jacob)
* Performance test application uses function to check if generic trace is
enabled.
v3:
* Simpler version with much fewer ifdefs. (Jerin Jacob)
v2:
* Added/modified macros required for building applications with trace
omitted.
---
app/test/test_trace.c | 4
config/rte_config.h| 1 +
lib/eal/include/rte_trace.h| 19 +++
lib/eal/include/rte_trace_point.h | 3 +++
lib/eal/include/rte_trace_point_register.h | 2 ++
5 files changed, 29 insertions(+)
diff --git a/app/test/test_trace.c b/app/test/test_trace.c
index 00809f433b..8ea1443044 100644
--- a/app/test/test_trace.c
+++ b/app/test/test_trace.c
@@ -245,6 +245,10 @@ static struct unit_test_suite trace_tests = {
static int
test_trace(void)
{
+ if (!rte_trace_feature_is_enabled()) {
+ printf("Trace omitted at build-time, skipping test\n");
+ return TEST_SKIPPED;
+ }
return unit_test_suite_runner(&trace_tests);
}
diff --git a/config/rte_config.h b/config/rte_config.h
index dd7bb0d35b..fd6f8a2f1a 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -49,6 +49,7 @@
#define RTE_MAX_TAILQ 32
#define RTE_LOG_DP_LEVEL RTE_LOG_INFO
#define RTE_MAX_VFIO_CONTAINERS 64
+#define RTE_TRACE 1
/* bsd module defines */
#define RTE_CONTIGMEM_MAX_NUM_BUFS 64
diff --git a/lib/eal/include/rte_trace.h b/lib/eal/include/rte_trace.h
index a6e991fad3..6eac95188b 100644
--- a/lib/eal/include/rte_trace.h
+++ b/lib/eal/include/rte_trace.h
@@ -35,6 +35,25 @@ extern "C" {
__rte_experimental
bool rte_trace_is_enabled(void);
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
+ *
+ * Test if trace feature is enabled at compile time.
+ *
+ * @return
+ * true if trace feature is enabled, false otherwise.
+ */
+static __rte_always_inline
+bool rte_trace_feature_is_enabled(void)
+{
+#ifdef RTE_TRACE
+ return true;
+#else
+ return false;
+#endif
+}
+
/**
* Enumerate trace mode operation.
*/
diff --git a/lib/eal/include/rte_trace_point.h
b/lib/eal/include/rte_trace_point.h
index 41e2a7f99e..dfe89302ed 100644
--- a/lib/eal/include/rte_trace_point.h
+++ b/lib/eal/include/rte_trace_point.h
@@ -30,6 +30,7 @@ extern "C" {
#include
#include
#include
+#include
#include
/** The tracepoint object. */
@@ -359,6 +360,8 @@ __rte_trace_point_emit_ev_header(void *mem, uint64_t in)
#define __rte_trace_point_emit_header_generic(t) \
void *mem; \
do { \
+ if (!rte_trace_feature_is_enabled()) \
+ return; \
const uint64_t val = rte_atomic_load_explicit(t,
rte_memory_order_acquire); \
if (likely(!(val & __RTE_TRACE_FIELD_ENABLE_MASK))) \
return; \
diff --git a/lib/eal/include/rte_trace_point_register.h
b/lib/eal/include/rte_trace_point_register.h
index 41260e5964..283dcef75d 100644
--- a/lib/eal/include/rte_trace_point_register.h
+++ b/lib/eal/include/rte_trace_point_register.h
@@ -23,6 +23,8 @@ rte_trace_point_t __rte_section("__rte_trace_point")
__##trace; \
static const char __##trace##_name[] = RTE_STR(name); \
RTE_INIT(trace##_init) \
{ \
+ if (!rte_trace_feature_is_enabled()) \
+ return; \
__rte_trace_point_register(&__##trace, __##trace##_name, \
(void (*)(void)) trace); \
}
--
2.43.0
RE: [PATCH] eal/x86: cache queried CPU flags
> On Mon, Oct 7, 2024 at 1:07 PM Bruce Richardson > wrote: > > > > Rather than re-querying the HW each time a CPU flag is requested, we > > can just save the return value in the flags array. This should speed > > up repeated querying of CPU flags, and provides a workaround for a > > reported issue where errors are seen with constant querying of the > > AVX-512 CPU flag from a non-AVX VM. > > This could be applied to other arches cpuflag implementation. > Copying other arches maintainers as a fyi. > +1
Re: [PATCH] bus/pci: don't open uio device in secondary process
On Wed, 28 Aug 2024 12:40:02 +0200
Konrad Sztyber wrote:
> The uio_pci_generic driver clears the bus master bit when the device
> file is closed. So, when the secondary process terminates after probing
> a device, that device becomes unusable in the primary process.
>
> To avoid that, the device file is now opened only in the primary
> process. The commit that introduced this regression, 847d78fb95
> ("bus/pci: fix FD in secondary process"), only mentioned enabling access
> to config space from secondary process, which still works, as it doesn't
> rely on the device file.
>
> Fixes: 847d78fb95 ("bus/pci: fix FD in secondary process")
>
> Signed-off-by: Konrad Sztyber
Wouldn't this break use of interrupts in the secondary process?
The patch does need the minor fix of the comment style.
So resubmit
Re: [PATCH v2 1/2] net/sxe: add net driver sxe
On Fri, 6 Sep 2024 10:09:30 +0800 Jie Liu wrote: > diff --git a/drivers/net/sxe/Makefile b/drivers/net/sxe/Makefile > new file mode 100644 > index 00..5e2870fdc4 > --- /dev/null > +++ b/drivers/net/sxe/Makefile DPDK does not use make anymore, please remove this from next version.
[PATCH v2 2/3] ethdev: make parameters to TM profile add fn constant
The function to add a new profile in rte_tm should not (and does not)
modify the profile parameters passed in via struct pointer. We should
guarantee this by marking the parameter pointer as const. This allows
SW to create multiple profiles using the same parameter struct without
having to reset it each time.
Signed-off-by: Bruce Richardson
Reviewed-by: Rosen Xu
Acked-by: Ferruh Yigit
---
drivers/net/ipn3ke/ipn3ke_tm.c | 4 ++--
lib/ethdev/rte_tm.c| 2 +-
lib/ethdev/rte_tm.h| 2 +-
lib/ethdev/rte_tm_driver.h | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ipn3ke/ipn3ke_tm.c b/drivers/net/ipn3ke/ipn3ke_tm.c
index cffe1fdaa4..20a0ed0467 100644
--- a/drivers/net/ipn3ke/ipn3ke_tm.c
+++ b/drivers/net/ipn3ke/ipn3ke_tm.c
@@ -848,7 +848,7 @@ ipn3ke_tm_shaper_profile_delete(struct rte_eth_dev *dev,
static int
ipn3ke_tm_tdrop_profile_check(__rte_unused struct rte_eth_dev *dev,
- uint32_t tdrop_profile_id, struct rte_tm_wred_params *profile,
+ uint32_t tdrop_profile_id, const struct rte_tm_wred_params *profile,
struct rte_tm_error *error)
{
enum rte_color color;
@@ -931,7 +931,7 @@ ipn3ke_hw_tm_tdrop_wr(struct ipn3ke_hw *hw,
/* Traffic manager TDROP profile add */
static int
ipn3ke_tm_tdrop_profile_add(struct rte_eth_dev *dev,
- uint32_t tdrop_profile_id, struct rte_tm_wred_params *profile,
+ uint32_t tdrop_profile_id, const struct rte_tm_wred_params *profile,
struct rte_tm_error *error)
{
struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
diff --git a/lib/ethdev/rte_tm.c b/lib/ethdev/rte_tm.c
index 74e6f4d610..d221b1e553 100644
--- a/lib/ethdev/rte_tm.c
+++ b/lib/ethdev/rte_tm.c
@@ -153,7 +153,7 @@ int rte_tm_node_capabilities_get(uint16_t port_id,
/* Add WRED profile */
int rte_tm_wred_profile_add(uint16_t port_id,
uint32_t wred_profile_id,
- struct rte_tm_wred_params *profile,
+ const struct rte_tm_wred_params *profile,
struct rte_tm_error *error)
{
struct rte_eth_dev *dev = &rte_eth_devices[port_id];
diff --git a/lib/ethdev/rte_tm.h b/lib/ethdev/rte_tm.h
index c52acd1b4f..f6f3f6a8d4 100644
--- a/lib/ethdev/rte_tm.h
+++ b/lib/ethdev/rte_tm.h
@@ -1347,7 +1347,7 @@ rte_tm_node_capabilities_get(uint16_t port_id,
int
rte_tm_wred_profile_add(uint16_t port_id,
uint32_t wred_profile_id,
- struct rte_tm_wred_params *profile,
+ const struct rte_tm_wred_params *profile,
struct rte_tm_error *error);
/**
diff --git a/lib/ethdev/rte_tm_driver.h b/lib/ethdev/rte_tm_driver.h
index 25d688516b..b6ecf1bd4d 100644
--- a/lib/ethdev/rte_tm_driver.h
+++ b/lib/ethdev/rte_tm_driver.h
@@ -51,7 +51,7 @@ typedef int (*rte_tm_node_capabilities_get_t)(struct
rte_eth_dev *dev,
/** @internal Traffic manager WRED profile add */
typedef int (*rte_tm_wred_profile_add_t)(struct rte_eth_dev *dev,
uint32_t wred_profile_id,
- struct rte_tm_wred_params *profile,
+ const struct rte_tm_wred_params *profile,
struct rte_tm_error *error);
/** @internal Traffic manager WRED profile delete */
--
2.43.0
[PATCH v2 1/3] ethdev: make parameters to TM node add fn constant
The function to add a new scheduling node in rte_tm should not (and
does not) modify the actual node parameters passed in via struct
pointer. We should guarantee this by marking the parameter pointer as
const. This allows SW to create multiple scheduling nodes using the same
parameter struct without having to reset it each time.
Signed-off-by: Bruce Richardson
Reviewed-by: Rosen Xu
Acked-by: Ferruh Yigit
---
drivers/net/cnxk/cnxk_tm.c | 2 +-
drivers/net/dpaa2/dpaa2_tm.c| 4 ++--
drivers/net/hns3/hns3_tm.c | 16
drivers/net/i40e/i40e_tm.c | 6 +++---
drivers/net/iavf/iavf_tm.c | 6 +++---
drivers/net/ice/ice_dcf_sched.c | 6 +++---
drivers/net/ice/ice_tm.c| 6 +++---
drivers/net/ipn3ke/ipn3ke_tm.c | 4 ++--
drivers/net/ixgbe/ixgbe_tm.c| 6 +++---
drivers/net/txgbe/txgbe_tm.c| 6 +++---
lib/ethdev/rte_tm.c | 2 +-
lib/ethdev/rte_tm.h | 2 +-
lib/ethdev/rte_tm_driver.h | 2 +-
13 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_tm.c b/drivers/net/cnxk/cnxk_tm.c
index c799193cb8..9293b3e8f2 100644
--- a/drivers/net/cnxk/cnxk_tm.c
+++ b/drivers/net/cnxk/cnxk_tm.c
@@ -336,7 +336,7 @@ static int
cnxk_nix_tm_node_add(struct rte_eth_dev *eth_dev, uint32_t node_id,
uint32_t parent_node_id, uint32_t priority,
uint32_t weight, uint32_t lvl,
-struct rte_tm_node_params *params,
+const struct rte_tm_node_params *params,
struct rte_tm_error *error)
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
diff --git a/drivers/net/dpaa2/dpaa2_tm.c b/drivers/net/dpaa2/dpaa2_tm.c
index cb854964b4..22337097e5 100644
--- a/drivers/net/dpaa2/dpaa2_tm.c
+++ b/drivers/net/dpaa2/dpaa2_tm.c
@@ -359,7 +359,7 @@ static int
dpaa2_node_check_params(struct rte_eth_dev *dev, uint32_t node_id,
__rte_unused uint32_t priority, uint32_t weight,
uint32_t level_id,
- struct rte_tm_node_params *params,
+ const struct rte_tm_node_params *params,
struct rte_tm_error *error)
{
if (node_id == RTE_TM_NODE_ID_NULL)
@@ -431,7 +431,7 @@ dpaa2_node_check_params(struct rte_eth_dev *dev, uint32_t
node_id,
static int
dpaa2_node_add(struct rte_eth_dev *dev, uint32_t node_id,
uint32_t parent_node_id, uint32_t priority, uint32_t weight,
- uint32_t level_id, struct rte_tm_node_params *params,
+ uint32_t level_id, const struct rte_tm_node_params *params,
struct rte_tm_error *error)
{
struct dpaa2_dev_priv *priv = dev->data->dev_private;
diff --git a/drivers/net/hns3/hns3_tm.c b/drivers/net/hns3/hns3_tm.c
index 92a668538f..06df32bbcd 100644
--- a/drivers/net/hns3/hns3_tm.c
+++ b/drivers/net/hns3/hns3_tm.c
@@ -329,7 +329,7 @@ hns3_tm_node_search(struct rte_eth_dev *dev,
static int
hns3_tm_nonleaf_node_param_check(struct rte_eth_dev *dev,
-struct rte_tm_node_params *params,
+const struct rte_tm_node_params *params,
struct rte_tm_error *error)
{
struct hns3_tm_shaper_profile *shaper_profile;
@@ -364,7 +364,7 @@ hns3_tm_nonleaf_node_param_check(struct rte_eth_dev *dev,
static int
hns3_tm_leaf_node_param_check(struct rte_eth_dev *dev __rte_unused,
- struct rte_tm_node_params *params,
+ const struct rte_tm_node_params *params,
struct rte_tm_error *error)
{
@@ -408,7 +408,7 @@ hns3_tm_leaf_node_param_check(struct rte_eth_dev *dev
__rte_unused,
static int
hns3_tm_node_param_check(struct rte_eth_dev *dev, uint32_t node_id,
uint32_t priority, uint32_t weight,
-struct rte_tm_node_params *params,
+const struct rte_tm_node_params *params,
struct rte_tm_error *error)
{
struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
@@ -457,7 +457,7 @@ hns3_tm_node_param_check(struct rte_eth_dev *dev, uint32_t
node_id,
static int
hns3_tm_port_node_add(struct rte_eth_dev *dev, uint32_t node_id,
- uint32_t level_id, struct rte_tm_node_params *params,
+ uint32_t level_id, const struct rte_tm_node_params
*params,
struct rte_tm_error *error)
{
struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
@@ -503,7 +503,7 @@ hns3_tm_port_node_add(struct rte_eth_dev *dev, uint32_t
node_id,
static int
hns3_tm_tc_node_add(struct rte_eth_dev *dev, uint32_t node_id,
uint32_t level_id, struct hns3_tm_node *parent_node,
- struct rte_tm_node_params *params,
+ const struct rte_tm_node_params *params,
[PATCH v2 3/3] ethdev: make TM shaper parameters constant
The function to add a new shaper profile in rte_tm should not (and does
not) modify the profile parameters passed in via struct pointer. We
should guarantee this by marking the parameter pointer as const. This
allows SW to create multiple profiles using the same parameter
struct without having to reset it each time.
Signed-off-by: Bruce Richardson
Reviewed-by: Rosen Xu
Acked-by: Ferruh Yigit
---
drivers/net/cnxk/cnxk_tm.c | 2 +-
drivers/net/dpaa2/dpaa2_tm.c| 2 +-
drivers/net/hns3/hns3_tm.c | 6 +++---
drivers/net/i40e/i40e_tm.c | 6 +++---
drivers/net/iavf/iavf_tm.c | 6 +++---
drivers/net/ice/ice_dcf_sched.c | 6 +++---
drivers/net/ice/ice_tm.c| 6 +++---
drivers/net/ipn3ke/ipn3ke_tm.c | 4 ++--
drivers/net/ixgbe/ixgbe_tm.c| 6 +++---
drivers/net/mvpp2/mrvl_tm.c | 2 +-
drivers/net/txgbe/txgbe_tm.c| 6 +++---
lib/ethdev/rte_tm.c | 2 +-
lib/ethdev/rte_tm.h | 2 +-
lib/ethdev/rte_tm_driver.h | 2 +-
14 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_tm.c b/drivers/net/cnxk/cnxk_tm.c
index 9293b3e8f2..0ed6732dda 100644
--- a/drivers/net/cnxk/cnxk_tm.c
+++ b/drivers/net/cnxk/cnxk_tm.c
@@ -267,7 +267,7 @@ cnxk_nix_tm_node_capa_get(struct rte_eth_dev *eth_dev,
uint32_t node_id,
static int
cnxk_nix_tm_shaper_profile_add(struct rte_eth_dev *eth_dev, uint32_t id,
- struct rte_tm_shaper_params *params,
+ const struct rte_tm_shaper_params *params,
struct rte_tm_error *error)
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
diff --git a/drivers/net/dpaa2/dpaa2_tm.c b/drivers/net/dpaa2/dpaa2_tm.c
index 22337097e5..115397ce47 100644
--- a/drivers/net/dpaa2/dpaa2_tm.c
+++ b/drivers/net/dpaa2/dpaa2_tm.c
@@ -268,7 +268,7 @@ dpaa2_shaper_profile_from_id(struct dpaa2_dev_priv *priv,
static int
dpaa2_shaper_profile_add(struct rte_eth_dev *dev, uint32_t shaper_profile_id,
-struct rte_tm_shaper_params *params,
+const struct rte_tm_shaper_params *params,
struct rte_tm_error *error)
{
struct dpaa2_dev_priv *priv = dev->data->dev_private;
diff --git a/drivers/net/hns3/hns3_tm.c b/drivers/net/hns3/hns3_tm.c
index 06df32bbcd..1c2ad71133 100644
--- a/drivers/net/hns3/hns3_tm.c
+++ b/drivers/net/hns3/hns3_tm.c
@@ -166,7 +166,7 @@ hns3_tm_shaper_profile_search(struct rte_eth_dev *dev,
static int
hns3_tm_shaper_profile_param_check(struct rte_eth_dev *dev,
- struct rte_tm_shaper_params *profile,
+ const struct rte_tm_shaper_params *profile,
struct rte_tm_error *error)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
@@ -220,7 +220,7 @@ hns3_tm_shaper_profile_param_check(struct rte_eth_dev *dev,
static int
hns3_tm_shaper_profile_add(struct rte_eth_dev *dev,
uint32_t shaper_profile_id,
- struct rte_tm_shaper_params *profile,
+ const struct rte_tm_shaper_params *profile,
struct rte_tm_error *error)
{
struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
@@ -1198,7 +1198,7 @@ hns3_tm_capabilities_get_wrap(struct rte_eth_dev *dev,
static int
hns3_tm_shaper_profile_add_wrap(struct rte_eth_dev *dev,
uint32_t shaper_profile_id,
- struct rte_tm_shaper_params *profile,
+ const struct rte_tm_shaper_params *profile,
struct rte_tm_error *error)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
diff --git a/drivers/net/i40e/i40e_tm.c b/drivers/net/i40e/i40e_tm.c
index c7d4680fb4..4c0940f355 100644
--- a/drivers/net/i40e/i40e_tm.c
+++ b/drivers/net/i40e/i40e_tm.c
@@ -12,7 +12,7 @@ static int i40e_tm_capabilities_get(struct rte_eth_dev *dev,
struct rte_tm_error *error);
static int i40e_shaper_profile_add(struct rte_eth_dev *dev,
uint32_t shaper_profile_id,
- struct rte_tm_shaper_params *profile,
+ const struct rte_tm_shaper_params *profile,
struct rte_tm_error *error);
static int i40e_shaper_profile_del(struct rte_eth_dev *dev,
uint32_t shaper_profile_id,
@@ -217,7 +217,7 @@ i40e_shaper_profile_search(struct rte_eth_dev *dev,
}
static int
-i40e_shaper_profile_param_check(struct rte_tm_shaper_params *profile,
+i40e_shaper_profile_param_check(const struct rte_tm_shaper_params *profile,
struct rte_tm_error *error)
{
/* min rate not supported */
@@ -251,7 +251,7 @@ i40e_shaper_profile
[PATCH v2 0/3] make struct parameters constant in rte_tm APIs
For functions for creating profiles, shapers and hierarchy nodes, make the parameter structure pointer a pointer to a const object. This guarantees to the user that the struct won't be modified by the function, which allows the user to re-use the same parameters multiple times without having to constantly reinitialize it. V2: drop final patch with new node query function, simplifying patchset Bruce Richardson (3): ethdev: make parameters to TM node add fn constant ethdev: make parameters to TM profile add fn constant ethdev: make TM shaper parameters constant drivers/net/cnxk/cnxk_tm.c | 4 ++-- drivers/net/dpaa2/dpaa2_tm.c| 6 +++--- drivers/net/hns3/hns3_tm.c | 22 +++--- drivers/net/i40e/i40e_tm.c | 12 ++-- drivers/net/iavf/iavf_tm.c | 12 ++-- drivers/net/ice/ice_dcf_sched.c | 12 ++-- drivers/net/ice/ice_tm.c| 12 ++-- drivers/net/ipn3ke/ipn3ke_tm.c | 12 ++-- drivers/net/ixgbe/ixgbe_tm.c| 12 ++-- drivers/net/mvpp2/mrvl_tm.c | 2 +- drivers/net/txgbe/txgbe_tm.c| 12 ++-- lib/ethdev/rte_tm.c | 6 +++--- lib/ethdev/rte_tm.h | 6 +++--- lib/ethdev/rte_tm_driver.h | 6 +++--- 14 files changed, 68 insertions(+), 68 deletions(-) -- 2.43.0
Re: [PATCH v2] common/mlx5: Optimize mlx5 mempool get extmem
Dear Stephen, The problem has not been solved, but I found a workaround. According to the documentation (https://doc.dpdk.org/guides/prog_guide/gpudev.html, sec 11.3), rte_extmem_register should be invoked with GPU_PAGE_SIZE as an argument. If GPU_PAGE_SIZE is set to 2 MB instead of 64 kB, registration of 72 GB of GPU memory (on a Grace Hopper) is done in about ten seconds, not hours. rte_extmem_register(ext_mem.buf_ptr, ext_mem.buf_len, NULL, ext_mem.buf_iova, GPU_PAGE_SIZE); Thanks, John Romein On 05-10-2024 00:16, Stephen Hemminger wrote: On Wed, 1 Nov 2023 22:21:16 +0100 John Romein wrote: Dear Slava, Thank you for looking at the patch. With the original code, I saw that the application spent literally hours in this function during program start up, if tens of gigabytes of GPU memory are registered. This was due to qsort being invoked for every new added item (to keep the list sorted). So I tried to write equivalent code that sorts the list only once, after all items were added. At least for our application, this works well and is /much/ faster, as the complexity decreased from n^2 log(n) to n log(n). But I must admit that I have no idea /what/ is being sorted, or why; I only understand this isolated piece of code (or at least I think so). So if you think there are better ways to initialize the list, then I am sure you will be absolutely right. But I will not be able to implement this, as I do not understand the full context of the code. Kind Regards, John Looks like the problem remains but patch has been sitting around for 11 months. Was this resolved?
Re: [PATCH] eal/x86: cache queried CPU flags
On Mon, Oct 7, 2024 at 1:07 PM Bruce Richardson wrote: > > Rather than re-querying the HW each time a CPU flag is requested, we can > just save the return value in the flags array. This should speed up > repeated querying of CPU flags, and provides a workaround for a reported > issue where errors are seen with constant querying of the AVX-512 CPU > flag from a non-AVX VM. This could be applied to other arches cpuflag implementation. Copying other arches maintainers as a fyi. > > Bugzilla Id: 1501 Bugzilla ID* > > Signed-off-by: Bruce Richardson I did a quick pass, it lgtm. -- David Marchand
[PATCH] eal/x86: cache queried CPU flags
Rather than re-querying the HW each time a CPU flag is requested, we can
just save the return value in the flags array. This should speed up
repeated querying of CPU flags, and provides a workaround for a reported
issue where errors are seen with constant querying of the AVX-512 CPU
flag from a non-AVX VM.
Bugzilla Id: 1501
Signed-off-by: Bruce Richardson
---
lib/eal/x86/rte_cpuflags.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c
index 26163ab746..62e782fb4b 100644
--- a/lib/eal/x86/rte_cpuflags.c
+++ b/lib/eal/x86/rte_cpuflags.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include "rte_cpuid.h"
@@ -21,12 +22,14 @@ struct feature_entry {
uint32_t bit; /**< cpuid register bit */
#define CPU_FLAG_NAME_MAX_LEN 64
char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */
+ bool has_value;
+ bool value;
};
#define FEAT_DEF(name, leaf, subleaf, reg, bit) \
[RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },
-const struct feature_entry rte_cpu_feature_table[] = {
+struct feature_entry rte_cpu_feature_table[] = {
FEAT_DEF(SSE3, 0x0001, 0, RTE_REG_ECX, 0)
FEAT_DEF(PCLMULQDQ, 0x0001, 0, RTE_REG_ECX, 1)
FEAT_DEF(DTES64, 0x0001, 0, RTE_REG_ECX, 2)
@@ -147,7 +150,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
int
rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
{
- const struct feature_entry *feat;
+ struct feature_entry *feat;
cpuid_registers_t regs;
unsigned int maxleaf;
@@ -156,6 +159,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
return -ENOENT;
feat = &rte_cpu_feature_table[feature];
+ if (feat->has_value)
+ return feat->value;
if (!feat->leaf)
/* This entry in the table wasn't filled out! */
@@ -163,8 +168,10 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
maxleaf = __get_cpuid_max(feat->leaf & 0x8000, NULL);
- if (maxleaf < feat->leaf)
- return 0;
+ if (maxleaf < feat->leaf) {
+ feat->value = 0;
+ goto out;
+ }
#ifdef RTE_TOOLCHAIN_MSVC
__cpuidex(regs, feat->leaf, feat->subleaf);
@@ -175,7 +182,10 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
#endif
/* check if the feature is enabled */
- return (regs[feat->reg] >> feat->bit) & 1;
+ feat->value = (regs[feat->reg] >> feat->bit) & 1;
+out:
+ feat->has_value = true;
+ return feat->value;
}
const char *
--
2.43.0
Re: [PATCH v18 1/3] eventdev: add support for independent enqueue
On Mon, Oct 7, 2024 at 1:43 PM Abdullah Sevincer wrote: > > Support for independent enqueue feature and updates Event Device > and PMD feature list. > > A new capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ is introduced. It > allows out-of-order enqueuing of RTE_EVENT_OP_FORWARD or RELEASE type > events on an event port where this capability is enabled. > > To use this capability applications need to set flag > RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ during port setup only if the > capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ exists. > > Signed-off-by: Abdullah Sevincer > Acked-by: Mattias Rönnblom Acked-by: Jerin Jacob Series applied to dpdk-next-net-eventdev/for-main. Thanks > --- > doc/guides/eventdevs/features/default.ini | 1 + > doc/guides/prog_guide/eventdev/eventdev.rst | 23 +++ > doc/guides/rel_notes/release_24_11.rst | 8 ++ > lib/eventdev/rte_eventdev.h | 31 + > 4 files changed, 63 insertions(+) > > diff --git a/doc/guides/eventdevs/features/default.ini > b/doc/guides/eventdevs/features/default.ini > index 1cc4303fe5..7c4ee99238 100644 > --- a/doc/guides/eventdevs/features/default.ini > +++ b/doc/guides/eventdevs/features/default.ini > @@ -22,6 +22,7 @@ carry_flow_id = > maintenance_free = > runtime_queue_attr = > profile_links = > +independent_enq= > > ; > ; Features of a default Ethernet Rx adapter. > diff --git a/doc/guides/prog_guide/eventdev/eventdev.rst > b/doc/guides/prog_guide/eventdev/eventdev.rst > index fb6dfce102..515744d8ec 100644 > --- a/doc/guides/prog_guide/eventdev/eventdev.rst > +++ b/doc/guides/prog_guide/eventdev/eventdev.rst > @@ -472,6 +472,29 @@ A flush callback can be passed to the function to handle > any outstanding events. > > Invocation of this API does not affect the existing port > configuration. > > +Independent Enqueue Capability > +~~ > + > +This capability applies to eventdev devices that expects all forwarded > events to be > +enqueued in the same order as they are dequeued. For dropped events, their > +releases should come at the same location as the original event was expected. > +The eventdev device has this restriction as it uses the order to retrieve > information about > +the original event that was sent to the CPU. This contains information like > atomic > +flow ID to release the flow lock and ordered events sequence number to > restore the > +original order. > + > +This capability only matters to eventdevs supporting burst mode. On ports > where > +the application is going to change enqueue order, > +``RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ`` support should be enabled. > + > +Example code to inform PMD that the application plans to use independent > enqueue > +order on a port: > + > +.. code-block:: c > + > + if (capability & RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ) > + port_config = port_config | RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ; > + > Stopping the EventDev > ~ > > diff --git a/doc/guides/rel_notes/release_24_11.rst > b/doc/guides/rel_notes/release_24_11.rst > index e0a9aa55a1..bf7b8f005c 100644 > --- a/doc/guides/rel_notes/release_24_11.rst > +++ b/doc/guides/rel_notes/release_24_11.rst > @@ -67,6 +67,14 @@ New Features > >The new statistics are useful for debugging and profiling. > > +* **Updated Event Device Library for independent enqueue feature** > + > + * Added support for independent enqueue feature. With this feature Eventdev > +supports enqueue in any order or specifically in a different order than > +dequeue. The feature is intended for eventdevs supporting burst mode. > +Applications should use ``RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ`` to enable > +the feature if the capability ``RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ`` > exists. > + > > Removed Items > - > diff --git a/lib/eventdev/rte_eventdev.h b/lib/eventdev/rte_eventdev.h > index 08e5f9320b..73a44b2ac5 100644 > --- a/lib/eventdev/rte_eventdev.h > +++ b/lib/eventdev/rte_eventdev.h > @@ -446,6 +446,25 @@ struct rte_event; > * @see RTE_SCHED_TYPE_PARALLEL > */ > > +#define RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ (1ULL << 16) > +/**< Event device is capable of independent enqueue. > + * A new capability, RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ, will indicate that > Eventdev > + * supports the enqueue in any order or specifically in a different order > than the > + * dequeue. Eventdev PMD can either dequeue events in the changed order in > which > + * they are enqueued or restore the original order before sending them to the > + * underlying hardware device. A flag is provided during the port > configuration to > + * inform Eventdev PMD that the application intends to use an independent > enqueue > + * order on a particular port. Note that this capability only matters for > eventdevs > + * supporting burst mode. > + * > + * When an implicit release is enabled o
[dpdk-dev] [PATCH v2] drivers: fix build issues with redundant newline changes
From: Jerin Jacob
Certain section of the code in net/mvpp2 and ml/cnxk is enabled only
when all depended library dependences where meet.
Fixing those build errors.
Fixes: f665790a5dba ("drivers: remove redundant newline from logs")
Signed-off-by: Jerin Jacob
---
v2:
- Add
https://patches.dpdk.org/project/dpdk/patch/20241007081301.2999359-1-jer...@marvell.com/
review comments (David)
drivers/ml/cnxk/mvtvm_ml_dev.c | 8 ++---
drivers/ml/cnxk/mvtvm_ml_model.c | 4 +--
drivers/ml/cnxk/mvtvm_ml_ops.c | 6 ++--
drivers/net/mvpp2/mrvl_ethdev.c | 14
drivers/net/mvpp2/mrvl_qos.c | 56
5 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/ml/cnxk/mvtvm_ml_dev.c b/drivers/ml/cnxk/mvtvm_ml_dev.c
index c9b9444eff..74959a12fc 100644
--- a/drivers/ml/cnxk/mvtvm_ml_dev.c
+++ b/drivers/ml/cnxk/mvtvm_ml_dev.c
@@ -63,7 +63,7 @@ mvtvm_mldev_parse_devargs(const char *args, struct
mvtvm_ml_dev *mvtvm_mldev)
kvlist = rte_kvargs_parse(args, valid_args);
if (kvlist == NULL) {
- plt_err("Error parsing %s devargs\n", "MLDEV_NAME_MVTVM_PMD");
+ plt_err("Error parsing %s devargs", "MLDEV_NAME_MVTVM_PMD");
return -EINVAL;
}
@@ -71,7 +71,7 @@ mvtvm_mldev_parse_devargs(const char *args, struct
mvtvm_ml_dev *mvtvm_mldev)
ret = rte_kvargs_process(kvlist, MVTVM_ML_DEV_MAX_QPS,
&parse_uint_arg,
&mvtvm_mldev->max_nb_qpairs);
if (ret < 0) {
- plt_err("Error processing arguments, key = %s\n",
MVTVM_ML_DEV_MAX_QPS);
+ plt_err("Error processing arguments, key = %s",
MVTVM_ML_DEV_MAX_QPS);
ret = -EINVAL;
goto exit;
}
@@ -82,7 +82,7 @@ mvtvm_mldev_parse_devargs(const char *args, struct
mvtvm_ml_dev *mvtvm_mldev)
ret = rte_kvargs_process(kvlist, MVTVM_ML_DEV_CACHE_MODEL_DATA,
&parse_integer_arg,
&mvtvm_mldev->cache_model_data);
if (ret < 0) {
- plt_err("Error processing arguments, key = %s\n",
+ plt_err("Error processing arguments, key = %s",
MVTVM_ML_DEV_CACHE_MODEL_DATA);
ret = -EINVAL;
goto exit;
@@ -99,7 +99,7 @@ mvtvm_mldev_parse_devargs(const char *args, struct
mvtvm_ml_dev *mvtvm_mldev)
mvtvm_mldev->cache_model_data =
CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT;
} else {
if ((mvtvm_mldev->cache_model_data < 0) ||
(mvtvm_mldev->cache_model_data > 1)) {
- plt_err("Invalid argument, %s = %d\n",
MVTVM_ML_DEV_CACHE_MODEL_DATA,
+ plt_err("Invalid argument, %s = %d",
MVTVM_ML_DEV_CACHE_MODEL_DATA,
mvtvm_mldev->cache_model_data);
ret = -EINVAL;
goto exit;
diff --git a/drivers/ml/cnxk/mvtvm_ml_model.c b/drivers/ml/cnxk/mvtvm_ml_model.c
index e3234ae442..3ada6f42db 100644
--- a/drivers/ml/cnxk/mvtvm_ml_model.c
+++ b/drivers/ml/cnxk/mvtvm_ml_model.c
@@ -50,7 +50,7 @@ mvtvm_ml_model_type_get(struct rte_ml_model_params *params)
/* Check if all objects are available */
for (i = 0; i < ML_MVTVM_MODEL_OBJECT_MAX; i++) {
if (!object_found[i]) {
- plt_err("Object %s not found in archive!\n",
mvtvm_object_list[i]);
+ plt_err("Object %s not found in archive!",
mvtvm_object_list[i]);
return ML_CNXK_MODEL_TYPE_INVALID;
}
}
@@ -100,7 +100,7 @@ mvtvm_ml_model_blob_parse(struct rte_ml_model_params
*params, struct mvtvm_ml_mo
/* Check if all objects are parsed */
for (i = 0; i < ML_MVTVM_MODEL_OBJECT_MAX; i++) {
if (!object_found[i]) {
- plt_err("Object %s not found in archive!\n",
mvtvm_object_list[i]);
+ plt_err("Object %s not found in archive!",
mvtvm_object_list[i]);
goto error;
}
}
diff --git a/drivers/ml/cnxk/mvtvm_ml_ops.c b/drivers/ml/cnxk/mvtvm_ml_ops.c
index e825c3fb23..ddde104f5b 100644
--- a/drivers/ml/cnxk/mvtvm_ml_ops.c
+++ b/drivers/ml/cnxk/mvtvm_ml_ops.c
@@ -123,7 +123,7 @@ mvtvm_ml_dev_configure(struct cnxk_ml_dev *cnxk_mldev,
const struct rte_ml_dev_c
/* Configure TVMDP library */
ret = tvmdp_configure(cnxk_mldev->mldev->data->nb_models,
rte_get_tsc_cycles);
if (ret != 0)
- plt_err("TVMDP configuration failed, error = %d\n", ret);
+ plt_err("TVMDP configuration failed, error = %d", ret);
return ret;
}
@@ -138,7 +138,7 @@ mvtvm_ml_dev_close(struct cnxk_ml_dev *cnxk_mldev)
/* Close TVMDP library configuration */
ret = tvmdp_close();
Re: [PATCH] test: fix option block
On Thu, 14 Mar 2024 09:46:26 +
Mingjin Ye wrote:
> The options allow (-a) and block (-b) cannot be used at the same time.
> Therefore, allow (-a) will not be added when block (-b) is present.
>
> Fixes: b3ce7891ad38 ("test: fix probing in secondary process")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Mingjin Ye
> ---
> app/test/process.h | 17 ++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/app/test/process.h b/app/test/process.h
> index 9fb2bf481c..388c7975cd 100644
> --- a/app/test/process.h
> +++ b/app/test/process.h
> @@ -44,7 +44,7 @@ add_parameter_allow(char **argv, int max_capacity)
> int count = 0;
>
> RTE_EAL_DEVARGS_FOREACH(NULL, devargs) {
> - if (strlen(devargs->name) == 0)
> + if (strlen(devargs->name) == 0 || devargs->type !=
> RTE_DEVTYPE_ALLOWED)
> continue;
>
> if (devargs->data == NULL || strlen(devargs->data) == 0) {
> @@ -74,7 +74,7 @@ process_dup(const char *const argv[], int numargs, const
> char *env_value)
> {
> int num = 0;
> char **argv_cpy;
> - int allow_num;
> + int allow_num, block_num;
> int argv_num;
> int i, status;
> char path[32];
> @@ -89,7 +89,18 @@ process_dup(const char *const argv[], int numargs, const
> char *env_value)
> if (pid < 0)
> return -1;
> else if (pid == 0) {
> - allow_num = rte_devargs_type_count(RTE_DEVTYPE_ALLOWED);
> + allow_num = 0;
> + block_num = 0;
> +
> + /* If block (-b) is present, allow (-a) is not added. */
> + for (i = 0; i < numargs; i++) {
> + if (strcmp(argv[i], "-b") == 0 ||
> + strcmp(argv[i], "-block") == 0)
The long form of the option is "--block" not "-block".
Why is a test infrastructure adding both options anyway, seems like that is the
real problem.
[PATCH v2 28/50] net/ntnic: add categorizer (CAT) FPGA module
From: Oleksandr Kolomeiets
The Categorizer module’s main purpose is to is select the behavior
of other modules in the FPGA pipeline depending on a protocol check.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 205
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c| 15 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 109 +-
.../ntnic/nthw/flow_api/hw_mod/hw_mod_cat.c | 985 ++
.../supported/nthw_fpga_9563_055_049_.c | 264 -
6 files changed, 1577 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_cat.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index f47153cbb6..20b10faf5e 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -22,12 +22,116 @@
#define MAX_PHYS_ADAPTERS 8
+#define VER_MAJOR(ver) (((ver) >> 16) & 0x)
+#define VER_MINOR(ver) ((ver) & 0x)
+
+struct flow_api_backend_s;
+struct common_func_s;
+
+void *callocate_mod(struct common_func_s *mod, int sets, ...);
+void zero_module_cache(struct common_func_s *mod);
+
+#define ALL_ENTRIES -1000
+
+#define INDEX_TOO_LARGE (NT_LOG(INF, FILTER, "ERROR:%s: Index too large\n",
__func__), -2)
+
+#define WORD_OFF_TOO_LARGE (NT_LOG(INF, FILTER, "ERROR:%s: Word offset too
large\n", __func__), -3)
+
+#define UNSUP_FIELD
\
+ (NT_LOG(INF, FILTER, "ERROR:%s: Unsupported field in NIC module\n",
__func__), -5)
+
+#define UNSUP_VER
\
+ (NT_LOG(INF, FILTER, "ERROR:%s: Unsupported NIC module: %s ver
%i.%i\n", __func__, _MOD_, \
+ VER_MAJOR(_VER_), VER_MINOR(_VER_)),
\
+-4)
+
+#define COUNT_ERROR(_RESOURCE_)
\
+ (NT_LOG(INF, FILTER,
\
+ "ERROR:%s: Insufficient resource [ %s ] : NIC module: %s ver
%i.%i\n", __func__, \
+ #_RESOURCE_, _MOD_, VER_MAJOR(_VER_), VER_MINOR(_VER_)),
\
+-4)
+
+#define NOT_FOUND 0x
+
+enum {
+ EXTRA_INDEXES
+};
+
+#define GET(cached_val, val) ({ *(val) = *(cached_val); })
+
+#define SET(cached_val, val) ({ *(cached_val) = *(val); })
+
+#define GET_SET(cached_val, val)
\
+ do {
\
+ uint32_t *temp_val = (val);
\
+ typeof(cached_val) *temp_cached_val = &(cached_val);
\
+ if (get)
\
+ GET(temp_cached_val, temp_val);
\
+ else
\
+ SET(temp_cached_val, temp_val);
\
+ } while (0)
+
+#define GET_SIGNED(cached_val, val) ({ *(val) = (uint32_t)(*(cached_val)); })
+
+#define SET_SIGNED(cached_val, val) ({ *(cached_val) = (int32_t)(*(val)); })
+
+#define GET_SET_SIGNED(cached_val, val)
\
+ do {
\
+ uint32_t *temp_val = (val);
\
+ typeof(cached_val) *temp_cached_val = &(cached_val);
\
+ if (get)
\
+ GET_SIGNED(temp_cached_val, temp_val);
\
+ else
\
+ SET_SIGNED(temp_cached_val, temp_val);
\
+ } while (0)
+
+#define FIND_EQUAL_INDEX(be_module_reg, type, idx, start, nb_elements)
\
+ do {
\
+ typeof(be_module_reg) *temp_be_module =
\
+ (typeof(be_module_reg) *)be_module_reg;
\
+ typeof(idx) tmp_idx = (idx);
\
+ typeof(nb_elements) tmp_nb_elements = (nb_elements);
[PATCH v2 39/50] net/ntnic: add scatter-gather HW deallocation
From: Danylo Vodopianov
Deallocates memory for hardware Virtio queues and unmaps
VFIO resources.
Updated eth_tx_queue_release and eth_rx_queue_release. Released
hardware Virtio queues for TX and RX.
Signed-off-by: Danylo Vodopianov
---
drivers/net/ntnic/include/ntos_drv.h | 1 +
drivers/net/ntnic/ntnic_ethdev.c | 32
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ntnic/include/ntos_drv.h
b/drivers/net/ntnic/include/ntos_drv.h
index 191686a07a..233d585303 100644
--- a/drivers/net/ntnic/include/ntos_drv.h
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -28,6 +28,7 @@
/* Structs: */
struct nthw_memory_descriptor {
+ void *phys_addr;
void *virt_addr;
uint32_t len;
};
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 79b5ae4d60..78a689d444 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -34,6 +34,8 @@
/* Max RSS queues */
#define MAX_QUEUES 125
+#define ONE_G_SIZE 0x4000
+
#define ETH_DEV_NTNIC_HELP_ARG "help"
#define ETH_DEV_NTHW_RXQUEUES_ARG "rxqs"
#define ETH_DEV_NTHW_TXQUEUES_ARG "txqs"
@@ -193,16 +195,38 @@ static void release_hw_virtio_queues(struct hwq_s *hwq)
hwq->vf_num = 0;
}
+static int deallocate_hw_virtio_queues(struct hwq_s *hwq)
+{
+ int vf_num = hwq->vf_num;
+
+ void *virt = hwq->virt_queues_ctrl.virt_addr;
+
+ int res = nt_vfio_dma_unmap(vf_num, hwq->virt_queues_ctrl.virt_addr,
+ (uint64_t)hwq->virt_queues_ctrl.phys_addr, ONE_G_SIZE);
+
+ if (res != 0) {
+ NT_LOG(ERR, NTNIC, "VFIO UNMMAP FAILED! res %i, vf_num %i\n",
res, vf_num);
+ return -1;
+ }
+
+ release_hw_virtio_queues(hwq);
+ rte_free(hwq->pkt_buffers);
+ rte_free(virt);
+ return 0;
+}
+
static void eth_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t
queue_id)
{
- (void)eth_dev;
- (void)queue_id;
+ struct pmd_internals *internals = (struct pmd_internals
*)eth_dev->data->dev_private;
+ struct ntnic_tx_queue *tx_q = &internals->txq_scg[queue_id];
+ deallocate_hw_virtio_queues(&tx_q->hwq);
}
static void eth_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t
queue_id)
{
- (void)eth_dev;
- (void)queue_id;
+ struct pmd_internals *internals = (struct pmd_internals
*)eth_dev->data->dev_private;
+ struct ntnic_rx_queue *rx_q = &internals->rxq_scg[queue_id];
+ deallocate_hw_virtio_queues(&rx_q->hwq);
}
static int num_queues_alloced;
--
2.45.0
[PATCH v2 43/50] net/ntnic: add split-queue support
From: Danylo Vodopianov
Split-queue support was added.
Internal structures were enhanced with additional managmnet fields.
Implement a managed virtual queue function based on the queue type
and configuration parameters.
DBS control registers were added.
Signed-off-by: Danylo Vodopianov
---
drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c | 411 +-
drivers/net/ntnic/include/ntnic_dbs.h | 19 +
drivers/net/ntnic/include/ntnic_virt_queue.h | 7 +
drivers/net/ntnic/nthw/dbs/nthw_dbs.c | 125 +-
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../nthw/supported/nthw_fpga_reg_defs_dbs.h | 79
6 files changed, 640 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h
diff --git a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
index fc1dab6c5f..e69cf7ad21 100644
--- a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
+++ b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
@@ -10,6 +10,7 @@
#include "ntnic_mod_reg.h"
#include "ntlog.h"
+#define STRUCT_ALIGNMENT (4 * 1024LU)
#define MAX_VIRT_QUEUES 128
#define LAST_QUEUE 127
@@ -34,12 +35,79 @@
#define TX_AM_POLL_SPEED 5
#define TX_UW_POLL_SPEED 8
+#define VIRTQ_AVAIL_F_NO_INTERRUPT 1
+
+struct __rte_aligned(8) virtq_avail {
+ uint16_t flags;
+ uint16_t idx;
+ uint16_t ring[];/* Queue Size */
+};
+
+struct __rte_aligned(8) virtq_used_elem {
+ /* Index of start of used descriptor chain. */
+ uint32_t id;
+ /* Total length of the descriptor chain which was used (written to) */
+ uint32_t len;
+};
+
+struct __rte_aligned(8) virtq_used {
+ uint16_t flags;
+ uint16_t idx;
+ struct virtq_used_elem ring[]; /* Queue Size */
+};
+
+struct virtq_struct_layout_s {
+ size_t used_offset;
+ size_t desc_offset;
+};
+
enum nthw_virt_queue_usage {
- NTHW_VIRTQ_UNUSED = 0
+ NTHW_VIRTQ_UNUSED = 0,
+ NTHW_VIRTQ_UNMANAGED,
+ NTHW_VIRTQ_MANAGED
};
struct nthw_virt_queue {
+ /* Pointers to virt-queue structs */
+ struct {
+ /* SPLIT virtqueue */
+ struct virtq_avail *p_avail;
+ struct virtq_used *p_used;
+ struct virtq_desc *p_desc;
+ /* Control variables for virt-queue structs */
+ uint16_t am_idx;
+ uint16_t used_idx;
+ uint16_t cached_idx;
+ uint16_t tx_descr_avail_idx;
+ };
+
+ /* Array with packet buffers */
+ struct nthw_memory_descriptor *p_virtual_addr;
+
+ /* Queue configuration info */
+ nthw_dbs_t *mp_nthw_dbs;
+
enum nthw_virt_queue_usage usage;
+ uint16_t irq_vector;
+ uint16_t vq_type;
+ uint16_t in_order;
+
+ uint16_t queue_size;
+ uint32_t index;
+ uint32_t am_enable;
+ uint32_t host_id;
+ uint32_t port; /* Only used by TX queues */
+ uint32_t virtual_port; /* Only used by TX queues */
+ /*
+* Only used by TX queues:
+* 0: VirtIO-Net header (12 bytes).
+* 1: Napatech DVIO0 descriptor (12 bytes).
+*/
+};
+
+struct pvirtq_struct_layout_s {
+ size_t driver_event_offset;
+ size_t device_event_offset;
};
static struct nthw_virt_queue rxvq[MAX_VIRT_QUEUES];
@@ -143,7 +211,348 @@ static int nthw_virt_queue_init(struct fpga_info_s
*p_fpga_info)
return 0;
}
+static struct virtq_struct_layout_s dbs_calc_struct_layout(uint32_t queue_size)
+{
+ /* + sizeof(uint16_t); ("avail->used_event" is not used) */
+ size_t avail_mem = sizeof(struct virtq_avail) + queue_size *
sizeof(uint16_t);
+ size_t avail_mem_aligned = ((avail_mem % STRUCT_ALIGNMENT) == 0)
+ ? avail_mem
+ : STRUCT_ALIGNMENT * (avail_mem / STRUCT_ALIGNMENT + 1);
+
+ /* + sizeof(uint16_t); ("used->avail_event" is not used) */
+ size_t used_mem = sizeof(struct virtq_used) + queue_size *
sizeof(struct virtq_used_elem);
+ size_t used_mem_aligned = ((used_mem % STRUCT_ALIGNMENT) == 0)
+ ? used_mem
+ : STRUCT_ALIGNMENT * (used_mem / STRUCT_ALIGNMENT + 1);
+
+ struct virtq_struct_layout_s virtq_layout;
+ virtq_layout.used_offset = avail_mem_aligned;
+ virtq_layout.desc_offset = avail_mem_aligned + used_mem_aligned;
+
+ return virtq_layout;
+}
+
+static void dbs_initialize_avail_struct(void *addr, uint16_t queue_size,
+ uint16_t initial_avail_idx)
+{
+ uint16_t i;
+ struct virtq_avail *p_avail = (struct virtq_avail *)addr;
+
+ p_avail->flags = VIRTQ_AVAIL_F_NO_INTERRUPT;
+ p_avail->idx = initial_avail_idx;
+
+ for (i = 0; i < queue_size; ++i)
+ p_avail->ring[i] = i;
+}
+
+static void dbs_initialize_used_struct(void *addr, uint16_t queue_size)
+{
+ int i;
+ struct virtq_used *p_used = (struc
[PATCH v2 45/50] net/ntnic: used writer data handling functions
From: Danylo Vodopianov
Introduced functions to set and flush RX and TX used writer data.
Added support for setting shadow data with functions for guest
physical address, host ID, queue size, packed, interrupt enable,
vector, and ISTK for RX and TX.
Implemented set_rx_used_writer_data and set_tx_used_writer_data to
configure and flush data based on updated shadow structures.
Signed-off-by: Danylo Vodopianov
---
drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c | 60 +++-
drivers/net/ntnic/include/ntnic_dbs.h | 71
drivers/net/ntnic/nthw/dbs/nthw_dbs.c | 316 ++
.../nthw/supported/nthw_fpga_reg_defs_dbs.h | 23 ++
4 files changed, 468 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
index 065dac6af0..1df42dad11 100644
--- a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
+++ b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
@@ -285,6 +285,19 @@ dbs_initialize_virt_queue_structs(void *avail_struct_addr,
void *used_struct_add
flgs);
}
+static uint16_t dbs_qsize_log2(uint16_t qsize)
+{
+ uint32_t qs = 0;
+
+ while (qsize) {
+ qsize = qsize >> 1;
+ ++qs;
+ }
+
+ --qs;
+ return qs;
+}
+
static struct nthw_virt_queue *nthw_setup_rx_virt_queue(nthw_dbs_t *p_nthw_dbs,
uint32_t index,
uint16_t start_idx,
@@ -300,7 +313,29 @@ static struct nthw_virt_queue
*nthw_setup_rx_virt_queue(nthw_dbs_t *p_nthw_dbs,
{
(void)header;
(void)desc_struct_phys_addr;
- (void)used_struct_phys_addr;
+ uint32_t qs = dbs_qsize_log2(queue_size);
+ uint32_t int_enable;
+ uint32_t vec;
+ uint32_t istk;
+
+ /*
+* 4. Configure the DBS.RX_UW_DATA memory; good idea to initialize all
+* DBS_RX_QUEUES entries.
+* Notice: We always start out with interrupts disabled (by setting
the
+* "irq_vector" argument to -1). Queues that require interrupts
will have
+* it enabled at a later time (after we have enabled vfio
interrupts in
+* the kernel).
+*/
+ int_enable = 0;
+ vec = 0;
+ istk = 0;
+ NT_LOG_DBGX(DBG, NTNIC, "set_rx_uw_data int=0 irq_vector=%u\n",
irq_vector);
+
+ if (set_rx_uw_data(p_nthw_dbs, index,
+ (uint64_t)used_struct_phys_addr,
+ host_id, qs, 0, int_enable, vec, istk) != 0) {
+ return NULL;
+ }
/*
* 2. Configure the DBS.RX_AM_DATA memory and enable the queues you
plan to use;
@@ -366,7 +401,28 @@ static struct nthw_virt_queue
*nthw_setup_tx_virt_queue(nthw_dbs_t *p_nthw_dbs,
{
(void)header;
(void)desc_struct_phys_addr;
- (void)used_struct_phys_addr;
+ uint32_t int_enable;
+ uint32_t vec;
+ uint32_t istk;
+ uint32_t qs = dbs_qsize_log2(queue_size);
+
+ /*
+* 4. Configure the DBS.TX_UW_DATA memory; good idea to initialize all
+*DBS_TX_QUEUES entries.
+*Notice: We always start out with interrupts disabled (by setting
the
+*"irq_vector" argument to -1). Queues that require
interrupts will have
+* it enabled at a later time (after we have enabled vfio
interrupts in the
+* kernel).
+*/
+ int_enable = 0;
+ vec = 0;
+ istk = 0;
+
+ if (set_tx_uw_data(p_nthw_dbs, index,
+ (uint64_t)used_struct_phys_addr,
+ host_id, qs, 0, int_enable, vec, istk, in_order) != 0) {
+ return NULL;
+ }
/*
* 2. Configure the DBS.TX_AM_DATA memory and enable the queues you
plan to use;
diff --git a/drivers/net/ntnic/include/ntnic_dbs.h
b/drivers/net/ntnic/include/ntnic_dbs.h
index 438f1858f5..f3b5a20739 100644
--- a/drivers/net/ntnic/include/ntnic_dbs.h
+++ b/drivers/net/ntnic/include/ntnic_dbs.h
@@ -33,6 +33,29 @@ struct nthw_dbs_tx_am_data_s {
uint32_t int_enable;
};
+/* DBS_RX_UW_DATA */
+struct nthw_dbs_rx_uw_data_s {
+ uint64_t guest_physical_address;
+ uint32_t host_id;
+ uint32_t queue_size;
+ uint32_t packed;
+ uint32_t int_enable;
+ uint32_t vec;
+ uint32_t istk;
+};
+
+/* DBS_TX_UW_DATA */
+struct nthw_dbs_tx_uw_data_s {
+ uint64_t guest_physical_address;
+ uint32_t host_id;
+ uint32_t queue_size;
+ uint32_t packed;
+ uint32_t int_enable;
+ uint32_t vec;
+ uint32_t istk;
+ uint32_t in_order;
+};
+
/* DBS_TX_QP_DATA */
struct nthw_dbs_tx_qp_data_s {
uint32_t virtual_port;
@@ -121,6 +144,33 @@ struct nthw_dbs_s {
nthw_field_t *mp_fld_tx_avail_monitor_data_packed;
nthw_field_t *mp_fld_tx_avail_monitor_data_int;
+ nthw_register_t *mp_reg_rx_used_writer_control;
+ nthw_field_t *mp_fld_rx_used_writer_control
[PATCH v2 41/50] net/ntnic: add packet handler for virtio queues
From: Danylo Vodopianov
Added functionality to handles the copying of segmented queue data
into a rte_mbuf and vice versa.
Added functionality to manages packet transmission for a
specified TX and RX queues.
Signed-off-by: Danylo Vodopianov
---
drivers/net/ntnic/include/ntnic_virt_queue.h | 87 +++-
drivers/net/ntnic/include/ntos_drv.h | 14 +
drivers/net/ntnic/ntnic_ethdev.c | 441 +++
3 files changed, 540 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ntnic/include/ntnic_virt_queue.h
b/drivers/net/ntnic/include/ntnic_virt_queue.h
index 821b23af6c..f8842819e4 100644
--- a/drivers/net/ntnic/include/ntnic_virt_queue.h
+++ b/drivers/net/ntnic/include/ntnic_virt_queue.h
@@ -14,10 +14,93 @@
struct nthw_virt_queue;
#define SPLIT_RING0
+#define PACKED_RING 1
#define IN_ORDER 1
-struct nthw_cvirtq_desc;
+/*
+ * SPLIT : This marks a buffer as continuing via the next field.
+ * PACKED: This marks a buffer as continuing. (packed does not have a next
field, so must be
+ * contiguous) In Used descriptors it must be ignored
+ */
+#define VIRTQ_DESC_F_NEXT 1
+
+/*
+ * Split Ring virtq Descriptor
+ */
+struct __rte_aligned(8) virtq_desc {
+ /* Address (guest-physical). */
+ uint64_t addr;
+ /* Length. */
+ uint32_t len;
+ /* The flags as indicated above. */
+ uint16_t flags;
+ /* Next field if flags & NEXT */
+ uint16_t next;
+};
+
+/* descr phys address must be 16 byte aligned */
+struct __rte_aligned(16) pvirtq_desc {
+ /* Buffer Address. */
+ uint64_t addr;
+ /* Buffer Length. */
+ uint32_t len;
+ /* Buffer ID. */
+ uint16_t id;
+ /* The flags depending on descriptor type. */
+ uint16_t flags;
+};
+
+/*
+ * Common virtq descr
+ */
+#define vq_set_next(vq, index, nxt) \
+do { \
+ struct nthw_cvirtq_desc *temp_vq = (vq); \
+ if (temp_vq->vq_type == SPLIT_RING) \
+ temp_vq->s[index].next = nxt; \
+} while (0)
+
+#define vq_add_flags(vq, index, flgs) \
+do { \
+ struct nthw_cvirtq_desc *temp_vq = (vq); \
+ uint16_t tmp_index = (index); \
+ typeof(flgs) tmp_flgs = (flgs); \
+ if (temp_vq->vq_type == SPLIT_RING) \
+ temp_vq->s[tmp_index].flags |= tmp_flgs; \
+ else if (temp_vq->vq_type == PACKED_RING) \
+ temp_vq->p[tmp_index].flags |= tmp_flgs; \
+} while (0)
+
+#define vq_set_flags(vq, index, flgs) \
+do { \
+ struct nthw_cvirtq_desc *temp_vq = (vq); \
+ uint32_t temp_flags = (flgs); \
+ uint32_t temp_index = (index); \
+ if ((temp_vq)->vq_type == SPLIT_RING) \
+ (temp_vq)->s[temp_index].flags = temp_flags; \
+ else if ((temp_vq)->vq_type == PACKED_RING) \
+ (temp_vq)->p[temp_index].flags = temp_flags; \
+} while (0)
+
+struct nthw_virtq_desc_buf {
+ /* Address (guest-physical). */
+ alignas(16) uint64_t addr;
+ /* Length. */
+ uint32_t len;
+};
+
+struct nthw_cvirtq_desc {
+ union {
+ struct nthw_virtq_desc_buf *b; /* buffer part as is common */
+ struct virtq_desc *s; /* SPLIT */
+ struct pvirtq_desc*p; /* PACKED */
+ };
+ uint16_t vq_type;
+};
-struct nthw_received_packets;
+struct nthw_received_packets {
+ void *addr;
+ uint32_t len;
+};
#endif /* __NTOSS_VIRT_QUEUE_H__ */
diff --git a/drivers/net/ntnic/include/ntos_drv.h
b/drivers/net/ntnic/include/ntos_drv.h
index 933b012e07..d51d1e3677 100644
--- a/drivers/net/ntnic/include/ntos_drv.h
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -27,6 +27,20 @@
#define MAX_QUEUES 125
/* Structs: */
+#define SG_HDR_SIZE12
+
+struct _pkt_hdr_rx {
+ uint32_t cap_len:14;
+ uint32_t fid:10;
+ uint32_t ofs1:8;
+ uint32_t ip_prot:8;
+ uint32_t port:13;
+ uint32_t descr:8;
+ uint32_t descr_12b:1;
+ uint32_t color_type:2;
+ uint32_t color:32;
+};
+
struct nthw_memory_descriptor {
void *phys_addr;
void *virt_addr;
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 57827d73d5..b0ec41e2bb 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -39,9 +39,29 @@
/* Max RSS queues */
#define MAX_QUEUES 125
+#define NUM_VQ_SEGS(_data_size_)
\
+ ({
\
+ size_t _size = (_data_size_);
\
+ size_t _segment_count = ((_size + SG_HDR_SIZE) >
SG_HW_TX_PKT_BUFFER_SIZE)\
+ ? (((_size + SG_HDR_SIZE) + SG_HW_TX_PKT_BUFFER_SIZE -
1) / \
+ SG_HW_TX_PKT_BUFFER_SIZE)
\
+
[PATCH v2 38/50] net/ntnic: enhance Ethernet device configuration
From: Danylo Vodopianov
Added eth_dev_close function to handle closing of Ethernet devices.
It releases managed RX/TX virtual queues.
Initialized scatter-gather queue system.
Defined constants and macros for hardware RX/TX descriptors and
packet buffer sizes.
Defined structures for RX and TX packet headers including
fields for packet length, descriptors, and color types.
Signed-off-by: Danylo Vodopianov
---
drivers/net/ntnic/include/ntnic_dbs.h| 19
drivers/net/ntnic/include/ntnic_virt_queue.h | 22 +
drivers/net/ntnic/include/ntos_drv.h | 15
drivers/net/ntnic/nthw/nthw_drv.h| 1 +
drivers/net/ntnic/ntnic_ethdev.c | 67 ++
drivers/net/ntnic/ntnic_mod_reg.c| 5 ++
drivers/net/ntnic/ntnic_mod_reg.h| 93
7 files changed, 222 insertions(+)
create mode 100644 drivers/net/ntnic/include/ntnic_dbs.h
create mode 100644 drivers/net/ntnic/include/ntnic_virt_queue.h
diff --git a/drivers/net/ntnic/include/ntnic_dbs.h
b/drivers/net/ntnic/include/ntnic_dbs.h
new file mode 100644
index 00..551c6ade43
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_dbs.h
@@ -0,0 +1,19 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTNIC_DBS_H_
+#define _NTNIC_DBS_H_
+
+#include "nthw_fpga_model.h"
+
+/*
+ * Struct for implementation of memory bank shadows
+ */
+
+struct nthw_dbs_s;
+
+typedef struct nthw_dbs_s nthw_dbs_t;
+
+#endif /* _NTNIC_DBS_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_virt_queue.h
b/drivers/net/ntnic/include/ntnic_virt_queue.h
new file mode 100644
index 00..422ac3b950
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_virt_queue.h
@@ -0,0 +1,22 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTOSS_VIRT_QUEUE_H__
+#define __NTOSS_VIRT_QUEUE_H__
+
+#include
+#include
+
+#include
+
+struct nthw_virt_queue;
+
+struct nthw_virtq_desc_buf;
+
+struct nthw_cvirtq_desc;
+
+struct nthw_received_packets;
+
+#endif /* __NTOSS_VIRT_QUEUE_H__ */
diff --git a/drivers/net/ntnic/include/ntos_drv.h
b/drivers/net/ntnic/include/ntos_drv.h
index a77e6a0247..191686a07a 100644
--- a/drivers/net/ntnic/include/ntos_drv.h
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -27,12 +27,25 @@
#define MAX_QUEUES 125
/* Structs: */
+struct nthw_memory_descriptor {
+ void *virt_addr;
+ uint32_t len;
+};
+
+struct hwq_s {
+ int vf_num;
+ struct nthw_memory_descriptor virt_queues_ctrl;
+ struct nthw_memory_descriptor *pkt_buffers;
+};
+
struct __rte_cache_aligned ntnic_rx_queue {
struct flow_queue_id_s queue;/* queue info - user id and hw queue
index */
struct rte_mempool *mb_pool; /* mbuf memory pool */
uint16_t buf_size; /* Size of data area in mbuf */
int enabled; /* Enabling/disabling of this queue */
+ struct hwq_s hwq;
+ struct nthw_virt_queue *vq;
nt_meta_port_type_t type;
uint32_t port; /* Rx port for this queue */
enum fpga_info_profile profile; /* Inline / Capture */
@@ -41,6 +54,8 @@ struct __rte_cache_aligned ntnic_rx_queue {
struct __rte_cache_aligned ntnic_tx_queue {
struct flow_queue_id_s queue; /* queue info - user id and hw queue
index */
+ struct hwq_s hwq;
+ struct nthw_virt_queue *vq;
nt_meta_port_type_t type;
uint32_t port; /* Tx port for this queue */
diff --git a/drivers/net/ntnic/nthw/nthw_drv.h
b/drivers/net/ntnic/nthw/nthw_drv.h
index 41500f49dd..eaa2b19015 100644
--- a/drivers/net/ntnic/nthw/nthw_drv.h
+++ b/drivers/net/ntnic/nthw/nthw_drv.h
@@ -7,6 +7,7 @@
#define __NTHW_DRV_H__
#include "nthw_core.h"
+#include "ntnic_dbs.h"
typedef enum nt_meta_port_type_e {
PORT_TYPE_PHYSICAL,
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 967e989575..79b5ae4d60 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -53,6 +53,8 @@ static const struct rte_pci_id nthw_pci_id_map[] = {
}, /* sentinel */
};
+static const struct sg_ops_s *sg_ops;
+
static rte_spinlock_t hwlock = RTE_SPINLOCK_INITIALIZER;
/*
@@ -183,6 +185,14 @@ eth_dev_infos_get(struct rte_eth_dev *eth_dev, struct
rte_eth_dev_info *dev_info
return 0;
}
+static void release_hw_virtio_queues(struct hwq_s *hwq)
+{
+ if (!hwq || hwq->vf_num == 0)
+ return;
+
+ hwq->vf_num = 0;
+}
+
static void eth_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t
queue_id)
{
(void)eth_dev;
@@ -474,6 +484,21 @@ eth_dev_close(struct rte_eth_dev *eth_dev)
struct pmd_internals *internals = (struct pmd_internals
*)eth_dev->data->dev_private;
struct drv_s *p_drv = internals->p_drv;
+ if (internals->type != PORT_TYPE_VIRTUAL) {
+ struct ntnic_rx_queue *rx_q = internals->rxq_s
[PATCH v2 40/50] net/ntnic: add queue setup operations
From: Danylo Vodopianov
Added TX and RX queue setup. Handles memory allocation
and hardware Virtio queue setup.
Allocates and configures memory for hardware Virtio queues,
including handling IOMMU and VFIO mappings.
Signed-off-by: Danylo Vodopianov
---
drivers/net/ntnic/include/ntnic_virt_queue.h | 3 +-
drivers/net/ntnic/include/ntos_drv.h | 6 +
drivers/net/ntnic/nthw/nthw_drv.h| 2 +
drivers/net/ntnic/ntnic_ethdev.c | 323 +++
4 files changed, 333 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ntnic/include/ntnic_virt_queue.h
b/drivers/net/ntnic/include/ntnic_virt_queue.h
index 422ac3b950..821b23af6c 100644
--- a/drivers/net/ntnic/include/ntnic_virt_queue.h
+++ b/drivers/net/ntnic/include/ntnic_virt_queue.h
@@ -13,7 +13,8 @@
struct nthw_virt_queue;
-struct nthw_virtq_desc_buf;
+#define SPLIT_RING0
+#define IN_ORDER 1
struct nthw_cvirtq_desc;
diff --git a/drivers/net/ntnic/include/ntos_drv.h
b/drivers/net/ntnic/include/ntos_drv.h
index 233d585303..933b012e07 100644
--- a/drivers/net/ntnic/include/ntos_drv.h
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -47,6 +47,7 @@ struct __rte_cache_aligned ntnic_rx_queue {
struct hwq_s hwq;
struct nthw_virt_queue *vq;
+ int nb_hw_rx_descr;
nt_meta_port_type_t type;
uint32_t port; /* Rx port for this queue */
enum fpga_info_profile profile; /* Inline / Capture */
@@ -57,7 +58,12 @@ struct __rte_cache_aligned ntnic_tx_queue {
struct flow_queue_id_s queue; /* queue info - user id and hw queue
index */
struct hwq_s hwq;
struct nthw_virt_queue *vq;
+ int nb_hw_tx_descr;
+ /* Used for bypass in NTDVIO0 header on Tx - pre calculated */
+ int target_id;
nt_meta_port_type_t type;
+ /* only used for exception tx queue from OVS SW switching */
+ int rss_target_id;
uint32_t port; /* Tx port for this queue */
int enabled; /* Enabling/disabling of this queue */
diff --git a/drivers/net/ntnic/nthw/nthw_drv.h
b/drivers/net/ntnic/nthw/nthw_drv.h
index eaa2b19015..69e0360f5f 100644
--- a/drivers/net/ntnic/nthw/nthw_drv.h
+++ b/drivers/net/ntnic/nthw/nthw_drv.h
@@ -71,6 +71,8 @@ typedef struct fpga_info_s {
struct nthw_pcie3 *mp_nthw_pcie3;
struct nthw_tsm *mp_nthw_tsm;
+ nthw_dbs_t *mp_nthw_dbs;
+
uint8_t *bar0_addr; /* Needed for register read/write */
size_t bar0_size;
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 78a689d444..57827d73d5 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -31,10 +31,16 @@
#define MAX_TOTAL_QUEUES 128
+#define SG_NB_HW_RX_DESCRIPTORS 1024
+#define SG_NB_HW_TX_DESCRIPTORS 1024
+#define SG_HW_RX_PKT_BUFFER_SIZE (1024 << 1)
+#define SG_HW_TX_PKT_BUFFER_SIZE (1024 << 1)
+
/* Max RSS queues */
#define MAX_QUEUES 125
#define ONE_G_SIZE 0x4000
+#define ONE_G_MASK (ONE_G_SIZE - 1)
#define ETH_DEV_NTNIC_HELP_ARG "help"
#define ETH_DEV_NTHW_RXQUEUES_ARG "rxqs"
@@ -187,6 +193,157 @@ eth_dev_infos_get(struct rte_eth_dev *eth_dev, struct
rte_eth_dev_info *dev_info
return 0;
}
+static int allocate_hw_virtio_queues(struct rte_eth_dev *eth_dev, int vf_num,
struct hwq_s *hwq,
+ int num_descr, int buf_size)
+{
+ int i, res;
+ uint32_t size;
+ uint64_t iova_addr;
+
+ NT_LOG(DBG, NTNIC, "* Configure IOMMU for HW queues on VF %i
*\n", vf_num);
+
+ /* Just allocate 1MB to hold all combined descr rings */
+ uint64_t tot_alloc_size = 0x10 + buf_size * num_descr;
+
+ void *virt =
+ rte_malloc_socket("VirtQDescr", tot_alloc_size,
nt_util_align_size(tot_alloc_size),
+ eth_dev->data->numa_node);
+
+ if (!virt)
+ return -1;
+
+ uint64_t gp_offset = (uint64_t)virt & ONE_G_MASK;
+ rte_iova_t hpa = rte_malloc_virt2iova(virt);
+
+ NT_LOG(DBG, NTNIC, "Allocated virtio descr rings : virt "
+ "%p [0x%" PRIX64 "],hpa %" PRIX64 " [0x%" PRIX64 "]\n",
+ virt, gp_offset, hpa, hpa & ONE_G_MASK);
+
+ /*
+* Same offset on both HPA and IOVA
+* Make sure 1G boundary is never crossed
+*/
+ if (((hpa & ONE_G_MASK) != gp_offset) ||
+ (((uint64_t)virt + tot_alloc_size) & ~ONE_G_MASK) !=
+ ((uint64_t)virt & ~ONE_G_MASK)) {
+ NT_LOG(ERR, NTNIC,
"*\n");
+ NT_LOG(ERR, NTNIC, "ERROR, no optimal IOMMU mapping available
hpa: %016" PRIX64
+ "(%016" PRIX64 "), gp_offset: %016" PRIX64 " size: %"
PRIu64 "\n",
+ hpa, hpa & ONE_G_MASK, gp_offset, tot_alloc_size);
+ NT_LOG(ERR, NTNIC,
"*\n
[PATCH v2 11/50] net/ntnic: add categorizer (CAT) flow module
From: Oleksandr Kolomeiets
The Categorizer module’s main purpose is to select the behavior
of other modules in the FPGA pipeline, depending on a protocol check.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 51 +
drivers/net/ntnic/include/hw_mod_cat_v18.h| 141 +++
drivers/net/ntnic/include/hw_mod_cat_v21.h| 91 ++
drivers/net/ntnic/meson.build | 1 +
.../nthw/flow_api/flow_backend/flow_backend.c | 465 ++
.../ntnic/nthw/flow_filter/flow_nthw_cat.c| 872 ++
.../ntnic/nthw/flow_filter/flow_nthw_cat.h| 291 ++
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../nthw/supported/nthw_fpga_reg_defs_cat.h | 238 +
10 files changed, 2152 insertions(+)
create mode 100644 drivers/net/ntnic/include/hw_mod_cat_v18.h
create mode 100644 drivers/net/ntnic/include/hw_mod_cat_v21.h
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 11a0d62c41..ce2c0cf7cf 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -6,8 +6,40 @@
#ifndef _HW_MOD_BACKEND_H_
#define _HW_MOD_BACKEND_H_
+#include
+
+#include "hw_mod_cat_v18.h"
+#include "hw_mod_cat_v21.h"
+
#define MAX_PHYS_ADAPTERS 8
+#define COMMON_FUNC_INFO_S
\
+ int ver;
\
+ void *base;
\
+ unsigned int alloced_size;
\
+ int debug
+
+struct cat_func_s {
+ COMMON_FUNC_INFO_S;
+ uint32_t nb_cat_funcs;
+ uint32_t nb_flow_types;
+ uint32_t nb_pm_ext;
+ uint32_t nb_len;
+ uint32_t kcc_size;
+ uint32_t cts_num;
+ uint32_t kcc_banks;
+ uint32_t kcc_id_bit_size;
+ uint32_t kcc_records;
+ uint32_t km_if_count;
+ int32_t km_if_m0;
+ int32_t km_if_m1;
+
+ union {
+ struct hw_mod_cat_v18_s v18;
+ struct hw_mod_cat_v21_s v21;
+ };
+};
+
enum debug_mode_e {
FLOW_BACKEND_DEBUG_MODE_NONE = 0x,
FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001
@@ -61,6 +93,25 @@ struct flow_api_backend_ops {
int (*alloc_rx_queue)(void *dev, int queue_id);
int (*free_rx_queue)(void *dev, int hw_queue);
+
+ /* CAT */
+ bool (*get_cat_present)(void *dev);
+ uint32_t (*get_cat_version)(void *dev);
+ int (*cat_cfn_flush)(void *dev, const struct cat_func_s *cat, int
cat_func, int cnt);
+ int (*cat_kce_flush)(void *dev, const struct cat_func_s *cat, int
km_if_idx, int index,
+ int cnt);
+ int (*cat_kcs_flush)(void *dev, const struct cat_func_s *cat, int
km_if_idx, int cat_func,
+ int cnt);
+ int (*cat_fte_flush)(void *dev, const struct cat_func_s *cat, int
km_if_idx, int index,
+ int cnt);
+ int (*cat_cte_flush)(void *dev, const struct cat_func_s *cat, int
cat_func, int cnt);
+ int (*cat_cts_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
+ int (*cat_cot_flush)(void *dev, const struct cat_func_s *cat, int
cat_func, int cnt);
+ int (*cat_cct_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
+ int (*cat_exo_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
+ int (*cat_rck_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
+ int (*cat_len_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
+ int (*cat_kcc_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
};
struct flow_api_backend_s {
diff --git a/drivers/net/ntnic/include/hw_mod_cat_v18.h
b/drivers/net/ntnic/include/hw_mod_cat_v18.h
new file mode 100644
index 00..7ba38207a0
--- /dev/null
+++ b/drivers/net/ntnic/include/hw_mod_cat_v18.h
@@ -0,0 +1,141 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _HW_MOD_CAT_V18_H_
+#define _HW_MOD_CAT_V18_H_
+
+#include
+
+struct cat_v18_cfn_s {
+ uint32_t enable;
+ uint32_t inv;
+ /* protocol checks */
+ uint32_t ptc_inv;
+ uint32_t ptc_isl;
+ uint32_t ptc_cfp;
+ uint32_t ptc_mac;
+ uint32_t ptc_l2;
+ uint32_t ptc_vntag;
+ uint32_t ptc_vlan;
+ uint32_t ptc_mpls;
+ uint32_t ptc_l3;
+ uint32_t ptc_frag;
+ uint32_t ptc_ip_prot;
+ uint32_t ptc_l4;
+ uint32_t ptc
[PATCH v2 10/50] net/ntnic: add INFO flow module
From: Oleksandr Kolomeiets
The info module keeps track of the hardcoded parameters of the FPGA
and provides an abstraction that can support if parameter is unsupported
for a given FPGA.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 57 +++
drivers/net/ntnic/meson.build | 3 +
.../nthw/flow_api/flow_backend/flow_backend.c | 384 ++
.../ntnic/nthw/flow_filter/flow_nthw_info.c | 341
.../ntnic/nthw/flow_filter/flow_nthw_info.h | 110 +
drivers/net/ntnic/nthw/nthw_drv.h | 2 +
drivers/net/ntnic/nthw/nthw_helper.h | 11 +
drivers/net/ntnic/ntnic_mod_reg.c | 8 +
drivers/net/ntnic/ntnic_mod_reg.h | 2 +
drivers/net/ntnic/ntutil/nt_util.h| 5 +
10 files changed, 923 insertions(+)
create mode 100644 drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_info.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_info.h
create mode 100644 drivers/net/ntnic/nthw/nthw_helper.h
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 46054a6a85..11a0d62c41 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -6,6 +6,63 @@
#ifndef _HW_MOD_BACKEND_H_
#define _HW_MOD_BACKEND_H_
+#define MAX_PHYS_ADAPTERS 8
+
+enum debug_mode_e {
+ FLOW_BACKEND_DEBUG_MODE_NONE = 0x,
+ FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001
+};
+
+struct flow_api_backend_ops {
+ int version;
+ int (*set_debug_mode)(void *dev, enum debug_mode_e mode);
+ int (*get_nb_phy_port)(void *dev);
+ int (*get_nb_rx_port)(void *dev);
+ int (*get_ltx_avail)(void *dev);
+ int (*get_nb_cat_funcs)(void *dev);
+ int (*get_nb_categories)(void *dev);
+ int (*get_nb_cat_km_if_cnt)(void *dev);
+ int (*get_nb_cat_km_if_m0)(void *dev);
+ int (*get_nb_cat_km_if_m1)(void *dev);
+
+ int (*get_nb_queues)(void *dev);
+ int (*get_nb_km_flow_types)(void *dev);
+ int (*get_nb_pm_ext)(void *dev);
+ int (*get_nb_len)(void *dev);
+ int (*get_kcc_size)(void *dev);
+ int (*get_kcc_banks)(void *dev);
+ int (*get_nb_km_categories)(void *dev);
+ int (*get_nb_km_cam_banks)(void *dev);
+ int (*get_nb_km_cam_record_words)(void *dev);
+ int (*get_nb_km_cam_records)(void *dev);
+ int (*get_nb_km_tcam_banks)(void *dev);
+ int (*get_nb_km_tcam_bank_width)(void *dev);
+ int (*get_nb_flm_categories)(void *dev);
+ int (*get_nb_flm_size_mb)(void *dev);
+ int (*get_nb_flm_entry_size)(void *dev);
+ int (*get_nb_flm_variant)(void *dev);
+ int (*get_nb_flm_prios)(void *dev);
+ int (*get_nb_flm_pst_profiles)(void *dev);
+ int (*get_nb_flm_scrub_profiles)(void *dev);
+ int (*get_nb_flm_load_aps_max)(void *dev);
+ int (*get_nb_qsl_categories)(void *dev);
+ int (*get_nb_qsl_qst_entries)(void *dev);
+ int (*get_nb_pdb_categories)(void *dev);
+ int (*get_nb_roa_categories)(void *dev);
+ int (*get_nb_tpe_categories)(void *dev);
+ int (*get_nb_tx_cpy_writers)(void *dev);
+ int (*get_nb_tx_cpy_mask_mem)(void *dev);
+ int (*get_nb_tx_rpl_depth)(void *dev);
+ int (*get_nb_tx_rpl_ext_categories)(void *dev);
+ int (*get_nb_tpe_ifr_categories)(void *dev);
+ int (*get_nb_rpp_per_ps)(void *dev);
+ int (*get_nb_hsh_categories)(void *dev);
+ int (*get_nb_hsh_toeplitz)(void *dev);
+
+ int (*alloc_rx_queue)(void *dev, int queue_id);
+ int (*free_rx_queue)(void *dev, int hw_queue);
+};
+
struct flow_api_backend_s {
void *be_dev;
};
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 00b1ae4c70..b771a600e4 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -17,6 +17,7 @@ includes = [
include_directories('nthw'),
include_directories('nthw/supported'),
include_directories('nthw/model'),
+include_directories('nthw/flow_filter'),
include_directories('nim/'),
]
@@ -43,7 +44,9 @@ sources = files(
'nthw/core/nthw_sdc.c',
'nthw/core/nthw_si5340.c',
'nthw/flow_api/flow_api.c',
+'nthw/flow_api/flow_backend/flow_backend.c',
'nthw/flow_api/flow_filter.c',
+'nthw/flow_filter/flow_nthw_info.c',
'nthw/model/nthw_fpga_model.c',
'nthw/nthw_platform.c',
'nthw/nthw_rac.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
new file mode 100644
index 00..f3ad3686d4
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -0,0 +1,384 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 20
[PATCH v2 05/50] net/ntnic: extend and fix logging implementation
From: Danylo Vodopianov
Add suffixes logging
Fix the issue with the configuration log level for a specific module
Fix extended debug logging
3-letter abbreviation for log type
Update documentation
new log modules were added
Log level in functions that initialize feature operations
was updated from INFO to DEBUG to avoid noisy traces
during driver startup.
log level for ops init was changed
nim and PMD modules was replaced with NTNIC
NIM module was replaced with NTNIC according to the ntnic log
convention.
Signed-off-by: Oleksandr Kolomeiets
Signed-off-by: Danylo Vodopianov
---
v2
* Update release notes
---
doc/guides/nics/ntnic.rst | 29 +
doc/guides/rel_notes/release_24_11.rst| 1 +
drivers/net/ntnic/nim/i2c_nim.c | 16 ++---
.../nthw/core/nt200a0x/nthw_fpga_nt200a0x.c | 2 +-
.../core/nt200a0x/reset/nthw_fpga_rst9563.c | 12 ++--
.../nt200a0x/reset/nthw_fpga_rst_nt200a0x.c | 10 +--
drivers/net/ntnic/nthw/core/nthw_iic.c| 6 +-
drivers/net/ntnic/nthw/core/nthw_pcie3.c | 2 +-
.../net/ntnic/nthw/model/nthw_fpga_model.c| 6 +-
drivers/net/ntnic/ntlog/ntlog.c | 2 -
drivers/net/ntnic/ntlog/ntlog.h | 63 +--
drivers/net/ntnic/ntnic_ethdev.c | 41 ++--
12 files changed, 124 insertions(+), 66 deletions(-)
diff --git a/doc/guides/nics/ntnic.rst b/doc/guides/nics/ntnic.rst
index 88d95832e5..7ac92c891c 100644
--- a/doc/guides/nics/ntnic.rst
+++ b/doc/guides/nics/ntnic.rst
@@ -49,3 +49,32 @@ which is required for the PMD to use vfio-pci on the PF.
This support has been back-ported to older Linux distributions
and they are also supported.
If vfio-pci is not required, kernel version 4.18 is supported.
+
+
+Logging and Debugging
+-
+
+NTNIC supports several groups of logging that can be enabled with
``--log-level``
+parameter:
+
+- NTNIC.
+
+Logging info from the main PMD code. i.e. code that is related to DPDK::
+
+--log-level=pmd.net.ntnic.ntnic,8
+
+- NTHW.
+
+Logging info from NTHW. i.e. code that is related to the FPGA and the
Adapter::
+
+--log-level=pmd.net.ntnic.nthw,8
+
+- FILTER.
+
+Logging info from filter. i.e. code that is related to the binary filter::
+
+--log-level=pmd.net.ntnic.filter,8
+
+To enable logging on all levels use wildcard in the following way::
+
+--log-level=pmd.net.ntnic.*,8
diff --git a/doc/guides/rel_notes/release_24_11.rst
b/doc/guides/rel_notes/release_24_11.rst
index c808639ee9..a126dcfcb9 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -103,6 +103,7 @@ New Features
* Update supported version of the FPGA to 9563.55.49
* Fix Coverity issues
* Fix issues related to release 24.07
+ * Extended and fixed the implementation of the logging
Removed Items
-
diff --git a/drivers/net/ntnic/nim/i2c_nim.c b/drivers/net/ntnic/nim/i2c_nim.c
index e6e256b062..310d5d2598 100644
--- a/drivers/net/ntnic/nim/i2c_nim.c
+++ b/drivers/net/ntnic/nim/i2c_nim.c
@@ -219,7 +219,7 @@ static int i2c_nim_common_construct(nim_i2c_ctx_p ctx)
res = -1;
if (res) {
- NT_LOG(ERR, PMD, "Can't read NIM id.");
+ NT_LOG(ERR, NTNIC, "Can't read NIM id.");
return res;
}
@@ -308,7 +308,7 @@ static int qsfp_nim_state_build(nim_i2c_ctx_t *ctx,
sfp_nim_state_t *state)
break;
default:
- NT_LOG(INF, NIM, "nim_id = %u is not an QSFP/QSFP+/QSFP28
module\n", ctx->nim_id);
+ NT_LOG(INF, NTNIC, "nim_id = %u is not an QSFP/QSFP+/QSFP28
module\n", ctx->nim_id);
res = -1;
}
@@ -419,7 +419,7 @@ static int qsfpplus_read_basic_data(nim_i2c_ctx_t *ctx)
yes_no[ctx->avg_pwr]);
qsfp_read_vendor_info(ctx);
- NT_LOG(DBG, PMD,
+ NT_LOG(DBG, NTNIC,
"Instance %d: NIM info: (Vendor: %s, PN: %s, SN: %s, Date: %s,
Rev: %s)\n",
ctx->instance, ctx->vendor_name, ctx->prod_no, ctx->serial_no,
ctx->date, ctx->rev);
@@ -540,7 +540,7 @@ static bool qsfp28_is_rate_selection_enabled(nim_i2c_ctx_p
ctx)
(read_byte(ctx, enh_options_reg_addr) >> 2) & 0x03; /* bit
3..2 */
if (rate_select_type != 2) {
- NT_LOG(DBG, PMD, "NIM has unhandled rate select type (%d)",
rate_select_type);
+ NT_LOG(DBG, NTNIC, "NIM has unhandled rate select type (%d)",
rate_select_type);
return false;
}
@@ -548,7 +548,7 @@ static bool qsfp28_is_rate_selection_enabled(nim_i2c_ctx_p
ctx)
read_byte(ctx, ext_rate_select_compl_reg_addr) & 0x03; /* bit
1..0 */
if (ext_rate_select_ver != 0x02) {
- NT_LOG(DBG, PMD, "NIM has unhandled extended rate select
version (%d)",
+ NT_LOG(DBG, NTNIC
[PATCH v2 02/50] net/ntnic: fix coverity issues:
From: Danylo Vodopianov
CI founc couple coverity problems which were fixed in this commit.
CID 440550, 440551, 440545, 440553, 440552, 440547:
Null pointer dereferences (REVERSE_INULL)
These issues were fixed by reworking variable NULL checking and adding
NULL checking before var using.
CID 440543: Incorrect expression (IDENTICAL_BRANCHES)
This issue was fixed by removing useless if statements from the code.
CID 440548: Null pointer dereferences (FORWARD_NULL)
This issue was fixed by adding NULL checking before
mp_fld_rst_serdes_rx var using.
CID 440546: Resource leaks (RESOURCE_LEAK)
This issue was fixed by moving NULL checking before var using.
CID 440540: Error handling issues (CHECKED_RETURN)
This issue was fixed with return value checking adding.
CID 440549: (OVERRUN)
This issue was fixed with array edge values fixing.
Coverity issue: 440550
Fixes: 51052594f795 ("net/ntnic: add physical layer control module")
Signed-off-by: Danylo Vodopianov
---
v2
* Update release notes
---
.mailmap | 1 +
doc/guides/rel_notes/release_24_11.rst| 1 +
.../nt200a0x/reset/nthw_fpga_rst_nt200a0x.c | 2 +-
drivers/net/ntnic/nthw/core/nthw_fpga.c | 24
drivers/net/ntnic/nthw/core/nthw_hif.c| 18 +-
.../net/ntnic/nthw/model/nthw_fpga_model.c| 58 ++-
drivers/net/ntnic/ntnic_ethdev.c | 21 +++
drivers/net/ntnic/ntnic_vfio.c| 5 +-
drivers/net/ntnic/ntutil/nt_util.c| 3 +-
9 files changed, 67 insertions(+), 66 deletions(-)
diff --git a/.mailmap b/.mailmap
index 959c45a2d3..6b095a7449 100644
--- a/.mailmap
+++ b/.mailmap
@@ -295,6 +295,7 @@ Dan Nowlin
Danny Patel
Danny Zhou
Dan Wei
+Danylo Vodopianov
Dapeng Yu
Darek Stojaczyk
Daria Kolistratova
diff --git a/doc/guides/rel_notes/release_24_11.rst
b/doc/guides/rel_notes/release_24_11.rst
index 4131b7dc57..e85549c1e1 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -101,6 +101,7 @@ New Features
* **Update Napatech ntnic net driver [EXPERIMENTAL].**
* Update supported version of the FPGA to 9563.55.49
+ * Fix Coverity issues
Removed Items
-
diff --git
a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c
b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c
index ea0276a90c..aa0d97dafd 100644
--- a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c
@@ -263,7 +263,7 @@ static int nthw_fpga_rst_nt200a0x_reset(nthw_fpga_t *p_fpga,
if (p->mp_fld_rst_serdes_rx)
nthw_field_set_flush(p->mp_fld_rst_serdes_rx); /* 0x03 2 ports
*/
- if (p->mp_fld_rst_serdes_rx_datapath) {
+ if (p->mp_fld_rst_serdes_rx_datapath && p->mp_fld_rst_serdes_rx) {
nthw_field_set_flush(p->mp_fld_rst_serdes_rx_datapath);
nthw_field_clr_flush(p->mp_fld_rst_serdes_rx);
}
diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga.c
b/drivers/net/ntnic/nthw/core/nthw_fpga.c
index d70205e5e3..082d3950bb 100644
--- a/drivers/net/ntnic/nthw/core/nthw_fpga.c
+++ b/drivers/net/ntnic/nthw/core/nthw_fpga.c
@@ -217,19 +217,19 @@ int nthw_fpga_init(struct fpga_info_s *p_fpga_info)
n_fpga_ident = p_fpga_info->n_fpga_ident;
p_fpga_mgr = nthw_fpga_mgr_new();
- nthw_fpga_mgr_init(p_fpga_mgr, nthw_fpga_instances,
- (const void *)sa_nthw_fpga_mod_str_map);
- nthw_fpga_mgr_log_dump(p_fpga_mgr);
- p_fpga = nthw_fpga_mgr_query_fpga(p_fpga_mgr, n_fpga_ident,
p_fpga_info);
- p_fpga_info->mp_fpga = p_fpga;
-
- if (p_fpga == NULL) {
- NT_LOG(ERR, NTHW, "%s: Unsupported FPGA: %s (%08X)\n",
p_adapter_id_str,
- s_fpga_prod_ver_rev_str,
p_fpga_info->n_fpga_build_time);
- return -1;
- }
-
if (p_fpga_mgr) {
+ nthw_fpga_mgr_init(p_fpga_mgr, nthw_fpga_instances,
+ (const void *)sa_nthw_fpga_mod_str_map);
+ nthw_fpga_mgr_log_dump(p_fpga_mgr);
+ p_fpga = nthw_fpga_mgr_query_fpga(p_fpga_mgr, n_fpga_ident,
p_fpga_info);
+ p_fpga_info->mp_fpga = p_fpga;
+
+ if (p_fpga == NULL) {
+ NT_LOG(ERR, NTHW, "%s: Unsupported FPGA: %s (%08X)\n",
p_adapter_id_str,
+ s_fpga_prod_ver_rev_str,
p_fpga_info->n_fpga_build_time);
+ return -1;
+ }
+
nthw_fpga_mgr_delete(p_fpga_mgr);
p_fpga_mgr = NULL;
}
diff --git a/drivers/net/ntnic/nthw/core/nthw_hif.c
b/drivers/net/ntnic/nthw/core/nthw_hif.c
index f05e1a0c51..cc2aaf83e4 100644
--- a/drivers/net/ntnic/nthw/core/nthw_hif.c
+++ b/drivers/net/ntnic/nthw/core/nthw_hif.c
@@ -83,23 +83,11 @@ int nthw_hif_init(nthw_hif_t *p, nthw_fpga_t *
[PATCH v2 14/50] net/ntnic: add IP fragmenter (IFR) flow module
From: Oleksandr Kolomeiets
The IP Fragmenter module can fragment outgoing packets
based on a programmable MTU.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/meson.build | 1 +
.../nthw/flow_api/flow_backend/flow_backend.c | 12
.../ntnic/nthw/flow_filter/flow_nthw_ifr.c| 68 +++
.../ntnic/nthw/flow_filter/flow_nthw_ifr.h| 43
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../nthw/supported/nthw_fpga_reg_defs_ifr.h | 42
7 files changed, 168 insertions(+)
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_ifr.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_ifr.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 317b696d5f..1ca34d8b47 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -48,6 +48,7 @@ sources = files(
'nthw/flow_api/flow_filter.c',
'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_flm.c',
+'nthw/flow_filter/flow_nthw_ifr.c',
'nthw/flow_filter/flow_nthw_info.c',
'nthw/flow_filter/flow_nthw_km.c',
'nthw/model/nthw_fpga_model.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
index 8703a4c712..5d2c09d52a 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -6,6 +6,7 @@
#include
#include "flow_nthw_info.h"
+#include "flow_nthw_ifr.h"
#include "flow_nthw_cat.h"
#include "flow_nthw_km.h"
#include "flow_nthw_flm.h"
@@ -27,6 +28,7 @@ static struct backend_dev_s {
struct cat_nthw *p_cat_nthw;
struct km_nthw *p_km_nthw;
struct flm_nthw *p_flm_nthw;
+ struct ifr_nthw *p_ifr_nthw;/* TPE module */
} be_devs[MAX_PHYS_ADAPTERS];
#define CHECK_DEBUG_ON(be, mod, inst)
\
@@ -1407,6 +1409,16 @@ const struct flow_api_backend_ops
*bin_flow_backend_init(nthw_fpga_t *p_fpga, vo
be_devs[physical_adapter_no].p_flm_nthw = NULL;
}
+ /* Init nthw IFR */
+ if (ifr_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) {
+ struct ifr_nthw *ifrnthw = ifr_nthw_new();
+ ifr_nthw_init(ifrnthw, p_fpga, physical_adapter_no);
+ be_devs[physical_adapter_no].p_ifr_nthw = ifrnthw;
+
+ } else {
+ be_devs[physical_adapter_no].p_ifr_nthw = NULL;
+ }
+
be_devs[physical_adapter_no].adapter_no = physical_adapter_no;
*dev = (void *)&be_devs[physical_adapter_no];
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_ifr.c
b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_ifr.c
new file mode 100644
index 00..849c599e32
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_ifr.c
@@ -0,0 +1,68 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include
+#include
+
+#include "ntlog.h"
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "flow_nthw_ifr.h"
+
+struct ifr_nthw *ifr_nthw_new(void)
+{
+ struct ifr_nthw *p = malloc(sizeof(struct ifr_nthw));
+
+ if (p)
+ (void)memset(p, 0, sizeof(*p));
+
+ return p;
+}
+
+int ifr_nthw_init(struct ifr_nthw *p, nthw_fpga_t *p_fpga, int n_instance)
+{
+ const char *const p_adapter_id_str =
p_fpga->p_fpga_info->mp_adapter_id_str;
+ nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_IFR,
n_instance);
+
+ assert(n_instance >= 0 && n_instance < 256);
+
+ if (p == NULL)
+ return p_mod == NULL ? -1 : 0;
+
+ if (p_mod == NULL) {
+ NT_LOG(ERR, NTHW, "%s: Ifr %d: no such instance\n",
p_adapter_id_str, n_instance);
+ return -1;
+ }
+
+ p->mp_fpga = p_fpga;
+ p->m_physical_adapter_no = (uint8_t)n_instance;
+ p->m_ifr = nthw_fpga_query_module(p_fpga, MOD_IFR, n_instance);
+
+ p->mp_rcp_ctrl = nthw_module_get_register(p->m_ifr, IFR_RCP_CTRL);
+ p->mp_rcp_addr = nthw_register_get_field(p->mp_rcp_ctrl,
IFR_RCP_CTRL_ADR);
+ p->mp_rcp_cnt = nthw_register_get_field(p->mp_rcp_ctrl,
IFR_RCP_CTRL_CNT);
+
+ p->mp_rcp_data = nthw_module_get_register(p->m_ifr, IFR_RCP_DATA);
+ p->mp_rcp_data_ipv4_en = nthw_register_query_field(p->mp_rcp_data,
IFR_RCP_DATA_IPV4_EN);
+ p->mp_rcp_data_ipv6_en = nthw_register_query_field(p->mp_rcp_data,
IFR_RCP_DATA_IPV6_EN);
+ p->mp_rcp_data_mtu = nthw_register_get_field(p->mp_rcp_data,
IFR_RCP_DATA_MTU);
+ p->mp_rcp_data_ipv4_df_drop =
+ nthw_register_query_field(p->mp_rcp_data,
IFR_RCP_DATA_IPV4_DF_DROP);
+ p->mp_rcp_data_
Re: [PATCH v3 1/1] eal: add C++ include guard in generic/rte_vect.h
On Tue, 2 Apr 2024 09:19:23 -0700
Tyler Retzlaff wrote:
> On Sun, Mar 17, 2024 at 08:44:15PM -0600, Ashish Sadanandan wrote:
> > The header was missing the extern "C" directive which causes name
> > mangling of functions by C++ compilers, leading to linker errors
> > complaining of undefined references to these functions.
> >
> > Also updated the coding style contribution guideline with a new
> > "Language Linkage" section stating `extern "C"` block should be added to
> > public headers.
> >
> > Fixes: 86c743cf9140 ("eal: define generic vector types")
> > Cc: nelio.laranje...@6wind.com
> > Cc: sta...@dpdk.org
> >
> > Signed-off-by: Ashish Sadanandan
> > ---
> Acked-by: Tyler Retzlaff
>
Acked-by: Stephen Hemminger
RE: [EXTERNAL] [PATCH v2] cryptodev: add ec points to sm2 op
> -Original Message-
> From: Akhil Goyal
> Sent: Thursday, October 3, 2024 4:39 PM
> To: Kusztal, ArkadiuszX ; dev@dpdk.org
> Cc: Dooley, Brian
> Subject: RE: [EXTERNAL] [PATCH v2] cryptodev: add ec points to sm2 op
>
> > In the case when PMD cannot support the full process of the SM2, but
> > elliptic curve computation only, additional fields are needed to
> > handle such a case.
> >
> > Points C1, kP therefore were added to the SM2 crypto operation struct.
> >
> > Signed-off-by: Arkadiusz Kusztal
> > ---
> > lib/cryptodev/rte_crypto_asym.h | 119
> > -
> > ---
> > 1 file changed, 71 insertions(+), 48 deletions(-)
> >
> > diff --git a/lib/cryptodev/rte_crypto_asym.h
> > b/lib/cryptodev/rte_crypto_asym.h index 39d3da3952..f59759062f 100644
> > --- a/lib/cryptodev/rte_crypto_asym.h
> > +++ b/lib/cryptodev/rte_crypto_asym.h
> > @@ -600,40 +600,6 @@ struct rte_crypto_ecpm_op_param { };
> >
> > /**
> > - * Asymmetric crypto transform data
> > - *
> > - * Structure describing asym xforms.
> > - */
> > -struct rte_crypto_asym_xform {
> > - struct rte_crypto_asym_xform *next;
> > - /**< Pointer to next xform to set up xform chain.*/
> > - enum rte_crypto_asym_xform_type xform_type;
> > - /**< Asymmetric crypto transform */
> > -
> > - union {
> > - struct rte_crypto_rsa_xform rsa;
> > - /**< RSA xform parameters */
> > -
> > - struct rte_crypto_modex_xform modex;
> > - /**< Modular Exponentiation xform parameters */
> > -
> > - struct rte_crypto_modinv_xform modinv;
> > - /**< Modular Multiplicative Inverse xform parameters */
> > -
> > - struct rte_crypto_dh_xform dh;
> > - /**< DH xform parameters */
> > -
> > - struct rte_crypto_dsa_xform dsa;
> > - /**< DSA xform parameters */
> > -
> > - struct rte_crypto_ec_xform ec;
> > - /**< EC xform parameters, used by elliptic curve based
> > -* operations.
> > -*/
> > - };
> > -};
> > -
> > -/**
> > * SM2 operation params.
> > */
> > struct rte_crypto_sm2_op_param {
> > @@ -658,20 +624,43 @@ struct rte_crypto_sm2_op_param {
> > * will be overwritten by the PMD with the decrypted length.
> > */
> >
> > - rte_crypto_param cipher;
> > - /**<
> > -* Pointer to input data
> > -* - to be decrypted for SM2 private decrypt.
> > -*
> > -* Pointer to output data
> > -* - for SM2 public encrypt.
> > -* In this case the underlying array should have been allocated
> > -* with enough memory to hold ciphertext output (at least X bytes
> > -* for prime field curve of N bytes and for message M bytes,
> > -* where X = (C1 || C2 || C3) and computed based on SM2 RFC as
> > -* C1 (1 + N + N), C2 = M, C3 = N. The cipher.length field will
> > -* be overwritten by the PMD with the encrypted length.
> > -*/
> > + union {
> > + rte_crypto_param cipher;
> > + /**<
> > +* Pointer to input data
> > +* - to be decrypted for SM2 private decrypt.
> > +*
> > +* Pointer to output data
> > +* - for SM2 public encrypt.
> > +* In this case the underlying array should have been allocated
> > +* with enough memory to hold ciphertext output (at least X
> > bytes
> > +* for prime field curve of N bytes and for message M bytes,
> > +* where X = (C1 || C2 || C3) and computed based on SM2 RFC
> > as
> > +* C1 (1 + N + N), C2 = M, C3 = N. The cipher.length field will
> > +* be overwritten by the PMD with the encrypted length.
> > +*/
> > + struct {
> > + struct rte_crypto_ec_point C1;
> > + /**<
> > +* This field is used only when PMD does not support
> the
> > full
> > +* process of the SM2 encryption/decryption, but the
> > elliptic
> > +* curve part only.
> > +*
> > +* In the case of encryption, it is an output - point
> > C1 =
> > (x1,y1).
> > +* In the case of decryption, if is an input - point C1
> > =
> > (x1,y1)
> > +*
> > +*/
> > + struct rte_crypto_ec_point kP;
> > + /**<
> > +* This field is used only when PMD does not support
> the
> > full
> > +* process of the SM2 encryption/decryption, but the
> > elliptic
> > +* curve part only.
> > +*
> > +* It is an output in the encryption case, it is a point
> > +* [k]P = (x2,y2)
> > +*/
> > + };
> > + };
> >
> > rte_crypto_uint id;
> > /**< The SM2 id used by signer and verifier. */ @@ -698,6 +687,40 @@
> > struct rte_crypto_sm
Re: [PATCH v1] crypto/ipsec_mb: bump minimum IPsec MB version
Acked-by: Kai Ji Any release doc needs to be updated ? From: Dooley, Brian Sent: 04 October 2024 15:58 To: Ji, Kai ; De Lara Guarch, Pablo Cc: dev@dpdk.org ; gak...@marvell.com ; wathsala.vithan...@arm.com ; Dooley, Brian Subject: [PATCH v1] crypto/ipsec_mb: bump minimum IPsec MB version AESNI_MB SW PMDs increment Intel IPsec MB version to 1.4. A minimum IPsec Multi-buffer version of 1.4 or greater is now required for the 24.11 LTS release. Signed-off-by: Brian Dooley --- This patch relates to a deprecation notice sent in the 24.03 release. Intel IPsec MB minimum version being bumped to 1.4 for the 24.11 release. https://patches.dpdk.org/project/dpdk/patch/20240314103731.3242086-2-brian.doo...@intel.com/ --- doc/guides/cryptodevs/aesni_gcm.rst | 3 +- doc/guides/cryptodevs/aesni_mb.rst | 3 +- doc/guides/cryptodevs/chacha20_poly1305.rst | 3 +- doc/guides/cryptodevs/kasumi.rst| 3 +- doc/guides/cryptodevs/snow3g.rst| 3 +- doc/guides/cryptodevs/zuc.rst | 3 +- drivers/crypto/ipsec_mb/ipsec_mb_ops.c | 24 --- drivers/crypto/ipsec_mb/meson.build | 2 +- drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 164 drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 9 -- 10 files changed, 13 insertions(+), 204 deletions(-) diff --git a/doc/guides/cryptodevs/aesni_gcm.rst b/doc/guides/cryptodevs/aesni_gcm.rst index 3af1486553..7592d33da2 100644 --- a/doc/guides/cryptodevs/aesni_gcm.rst +++ b/doc/guides/cryptodevs/aesni_gcm.rst @@ -74,7 +74,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.11 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/aesni_mb.rst b/doc/guides/cryptodevs/aesni_mb.rst index 3c77d0f463..c2f6633ee6 100644 --- a/doc/guides/cryptodevs/aesni_mb.rst +++ b/doc/guides/cryptodevs/aesni_mb.rst @@ -132,7 +132,8 @@ and the Multi-Buffer library version supported by them: DPDK versionMulti-buffer library version == 20.11 - 21.08 0.53 - 1.3 - 21.11+ 1.0 - 1.5 + 21.11 - 24.07 1.0 - 1.5 + 24.11+ 1.4 - 1.5 == Initialization diff --git a/doc/guides/cryptodevs/chacha20_poly1305.rst b/doc/guides/cryptodevs/chacha20_poly1305.rst index 44cff85918..b5a980b247 100644 --- a/doc/guides/cryptodevs/chacha20_poly1305.rst +++ b/doc/guides/cryptodevs/chacha20_poly1305.rst @@ -66,7 +66,8 @@ and the external crypto libraries supported by them: = DPDK version Crypto library version = - 21.11+ Multi-buffer library 1.0-1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/kasumi.rst b/doc/guides/cryptodevs/kasumi.rst index 4070f025e1..b57f18b56f 100644 --- a/doc/guides/cryptodevs/kasumi.rst +++ b/doc/guides/cryptodevs/kasumi.rst @@ -80,7 +80,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.02 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/snow3g.rst b/doc/guides/cryptodevs/snow3g.rst index 6eb8229fb5..fb4e0448ac 100644 --- a/doc/guides/cryptodevs/snow3g.rst +++ b/doc/guides/cryptodevs/snow3g.rst @@ -89,7 +89,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.02 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/zuc.rst b/doc/guides/cryptodevs/zuc.rst index 29fe6279aa..4615562246 100644 --- a/doc/guides/cryptodevs/zuc.rst +++ b/doc/guides/cryptodevs/zuc.rst @@ -88,7 +88,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.02 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07
RE: [PATCH v1] crypto/ipsec_mb: bump minimum IPsec MB version
> -Original Message- > From: Dooley, Brian > Sent: Friday, October 4, 2024 3:58 PM > To: Ji, Kai ; De Lara Guarch, Pablo > > Cc: dev@dpdk.org; gak...@marvell.com; wathsala.vithan...@arm.com; > Dooley, Brian > Subject: [PATCH v1] crypto/ipsec_mb: bump minimum IPsec MB version > > AESNI_MB SW PMDs increment Intel IPsec MB version to 1.4. > A minimum IPsec Multi-buffer version of 1.4 or greater is now required for the > 24.11 LTS release. > > Signed-off-by: Brian Dooley Acked-by: Pablo de Lara
Re: [PATCH v2] vhost: restrict set max queue pair API to VDUSE
On 10/3/24 10:11, Maxime Coquelin wrote:
In order to avoid breaking Vhost-user live-migration, we want the
rte_vhost_driver_set_max_queue_num API to only be effective with
VDUSE.
Furthermore, this API is only really needed for VDUSE where the
device number of queues is defined by the backend. For Vhost-user,
this is defined by the frontend (e.g. QEMU), so the advantages of
restricting more the maximum number of queue pairs is limited to
a small memory gain (a handful of pointers).
Fixes: 4aa1f88ac13d ("vhost: add API to set max queue pairs")
Cc: sta...@dpdk.org
Reported-by: Yu Jiang
Signed-off-by: Maxime Coquelin
---
Changes in v2:
==
- Document the change in the API (David)
---
lib/vhost/rte_vhost.h | 2 ++
lib/vhost/socket.c| 12
2 files changed, 14 insertions(+)
Applied to next-virtio/for-next-net
Thanks,
Maxime
RE: [PATCH v2 1/2] cryptodev: fix RSA xform for ASN.1 syntax
> -Original Message-
> From: Kusztal, ArkadiuszX
> Sent: Monday, October 7, 2024 9:20 AM
> To: Gowrishankar Muthukrishnan ;
> dev@dpdk.org; Akhil Goyal ; Fan Zhang
>
> Cc: Anoob Joseph ; Richardson, Bruce
> ; jer...@marvell.com; Ji, Kai ;
> jack.bond-pres...@foss.arm.com; Marchand, David
> ; hemant.agra...@nxp.com; De Lara Guarch,
> Pablo ; Trahe, Fiona
> ; Doherty, Declan ;
> ma...@nvidia.com; ruifeng.w...@arm.com; Gujjar, Abhinandan S
> ; maxime.coque...@redhat.com;
> chen...@nvidia.com; sunilprakashrao.uttar...@amd.com;
> andrew.bo...@amd.com; ajit.khapa...@broadcom.com;
> raveendra.padasal...@broadcom.com; vikas.gu...@broadcom.com;
> zhangfei@linaro.org; g.si...@nxp.com; jianjay.z...@huawei.com; Daly,
> Lee ; Dooley, Brian
> Subject: RE: [PATCH v2 1/2] cryptodev: fix RSA xform for ASN.1 syntax
>
> Acked with a small comment.
>
> > -Original Message-
> > From: Gowrishankar Muthukrishnan
> > Sent: Friday, October 4, 2024 8:11 AM
> > To: dev@dpdk.org; Akhil Goyal ; Fan Zhang
> >
> > Cc: Anoob Joseph ; Richardson, Bruce
> > ; jer...@marvell.com; Kusztal, ArkadiuszX
> > ; Ji, Kai ; jack.bond-
> > pres...@foss.arm.com; Marchand, David ;
> > hemant.agra...@nxp.com; De Lara Guarch, Pablo
> > ; Trahe, Fiona
> > ; Doherty, Declan ;
> > ma...@nvidia.com; ruifeng.w...@arm.com; Gujjar, Abhinandan S
> > ; maxime.coque...@redhat.com;
> > chen...@nvidia.com; sunilprakashrao.uttar...@amd.com;
> > andrew.bo...@amd.com; ajit.khapa...@broadcom.com;
> > raveendra.padasal...@broadcom.com;
> > vikas.gu...@broadcom.com; zhangfei@linaro.org; g.si...@nxp.com;
> > jianjay.z...@huawei.com; Daly, Lee ; Dooley, Brian
> > ; Gowrishankar Muthukrishnan
> >
> > Subject: [PATCH v2 1/2] cryptodev: fix RSA xform for ASN.1 syntax
Additionally, it should not be a fix.
The RFC mandates usage of the ASN.1, but only in case sharing private key
across the network.
How the Cryptodev should interpret it, is up to the implementation.
> >
> > As per ASN.1 syntax (RFC 3447 Appendix A.1.2), RSA private key would
> > need
> It could be RFC 8017 instead.
> > specification of quintuple along with private exponent.
> > It is up to the implementation to internally handle, but not at RTE
> > itself to make them exclusive each other. Removing union on them
> > allows asymmetric implementation in VirtIO to benefit from the xform as per
> ASN.1 syntax.
> >
> > Signed-off-by: Gowrishankar Muthukrishnan
> > ---
> > lib/cryptodev/rte_crypto_asym.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/lib/cryptodev/rte_crypto_asym.h
> > b/lib/cryptodev/rte_crypto_asym.h index 39d3da3952..c33be3b155 100644
> > --- a/lib/cryptodev/rte_crypto_asym.h
> > +++ b/lib/cryptodev/rte_crypto_asym.h
> > @@ -306,7 +306,7 @@ struct rte_crypto_rsa_xform {
> >
> > enum rte_crypto_rsa_priv_key_type key_type;
> >
> > - union {
> > + struct {
> > rte_crypto_uint d;
> > /**< the RSA private exponent */
> > struct rte_crypto_rsa_priv_key_qt qt;
> > --
> > 2.21.0
>
> Acked-by: Arkadiusz Kusztal
Re: [PATCH 2/2] eal/riscv: add support for zicbop extension
On Thu, May 30, 2024 at 7:20 PM Daniel Gregory
wrote:
>
> The zicbop extension adds instructions for prefetching data into cache.
> Use them to implement RISCV-specific versions of the rte_prefetch* and
> rte_prefetch*_write functions.
>
> - prefetch.r indicates to hardware that the cache block will be accessed
> by a data read soon
> - prefetch.w indicates to hardware that the cache block will be accessed
> by a data write soon
>
> These instructions are emitted by __builtin_prefetch on modern versions
> of Clang (17.0.1+) and GCC (13.1.0+). For earlier versions, we may not
> have support for assembling Zicbop instructions, so emit the word
> that encodes a 'prefetch.[rw] 0(a0)' instruction.
Is there a benefit of adding this flag instead of relying on compiler
implementation of __builtin_prefetch()? As in do you have some
requirements for older compiler support? If just using
__builtin_prefetch could simplify this code a lot and push the
detection of zicbop to the compiler implementation. The runtime
detection is another issue and would require runtime patching to keep
the code fast.
>
> This new functionality is controlled by a Meson flag that is disabled by
> default. Whilst it's a hint, like rte_pause(), and so has no effect if
> the target doesn't support the extension, it requires the address
> prefetched to be loaded into a0, which may be costly.
>
> Signed-off-by: Daniel Gregory
> Suggested-by: Punit Agrawal
> ---
> config/riscv/meson.build | 6 +++
> lib/eal/riscv/include/rte_prefetch.h | 57 ++--
> 2 files changed, 59 insertions(+), 4 deletions(-)
>
> diff --git a/config/riscv/meson.build b/config/riscv/meson.build
> index 07d7d9da23..ecf9da1c39 100644
> --- a/config/riscv/meson.build
> +++ b/config/riscv/meson.build
> @@ -26,6 +26,12 @@ flags_common = [
> # read from /proc/device-tree/cpus/timebase-frequency. This property is
> # guaranteed on Linux, as riscv time_init() requires it.
> ['RTE_RISCV_TIME_FREQ', 0],
> +
> +# When true override the default implementation of the prefetching
> functions
> +# (rte_prefetch*) with a version that explicitly uses the Zicbop
> extension.
> +# Do not enable when using modern versions of GCC (13.1.0+) or Clang
> +# (17.0.1+). They will emit these instructions in the default
> implementation
> +['RTE_RISCV_ZICBOP', false],
> ]
>
> ## SoC-specific options.
> diff --git a/lib/eal/riscv/include/rte_prefetch.h
> b/lib/eal/riscv/include/rte_prefetch.h
> index 748cf1b626..82cad526b3 100644
> --- a/lib/eal/riscv/include/rte_prefetch.h
> +++ b/lib/eal/riscv/include/rte_prefetch.h
> @@ -14,21 +14,42 @@ extern "C" {
>
> #include
> #include
> +
> +#ifdef RTE_RISCV_ZICBOP
> +#define RTE_PREFETCH_WRITE_ARCH_DEFINED
> +#endif
> +
> #include "generic/rte_prefetch.h"
>
> +/*
> + * Modern versions of GCC & Clang will emit prefetch instructions for
> + * __builtin_prefetch when the Zicbop extension is present.
> + * The RTE_RISCV_ZICBOP option controls whether we emit them manually for
> older
> + * compilers that may not have the support to assemble them.
> + */
> static inline void rte_prefetch0(const volatile void *p)
> {
> - RTE_SET_USED(p);
> +#ifndef RTE_RISCV_ZICBOP
> + /* by default __builtin_prefetch prepares for a read */
> + __builtin_prefetch((const void *)p);
> +#else
> + /* prefetch.r 0(a0) */
> + register const volatile void *a0 asm("a0") = p;
> + asm volatile (".int 0x00156013" : : "r" (a0));
> +#endif
> }
>
> +/*
> + * The RISC-V Zicbop extension doesn't have instructions to prefetch to only
> a
> + * subset of cache levels, so fallback to rte_prefetch0
> + */
> static inline void rte_prefetch1(const volatile void *p)
> {
> - RTE_SET_USED(p);
> + rte_prefetch0(p);
> }
> -
> static inline void rte_prefetch2(const volatile void *p)
> {
> - RTE_SET_USED(p);
> + rte_prefetch0(p);
> }
>
> static inline void rte_prefetch_non_temporal(const volatile void *p)
> @@ -44,6 +65,34 @@ rte_cldemote(const volatile void *p)
> RTE_SET_USED(p);
> }
>
> +#ifdef RTE_RISCV_ZICBOP
> +__rte_experimental
> +static inline void
> +rte_prefetch0_write(const void *p)
> +{
> + /* prefetch.w 0(a0) */
> + register const void *a0 asm("a0") = p;
> + asm volatile (".int 0x00356013" : : "r" (a0));
> +}
> +
> +/*
> + * The RISC-V Zicbop extension doesn't have instructions to prefetch to only
> a
> + * subset of cache levels, so fallback to rte_prefetch0_write
> + */
> +__rte_experimental
> +static inline void
> +rte_prefetch1_write(const void *p)
> +{
> + rte_prefetch0_write(p);
> +}
> +__rte_experimental
> +static inline void
> +rte_prefetch2_write(const void *p)
> +{
> + rte_prefetch0_write(p);
> +}
> +#endif /* RTE_RISCV_ZICBOP */
> +
> #ifdef __cplusplus
> }
> #endif
> --
> 2.39.2
>
RE: [PATCH v17 1/3] eventdev: add support for independent enqueue
That part below was intended for continuation of the above code sample. Remember there was a DLB2 related information below I removed that. But, It looks like it is thought to be an orphan section I will remove it in the next patch set. >+The below section does not have any code. It is an orphan section. >+Move _below section_(only below) along with code in 2/3 patch to >doc/guides/eventdevs/dlb2.rst as it is not specific generic. > +This code example enables enqueue event reordering inside PMD before > +the events are sent to the hardware. If the application is not going > +to change the enqueue order, this flag should not be enabled to get better > performance.
[PATCH v18 2/3] event/dlb2: add support for independent enqueue
DLB devices need events to be enqueued in the same order they are
dequeued. Applications are not suppose to change event order between
dequeue and to enqueue. Since Eventdev standard does not add such
restrictions independent enqueue support is needed for DLB PMD so that
it restores dequeue order on enqueue if applications happen to change
it. It also adds missing releases in places where events are dropped
by the application and it expects implicit release to handle it.
By default the feature will be off on all DLB ports and they will
behave the same as older releases. To enable reordering feature,
applications need to add the flag RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ
to port configuration if only the device advertises the capability
RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ.
Signed-off-by: Abdullah Sevincer
Acked-by: Mattias Rönnblom
---
doc/guides/eventdevs/features/dlb2.ini | 1 +
doc/guides/rel_notes/release_24_11.rst | 2 +
drivers/event/dlb2/dlb2.c | 490 -
drivers/event/dlb2/dlb2_avx512.c | 27 +-
drivers/event/dlb2/dlb2_inline_fns.h | 8 +
drivers/event/dlb2/dlb2_priv.h | 25 +-
drivers/event/dlb2/rte_pmd_dlb2.h | 24 ++
7 files changed, 387 insertions(+), 190 deletions(-)
diff --git a/doc/guides/eventdevs/features/dlb2.ini
b/doc/guides/eventdevs/features/dlb2.ini
index 7b80286927..c7193b47c1 100644
--- a/doc/guides/eventdevs/features/dlb2.ini
+++ b/doc/guides/eventdevs/features/dlb2.ini
@@ -15,6 +15,7 @@ implicit_release_disable = Y
runtime_port_link = Y
multiple_queue_port= Y
maintenance_free = Y
+independent_enq= Y
[Eth Rx adapter Features]
diff --git a/doc/guides/rel_notes/release_24_11.rst
b/doc/guides/rel_notes/release_24_11.rst
index bf7b8f005c..1485447393 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -75,6 +75,8 @@ New Features
Applications should use ``RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ`` to enable
the feature if the capability ``RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ``
exists.
+ * Updated DLB2 driver for independent enqueue feature.
+
Removed Items
-
diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
index c43ab864ca..09e4107824 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb2/dlb2.c
@@ -82,6 +82,7 @@ static struct rte_event_dev_info evdev_dlb2_default_info = {
RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE |
RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
+ RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ |
RTE_EVENT_DEV_CAP_MAINTENANCE_FREE),
.max_profiles_per_port = 1,
};
@@ -98,6 +99,11 @@ dlb2_free_qe_mem(struct dlb2_port *qm_port)
rte_free(qm_port->qe4);
qm_port->qe4 = NULL;
+ if (qm_port->order) {
+ rte_free(qm_port->order);
+ qm_port->order = NULL;
+ }
+
rte_free(qm_port->int_arm_qe);
qm_port->int_arm_qe = NULL;
@@ -304,7 +310,7 @@ set_max_cq_depth(const char *key __rte_unused,
if (*max_cq_depth < DLB2_MIN_CQ_DEPTH_OVERRIDE ||
*max_cq_depth > DLB2_MAX_CQ_DEPTH_OVERRIDE ||
!rte_is_power_of_2(*max_cq_depth)) {
- DLB2_LOG_ERR("dlb2: max_cq_depth %d and %d and a power of 2",
+ DLB2_LOG_ERR("dlb2: Allowed max_cq_depth range %d - %d and
should be power of 2",
DLB2_MIN_CQ_DEPTH_OVERRIDE,
DLB2_MAX_CQ_DEPTH_OVERRIDE);
return -EINVAL;
@@ -1445,6 +1451,17 @@ dlb2_init_qe_mem(struct dlb2_port *qm_port, char
*mz_name)
goto error_exit;
}
+ if (qm_port->reorder_en) {
+ sz = sizeof(struct dlb2_reorder);
+ qm_port->order = rte_zmalloc(mz_name, sz, RTE_CACHE_LINE_SIZE);
+
+ if (qm_port->order == NULL) {
+ DLB2_LOG_ERR("dlb2: no reorder memory");
+ ret = -ENOMEM;
+ goto error_exit;
+ }
+ }
+
ret = dlb2_init_int_arm_qe(qm_port, mz_name);
if (ret < 0) {
DLB2_LOG_ERR("dlb2: dlb2_init_int_arm_qe ret=%d", ret);
@@ -1541,13 +1558,6 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
return -EINVAL;
}
- if (dlb2->version == DLB2_HW_V2 && ev_port->cq_weight != 0 &&
- ev_port->cq_weight > dequeue_depth) {
- DLB2_LOG_ERR("dlb2: invalid cq dequeue depth %d, must be >= cq
weight %d",
-dequeue_depth, ev_port->cq_weight);
- return -EINVAL;
- }
-
rte_spinlock_lock(&handle->resource_lock);
/* We round up to the next power of 2 if necessary */
@@ -1620,9 +1630,6 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
[dpdk-dev] [PATCH] drivers: fix build issues with redundant newline changes
From: Jerin Jacob
Certain section of the code in net/mvpp2 and ml/cnxk is enabled only
when all depended library dependences where meet.
Fixing those build errors.
Fixes: e99981af3463 ("drivers: replace logging helpers")
Signed-off-by: Jerin Jacob
---
drivers/ml/cnxk/mvtvm_ml_dev.c | 8 ++---
drivers/ml/cnxk/mvtvm_ml_model.c | 4 +--
drivers/ml/cnxk/mvtvm_ml_ops.c | 6 ++--
drivers/net/mvpp2/mrvl_ethdev.c | 14 -
drivers/net/mvpp2/mrvl_qos.c | 54
5 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/ml/cnxk/mvtvm_ml_dev.c b/drivers/ml/cnxk/mvtvm_ml_dev.c
index c9b9444eff..74959a12fc 100644
--- a/drivers/ml/cnxk/mvtvm_ml_dev.c
+++ b/drivers/ml/cnxk/mvtvm_ml_dev.c
@@ -63,7 +63,7 @@ mvtvm_mldev_parse_devargs(const char *args, struct
mvtvm_ml_dev *mvtvm_mldev)
kvlist = rte_kvargs_parse(args, valid_args);
if (kvlist == NULL) {
- plt_err("Error parsing %s devargs\n", "MLDEV_NAME_MVTVM_PMD");
+ plt_err("Error parsing %s devargs", "MLDEV_NAME_MVTVM_PMD");
return -EINVAL;
}
@@ -71,7 +71,7 @@ mvtvm_mldev_parse_devargs(const char *args, struct
mvtvm_ml_dev *mvtvm_mldev)
ret = rte_kvargs_process(kvlist, MVTVM_ML_DEV_MAX_QPS,
&parse_uint_arg,
&mvtvm_mldev->max_nb_qpairs);
if (ret < 0) {
- plt_err("Error processing arguments, key = %s\n",
MVTVM_ML_DEV_MAX_QPS);
+ plt_err("Error processing arguments, key = %s",
MVTVM_ML_DEV_MAX_QPS);
ret = -EINVAL;
goto exit;
}
@@ -82,7 +82,7 @@ mvtvm_mldev_parse_devargs(const char *args, struct
mvtvm_ml_dev *mvtvm_mldev)
ret = rte_kvargs_process(kvlist, MVTVM_ML_DEV_CACHE_MODEL_DATA,
&parse_integer_arg,
&mvtvm_mldev->cache_model_data);
if (ret < 0) {
- plt_err("Error processing arguments, key = %s\n",
+ plt_err("Error processing arguments, key = %s",
MVTVM_ML_DEV_CACHE_MODEL_DATA);
ret = -EINVAL;
goto exit;
@@ -99,7 +99,7 @@ mvtvm_mldev_parse_devargs(const char *args, struct
mvtvm_ml_dev *mvtvm_mldev)
mvtvm_mldev->cache_model_data =
CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT;
} else {
if ((mvtvm_mldev->cache_model_data < 0) ||
(mvtvm_mldev->cache_model_data > 1)) {
- plt_err("Invalid argument, %s = %d\n",
MVTVM_ML_DEV_CACHE_MODEL_DATA,
+ plt_err("Invalid argument, %s = %d",
MVTVM_ML_DEV_CACHE_MODEL_DATA,
mvtvm_mldev->cache_model_data);
ret = -EINVAL;
goto exit;
diff --git a/drivers/ml/cnxk/mvtvm_ml_model.c b/drivers/ml/cnxk/mvtvm_ml_model.c
index e3234ae442..3ada6f42db 100644
--- a/drivers/ml/cnxk/mvtvm_ml_model.c
+++ b/drivers/ml/cnxk/mvtvm_ml_model.c
@@ -50,7 +50,7 @@ mvtvm_ml_model_type_get(struct rte_ml_model_params *params)
/* Check if all objects are available */
for (i = 0; i < ML_MVTVM_MODEL_OBJECT_MAX; i++) {
if (!object_found[i]) {
- plt_err("Object %s not found in archive!\n",
mvtvm_object_list[i]);
+ plt_err("Object %s not found in archive!",
mvtvm_object_list[i]);
return ML_CNXK_MODEL_TYPE_INVALID;
}
}
@@ -100,7 +100,7 @@ mvtvm_ml_model_blob_parse(struct rte_ml_model_params
*params, struct mvtvm_ml_mo
/* Check if all objects are parsed */
for (i = 0; i < ML_MVTVM_MODEL_OBJECT_MAX; i++) {
if (!object_found[i]) {
- plt_err("Object %s not found in archive!\n",
mvtvm_object_list[i]);
+ plt_err("Object %s not found in archive!",
mvtvm_object_list[i]);
goto error;
}
}
diff --git a/drivers/ml/cnxk/mvtvm_ml_ops.c b/drivers/ml/cnxk/mvtvm_ml_ops.c
index e825c3fb23..ddde104f5b 100644
--- a/drivers/ml/cnxk/mvtvm_ml_ops.c
+++ b/drivers/ml/cnxk/mvtvm_ml_ops.c
@@ -123,7 +123,7 @@ mvtvm_ml_dev_configure(struct cnxk_ml_dev *cnxk_mldev,
const struct rte_ml_dev_c
/* Configure TVMDP library */
ret = tvmdp_configure(cnxk_mldev->mldev->data->nb_models,
rte_get_tsc_cycles);
if (ret != 0)
- plt_err("TVMDP configuration failed, error = %d\n", ret);
+ plt_err("TVMDP configuration failed, error = %d", ret);
return ret;
}
@@ -138,7 +138,7 @@ mvtvm_ml_dev_close(struct cnxk_ml_dev *cnxk_mldev)
/* Close TVMDP library configuration */
ret = tvmdp_close();
if (ret != 0)
- plt_err("TVMDP close failed, error = %d\n", ret);
+ plt_err("TVMDP close failed, error
[PATCH v18 1/3] eventdev: add support for independent enqueue
Support for independent enqueue feature and updates Event Device and PMD feature list. A new capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ is introduced. It allows out-of-order enqueuing of RTE_EVENT_OP_FORWARD or RELEASE type events on an event port where this capability is enabled. To use this capability applications need to set flag RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ during port setup only if the capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ exists. Signed-off-by: Abdullah Sevincer Acked-by: Mattias Rönnblom --- doc/guides/eventdevs/features/default.ini | 1 + doc/guides/prog_guide/eventdev/eventdev.rst | 23 +++ doc/guides/rel_notes/release_24_11.rst | 8 ++ lib/eventdev/rte_eventdev.h | 31 + 4 files changed, 63 insertions(+) diff --git a/doc/guides/eventdevs/features/default.ini b/doc/guides/eventdevs/features/default.ini index 1cc4303fe5..7c4ee99238 100644 --- a/doc/guides/eventdevs/features/default.ini +++ b/doc/guides/eventdevs/features/default.ini @@ -22,6 +22,7 @@ carry_flow_id = maintenance_free = runtime_queue_attr = profile_links = +independent_enq= ; ; Features of a default Ethernet Rx adapter. diff --git a/doc/guides/prog_guide/eventdev/eventdev.rst b/doc/guides/prog_guide/eventdev/eventdev.rst index fb6dfce102..515744d8ec 100644 --- a/doc/guides/prog_guide/eventdev/eventdev.rst +++ b/doc/guides/prog_guide/eventdev/eventdev.rst @@ -472,6 +472,29 @@ A flush callback can be passed to the function to handle any outstanding events. Invocation of this API does not affect the existing port configuration. +Independent Enqueue Capability +~~ + +This capability applies to eventdev devices that expects all forwarded events to be +enqueued in the same order as they are dequeued. For dropped events, their +releases should come at the same location as the original event was expected. +The eventdev device has this restriction as it uses the order to retrieve information about +the original event that was sent to the CPU. This contains information like atomic +flow ID to release the flow lock and ordered events sequence number to restore the +original order. + +This capability only matters to eventdevs supporting burst mode. On ports where +the application is going to change enqueue order, +``RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ`` support should be enabled. + +Example code to inform PMD that the application plans to use independent enqueue +order on a port: + +.. code-block:: c + + if (capability & RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ) + port_config = port_config | RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ; + Stopping the EventDev ~ diff --git a/doc/guides/rel_notes/release_24_11.rst b/doc/guides/rel_notes/release_24_11.rst index e0a9aa55a1..bf7b8f005c 100644 --- a/doc/guides/rel_notes/release_24_11.rst +++ b/doc/guides/rel_notes/release_24_11.rst @@ -67,6 +67,14 @@ New Features The new statistics are useful for debugging and profiling. +* **Updated Event Device Library for independent enqueue feature** + + * Added support for independent enqueue feature. With this feature Eventdev +supports enqueue in any order or specifically in a different order than +dequeue. The feature is intended for eventdevs supporting burst mode. +Applications should use ``RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ`` to enable +the feature if the capability ``RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ`` exists. + Removed Items - diff --git a/lib/eventdev/rte_eventdev.h b/lib/eventdev/rte_eventdev.h index 08e5f9320b..73a44b2ac5 100644 --- a/lib/eventdev/rte_eventdev.h +++ b/lib/eventdev/rte_eventdev.h @@ -446,6 +446,25 @@ struct rte_event; * @see RTE_SCHED_TYPE_PARALLEL */ +#define RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ (1ULL << 16) +/**< Event device is capable of independent enqueue. + * A new capability, RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ, will indicate that Eventdev + * supports the enqueue in any order or specifically in a different order than the + * dequeue. Eventdev PMD can either dequeue events in the changed order in which + * they are enqueued or restore the original order before sending them to the + * underlying hardware device. A flag is provided during the port configuration to + * inform Eventdev PMD that the application intends to use an independent enqueue + * order on a particular port. Note that this capability only matters for eventdevs + * supporting burst mode. + * + * When an implicit release is enabled on a port, Eventdev PMD will also handle + * the insertion of RELEASE events in place of dropped events. The independent enqueue + * feature only applies to FORWARD and RELEASE events. New events (op=RTE_EVENT_OP_NEW) + * will be dequeued in the order the application enqueues them and do not maintain + * any order relative to FORWARD/RELEASE events. FORWARD vs NEW re
[PATCH v18 0/3] Independent Enqueue Support
v18: Address comments. v17: Address comments. v16: Address comments. v15: Address comments. v14: Address comments. v13: Address comments. v12: Address comments. v11: Address comments. v10: Add acked-by reviewer name. v9: Address comments. v8: Address build issues. v7: Address documentation reviews. v6: Update patch with more documentation. v5: Address build issues. v4: Address comments. v3: Fix CI/build issues. v2: Fix CI/build issues. v1: Initial patchset. Abdullah Sevincer (3): eventdev: add support for independent enqueue event/dlb2: add support for independent enqueue event/dsw: add capability for independent enqueue doc/guides/eventdevs/features/default.ini | 1 + doc/guides/eventdevs/features/dlb2.ini | 1 + doc/guides/eventdevs/features/dsw.ini | 1 + doc/guides/prog_guide/eventdev/eventdev.rst | 23 + doc/guides/rel_notes/release_24_11.rst | 12 + drivers/event/dlb2/dlb2.c | 490 +--- drivers/event/dlb2/dlb2_avx512.c| 27 +- drivers/event/dlb2/dlb2_inline_fns.h| 8 + drivers/event/dlb2/dlb2_priv.h | 25 +- drivers/event/dlb2/rte_pmd_dlb2.h | 24 + drivers/event/dsw/dsw_evdev.c | 3 +- lib/eventdev/rte_eventdev.h | 31 ++ 12 files changed, 455 insertions(+), 191 deletions(-) -- 2.25.1
[PATCH v18 3/3] event/dsw: add capability for independent enqueue
To use independent enqueue capability applications need to set flag RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ during port setup only if the capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ exists. Hence, this commit adds the capability of independent enqueue to the DSW driver. Signed-off-by: Abdullah Sevincer Acked-by: Mattias Rönnblom --- doc/guides/eventdevs/features/dsw.ini | 1 + doc/guides/rel_notes/release_24_11.rst | 2 ++ drivers/event/dsw/dsw_evdev.c | 3 ++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/doc/guides/eventdevs/features/dsw.ini b/doc/guides/eventdevs/features/dsw.ini index 4038b9dd3d..d8633abc7a 100644 --- a/doc/guides/eventdevs/features/dsw.ini +++ b/doc/guides/eventdevs/features/dsw.ini @@ -11,6 +11,7 @@ burst_mode = Y nonseq_mode= Y multiple_queue_port= Y carry_flow_id = Y +independent_enq= Y [Eth Rx adapter Features] multi_eventq = Y diff --git a/doc/guides/rel_notes/release_24_11.rst b/doc/guides/rel_notes/release_24_11.rst index 1485447393..f806c08244 100644 --- a/doc/guides/rel_notes/release_24_11.rst +++ b/doc/guides/rel_notes/release_24_11.rst @@ -77,6 +77,8 @@ New Features * Updated DLB2 driver for independent enqueue feature. + * Updated DSW driver for independent enqueue feature. + Removed Items - diff --git a/drivers/event/dsw/dsw_evdev.c b/drivers/event/dsw/dsw_evdev.c index 8a1a2db8ac..9fb187bc74 100644 --- a/drivers/event/dsw/dsw_evdev.c +++ b/drivers/event/dsw/dsw_evdev.c @@ -230,7 +230,8 @@ dsw_info_get(struct rte_eventdev *dev __rte_unused, RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE| RTE_EVENT_DEV_CAP_NONSEQ_MODE| RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT| - RTE_EVENT_DEV_CAP_CARRY_FLOW_ID + RTE_EVENT_DEV_CAP_CARRY_FLOW_ID | + RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ }; } -- 2.25.1
Re: [PATCH 1/5] config/riscv: add flag for using Zbc extension
On Wed, Jun 19, 2024 at 6:41 PM Daniel Gregory wrote: > > On Wed, Jun 19, 2024 at 09:08:14AM +0200, Morten Brørup wrote: > > > From: Stephen Hemminger [mailto:step...@networkplumber.org] > > 1/5] config/riscv: add flag for using Zbc extension > > > > > > On Tue, 18 Jun 2024 18:41:29 +0100 > > > Daniel Gregory wrote: > > > > > > > diff --git a/config/riscv/meson.build b/config/riscv/meson.build > > > > index 07d7d9da23..4bda4089bd 100644 > > > > --- a/config/riscv/meson.build > > > > +++ b/config/riscv/meson.build > > > > @@ -26,6 +26,13 @@ flags_common = [ > > > > # read from /proc/device-tree/cpus/timebase-frequency. This > > > > property is > > > > # guaranteed on Linux, as riscv time_init() requires it. > > > > ['RTE_RISCV_TIME_FREQ', 0], > > > > + > > > > +# Use RISC-V Carry-less multiplication extension (Zbc) for hardware > > > > +# implementations of CRC-32C (lib/hash/rte_crc_riscv64.h), CRC-32 > > > > and > > > CRC-16 > > > > +# (lib/net/net_crc_zbc.c). Requires intrinsics available in GCC > > > > 14.1.0+ > > > and > > > > +# Clang 18.1.0+ > > > > +# Make sure to add '_zbc' to your target's -march below > > > > +['RTE_RISCV_ZBC', false], > > > > ] > > > > > > Please do not add more config options via compile flags. > > > It makes it impossible for distros to ship one version. That is a problem with RISC-V in general. Since all features are "extensions" and there is no limit (up to a point) on the permutation of those, we cannot statically build the code for all extensions. Fortunately instructions tend to resolve to nops if an instruction is not present but that still increases the code size for no benefit on platforms without a given extension. > > > > > > Instead, detect at compile or runtime > > > > Build time detection is not possible for cross builds. > > > > How about build time detection based on the target's configured > instruction set (either specified by cross-file or passed in through > -Dinstruction_set)? We could have a map from extensions present in the > ISA string to compile flags that should be enabled. > > I suggested this whilst discussing a previous patch adding support for > the Zawrs extension, but haven't heard back from Stanisław yet: > https://lore.kernel.org/dpdk-dev/20240520094854.GA3672529@ste-uk-lab-gw/ I think we already have 1 case of a cross compile config: https://git.dpdk.org/dpdk/tree/config/riscv/riscv64_sifive_u740_linux_gcc. This could serve as a stop gap before runtime detection is sorted out. I would prefer the static option to rather list all the hardware platforms explicitly. This way we will support existing platforms, not some RISC-V vendor plans. Maybe at some point the extension mess gets fixed in the arch. > > As for runtime detection, newer kernel versions have a hardware probing > interface for detecting the presence of extensions, support could be > added to rte_cpuflags.c? > https://docs.kernel.org/arch/riscv/hwprobe.html > > In combination, distros on newer kernels could ship a version that has > these optimisations baked in that falls back to a generic implementation > when the extension is detected to not be present, and systems without > the latest GCC/Clang can still compile by specifying a target ISA that > doesn't include "_zbc". hwprobe sounds like a good idea, although the key name for extensions (RISCV_HWPROBE_KEY_IMA_EXT_0) suggests that there will be more (it's 64bit and we already have 46 bits taken). That I wonder what options we have to keep the performance characteristics of the code. We either need to live-patch the code (which is problematic for userspace processes) or resort to some .so or a driver-like model. Neither option sounds very appealing.
RE: [EXTERNAL] Re: [v2 7/7] crypto/dpaa2_sec: rework debug code
Hi All,
> -Original Message-
> From: Akhil Goyal
> Sent: Friday, October 4, 2024 9:31 PM
> To: David Marchand ; Gagandeep Singh
>
> Cc: dev@dpdk.org; Hemant Agrawal ; Jun Yang
> ; Thomas Monjalon
> Subject: RE: [EXTERNAL] Re: [v2 7/7] crypto/dpaa2_sec: rework debug code
>
> > Hello guys,
> >
> > On Tue, Aug 6, 2024 at 12:28 PM Gagandeep Singh wrote:
> > >
> > > From: Jun Yang
> > >
> > > Output debug information according to various modes.
> > >
> > > Signed-off-by: Jun Yang
> > > ---
> > > drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 87
> > > +++--
> > > 1 file changed, 63 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> > b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> > > index 1e28c71b53..a293a21881 100644
> > > --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> > > +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> > > @@ -1095,7 +1095,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct
> > rte_crypto_op *op,
> > >
> > > static int
> > > build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
> > > - struct qbman_fd *fd, __rte_unused uint16_t bpid)
> > > + struct qbman_fd *fd, uint16_t bpid)
> > > {
> > > struct rte_crypto_sym_op *sym_op = op->sym;
> > > struct qbman_fle *ip_fle, *op_fle, *sge, *fle; @@ -1105,6
> > > +1105,10 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct
> > rte_crypto_op *op,
> > > struct rte_mbuf *mbuf;
> > > uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
> > > sess->iv.offset);
> > > +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> > > + char debug_str[1024];
> > > + int offset;
> > > +#endif
> > >
> > > data_len = sym_op->cipher.data.length;
> > > data_offset = sym_op->cipher.data.offset; @@ -1210,14
> > > +1214,26 @@ build_cipher_sg_fd(dpaa2_sec_session *sess,
> > struct rte_crypto_op *op,
> > > DPAA2_SET_FD_COMPOUND_FMT(fd);
> > > DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
> > >
> > > - DPAA2_SEC_DP_DEBUG(
> > > - "CIPHER SG: fdaddr =%" PRIx64 " bpid =%d meta =%d"
> > > - " off =%d, len =%d\n",
> > > +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> > > + offset = sprintf(debug_str,
> > > + "CIPHER SG: fdaddr =%" PRIx64 ", from %s pool ",
> > > DPAA2_GET_FD_ADDR(fd),
> > > - DPAA2_GET_FD_BPID(fd),
> > > - rte_dpaa2_bpid_info[bpid].meta_data_size,
> > > - DPAA2_GET_FD_OFFSET(fd),
> > > - DPAA2_GET_FD_LEN(fd));
> > > + bpid < MAX_BPID ? "SW" : "BMAN");
> > > + if (bpid < MAX_BPID) {
> > > + offset += sprintf(&debug_str[offset],
> > > + "bpid = %d ", bpid);
> > > + }
> > > + offset += sprintf(&debug_str[offset],
> > > + "private size = %d ",
> > > + mbuf->pool->private_data_size);
> > > + offset += sprintf(&debug_str[offset],
> > > + "off =%d, len =%d\n",
> >
> > DPAA2_SEC_DP_DEBUG already appends a \n, don't add a new one.
> >
> > > + DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
> > > + DPAA2_SEC_DP_DEBUG("%s", debug_str);
> >
> > Indentation is wrong.
> >
> > > +#else
> > > + RTE_SET_USED(bpid);
> > > +#endif
> > > +
> > > return 0;
> > > }
> > >
> > > @@ -1233,6 +1249,10 @@ build_cipher_fd(dpaa2_sec_session *sess,
> > > struct
> > rte_crypto_op *op,
> > > uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
> > > sess->iv.offset);
> > > struct rte_mbuf *dst;
> > > +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> > > + char debug_str[1024];
> > > + int offset;
> > > +#endif
> > >
> > > data_len = sym_op->cipher.data.length;
> > > data_offset = sym_op->cipher.data.offset; @@ -1324,14
> > > +1344,23 @@ build_cipher_fd(dpaa2_sec_session *sess, struct
> > rte_crypto_op *op,
> > > DPAA2_SET_FLE_FIN(sge);
> > > DPAA2_SET_FLE_FIN(fle);
> > >
> > > - DPAA2_SEC_DP_DEBUG(
> > > - "CIPHER: fdaddr =%" PRIx64 " bpid =%d meta =%d"
> > > - " off =%d, len =%d\n",
> > > +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> > > + offset = sprintf(debug_str,
> > > + "CIPHER: fdaddr =%" PRIx64 ", from %s pool ",
> > > DPAA2_GET_FD_ADDR(fd),
> > > - DPAA2_GET_FD_BPID(fd),
> > > - rte_dpaa2_bpid_info[bpid].meta_data_size,
> > > - DPAA2_GET_FD_OFFSET(fd),
> > > - DPAA2_GET_FD_LEN(fd));
> > > + bpid < MAX_BPID ? "SW" : "BMAN");
> > > + if (bpid < MAX_BPID) {
> > > + offset += sprintf(&debug_str[offset],
> > > + "bpid = %d ", bpid);
> > > + }
> > > + offset += sprintf(&debug_str[offset],
> > > + "
Re: [PATCH v17 1/3] eventdev: add support for independent enqueue
On Mon, Oct 7, 2024 at 7:31 AM Abdullah Sevincer wrote: > > Support for independent enqueue feature and updates Event Device > and PMD feature list. > > A new capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ is introduced. It > allows out-of-order enqueuing of RTE_EVENT_OP_FORWARD or RELEASE type > events on an event port where this capability is enabled. > > To use this capability applications need to set flag > RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ during port setup only if the > capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ exists. > > Signed-off-by: Abdullah Sevincer > Acked-by: Mattias Rönnblom > --- > doc/guides/eventdevs/features/default.ini | 1 + > doc/guides/eventdevs/features/dlb2.ini | 1 + > doc/guides/prog_guide/eventdev/eventdev.rst | 27 ++ > doc/guides/rel_notes/release_24_11.rst | 8 ++ > lib/eventdev/rte_eventdev.h | 31 + > 5 files changed, 68 insertions(+) > > diff --git a/doc/guides/eventdevs/features/default.ini > b/doc/guides/eventdevs/features/default.ini > index 1cc4303fe5..7c4ee99238 100644 > --- a/doc/guides/eventdevs/features/default.ini > +++ b/doc/guides/eventdevs/features/default.ini > @@ -22,6 +22,7 @@ carry_flow_id = > maintenance_free = > runtime_queue_attr = > profile_links = > +independent_enq= > > ; > ; Features of a default Ethernet Rx adapter. > diff --git a/doc/guides/eventdevs/features/dlb2.ini > b/doc/guides/eventdevs/features/dlb2.ini Why adding dlb2.ini update in 1/3. Move to 2/3. Also add the same for DSW in 3/3. > index 7b80286927..c7193b47c1 100644 > --- a/doc/guides/eventdevs/features/dlb2.ini > +++ b/doc/guides/eventdevs/features/dlb2.ini > @@ -15,6 +15,7 @@ implicit_release_disable = Y > runtime_port_link = Y > multiple_queue_port= Y > maintenance_free = Y > +independent_enq= Y > > [Eth Rx adapter Features] > > diff --git a/doc/guides/prog_guide/eventdev/eventdev.rst > b/doc/guides/prog_guide/eventdev/eventdev.rst > index fb6dfce102..ab53fe4e6c 100644 > --- a/doc/guides/prog_guide/eventdev/eventdev.rst > +++ b/doc/guides/prog_guide/eventdev/eventdev.rst > @@ -472,6 +472,33 @@ A flush callback can be passed to the function to handle > any outstanding events. > > Invocation of this API does not affect the existing port > configuration. > > +Independent Enqueue Capability > +~~ > + > +This capability applies to eventdev devices that expects all forwarded > events to be > +enqueued in the same order as they are dequeued. For dropped events, their > +releases should come at the same location as the original event was expected. > +The eventdev device has this restriction as it uses the order to retrieve > information about > +the original event that was sent to the CPU. This contains information like > atomic > +flow ID to release the flow lock and ordered events sequence number to > restore the > +original order. > + > +This capability only matters to eventdevs supporting burst mode. On ports > where > +the application is going to change enqueue order, > +``RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ`` support should be enabled. > + > +Example code to inform PMD that the application plans to use independent > enqueue > +order on a port: > + > +.. code-block:: c > + > + if (capability & RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ) > + port_config = port_config | RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ; > + The below section does not have any code. It is an orphan section. Move _below section_(only below) along with code in 2/3 patch to doc/guides/eventdevs/dlb2.rst as it is not specific generic. > +This code example enables enqueue event reordering inside PMD before the > events > +are sent to the hardware. If the application is not going to change the > enqueue > +order, this flag should not be enabled to get better performance. PLEASE PAY SOME ATTENTION before sending the next version. I am repeating the same.
RE: [PATCH v2 1/2] cryptodev: fix RSA xform for ASN.1 syntax
Acked with a small comment.
> -Original Message-
> From: Gowrishankar Muthukrishnan
> Sent: Friday, October 4, 2024 8:11 AM
> To: dev@dpdk.org; Akhil Goyal ; Fan Zhang
>
> Cc: Anoob Joseph ; Richardson, Bruce
> ; jer...@marvell.com; Kusztal, ArkadiuszX
> ; Ji, Kai ; jack.bond-
> pres...@foss.arm.com; Marchand, David ;
> hemant.agra...@nxp.com; De Lara Guarch, Pablo
> ; Trahe, Fiona ;
> Doherty, Declan ; ma...@nvidia.com;
> ruifeng.w...@arm.com; Gujjar, Abhinandan S ;
> maxime.coque...@redhat.com; chen...@nvidia.com;
> sunilprakashrao.uttar...@amd.com; andrew.bo...@amd.com;
> ajit.khapa...@broadcom.com; raveendra.padasal...@broadcom.com;
> vikas.gu...@broadcom.com; zhangfei@linaro.org; g.si...@nxp.com;
> jianjay.z...@huawei.com; Daly, Lee ; Dooley, Brian
> ; Gowrishankar Muthukrishnan
>
> Subject: [PATCH v2 1/2] cryptodev: fix RSA xform for ASN.1 syntax
>
> As per ASN.1 syntax (RFC 3447 Appendix A.1.2), RSA private key would need
It could be RFC 8017 instead.
> specification of quintuple along with private exponent.
> It is up to the implementation to internally handle, but not at RTE itself to
> make
> them exclusive each other. Removing union on them allows asymmetric
> implementation in VirtIO to benefit from the xform as per ASN.1 syntax.
>
> Signed-off-by: Gowrishankar Muthukrishnan
> ---
> lib/cryptodev/rte_crypto_asym.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/cryptodev/rte_crypto_asym.h b/lib/cryptodev/rte_crypto_asym.h
> index 39d3da3952..c33be3b155 100644
> --- a/lib/cryptodev/rte_crypto_asym.h
> +++ b/lib/cryptodev/rte_crypto_asym.h
> @@ -306,7 +306,7 @@ struct rte_crypto_rsa_xform {
>
> enum rte_crypto_rsa_priv_key_type key_type;
>
> - union {
> + struct {
> rte_crypto_uint d;
> /**< the RSA private exponent */
> struct rte_crypto_rsa_priv_key_qt qt;
> --
> 2.21.0
Acked-by: Arkadiusz Kusztal
Re: [PATCH v6 2/6] crypto/openssl: support EDDSA
Acked-by: Kai Ji
From: Gowrishankar Muthukrishnan
Sent: 04 October 2024 09:26
To: dev@dpdk.org ; Ji, Kai
Cc: Anoob Joseph ; Richardson, Bruce
; jer...@marvell.com ;
fanzhang@gmail.com ; Kusztal, ArkadiuszX
; jack.bond-pres...@foss.arm.com
; Marchand, David ;
hemant.agra...@nxp.com ; De Lara Guarch, Pablo
; Trahe, Fiona ;
Doherty, Declan ; ma...@nvidia.com
; ruifeng.w...@arm.com ; Akhil Goyal
; Gowrishankar Muthukrishnan
Subject: [PATCH v6 2/6] crypto/openssl: support EDDSA
Support EDDSA crypto algorithm in OpenSSL PMD.
Signed-off-by: Gowrishankar Muthukrishnan
---
doc/guides/cryptodevs/features/openssl.ini | 1 +
drivers/crypto/openssl/openssl_pmd_private.h | 13 ++
drivers/crypto/openssl/rte_openssl_pmd.c | 223 +++
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 131 +++
4 files changed, 368 insertions(+)
diff --git a/doc/guides/cryptodevs/features/openssl.ini
b/doc/guides/cryptodevs/features/openssl.ini
index b64c8ec4a5..0540c075dc 100644
--- a/doc/guides/cryptodevs/features/openssl.ini
+++ b/doc/guides/cryptodevs/features/openssl.ini
@@ -66,6 +66,7 @@ Modular Exponentiation = Y
Modular Inversion = Y
Diffie-hellman = Y
SM2 = Y
+EDDSA = Y
;
; Supported Operating systems of the 'openssl' crypto driver.
diff --git a/drivers/crypto/openssl/openssl_pmd_private.h
b/drivers/crypto/openssl/openssl_pmd_private.h
index 0282b3d829..7dd97f1c72 100644
--- a/drivers/crypto/openssl/openssl_pmd_private.h
+++ b/drivers/crypto/openssl/openssl_pmd_private.h
@@ -231,10 +231,23 @@ struct __rte_cache_aligned openssl_asym_session {
#endif
} s;
struct {
+ uint8_t curve_id;
+#if (OPENSSL_VERSION_NUMBER >= 0x3000L)
+ EC_GROUP * group;
+ BIGNUM *priv_key;
+#endif
+ } ec;
+ struct {
#if (OPENSSL_VERSION_NUMBER >= 0x3000L)
OSSL_PARAM * params;
#endif
} sm2;
+ struct {
+ uint8_t curve_id;
+#if (OPENSSL_VERSION_NUMBER >= 0x3000L)
+ OSSL_PARAM * params;
+#endif
+ } eddsa;
} u;
};
/** Set and validate OPENSSL crypto session parameters */
diff --git a/drivers/crypto/openssl/rte_openssl_pmd.c
b/drivers/crypto/openssl/rte_openssl_pmd.c
index e10a172f46..4e4d06403b 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd.c
@@ -2849,6 +2849,45 @@ process_openssl_rsa_op_evp(struct rte_crypto_op *cop,
}
+static int
+process_openssl_ecfpm_op_evp(struct rte_crypto_op *cop,
+ struct openssl_asym_session *sess)
+{
+ const EC_GROUP *ecgrp = sess->u.ec.group;
+ EC_POINT *ecpt = NULL;
+ BN_CTX *ctx = NULL;
+ BIGNUM *n = NULL;
+ int ret = -1;
+
+ n = BN_bin2bn((const unsigned char *)
+ cop->asym->ecpm.scalar.data,
+ cop->asym->ecpm.scalar.length,
+ BN_new());
+
+ ctx = BN_CTX_new();
+ if (!ctx)
+ goto err_ecfpm;
+
+ if (!EC_POINT_mul(ecgrp, ecpt, n, NULL, NULL, ctx))
+ goto err_ecfpm;
+
+ if (cop->asym->flags & RTE_CRYPTO_ASYM_FLAG_PUB_KEY_COMPRESSED) {
+ unsigned char *buf = cop->asym->ecpm.r.x.data;
+ size_t sz;
+
+ sz = EC_POINT_point2oct(ecgrp, ecpt,
POINT_CONVERSION_COMPRESSED, buf, 0, ctx);
+ if (!sz)
+ goto err_ecfpm;
+
+ cop->asym->ecpm.r.x.length = sz;
+ }
+
+err_ecfpm:
+ BN_CTX_free(ctx);
+ BN_free(n);
+ return ret;
+}
+
static int
process_openssl_sm2_op_evp(struct rte_crypto_op *cop,
struct openssl_asym_session *sess)
@@ -3074,6 +3113,158 @@ process_openssl_sm2_op_evp(struct rte_crypto_op *cop,
return ret;
}
+static int
+process_openssl_eddsa_op_evp(struct rte_crypto_op *cop,
+ struct openssl_asym_session *sess)
+{
+ static const char * const instance[] = {"Ed25519", "Ed25519ctx",
"Ed25519ph",
+ "Ed448", "Ed448ph"};
+ EVP_PKEY_CTX *kctx = NULL, *sctx = NULL, *cctx = NULL;
+ const uint8_t curve_id = sess->u.eddsa.curve_id;
+ struct rte_crypto_asym_op *op = cop->asym;
+ OSSL_PARAM *params = sess->u.eddsa.params;
+ OSSL_PARAM_BLD *iparam_bld = NULL;
+ OSSL_PARAM *iparams = NULL;
+ uint8_t signbuf[128] = {0};
+ EVP_MD_CTX *md_ctx = NULL;
+ EVP_PKEY *pkey = NULL;
+ size_t signlen;
+ int ret = -1;
+
+ cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+
+ iparam_bld = OSSL_PARAM_BLD_new();
+ if (!iparam_bld)
+ goto err_eddsa;
+
+ if (op->eddsa.instance == RTE_CRYPTO_EDCURVE_25519CTX) {
+ OSSL_PARAM_BLD_push_octet_string(iparam_bld, "context-string",
+
Re: [PATCH] crypto/dpaa2_sec: rework debug code
On Mon, Oct 7, 2024 at 10:44 AM Gagandeep Singh wrote:
>
> Output debug information according to various modes.
>
> Signed-off-by: Jun Yang
> Signed-off-by: Gagandeep Singh
> ---
> drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 87 +++--
> 1 file changed, 63 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> index 2cdf9308f8..1a897514e1 100644
> --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> @@ -1097,7 +1097,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct
> rte_crypto_op *op,
>
> static int
> build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
> - struct qbman_fd *fd, __rte_unused uint16_t bpid)
> + struct qbman_fd *fd, uint16_t bpid)
> {
> struct rte_crypto_sym_op *sym_op = op->sym;
> struct qbman_fle *ip_fle, *op_fle, *sge, *fle;
> @@ -1107,6 +1107,10 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct
> rte_crypto_op *op,
> struct rte_mbuf *mbuf;
> uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
> sess->iv.offset);
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> + char debug_str[1024];
> + int offset;
> +#endif
>
> data_len = sym_op->cipher.data.length;
> data_offset = sym_op->cipher.data.offset;
> @@ -1212,14 +1216,26 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct
> rte_crypto_op *op,
> DPAA2_SET_FD_COMPOUND_FMT(fd);
> DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
>
> - DPAA2_SEC_DP_DEBUG(
> - "CIPHER SG: fdaddr =%" PRIx64 " bpid =%d meta =%d"
> - " off =%d, len =%d",
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> + offset = sprintf(debug_str,
> + "CIPHER SG: fdaddr =%" PRIx64 ", from %s pool ",
> DPAA2_GET_FD_ADDR(fd),
> - DPAA2_GET_FD_BPID(fd),
> - rte_dpaa2_bpid_info[bpid].meta_data_size,
> - DPAA2_GET_FD_OFFSET(fd),
> - DPAA2_GET_FD_LEN(fd));
> + bpid < MAX_BPID ? "SW" : "BMAN");
> + if (bpid < MAX_BPID) {
> + offset += sprintf(&debug_str[offset],
> + "bpid = %d ", bpid);
> + }
> + offset += sprintf(&debug_str[offset],
> + "private size = %d ",
> + mbuf->pool->private_data_size);
> + offset += sprintf(&debug_str[offset],
> + "off =%d, len =%d",
> + DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
> + DPAA2_SEC_DP_DEBUG("%s", debug_str);
> +#else
> + RTE_SET_USED(bpid);
> +#endif
> +
> return 0;
> }
>
> @@ -1235,6 +1251,10 @@ build_cipher_fd(dpaa2_sec_session *sess, struct
> rte_crypto_op *op,
> uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
> sess->iv.offset);
> struct rte_mbuf *dst;
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> + char debug_str[1024];
> + int offset;
> +#endif
>
> data_len = sym_op->cipher.data.length;
> data_offset = sym_op->cipher.data.offset;
> @@ -1326,14 +1346,23 @@ build_cipher_fd(dpaa2_sec_session *sess, struct
> rte_crypto_op *op,
> DPAA2_SET_FLE_FIN(sge);
> DPAA2_SET_FLE_FIN(fle);
>
> - DPAA2_SEC_DP_DEBUG(
> - "CIPHER: fdaddr =%" PRIx64 " bpid =%d meta =%d"
> - " off =%d, len =%d",
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> + offset = sprintf(debug_str,
> + "CIPHER: fdaddr =%" PRIx64 ", from %s pool ",
> DPAA2_GET_FD_ADDR(fd),
> - DPAA2_GET_FD_BPID(fd),
> - rte_dpaa2_bpid_info[bpid].meta_data_size,
> - DPAA2_GET_FD_OFFSET(fd),
> - DPAA2_GET_FD_LEN(fd));
> + bpid < MAX_BPID ? "SW" : "BMAN");
> + if (bpid < MAX_BPID) {
> + offset += sprintf(&debug_str[offset],
> + "bpid = %d ", bpid);
> + }
> + offset += sprintf(&debug_str[offset],
> + "private size = %d ",
> + dst->pool->private_data_size);
> + offset += sprintf(&debug_str[offset],
> + "off =%d, len =%d",
> + DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
> + DPAA2_SEC_DP_DEBUG("%s", debug_str);
> +#endif
>
> return 0;
> }
> @@ -1566,6 +1595,10 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct
> dpaa2_sec_qp *qp)
> struct qbman_fle *fle;
> struct rte_crypto_op *op;
> struct rte_mbuf *dst, *src;
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> + char debug_str[1024];
> + int offset;
> +#endif
>
> if (DPAA2_FD_GET_FORMAT(fd) == qbman_fd_single)
> return sec_simple_fd_to_mbuf(fd);
> @@ -1604,15 +1637,21 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct
> dpaa2_sec_q
Re: [EXTERNAL] Re: [v2 7/7] crypto/dpaa2_sec: rework debug code
On Mon, Oct 7, 2024 at 10:46 AM Gagandeep Singh wrote: > > > I see this patch is already merged in next-crypto. > > > Please, can this be fixed before reaching main? > > > > > Gagan, > > This patch is removed from the crypto tree for now. > > > > Please rework and send as separate patch. > > I have Submitted the updated patch: > https://patchwork.dpdk.org/project/dpdk/patch/20241007084354.852733-1-g.si...@nxp.com/ LGTM. -- David Marchand
RE: [RFC 0/4] ethdev: rework config restore
> > External email: Use caution opening links or attachments > > > > > > On 9/18/2024 10:21 AM, Dariusz Sosnowski wrote: > > > Hi all, > > > > > > We have been working on optimizing the latency of calls to > > > rte_eth_dev_start(), on ports spawned by mlx5 PMD. Most of the work > > > requires changes in the implementation of > > > .dev_start() PMD callback, but I also wanted to start a discussion > > > regarding configuration restore. > > > > > > rte_eth_dev_start() does a few things on top of calling .dev_start() > > > callback: > > > > > > - Before calling it: > > > - eth_dev_mac_restore() - if device supports > > > RTE_ETH_DEV_NOLIVE_MAC_ADDR; > > > - After calling it: > > > - eth_dev_mac_restore() - if device does not support > > RTE_ETH_DEV_NOLIVE_MAC_ADDR; > > > - restore promiscuous config > > > - restore all multicast config > > > > > > eth_dev_mac_restore() iterates over all known MAC addresses - stored > > > in rte_eth_dev_data.mac_addrs array - and calls > > > .mac_addr_set() and .mac_addr_add() callbacks to apply these MAC > > > addresses. > > > > > > Promiscuous config restore checks if promiscuous mode is enabled or > > > not, and calls .promiscuous_enable() or .promiscuous_disable() callback. > > > > > > All multicast config restore checks if all multicast mode is enabled > > > or not, and calls .allmulticast_enable() or .allmulticast_disable() > > > callback. > > > > > > Callbacks are called directly in all of these cases, to bypass the > > > checks for applying the same configuration, which exist in relevant APIs. > > > Checks are bypassed to force drivers to reapply the configuration. > > > > > > Let's consider what happens in the following sequence of API calls. > > > > > > 1. rte_eth_dev_configure() > > > 2. rte_eth_tx_queue_setup() > > > 3. rte_eth_rx_queue_setup() > > > 4. rte_eth_promiscuous_enable() > > > - Call dev->dev_ops->promiscuous_enable() > > > - Stores promiscuous state in dev->data->promiscuous 5. > > > rte_eth_allmulticast_enable() > > > - Call dev->dev_ops->allmulticast_enable() > > > - Stores allmulticast state in dev->data->allmulticast 6. > > > rte_eth_dev_start() > > > - Call dev->dev_ops->dev_start() > > > - Call dev->dev_ops->mac_addr_set() - apply default MAC address > > > - Call dev->dev_ops->promiscuous_enable() > > > - Call dev->dev_ops->allmulticast_enable() > > > > > > Even though all configuration is available in dev->data after step 5, > > > library forces reapplying this configuration in step 6. > > > > > > In mlx5 PMD case all relevant callbacks require communication with the > > > kernel driver, to configure the device (mlx5 PMD must create/destroy > > > new kernel flow rules and/or change netdev config). > > > > > > mlx5 PMD handles applying all configuration in .dev_start(), so the > > > following forced callbacks force additional communication with the > > > kernel. The > > same configuration is applied multiple times. > > > > > > As an optimization, mlx5 PMD could check if a given configuration was > > > applied, but this would duplicate the functionality of the library > > > (for example rte_eth_promiscuous_enable() does not call the driver if > > > dev->data->promiscuous is set). > > > > > > Question: Since all of the configuration is available before > > > .dev_start() callback is called, why ethdev library does not expect > > > .dev_start() to > > take this configuration into account? > > > In other words, why library has to reapply the configuration? > > > > > > I could not find any particular reason why configuration restore > > > exists as part of the process (it was in the initial DPDK commit). > > > > > > > My assumption is .dev_stop() cause these values reset in some devices, so > > .dev_start() restores them back. > > @Bruce or @Konstantin may remember the history. Yep, as I remember, at least some Intel PMDs calling hw_reset() ad dec_stop() and even dev_start() to make sure that HW is in a clean (known) state. > > > > But I agree this is device specific behavior, and can be managed by what > > device > > requires. Probably yes. > > > > > The patches included in this RFC, propose a mechanism which would help > > > with managing which drivers rely on forceful configuration restore. > > > Drivers could advertise if forceful configuration restore is needed > > > through `RTE_ETH_DEV_*_FORCE_RESTORE` device flag. If this flag is > > > set, then the driver in question requires ethdev to forcefully restore > > configuration. > > > > > > > OK to use flag for it, but not sure about using 'dev_info->dev_flags' > > (RTE_ETH_DEV_*) for this, as this flag is shared with user and this is all > > dpdk > > internal. > > > > What about to have a dedicated flag for it? We can have a dedicated set of > > flag > > values for restore. > > Agreed. What do you think about the following? Instead of exposing that, can we probably make it transparent to the user and probably ethdev layer too? Might
Re: [PATCH v2 02/10] baseband/acc: queue allocation refactor
Hi Nicolas,
On 10/4/24 20:19, Chautru, Nicolas wrote:
Hi Maxime,
-Original Message-
From: Maxime Coquelin
Sent: Friday, October 4, 2024 5:08 AM
To: Vargas, Hernan ; dev@dpdk.org;
gak...@marvell.com; t...@redhat.com
Cc: Chautru, Nicolas ; Zhang, Qi Z
Subject: Re: [PATCH v2 02/10] baseband/acc: queue allocation refactor
On 10/3/24 22:49, Hernan Vargas wrote:
Refactor to manage queue memory per operation more flexibly for VRB
devices.
Signed-off-by: Hernan Vargas
---
drivers/baseband/acc/acc_common.h | 5 +
drivers/baseband/acc/rte_vrb_pmd.c | 214 -
2 files changed, 157 insertions(+), 62 deletions(-)
diff --git a/drivers/baseband/acc/acc_common.h
b/drivers/baseband/acc/acc_common.h
index b1f81e73e68d..adbac0dcca70 100644
--- a/drivers/baseband/acc/acc_common.h
+++ b/drivers/baseband/acc/acc_common.h
@@ -149,6 +149,8 @@
#define VRB2_VF_ID_SHIFT 6
#define ACC_MAX_FFT_WIN 16
+#define ACC_MAX_RING_BUFFER 64
+#define VRB2_MAX_Q_PER_OP 256
extern int acc_common_logtype;
@@ -581,6 +583,9 @@ struct acc_device {
void *sw_rings_base; /* Base addr of un-aligned memory for sw rings
*/
void *sw_rings; /* 64MBs of 64MB aligned memory for sw rings */
rte_iova_t sw_rings_iova; /* IOVA address of sw_rings */
+ void *sw_rings_array[ACC_MAX_RING_BUFFER]; /* Array of aligned
memory for sw rings. */
+ rte_iova_t sw_rings_iova_array[ACC_MAX_RING_BUFFER]; /* Array
of sw_rings IOVA. */
+ uint32_t queue_index[ACC_MAX_RING_BUFFER]; /* Tracking queue
index
+per ring buffer. */
/* Virtual address of the info memory routed to the this function under
* operation, whether it is PF or VF.
* HW may DMA information data at this location asynchronously diff
--git a/drivers/baseband/acc/rte_vrb_pmd.c
b/drivers/baseband/acc/rte_vrb_pmd.c
index bae01e563826..2c62a5b3e329 100644
--- a/drivers/baseband/acc/rte_vrb_pmd.c
+++ b/drivers/baseband/acc/rte_vrb_pmd.c
@@ -281,7 +281,7 @@ fetch_acc_config(struct rte_bbdev *dev)
/* Check the depth of the AQs. */
reg_len0 = acc_reg_read(d, d->reg_addr->depth_log0_offset);
reg_len1 = acc_reg_read(d, d->reg_addr->depth_log1_offset);
- for (acc = 0; acc < NUM_ACC; acc++) {
+ for (acc = 0; acc < VRB1_NUM_ACCS; acc++) {
qtopFromAcc(&q_top, acc, acc_conf);
if (q_top->first_qgroup_index <
ACC_NUM_QGRPS_PER_WORD)
q_top->aq_depth_log2 =
@@ -290,7 +290,7 @@ fetch_acc_config(struct rte_bbdev *dev)
q_top->aq_depth_log2 = (reg_len1 >> ((q_top-
first_qgroup_index -
ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;
}
- } else {
+ } else if (d->device_variant == VRB2_VARIANT) {
reg0 = acc_reg_read(d, d->reg_addr->qman_group_func);
reg1 = acc_reg_read(d, d->reg_addr->qman_group_func + 4);
reg2 = acc_reg_read(d, d->reg_addr->qman_group_func + 8);
@@
-308,7 +308,7 @@ fetch_acc_config(struct rte_bbdev *dev)
idx = (reg2 >> ((qg %
ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
else
idx = (reg3 >> ((qg %
ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
- if (idx < VRB_NUM_ACCS) {
+ if (idx < VRB2_NUM_ACCS) {
acc = qman_func_id[idx];
updateQtop(acc, qg, acc_conf, d);
}
@@ -321,7 +321,7 @@ fetch_acc_config(struct rte_bbdev *dev)
reg_len2 = acc_reg_read(d, d->reg_addr->depth_log0_offset +
8);
reg_len3 = acc_reg_read(d, d->reg_addr->depth_log0_offset +
12);
- for (acc = 0; acc < NUM_ACC; acc++) {
+ for (acc = 0; acc < VRB2_NUM_ACCS; acc++) {
qtopFromAcc(&q_top, acc, acc_conf);
if (q_top->first_qgroup_index /
ACC_NUM_QGRPS_PER_WORD == 0)
q_top->aq_depth_log2 = (reg_len0 >> ((q_top-
first_qgroup_index
%
This function could be much heavily refactored.
If we look at was is actuallt performed, VRB1 and VRB2 logic is the same, just a
couple of value differs (they could be set at probe time).
I might propose something in the future.
@@ -543,6 +543,7 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t
num_queues, int socket_id)
{
uint32_t phys_low, phys_high, value;
struct acc_device *d = dev->data->dev_private;
+ uint16_t queues_per_op, i;
int ret;
if (d->pf_device && !d->acc_conf.pf_mode_en) { @@ -564,27 +565,37
@@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int
socket_id)
return -ENODEV;
}
- alloc_sw_rings_min_mem(de
[PATCH] crypto/dpaa2_sec: rework debug code
Output debug information according to various modes.
Signed-off-by: Jun Yang
Signed-off-by: Gagandeep Singh
---
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 87 +++--
1 file changed, 63 insertions(+), 24 deletions(-)
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 2cdf9308f8..1a897514e1 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1097,7 +1097,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
static int
build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
- struct qbman_fd *fd, __rte_unused uint16_t bpid)
+ struct qbman_fd *fd, uint16_t bpid)
{
struct rte_crypto_sym_op *sym_op = op->sym;
struct qbman_fle *ip_fle, *op_fle, *sge, *fle;
@@ -1107,6 +1107,10 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
struct rte_mbuf *mbuf;
uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
sess->iv.offset);
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ char debug_str[1024];
+ int offset;
+#endif
data_len = sym_op->cipher.data.length;
data_offset = sym_op->cipher.data.offset;
@@ -1212,14 +1216,26 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
DPAA2_SET_FD_COMPOUND_FMT(fd);
DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
- DPAA2_SEC_DP_DEBUG(
- "CIPHER SG: fdaddr =%" PRIx64 " bpid =%d meta =%d"
- " off =%d, len =%d",
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ offset = sprintf(debug_str,
+ "CIPHER SG: fdaddr =%" PRIx64 ", from %s pool ",
DPAA2_GET_FD_ADDR(fd),
- DPAA2_GET_FD_BPID(fd),
- rte_dpaa2_bpid_info[bpid].meta_data_size,
- DPAA2_GET_FD_OFFSET(fd),
- DPAA2_GET_FD_LEN(fd));
+ bpid < MAX_BPID ? "SW" : "BMAN");
+ if (bpid < MAX_BPID) {
+ offset += sprintf(&debug_str[offset],
+ "bpid = %d ", bpid);
+ }
+ offset += sprintf(&debug_str[offset],
+ "private size = %d ",
+ mbuf->pool->private_data_size);
+ offset += sprintf(&debug_str[offset],
+ "off =%d, len =%d",
+ DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+ DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#else
+ RTE_SET_USED(bpid);
+#endif
+
return 0;
}
@@ -1235,6 +1251,10 @@ build_cipher_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
sess->iv.offset);
struct rte_mbuf *dst;
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ char debug_str[1024];
+ int offset;
+#endif
data_len = sym_op->cipher.data.length;
data_offset = sym_op->cipher.data.offset;
@@ -1326,14 +1346,23 @@ build_cipher_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
DPAA2_SET_FLE_FIN(sge);
DPAA2_SET_FLE_FIN(fle);
- DPAA2_SEC_DP_DEBUG(
- "CIPHER: fdaddr =%" PRIx64 " bpid =%d meta =%d"
- " off =%d, len =%d",
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ offset = sprintf(debug_str,
+ "CIPHER: fdaddr =%" PRIx64 ", from %s pool ",
DPAA2_GET_FD_ADDR(fd),
- DPAA2_GET_FD_BPID(fd),
- rte_dpaa2_bpid_info[bpid].meta_data_size,
- DPAA2_GET_FD_OFFSET(fd),
- DPAA2_GET_FD_LEN(fd));
+ bpid < MAX_BPID ? "SW" : "BMAN");
+ if (bpid < MAX_BPID) {
+ offset += sprintf(&debug_str[offset],
+ "bpid = %d ", bpid);
+ }
+ offset += sprintf(&debug_str[offset],
+ "private size = %d ",
+ dst->pool->private_data_size);
+ offset += sprintf(&debug_str[offset],
+ "off =%d, len =%d",
+ DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+ DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#endif
return 0;
}
@@ -1566,6 +1595,10 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct
dpaa2_sec_qp *qp)
struct qbman_fle *fle;
struct rte_crypto_op *op;
struct rte_mbuf *dst, *src;
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ char debug_str[1024];
+ int offset;
+#endif
if (DPAA2_FD_GET_FORMAT(fd) == qbman_fd_single)
return sec_simple_fd_to_mbuf(fd);
@@ -1604,15 +1637,21 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct
dpaa2_sec_qp *qp)
dst->data_len = len;
}
- DPAA2_SEC_DP_DEBUG("mbuf %p BMAN buf addr %p,"
- " fdaddr =%" PRIx64 " bpid =%d meta =%d off =%d, len =%d",
- (void *)dst,
- dst->buf_addr,
- DPAA2_GET_FD_ADDR(fd),
-
[PATCH] net/mlx5/hws: in NAT64 fix TC to TOS fields mapping
From: Hamdan Igbaria
In IPv6 to IPv4 scenario when copying the TC field to the
TOS[DSCP:6 bits, ECN: 2 bits] field the mapping of the fields
get set wrongly, since the destination field of TOS is defined as 2
split fields of DSCP and ECN.
In IPv4 to IPv6 we don't have this issue since both the source field of
TOS and destination field of TC defined as 8 bits.
Example to the problematic case of IPv6 to IPv4, TOS to TC mapping:
TC=[abcdefgh], it should be mapped to TOS=[DSCP=abcdef, ECN=gh],
but instead it was mapped as follow TOS=[DSCP=cdefgh, ECN=ab].
Fixes: 06d969a8c5b8 ("net/mlx5/hws: support NAT64 flow action")
Cc: sta...@dpdk.org
Signed-off-by: Hamdan Igbaria
Acked-by: Dariusz Sosnowski
---
drivers/net/mlx5/hws/mlx5dr_action.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c
b/drivers/net/mlx5/hws/mlx5dr_action.c
index 3fceb96de2..f163be256c 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -617,7 +617,7 @@ mlx5dr_action_create_nat64_copy_back_state(struct
mlx5dr_context *ctx,
MLX5_SET(copy_action_in, action_ptr, src_field,
attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
MLX5_SET(copy_action_in, action_ptr, dst_field, tos_field);
- MLX5_SET(copy_action_in, action_ptr, src_offset, 24);
+ MLX5_SET(copy_action_in, action_ptr, src_offset, 24 + (ecn ?
MLX5DR_ACTION_NAT64_ECN_SIZE : 0));
MLX5_SET(copy_action_in, action_ptr, length, tos_size);
action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
@@ -629,7 +629,7 @@ mlx5dr_action_create_nat64_copy_back_state(struct
mlx5dr_context *ctx,
MLX5_SET(copy_action_in, action_ptr, src_field,
attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
MLX5_SET(copy_action_in, action_ptr, dst_field, ecn);
- MLX5_SET(copy_action_in, action_ptr, src_offset, 24 + tos_size);
+ MLX5_SET(copy_action_in, action_ptr, src_offset, 24);
MLX5_SET(copy_action_in, action_ptr, length,
MLX5DR_ACTION_NAT64_ECN_SIZE);
action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
}
--
2.39.3
Re: [dpdk-dev] [PATCH] drivers: fix build issues with redundant newline changes
Hello Jerin,
On Mon, Oct 7, 2024 at 10:13 AM wrote:
>
> From: Jerin Jacob
>
> Certain section of the code in net/mvpp2 and ml/cnxk is enabled only
> when all depended library dependences where meet.
> Fixing those build errors.
Sorry for missing those.
Too bad there is no CI with such libraries installed.
>
> Fixes: e99981af3463 ("drivers: replace logging helpers")
I fixed other similar issues for ml/cnxk fixes in commit f665790a5dba
("drivers: remove redundant newline from logs").
net/mvpp2 was touched only with 2b843cac232e ("drivers: use per line
logging in helpers").
But the issues were present regardless of the changes in the logging macro.
In the end, I would rather flag this whole patch as:
Fixes: f665790a5dba ("drivers: remove redundant newline from logs").
>
> Signed-off-by: Jerin Jacob
Double checking manually, I think we are missing another small fix:
$ git diff
diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c
index 3e98cce099..e298da2724 100644
--- a/drivers/net/mvpp2/mrvl_qos.c
+++ b/drivers/net/mvpp2/mrvl_qos.c
@@ -972,7 +972,7 @@ setup_policer(struct mrvl_priv *priv, struct
pp2_cls_plcr_params *params)
*
* Lets use 0th then.
*/
- sprintf(match, "policer-%d:%d\n", priv->pp_id, 0);
+ sprintf(match, "policer-%d:%d", priv->pp_id, 0);
params->match = match;
ret = pp2_cls_plcr_init(params, &priv->default_policer);
--
David Marchand
[PATCH] crypto/dpaa2_sec: rework debug code
Output debug information according to various modes.
Signed-off-by: Jun Yang
Signed-off-by: Gagandeep Singh
---
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 87 +++--
1 file changed, 63 insertions(+), 24 deletions(-)
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 2cdf9308f8..1a897514e1 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1097,7 +1097,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
static int
build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
- struct qbman_fd *fd, __rte_unused uint16_t bpid)
+ struct qbman_fd *fd, uint16_t bpid)
{
struct rte_crypto_sym_op *sym_op = op->sym;
struct qbman_fle *ip_fle, *op_fle, *sge, *fle;
@@ -1107,6 +1107,10 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
struct rte_mbuf *mbuf;
uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
sess->iv.offset);
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ char debug_str[1024];
+ int offset;
+#endif
data_len = sym_op->cipher.data.length;
data_offset = sym_op->cipher.data.offset;
@@ -1212,14 +1216,26 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
DPAA2_SET_FD_COMPOUND_FMT(fd);
DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
- DPAA2_SEC_DP_DEBUG(
- "CIPHER SG: fdaddr =%" PRIx64 " bpid =%d meta =%d"
- " off =%d, len =%d",
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ offset = sprintf(debug_str,
+ "CIPHER SG: fdaddr =%" PRIx64 ", from %s pool ",
DPAA2_GET_FD_ADDR(fd),
- DPAA2_GET_FD_BPID(fd),
- rte_dpaa2_bpid_info[bpid].meta_data_size,
- DPAA2_GET_FD_OFFSET(fd),
- DPAA2_GET_FD_LEN(fd));
+ bpid < MAX_BPID ? "SW" : "BMAN");
+ if (bpid < MAX_BPID) {
+ offset += sprintf(&debug_str[offset],
+ "bpid = %d ", bpid);
+ }
+ offset += sprintf(&debug_str[offset],
+ "private size = %d ",
+ mbuf->pool->private_data_size);
+ offset += sprintf(&debug_str[offset],
+ "off =%d, len =%d",
+ DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+ DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#else
+ RTE_SET_USED(bpid);
+#endif
+
return 0;
}
@@ -1235,6 +1251,10 @@ build_cipher_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
sess->iv.offset);
struct rte_mbuf *dst;
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ char debug_str[1024];
+ int offset;
+#endif
data_len = sym_op->cipher.data.length;
data_offset = sym_op->cipher.data.offset;
@@ -1326,14 +1346,23 @@ build_cipher_fd(dpaa2_sec_session *sess, struct
rte_crypto_op *op,
DPAA2_SET_FLE_FIN(sge);
DPAA2_SET_FLE_FIN(fle);
- DPAA2_SEC_DP_DEBUG(
- "CIPHER: fdaddr =%" PRIx64 " bpid =%d meta =%d"
- " off =%d, len =%d",
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ offset = sprintf(debug_str,
+ "CIPHER: fdaddr =%" PRIx64 ", from %s pool ",
DPAA2_GET_FD_ADDR(fd),
- DPAA2_GET_FD_BPID(fd),
- rte_dpaa2_bpid_info[bpid].meta_data_size,
- DPAA2_GET_FD_OFFSET(fd),
- DPAA2_GET_FD_LEN(fd));
+ bpid < MAX_BPID ? "SW" : "BMAN");
+ if (bpid < MAX_BPID) {
+ offset += sprintf(&debug_str[offset],
+ "bpid = %d ", bpid);
+ }
+ offset += sprintf(&debug_str[offset],
+ "private size = %d ",
+ dst->pool->private_data_size);
+ offset += sprintf(&debug_str[offset],
+ "off =%d, len =%d",
+ DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+ DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#endif
return 0;
}
@@ -1566,6 +1595,10 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct
dpaa2_sec_qp *qp)
struct qbman_fle *fle;
struct rte_crypto_op *op;
struct rte_mbuf *dst, *src;
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+ char debug_str[1024];
+ int offset;
+#endif
if (DPAA2_FD_GET_FORMAT(fd) == qbman_fd_single)
return sec_simple_fd_to_mbuf(fd);
@@ -1604,15 +1637,21 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct
dpaa2_sec_qp *qp)
dst->data_len = len;
}
- DPAA2_SEC_DP_DEBUG("mbuf %p BMAN buf addr %p,"
- " fdaddr =%" PRIx64 " bpid =%d meta =%d off =%d, len =%d",
- (void *)dst,
- dst->buf_addr,
- DPAA2_GET_FD_ADDR(fd),
-
Re: [PATCH] crypto/scheduler: fix incorrect variable usage
I'm not see any issue with original code, can you give more details about crash
so I can try to reproduce at my end.
cc kirill.rybalche...@intel.com for review
From: Yong Liang <1269690...@qq.com>
Sent: 18 September 2024 15:15
To: dev@dpdk.org
Cc: roy.fan.zh...@intel.com
Subject: [PATCH] crypto/scheduler: fix incorrect variable usage
The variable `pending_deq_ops` was incorrectly used
instead of `pending_enq_ops`.
This causes the program to crash
when the worker PMD accesses the session
Bugzilla ID: 1537
Fixes: 6812b9bf470e ("crypto/scheduler: use unified session")
Cc: roy.fan.zh...@intel.com
Signed-off-by: Yong Liang <1269690...@qq.com>
---
drivers/crypto/scheduler/scheduler_multicore.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/scheduler/scheduler_multicore.c
b/drivers/crypto/scheduler/scheduler_multicore.c
index a21b522f9f..70f8a25b70 100644
--- a/drivers/crypto/scheduler/scheduler_multicore.c
+++ b/drivers/crypto/scheduler/scheduler_multicore.c
@@ -191,11 +191,11 @@ mc_scheduler_worker(struct rte_cryptodev *dev)
worker->qp_id,
&enq_ops[pending_enq_ops_idx],
pending_enq_ops);
- if (processed_ops < pending_deq_ops)
+ if (processed_ops < pending_enq_ops)
scheduler_retrieve_sessions(
&enq_ops[pending_enq_ops_idx +
processed_ops],
- pending_deq_ops - processed_ops);
+ pending_enq_ops - processed_ops);
pending_enq_ops -= processed_ops;
pending_enq_ops_idx += processed_ops;
inflight_ops += processed_ops;
--
2.43.0
Re: [PATCH v1] crypto/ipsec_mb: bump minimum IPsec MB version
Good point Kai, i'll update the patch. Thanks, Brian From: Ji, Kai Sent: Monday, October 7, 2024 11:09 AM To: Dooley, Brian ; De Lara Guarch, Pablo Cc: dev@dpdk.org ; gak...@marvell.com ; wathsala.vithan...@arm.com Subject: Re: [PATCH v1] crypto/ipsec_mb: bump minimum IPsec MB version Acked-by: Kai Ji Any release doc needs to be updated ? From: Dooley, Brian Sent: 04 October 2024 15:58 To: Ji, Kai ; De Lara Guarch, Pablo Cc: dev@dpdk.org ; gak...@marvell.com ; wathsala.vithan...@arm.com ; Dooley, Brian Subject: [PATCH v1] crypto/ipsec_mb: bump minimum IPsec MB version AESNI_MB SW PMDs increment Intel IPsec MB version to 1.4. A minimum IPsec Multi-buffer version of 1.4 or greater is now required for the 24.11 LTS release. Signed-off-by: Brian Dooley --- This patch relates to a deprecation notice sent in the 24.03 release. Intel IPsec MB minimum version being bumped to 1.4 for the 24.11 release. https://patches.dpdk.org/project/dpdk/patch/20240314103731.3242086-2-brian.doo...@intel.com/ --- doc/guides/cryptodevs/aesni_gcm.rst | 3 +- doc/guides/cryptodevs/aesni_mb.rst | 3 +- doc/guides/cryptodevs/chacha20_poly1305.rst | 3 +- doc/guides/cryptodevs/kasumi.rst| 3 +- doc/guides/cryptodevs/snow3g.rst| 3 +- doc/guides/cryptodevs/zuc.rst | 3 +- drivers/crypto/ipsec_mb/ipsec_mb_ops.c | 24 --- drivers/crypto/ipsec_mb/meson.build | 2 +- drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 164 drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 9 -- 10 files changed, 13 insertions(+), 204 deletions(-) diff --git a/doc/guides/cryptodevs/aesni_gcm.rst b/doc/guides/cryptodevs/aesni_gcm.rst index 3af1486553..7592d33da2 100644 --- a/doc/guides/cryptodevs/aesni_gcm.rst +++ b/doc/guides/cryptodevs/aesni_gcm.rst @@ -74,7 +74,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.11 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/aesni_mb.rst b/doc/guides/cryptodevs/aesni_mb.rst index 3c77d0f463..c2f6633ee6 100644 --- a/doc/guides/cryptodevs/aesni_mb.rst +++ b/doc/guides/cryptodevs/aesni_mb.rst @@ -132,7 +132,8 @@ and the Multi-Buffer library version supported by them: DPDK versionMulti-buffer library version == 20.11 - 21.08 0.53 - 1.3 - 21.11+ 1.0 - 1.5 + 21.11 - 24.07 1.0 - 1.5 + 24.11+ 1.4 - 1.5 == Initialization diff --git a/doc/guides/cryptodevs/chacha20_poly1305.rst b/doc/guides/cryptodevs/chacha20_poly1305.rst index 44cff85918..b5a980b247 100644 --- a/doc/guides/cryptodevs/chacha20_poly1305.rst +++ b/doc/guides/cryptodevs/chacha20_poly1305.rst @@ -66,7 +66,8 @@ and the external crypto libraries supported by them: = DPDK version Crypto library version = - 21.11+ Multi-buffer library 1.0-1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/kasumi.rst b/doc/guides/cryptodevs/kasumi.rst index 4070f025e1..b57f18b56f 100644 --- a/doc/guides/cryptodevs/kasumi.rst +++ b/doc/guides/cryptodevs/kasumi.rst @@ -80,7 +80,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.02 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/snow3g.rst b/doc/guides/cryptodevs/snow3g.rst index 6eb8229fb5..fb4e0448ac 100644 --- a/doc/guides/cryptodevs/snow3g.rst +++ b/doc/guides/cryptodevs/snow3g.rst @@ -89,7 +89,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.02 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/zuc.rst b/doc/guides/cryptodevs/zuc.rst index 29fe6279aa..4615562246 100644 --- a/doc/guides/cryptodevs/zu
Re: [PATCH] eal/x86: cache queried CPU flags
On Mon, Oct 07, 2024 at 04:29:31PM +, Wathsala Wathawana Vithanage wrote: > > Rather than re-querying the HW each time a CPU flag is requested, we can > > just > > save the return value in the flags array. This should speed up repeated > > querying of CPU flags, and provides a workaround for a reported issue where > > errors are seen with constant querying of the AVX-512 CPU flag from a non- > > AVX VM. > > > > Bugzilla Id: 1501 > > > > Signed-off-by: Bruce Richardson > > --- > > Hi Bruce, > Why x86/rte_cpuflags.c is not using rte_getauxval() ? I don't see any such DPDK function, unless I'm missing something? I do see a linux function which includes hw capability flags. I suspect the reasons we don't use that are: 1. Lack of awareness of it (at least on my end! :-)) 2. Originally when we added flags for new instruction sets we may have needed to support their detection on platforms where the kernel/libc was too old to be aware of them. 3. It's linux only, so we'd still need these cpuid calls for other OS's anyway. Therefore, I don't see any benefit in using that function over what we do now. Is there some benefit that you see that makes you think it would be worthwhile switching? Thanks, /Bruce
RE: [PATCH v2 02/10] baseband/acc: queue allocation refactor
Hi Maxime,
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, October 7, 2024 2:31 AM
> To: Chautru, Nicolas ; Vargas, Hernan
> ; dev@dpdk.org; gak...@marvell.com;
> t...@redhat.com
> Cc: Zhang, Qi Z
> Subject: Re: [PATCH v2 02/10] baseband/acc: queue allocation refactor
>
> Hi Nicolas,
>
> On 10/4/24 20:19, Chautru, Nicolas wrote:
> > Hi Maxime,
> >
> >> -Original Message-
> >> From: Maxime Coquelin
> >> Sent: Friday, October 4, 2024 5:08 AM
> >> To: Vargas, Hernan ; dev@dpdk.org;
> >> gak...@marvell.com; t...@redhat.com
> >> Cc: Chautru, Nicolas ; Zhang, Qi Z
> >>
> >> Subject: Re: [PATCH v2 02/10] baseband/acc: queue allocation refactor
> >>
> >>
> >>
> >> On 10/3/24 22:49, Hernan Vargas wrote:
> >>> Refactor to manage queue memory per operation more flexibly for VRB
> >>> devices.
> >>>
> >>> Signed-off-by: Hernan Vargas
> >>> ---
> >>>drivers/baseband/acc/acc_common.h | 5 +
> >>>drivers/baseband/acc/rte_vrb_pmd.c | 214 --
> ---
> >>>2 files changed, 157 insertions(+), 62 deletions(-)
> >>>
> >>> diff --git a/drivers/baseband/acc/acc_common.h
> >>> b/drivers/baseband/acc/acc_common.h
> >>> index b1f81e73e68d..adbac0dcca70 100644
> >>> --- a/drivers/baseband/acc/acc_common.h
> >>> +++ b/drivers/baseband/acc/acc_common.h
> >>> @@ -149,6 +149,8 @@
> >>>#define VRB2_VF_ID_SHIFT 6
> >>>
> >>>#define ACC_MAX_FFT_WIN 16
> >>> +#define ACC_MAX_RING_BUFFER 64
> >>> +#define VRB2_MAX_Q_PER_OP 256
> >>>
> >>>extern int acc_common_logtype;
> >>>
> >>> @@ -581,6 +583,9 @@ struct acc_device {
> >>> void *sw_rings_base; /* Base addr of un-aligned memory for sw
> >>> rings
> >> */
> >>> void *sw_rings; /* 64MBs of 64MB aligned memory for sw rings */
> >>> rte_iova_t sw_rings_iova; /* IOVA address of sw_rings */
> >>> + void *sw_rings_array[ACC_MAX_RING_BUFFER]; /* Array of aligned
> >> memory for sw rings. */
> >>> + rte_iova_t sw_rings_iova_array[ACC_MAX_RING_BUFFER]; /* Array
> >> of sw_rings IOVA. */
> >>> + uint32_t queue_index[ACC_MAX_RING_BUFFER]; /* Tracking queue
> >> index
> >>> +per ring buffer. */
> >>> /* Virtual address of the info memory routed to the this
> >>> function under
> >>>* operation, whether it is PF or VF.
> >>>* HW may DMA information data at this location asynchronously
> >>> diff --git a/drivers/baseband/acc/rte_vrb_pmd.c
> >>> b/drivers/baseband/acc/rte_vrb_pmd.c
> >>> index bae01e563826..2c62a5b3e329 100644
> >>> --- a/drivers/baseband/acc/rte_vrb_pmd.c
> >>> +++ b/drivers/baseband/acc/rte_vrb_pmd.c
> >>> @@ -281,7 +281,7 @@ fetch_acc_config(struct rte_bbdev *dev)
> >>> /* Check the depth of the AQs. */
> >>> reg_len0 = acc_reg_read(d,
> >>> d->reg_addr->depth_log0_offset);
> >>> reg_len1 = acc_reg_read(d,
> >>> d->reg_addr->depth_log1_offset);
> >>> - for (acc = 0; acc < NUM_ACC; acc++) {
> >>> + for (acc = 0; acc < VRB1_NUM_ACCS; acc++) {
> >>> qtopFromAcc(&q_top, acc, acc_conf);
> >>> if (q_top->first_qgroup_index <
> >> ACC_NUM_QGRPS_PER_WORD)
> >>> q_top->aq_depth_log2 =
> >>> @@ -290,7 +290,7 @@ fetch_acc_config(struct rte_bbdev *dev)
> >>> q_top->aq_depth_log2 = (reg_len1 >>
> >>> ((q_top-
> >>> first_qgroup_index -
> >>>
> >>ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;
> >>> }
> >>> - } else {
> >>> + } else if (d->device_variant == VRB2_VARIANT) {
> >>> reg0 = acc_reg_read(d, d->reg_addr->qman_group_func);
> >>> reg1 = acc_reg_read(d, d->reg_addr->qman_group_func +
> >>> 4);
> >>> reg2 = acc_reg_read(d, d->reg_addr->qman_group_func +
> >>> 8);
> >> @@
> >>> -308,7 +308,7 @@ fetch_acc_config(struct rte_bbdev *dev)
> >>> idx = (reg2 >> ((qg %
> >> ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
> >>> else
> >>> idx = (reg3 >> ((qg %
> >> ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;
> >>> - if (idx < VRB_NUM_ACCS) {
> >>> + if (idx < VRB2_NUM_ACCS) {
> >>> acc = qman_func_id[idx];
> >>> updateQtop(acc, qg, acc_conf,
> >>> d);
> >>> }
> >>> @@ -321,7 +321,7 @@ fetch_acc_config(struct rte_bbdev *dev)
> >>> reg_len2 = acc_reg_read(d,
> >>> d->reg_addr->depth_log0_offset +
> >> 8);
> >>> reg_len3 = acc_reg_read(d,
> >>> d->reg_addr->depth_log0_offset +
> >> 12);
> >>>
> >>> - for (acc = 0; acc < NUM_ACC; acc++) {
> >>> + for (acc = 0; acc < VRB2_NUM_ACCS; acc++) {
> >>> qtopFromAcc(&q_top, acc, acc_conf);
> >>>
[PATCH v2] crypto/ipsec_mb: bump minimum IPsec MB version
AESNI_MB SW PMDs increment Intel IPsec MB version to 1.4. A minimum IPsec Multi-buffer version of 1.4 or greater is now required for the 24.11 LTS release. Signed-off-by: Brian Dooley Acked-by: Kai Ji Acked-by: Pablo de Lara --- This patch relates to a deprecation notice sent in the 24.03 release. Intel IPsec MB minimum version being bumped to 1.4 for the 24.11 release. https://patches.dpdk.org/project/dpdk/patch/20240314103731.3242086-2-brian.doo...@intel.com/ v2: Added release note Remove more IMB_VERSION checks --- doc/guides/cryptodevs/aesni_gcm.rst | 3 +- doc/guides/cryptodevs/aesni_mb.rst | 3 +- doc/guides/cryptodevs/chacha20_poly1305.rst | 3 +- doc/guides/cryptodevs/kasumi.rst| 3 +- doc/guides/cryptodevs/snow3g.rst| 3 +- doc/guides/cryptodevs/zuc.rst | 3 +- doc/guides/rel_notes/release_24_11.rst | 7 + drivers/crypto/ipsec_mb/ipsec_mb_ops.c | 24 -- drivers/crypto/ipsec_mb/meson.build | 2 +- drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 268 +--- drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 9 - 11 files changed, 23 insertions(+), 305 deletions(-) diff --git a/doc/guides/cryptodevs/aesni_gcm.rst b/doc/guides/cryptodevs/aesni_gcm.rst index 3af1486553..7592d33da2 100644 --- a/doc/guides/cryptodevs/aesni_gcm.rst +++ b/doc/guides/cryptodevs/aesni_gcm.rst @@ -74,7 +74,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.11 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/aesni_mb.rst b/doc/guides/cryptodevs/aesni_mb.rst index 3c77d0f463..c2f6633ee6 100644 --- a/doc/guides/cryptodevs/aesni_mb.rst +++ b/doc/guides/cryptodevs/aesni_mb.rst @@ -132,7 +132,8 @@ and the Multi-Buffer library version supported by them: DPDK versionMulti-buffer library version == 20.11 - 21.08 0.53 - 1.3 - 21.11+ 1.0 - 1.5 + 21.11 - 24.07 1.0 - 1.5 + 24.11+ 1.4 - 1.5 == Initialization diff --git a/doc/guides/cryptodevs/chacha20_poly1305.rst b/doc/guides/cryptodevs/chacha20_poly1305.rst index 44cff85918..b5a980b247 100644 --- a/doc/guides/cryptodevs/chacha20_poly1305.rst +++ b/doc/guides/cryptodevs/chacha20_poly1305.rst @@ -66,7 +66,8 @@ and the external crypto libraries supported by them: = DPDK version Crypto library version = - 21.11+ Multi-buffer library 1.0-1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/kasumi.rst b/doc/guides/cryptodevs/kasumi.rst index 4070f025e1..b57f18b56f 100644 --- a/doc/guides/cryptodevs/kasumi.rst +++ b/doc/guides/cryptodevs/kasumi.rst @@ -80,7 +80,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.02 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/snow3g.rst b/doc/guides/cryptodevs/snow3g.rst index 6eb8229fb5..fb4e0448ac 100644 --- a/doc/guides/cryptodevs/snow3g.rst +++ b/doc/guides/cryptodevs/snow3g.rst @@ -89,7 +89,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.02 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff --git a/doc/guides/cryptodevs/zuc.rst b/doc/guides/cryptodevs/zuc.rst index 29fe6279aa..4615562246 100644 --- a/doc/guides/cryptodevs/zuc.rst +++ b/doc/guides/cryptodevs/zuc.rst @@ -88,7 +88,8 @@ and the external crypto libraries supported by them: DPDK version Crypto library version = 20.02 - 21.08 Multi-buffer library 0.53 - 1.3 - 21.11+ Multi-buffer library 1.0 - 1.5 + 21.11 - 24.07 Multi-buffer library 1.0 - 1.5 + 24.11+ Multi-buffer library 1.4 - 1.5 = Initialization diff -
Re: [PATCH v8 3/6] eventdev: add event preschedule hint
On Sun, Oct 6, 2024 at 10:44 PM wrote: > > From: Pavan Nikhilesh > > Add a new eventdev API to provide a hint to the eventdev PMD to > pre-schedule the next event into the event port, without releasing > the current flow context. > Event device that support this feature advertises the capability > using the RTE_EVENT_DEV_CAP_PRESCHEDULE_EXPLICIT capability flag. > > Application can invoke `rte_event_port_preschedule` to hint the PMD, > if event device does not support this feature it is treated as a no-op. > > Signed-off-by: Pavan Nikhilesh > --- > Starting the EventDev > ~ > diff --git a/doc/guides/rel_notes/release_24_11.rst > b/doc/guides/rel_notes/release_24_11.rst > index f7cc2ec047..e4ba9c2d53 100644 > --- a/doc/guides/rel_notes/release_24_11.rst > +++ b/doc/guides/rel_notes/release_24_11.rst > @@ -76,7 +76,8 @@ New Features > level pre-scheduling type. >* Added ``rte_event_port_preschedule_modify`` to modify pre-scheduling type > on a given event port. > - 1) Don't delete this new line. Also add new line between features. Final one should like below, * **Added event device pre-scheduling support.** Added support for pre-scheduling of events to event ports to improve scheduling performance and latency. * Added ``rte_event_dev_config::preschedule_type`` to configure the device level pre-scheduling type. * Added ``rte_event_port_preschedule_modify`` to modify pre-scheduling type on a given event port. * Added ``rte_event_port_preschedule`` to allow applications provide explicit pre-schedule hints to event ports. 2)Due to the merge of https://patches.dpdk.org/project/dpdk/list/?series=33326 Capa flags value are changed. Please rebase. > + * Added ``rte_event_port_preschedule`` to allow applications provide > explicit > +pre-schedule hints to event ports. >
RE: [PATCH v6 1/6] cryptodev: add EDDSA asymmetric crypto algorithm
Hi Gowrishankar,
I like the idea of adding EdDSA, but I have several comments.
> -Original Message-
> From: Gowrishankar Muthukrishnan
> Sent: Friday, October 4, 2024 10:26 AM
> To: dev@dpdk.org; Akhil Goyal ; Fan Zhang
>
> Cc: Anoob Joseph ; Richardson, Bruce
> ; jer...@marvell.com; Kusztal, ArkadiuszX
> ; Ji, Kai ; jack.bond-
> pres...@foss.arm.com; Marchand, David ;
> hemant.agra...@nxp.com; De Lara Guarch, Pablo
> ; Trahe, Fiona ;
> Doherty, Declan ; ma...@nvidia.com;
> ruifeng.w...@arm.com; Gowrishankar Muthukrishnan
>
> Subject: [PATCH v6 1/6] cryptodev: add EDDSA asymmetric crypto algorithm
>
> Add support for asymmetric EDDSA in cryptodev, as referenced in RFC:
> https://datatracker.ietf.org/doc/html/rfc8032
>
> Signed-off-by: Gowrishankar Muthukrishnan
> ---
> doc/guides/cryptodevs/features/default.ini | 1 +
> doc/guides/prog_guide/cryptodev_lib.rst| 2 +-
> lib/cryptodev/rte_crypto_asym.h| 47 ++
> 3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/doc/guides/cryptodevs/features/default.ini
> b/doc/guides/cryptodevs/features/default.ini
> index f411d4bab7..3073753911 100644
> --- a/doc/guides/cryptodevs/features/default.ini
> +++ b/doc/guides/cryptodevs/features/default.ini
> @@ -130,6 +130,7 @@ ECDSA =
> ECPM=
> ECDH=
> SM2 =
> +EDDSA =
>
> ;
> ; Supported Operating systems of a default crypto driver.
> diff --git a/doc/guides/prog_guide/cryptodev_lib.rst
> b/doc/guides/prog_guide/cryptodev_lib.rst
> index 2b513bbf82..dd636ba5ef 100644
> --- a/doc/guides/prog_guide/cryptodev_lib.rst
> +++ b/doc/guides/prog_guide/cryptodev_lib.rst
> @@ -927,7 +927,7 @@ Asymmetric Cryptography The cryptodev library
> currently provides support for the following asymmetric Crypto operations;
> RSA, Modular exponentiation and inversion, Diffie-Hellman and Elliptic Curve
> Diffie-Hellman public and/or private key generation and shared -secret
> compute,
> DSA Signature generation and verification.
> +secret compute, DSA and EdDSA Signature generation and verification.
>
> Session and Session Management
> ~~
> diff --git a/lib/cryptodev/rte_crypto_asym.h b/lib/cryptodev/rte_crypto_asym.h
> index 39d3da3952..fe4194c184 100644
> --- a/lib/cryptodev/rte_crypto_asym.h
> +++ b/lib/cryptodev/rte_crypto_asym.h
> @@ -49,6 +49,10 @@ rte_crypto_asym_op_strings[];
> * and if the flag is not set, shared secret will be padded to the left with
> * zeros to the size of the underlying algorithm (default)
> */
> +#define RTE_CRYPTO_ASYM_FLAG_PUB_KEY_COMPRESSED
> RTE_BIT32(2)
> +/**<
> + * Flag to denote public key will be returned in compressed form */
>
> /**
> * List of elliptic curves. This enum aligns with @@ -65,9 +69,22 @@ enum
> rte_crypto_curve_id {
> RTE_CRYPTO_EC_GROUP_SECP256R1 = 23,
> RTE_CRYPTO_EC_GROUP_SECP384R1 = 24,
> RTE_CRYPTO_EC_GROUP_SECP521R1 = 25,
> + RTE_CRYPTO_EC_GROUP_ED25519 = 29,
> + RTE_CRYPTO_EC_GROUP_ED448 = 30,
> RTE_CRYPTO_EC_GROUP_SM2 = 41,
> };
>
> +/**
> + * List of Edwards curve instances as per RFC 8032 (Section 5).
> + */
> +enum rte_crypto_edward_instance {
> + RTE_CRYPTO_EDCURVE_25519,
> + RTE_CRYPTO_EDCURVE_25519CTX,
> + RTE_CRYPTO_EDCURVE_25519PH,
> + RTE_CRYPTO_EDCURVE_448,
> + RTE_CRYPTO_EDCURVE_448PH
> +};
> +
> /**
> * Asymmetric crypto transformation types.
> * Each xform type maps to one asymmetric algorithm @@ -119,6 +136,10 @@
> enum rte_crypto_asym_xform_type {
>* Performs Encrypt, Decrypt, Sign and Verify.
>* Refer to rte_crypto_asym_op_type.
>*/
> + RTE_CRYPTO_ASYM_XFORM_EDDSA,
> + /**< Edwards Curve Digital Signature Algorithm
> + * Perform Signature Generation and Verification.
> + */
> RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END
> /**< End of list */
> };
> @@ -585,6 +606,31 @@ struct rte_crypto_ecdsa_op_param {
>*/
> };
>
> +/**
> + * EdDSA operation params
> + */
> +struct rte_crypto_eddsa_op_param {
> + enum rte_crypto_asym_op_type op_type;
> + /**< Signature generation or verification */
> +
> + rte_crypto_param message;
> + /**< Input message digest to be signed or verified */
HashEdDSA will require a message digest; pure EdDSA will require the message
itself. For HW it will be more complicated.
> +
> + rte_crypto_param context;
> + /**< Context value for the sign op.
> + * Must not be empty for Ed25519ctx instance.
> + */
> +
> + enum rte_crypto_edward_instance instance;
> + /**< Type of Edwards curve. */
All instances are using the same curve, where they differ is the way of
handling input message.
And I think this should be a session variable -> new xform for the EdDSA.
> +
> + rte_crypto_uint sign;
> + /**< Edward curve signature
> + * output : for signature gen
Re: [PATCH 1/5] config/riscv: add flag for using Zbc extension
On Mon, 7 Oct 2024 10:14:22 +0200 Stanisław Kardach wrote: > > > > > > > > Please do not add more config options via compile flags. > > > > It makes it impossible for distros to ship one version. > That is a problem with RISC-V in general. Since all features are > "extensions" and there is no limit (up to a point) on the permutation > of those, we cannot statically build the code for all extensions. > Fortunately instructions tend to resolve to nops if an instruction is > not present but that still increases the code size for no benefit on > platforms without a given extension. X86 already has the cpu feature flag infrastructure, why not use similar mechanism on RiscV?
Re: [PATCH 4/4] ethdev: add traffic manager query function
On Sun, Sep 22, 2024 at 05:26:30PM +0100, Ferruh Yigit wrote: > On 8/6/2024 4:24 PM, Bruce Richardson wrote: > > +/** > > + * Return information about a traffic management node > > + * > > + * Return information about a hierarchy node, using the same format of > > parameters > > + * as was passed to the rte_rm_node_add() function. > > + * Each of the "out" parameters pointers (except error) may be passed as > > NULL if the > > + * information is not needed by the caller. For example, to one may check > > if a node id > > + * is in use by: > > + * > > + * struct rte_tm_error error; > > + * int ret = rte_tm_node_query(port, node_id, NULL, NULL, NULL, NULL, > > NULL, &error); > > + * if (ret == ENOENT) ... > > + * > > + * @param[in] port_id > > + * The port identifier of the Ethernet device. > > + * @param[in] node_id > > + * Node ID. Should be a valid node id. > > + * @param[out] parent_node_id > > + * Parent node ID. > > + * @param[out] priority > > + * Node priority. The highest node priority is zero. Used by the SP > > algorithm > > + * running on the parent of the current node for scheduling this child > > node. > > + * @param[out] weight > > + * Node weight. The node weight is relative to the weight sum of all > > siblings > > + * that have the same priority. The lowest weight is one. Used by the WFQ > > + * algorithm running on the parent of the current node for scheduling > > this > > + * child node. > > + * @param[out] level_id > > + * The node level in the scheduler hierarchy. > > + * @param[out] params > > + * Node parameters, as would be used when creating the node. > > + * @param[out] error > > + * Error details. Filled in only on error, when not NULL. > > + * @return > > + * 0 on success, non-zero error code otherwise. > > + * -EINVAL - port or node id value is invalid > > + * -ENOENT - no node exists with the provided id > > + */ > > +int > > +rte_tm_node_query(uint16_t port_id, > > + uint32_t node_id, > > + uint32_t *parent_node_id, > > + uint32_t *priority, > > + uint32_t *weight, > > + uint32_t *level_id, > > + struct rte_tm_node_params *params, > > + struct rte_tm_error *error); > > + > > > > No objection to get an TM node query API overall, but it would be good > to get more comment on the what correct API should be, we are missing it. > Both because it is not discussed much, and it is first release, better > to add this API as experimental. > Yes, good point, it should be added to version.map file and marked as experimental. Happy to take any feedback on what the API should be. > Also we should have an implementation in driver and a sample application > usage (testpmd?) with new API. Are these planned separately for this > release, or can it be available part of next version of this patch? > I have an implemented for ice driver in [1]. On testpmd side, I never thought to do so, because it was more for me when writing test code around the APIs than for actual end-users. [As I explain, this API should save app developers the work of storing a copy of the TM hierarchy in the app code too]. However, I think it may be no harm to do a testpmd call for it, it may be useful for debugging. [1] https://patches.dpdk.org/project/dpdk/patch/20240812152815.1132697-2-bruce.richard...@intel.com/ > Finally, does it worth documenting this in release notes, as just a > query API I am not sure if this a notable feature, but just a reminder. > Don't think it requires an RN item. Will perhaps do a new revision of this patchset without this final patch, and then submit this patch as a separate one for tracking. I don't think the other patches to mark things const should be blocked by discussion on this. Regards, /Bruce
[PATCH v9 1/6] eventdev: introduce event pre-scheduling
From: Pavan Nikhilesh
Event pre-scheduling improves scheduling performance by assigning events
to event ports in advance when dequeues are issued.
The dequeue operation initiates the pre-schedule operation, which completes
in parallel without affecting the dequeued event flow contexts and
dequeue latency.
Event devices can indicate pre-scheduling capabilities using
`RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE` and
`RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE` via the event device info
function `info.event_dev_cap`.
Applications can select the pre-schedule type and configure it through
`rte_event_dev_config.preschedule_type` during `rte_event_dev_configure`.
The supported pre-schedule types are:
* `RTE_EVENT_PRESCHEDULE_NONE` - No pre-scheduling.
* `RTE_EVENT_PRESCHEDULE` - Always issue a pre-schedule on dequeue.
* `RTE_EVENT_PRESCHEDULE_ADAPTIVE` - Delay issuing pre-schedule until
there are no forward progress constraints with the held flow contexts.
Signed-off-by: Pavan Nikhilesh
---
app/test/test_eventdev.c| 108
doc/guides/eventdevs/features/default.ini | 1 +
doc/guides/prog_guide/eventdev/eventdev.rst | 23 +
doc/guides/rel_notes/release_24_11.rst | 10 ++
lib/eventdev/rte_eventdev.h | 49 +
5 files changed, 191 insertions(+)
diff --git a/app/test/test_eventdev.c b/app/test/test_eventdev.c
index 9a6c8f470c..a45d1396d7 100644
--- a/app/test/test_eventdev.c
+++ b/app/test/test_eventdev.c
@@ -1251,6 +1251,112 @@ test_eventdev_profile_switch(void)
return TEST_SUCCESS;
}
+static int
+preschedule_test(enum rte_event_dev_preschedule_type preschedule_type, const
char *preschedule_name)
+{
+#define NB_EVENTS 1024
+ uint64_t start, total;
+ struct rte_event ev;
+ int rc, cnt;
+
+ ev.event_type = RTE_EVENT_TYPE_CPU;
+ ev.queue_id = 0;
+ ev.op = RTE_EVENT_OP_NEW;
+ ev.u64 = 0xBADF00D0;
+
+ for (cnt = 0; cnt < NB_EVENTS; cnt++) {
+ ev.flow_id = cnt;
+ rc = rte_event_enqueue_burst(TEST_DEV_ID, 0, &ev, 1);
+ TEST_ASSERT(rc == 1, "Failed to enqueue event");
+ }
+
+ RTE_SET_USED(preschedule_type);
+ total = 0;
+ while (cnt) {
+ start = rte_rdtsc_precise();
+ rc = rte_event_dequeue_burst(TEST_DEV_ID, 0, &ev, 1, 0);
+ if (rc) {
+ total += rte_rdtsc_precise() - start;
+ cnt--;
+ }
+ }
+ printf("Preschedule type : %s, avg cycles %" PRIu64 "\n",
preschedule_name,
+ total / NB_EVENTS);
+
+ return TEST_SUCCESS;
+}
+
+static int
+preschedule_configure(enum rte_event_dev_preschedule_type type, struct
rte_event_dev_info *info)
+{
+ struct rte_event_dev_config dev_conf;
+ struct rte_event_queue_conf qcfg;
+ struct rte_event_port_conf pcfg;
+ int rc;
+
+ devconf_set_default_sane_values(&dev_conf, info);
+ dev_conf.nb_event_ports = 1;
+ dev_conf.nb_event_queues = 1;
+ dev_conf.preschedule_type = type;
+
+ rc = rte_event_dev_configure(TEST_DEV_ID, &dev_conf);
+ TEST_ASSERT_SUCCESS(rc, "Failed to configure eventdev");
+
+ rc = rte_event_port_default_conf_get(TEST_DEV_ID, 0, &pcfg);
+ TEST_ASSERT_SUCCESS(rc, "Failed to get port0 default config");
+ rc = rte_event_port_setup(TEST_DEV_ID, 0, &pcfg);
+ TEST_ASSERT_SUCCESS(rc, "Failed to setup port0");
+
+ rc = rte_event_queue_default_conf_get(TEST_DEV_ID, 0, &qcfg);
+ TEST_ASSERT_SUCCESS(rc, "Failed to get queue0 default config");
+ rc = rte_event_queue_setup(TEST_DEV_ID, 0, &qcfg);
+ TEST_ASSERT_SUCCESS(rc, "Failed to setup queue0");
+
+ rc = rte_event_port_link(TEST_DEV_ID, 0, NULL, NULL, 0);
+ TEST_ASSERT(rc == (int)dev_conf.nb_event_queues, "Failed to link port,
device %d",
+ TEST_DEV_ID);
+
+ rc = rte_event_dev_start(TEST_DEV_ID);
+ TEST_ASSERT_SUCCESS(rc, "Failed to start event device");
+
+ return 0;
+}
+
+static int
+test_eventdev_preschedule_configure(void)
+{
+ struct rte_event_dev_info info;
+ int rc;
+
+ rte_event_dev_info_get(TEST_DEV_ID, &info);
+
+ if ((info.event_dev_cap & RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE) == 0)
+ return TEST_SKIPPED;
+
+ rc = preschedule_configure(RTE_EVENT_PRESCHEDULE_NONE, &info);
+ TEST_ASSERT_SUCCESS(rc, "Failed to configure eventdev");
+ rc = preschedule_test(RTE_EVENT_PRESCHEDULE_NONE,
"RTE_EVENT_PRESCHEDULE_NONE");
+ TEST_ASSERT_SUCCESS(rc, "Failed to test preschedule
RTE_EVENT_PRESCHEDULE_NONE");
+
+ rte_event_dev_stop(TEST_DEV_ID);
+ rc = preschedule_configure(RTE_EVENT_PRESCHEDULE, &info);
+ TEST_ASSERT_SUCCESS(rc, "Failed to configure eventdev");
+ rc = preschedule_test(RTE_EVENT_PRESCHEDULE, "RTE_EVENT_PRESCHEDULE");
+ TEST_ASSERT_SUCCESS(rc, "Fai
[PATCH v9 2/6] eventdev: add event port pre-schedule modify
From: Pavan Nikhilesh
Some event devices allow pre-schedule types to be modified at
runtime on an event port.
Add `RTE_EVENT_DEV_CAP_PER_PORT_PRESCHEDULE` capability
to indicate that the event device supports this feature.
Add `rte_event_port_preschedule_modify()` API to modify the
pre-schedule type at runtime.
To avoid fastpath capability checks, the API reports -ENOTSUP
if the event device does not support this feature.
Signed-off-by: Pavan Nikhilesh
---
app/test/test_eventdev.c| 45 +--
doc/guides/prog_guide/eventdev/eventdev.rst | 16 ++
doc/guides/rel_notes/release_24_11.rst | 3 +
lib/eventdev/eventdev_pmd.h | 2 +
lib/eventdev/eventdev_private.c | 20 +++
lib/eventdev/eventdev_trace_points.c| 3 +
lib/eventdev/rte_eventdev.h | 61 +
lib/eventdev/rte_eventdev_core.h| 8 ++-
lib/eventdev/rte_eventdev_trace_fp.h| 11 +++-
lib/eventdev/version.map| 4 ++
10 files changed, 166 insertions(+), 7 deletions(-)
diff --git a/app/test/test_eventdev.c b/app/test/test_eventdev.c
index a45d1396d7..a9258d2abc 100644
--- a/app/test/test_eventdev.c
+++ b/app/test/test_eventdev.c
@@ -1252,7 +1252,8 @@ test_eventdev_profile_switch(void)
}
static int
-preschedule_test(enum rte_event_dev_preschedule_type preschedule_type, const
char *preschedule_name)
+preschedule_test(enum rte_event_dev_preschedule_type preschedule_type, const
char *preschedule_name,
+uint8_t modify)
{
#define NB_EVENTS 1024
uint64_t start, total;
@@ -1270,7 +1271,11 @@ preschedule_test(enum rte_event_dev_preschedule_type
preschedule_type, const cha
TEST_ASSERT(rc == 1, "Failed to enqueue event");
}
- RTE_SET_USED(preschedule_type);
+ if (modify) {
+ rc = rte_event_port_preschedule_modify(TEST_DEV_ID, 0,
preschedule_type);
+ TEST_ASSERT_SUCCESS(rc, "Failed to modify preschedule type");
+ }
+
total = 0;
while (cnt) {
start = rte_rdtsc_precise();
@@ -1335,13 +1340,13 @@ test_eventdev_preschedule_configure(void)
rc = preschedule_configure(RTE_EVENT_PRESCHEDULE_NONE, &info);
TEST_ASSERT_SUCCESS(rc, "Failed to configure eventdev");
- rc = preschedule_test(RTE_EVENT_PRESCHEDULE_NONE,
"RTE_EVENT_PRESCHEDULE_NONE");
+ rc = preschedule_test(RTE_EVENT_PRESCHEDULE_NONE,
"RTE_EVENT_PRESCHEDULE_NONE", 0);
TEST_ASSERT_SUCCESS(rc, "Failed to test preschedule
RTE_EVENT_PRESCHEDULE_NONE");
rte_event_dev_stop(TEST_DEV_ID);
rc = preschedule_configure(RTE_EVENT_PRESCHEDULE, &info);
TEST_ASSERT_SUCCESS(rc, "Failed to configure eventdev");
- rc = preschedule_test(RTE_EVENT_PRESCHEDULE, "RTE_EVENT_PRESCHEDULE");
+ rc = preschedule_test(RTE_EVENT_PRESCHEDULE, "RTE_EVENT_PRESCHEDULE",
0);
TEST_ASSERT_SUCCESS(rc, "Failed to test preschedule
RTE_EVENT_PRESCHEDULE");
if (info.event_dev_cap & RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE) {
@@ -1349,7 +1354,7 @@ test_eventdev_preschedule_configure(void)
rc = preschedule_configure(RTE_EVENT_PRESCHEDULE_ADAPTIVE,
&info);
TEST_ASSERT_SUCCESS(rc, "Failed to configure eventdev");
rc = preschedule_test(RTE_EVENT_PRESCHEDULE_ADAPTIVE,
- "RTE_EVENT_PRESCHEDULE_ADAPTIVE");
+ "RTE_EVENT_PRESCHEDULE_ADAPTIVE", 0);
TEST_ASSERT_SUCCESS(rc,
"Failed to test preschedule
RTE_EVENT_PRESCHEDULE_ADAPTIVE");
}
@@ -1357,6 +1362,34 @@ test_eventdev_preschedule_configure(void)
return TEST_SUCCESS;
}
+static int
+test_eventdev_preschedule_modify(void)
+{
+ struct rte_event_dev_info info;
+ int rc;
+
+ rte_event_dev_info_get(TEST_DEV_ID, &info);
+ if ((info.event_dev_cap & RTE_EVENT_DEV_CAP_PER_PORT_PRESCHEDULE) == 0)
+ return TEST_SKIPPED;
+
+ rc = preschedule_configure(RTE_EVENT_PRESCHEDULE_NONE, &info);
+ TEST_ASSERT_SUCCESS(rc, "Failed to configure eventdev");
+ rc = preschedule_test(RTE_EVENT_PRESCHEDULE_NONE,
"RTE_EVENT_PRESCHEDULE_NONE", 1);
+ TEST_ASSERT_SUCCESS(rc, "Failed to test per port preschedule
RTE_EVENT_PRESCHEDULE_NONE");
+
+ rc = preschedule_test(RTE_EVENT_PRESCHEDULE, "RTE_EVENT_PRESCHEDULE",
1);
+ TEST_ASSERT_SUCCESS(rc, "Failed to test per port preschedule
RTE_EVENT_PRESCHEDULE");
+
+ if (info.event_dev_cap & RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE) {
+ rc = preschedule_test(RTE_EVENT_PRESCHEDULE_ADAPTIVE,
+ "RTE_EVENT_PRESCHEDULE_ADAPTIVE", 1);
+ TEST_ASSERT_SUCCESS(
+ rc, "Failed to test per port preschedule
RTE_EVENT_PRESCHEDULE_ADAPTIVE");
+ }
+
+ return TE
[PATCH v9 3/6] eventdev: add event preschedule hint
From: Pavan Nikhilesh
Add a new eventdev API to provide a hint to the eventdev PMD to
pre-schedule the next event into the event port, without releasing
the current flow context.
Event device that support this feature advertises the capability
using the RTE_EVENT_DEV_CAP_PRESCHEDULE_EXPLICIT capability flag.
Application can invoke `rte_event_port_preschedule` to hint the PMD,
if event device does not support this feature it is treated as a no-op.
Signed-off-by: Pavan Nikhilesh
---
doc/guides/prog_guide/eventdev/eventdev.rst | 9
doc/guides/rel_notes/release_24_11.rst | 3 ++
lib/eventdev/eventdev_pmd.h | 2 +
lib/eventdev/eventdev_private.c | 21 -
lib/eventdev/eventdev_trace_points.c| 3 ++
lib/eventdev/rte_eventdev.h | 51 +
lib/eventdev/rte_eventdev_core.h| 8 +++-
lib/eventdev/rte_eventdev_trace_fp.h| 8
lib/eventdev/version.map| 2 +
9 files changed, 104 insertions(+), 3 deletions(-)
diff --git a/doc/guides/prog_guide/eventdev/eventdev.rst
b/doc/guides/prog_guide/eventdev/eventdev.rst
index e3fbfb11f4..d360cf86cd 100644
--- a/doc/guides/prog_guide/eventdev/eventdev.rst
+++ b/doc/guides/prog_guide/eventdev/eventdev.rst
@@ -395,6 +395,15 @@ will be treated as a no-op.
// Disable pre-scheduling if thread is about to be scheduled out and issue
dequeue() to drain
// pending events.
+Application may provide a hint to the eventdev PMD to pre-schedule the next
event without
+releasing the current flow context. Event device that support this feature
advertises
+the capability via the ``RTE_EVENT_DEV_CAP_PRESCHEDULE_EXPLICIT`` flag.
+If pre-scheduling is already enabled at a event device or event port level or
if the
+capability is not supported then the hint is ignored.
+
+.. code-block:: c
+
+ rte_event_port_preschedule(dev_id, port_id, RTE_EVENT_PRESCHEDULE);
Starting the EventDev
~
diff --git a/doc/guides/rel_notes/release_24_11.rst
b/doc/guides/rel_notes/release_24_11.rst
index e13a7479ce..2671cae9a8 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -90,6 +90,9 @@ New Features
* Added ``rte_event_port_preschedule_modify`` to modify pre-scheduling type
on a given event port.
+ * Added ``rte_event_port_preschedule`` to allow applications provide explicit
+pre-schedule hints to event ports.
+
Removed Items
-
diff --git a/lib/eventdev/eventdev_pmd.h b/lib/eventdev/eventdev_pmd.h
index 9ea23aa6cd..0bee2347ef 100644
--- a/lib/eventdev/eventdev_pmd.h
+++ b/lib/eventdev/eventdev_pmd.h
@@ -186,6 +186,8 @@ struct __rte_cache_aligned rte_eventdev {
/**< Pointer to PMD Event switch profile function. */
event_preschedule_modify_t preschedule_modify;
/**< Pointer to PMD Event port pre-schedule type modify function. */
+ event_preschedule_t preschedule;
+ /**< Pointer to PMD Event port pre-schedule function. */
uint64_t reserved_64s[3]; /**< Reserved for future fields */
void *reserved_ptrs[3]; /**< Reserved for future fields */
diff --git a/lib/eventdev/eventdev_private.c b/lib/eventdev/eventdev_private.c
index cc5963b31b..b628f4a69e 100644
--- a/lib/eventdev/eventdev_private.c
+++ b/lib/eventdev/eventdev_private.c
@@ -111,6 +111,19 @@ dummy_event_port_preschedule_modify_hint(
return -ENOTSUP;
}
+static void
+dummy_event_port_preschedule(__rte_unused void *port,
+__rte_unused enum rte_event_dev_preschedule_type
preschedule)
+{
+ RTE_EDEV_LOG_ERR("pre-schedule requested for unconfigured event
device");
+}
+
+static void
+dummy_event_port_preschedule_hint(__rte_unused void *port,
+ __rte_unused enum
rte_event_dev_preschedule_type preschedule)
+{
+}
+
void
event_dev_fp_ops_reset(struct rte_event_fp_ops *fp_op)
{
@@ -124,12 +137,12 @@ event_dev_fp_ops_reset(struct rte_event_fp_ops *fp_op)
.dequeue_burst = dummy_event_dequeue_burst,
.maintain = dummy_event_maintain,
.txa_enqueue = dummy_event_tx_adapter_enqueue,
- .txa_enqueue_same_dest =
- dummy_event_tx_adapter_enqueue_same_dest,
+ .txa_enqueue_same_dest =
dummy_event_tx_adapter_enqueue_same_dest,
.ca_enqueue = dummy_event_crypto_adapter_enqueue,
.dma_enqueue = dummy_event_dma_adapter_enqueue,
.profile_switch = dummy_event_port_profile_switch,
.preschedule_modify = dummy_event_port_preschedule_modify,
+ .preschedule = dummy_event_port_preschedule,
.data = dummy_data,
};
@@ -153,8 +166,12 @@ event_dev_fp_ops_set(struct rte_event_fp_ops *fp_op,
fp_op->dma_enqueue = dev->dma_enqueue;
fp_op->profile_switch = dev->profile_switch;
fp_op->preschedule_m
[PATCH v9 4/6] event/cnkx: add pre-schedule support
From: Pavan Nikhilesh
Add device level and port level pre-schedule
support for cnxk eventdev.
Signed-off-by: Pavan Nikhilesh
---
doc/guides/eventdevs/cnxk.rst | 10 --
doc/guides/eventdevs/features/cnxk.ini | 1 +
drivers/event/cnxk/cn10k_eventdev.c| 19 +--
drivers/event/cnxk/cn10k_worker.c | 21 +
drivers/event/cnxk/cn10k_worker.h | 2 ++
drivers/event/cnxk/cnxk_eventdev.c | 2 --
drivers/event/cnxk/cnxk_eventdev.h | 1 -
7 files changed, 41 insertions(+), 15 deletions(-)
diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst
index d038930594..e21846f4e0 100644
--- a/doc/guides/eventdevs/cnxk.rst
+++ b/doc/guides/eventdevs/cnxk.rst
@@ -78,16 +78,6 @@ Runtime Config Options
-a 0002:0e:00.0,single_ws=1
-- ``CN10K Getwork mode``
-
- CN10K supports three getwork prefetch modes no prefetch[0], prefetch
- immediately[1] and delayed prefetch on forward progress event[2].
- The default getwork mode is 2.
-
- For example::
-
--a 0002:0e:00.0,gw_mode=1
-
- ``Event Group QoS support``
SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight
diff --git a/doc/guides/eventdevs/features/cnxk.ini
b/doc/guides/eventdevs/features/cnxk.ini
index d1516372fa..5ba528f086 100644
--- a/doc/guides/eventdevs/features/cnxk.ini
+++ b/doc/guides/eventdevs/features/cnxk.ini
@@ -17,6 +17,7 @@ carry_flow_id = Y
maintenance_free = Y
runtime_queue_attr = Y
profile_links = Y
+preschedule= Y
[Eth Rx adapter Features]
internal_port = Y
diff --git a/drivers/event/cnxk/cn10k_eventdev.c
b/drivers/event/cnxk/cn10k_eventdev.c
index 2d7b169974..5bd779990e 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -527,6 +527,7 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
event_dev->dma_enqueue = cn10k_dma_adapter_enqueue;
event_dev->profile_switch = cn10k_sso_hws_profile_switch;
+ event_dev->preschedule_modify = cn10k_sso_hws_preschedule_modify;
#else
RTE_SET_USED(event_dev);
#endif
@@ -541,6 +542,9 @@ cn10k_sso_info_get(struct rte_eventdev *event_dev,
dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
cnxk_sso_info_get(dev, dev_info);
dev_info->max_event_port_enqueue_depth = UINT32_MAX;
+ dev_info->event_dev_cap |= RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE |
+ RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE
|
+ RTE_EVENT_DEV_CAP_PER_PORT_PRESCHEDULE;
}
static int
@@ -566,6 +570,19 @@ cn10k_sso_dev_configure(const struct rte_eventdev
*event_dev)
if (rc < 0)
goto cnxk_rsrc_fini;
+ switch (event_dev->data->dev_conf.preschedule_type) {
+ default:
+ case RTE_EVENT_PRESCHEDULE_NONE:
+ dev->gw_mode = CN10K_GW_MODE_NONE;
+ break;
+ case RTE_EVENT_PRESCHEDULE:
+ dev->gw_mode = CN10K_GW_MODE_PREF;
+ break;
+ case RTE_EVENT_PRESCHEDULE_ADAPTIVE:
+ dev->gw_mode = CN10K_GW_MODE_PREF_WFE;
+ break;
+ }
+
rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
cn10k_sso_hws_setup);
if (rc < 0)
@@ -1199,7 +1216,6 @@ cn10k_sso_init(struct rte_eventdev *event_dev)
return 0;
}
- dev->gw_mode = CN10K_GW_MODE_PREF_WFE;
rc = cnxk_sso_init(event_dev);
if (rc < 0)
return rc;
@@ -1256,7 +1272,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "="
CNXK_SSO_GGRP_QOS "="
CNXK_SSO_FORCE_BP "=1"
- CN10K_SSO_GW_MODE "="
CN10K_SSO_STASH "="
CNXK_TIM_DISABLE_NPA "=1"
CNXK_TIM_CHNK_SLOTS "="
diff --git a/drivers/event/cnxk/cn10k_worker.c
b/drivers/event/cnxk/cn10k_worker.c
index d59769717e..a0e85face1 100644
--- a/drivers/event/cnxk/cn10k_worker.c
+++ b/drivers/event/cnxk/cn10k_worker.c
@@ -442,3 +442,24 @@ cn10k_sso_hws_profile_switch(void *port, uint8_t profile)
return 0;
}
+
+int __rte_hot
+cn10k_sso_hws_preschedule_modify(void *port, enum
rte_event_dev_preschedule_type type)
+{
+ struct cn10k_sso_hws *ws = port;
+
+ ws->gw_wdata &= ~(BIT(19) | BIT(20));
+ switch (type) {
+ default:
+ case RTE_EVENT_PRESCHEDULE_NONE:
+ break;
+ case RTE_EVENT_PRESCHEDULE:
+ ws->gw_wdata |= BIT(19);
+ break;
+ case RTE_EVENT_PRESCHEDULE_ADAPTIVE:
+ ws->gw_wdata |= BIT(19) | BIT(20);
+ break;
+ }
+
+ return 0;
+}
diff --git a/drivers/event/cnxk/cn10k_worker.h
b/drive
[PATCH v9 0/6] Introduce event pre-scheduling
From: Pavan Nikhilesh Event pre-scheduling improves scheduling performance by assigning events to event ports in advance when dequeues are issued. This series introduces various types and levels of pre-scheduling to the eventdev library. pre-scheduling Types: * RTE_EVENT_PRESCHEDULE_NONE: No pre-scheduling. * RTE_EVENT_PRESCHEDULE: Always issue a pre-schedule when dequeue is issued. * RTE_EVENT_PRESCHEDULE_ADAPTIVE: Delay issuing pre-schedule until there are no forward progress constraints with the held flow contexts. pre-scheduling Levels: * Event Device Level Pre-scheduling: Pre-scheduling can be enabled or disabled at the event device during configuration. Event devices can indicate pre-scheduling capabilities using `RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE` and `RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE` via the event device info function `info.event_dev_cap`. * Event Port Level Prefetch: Pre-scheduling can be selectively enabled or disabled at the event port during runtime. Event devices can indicate this capability using `RTE_EVENT_PORT_CAP_PER_PORT_PRESCHEDULE` via the event device info function `info.event_port_cap`. * Application Controlled Prefetch Hint: Applications can provide hints to the event device to start pre-scheduling events using the new API `rte_event_port_pre-schedule`. Event devices can indicate this capabilities using `RTE_EVENT_DEV_CAP_PRESCHEDULE_EXPLICIT` via the event device info function `info.event_dev_cap`. The rte_event_dequeue_burst operation initiates the pre-schedule operation, which completes in parallel without affecting the flow context of the dequeued events and dequeue latency. On the next dequeue operation, the pre-scheduleed events are dequeued, and pre-schedule operation is initiated again. In the case of application-controlled pre-schedule hints, the currently held flow contexts, if any, are not affected by the pre-schedule operation. On the next dequeue operation, the pre-scheduleed events are returned, but pre-schedule is not initiated again until the application provides the hint again. If pre-scheduling is already enabled at the event device level or event port level, the hint is ignored. v2 Changes: - s/prefetch/pre-schedule (Mattias). v3 Changes: - Add CNXK preschedule implementation. - Update test-eventdev to use prescheduling. - Update examples to use prescheduling. v4 Changes: - Fix compilation. v5 Changes: - Update ABI changes - s/RTE_EVENT_DEV_PRESCHEDULE/RTE_EVENT_PRESCHEDULE/ - s/RTE_EVENT_DEV_CAP_SW_PRESCHEDULE/RTE_EVENT_DEV_CAP_PRESCHEDULE_EXPLICIT/ - s/RTE_EVENT_PORT_CAP_EVENT_PER_PORT_PRESCHEDULE/RTE_EVENT_PORT_CAP_PER_PORT_PRESCHEDULE - Various documentation fixes and updates. v6 Changes: - Mark new APIs as experimental (Stephen). v7 Changes: - Use correct patchset for rebase. v8 Changes: - fix checkpatch issues. v9 Changes: - Rebase update capability bits, fix release notes format. Pavan Nikhilesh (6): eventdev: introduce event pre-scheduling eventdev: add event port pre-schedule modify eventdev: add event preschedule hint event/cnkx: add pre-schedule support app/test-eventdev: add pre-scheduling support examples: use eventdev pre-scheduling app/test-eventdev/evt_common.h| 45 +++-- app/test-eventdev/evt_options.c | 17 ++ app/test-eventdev/evt_options.h | 1 + app/test/test_eventdev.c | 143 doc/guides/eventdevs/cnxk.rst | 10 -- doc/guides/eventdevs/features/cnxk.ini| 1 + doc/guides/eventdevs/features/default.ini | 1 + doc/guides/prog_guide/eventdev/eventdev.rst | 48 ++ doc/guides/rel_notes/release_24_11.rst| 16 ++ doc/guides/tools/testeventdev.rst | 6 + drivers/event/cnxk/cn10k_eventdev.c | 19 ++- drivers/event/cnxk/cn10k_worker.c | 21 +++ drivers/event/cnxk/cn10k_worker.h | 2 + drivers/event/cnxk/cnxk_eventdev.c| 2 - drivers/event/cnxk/cnxk_eventdev.h| 1 - .../pipeline_worker_generic.c | 6 + .../eventdev_pipeline/pipeline_worker_tx.c| 6 + examples/ipsec-secgw/event_helper.c | 6 + examples/l2fwd-event/l2fwd_event_generic.c| 6 + .../l2fwd-event/l2fwd_event_internal_port.c | 6 + examples/l3fwd/l3fwd_event_generic.c | 6 + examples/l3fwd/l3fwd_event_internal_port.c| 6 + lib/eventdev/eventdev_pmd.h | 4 + lib/eventdev/eventdev_private.c | 41 - lib/eventdev/eventdev_trace_points.c | 6 + lib/eventdev/rte_eventdev.h | 161 ++ lib/eventdev/rte_eventdev_core.h | 14 +- lib/eventdev/rte_eventdev_trace_fp.h | 19 ++- lib/eventdev/version.map | 6 + 29 files changed, 597 insertions(+), 29 deletions(-) -- 2.25.1
[PATCH v9 5/6] app/test-eventdev: add pre-scheduling support
From: Pavan Nikhilesh
Add support to configure pre-scheduling for eventdev
test application.
Option `--preschedule`
0 - Disable pre-scheduling.
1 - Enable pre-scheduling.
2 - Enable pre-schedule with adaptive mode (Default).
Signed-off-by: Pavan Nikhilesh
---
app/test-eventdev/evt_common.h| 45 ---
app/test-eventdev/evt_options.c | 17
app/test-eventdev/evt_options.h | 1 +
doc/guides/tools/testeventdev.rst | 6 +
4 files changed, 59 insertions(+), 10 deletions(-)
diff --git a/app/test-eventdev/evt_common.h b/app/test-eventdev/evt_common.h
index dbe1e5c0c4..901b8ba55d 100644
--- a/app/test-eventdev/evt_common.h
+++ b/app/test-eventdev/evt_common.h
@@ -64,6 +64,8 @@ struct evt_options {
uint8_t nb_timer_adptrs;
uint8_t timdev_use_burst;
uint8_t per_port_pool;
+ uint8_t preschedule;
+ uint8_t preschedule_opted;
uint8_t sched_type_list[EVT_MAX_STAGES];
uint16_t mbuf_sz;
uint16_t wkr_deq_dep;
@@ -184,6 +186,30 @@ evt_configure_eventdev(struct evt_options *opt, uint8_t
nb_queues,
return ret;
}
+ if (opt->preschedule_opted && opt->preschedule) {
+ switch (opt->preschedule) {
+ case RTE_EVENT_PRESCHEDULE_ADAPTIVE:
+ if (!(info.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE)) {
+ evt_err("Preschedule type %d not supported",
opt->preschedule);
+ return -EINVAL;
+ }
+ break;
+ case RTE_EVENT_PRESCHEDULE:
+ if (!(info.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE)) {
+ evt_err("Preschedule type %d not supported",
opt->preschedule);
+ return -EINVAL;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (!opt->preschedule_opted) {
+ if (info.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE)
+ opt->preschedule = RTE_EVENT_PRESCHEDULE_ADAPTIVE;
+ }
+
if (opt->deq_tmo_nsec) {
if (opt->deq_tmo_nsec < info.min_dequeue_timeout_ns) {
opt->deq_tmo_nsec = info.min_dequeue_timeout_ns;
@@ -198,16 +224,15 @@ evt_configure_eventdev(struct evt_options *opt, uint8_t
nb_queues,
}
const struct rte_event_dev_config config = {
- .dequeue_timeout_ns = opt->deq_tmo_nsec,
- .nb_event_queues = nb_queues,
- .nb_event_ports = nb_ports,
- .nb_single_link_event_port_queues = 0,
- .nb_events_limit = info.max_num_events,
- .nb_event_queue_flows = opt->nb_flows,
- .nb_event_port_dequeue_depth =
- info.max_event_port_dequeue_depth,
- .nb_event_port_enqueue_depth =
- info.max_event_port_enqueue_depth,
+ .dequeue_timeout_ns = opt->deq_tmo_nsec,
+ .nb_event_queues = nb_queues,
+ .nb_event_ports = nb_ports,
+ .nb_single_link_event_port_queues = 0,
+ .nb_events_limit = info.max_num_events,
+ .nb_event_queue_flows = opt->nb_flows,
+ .nb_event_port_dequeue_depth =
info.max_event_port_dequeue_depth,
+ .nb_event_port_enqueue_depth =
info.max_event_port_enqueue_depth,
+ .preschedule_type = opt->preschedule,
};
return rte_event_dev_configure(opt->dev_id, &config);
diff --git a/app/test-eventdev/evt_options.c b/app/test-eventdev/evt_options.c
index fb5a0a255f..323d1e724d 100644
--- a/app/test-eventdev/evt_options.c
+++ b/app/test-eventdev/evt_options.c
@@ -130,6 +130,17 @@ evt_parse_tx_pkt_sz(struct evt_options *opt, const char
*arg __rte_unused)
return ret;
}
+static int
+evt_parse_preschedule(struct evt_options *opt, const char *arg __rte_unused)
+{
+ int ret;
+
+ ret = parser_read_uint8(&(opt->preschedule), arg);
+ opt->preschedule_opted = 1;
+
+ return ret;
+}
+
static int
evt_parse_timer_prod_type(struct evt_options *opt, const char *arg
__rte_unused)
{
@@ -510,6 +521,10 @@ usage(char *program)
" across all the ethernet devices
before\n"
" event workers start.\n"
"\t--tx_pkt_sz: Packet size to use with Tx first."
+ "\t--preschedule : Pre-schedule type to use.\n"
+ " 0 - disable pre-schedule\n"
+ " 1 - pre-schedule\n"
+ " 2 - pre-schedule adaptive (Default)\n"
[PATCH v9 6/6] examples: use eventdev pre-scheduling
From: Pavan Nikhilesh
Enable event pre-scheduling if supported by the event device.
Signed-off-by: Pavan Nikhilesh
---
examples/eventdev_pipeline/pipeline_worker_generic.c | 6 ++
examples/eventdev_pipeline/pipeline_worker_tx.c | 6 ++
examples/ipsec-secgw/event_helper.c | 6 ++
examples/l2fwd-event/l2fwd_event_generic.c | 6 ++
examples/l2fwd-event/l2fwd_event_internal_port.c | 6 ++
examples/l3fwd/l3fwd_event_generic.c | 6 ++
examples/l3fwd/l3fwd_event_internal_port.c | 6 ++
7 files changed, 42 insertions(+)
diff --git a/examples/eventdev_pipeline/pipeline_worker_generic.c
b/examples/eventdev_pipeline/pipeline_worker_generic.c
index 831d7fd53d..06384c683c 100644
--- a/examples/eventdev_pipeline/pipeline_worker_generic.c
+++ b/examples/eventdev_pipeline/pipeline_worker_generic.c
@@ -192,6 +192,12 @@ setup_eventdev_generic(struct worker_data *worker_data)
config.nb_event_port_enqueue_depth =
dev_info.max_event_port_enqueue_depth;
+ if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE)
+ config.preschedule_type = RTE_EVENT_PRESCHEDULE;
+
+ if (dev_info.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE)
+ config.preschedule_type = RTE_EVENT_PRESCHEDULE_ADAPTIVE;
+
ret = rte_event_dev_configure(dev_id, &config);
if (ret < 0) {
printf("%d: Error configuring device\n", __LINE__);
diff --git a/examples/eventdev_pipeline/pipeline_worker_tx.c
b/examples/eventdev_pipeline/pipeline_worker_tx.c
index 98a52f3892..c9a04cad56 100644
--- a/examples/eventdev_pipeline/pipeline_worker_tx.c
+++ b/examples/eventdev_pipeline/pipeline_worker_tx.c
@@ -505,6 +505,12 @@ setup_eventdev_worker_tx_enq(struct worker_data
*worker_data)
config.nb_event_port_enqueue_depth =
dev_info.max_event_port_enqueue_depth;
+ if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE)
+ config.preschedule_type = RTE_EVENT_PRESCHEDULE;
+
+ if (dev_info.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE)
+ config.preschedule_type = RTE_EVENT_PRESCHEDULE_ADAPTIVE;
+
ret = rte_event_dev_configure(dev_id, &config);
if (ret < 0) {
printf("%d: Error configuring device\n", __LINE__);
diff --git a/examples/ipsec-secgw/event_helper.c
b/examples/ipsec-secgw/event_helper.c
index 89fb7e62a5..dadddcb306 100644
--- a/examples/ipsec-secgw/event_helper.c
+++ b/examples/ipsec-secgw/event_helper.c
@@ -669,6 +669,12 @@ eh_initialize_eventdev(struct eventmode_conf *em_conf)
eventdev_conf.nb_event_port_enqueue_depth =
evdev_default_conf.max_event_port_enqueue_depth;
+ if (evdev_default_conf.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE)
+ eventdev_conf.preschedule_type = RTE_EVENT_PRESCHEDULE;
+
+ if (evdev_default_conf.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE)
+ eventdev_conf.preschedule_type =
RTE_EVENT_PRESCHEDULE_ADAPTIVE;
+
/* Configure event device */
ret = rte_event_dev_configure(eventdev_id, &eventdev_conf);
if (ret < 0) {
diff --git a/examples/l2fwd-event/l2fwd_event_generic.c
b/examples/l2fwd-event/l2fwd_event_generic.c
index 1977e23261..d805264744 100644
--- a/examples/l2fwd-event/l2fwd_event_generic.c
+++ b/examples/l2fwd-event/l2fwd_event_generic.c
@@ -86,6 +86,12 @@ l2fwd_event_device_setup_generic(struct l2fwd_resources
*rsrc)
evt_rsrc->has_burst = !!(dev_info.event_dev_cap &
RTE_EVENT_DEV_CAP_BURST_MODE);
+ if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE)
+ event_d_conf.preschedule_type = RTE_EVENT_PRESCHEDULE;
+
+ if (dev_info.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE)
+ event_d_conf.preschedule_type = RTE_EVENT_PRESCHEDULE_ADAPTIVE;
+
ret = rte_event_dev_configure(event_d_id, &event_d_conf);
if (ret < 0)
rte_panic("Error in configuring event device\n");
diff --git a/examples/l2fwd-event/l2fwd_event_internal_port.c
b/examples/l2fwd-event/l2fwd_event_internal_port.c
index 717a7bceb8..26233d1ab6 100644
--- a/examples/l2fwd-event/l2fwd_event_internal_port.c
+++ b/examples/l2fwd-event/l2fwd_event_internal_port.c
@@ -82,6 +82,12 @@ l2fwd_event_device_setup_internal_port(struct
l2fwd_resources *rsrc)
evt_rsrc->has_burst = !!(dev_info.event_dev_cap &
RTE_EVENT_DEV_CAP_BURST_MODE);
+ if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE)
+ event_d_conf.preschedule_type = RTE_EVENT_PRESCHEDULE;
+
+ if (dev_info.event_dev_cap &
RTE_EVENT_DEV_CAP_EVENT
RE: [PATCH v6 2/6] crypto/openssl: support EDDSA
Hi Gowrishankar,
> -Original Message-
> From: Gowrishankar Muthukrishnan
> Sent: Friday, October 4, 2024 10:26 AM
> To: dev@dpdk.org; Ji, Kai
> Cc: Anoob Joseph ; Richardson, Bruce
> ; jer...@marvell.com; fanzhang@gmail.com;
> Kusztal, ArkadiuszX ; jack.bond-
> pres...@foss.arm.com; Marchand, David ;
> hemant.agra...@nxp.com; De Lara Guarch, Pablo
> ; Trahe, Fiona ;
> Doherty, Declan ; ma...@nvidia.com;
> ruifeng.w...@arm.com; Akhil Goyal ; Gowrishankar
> Muthukrishnan
> Subject: [PATCH v6 2/6] crypto/openssl: support EDDSA
>
> Support EDDSA crypto algorithm in OpenSSL PMD.
>
> Signed-off-by: Gowrishankar Muthukrishnan
> ---
> doc/guides/cryptodevs/features/openssl.ini | 1 +
> drivers/crypto/openssl/openssl_pmd_private.h | 13 ++
> drivers/crypto/openssl/rte_openssl_pmd.c | 223 +++
> drivers/crypto/openssl/rte_openssl_pmd_ops.c | 131 +++
> 4 files changed, 368 insertions(+)
>
> diff --git a/doc/guides/cryptodevs/features/openssl.ini
> b/doc/guides/cryptodevs/features/openssl.ini
> index b64c8ec4a5..0540c075dc 100644
> --- a/doc/guides/cryptodevs/features/openssl.ini
> +++ b/doc/guides/cryptodevs/features/openssl.ini
> @@ -66,6 +66,7 @@ Modular Exponentiation = Y Modular Inversion = Y Diffie-
> hellman = Y
> SM2 = Y
> +EDDSA = Y
>
> ;
> ; Supported Operating systems of the 'openssl' crypto driver.
> diff --git a/drivers/crypto/openssl/openssl_pmd_private.h
> b/drivers/crypto/openssl/openssl_pmd_private.h
> index 0282b3d829..7dd97f1c72 100644
> --- a/drivers/crypto/openssl/openssl_pmd_private.h
> +++ b/drivers/crypto/openssl/openssl_pmd_private.h
> @@ -231,10 +231,23 @@ struct __rte_cache_aligned openssl_asym_session {
> #endif
> } s;
> struct {
> + uint8_t curve_id;
> +#if (OPENSSL_VERSION_NUMBER >= 0x3000L)
> + EC_GROUP * group;
> + BIGNUM *priv_key;
> +#endif
> + } ec;
> + struct {
> #if (OPENSSL_VERSION_NUMBER >= 0x3000L)
> OSSL_PARAM * params;
> #endif
> } sm2;
> + struct {
> + uint8_t curve_id;
> +#if (OPENSSL_VERSION_NUMBER >= 0x3000L)
> + OSSL_PARAM * params;
> +#endif
> + } eddsa;
> } u;
> };
> /** Set and validate OPENSSL crypto session parameters */ diff --git
> a/drivers/crypto/openssl/rte_openssl_pmd.c
> b/drivers/crypto/openssl/rte_openssl_pmd.c
> index e10a172f46..4e4d06403b 100644
> --- a/drivers/crypto/openssl/rte_openssl_pmd.c
> +++ b/drivers/crypto/openssl/rte_openssl_pmd.c
> @@ -2849,6 +2849,45 @@ process_openssl_rsa_op_evp(struct rte_crypto_op
> *cop,
>
> }
>
> +static int
> +process_openssl_ecfpm_op_evp(struct rte_crypto_op *cop,
> + struct openssl_asym_session *sess)
> +{
> + const EC_GROUP *ecgrp = sess->u.ec.group;
> + EC_POINT *ecpt = NULL;
> + BN_CTX *ctx = NULL;
> + BIGNUM *n = NULL;
> + int ret = -1;
> +
> + n = BN_bin2bn((const unsigned char *)
> + cop->asym->ecpm.scalar.data,
> + cop->asym->ecpm.scalar.length,
> + BN_new());
> +
> + ctx = BN_CTX_new();
> + if (!ctx)
> + goto err_ecfpm;
> +
> + if (!EC_POINT_mul(ecgrp, ecpt, n, NULL, NULL, ctx))
> + goto err_ecfpm;
> +
> + if (cop->asym->flags &
> RTE_CRYPTO_ASYM_FLAG_PUB_KEY_COMPRESSED) {
> + unsigned char *buf = cop->asym->ecpm.r.x.data;
> + size_t sz;
> +
> + sz = EC_POINT_point2oct(ecgrp, ecpt,
> POINT_CONVERSION_COMPRESSED, buf, 0, ctx);
> + if (!sz)
> + goto err_ecfpm;
> +
> + cop->asym->ecpm.r.x.length = sz;
> + }
> +
> +err_ecfpm:
> + BN_CTX_free(ctx);
> + BN_free(n);
> + return ret;
> +}
> +
> static int
> process_openssl_sm2_op_evp(struct rte_crypto_op *cop,
> struct openssl_asym_session *sess)
> @@ -3074,6 +3113,158 @@ process_openssl_sm2_op_evp(struct
> rte_crypto_op *cop,
> return ret;
> }
>
> +static int
> +process_openssl_eddsa_op_evp(struct rte_crypto_op *cop,
> + struct openssl_asym_session *sess)
> +{
> + static const char * const instance[] = {"Ed25519", "Ed25519ctx",
> "Ed25519ph",
> + "Ed448", "Ed448ph"};
> + EVP_PKEY_CTX *kctx = NULL, *sctx = NULL, *cctx = NULL;
> + const uint8_t curve_id = sess->u.eddsa.curve_id;
> + struct rte_crypto_asym_op *op = cop->asym;
> + OSSL_PARAM *params = sess->u.eddsa.params;
> + OSSL_PARAM_BLD *iparam_bld = NULL;
> + OSSL_PARAM *iparams = NULL;
> + uint8_t signbuf[128] = {0};
> + EVP_MD_CTX *md_ctx = NULL;
> + EVP_PKEY *pkey = NULL;
> + size_t signlen;
> + int ret = -1;
> +
> + cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
> +
> + iparam_bld = OSSL_PARAM_BLD_new();
> + if (!iparam_bld)
> + goto err_eddsa;
> +
RE: [PATCH] eal/x86: cache queried CPU flags
> Rather than re-querying the HW each time a CPU flag is requested, we can just > save the return value in the flags array. This should speed up repeated > querying of CPU flags, and provides a workaround for a reported issue where > errors are seen with constant querying of the AVX-512 CPU flag from a non- > AVX VM. > > Bugzilla Id: 1501 > > Signed-off-by: Bruce Richardson > --- Hi Bruce, Why x86/rte_cpuflags.c is not using rte_getauxval() ?
[PATCH 4/5] net/virtio: implement update link state API
From: Satha Rao
This patch introduces the vhost_vdpa_update_link_state API to manage the
link state updates.
Signed-off-by: Satha Rao
---
drivers/net/virtio/virtio_user/vhost_vdpa.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/virtio/virtio_user/vhost_vdpa.c
b/drivers/net/virtio/virtio_user/vhost_vdpa.c
index 5c610664b6..e8aea54000 100644
--- a/drivers/net/virtio/virtio_user/vhost_vdpa.c
+++ b/drivers/net/virtio/virtio_user/vhost_vdpa.c
@@ -619,9 +619,17 @@ vhost_vdpa_get_backend_features(uint64_t *features)
}
static int
-vhost_vdpa_update_link_state(struct virtio_user_dev *dev __rte_unused)
+vhost_vdpa_update_link_state(struct virtio_user_dev *dev)
{
- /* Nothing to update (for now?) */
+ uint16_t status;
+ int rc, offset;
+
+ offset = offsetof(struct virtio_net_config, status);
+ rc = vhost_vdpa_get_config(dev, (uint8_t *)&status, offset,
sizeof(status));
+ if (rc)
+ return rc;
+ dev->net_status = status & VIRTIO_NET_S_LINK_UP;
+
return 0;
}
--
2.25.1
[PATCH 5/5] net/virtio-user: support vDPA configuration callback
From: Satha Rao
Extended the vhost_vdpa_get_intr_fd API to create an event and
register for configuration callbacks with the vDPA backend. This
enhancement allows the virtio-user driver to handle configuration
changes more effectively.
Signed-off-by: Satha Rao
---
drivers/net/virtio/virtio_user/vhost_vdpa.c | 18 ++--
.../net/virtio/virtio_user/virtio_user_dev.c | 29 +++
.../net/virtio/virtio_user/virtio_user_dev.h | 2 ++
3 files changed, 46 insertions(+), 3 deletions(-)
diff --git a/drivers/net/virtio/virtio_user/vhost_vdpa.c
b/drivers/net/virtio/virtio_user/vhost_vdpa.c
index e8aea54000..c9eaffce16 100644
--- a/drivers/net/virtio/virtio_user/vhost_vdpa.c
+++ b/drivers/net/virtio/virtio_user/vhost_vdpa.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
@@ -634,10 +635,21 @@ vhost_vdpa_update_link_state(struct virtio_user_dev *dev)
}
static int
-vhost_vdpa_get_intr_fd(struct virtio_user_dev *dev __rte_unused)
+vhost_vdpa_get_intr_fd(struct virtio_user_dev *dev)
{
- /* No link state interrupt with Vhost-vDPA */
- return -1;
+ int fd;
+
+ if (dev->cfg_epfd)
+ return dev->cfg_epfd;
+
+ fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
+ if (fd < 0) {
+ PMD_DRV_LOG(ERR, "failed to create fd error, %s",
strerror(errno));
+ fd = -1;
+ }
+ dev->cfg_epfd = fd;
+
+ return fd;
}
static int
diff --git a/drivers/net/virtio/virtio_user/virtio_user_dev.c
b/drivers/net/virtio/virtio_user/virtio_user_dev.c
index 91ad1312f7..ea00eb50f5 100644
--- a/drivers/net/virtio/virtio_user/virtio_user_dev.c
+++ b/drivers/net/virtio/virtio_user/virtio_user_dev.c
@@ -487,6 +487,21 @@ virtio_user_dev_get_speed_duplex_config(struct
virtio_user_dev *dev, void *dst,
return ret;
}
+int
+virtio_user_dev_set_config_call(struct virtio_user_dev *dev, int fd)
+{
+ int ret = 0;
+
+ if (!dev->ops->set_config_call)
+ return -ENOTSUP;
+
+ ret = dev->ops->set_config_call(dev, fd);
+ if (ret)
+ PMD_DRV_LOG(ERR, "(%s) Failed to set config call in device",
dev->path);
+
+ return ret;
+}
+
static int
virtio_user_dev_init_notify(struct virtio_user_dev *dev)
{
@@ -769,6 +784,7 @@ virtio_user_dev_init(struct virtio_user_dev *dev, char
*path, uint16_t queues,
dev->unsupported_features = 0;
dev->backend_type = backend_type;
dev->ifname = *ifname;
+ dev->cfg_epfd = 0;
if (virtio_user_dev_setup(dev) < 0) {
PMD_INIT_LOG(ERR, "(%s) backend set up fails", dev->path);
@@ -863,6 +879,15 @@ virtio_user_dev_init(struct virtio_user_dev *dev, char
*path, uint16_t queues,
}
}
+ /* vhost vdpa register valid fd to handle config callback */
+ if (dev->cfg_epfd) {
+ struct rte_eth_dev *eth_dev = &rte_eth_devices[dev->hw.port_id];
+
+ if (rte_intr_efd_counter_size_set(eth_dev->intr_handle, 8))
+ return -rte_errno;
+ virtio_user_dev_set_config_call(dev, dev->cfg_epfd);
+ }
+
*ifname = NULL;
return 0;
@@ -892,6 +917,10 @@ virtio_user_dev_uninit(struct virtio_user_dev *dev)
virtio_user_free_vrings(dev);
+ if (dev->cfg_epfd) {
+ close(dev->cfg_epfd);
+ dev->cfg_epfd = 0;
+ }
free(dev->ifname);
if (dev->is_server)
diff --git a/drivers/net/virtio/virtio_user/virtio_user_dev.h
b/drivers/net/virtio/virtio_user/virtio_user_dev.h
index 57d75d1c53..1ad93521e3 100644
--- a/drivers/net/virtio/virtio_user/virtio_user_dev.h
+++ b/drivers/net/virtio/virtio_user/virtio_user_dev.h
@@ -31,6 +31,7 @@ struct virtio_user_dev {
int *callfds;
int *kickfds;
+ int cfg_epfd; /* config callback interrupt */
int mac_specified;
uint16_tmax_queue_pairs;
uint16_tqueue_pairs;
@@ -89,6 +90,7 @@ int virtio_user_dev_get_rss_config(struct virtio_user_dev
*dev, void *dst, size_
int length);
int virtio_user_dev_get_speed_duplex_config(struct virtio_user_dev *dev, void
*dst,
size_t offset, int length);
+int virtio_user_dev_set_config_call(struct virtio_user_dev *dev, int fd);
void virtio_user_dev_delayed_disconnect_handler(void *param);
int virtio_user_dev_server_reconnect(struct virtio_user_dev *dev);
extern const char * const virtio_user_backend_strings[];
--
2.25.1
[PATCH 2/5] net/virtio-user: get link duplex and speed
From: Satha Rao
This patch extends the virtio_user_read_dev_config API to retrieve link
speed and duplex settings if the device features support
VIRTIO_NET_F_SPEED_DUPLEX.
Signed-off-by: Satha Rao
---
.../net/virtio/virtio_user/virtio_user_dev.c | 22 ++-
.../net/virtio/virtio_user/virtio_user_dev.h | 2 ++
drivers/net/virtio/virtio_user_ethdev.c | 6 +
3 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/net/virtio/virtio_user/virtio_user_dev.c
b/drivers/net/virtio/virtio_user/virtio_user_dev.c
index 2997d2bd26..91ad1312f7 100644
--- a/drivers/net/virtio/virtio_user/virtio_user_dev.c
+++ b/drivers/net/virtio/virtio_user/virtio_user_dev.c
@@ -468,6 +468,25 @@ virtio_user_dev_init_mac(struct virtio_user_dev *dev,
const char *mac)
PMD_DRV_LOG(INFO, "(%s) MAC %s specified", dev->path, buf);
}
+int
+virtio_user_dev_get_speed_duplex_config(struct virtio_user_dev *dev, void
*dst, size_t offset,
+ int length)
+{
+ int ret = 0;
+
+ if (!(dev->device_features & (1ULL << VIRTIO_NET_F_SPEED_DUPLEX)))
+ return -ENOTSUP;
+
+ if (!dev->ops->get_config)
+ return -ENOTSUP;
+
+ ret = dev->ops->get_config(dev, dst, offset, length);
+ if (ret)
+ PMD_DRV_LOG(ERR, "(%s) Failed to get speed/duplex config in
device", dev->path);
+
+ return ret;
+}
+
static int
virtio_user_dev_init_notify(struct virtio_user_dev *dev)
{
@@ -726,7 +745,8 @@ virtio_user_free_vrings(struct virtio_user_dev *dev)
1ULL << VIRTIO_F_RING_PACKED | \
1ULL << VIRTIO_F_NOTIFICATION_DATA | \
1ULL << VIRTIO_F_ORDER_PLATFORM| \
-1ULL << VIRTIO_NET_F_RSS)
+1ULL << VIRTIO_NET_F_RSS | \
+1ULL << VIRTIO_NET_F_SPEED_DUPLEX)
int
virtio_user_dev_init(struct virtio_user_dev *dev, char *path, uint16_t queues,
diff --git a/drivers/net/virtio/virtio_user/virtio_user_dev.h
b/drivers/net/virtio/virtio_user/virtio_user_dev.h
index 66400b3b62..57d75d1c53 100644
--- a/drivers/net/virtio/virtio_user/virtio_user_dev.h
+++ b/drivers/net/virtio/virtio_user/virtio_user_dev.h
@@ -87,6 +87,8 @@ int virtio_user_dev_set_mac(struct virtio_user_dev *dev);
int virtio_user_dev_get_mac(struct virtio_user_dev *dev);
int virtio_user_dev_get_rss_config(struct virtio_user_dev *dev, void *dst,
size_t offset,
int length);
+int virtio_user_dev_get_speed_duplex_config(struct virtio_user_dev *dev, void
*dst,
+ size_t offset, int length);
void virtio_user_dev_delayed_disconnect_handler(void *param);
int virtio_user_dev_server_reconnect(struct virtio_user_dev *dev);
extern const char * const virtio_user_backend_strings[];
diff --git a/drivers/net/virtio/virtio_user_ethdev.c
b/drivers/net/virtio/virtio_user_ethdev.c
index bf29f0dacd..d431b4521b 100644
--- a/drivers/net/virtio/virtio_user_ethdev.c
+++ b/drivers/net/virtio/virtio_user_ethdev.c
@@ -55,6 +55,12 @@ virtio_user_read_dev_config(struct virtio_hw *hw, size_t
offset,
if (offset >= offsetof(struct virtio_net_config, rss_max_key_size))
virtio_user_dev_get_rss_config(dev, dst, offset, length);
+
+ if (offset == offsetof(struct virtio_net_config, speed))
+ virtio_user_dev_get_speed_duplex_config(dev, dst, offset,
length);
+
+ if (offset == offsetof(struct virtio_net_config, duplex))
+ virtio_user_dev_get_speed_duplex_config(dev, dst, offset,
length);
}
static void
--
2.25.1
[PATCH 3/5] net/virtio: add set config callback
From: Satha Rao
This patch enables the set config callback handler.
Signed-off-by: Satha Rao
---
drivers/net/virtio/virtio_user/vhost.h | 1 +
drivers/net/virtio/virtio_user/vhost_vdpa.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/net/virtio/virtio_user/vhost.h
b/drivers/net/virtio/virtio_user/vhost.h
index eee3a4bc47..45ae56e3b5 100644
--- a/drivers/net/virtio/virtio_user/vhost.h
+++ b/drivers/net/virtio/virtio_user/vhost.h
@@ -92,6 +92,7 @@ struct virtio_user_backend_ops {
int (*get_intr_fd)(struct virtio_user_dev *dev);
int (*map_notification_area)(struct virtio_user_dev *dev);
int (*unmap_notification_area)(struct virtio_user_dev *dev);
+ int (*set_config_call)(struct virtio_user_dev *dev, int fd);
};
extern struct virtio_user_backend_ops virtio_ops_user;
diff --git a/drivers/net/virtio/virtio_user/vhost_vdpa.c
b/drivers/net/virtio/virtio_user/vhost_vdpa.c
index bc3e2a9af5..5c610664b6 100644
--- a/drivers/net/virtio/virtio_user/vhost_vdpa.c
+++ b/drivers/net/virtio/virtio_user/vhost_vdpa.c
@@ -48,6 +48,7 @@ struct vhost_vdpa_data {
#define VHOST_VDPA_SET_VRING_ENABLE _IOW(VHOST_VIRTIO, 0x75, struct
vhost_vring_state)
#define VHOST_SET_BACKEND_FEATURES _IOW(VHOST_VIRTIO, 0x25, __u64)
#define VHOST_GET_BACKEND_FEATURES _IOR(VHOST_VIRTIO, 0x26, __u64)
+#define VHOST_SET_CONFIG_CALL _IOW(VHOST_VIRTIO, 0x77, int)
/* no alignment requirement */
struct vhost_iotlb_msg {
@@ -509,6 +510,14 @@ vhost_vdpa_set_config(struct virtio_user_dev *dev, const
uint8_t *data, uint32_t
return ret;
}
+static int
+vhost_vdpa_set_config_call(struct virtio_user_dev *dev, int fd)
+{
+ struct vhost_vdpa_data *data = dev->backend_data;
+
+ return vhost_vdpa_ioctl(data->vhostfd, VHOST_SET_CONFIG_CALL, &fd);
+}
+
/**
* Set up environment to talk with a vhost vdpa backend.
*
@@ -706,6 +715,7 @@ struct virtio_user_backend_ops virtio_ops_vdpa = {
.set_status = vhost_vdpa_set_status,
.get_config = vhost_vdpa_get_config,
.set_config = vhost_vdpa_set_config,
+ .set_config_call = vhost_vdpa_set_config_call,
.cvq_enable = vhost_vdpa_cvq_enable,
.enable_qp = vhost_vdpa_enable_queue_pair,
.dma_map = vhost_vdpa_dma_map_batch,
--
2.25.1
[PATCH 1/5] interrupts: fix number of bytes read for vdev
From: Satha Rao
Correct the number of bytes to read during vdev interrupt processing.
The driver sets this value, and the rxtx interrupt handling already
performs this correctly.
Fixes: 8feec90 ("eal/linux: add interrupt type for vdev")
Cc: sta...@dpdk.org
Signed-off-by: Satha Rao
---
lib/eal/linux/eal_interrupts.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/eal/linux/eal_interrupts.c b/lib/eal/linux/eal_interrupts.c
index 6436f796eb..80eef7ec4b 100644
--- a/lib/eal/linux/eal_interrupts.c
+++ b/lib/eal/linux/eal_interrupts.c
@@ -949,6 +949,10 @@ eal_intr_process_interrupts(struct epoll_event *events,
int nfds)
break;
#endif
case RTE_INTR_HANDLE_VDEV:
+ /* For vdev, number of bytes to read is set by driver */
+ bytes_read =
rte_intr_efd_counter_size_get(src->intr_handle);
+ call = true;
+ break;
case RTE_INTR_HANDLE_EXT:
bytes_read = 0;
call = true;
--
2.25.1
Re: [PATCH v2 0/3] make struct parameters constant in rte_tm APIs
On Mon, 7 Oct 2024 12:49:04 +0100 Bruce Richardson wrote: > For functions for creating profiles, shapers and hierarchy nodes, make > the parameter structure pointer a pointer to a const object. This > guarantees to the user that the struct won't be modified by the > function, which allows the user to re-use the same parameters multiple > times without having to constantly reinitialize it. > > V2: drop final patch with new node query function, simplifying patchset > > Bruce Richardson (3): > ethdev: make parameters to TM node add fn constant > ethdev: make parameters to TM profile add fn constant > ethdev: make TM shaper parameters constant > > drivers/net/cnxk/cnxk_tm.c | 4 ++-- > drivers/net/dpaa2/dpaa2_tm.c| 6 +++--- > drivers/net/hns3/hns3_tm.c | 22 +++--- > drivers/net/i40e/i40e_tm.c | 12 ++-- > drivers/net/iavf/iavf_tm.c | 12 ++-- > drivers/net/ice/ice_dcf_sched.c | 12 ++-- > drivers/net/ice/ice_tm.c| 12 ++-- > drivers/net/ipn3ke/ipn3ke_tm.c | 12 ++-- > drivers/net/ixgbe/ixgbe_tm.c| 12 ++-- > drivers/net/mvpp2/mrvl_tm.c | 2 +- > drivers/net/txgbe/txgbe_tm.c| 12 ++-- > lib/ethdev/rte_tm.c | 6 +++--- > lib/ethdev/rte_tm.h | 6 +++--- > lib/ethdev/rte_tm_driver.h | 6 +++--- > 14 files changed, 68 insertions(+), 68 deletions(-) > > -- > 2.43.0 > Series-Acked-by: Stephen Hemminger
Re: [PATCH] net/mlx5: support no host PF configuration
On Wed, 11 Oct 2023 09:41:53 +0300 Jiawei Wang wrote: > From: Xueming Li > > In BlueField, a new firmware configuration option NUM_OF_PF=0 disables > PF on the x86 host side, no HPF on the ARM side, and the only RDMA port > on the ARM side is the bonding device(PF0). A device probe with devargs > of representor=pf[0-1]vf[...] will probe PF0 and PF1 one by one, and > it's possible that PF1 device scan results in no switch ports. > > This patch supports the new configuration by allowing a PF scan with > empty switch ports. > > Signed-off-by: Xueming Li > Signed-off-by: Jiawei Wang Not sure why it never got merged but looks fine. Acked-by: Stephen Hemminger
Re: [PATCH v2 0/4] power: refactor power management library
On Mon, 26 Aug 2024 13:06:45 + Sivaprasad Tummala wrote: > This patchset refactors the power management library, addressing both > core and uncore power management. The primary changes involve the > creation of dedicated directories for each driver within > 'drivers/power/core/*' and 'drivers/power/uncore/*'. > > This refactor significantly improves code organization, enhances > clarity, and boosts maintainability. It lays the foundation for more > focused development on individual drivers and facilitates seamless integration > of future enhancements, particularly the AMD uncore driver. > > Furthermore, this effort aims to streamline code maintenance by > consolidating common functions for cpufreq and cppc across various > core drivers, thus reducing code duplication. > > Sivaprasad Tummala (4): > power: refactor core power management library > power: refactor uncore power management library > test/power: removed function pointer validations > power/amd_uncore: uncore power management support for AMD EPYC > processors Build fails and lots of comments. Please redo.
Re: [PATCH v6] app/testpmd: enable cli for programmable action
On Thu, 18 Apr 2024 16:39:14 +0100 Ferruh Yigit wrote: > On 2/8/2024 1:10 AM, Ferruh Yigit wrote: > > On 10/11/2023 1:03 PM, Qi Zhang wrote: > >> Parsing command line for rte_flow_action_prog. > >> > >> Syntax: > >> > >> "prog name [arguments \ > >>... end]" > >> > >> Use parse_string0 to parse name string. > >> Use parse_hex to parse hex string. > >> Use struct action_prog_data to store parsed result. > >> > >> Example: > >> > >> Action with 2 arguments: > >> > >> "prog name action0 arguments field0 03FF field1 55AA end" > >> > >> Action without argument: > >> "prog name action1" > >> > >> Signed-off-by: Qi Zhang > >> > >> > > > > Hi Ori, Cristian, can you please help reviewing this patch? > > > > Is this patch still/active valid? This patch no longer applies, merge conflicts please rebase/retest and resubmit.
Re: [PATCH] doc: remove confusing command to send patch
On Tue, 10 Oct 2023 18:26:35 +0200 Thomas Monjalon wrote: > In the contributor guide, it was said that no need to Cc maintainers > for new additions, probably for new directories not having a maintainer. > There is no harm, and it is a good habit, to always Cc maintainers. > > Remove this case as it can mislead to not Cc maintainers when needed. > > Signed-off-by: Thomas Monjalon > --- > doc/guides/contributing/patches.rst | 4 > 1 file changed, 4 deletions(-) > > diff --git a/doc/guides/contributing/patches.rst > b/doc/guides/contributing/patches.rst > index e286d9e6d5..d114ceba2b 100644 > --- a/doc/guides/contributing/patches.rst > +++ b/doc/guides/contributing/patches.rst > @@ -561,10 +561,6 @@ Script ``get-maintainer.sh`` can be used to select > maintainers automatically:: > >git send-email --to-cmd ./devtools/get-maintainer.sh --cc dev@dpdk.org > 000*.patch > > -New additions can be sent without a maintainer:: > - > - git send-email --to dev@dpdk.org 000*.patch > - > You can test the emails by sending it to yourself or with the ``--dry-run`` > option. > > If the patch is in relation to a previous email thread you can add it to the > same thread using the Message ID:: Acked-by: Stephen Hemminger
[PATCH v2 29/50] net/ntnic: add key match (KM) FPGA module
From: Oleksandr Kolomeiets
The Key Matcher module checks the values of individual fields of a packet.
It supports both exact match which is implemented with a CAM,
and wildcards which is implemented with a TCAM.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 85 ++
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c| 3 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 +
.../ntnic/nthw/flow_api/hw_mod/hw_mod_km.c| 278 ++
.../supported/nthw_fpga_9563_055_049_.c | 94 +-
6 files changed, 461 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_km.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 20b10faf5e..f40b33a888 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -32,6 +32,7 @@ void *callocate_mod(struct common_func_s *mod, int sets, ...);
void zero_module_cache(struct common_func_s *mod);
#define ALL_ENTRIES -1000
+#define ALL_BANK_ENTRIES -1001
#define INDEX_TOO_LARGE (NT_LOG(INF, FILTER, "ERROR:%s: Index too large\n",
__func__), -2)
@@ -267,6 +268,89 @@ struct km_func_s {
struct hw_mod_km_v7_s v7;
};
};
+enum hw_km_e {
+ /* functions */
+ HW_KM_RCP_PRESET_ALL = 0,
+ HW_KM_CAM_PRESET_ALL,
+ /* to sync and reset hw with cache - force write all entries in a bank
*/
+ HW_KM_TCAM_BANK_RESET,
+ /* fields */
+ HW_KM_RCP_QW0_DYN = FIELD_START_INDEX,
+ HW_KM_RCP_QW0_OFS,
+ HW_KM_RCP_QW0_SEL_A,
+ HW_KM_RCP_QW0_SEL_B,
+ HW_KM_RCP_QW4_DYN,
+ HW_KM_RCP_QW4_OFS,
+ HW_KM_RCP_QW4_SEL_A,
+ HW_KM_RCP_QW4_SEL_B,
+ HW_KM_RCP_DW8_DYN,
+ HW_KM_RCP_DW8_OFS,
+ HW_KM_RCP_DW8_SEL_A,
+ HW_KM_RCP_DW8_SEL_B,
+ HW_KM_RCP_DW10_DYN,
+ HW_KM_RCP_DW10_OFS,
+ HW_KM_RCP_DW10_SEL_A,
+ HW_KM_RCP_DW10_SEL_B,
+ HW_KM_RCP_SWX_CCH,
+ HW_KM_RCP_SWX_SEL_A,
+ HW_KM_RCP_SWX_SEL_B,
+ HW_KM_RCP_MASK_A,
+ HW_KM_RCP_MASK_B,
+ HW_KM_RCP_DUAL,
+ HW_KM_RCP_PAIRED,
+ HW_KM_RCP_EL_A,
+ HW_KM_RCP_EL_B,
+ HW_KM_RCP_INFO_A,
+ HW_KM_RCP_INFO_B,
+ HW_KM_RCP_FTM_A,
+ HW_KM_RCP_FTM_B,
+ HW_KM_RCP_BANK_A,
+ HW_KM_RCP_BANK_B,
+ HW_KM_RCP_KL_A,
+ HW_KM_RCP_KL_B,
+ HW_KM_RCP_KEYWAY_A,
+ HW_KM_RCP_KEYWAY_B,
+ HW_KM_RCP_SYNERGY_MODE,
+ HW_KM_RCP_DW0_B_DYN,
+ HW_KM_RCP_DW0_B_OFS,
+ HW_KM_RCP_DW2_B_DYN,
+ HW_KM_RCP_DW2_B_OFS,
+ HW_KM_RCP_SW4_B_DYN,
+ HW_KM_RCP_SW4_B_OFS,
+ HW_KM_RCP_SW5_B_DYN,
+ HW_KM_RCP_SW5_B_OFS,
+ HW_KM_CAM_W0,
+ HW_KM_CAM_W1,
+ HW_KM_CAM_W2,
+ HW_KM_CAM_W3,
+ HW_KM_CAM_W4,
+ HW_KM_CAM_W5,
+ HW_KM_CAM_FT0,
+ HW_KM_CAM_FT1,
+ HW_KM_CAM_FT2,
+ HW_KM_CAM_FT3,
+ HW_KM_CAM_FT4,
+ HW_KM_CAM_FT5,
+ HW_KM_TCAM_T,
+ HW_KM_TCI_COLOR,
+ HW_KM_TCI_FT,
+ HW_KM_TCQ_BANK_MASK,
+ HW_KM_TCQ_QUAL
+};
+bool hw_mod_km_present(struct flow_api_backend_s *be);
+int hw_mod_km_alloc(struct flow_api_backend_s *be);
+void hw_mod_km_free(struct flow_api_backend_s *be);
+int hw_mod_km_reset(struct flow_api_backend_s *be);
+int hw_mod_km_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+int hw_mod_km_cam_flush(struct flow_api_backend_s *be, int start_bank, int
start_record,
+ int count);
+int hw_mod_km_tcam_flush(struct flow_api_backend_s *be, int start_bank, int
count);
+int hw_mod_km_tcam_set(struct flow_api_backend_s *be, enum hw_km_e field, int
bank, int byte,
+ int byte_val, uint32_t *value_set);
+int hw_mod_km_tci_flush(struct flow_api_backend_s *be, int start_bank, int
start_record,
+ int count);
+int hw_mod_km_tcq_flush(struct flow_api_backend_s *be, int start_bank, int
start_record,
+ int count);
struct flm_func_s {
COMMON_FUNC_INFO_S;
@@ -483,6 +567,7 @@ struct flow_api_backend_s {
/* flow filter FPGA modules */
struct cat_func_s cat;
+ struct km_func_s km;
/* NIC attributes */
unsigned int num_phy_ports;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 3d394f9bad..e37bb96331 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -50,6 +50,7 @@ sources = files(
'nthw/flow_api/flow_km.c',
'nthw/flow_api/hw_mod/hw_mod_backend.c',
'nthw/flow_api/hw_mod/hw_mod_cat.c',
+'nthw/flow_api/hw_mod/hw_mod_km.c',
'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_csu.c',
'nthw/flow_filter/flow_nthw_flm.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c
b/drivers/net/ntnic/nthw/flow_api/flow_api.c
index 3b1d7c5850..c
[PATCH v2 30/50] net/ntnic: add flow matcher (FLM) FPGA module
From: Oleksandr Kolomeiets
The Flow Matcher module is a high-performance stateful SDRAM lookup
and programming engine which supported exact match lookup
in line-rate of up to hundreds of millions of flows.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 117 +++
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c| 6 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 +
.../ntnic/nthw/flow_api/hw_mod/hw_mod_flm.c | 300 ++
5 files changed, 425 insertions(+)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_flm.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index f40b33a888..3933d4bf53 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -367,6 +367,122 @@ struct flm_func_s {
struct hw_mod_flm_v25_s v25;
};
};
+enum hw_flm_e {
+ /* functions */
+ HW_FLM_CONTROL_PRESET_ALL = 0,
+ HW_FLM_RCP_PRESET_ALL,
+ HW_FLM_FLOW_LRN_DATA,
+ HW_FLM_FLOW_INF_STA_DATA,
+ /* Control fields */
+ HW_FLM_CONTROL_ENABLE = FIELD_START_INDEX,
+ HW_FLM_CONTROL_INIT,
+ HW_FLM_CONTROL_LDS,
+ HW_FLM_CONTROL_LFS,
+ HW_FLM_CONTROL_LIS,
+ HW_FLM_CONTROL_UDS,
+ HW_FLM_CONTROL_UIS,
+ HW_FLM_CONTROL_RDS,
+ HW_FLM_CONTROL_RIS,
+ HW_FLM_CONTROL_PDS,
+ HW_FLM_CONTROL_PIS,
+ HW_FLM_CONTROL_CRCWR,
+ HW_FLM_CONTROL_CRCRD,
+ HW_FLM_CONTROL_RBL,
+ HW_FLM_CONTROL_EAB,
+ HW_FLM_CONTROL_SPLIT_SDRAM_USAGE,
+ HW_FLM_STATUS_CALIB_SUCCESS,
+ HW_FLM_STATUS_CALIB_FAIL,
+ HW_FLM_STATUS_INITDONE,
+ HW_FLM_STATUS_IDLE,
+ HW_FLM_STATUS_CRITICAL,
+ HW_FLM_STATUS_PANIC,
+ HW_FLM_STATUS_CRCERR,
+ HW_FLM_STATUS_EFT_BP,
+ HW_FLM_STATUS_CACHE_BUFFER_CRITICAL,
+ HW_FLM_LOAD_BIN,
+ HW_FLM_LOAD_LPS,
+ HW_FLM_LOAD_APS,
+ HW_FLM_PRIO_LIMIT0,
+ HW_FLM_PRIO_FT0,
+ HW_FLM_PRIO_LIMIT1,
+ HW_FLM_PRIO_FT1,
+ HW_FLM_PRIO_LIMIT2,
+ HW_FLM_PRIO_FT2,
+ HW_FLM_PRIO_LIMIT3,
+ HW_FLM_PRIO_FT3,
+ HW_FLM_PST_PRESET_ALL,
+ HW_FLM_PST_BP,
+ HW_FLM_PST_PP,
+ HW_FLM_PST_TP,
+ HW_FLM_RCP_LOOKUP,
+ HW_FLM_RCP_QW0_DYN,
+ HW_FLM_RCP_QW0_OFS,
+ HW_FLM_RCP_QW0_SEL,
+ HW_FLM_RCP_QW4_DYN,
+ HW_FLM_RCP_QW4_OFS,
+ HW_FLM_RCP_SW8_DYN,
+ HW_FLM_RCP_SW8_OFS,
+ HW_FLM_RCP_SW8_SEL,
+ HW_FLM_RCP_SW9_DYN,
+ HW_FLM_RCP_SW9_OFS,
+ HW_FLM_RCP_MASK,
+ HW_FLM_RCP_KID,
+ HW_FLM_RCP_OPN,
+ HW_FLM_RCP_IPN,
+ HW_FLM_RCP_BYT_DYN,
+ HW_FLM_RCP_BYT_OFS,
+ HW_FLM_RCP_TXPLM,
+ HW_FLM_RCP_AUTO_IPV4_MASK,
+ HW_FLM_BUF_CTRL_LRN_FREE,
+ HW_FLM_BUF_CTRL_INF_AVAIL,
+ HW_FLM_BUF_CTRL_STA_AVAIL,
+ HW_FLM_STAT_LRN_DONE,
+ HW_FLM_STAT_LRN_IGNORE,
+ HW_FLM_STAT_LRN_FAIL,
+ HW_FLM_STAT_UNL_DONE,
+ HW_FLM_STAT_UNL_IGNORE,
+ HW_FLM_STAT_REL_DONE,
+ HW_FLM_STAT_REL_IGNORE,
+ HW_FLM_STAT_PRB_DONE,
+ HW_FLM_STAT_PRB_IGNORE,
+ HW_FLM_STAT_AUL_DONE,
+ HW_FLM_STAT_AUL_IGNORE,
+ HW_FLM_STAT_AUL_FAIL,
+ HW_FLM_STAT_TUL_DONE,
+ HW_FLM_STAT_FLOWS,
+ HW_FLM_STAT_STA_DONE, /* module ver 0.20 */
+ HW_FLM_STAT_INF_DONE, /* module ver 0.20 */
+ HW_FLM_STAT_INF_SKIP, /* module ver 0.20 */
+ HW_FLM_STAT_PCK_HIT,/* module ver 0.20 */
+ HW_FLM_STAT_PCK_MISS, /* module ver 0.20 */
+ HW_FLM_STAT_PCK_UNH,/* module ver 0.20 */
+ HW_FLM_STAT_PCK_DIS,/* module ver 0.20 */
+ HW_FLM_STAT_CSH_HIT,/* module ver 0.20 */
+ HW_FLM_STAT_CSH_MISS, /* module ver 0.20 */
+ HW_FLM_STAT_CSH_UNH,/* module ver 0.20 */
+ HW_FLM_STAT_CUC_START, /* module ver 0.20 */
+ HW_FLM_STAT_CUC_MOVE, /* module ver 0.20 */
+ HW_FLM_SCAN_I, /* module ver 0.22 */
+ HW_FLM_SCRUB_PRESET_ALL,
+ HW_FLM_SCRUB_T, /* module ver 0.22 */
+ HW_FLM_SCRUB_R, /* module ver 0.24 */
+ HW_FLM_SCRUB_DEL, /* module ver 0.24 */
+ HW_FLM_SCRUB_INF, /* module ver 0.24 */
+};
+
+bool hw_mod_flm_present(struct flow_api_backend_s *be);
+int hw_mod_flm_alloc(struct flow_api_backend_s *be);
+void hw_mod_flm_free(struct flow_api_backend_s *be);
+int hw_mod_flm_reset(struct flow_api_backend_s *be);
+
+int hw_mod_flm_control_flush(struct flow_api_backend_s *be);
+int hw_mod_flm_control_set(struct flow_api_backend_s *be, enum hw_flm_e field,
uint32_t value);
+
+int hw_mod_flm_scan_flush(struct flow_api_backend_s *be);
+
+int hw_mod_flm_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_flm_scrub_flush(struct flow_api_backend_s *be, int start_idx, int
count);
struct hsh_func_s {
[PATCH v2 35/50] net/ntnic: add Tx Packet Editor (TPE) FPGA module
From: Oleksandr Kolomeiets
The TX Packet Editor is a software abstraction module,
that keeps track of the handful of FPGA modules
that are used to edit packets in the TX pipeline.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 80 +
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c| 9 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 +
.../ntnic/nthw/flow_api/hw_mod/hw_mod_tpe.c | 277 ++
5 files changed, 368 insertions(+)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_tpe.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 9644639131..cfd5150e59 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -654,6 +654,85 @@ struct tpe_func_s {
struct hw_mod_tpe_v3_s v3;
};
};
+enum hw_tpe_e {
+ /* functions */
+ HW_TPE_PRESET_ALL = 0,
+ HW_TPE_FIND,
+ HW_TPE_COMPARE,
+ /* Control fields */
+ HW_TPE_RPP_RCP_EXP = FIELD_START_INDEX,
+ HW_TPE_IFR_RCP_IPV4_EN,
+ HW_TPE_IFR_RCP_IPV4_DF_DROP,
+ HW_TPE_IFR_RCP_IPV6_EN,
+ HW_TPE_IFR_RCP_IPV6_DROP,
+ HW_TPE_IFR_RCP_MTU,
+ HW_TPE_INS_RCP_DYN,
+ HW_TPE_INS_RCP_OFS,
+ HW_TPE_INS_RCP_LEN,
+ HW_TPE_RPL_RCP_DYN,
+ HW_TPE_RPL_RCP_OFS,
+ HW_TPE_RPL_RCP_LEN,
+ HW_TPE_RPL_RCP_RPL_PTR,
+ HW_TPE_RPL_RCP_EXT_PRIO,
+ HW_TPE_RPL_RCP_ETH_TYPE_WR,
+ HW_TPE_RPL_EXT_RPL_PTR,
+ HW_TPE_RPL_EXT_META_RPL_LEN,/* SW only */
+ HW_TPE_RPL_RPL_VALUE,
+ HW_TPE_CPY_RCP_READER_SELECT,
+ HW_TPE_CPY_RCP_DYN,
+ HW_TPE_CPY_RCP_OFS,
+ HW_TPE_CPY_RCP_LEN,
+ HW_TPE_HFU_RCP_LEN_A_WR,
+ HW_TPE_HFU_RCP_LEN_A_OUTER_L4_LEN,
+ HW_TPE_HFU_RCP_LEN_A_POS_DYN,
+ HW_TPE_HFU_RCP_LEN_A_POS_OFS,
+ HW_TPE_HFU_RCP_LEN_A_ADD_DYN,
+ HW_TPE_HFU_RCP_LEN_A_ADD_OFS,
+ HW_TPE_HFU_RCP_LEN_A_SUB_DYN,
+ HW_TPE_HFU_RCP_LEN_B_WR,
+ HW_TPE_HFU_RCP_LEN_B_POS_DYN,
+ HW_TPE_HFU_RCP_LEN_B_POS_OFS,
+ HW_TPE_HFU_RCP_LEN_B_ADD_DYN,
+ HW_TPE_HFU_RCP_LEN_B_ADD_OFS,
+ HW_TPE_HFU_RCP_LEN_B_SUB_DYN,
+ HW_TPE_HFU_RCP_LEN_C_WR,
+ HW_TPE_HFU_RCP_LEN_C_POS_DYN,
+ HW_TPE_HFU_RCP_LEN_C_POS_OFS,
+ HW_TPE_HFU_RCP_LEN_C_ADD_DYN,
+ HW_TPE_HFU_RCP_LEN_C_ADD_OFS,
+ HW_TPE_HFU_RCP_LEN_C_SUB_DYN,
+ HW_TPE_HFU_RCP_TTL_WR,
+ HW_TPE_HFU_RCP_TTL_POS_DYN,
+ HW_TPE_HFU_RCP_TTL_POS_OFS,
+ HW_TPE_CSU_RCP_OUTER_L3_CMD,
+ HW_TPE_CSU_RCP_OUTER_L4_CMD,
+ HW_TPE_CSU_RCP_INNER_L3_CMD,
+ HW_TPE_CSU_RCP_INNER_L4_CMD,
+};
+bool hw_mod_tpe_present(struct flow_api_backend_s *be);
+int hw_mod_tpe_alloc(struct flow_api_backend_s *be);
+void hw_mod_tpe_free(struct flow_api_backend_s *be);
+int hw_mod_tpe_reset(struct flow_api_backend_s *be);
+
+int hw_mod_tpe_rpp_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_tpe_rpp_ifr_rcp_flush(struct flow_api_backend_s *be, int start_idx,
int count);
+
+int hw_mod_tpe_ifr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_tpe_ins_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_tpe_rpl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_tpe_rpl_ext_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_tpe_rpl_rpl_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_tpe_cpy_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_tpe_hfu_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+
+int hw_mod_tpe_csu_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
enum debug_mode_e {
FLOW_BACKEND_DEBUG_MODE_NONE = 0x,
@@ -813,6 +892,7 @@ struct flow_api_backend_s {
struct qsl_func_s qsl;
struct slc_lr_func_s slc_lr;
struct pdb_func_s pdb;
+ struct tpe_func_s tpe;
/* NIC attributes */
unsigned int num_phy_ports;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 0415e5a5b2..e2eff3cf1e 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -56,6 +56,7 @@ sources = files(
'nthw/flow_api/hw_mod/hw_mod_pdb.c',
'nthw/flow_api/hw_mod/hw_mod_qsl.c',
'nthw/flow_api/hw_mod/hw_mod_slc_lr.c',
+'nthw/flow_api/hw_mod/hw_mod_tpe.c',
'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_csu.c',
'nthw/flow_filter/flow_nthw_flm.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c
b/drivers/net/ntnic/nthw/flow_api/flow_api.c
index 03946fb52f..9d47aed061 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_api.c
+++ b/drivers/net/ntnic/nthw/
[PATCH v2 32/50] net/ntnic: add queue select (QSL) FPGA module
From: Oleksandr Kolomeiets
The Queue Selector module directs packets to a given destination
which includes host queues, physical ports, exceptions paths, and discard.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 37
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c| 14 ++
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 +
.../ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c | 170 ++
.../supported/nthw_fpga_9563_055_049_.c | 57 +-
6 files changed, 279 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 6bf651272f..13e0d1731e 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -537,6 +537,42 @@ struct qsl_func_s {
struct hw_mod_qsl_v7_s v7;
};
};
+enum hw_qsl_e {
+ /* functions */
+ HW_QSL_RCP_PRESET_ALL = 0,
+ HW_QSL_RCP_COMPARE,
+ HW_QSL_RCP_FIND,
+ HW_QSL_QST_PRESET_ALL,
+ /* fields */
+ HW_QSL_RCP_DISCARD = FIELD_START_INDEX,
+ HW_QSL_RCP_DROP,
+ HW_QSL_RCP_TBL_LO,
+ HW_QSL_RCP_TBL_HI,
+ HW_QSL_RCP_TBL_IDX,
+ HW_QSL_RCP_TBL_MSK,
+ HW_QSL_RCP_LR,
+ HW_QSL_RCP_TSA,
+ HW_QSL_RCP_VLI,
+ HW_QSL_QST_QUEUE,
+ HW_QSL_QST_EN, /* Alias: HW_QSL_QST_QEN */
+ HW_QSL_QST_TX_PORT,
+ HW_QSL_QST_LRE,
+ HW_QSL_QST_TCI,
+ HW_QSL_QST_VEN,
+ HW_QSL_QEN_EN,
+ HW_QSL_UNMQ_DEST_QUEUE,
+ HW_QSL_UNMQ_EN,
+};
+bool hw_mod_qsl_present(struct flow_api_backend_s *be);
+int hw_mod_qsl_alloc(struct flow_api_backend_s *be);
+void hw_mod_qsl_free(struct flow_api_backend_s *be);
+int hw_mod_qsl_reset(struct flow_api_backend_s *be);
+int hw_mod_qsl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+int hw_mod_qsl_qst_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+int hw_mod_qsl_qen_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+int hw_mod_qsl_unmq_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+int hw_mod_qsl_unmq_set(struct flow_api_backend_s *be, enum hw_qsl_e field,
uint32_t index,
+ uint32_t value);
struct slc_lr_func_s {
COMMON_FUNC_INFO_S;
@@ -721,6 +757,7 @@ struct flow_api_backend_s {
struct km_func_s km;
struct flm_func_s flm;
struct hsh_func_s hsh;
+ struct qsl_func_s qsl;
/* NIC attributes */
unsigned int num_phy_ports;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 18aafc57f0..02981ef987 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -53,6 +53,7 @@ sources = files(
'nthw/flow_api/hw_mod/hw_mod_flm.c',
'nthw/flow_api/hw_mod/hw_mod_hsh.c',
'nthw/flow_api/hw_mod/hw_mod_km.c',
+'nthw/flow_api/hw_mod/hw_mod_qsl.c',
'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_csu.c',
'nthw/flow_filter/flow_nthw_flm.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c
b/drivers/net/ntnic/nthw/flow_api/flow_api.c
index b43c8fef1a..5d6571310c 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_api.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_api.c
@@ -144,6 +144,14 @@ int flow_delete_eth_dev(struct flow_eth_dev *eth_dev)
/* delete all created flows from this device */
pthread_mutex_lock(&ndev->mtx);
+ /*
+* remove unmatched queue if setup in QSL
+* remove exception queue setting in QSL UNM
+*/
+ hw_mod_qsl_unmq_set(&ndev->be, HW_QSL_UNMQ_DEST_QUEUE, eth_dev->port,
0);
+ hw_mod_qsl_unmq_set(&ndev->be, HW_QSL_UNMQ_EN, eth_dev->port, 0);
+ hw_mod_qsl_unmq_flush(&ndev->be, eth_dev->port, 1);
+
#ifdef FLOW_DEBUG
ndev->be.iface->set_debug_mode(ndev->be.be_dev,
FLOW_BACKEND_DEBUG_MODE_NONE);
#endif
@@ -293,6 +301,12 @@ struct flow_nic_dev *flow_api_create(uint8_t adapter_no,
const struct flow_api_b
if (init_resource_elements(ndev, RES_HSH_RCP, ndev->be.hsh.nb_rcp))
goto err_exit;
+ if (init_resource_elements(ndev, RES_QSL_RCP,
ndev->be.qsl.nb_rcp_categories))
+ goto err_exit;
+
+ if (init_resource_elements(ndev, RES_QSL_QST,
ndev->be.qsl.nb_qst_entries))
+ goto err_exit;
+
if (init_resource_elements(ndev, RES_SLC_LR_RCP,
ndev->be.max_categories))
goto err_exit;
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
index 3ccc14c4ce..4f16235a67 100644
--- a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
@@ -21,6 +21,7 @@ static const struct {
[PATCH v2 31/50] net/ntnic: add hasher (HSH) FPGA module
From: Oleksandr Kolomeiets
The Hasher module calculates a configurable hash value
to be used internally by the FPGA.
The module support both Toeplitz and NT-hash.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 36
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c| 3 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 +
.../ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c | 84 +++
.../supported/nthw_fpga_9563_055_049_.c | 39 -
6 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 3933d4bf53..6bf651272f 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -493,6 +493,41 @@ struct hsh_func_s {
struct hw_mod_hsh_v5_s v5;
};
};
+enum hw_hsh_e {
+ /* functions */
+ HW_HSH_RCP_PRESET_ALL = 0,
+ HW_HSH_RCP_COMPARE,
+ HW_HSH_RCP_FIND,
+ /* fields */
+ HW_HSH_RCP_LOAD_DIST_TYPE = FIELD_START_INDEX,
+ HW_HSH_RCP_MAC_PORT_MASK,
+ HW_HSH_RCP_SORT,
+ HW_HSH_RCP_QW0_PE,
+ HW_HSH_RCP_QW0_OFS,
+ HW_HSH_RCP_QW4_PE,
+ HW_HSH_RCP_QW4_OFS,
+ HW_HSH_RCP_W8_PE,
+ HW_HSH_RCP_W8_OFS,
+ HW_HSH_RCP_W8_SORT,
+ HW_HSH_RCP_W9_PE,
+ HW_HSH_RCP_W9_OFS,
+ HW_HSH_RCP_W9_SORT,
+ HW_HSH_RCP_W9_P,
+ HW_HSH_RCP_P_MASK,
+ HW_HSH_RCP_WORD_MASK,
+ HW_HSH_RCP_SEED,
+ HW_HSH_RCP_TNL_P,
+ HW_HSH_RCP_HSH_VALID,
+ HW_HSH_RCP_HSH_TYPE,
+ HW_HSH_RCP_TOEPLITZ,
+ HW_HSH_RCP_K,
+ HW_HSH_RCP_AUTO_IPV4_MASK
+};
+bool hw_mod_hsh_present(struct flow_api_backend_s *be);
+int hw_mod_hsh_alloc(struct flow_api_backend_s *be);
+void hw_mod_hsh_free(struct flow_api_backend_s *be);
+int hw_mod_hsh_reset(struct flow_api_backend_s *be);
+int hw_mod_hsh_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
struct qsl_func_s {
COMMON_FUNC_INFO_S;
@@ -685,6 +720,7 @@ struct flow_api_backend_s {
struct cat_func_s cat;
struct km_func_s km;
struct flm_func_s flm;
+ struct hsh_func_s hsh;
/* NIC attributes */
unsigned int num_phy_ports;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 9af7e3d813..18aafc57f0 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -51,6 +51,7 @@ sources = files(
'nthw/flow_api/hw_mod/hw_mod_backend.c',
'nthw/flow_api/hw_mod/hw_mod_cat.c',
'nthw/flow_api/hw_mod/hw_mod_flm.c',
+'nthw/flow_api/hw_mod/hw_mod_hsh.c',
'nthw/flow_api/hw_mod/hw_mod_km.c',
'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_csu.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c
b/drivers/net/ntnic/nthw/flow_api/flow_api.c
index d39bdc9936..b43c8fef1a 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_api.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_api.c
@@ -290,6 +290,9 @@ struct flow_nic_dev *flow_api_create(uint8_t adapter_no,
const struct flow_api_b
if (init_resource_elements(ndev, RES_KM_CATEGORY,
ndev->be.km.nb_categories))
goto err_exit;
+ if (init_resource_elements(ndev, RES_HSH_RCP, ndev->be.hsh.nb_rcp))
+ goto err_exit;
+
if (init_resource_elements(ndev, RES_SLC_LR_RCP,
ndev->be.max_categories))
goto err_exit;
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
index fe66493336..3ccc14c4ce 100644
--- a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
@@ -20,6 +20,7 @@ static const struct {
{ "CAT", hw_mod_cat_alloc, hw_mod_cat_free, hw_mod_cat_reset,
hw_mod_cat_present },
{ "KM", hw_mod_km_alloc, hw_mod_km_free, hw_mod_km_reset,
hw_mod_km_present },
{ "FLM", hw_mod_flm_alloc, hw_mod_flm_free, hw_mod_flm_reset,
hw_mod_flm_present },
+ { "HSH", hw_mod_hsh_alloc, hw_mod_hsh_free, hw_mod_hsh_reset,
hw_mod_hsh_present },
};
#define MOD_COUNT (ARRAY_SIZE(module))
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c
new file mode 100644
index 00..77dfbb5374
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c
@@ -0,0 +1,84 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include
+#include
+#include
+
+#include "hw_mod_backend.h"
+
+#define _MOD_ "HSH"
+#define _VER_ be->hsh.ver
+
+bool hw_mod_hsh_present(struct flow_api_backend_s *be)
+{
+ return be->iface->get_hsh_present(be->be_dev);
+}
+
+int hw_mod_hsh_all
[PATCH v2 37/50] net/ntnic: add basic queue operations
From: Danylo Vodopianov
Adds support for queue configure, start, stop, release.
The internal macro and functions of ntnic were also added and
initialized.
Signed-off-by: Danylo Vodopianov
---
doc/guides/nics/features/ntnic.ini | 1 +
drivers/net/ntnic/include/ntos_drv.h | 34 +
drivers/net/ntnic/ntnic_ethdev.c | 208 +++
drivers/net/ntnic/ntutil/nt_util.c | 10 ++
drivers/net/ntnic/ntutil/nt_util.h | 2 +
5 files changed, 255 insertions(+)
diff --git a/doc/guides/nics/features/ntnic.ini
b/doc/guides/nics/features/ntnic.ini
index b6d92c7ee1..8b9b87bdfe 100644
--- a/doc/guides/nics/features/ntnic.ini
+++ b/doc/guides/nics/features/ntnic.ini
@@ -7,6 +7,7 @@
FW version = Y
Speed capabilities = Y
Link status = Y
+Queue start/stop = Y
Unicast MAC filter = Y
Multicast MAC filter = Y
Linux= Y
diff --git a/drivers/net/ntnic/include/ntos_drv.h
b/drivers/net/ntnic/include/ntos_drv.h
index 67baf9fe0c..a77e6a0247 100644
--- a/drivers/net/ntnic/include/ntos_drv.h
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -13,6 +13,7 @@
#include
+#include "stream_binary_flow_api.h"
#include "nthw_drv.h"
#define NUM_MAC_ADDRS_PER_PORT (16U)
@@ -21,6 +22,32 @@
#define NUM_ADAPTER_MAX (8)
#define NUM_ADAPTER_PORTS_MAX (128)
+
+/* Max RSS queues */
+#define MAX_QUEUES 125
+
+/* Structs: */
+struct __rte_cache_aligned ntnic_rx_queue {
+ struct flow_queue_id_s queue;/* queue info - user id and hw queue
index */
+ struct rte_mempool *mb_pool; /* mbuf memory pool */
+ uint16_t buf_size; /* Size of data area in mbuf */
+ int enabled; /* Enabling/disabling of this queue */
+
+ nt_meta_port_type_t type;
+ uint32_t port; /* Rx port for this queue */
+ enum fpga_info_profile profile; /* Inline / Capture */
+
+};
+
+struct __rte_cache_aligned ntnic_tx_queue {
+ struct flow_queue_id_s queue; /* queue info - user id and hw queue
index */
+ nt_meta_port_type_t type;
+
+ uint32_t port; /* Tx port for this queue */
+ int enabled; /* Enabling/disabling of this queue */
+ enum fpga_info_profile profile; /* Inline / Capture */
+};
+
struct pmd_internals {
const struct rte_pci_device *pci_dev;
char name[20];
@@ -30,7 +57,14 @@ struct pmd_internals {
unsigned int nb_tx_queues;
/* Offset of the VF from the PF */
uint8_t vf_offset;
+ uint32_t port;
nt_meta_port_type_t type;
+ struct flow_queue_id_s vpq[MAX_QUEUES];
+ unsigned int vpq_nb_vq;
+ /* Array of Rx queues */
+ struct ntnic_rx_queue rxq_scg[MAX_QUEUES];
+ /* Array of Tx queues */
+ struct ntnic_tx_queue txq_scg[MAX_QUEUES];
struct drv_s *p_drv;
/* Ethernet (MAC) addresses. Element number zero denotes default
address. */
struct rte_ether_addr eth_addrs[NUM_MAC_ADDRS_PER_PORT];
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 5af18a3b27..967e989575 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -3,12 +3,17 @@
* Copyright(c) 2023 Napatech A/S
*/
+#include
+
#include
#include
#include
#include
#include
#include
+#include
+
+#include
#include "ntlog.h"
#include "ntdrv_4ga.h"
@@ -24,6 +29,23 @@
#define EXCEPTION_PATH_HID 0
+#define MAX_TOTAL_QUEUES 128
+
+/* Max RSS queues */
+#define MAX_QUEUES 125
+
+#define ETH_DEV_NTNIC_HELP_ARG "help"
+#define ETH_DEV_NTHW_RXQUEUES_ARG "rxqs"
+#define ETH_DEV_NTHW_TXQUEUES_ARG "txqs"
+
+static const char *const valid_arguments[] = {
+ ETH_DEV_NTNIC_HELP_ARG,
+ ETH_DEV_NTHW_RXQUEUES_ARG,
+ ETH_DEV_NTHW_TXQUEUES_ARG,
+ NULL,
+};
+
+
static const struct rte_pci_id nthw_pci_id_map[] = {
{ RTE_PCI_DEVICE(NT_HW_PCI_VENDOR_ID, NT_HW_PCI_DEVICE_ID_NT200A02) },
{
@@ -161,6 +183,58 @@ eth_dev_infos_get(struct rte_eth_dev *eth_dev, struct
rte_eth_dev_info *dev_info
return 0;
}
+static void eth_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t
queue_id)
+{
+ (void)eth_dev;
+ (void)queue_id;
+}
+
+static void eth_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t
queue_id)
+{
+ (void)eth_dev;
+ (void)queue_id;
+}
+
+static int num_queues_alloced;
+
+/* Returns num queue starting at returned queue num or -1 on fail */
+static int allocate_queue(int num)
+{
+ int next_free = num_queues_alloced;
+ NT_LOG_DBGX(DBG, NTNIC, "num_queues_alloced=%u, New queues=%u, Max
queues=%u\n",
+ num_queues_alloced, num, MAX_TOTAL_QUEUES);
+
+ if (num_queues_alloced + num > MAX_TOTAL_QUEUES)
+ return -1;
+
+ num_queues_alloced += num;
+ return next_free;
+}
+
+static int eth_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t
rx_queue_id)
+{
+ eth_dev->data->rx_queue_state[rx_queue_id] =
RTE_ETH_QUEUE_
[PATCH v2 36/50] net/ntnic: add receive MAC converter (RMC) core module
From: Oleksandr Kolomeiets
The RX MAC Converter module is part of the control mechanism
of the physical ports.
Signed-off-by: Oleksandr Kolomeiets
---
v2
* Fix Typo/Spelling
* Update release notes
---
doc/guides/rel_notes/release_24_11.rst| 1 +
drivers/net/ntnic/adapter/nt4ga_adapter.c | 14 +++
drivers/net/ntnic/include/nt4ga_adapter.h | 1 +
drivers/net/ntnic/include/ntnic_stat.h| 11 +++
drivers/net/ntnic/meson.build | 1 +
.../net/ntnic/nthw/core/include/nthw_rmc.h| 49 ++
drivers/net/ntnic/nthw/core/nthw_rmc.c| 90 +++
.../supported/nthw_fpga_9563_055_049_.c | 29 +-
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../nthw/supported/nthw_fpga_reg_defs_rmc.h | 36
11 files changed, 233 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/include/ntnic_stat.h
create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_rmc.h
create mode 100644 drivers/net/ntnic/nthw/core/nthw_rmc.c
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h
diff --git a/doc/guides/rel_notes/release_24_11.rst
b/doc/guides/rel_notes/release_24_11.rst
index 28d27366f1..705a62f226 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -106,6 +106,7 @@ New Features
* Extended and fixed the implementation of the logging
* Added NT flow filter init API
* Added NT flow backend initialization API
+ * Added initialization of FPGA modules related to flow HW offload
Removed Items
-
diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c
b/drivers/net/ntnic/adapter/nt4ga_adapter.c
index fd90f31abd..5d9db3450d 100644
--- a/drivers/net/ntnic/adapter/nt4ga_adapter.c
+++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c
@@ -212,6 +212,20 @@ static int nt4ga_adapter_init(struct adapter_info_s
*p_adapter_info)
}
}
+ nthw_rmc_t *p_nthw_rmc = nthw_rmc_new();
+ if (p_nthw_rmc == NULL) {
+ NT_LOG(ERR, NTNIC, "Failed to allocate memory for RMC
module\n");
+ return -1;
+ }
+
+ res = nthw_rmc_init(p_nthw_rmc, p_fpga, 0);
+ if (res) {
+ NT_LOG(ERR, NTNIC, "Failed to initialize RMC module\n");
+ return -1;
+ }
+
+ nthw_rmc_unblock(p_nthw_rmc, false);
+
return 0;
}
diff --git a/drivers/net/ntnic/include/nt4ga_adapter.h
b/drivers/net/ntnic/include/nt4ga_adapter.h
index 93218fd45b..809135f130 100644
--- a/drivers/net/ntnic/include/nt4ga_adapter.h
+++ b/drivers/net/ntnic/include/nt4ga_adapter.h
@@ -27,6 +27,7 @@ typedef struct hw_info_s {
* Services provided by the adapter module
*/
#include "nt4ga_filter.h"
+#include "ntnic_stat.h"
typedef struct adapter_info_s {
struct nt4ga_filter_s nt4ga_filter;
diff --git a/drivers/net/ntnic/include/ntnic_stat.h
b/drivers/net/ntnic/include/ntnic_stat.h
new file mode 100644
index 00..148088fe1d
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_stat.h
@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTNIC_STAT_H_
+#define NTNIC_STAT_H_
+
+#include "nthw_rmc.h"
+
+#endif /* NTNIC_STAT_H_ */
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index e2eff3cf1e..66d2770da7 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -41,6 +41,7 @@ sources = files(
'nthw/core/nthw_iic.c',
'nthw/core/nthw_mac_pcs.c',
'nthw/core/nthw_pcie3.c',
+'nthw/core/nthw_rmc.c',
'nthw/core/nthw_sdc.c',
'nthw/core/nthw_si5340.c',
'nthw/flow_api/flow_api.c',
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_rmc.h
b/drivers/net/ntnic/nthw/core/include/nthw_rmc.h
new file mode 100644
index 00..2345820bdc
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_rmc.h
@@ -0,0 +1,49 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_RMC_H_
+#define NTHW_RMC_H_
+
+#include "nthw_fpga_model.h"
+
+struct nthw_rmc {
+ nthw_fpga_t *mp_fpga;
+ nthw_module_t *mp_mod_rmc;
+ int mn_instance;
+
+ int mn_ports;
+ int mn_nims;
+
+ bool mb_administrative_block;
+
+ /* RMC CTRL register */
+ nthw_register_t *mp_reg_ctrl;
+ nthw_field_t *mp_fld_ctrl_block_stat_drop;
+ nthw_field_t *mp_fld_ctrl_block_keep_alive;
+ nthw_field_t *mp_fld_ctrl_block_mac_port;
+
+ /* RMC Status register */
+ nthw_register_t *mp_reg_status;
+ nthw_field_t *mp_fld_sf_ram_of;
+ nthw_field_t *mp_fld_descr_fifo_of;
+
+ /* RMC DBG register */
+ nthw_register_t *mp_reg_dbg;
+ nthw_field_t *mp_fld_dbg_merge;
+
+ /* RMC MAC_IF register */
+ nthw_register_t *mp_reg_mac_if;
+ nthw_field_t *mp_fld_mac_if
[PATCH v2 34/50] net/ntnic: add packet descriptor builder (PDB) FPGA module
From: Oleksandr Kolomeiets
The Packet Description Builder module creates packet meta-data
for example virtio-net headers.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 34
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c| 3 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 +
.../ntnic/nthw/flow_api/hw_mod/hw_mod_pdb.c | 86 +++
.../supported/nthw_fpga_9563_055_049_.c | 40 -
6 files changed, 164 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_pdb.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index b28192e682..9644639131 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -609,6 +609,39 @@ struct pdb_func_s {
struct hw_mod_pdb_v9_s v9;
};
};
+enum hw_pdb_e {
+ /* functions */
+ HW_PDB_RCP_PRESET_ALL = 0,
+ HW_PDB_RCP_COMPARE,
+ HW_PDB_RCP_FIND,
+ /* fields */
+ HW_PDB_RCP_DESCRIPTOR = FIELD_START_INDEX,
+ HW_PDB_RCP_DESC_LEN,
+ HW_PDB_RCP_TX_PORT,
+ HW_PDB_RCP_TX_IGNORE,
+ HW_PDB_RCP_TX_NOW,
+ HW_PDB_RCP_CRC_OVERWRITE,
+ HW_PDB_RCP_ALIGN,
+ HW_PDB_RCP_OFS0_DYN,
+ HW_PDB_RCP_OFS0_REL,
+ HW_PDB_RCP_OFS1_DYN,
+ HW_PDB_RCP_OFS1_REL,
+ HW_PDB_RCP_OFS2_DYN,
+ HW_PDB_RCP_OFS2_REL,
+ HW_PDB_RCP_IP_PROT_TNL,
+ HW_PDB_RCP_PPC_HSH,
+ HW_PDB_RCP_DUPLICATE_EN,
+ HW_PDB_RCP_DUPLICATE_BIT,
+ HW_PDB_RCP_PCAP_KEEP_FCS,
+ HW_PDB_CONFIG_TS_FORMAT,
+ HW_PDB_CONFIG_PORT_OFS,
+};
+bool hw_mod_pdb_present(struct flow_api_backend_s *be);
+int hw_mod_pdb_alloc(struct flow_api_backend_s *be);
+void hw_mod_pdb_free(struct flow_api_backend_s *be);
+int hw_mod_pdb_reset(struct flow_api_backend_s *be);
+int hw_mod_pdb_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+int hw_mod_pdb_config_flush(struct flow_api_backend_s *be);
struct tpe_func_s {
COMMON_FUNC_INFO_S;
@@ -779,6 +812,7 @@ struct flow_api_backend_s {
struct hsh_func_s hsh;
struct qsl_func_s qsl;
struct slc_lr_func_s slc_lr;
+ struct pdb_func_s pdb;
/* NIC attributes */
unsigned int num_phy_ports;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 4caee8ac41..0415e5a5b2 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -53,6 +53,7 @@ sources = files(
'nthw/flow_api/hw_mod/hw_mod_flm.c',
'nthw/flow_api/hw_mod/hw_mod_hsh.c',
'nthw/flow_api/hw_mod/hw_mod_km.c',
+'nthw/flow_api/hw_mod/hw_mod_pdb.c',
'nthw/flow_api/hw_mod/hw_mod_qsl.c',
'nthw/flow_api/hw_mod/hw_mod_slc_lr.c',
'nthw/flow_filter/flow_nthw_cat.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c
b/drivers/net/ntnic/nthw/flow_api/flow_api.c
index 5d6571310c..03946fb52f 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_api.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_api.c
@@ -301,6 +301,9 @@ struct flow_nic_dev *flow_api_create(uint8_t adapter_no,
const struct flow_api_b
if (init_resource_elements(ndev, RES_HSH_RCP, ndev->be.hsh.nb_rcp))
goto err_exit;
+ if (init_resource_elements(ndev, RES_PDB_RCP,
ndev->be.pdb.nb_pdb_rcp_categories))
+ goto err_exit;
+
if (init_resource_elements(ndev, RES_QSL_RCP,
ndev->be.qsl.nb_rcp_categories))
goto err_exit;
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
index 6b0ea2a4a6..118e49f539 100644
--- a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
@@ -26,6 +26,7 @@ static const struct {
"SLC LR", hw_mod_slc_lr_alloc, hw_mod_slc_lr_free,
hw_mod_slc_lr_reset,
hw_mod_slc_lr_present
},
+ { "PDB", hw_mod_pdb_alloc, hw_mod_pdb_free, hw_mod_pdb_reset,
hw_mod_pdb_present },
};
#define MOD_COUNT (ARRAY_SIZE(module))
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_pdb.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_pdb.c
new file mode 100644
index 00..13f0972e07
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_pdb.c
@@ -0,0 +1,86 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include
+#include
+#include
+
+#include "hw_mod_backend.h"
+
+#define _MOD_ "PDB"
+#define _VER_ be->pdb.ver
+
+bool hw_mod_pdb_present(struct flow_api_backend_s *be)
+{
+ return be->iface->get_pdb_present(be->be_dev);
+}
+
+int hw_mod_pdb_alloc(struct flow_api_backend_s *be)
+{
+ int nb;
+ _VER_ = be->iface->get_pdb_version(be->be_dev);
+ NT_LOG(DBG, FILTER,
[PATCH v2 33/50] net/ntnic: add slicer (SLC LR) FPGA module
From: Oleksandr Kolomeiets
The Slicer for Local Retransmit module can cut of the head a packet
before the packet leaves the FPGA RX pipeline.
This is used when the TX pipeline is configured
to add a new head in the packet.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 21 ++
drivers/net/ntnic/meson.build | 1 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 4 ++
.../nthw/flow_api/hw_mod/hw_mod_slc_lr.c | 65 +++
4 files changed, 91 insertions(+)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_slc_lr.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 13e0d1731e..b28192e682 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -7,6 +7,7 @@
#define _HW_MOD_BACKEND_H_
#include
+#include
#include "ntlog.h"
@@ -580,6 +581,25 @@ struct slc_lr_func_s {
struct hw_mod_slc_lr_v2_s v2;
};
};
+enum hw_slc_lr_e {
+ /* functions */
+ HW_SLC_LR_RCP_PRESET_ALL = 0,
+ HW_SLC_LR_RCP_COMPARE,
+ HW_SLC_LR_RCP_FIND,
+ /* fields */
+ HW_SLC_LR_RCP_HEAD_SLC_EN = FIELD_START_INDEX,
+ HW_SLC_LR_RCP_HEAD_DYN,
+ HW_SLC_LR_RCP_HEAD_OFS,
+ HW_SLC_LR_RCP_TAIL_SLC_EN,
+ HW_SLC_LR_RCP_TAIL_DYN,
+ HW_SLC_LR_RCP_TAIL_OFS,
+ HW_SLC_LR_RCP_PCAP
+};
+bool hw_mod_slc_lr_present(struct flow_api_backend_s *be);
+int hw_mod_slc_lr_alloc(struct flow_api_backend_s *be);
+void hw_mod_slc_lr_free(struct flow_api_backend_s *be);
+int hw_mod_slc_lr_reset(struct flow_api_backend_s *be);
+int hw_mod_slc_lr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
struct pdb_func_s {
COMMON_FUNC_INFO_S;
@@ -758,6 +778,7 @@ struct flow_api_backend_s {
struct flm_func_s flm;
struct hsh_func_s hsh;
struct qsl_func_s qsl;
+ struct slc_lr_func_s slc_lr;
/* NIC attributes */
unsigned int num_phy_ports;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 02981ef987..4caee8ac41 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -54,6 +54,7 @@ sources = files(
'nthw/flow_api/hw_mod/hw_mod_hsh.c',
'nthw/flow_api/hw_mod/hw_mod_km.c',
'nthw/flow_api/hw_mod/hw_mod_qsl.c',
+'nthw/flow_api/hw_mod/hw_mod_slc_lr.c',
'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_csu.c',
'nthw/flow_filter/flow_nthw_flm.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
index 4f16235a67..6b0ea2a4a6 100644
--- a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
@@ -22,6 +22,10 @@ static const struct {
{ "FLM", hw_mod_flm_alloc, hw_mod_flm_free, hw_mod_flm_reset,
hw_mod_flm_present },
{ "HSH", hw_mod_hsh_alloc, hw_mod_hsh_free, hw_mod_hsh_reset,
hw_mod_hsh_present },
{ "QSL", hw_mod_qsl_alloc, hw_mod_qsl_free, hw_mod_qsl_reset,
hw_mod_qsl_present },
+ {
+ "SLC LR", hw_mod_slc_lr_alloc, hw_mod_slc_lr_free,
hw_mod_slc_lr_reset,
+ hw_mod_slc_lr_present
+ },
};
#define MOD_COUNT (ARRAY_SIZE(module))
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_slc_lr.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_slc_lr.c
new file mode 100644
index 00..d95352ec67
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_slc_lr.c
@@ -0,0 +1,65 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include
+#include
+
+#include "hw_mod_backend.h"
+
+#define _MOD_ "SLC_LR"
+#define _VER_ be->slc_lr.ver
+
+bool hw_mod_slc_lr_present(struct flow_api_backend_s *be)
+{
+ return be->iface->get_slc_lr_present(be->be_dev);
+}
+
+int hw_mod_slc_lr_alloc(struct flow_api_backend_s *be)
+{
+ _VER_ = be->iface->get_slc_lr_version(be->be_dev);
+ NT_LOG(DBG, FILTER, "SLC LR MODULE VERSION %i.%i\n", VER_MAJOR(_VER_),
VER_MINOR(_VER_));
+
+ switch (_VER_) {
+ case 2:
+ if (!callocate_mod((struct common_func_s *)&be->slc_lr, 1,
&be->slc_lr.v2.rcp,
+ be->max_categories, sizeof(struct
slc_lr_v2_rcp_s)))
+ return -1;
+
+ break;
+
+ default:
+ return UNSUP_VER;
+ }
+
+ return 0;
+}
+
+void hw_mod_slc_lr_free(struct flow_api_backend_s *be)
+{
+ if (be->slc_lr.base) {
+ free(be->slc_lr.base);
+ be->slc_lr.base = NULL;
+ }
+}
+
+int hw_mod_slc_lr_reset(struct flow_api_backend_s *be)
+{
+ /* Zero entire cache area */
+ zero_module_cache((struct common_func_s *)(&be->slc_lr));
+
+ NT_LOG(DBG, FILTER, "INIT SLC LR RCP\n");
Re: [PATCH] app/flow-perf: replace RTE_BE32/16 with rte_cpu_to_be_32/16 for variables
On Tue, 18 Apr 2023 11:32:50 + Wisam Monther wrote: > Hi, > > > > > > > > -Original Message- > > > > From: Harold Huang > > > > Sent: Sunday, March 12, 2023 4:00 AM > > > > To: dev@dpdk.org > > > > Cc: Harold Huang ; Wisam Monther > > > > > > > > Subject: [PATCH] app/flow-perf: replace RTE_BE32/16 with > > > > rte_cpu_to_be_32/16 for variables > > > > > > > > In DPDK, the macros RTE_BE32 or RTE_BE16 are usually used for > > > > constant values. And functions such as rte_cpu_to_be_32 or > > > > rte_cpu_to_be_16 are optimized for variables. > > > > > > > > Signed-off-by: Harold Huang > > Acked-by: Wisam Jaddo Make sense. Really doesn't make much difference and I wounder why the macro version is necessary at all. Since the function already compiles to: #define rte_bswap32(x) ((uint32_t)(__builtin_constant_p(x) ?\ rte_constant_bswap32(x) :\ rte_arch_bswap32(x))) Acked-by: Stephen Hemminger
Re: [PATCH] examples/ipsec-secgw: fix cmp_sa_key bug
On Wed, 22 Nov 2023 15:58:40 +0800 supeng2087 wrote: > From: supeng > > Inbound direction, sad_lookup function will call cmp_sa_key to compare packet > outer ip info with local sa. Local sa src ip should equal packet dst ip, > Local sa dst ip should equal src ip. > --- > examples/ipsec-secgw/sad.h | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) Patch without Signed-off-by can not be accepted. For explanation of Signed-off-by see: https://en.wikipedia.org/wiki/Developer_Certificate_of_Origin
[PATCH v2 12/50] net/ntnic: add key match (KM) flow module
From: Oleksandr Kolomeiets
The Key Matcher module checks the values of individual fields of a packet.
It supports both exact match which is implemented with a CAM,
and wildcards which is implemented with a TCAM.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 28 +
drivers/net/ntnic/include/hw_mod_km_v7.h | 96 +++
drivers/net/ntnic/meson.build | 1 +
.../nthw/flow_api/flow_backend/flow_backend.c | 206 ++
.../net/ntnic/nthw/flow_filter/flow_nthw_km.c | 610 ++
.../net/ntnic/nthw/flow_filter/flow_nthw_km.h | 214 ++
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../nthw/supported/nthw_fpga_reg_defs_km.h| 126
9 files changed, 1283 insertions(+)
create mode 100644 drivers/net/ntnic/include/hw_mod_km_v7.h
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_km.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index ce2c0cf7cf..b921c06643 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -10,6 +10,7 @@
#include "hw_mod_cat_v18.h"
#include "hw_mod_cat_v21.h"
+#include "hw_mod_km_v7.h"
#define MAX_PHYS_ADAPTERS 8
@@ -40,6 +41,23 @@ struct cat_func_s {
};
};
+struct km_func_s {
+ COMMON_FUNC_INFO_S;
+ uint32_t nb_categories;
+ uint32_t nb_cam_banks;
+ uint32_t nb_cam_record_words;
+ uint32_t nb_cam_records;
+ uint32_t nb_tcam_banks;
+ uint32_t nb_tcam_bank_width;
+ /* not read from backend, but rather set using version */
+ uint32_t nb_km_rcp_mask_a_word_size;
+ /* --- || --- */
+ uint32_t nb_km_rcp_mask_b_word_size;
+ union {
+ struct hw_mod_km_v7_s v7;
+ };
+};
+
enum debug_mode_e {
FLOW_BACKEND_DEBUG_MODE_NONE = 0x,
FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001
@@ -112,6 +130,16 @@ struct flow_api_backend_ops {
int (*cat_rck_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
int (*cat_len_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
int (*cat_kcc_flush)(void *dev, const struct cat_func_s *cat, int
index, int cnt);
+
+ /* KM */
+ bool (*get_km_present)(void *dev);
+ uint32_t (*get_km_version)(void *dev);
+ int (*km_rcp_flush)(void *dev, const struct km_func_s *km, int
category, int cnt);
+ int (*km_cam_flush)(void *dev, const struct km_func_s *km, int bank,
int record, int cnt);
+ int (*km_tcam_flush)(void *dev, const struct km_func_s *km, int bank,
int byte, int value,
+ int cnt);
+ int (*km_tci_flush)(void *dev, const struct km_func_s *km, int bank,
int record, int cnt);
+ int (*km_tcq_flush)(void *dev, const struct km_func_s *km, int bank,
int record, int cnt);
};
struct flow_api_backend_s {
diff --git a/drivers/net/ntnic/include/hw_mod_km_v7.h
b/drivers/net/ntnic/include/hw_mod_km_v7.h
new file mode 100644
index 00..dcc28c1812
--- /dev/null
+++ b/drivers/net/ntnic/include/hw_mod_km_v7.h
@@ -0,0 +1,96 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _HW_MOD_KM_V7_H_
+#define _HW_MOD_KM_V7_H_
+
+#include
+
+struct km_v7_rcp_s {
+ uint32_t qw0_dyn;
+ int32_t qw0_ofs;
+ uint32_t qw0_sel_a;
+ uint32_t qw0_sel_b;
+ uint32_t qw4_dyn;
+ int32_t qw4_ofs;
+ uint32_t qw4_sel_a;
+ uint32_t qw4_sel_b;
+ uint32_t dw8_dyn;
+ int32_t dw8_ofs;
+ uint32_t dw8_sel_a;
+ uint32_t dw8_sel_b;
+ uint32_t dw10_dyn;
+ int32_t dw10_ofs;
+ uint32_t dw10_sel_a;
+ uint32_t dw10_sel_b;
+ uint32_t swx_cch;
+ uint32_t swx_sel_a;
+ uint32_t swx_sel_b;
+ uint32_t mask_d_a[12];
+ uint32_t mask_b[6];
+ uint32_t dual;
+ uint32_t paired;
+ uint32_t el_a;
+ uint32_t el_b;
+ uint32_t info_a;
+ uint32_t info_b;
+ uint32_t ftm_a;
+ uint32_t ftm_b;
+ uint32_t bank_a;
+ uint32_t bank_b;
+ uint32_t kl_a;
+ uint32_t kl_b;
+ uint32_t keyway_a;
+ uint32_t keyway_b;
+ uint32_t synergy_mode;
+ uint32_t dw0_b_dyn;
+ int32_t dw0_b_ofs;
+ uint32_t dw2_b_dyn;
+ int32_t dw2_b_ofs;
+ uint32_t sw4_b_dyn;
+ int32_t sw4_b_ofs;
+ uint32_t sw5_b_dyn;
+ int32_t sw5_b_ofs;
+};
+
+struct km_v7_cam_s {
+ uint32_t w0;
+ uint32_t w1;
+ uint32_t w2;
+ uint32_t w3;
+ uint32_t w4;
+ uint32_t w5;
+ uint32_t ft0;
+ uint32_t ft1;
+ uint32_t ft2;
+ uint32_t ft3;
+ uint32_t ft4;
+ uint32_t ft5;
+};
[PATCH v2 25/50] net/ntnic: add Tx Packet Editor (TPE) flow module
The TX Packet Editor is a software abstraction module,
that keeps track of the handful of FPGA modules
that are used to edit packets in the TX pipeline.
Signed-off-by: Serhii Iliushyk
---
drivers/net/ntnic/include/hw_mod_backend.h| 27 ++
drivers/net/ntnic/include/hw_mod_tpe_v3.h | 126 ++
.../nthw/flow_api/flow_backend/flow_backend.c | 364 ++
.../ntnic/nthw/flow_filter/flow_nthw_csu.c| 79
.../ntnic/nthw/flow_filter/flow_nthw_csu.h| 9 +
.../ntnic/nthw/flow_filter/flow_nthw_hfu.c| 131 +++
.../ntnic/nthw/flow_filter/flow_nthw_hfu.h| 30 ++
.../ntnic/nthw/flow_filter/flow_nthw_ifr.c| 55 +++
.../ntnic/nthw/flow_filter/flow_nthw_ifr.h| 11 +
.../ntnic/nthw/flow_filter/flow_nthw_rpp_lr.c | 81
.../ntnic/nthw/flow_filter/flow_nthw_rpp_lr.h | 17 +
.../ntnic/nthw/flow_filter/flow_nthw_tx_cpy.c | 49 +++
.../ntnic/nthw/flow_filter/flow_nthw_tx_cpy.h | 10 +
.../ntnic/nthw/flow_filter/flow_nthw_tx_ins.c | 36 ++
.../ntnic/nthw/flow_filter/flow_nthw_tx_ins.h | 9 +
.../ntnic/nthw/flow_filter/flow_nthw_tx_rpl.c | 94 +
.../ntnic/nthw/flow_filter/flow_nthw_tx_rpl.h | 22 ++
17 files changed, 1150 insertions(+)
create mode 100644 drivers/net/ntnic/include/hw_mod_tpe_v3.h
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 3ea2fefc53..29c33306d1 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -16,6 +16,7 @@
#include "hw_mod_pdb_v9.h"
#include "hw_mod_slc_lr_v2.h"
#include "hw_mod_hsh_v5.h"
+#include "hw_mod_tpe_v3.h"
#define MAX_PHYS_ADAPTERS 8
@@ -114,6 +115,18 @@ struct pdb_func_s {
};
};
+struct tpe_func_s {
+ COMMON_FUNC_INFO_S;
+ uint32_t nb_rcp_categories;
+ uint32_t nb_ifr_categories;
+ uint32_t nb_cpy_writers;
+ uint32_t nb_rpl_depth;
+ uint32_t nb_rpl_ext_categories;
+ union {
+ struct hw_mod_tpe_v3_s v3;
+ };
+};
+
enum debug_mode_e {
FLOW_BACKEND_DEBUG_MODE_NONE = 0x,
FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001
@@ -244,6 +257,20 @@ struct flow_api_backend_ops {
uint32_t (*get_pdb_version)(void *dev);
int (*pdb_rcp_flush)(void *dev, const struct pdb_func_s *pdb, int
category, int cnt);
int (*pdb_config_flush)(void *dev, const struct pdb_func_s *pdb);
+
+ /* TPE */
+ bool (*get_tpe_present)(void *dev);
+ uint32_t (*get_tpe_version)(void *dev);
+ int (*tpe_rpp_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
+ int (*tpe_rpp_ifr_rcp_flush)(void *dev, const struct tpe_func_s *tpe,
int index, int cnt);
+ int (*tpe_ifr_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
+ int (*tpe_ins_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
+ int (*tpe_rpl_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
+ int (*tpe_rpl_ext_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
+ int (*tpe_rpl_rpl_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
+ int (*tpe_cpy_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
+ int (*tpe_hfu_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
+ int (*tpe_csu_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int
index, int cnt);
};
struct flow_api_backend_s {
diff --git a/drivers/net/ntnic/include/hw_mod_tpe_v3.h
b/drivers/net/ntnic/include/hw_mod_tpe_v3.h
new file mode 100644
index 00..87710d8b35
--- /dev/null
+++ b/drivers/net/ntnic/include/hw_mod_tpe_v3.h
@@ -0,0 +1,126 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _HW_MOD_TPE_V3_H_
+#define _HW_MOD_TPE_V3_H_
+
+#include
+
+struct tpe_v1_rpp_v0_rcp_s {
+ uint32_t exp;
+};
+
+struct tpe_v1_ins_v1_rcp_s {
+ uint32_t dyn;
+ uint32_t ofs;
+ uint32_t len;
+};
+
+struct tpe_v3_rpl_v4_rcp_s {
+ uint32_t dyn;
+ uint32_t ofs;
+ uint32_t len;
+ uint32_t rpl_ptr;
+ uint32_t ext_prio;
+ uint32_t eth_type_wr;
+};
+
+struct tpe_v1_rpl_v2_ext_s {
+ uint32_t rpl_ptr;
+ uint32_t meta_rpl_len; /* SW only */
+};
+
+struct tpe_v1_rpl_v2_rpl_s {
+ uint32_t value[4];
+};
+
+struct tpe_v1_cpy_v1_rcp_s {
+ uint32_t reader_select;
+ uint32_t dyn;
+ uint32_t ofs;
+ uint32_t len;
+};
+
+struct tpe_v1_hfu_v1_rcp_s {
+ uint32_t len_a_wr;
+ uint32_t len_a_outer_l4_len;
+ uint32_t len_a_pos_dyn;
+ uint32_t len_a_pos_ofs;
+ uint32_t len_a_add_dyn;
+ uint32_t len_a_add_ofs;
+ uint32_t len_a_sub_dyn;
+
+ uint32_t len_b_wr;
+ uint32_t len_b_pos_dyn;
+ uint32_t len_b_pos_ofs;
+ uint32_t len_b_add_dyn;
+ uint32_t len_b_add_ofs;
+ uint32_t len_b_s
[PATCH v2 24/50] net/ntnic: add replacer (Tx RPL) flow module
From: Oleksandr Kolomeiets
The TX Replacer module can replace a range of bytes in a packet.
The replacing data is stored in a table in the module
and will often contain tunnel data.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/meson.build | 1 +
.../nthw/flow_api/flow_backend/flow_backend.c | 13
.../ntnic/nthw/flow_filter/flow_nthw_tx_rpl.c | 78 +++
.../ntnic/nthw/flow_filter/flow_nthw_tx_rpl.h | 52 +
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 2 +
.../nthw/supported/nthw_fpga_reg_defs_rpl.h | 43 ++
.../supported/nthw_fpga_reg_defs_tx_rpl.h | 23 ++
8 files changed, 213 insertions(+)
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_rpl.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_rpl.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 7e0900f0eb..e236b82b36 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -60,6 +60,7 @@ sources = files(
'nthw/flow_filter/flow_nthw_slc_lr.c',
'nthw/flow_filter/flow_nthw_tx_cpy.c',
'nthw/flow_filter/flow_nthw_tx_ins.c',
+'nthw/flow_filter/flow_nthw_tx_rpl.c',
'nthw/model/nthw_fpga_model.c',
'nthw/nthw_platform.c',
'nthw/nthw_rac.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
index 1b4c6d6b4d..f093bfb8bb 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -19,6 +19,7 @@
#include "flow_nthw_rpp_lr.h"
#include "flow_nthw_tx_cpy.h"
#include "flow_nthw_tx_ins.h"
+#include "flow_nthw_tx_rpl.h"
#include "ntnic_mod_reg.h"
#include "nthw_fpga_model.h"
#include "hw_mod_backend.h"
@@ -45,6 +46,7 @@ static struct backend_dev_s {
struct rpp_lr_nthw *p_rpp_lr_nthw; /* TPE module */
struct tx_cpy_nthw *p_tx_cpy_nthw; /* TPE module */
struct tx_ins_nthw *p_tx_ins_nthw; /* TPE module */
+ struct tx_rpl_nthw *p_tx_rpl_nthw; /* TPE module */
struct csu_nthw *p_csu_nthw;/* TPE module */
struct ifr_nthw *p_ifr_nthw;/* TPE module */
} be_devs[MAX_PHYS_ADAPTERS];
@@ -1843,6 +1845,16 @@ const struct flow_api_backend_ops
*bin_flow_backend_init(nthw_fpga_t *p_fpga, vo
be_devs[physical_adapter_no].p_tx_ins_nthw = NULL;
}
+ /* Init nthw TX_RPL */
+ if (tx_rpl_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) {
+ struct tx_rpl_nthw *ptr = tx_rpl_nthw_new();
+ tx_rpl_nthw_init(ptr, p_fpga, physical_adapter_no);
+ be_devs[physical_adapter_no].p_tx_rpl_nthw = ptr;
+
+ } else {
+ be_devs[physical_adapter_no].p_tx_rpl_nthw = NULL;
+ }
+
be_devs[physical_adapter_no].adapter_no = physical_adapter_no;
*dev = (void *)&be_devs[physical_adapter_no];
@@ -1865,6 +1877,7 @@ static void bin_flow_backend_done(void *dev)
rpp_lr_nthw_delete(be_dev->p_rpp_lr_nthw);
tx_cpy_nthw_delete(be_dev->p_tx_cpy_nthw);
tx_ins_nthw_delete(be_dev->p_tx_ins_nthw);
+ tx_rpl_nthw_delete(be_dev->p_tx_rpl_nthw);
}
static const struct flow_backend_ops ops = {
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_rpl.c
b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_rpl.c
new file mode 100644
index 00..65fc1a9c5e
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_rpl.c
@@ -0,0 +1,78 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include
+#include
+
+#include "ntlog.h"
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "flow_nthw_tx_rpl.h"
+
+struct tx_rpl_nthw *tx_rpl_nthw_new(void)
+{
+ struct tx_rpl_nthw *p = malloc(sizeof(struct tx_rpl_nthw));
+
+ if (p)
+ (void)memset(p, 0, sizeof(*p));
+
+ return p;
+}
+
+void tx_rpl_nthw_delete(struct tx_rpl_nthw *p)
+{
+ if (p) {
+ (void)memset(p, 0, sizeof(*p));
+ free(p);
+ }
+}
+
+int tx_rpl_nthw_init(struct tx_rpl_nthw *p, nthw_fpga_t *p_fpga, int
n_instance)
+{
+ const char *const p_adapter_id_str =
p_fpga->p_fpga_info->mp_adapter_id_str;
+ nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_TX_RPL,
n_instance);
+
+ assert(n_instance >= 0 && n_instance < 256);
+
+ if (p == NULL)
+ return p_mod == NULL ? -1 : 0;
+
+ if (p_mod == NULL) {
+ NT_LOG(ERR, NTHW, "%s: TxRpl %d: no such instance\n",
p_adapter_id_str,
+ n_instance);
+ return -1;
+ }
[PATCH v2 18/50] net/ntnic: add packet descriptor builder (PDB) flow module
From: Oleksandr Kolomeiets
The Packet Description Builder module creates packet meta-data
for example virtio-net headers.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/include/hw_mod_backend.h| 16 ++
drivers/net/ntnic/include/hw_mod_pdb_v9.h | 42
drivers/net/ntnic/meson.build | 1 +
.../nthw/flow_api/flow_backend/flow_backend.c | 93
.../ntnic/nthw/flow_filter/flow_nthw_pdb.c| 210 ++
.../ntnic/nthw/flow_filter/flow_nthw_pdb.h| 85 +++
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../nthw/supported/nthw_fpga_reg_defs_pdb.h | 48
9 files changed, 497 insertions(+)
create mode 100644 drivers/net/ntnic/include/hw_mod_pdb_v9.h
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 309365f30d..3ea2fefc53 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -13,6 +13,7 @@
#include "hw_mod_flm_v25.h"
#include "hw_mod_km_v7.h"
#include "hw_mod_qsl_v7.h"
+#include "hw_mod_pdb_v9.h"
#include "hw_mod_slc_lr_v2.h"
#include "hw_mod_hsh_v5.h"
@@ -104,6 +105,15 @@ struct slc_lr_func_s {
};
};
+struct pdb_func_s {
+ COMMON_FUNC_INFO_S;
+ uint32_t nb_pdb_rcp_categories;
+
+ union {
+ struct hw_mod_pdb_v9_s v9;
+ };
+};
+
enum debug_mode_e {
FLOW_BACKEND_DEBUG_MODE_NONE = 0x,
FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001
@@ -228,6 +238,12 @@ struct flow_api_backend_ops {
uint32_t (*get_slc_lr_version)(void *dev);
int (*slc_lr_rcp_flush)(void *dev, const struct slc_lr_func_s *slc_lr,
int category,
int cnt);
+
+ /* PDB */
+ bool (*get_pdb_present)(void *dev);
+ uint32_t (*get_pdb_version)(void *dev);
+ int (*pdb_rcp_flush)(void *dev, const struct pdb_func_s *pdb, int
category, int cnt);
+ int (*pdb_config_flush)(void *dev, const struct pdb_func_s *pdb);
};
struct flow_api_backend_s {
diff --git a/drivers/net/ntnic/include/hw_mod_pdb_v9.h
b/drivers/net/ntnic/include/hw_mod_pdb_v9.h
new file mode 100644
index 00..b155ee6d1e
--- /dev/null
+++ b/drivers/net/ntnic/include/hw_mod_pdb_v9.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _HW_MOD_PDB_V9_H_
+#define _HW_MOD_PDB_V9_H_
+
+#include
+
+struct pdb_v9_rcp_s {
+ uint32_t descriptor;
+ uint32_t desc_len;
+ uint32_t tx_port;
+ uint32_t tx_ignore;
+ uint32_t tx_now;
+ uint32_t crc_overwrite;
+ uint32_t align;
+ uint32_t ofs0_dyn;
+ int32_t ofs0_rel;
+ uint32_t ofs1_dyn;
+ int32_t ofs1_rel;
+ uint32_t ofs2_dyn;
+ int32_t ofs2_rel;
+ uint32_t ip_prot_tnl;
+ uint32_t ppc_hsh;
+ uint32_t duplicate_en;
+ uint32_t duplicate_bit;
+ uint32_t pcap_keep_fcs; /* only field added to v9 cmp to v7/8 */
+};
+
+struct pdb_v9_config_s {
+ uint32_t ts_format;
+ uint32_t port_ofs;
+};
+
+struct hw_mod_pdb_v9_s {
+ struct pdb_v9_rcp_s *rcp;
+ struct pdb_v9_config_s *config;
+};
+
+#endif /* _HW_MOD_PDB_V9_H_ */
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 2c303f6980..35f7feb7be 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -52,6 +52,7 @@ sources = files(
'nthw/flow_filter/flow_nthw_ifr.c',
'nthw/flow_filter/flow_nthw_info.c',
'nthw/flow_filter/flow_nthw_km.c',
+'nthw/flow_filter/flow_nthw_pdb.c',
'nthw/flow_filter/flow_nthw_qsl.c',
'nthw/flow_filter/flow_nthw_slc_lr.c',
'nthw/model/nthw_fpga_model.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
index 6188d900bb..e3c4c5b7cb 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -13,6 +13,7 @@
#include "flow_nthw_hsh.h"
#include "flow_nthw_qsl.h"
#include "flow_nthw_slc_lr.h"
+#include "flow_nthw_pdb.h"
#include "ntnic_mod_reg.h"
#include "nthw_fpga_model.h"
#include "hw_mod_backend.h"
@@ -34,6 +35,7 @@ static struct backend_dev_s {
struct hsh_nthw *p_hsh_nthw;
struct qsl_nthw *p_qsl_nthw;
struct slc_lr_nthw *p_slc_lr_nthw;
+ struct pdb_nthw *p_pdb_nthw;
struct ifr_nthw *p_ifr_nthw;/* TPE module */
} be_devs[MAX_PHYS_ADAPTERS];
@@ -1487,6 +1489,81 @@ static int slc_lr_rcp_flush(void *be_dev, const struct
slc_lr_func_s *slc_lr, in
return 0;
}
+/*
+ * PDB
+ */
[PATCH v2 23/50] net/ntnic: add insert (Tx INS) flow module
From: Oleksandr Kolomeiets
he TX Inserter module injects zeros into an offset of a packet,
effectively expanding the packet.
Signed-off-by: Oleksandr Kolomeiets
---
drivers/net/ntnic/meson.build | 1 +
.../nthw/flow_api/flow_backend/flow_backend.c | 13
.../ntnic/nthw/flow_filter/flow_nthw_tx_ins.c | 62 +++
.../ntnic/nthw/flow_filter/flow_nthw_tx_ins.h | 35 +++
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 2 +
.../nthw/supported/nthw_fpga_reg_defs_ins.h | 30 +
.../supported/nthw_fpga_reg_defs_tx_ins.h | 23 +++
8 files changed, 167 insertions(+)
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_ins.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_ins.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index cc5e6fe100..7e0900f0eb 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -59,6 +59,7 @@ sources = files(
'nthw/flow_filter/flow_nthw_rpp_lr.c',
'nthw/flow_filter/flow_nthw_slc_lr.c',
'nthw/flow_filter/flow_nthw_tx_cpy.c',
+'nthw/flow_filter/flow_nthw_tx_ins.c',
'nthw/model/nthw_fpga_model.c',
'nthw/nthw_platform.c',
'nthw/nthw_rac.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
index c12a3204bc..1b4c6d6b4d 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -18,6 +18,7 @@
#include "flow_nthw_pdb.h"
#include "flow_nthw_rpp_lr.h"
#include "flow_nthw_tx_cpy.h"
+#include "flow_nthw_tx_ins.h"
#include "ntnic_mod_reg.h"
#include "nthw_fpga_model.h"
#include "hw_mod_backend.h"
@@ -43,6 +44,7 @@ static struct backend_dev_s {
struct hfu_nthw *p_hfu_nthw;/* TPE module */
struct rpp_lr_nthw *p_rpp_lr_nthw; /* TPE module */
struct tx_cpy_nthw *p_tx_cpy_nthw; /* TPE module */
+ struct tx_ins_nthw *p_tx_ins_nthw; /* TPE module */
struct csu_nthw *p_csu_nthw;/* TPE module */
struct ifr_nthw *p_ifr_nthw;/* TPE module */
} be_devs[MAX_PHYS_ADAPTERS];
@@ -1831,6 +1833,16 @@ const struct flow_api_backend_ops
*bin_flow_backend_init(nthw_fpga_t *p_fpga, vo
be_devs[physical_adapter_no].p_csu_nthw = NULL;
}
+ /* Init nthw TX_INS */
+ if (tx_ins_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) {
+ struct tx_ins_nthw *ptr = tx_ins_nthw_new();
+ tx_ins_nthw_init(ptr, p_fpga, physical_adapter_no);
+ be_devs[physical_adapter_no].p_tx_ins_nthw = ptr;
+
+ } else {
+ be_devs[physical_adapter_no].p_tx_ins_nthw = NULL;
+ }
+
be_devs[physical_adapter_no].adapter_no = physical_adapter_no;
*dev = (void *)&be_devs[physical_adapter_no];
@@ -1852,6 +1864,7 @@ static void bin_flow_backend_done(void *dev)
hfu_nthw_delete(be_dev->p_hfu_nthw);
rpp_lr_nthw_delete(be_dev->p_rpp_lr_nthw);
tx_cpy_nthw_delete(be_dev->p_tx_cpy_nthw);
+ tx_ins_nthw_delete(be_dev->p_tx_ins_nthw);
}
static const struct flow_backend_ops ops = {
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_ins.c
b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_ins.c
new file mode 100644
index 00..5d9867981e
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_tx_ins.c
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include
+#include
+
+#include "ntlog.h"
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "flow_nthw_tx_ins.h"
+
+struct tx_ins_nthw *tx_ins_nthw_new(void)
+{
+ struct tx_ins_nthw *p = malloc(sizeof(struct tx_ins_nthw));
+
+ if (p)
+ (void)memset(p, 0, sizeof(*p));
+
+ return p;
+}
+
+void tx_ins_nthw_delete(struct tx_ins_nthw *p)
+{
+ if (p) {
+ (void)memset(p, 0, sizeof(*p));
+ free(p);
+ }
+}
+
+int tx_ins_nthw_init(struct tx_ins_nthw *p, nthw_fpga_t *p_fpga, int
n_instance)
+{
+ const char *const p_adapter_id_str =
p_fpga->p_fpga_info->mp_adapter_id_str;
+ nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_TX_INS,
n_instance);
+
+ assert(n_instance >= 0 && n_instance < 256);
+
+ if (p == NULL)
+ return p_mod == NULL ? -1 : 0;
+
+ if (p_mod == NULL) {
+ NT_LOG(ERR, NTHW, "%s: TxIns %d: no such instance\n",
p_adapter_id_str,
+ n_instance);
+ return -1;
+ }
+
+ p->mp_fpga = p_fpga;
+ p->m_physical_adapter_no = (uint8_t)n_i
