[PATCH] D80415: [AIX] Add '-bcdtors:all:0:s' to linker to gather static init functions

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/Driver/aix-ld.cpp:1
+// Check powerpc-ibm-aix7.1.0.0, 32-bit. 'bcdtors' and Arguemnt order.
+// // RUN: %clang++ -no-canonical-prefixes %s -### -o %t.o 2>&1 \

s/Arguemnt/Argument/



Comment at: clang/test/Driver/aix-ld.cpp:7
+// // RUN:   | FileCheck --check-prefix=CHECK-LD32-ARG-ORDER %s
+// // CHECK-LD32-ARG-ORDER-NOT: warning:
+// // CHECK-LD32-ARG-ORDER: {{.*}}clang++" "-cc1" "-triple" 
"powerpc-ibm-aix7.1.0.0"

Add a line between the run steps and check, and can you align things 
vertically. 

Eg. 

```
CHECK-LD32-ARG-ORDER-NOT: warning:
CHECK-LD32-ARG-ORDER: {{.*}}clang++" "-cc1" "-triple" 
"powerpc-ibm-aix7.1.0.0"
```


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[PATCH] D80415: [AIX] Add '-bcdtors:all:0:s' to linker to gather static init functions

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/Driver/aix-ld.cpp:3
+// // RUN: %clang++ -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// // RUN: -Wl,-bnocdtors \
+// // RUN: -target powerpc-ibm-aix7.1.0.0 \

formatting, align with the line above


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[PATCH] D76130: [PPC][AIX] Implement variadic function handling in LowerFormalArguments_AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 255321.
ZarkoCA added a comment.

Rebase and ping.


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Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
  llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll

Index: llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
@@ -0,0 +1,357 @@
+; RUN: llc -O2 -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
+
+; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefixes=CHECKASM,ASM64 %s
+
+  define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr  {
+  entry:
+%arg1 = alloca i8*, align 8
+%arg2 = alloca i8*, align 8
+%0 = bitcast i8** %arg1 to i8*
+call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) 
+%1 = bitcast i8** %arg2 to i8*
+call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %1)
+call void @llvm.va_start(i8* nonnull %0)
+call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+%2 = va_arg i8** %arg1, i32
+%add = add nsw i32 %2, %a
+%3 = va_arg i8** %arg2, i32
+%mul = shl i32 %3, 1
+%add3 = add nsw i32 %add, %mul
+call void @llvm.va_end(i8* nonnull %0)
+call void @llvm.va_end(i8* nonnull %1)
+call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %1) 
+call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0) 
+ret i32 %add3
+  }
+
+  declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) 
+  declare void @llvm.va_start(i8*) 
+  declare void @llvm.va_copy(i8*, i8*) 
+  declare void @llvm.va_end(i8*) 
+  declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) 
+  
+; 64BIT-LABEL:   name:int_va_arg
+; 64BIT-LABEL:   liveins:
+; 64BIT-DAG: - { reg: '$x3', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x4', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x5', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x6', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x7', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x8', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x9', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x10', virtual-reg: '' }
+
+; 64BIT-LABEL:   fixedStack:
+; 64BIT-DAG: - { id: 0, type: default, offset: 56, size: 8
+
+; 64BIT-LABEL:   stack:
+; 64BIT-DAG: - { id: 0, name: arg1, type: default, offset: 0, size: 8
+; 64BIT-DAG: - { id: 1, name: arg2, type: default, offset: 0, size: 8 
+
+; 64BIT-LABEL:   body: |
+; 64BIT-DAG: bb.0.entry:
+; 64BIT-DAG: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+; 64BIT-DAG: STD killed renamable $x4, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0)
+; 64BIT-DAG: STD killed renamable $x5, 8, %fixed-stack.0 :: (store 8 into %fixed-stack.0 + 8)
+; 64BIT-DAG: STD killed renamable $x6, 16, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x7, 24, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x8, 32, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x9, 40, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x10, 48, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: renamable $x11 = ADDI8 %fixed-stack.0, 0
+; 64BIT-DAG: STD renamable $x11, 0, %stack.1.arg2 :: (store 8 into %ir.1)
+; 64BIT-DAG: renamable $x4 = LD 0, %stack.1.arg2 :: (load 8 from %ir.arg2)
+; 64BIT-DAG: renamable $x7 = ADDI8 renamable $x4, 4
+; 64BIT-DAG: renamable $x5 = ADDI8 %fixed-stack.0, 4
+; 64BIT-DAG: renamable $r6 = LWZ 0, %fixed-stack.0 :: (load 4 from %fixed-stack.0, align 8)
+; 64BIT-DAG: STD killed renamable $x11, 0, %stack.0.arg1 :: (store 8 into %ir.0)
+; 64BIT-DAG: STD killed renamable $x5, 0, %stack.0.arg1 :: (store 8 into %ir.arg1)
+; 64BIT-DAG: STD killed renamable $x7, 0, %stack.1.arg2 :: (store 8 into %ir.arg2)
+; 64BIT-DAG: renamable $r4 = LWZ 0, killed renamable $x4 :: (load 4)
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r6, renamable $r3, implicit killed $x3
+; 64BIT-DAG: renamable $r4 = RLWINM killed renamable $r4, 1, 0, 30
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4, implicit-def $x3
+; 64BIT-DAG: BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+; ASM64-LABEL:   .int_va_arg:
+; ASM64-DAG: std 4, 56(1)
+; ASM64-DAG: addi 4, 1, 56
+; ASM64-DAG: std 4, -16(1)
+; ASM64-DAG: std 4, -8(1)
+; ASM64-DAG: ld 4, -16(1)
+; ASM64-DAG: std 5, 64(1)
+; ASM64-DAG: addi 5, 1, 60
+; ASM64-DAG: std 5, -8(1)
+; ASM64-DAG: addi 5, 4, 4
+; ASM64-DAG: std 6, 72(1)
+; ASM64-DAG: std 7, 80(1)
+; ASM64-DAG: std 8

[PATCH] D76360: [PPC][AIX] Emit correct Vaarg for 32BIT-AIX in clang

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 255323.
ZarkoCA added a comment.

Rebase.


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Files:
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-vararg.c
  clang/test/CodeGen/aix32-dwarf-error.c

Index: clang/test/CodeGen/aix32-dwarf-error.c
===
--- /dev/null
+++ clang/test/CodeGen/aix32-dwarf-error.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify -emit-llvm %s
+
+static unsigned char dwarf_reg_size_table[1024];
+
+int test() {
+  __builtin_init_dwarf_reg_size_table(dwarf_reg_size_table); //expected-error {{cannot compile this __builtin_init_dwarf_reg_size_table yet}}
+  return __builtin_dwarf_sp_column();
+}
Index: clang/test/CodeGen/aix-vararg.c
===
--- /dev/null
+++ clang/test/CodeGen/aix-vararg.c
@@ -0,0 +1,39 @@
+// REQUIRES: powerpc-registered-target
+// REQUIRES: asserts
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -emit-llvm -o - %s | FileCheck %s --check-prefix=32BIT
+
+void aix_varg(int a, ...) {
+  __builtin_va_list arg;
+  __builtin_va_start(arg, a);
+  __builtin_va_list arg2;
+  __builtin_va_arg(arg, int);
+  __builtin_va_copy(arg2, arg);
+  __builtin_va_end(arg);
+  __builtin_va_end(arg2);
+}
+
+  // 32BIT:   define void @aix_varg(i32 %a, ...) #0 {
+  // 32BIT-NEXT:  entry:
+  // 32BIT-NEXT:%a.addr = alloca i32, align 4
+  // 32BIT-NEXT:%arg = alloca i8*, align 4
+  // 32BIT-NEXT:%arg2 = alloca i8*, align 4
+  // 32BIT-NEXT:store i32 %a, i32* %a.addr, align 4
+  // 32BIT-NEXT:%arg1 = bitcast i8** %arg to i8*
+  // 32BIT-NEXT:call void @llvm.va_start(i8* %arg1)
+  // 32BIT-NEXT:%argp.cur = load i8*, i8** %arg, align 4
+  // 32BIT-NEXT:%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
+  // 32BIT-NEXT:store i8* %argp.next, i8** %arg, align 4
+  // 32BIT-NEXT:%0 = bitcast i8* %argp.cur to i32*
+  // 32BIT-NEXT:%1 = load i32, i32* %0, align 4
+  // 32BIT-NEXT:%2 = bitcast i8** %arg2 to i8*
+  // 32BIT-NEXT:%3 = bitcast i8** %arg to i8*
+  // 32BIT-NEXT:call void @llvm.va_copy(i8* %2, i8* %3)
+  // 32BIT-NEXT:%arg3 = bitcast i8** %arg to i8*
+  // 32BIT-NEXT:call void @llvm.va_end(i8* %arg3)
+  // 32BIT-NEXT:%arg24 = bitcast i8** %arg2 to i8*
+  // 32BIT-NEXT:call void @llvm.va_end(i8* %arg24)
+  // 32BIT-NEXT:ret void
+  // 32BIT-NEXT:  }
+  // 32BIT: declare void @llvm.va_start(i8*) #1
+  // 32BIT: declare void @llvm.va_copy(i8*, i8*) #1
+  // 32BIT: declare void @llvm.va_end(i8*) #1
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -4173,14 +4173,15 @@
 
 // PowerPC-32
 namespace {
-/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
-class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
+/// PowerPC32ABIInfo - The 32-bit PowerPC ABI information, used by PowerPC ELF
+/// (SVR4), Darwin and AIX.
+class PowerPC32ABIInfo : public DefaultABIInfo {
   bool IsSoftFloatABI;
 
   CharUnits getParamTypeAlignment(QualType Ty) const;
 
 public:
-  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
+  PowerPC32ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
   : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
 
   Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
@@ -4190,7 +4191,7 @@
 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
 public:
   PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
-  : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
+  : TargetCodeGenInfo(new PowerPC32ABIInfo(CGT, SoftFloatABI)) {}
 
   int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
 // This is recovered from gcc output.
@@ -4200,9 +4201,22 @@
   bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
llvm::Value *Address) const override;
 };
+
+class PPCAIX32TargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  PPCAIX32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
+  : TargetCodeGenInfo(new PowerPC32ABIInfo(CGT, SoftFloatABI)) {}
+
+  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
+return 1; // r1 is the dedicated stack pointer
+  }
+
+  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
+   llvm::Value *Address) const override;
+};
 }
 
-CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
+CharUnits PowerPC32ABIInfo::getParamTypeAlignment(QualType Ty) const {
   // Complex types are passed just like their elements
   if (const ComplexType *CTy = Ty->getAs())
 Ty = CTy->getElementTy

[PATCH] D73290: [PowerPC] Add clang -msvr4-struct-return for 32-bit ELF

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added a comment.

@jhibbits is this patch going to be committed soon? I have a patch 
(https://reviews.llvm.org/D76360) that I will need to rebase once this is in.  
Thanks.


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[PATCH] D76360: [PPC][AIX] Emit correct Vaarg for 32BIT-AIX in clang

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 8 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:4205
+
+class PPCAIX32TargetCodeGenInfo : public TargetCodeGenInfo {
+public:

Xiangling_L wrote:
> sfertile wrote:
> > Xiangling_L wrote:
> > > I have a question here. AIX32 falls into PPC32 target, so why we don't 
> > > inherit from `PPC32TargetCodeGenInfo` instead?
> > Do we need a separate AIX specific class? We are implementing 2 functions, 
> > 1 of which is the same implementation as its `PPC32TargetCodeGenInfo` 
> > counterpart. If we have access to the triple, we can  return true when the 
> > OS is AIX in `PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable`. With the 
> > implementations being nearly identical (and after enabling 
> > DwarfEHRegSizeTable they will be identical) I think we are better to not 
> > add a new class if we can avoid it.
> Not adding a new class makes sense to me if we are sure that 
> `DwarfEHRegSizeTable` will be identical/viable for AIX.
I had an offline conversation with @sfertile, verified that the existing 
initDwarfEHRegSizeTable() function can work for AIX with minor changes.  

At first, I thought it may be useuful to create a stub class for for AIX at 
least. But I was able to access the AIX triple info through getABIInfo() and we 
can keep the one PPC32 class and diverge for AIX within the function when 
required. 



Comment at: clang/lib/CodeGen/TargetInfo.cpp:4210
+
+  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
+return 1; // r1 is the dedicated stack pointer

Xiangling_L wrote:
> Is `getDwarfEHStackPointer` necessary to be correct for vararg of AIX to 
> work[I guess possibly not]? If not, should it fall into Dwarf related patch 
> rather than in this one? BTW, if your `PPCAIX32TargetCodeGenInfo` inherits 
> from `PPC32TargetCodeGenInfo` instead as I mentioned above, then it would be 
> naturally correct.
It's not related to vaarg but the implementation is pretty simple so we might 
as well do it since we are here.  I also added a testcase with this enabled. 


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[PATCH] D76360: [PPC][AIX] Emit correct Vaarg for 32BIT-AIX in clang

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 256351.
ZarkoCA marked 2 inline comments as done.
ZarkoCA added a comment.

Rebased on https://reviews.llvm.org/D73290 and this patch now depends on it.
Removed PPCAIX32TargetCodegenClass from previous diff.
Corrected behaviour `PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable()` for 
32BIT AIX, and added the expected output to the test case which has also been 
renamed to reflect that.


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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-vararg.c
  clang/test/CodeGen/ppc64-aix32-dwarf.c
  clang/test/CodeGen/ppc64-dwarf.c

Index: clang/test/CodeGen/ppc64-dwarf.c
===
--- clang/test/CodeGen/ppc64-dwarf.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-static unsigned char dwarf_reg_size_table[1024];
-
-int test() {
-  __builtin_init_dwarf_reg_size_table(dwarf_reg_size_table);
-
-  return __builtin_dwarf_sp_column();
-}
-
-// CHECK-LABEL: define signext i32 @test()
-// CHECK:  store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 0), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 1), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 2), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 3), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 4), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 5), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 6), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 7), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 8), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 9), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 10), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 11), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 12), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 13), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 14), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 15), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 16), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 17), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 18), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 19), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 20), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 21), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 22), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 23), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 24), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 25), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 26), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 27), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 28), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i

[PATCH] D76360: [PPC][AIX] Emit correct Vaarg for 32BIT-AIX in clang

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 256398.
ZarkoCA edited the summary of this revision.
ZarkoCA added a comment.

Addressed comments
-added error for -msvr4-struct-return on AIX and modified appropriate test case
-changed code structure as per comment
-renamed test file


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76360/new/

https://reviews.llvm.org/D76360

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-vararg.c
  clang/test/CodeGen/ppc-dwarf.c
  clang/test/CodeGen/ppc32-struct-return.c
  clang/test/CodeGen/ppc64-dwarf.c

Index: clang/test/CodeGen/ppc64-dwarf.c
===
--- clang/test/CodeGen/ppc64-dwarf.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-static unsigned char dwarf_reg_size_table[1024];
-
-int test() {
-  __builtin_init_dwarf_reg_size_table(dwarf_reg_size_table);
-
-  return __builtin_dwarf_sp_column();
-}
-
-// CHECK-LABEL: define signext i32 @test()
-// CHECK:  store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 0), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 1), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 2), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 3), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 4), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 5), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 6), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 7), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 8), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 9), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 10), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 11), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 12), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 13), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 14), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 15), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 16), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 17), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 18), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 19), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 20), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 21), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 22), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 23), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 24), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 25), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 26), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 27), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 28), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 29), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds

[PATCH] D76360: [PPC][AIX] Emit correct Vaarg for 32BIT-AIX in clang

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked an inline comment as done.
ZarkoCA added inline comments.



Comment at: clang/test/CodeGen/ppc32-struct-return.c:53
+
+// AIX-SVR4: fatal error: error in backend: -msvr4-struct-return not supported 
on AIX
+ 

jasonliu wrote:
> jasonliu wrote:
> > sfertile wrote:
> > > jasonliu wrote:
> > > > If certain front end option is not supported on certain target, I think 
> > > > it makes more sense to have a standard diagnostic in the driver 
> > > > component, instead of "crash" in the backend. 
> > > > i.e. What if we specify this option on a Windows machine? Maybe we 
> > > > should pursue the same behavior. 
> > > Its not that we don't intend to support the option on AIX, but that 
> > > support for the option takes further verification on AIX.  Since there is 
> > > a difference how  AIX justifies subregister sized values in its argument 
> > > passing, we can't just assume that this option will pack the return 
> > > values the same way on AIX and Linux. 
> > > 
> > > The focus of this patch was originally to enable and verify the proper IR 
> > > generation of va-arg/va-lis/va-start, however the scope of the patch has 
> > > kept growing. If there are codegen differences in packing the return 
> > > register with the svr4-return option enabled it will grow this patch once 
> > > again. The fatal error lets us limit the scope of this patch, while not 
> > > silently emiting bad codegen if there is a difference in how gcc 
> > > initializes the return  registers. If during verification we decide we 
> > > don't want to support the option on AIX, then adopting  a standard 
> > > diagnostic in the driver component becomes the appropriate behavior. 
> > It wasn't clear for me from the code that this is not a permanent thing.  
> > In that case, does it make sense to leave a TODO here and say we need to 
> > re-evaluate this in the future to decide if we want to support it or not on 
> > AIX?
> > On another note, I'm not sure if this is really needed on AIX target 
> > though. But I guess we could discuss it down the road. 
> Just to avoid ambiguity, I meant I'm not sure if we really need this *option* 
> on AIX.
>The focus of this patch was originally to enable and verify the proper IR 
>generation of va-arg/va-lis/va-start, however the scope of the patch has kept 
>growing. If there are codegen differences in packing the return register with 
>the svr4-return option enabled it will grow this patch once again. The fatal 
>error lets us limit the scope of this patch, while not silently emiting bad 
>codegen if there is a difference in how gcc initializes the return registers. 
>If during verification we decide we don't want to support the option on AIX, 
>then adopting a standard diagnostic in the driver component becomes the 
>appropriate behavior.

@sfertile basically articulated my reasoning quite well here.  I just want to 
add, if verified to work on AIX, then we can simply remove the error in that 
one place and have the option working. 

GCC on AIX has those options and they work in the same way as described in 
https://reviews.llvm.org/D73290.  I think implementing a compatible GCC option 
in a fairly straightforward way doesn't hurt us.

I agree with your point made earlier, I will add a TODO to make it clearer that 
we need to completely verify the behaviour. 


Repository:
  rG LLVM Github Monorepo

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[PATCH] D76360: [PPC][AIX] Emit correct Vaarg for 32BIT-AIX in clang

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 258110.
ZarkoCA added a comment.

Added a TODO to remove the error for `msvr4-struct-return` on AIX when we 
verify it works as expected.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76360/new/

https://reviews.llvm.org/D76360

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-vararg.c
  clang/test/CodeGen/ppc-dwarf.c
  clang/test/CodeGen/ppc32-struct-return.c
  clang/test/CodeGen/ppc64-dwarf.c

Index: clang/test/CodeGen/ppc64-dwarf.c
===
--- clang/test/CodeGen/ppc64-dwarf.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-static unsigned char dwarf_reg_size_table[1024];
-
-int test() {
-  __builtin_init_dwarf_reg_size_table(dwarf_reg_size_table);
-
-  return __builtin_dwarf_sp_column();
-}
-
-// CHECK-LABEL: define signext i32 @test()
-// CHECK:  store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 0), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 1), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 2), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 3), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 4), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 5), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 6), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 7), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 8), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 9), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 10), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 11), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 12), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 13), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 14), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 15), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 16), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 17), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 18), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 19), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 20), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 21), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 22), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 23), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 24), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 25), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 26), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 27), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 28), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 29), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 30), align 1
-// CHECK-NEXT: store i

[PATCH] D76360: [PPC][AIX] Emit correct Vaarg for 32BIT-AIX in clang

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 261837.
ZarkoCA edited the summary of this revision.
ZarkoCA added a comment.

Rebased patch to include latest changes in trunk.  Removed that it depended on 
https://reviews.llvm.org/D73290 in the summary, as that patch has been landed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76360/new/

https://reviews.llvm.org/D76360

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-vararg.c
  clang/test/CodeGen/ppc-dwarf.c
  clang/test/CodeGen/ppc32-struct-return.c
  clang/test/CodeGen/ppc64-dwarf.c

Index: clang/test/CodeGen/ppc64-dwarf.c
===
--- clang/test/CodeGen/ppc64-dwarf.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-static unsigned char dwarf_reg_size_table[1024];
-
-int test() {
-  __builtin_init_dwarf_reg_size_table(dwarf_reg_size_table);
-
-  return __builtin_dwarf_sp_column();
-}
-
-// CHECK-LABEL: define signext i32 @test()
-// CHECK:  store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 0), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 1), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 2), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 3), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 4), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 5), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 6), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 7), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 8), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 9), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 10), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 11), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 12), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 13), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 14), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 15), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 16), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 17), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 18), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 19), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 20), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 21), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 22), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 23), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 24), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 25), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 26), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 27), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 28), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 29), align 1
-// CHECK-NEXT: store i8 8, i8* getelementptr inboun

[PATCH] D79035: [clang][AIX] Implement ABIInfo and TargetCodeGenInfo for AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:4368
+
+  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, TypeInfo,
+  SlotSize, /*AllowHigher*/ true);

Is there a reason why Indirect is set to `false` instead of querying for it 
using `classifyArgumentType(Ty).isIndirect()`?



Comment at: clang/lib/CodeGen/TargetInfo.cpp:4641
 return false;
   case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return
 return true;

Has this option been verified to work correctly on AIX? In 
https://reviews.llvm.org/D76360 we added a defensive error because we weren't 
sure whether padding was handled correctly as described in the code. 



Comment at: clang/lib/CodeGen/TargetInfo.cpp:4654
 llvm::Value *Address) const {
-  // This is calculated from the LLVM and GCC tables and verified
-  // against gcc output.  AFAIK all ABIs use the same encoding.
-
-  CodeGen::CGBuilderTy &Builder = CGF.Builder;
-
-  llvm::IntegerType *i8 = CGF.Int8Ty;
-  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
-  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
-  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
-
-  // 0-31: r0-31, the 4-byte general-purpose registers
-  AssignToArrayRange(Builder, Address, Four8, 0, 31);
-
-  // 32-63: fp0-31, the 8-byte floating-point registers
-  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
-
-  // 64-76 are various 4-byte special-purpose registers:
-  // 64: mq
-  // 65: lr
-  // 66: ctr
-  // 67: ap
-  // 68-75 cr0-7
-  // 76: xer
-  AssignToArrayRange(Builder, Address, Four8, 64, 76);
-
-  // 77-108: v0-31, the 16-byte vector registers
-  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
-
-  // 109: vrsave
-  // 110: vscr
-  // 111: spe_acc
-  // 112: spefscr
-  // 113: sfp
-  AssignToArrayRange(Builder, Address, Four8, 109, 113);
-
-  return false;
+  return PPC_initDwarfEHRegSizeTable(CGF, Address, /* Is64Bit*/ false,
+ /*IsAIX*/ false);

Should be changed to `/*Is64BIT*/`? Or you can add spaces to`/*IsAIX*/` so that 
it's consistent.  



Comment at: clang/lib/CodeGen/TargetInfo.cpp:5195
+  return PPC_initDwarfEHRegSizeTable(CGF, Address, /* Is64Bit*/ true,
+ /*IsAIX*/ false);
 }

Remove extra space from `/* Is64Bit*/`



Comment at: clang/lib/CodeGen/TargetInfo.cpp:10454
+if (Triple.isOSAIX())
+  return SetCGInfo(new AIXTargetCodeGenInfo(Types, /* Is64Bit */ false));
+

same as above about removing extra spaces. 



Comment at: clang/lib/CodeGen/TargetInfo.cpp:10465
+if (Triple.isOSAIX())
+  return SetCGInfo(new AIXTargetCodeGenInfo(Types, /* Is64Bit */ true));
+

spaces



Comment at: clang/test/CodeGen/aix-return.c:3
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefixes=AIX-COM,AIX32
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \

I think it would be simpler to just use `AIX` instead of `AIX-COM`.  



Comment at: clang/test/CodeGen/aix-struct-arg.c:3
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \

Same here, I think it be simpler to use either `CHECK` or `AIX`.  My preference 
is to use `CHECK` since other targets aren't being tested here but I would 
leave it up to you. 



Comment at: clang/test/CodeGen/aix-vaargs.c:3
+// REQUIRES: asserts
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -o - %s | FileCheck 
%s --check-prefixes=AIX-COM,AIX-M32
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm -o - %s | 
FileCheck %s --check-prefixes=AIX-COM,AIX-M64

jasonliu wrote:
> Xiangling_L wrote:
> > Consistent with other testcases to use `AIX32/AIX64`?
> I chose AIX-M32/AIX-M64 mainly because the length is the same as AIX-COM so 
> we don't need to worry about aligning the space. I would prefer to keep it 
> that.
I agree with Xiangling, it would be better to be consistent with the other 
testcases.  To get things to line up properly you can use `AIX32/AIX64` and 
`CHECK` instead of `AIX-COM`.


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[PATCH] D76360: [PPC][AIX] Emit correct Vaarg for 32BIT-AIX in clang

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA abandoned this revision.
ZarkoCA added a comment.

This work is included in https://reviews.llvm.org/D79035. Abandoning this 
revision.


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[PATCH] D74166: [AIX][Frontend] Static init implementation for AIX considering no priority

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/lib/CodeGen/CGDeclCXX.cpp:691
   AddGlobalDtor(Fn);
+  CXXGlobalDtors.clear();
 }

I may be missing something but why do we need this now, as opposed to not 
needing it before? Why didn't we need to clear the CXXGlobalDtors after 
emitting the function function before?



Comment at: clang/lib/CodeGen/ItaniumCXXABI.cpp:4442
+  if (D.getTLSKind() != VarDecl::TLS_None)
+llvm::report_fatal_error("Thread local storage unimplemented on AIX yet.");
+

Style guide now says no capitalization and no punctuation at the end for 
`report_fatal_error` messages.  


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[PATCH] D79035: [clang][AIX] Implement ABIInfo and TargetCodeGenInfo for AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:4257
+  // 64-bit only registers:
+  // 114: tfhar
+  // 115: tfiar

From what I've seen, the tfhar, tfiar and texasr are used by the Power8 CPU, 
which means that there is potential for them to be used on 64BIT AIX.  I don't 
have access to a Power8 AIX machine to test and confirm this however.  If no 
one else can confirm, maybe it's good to leave a TODO here to check?



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4541
options::OPT_msvr4_struct_return)) {
-if (TC.getArch() != llvm::Triple::ppc) {
+if (TC.getArch() != llvm::Triple::ppc || TC.getTriple().isOSAIX()) {
   D.Diag(diag::err_drv_unsupported_opt_for_target)

-maix-struct-return behaves as expected on AIX (ie. it has no change from 
default behaviour) but I agree, to me it makes disable both if we are not sure 
about one of them.  However, I think it would be good to add a TODO to enable 
this once it's verified on AIX.  



Comment at: clang/test/CodeGen/ppc32-and-aix-struct-return.c:55
+// CHECK-AIX-LABEL: define void @ret0(%struct.Zero* noalias sret {{[^,]*}})
+// CHECK-SVR4-LABEL: define void @ret0()
+Zero ret0(void) { return (Zero){}; }

sorry, is it possible to lineup the `define ..` with the line below, for the 
entire testcase?


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[PATCH] D79035: [clang][AIX] Implement ABIInfo and TargetCodeGenInfo for AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:5244
 llvm::Value *Address) const {
-
-  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
+  return PPC_initDwarfEHRegSizeTable(CGF, Address, /* Is64Bit*/ true,
+ /*IsAIX*/ false);

Missed to point out the extra space in `/* Is64Bit*/` previously. 



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4541
options::OPT_msvr4_struct_return)) {
-if (TC.getArch() != llvm::Triple::ppc) {
+// TODO: We might want to consider enable these two options on AIX in the
+// future.

s/enable/enabling/


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[PATCH] D79035: [clang][AIX] Implement ABIInfo and TargetCodeGenInfo for AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added a comment.

I'm ok with this now. I will let @Xiangling_L approve if she's ok with it since 
she had the last few comments.


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[PATCH] D105660: [PowerPC][AIX] Add warning when alignment is incompatible with XL

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 358934.
ZarkoCA added a comment.

- Fix formatting in test case
- Reword warning message


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Files:
  clang/include/clang/Basic/DiagnosticGroups.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Sema/aix-attr-align.c


Index: clang/test/Sema/aix-attr-align.c
===
--- /dev/null
+++ clang/test/Sema/aix-attr-align.c
@@ -0,0 +1,22 @@
+// off-no-diagnostics
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify=off -Wno-aix-compat 
-fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify=off -Wno-aix-compat 
-fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only 
%s
+
+struct S {
+  int a[8] __attribute__((aligned(8))); // no-warning
+};
+
+struct T {
+  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an 
alignment of 16 bytes or greater for struct members is not binary compatible 
with AIX XL 16.1 and older}}
+};
+
+struct U {
+  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an 
alignment of 16 bytes or greater for struct members is not binary compatible 
with AIX XL 16.1 and older}}
+};
+
+int a[8] __attribute__((aligned(8)));  // no-warning
+int b[4] __attribute__((aligned(16))); // no-warning
+int c[2] __attribute__((aligned(32))); // no-warning
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -3953,6 +3953,12 @@
 return;
 
   uint64_t AlignVal = Alignment.getZExtValue();
+  // 16 byte ByVal alignment not due to a vector member is not honoured by XL
+  // on AIX. Emit a warning here that users are generating binary incompatible
+  // code to be safe.
+  if (AlignVal >= 16 && isa(D) &&
+  Context.getTargetInfo().getTriple().isOSAIX())
+Diag(AttrLoc, diag::warn_not_xl_compatible) << E->getSourceRange();
 
   // C++11 [dcl.align]p2:
   //   -- if the constant expression evaluates to zero, the alignment
Index: clang/include/clang/Basic/DiagnosticSemaKinds.td
===
--- clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -3254,6 +3254,10 @@
 : Warning<"requested alignment must be %0 bytes or smaller; maximum "
   "alignment assumed">,
   InGroup>;
+def warn_not_xl_compatible
+: Warning<"requesting an alignment of 16 bytes or greater for struct"
+  " members is not binary compatible with AIX XL 16.1 and older">,
+  InGroup;
 def warn_redeclaration_without_attribute_prev_attribute_ignored : Warning<
   "%q0 redeclared without %1 attribute: previous %1 ignored">,
   InGroup;
Index: clang/include/clang/Basic/DiagnosticGroups.td
===
--- clang/include/clang/Basic/DiagnosticGroups.td
+++ clang/include/clang/Basic/DiagnosticGroups.td
@@ -1083,6 +1083,9 @@
 // A warning group for warnings about code that clang accepts but gcc doesn't.
 def GccCompat : DiagGroup<"gcc-compat">;
 
+// A warning group for warnings about code that may be incompatible on AIX.
+def AIXCompat : DiagGroup<"aix-compat">;
+
 // Warnings for Microsoft extensions.
 def MicrosoftCharize : DiagGroup<"microsoft-charize">;
 def MicrosoftDrectveSection : DiagGroup<"microsoft-drectve-section">;


Index: clang/test/Sema/aix-attr-align.c
===
--- /dev/null
+++ clang/test/Sema/aix-attr-align.c
@@ -0,0 +1,22 @@
+// off-no-diagnostics
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify=off -Wno-aix-compat -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify=off -Wno-aix-compat -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only %s
+
+struct S {
+  int a[8] __attribute__((aligned(8))); // no-warning
+};
+
+struct T {
+  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with AIX XL 16.1 and older}}
+};
+
+struct U {
+  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with AIX XL 16.1 and older}}
+};
+
+int a[8] __attribute__((aligned(8)));  // no-warning
+int b[4] __attribute

[PATCH] D105660: [PowerPC][AIX] Add warning when alignment is incompatible with XL

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 2 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:3255-3256
+def warn_not_xl_compatible
+: Warning<"requested alignment of arguments 16 bytes or greater is not"
+  " compatible with previous versions of the AIX XL compiler">,
+  InGroup>;

aaron.ballman wrote:
> ZarkoCA wrote:
> > aaron.ballman wrote:
> > > ZarkoCA wrote:
> > > > aaron.ballman wrote:
> > > > > Should we be talking about the AIX XL compiler in a Clang diagnostic?
> > > > I see your point. Sorry if this isn't what is supposed to be done or if 
> > > > it doesn't a good precedent.
> > > > 
> > > > The reasons for adding this warning is that our back end implementation 
> > > > isn't totally compatible with XL now and, while buggy, users on AIX may 
> > > > expect clang and xlclang to be compatible since AIX is the reference 
> > > > compiler.  The xlclang name implies it's clang based and it's possible 
> > > > for users to expect some sort of binary compatibility.
> > > > 
> > > > I see your point. Sorry if this isn't what is supposed to be done or if 
> > > > it doesn't a good precedent.
> > > 
> > > No worries, it's a good discussion to have! We have some MSVC and GCC 
> > > compatibility warnings, so there's precedent for naming other compilers. 
> > > Now that you've moved the diagnostic into an AIX compatibility diagnostic 
> > > group, I am more comfortable with it. Thanks!
> > Thanks, glad it's better now. 
> I missed this last time, sorry, but is "arguments" actually necessary for the 
> diagnostic or can that be dropped?
It actually isn't correct, the warning should apply only to members of structs. 
 Thanks for bringing it to my attention again, I also missed this the last 
time. 


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[PATCH] D105660: [PowerPC][AIX] Add warning when alignment is incompatible with XL

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:3255-3256
+def warn_not_xl_compatible
+: Warning<"requested alignment of arguments 16 bytes or greater is not"
+  " compatible with previous versions of the AIX XL compiler">,
+  InGroup>;

aaron.ballman wrote:
> ZarkoCA wrote:
> > aaron.ballman wrote:
> > > ZarkoCA wrote:
> > > > aaron.ballman wrote:
> > > > > ZarkoCA wrote:
> > > > > > aaron.ballman wrote:
> > > > > > > Should we be talking about the AIX XL compiler in a Clang 
> > > > > > > diagnostic?
> > > > > > I see your point. Sorry if this isn't what is supposed to be done 
> > > > > > or if it doesn't a good precedent.
> > > > > > 
> > > > > > The reasons for adding this warning is that our back end 
> > > > > > implementation isn't totally compatible with XL now and, while 
> > > > > > buggy, users on AIX may expect clang and xlclang to be compatible 
> > > > > > since AIX is the reference compiler.  The xlclang name implies it's 
> > > > > > clang based and it's possible for users to expect some sort of 
> > > > > > binary compatibility.
> > > > > > 
> > > > > > I see your point. Sorry if this isn't what is supposed to be done 
> > > > > > or if it doesn't a good precedent.
> > > > > 
> > > > > No worries, it's a good discussion to have! We have some MSVC and GCC 
> > > > > compatibility warnings, so there's precedent for naming other 
> > > > > compilers. Now that you've moved the diagnostic into an AIX 
> > > > > compatibility diagnostic group, I am more comfortable with it. Thanks!
> > > > Thanks, glad it's better now. 
> > > I missed this last time, sorry, but is "arguments" actually necessary for 
> > > the diagnostic or can that be dropped?
> > It actually isn't correct, the warning should apply only to members of 
> > structs.  Thanks for bringing it to my attention again, I also missed this 
> > the last time. 
> Huttah for code review working as intended! :-)
Indeed, thank you for the timely reviews. 


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[PATCH] D105660: [PowerPC][AIX] Add warning when alignment is incompatible with XL

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG66225db98d83: [PowerPC][AIX] Add warning when alignment is 
incompatible with XL (authored by ZarkoCA).

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Files:
  clang/include/clang/Basic/DiagnosticGroups.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Sema/aix-attr-align.c


Index: clang/test/Sema/aix-attr-align.c
===
--- /dev/null
+++ clang/test/Sema/aix-attr-align.c
@@ -0,0 +1,22 @@
+// off-no-diagnostics
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify=off -Wno-aix-compat 
-fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify=off -Wno-aix-compat 
-fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only 
%s
+
+struct S {
+  int a[8] __attribute__((aligned(8))); // no-warning
+};
+
+struct T {
+  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an 
alignment of 16 bytes or greater for struct members is not binary compatible 
with AIX XL 16.1 and older}}
+};
+
+struct U {
+  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an 
alignment of 16 bytes or greater for struct members is not binary compatible 
with AIX XL 16.1 and older}}
+};
+
+int a[8] __attribute__((aligned(8)));  // no-warning
+int b[4] __attribute__((aligned(16))); // no-warning
+int c[2] __attribute__((aligned(32))); // no-warning
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -3953,6 +3953,12 @@
 return;
 
   uint64_t AlignVal = Alignment.getZExtValue();
+  // 16 byte ByVal alignment not due to a vector member is not honoured by XL
+  // on AIX. Emit a warning here that users are generating binary incompatible
+  // code to be safe.
+  if (AlignVal >= 16 && isa(D) &&
+  Context.getTargetInfo().getTriple().isOSAIX())
+Diag(AttrLoc, diag::warn_not_xl_compatible) << E->getSourceRange();
 
   // C++11 [dcl.align]p2:
   //   -- if the constant expression evaluates to zero, the alignment
Index: clang/include/clang/Basic/DiagnosticSemaKinds.td
===
--- clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -3254,6 +3254,10 @@
 : Warning<"requested alignment must be %0 bytes or smaller; maximum "
   "alignment assumed">,
   InGroup>;
+def warn_not_xl_compatible
+: Warning<"requesting an alignment of 16 bytes or greater for struct"
+  " members is not binary compatible with AIX XL 16.1 and older">,
+  InGroup;
 def warn_redeclaration_without_attribute_prev_attribute_ignored : Warning<
   "%q0 redeclared without %1 attribute: previous %1 ignored">,
   InGroup;
Index: clang/include/clang/Basic/DiagnosticGroups.td
===
--- clang/include/clang/Basic/DiagnosticGroups.td
+++ clang/include/clang/Basic/DiagnosticGroups.td
@@ -1083,6 +1083,9 @@
 // A warning group for warnings about code that clang accepts but gcc doesn't.
 def GccCompat : DiagGroup<"gcc-compat">;
 
+// A warning group for warnings about code that may be incompatible on AIX.
+def AIXCompat : DiagGroup<"aix-compat">;
+
 // Warnings for Microsoft extensions.
 def MicrosoftCharize : DiagGroup<"microsoft-charize">;
 def MicrosoftDrectveSection : DiagGroup<"microsoft-drectve-section">;


Index: clang/test/Sema/aix-attr-align.c
===
--- /dev/null
+++ clang/test/Sema/aix-attr-align.c
@@ -0,0 +1,22 @@
+// off-no-diagnostics
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify=off -Wno-aix-compat -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify=off -Wno-aix-compat -fsyntax-only %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only %s
+
+struct S {
+  int a[8] __attribute__((aligned(8))); // no-warning
+};
+
+struct T {
+  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with AIX XL 16.1 and older}}
+};
+
+struct U {
+  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not bin

[PATCH] D106393: [PowerPC][AIX] Add support for varargs for complex types on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA created this revision.
ZarkoCA added reviewers: cebowleratibm, sfertile, PowerPC.
Herald added subscribers: shchenz, kbarton, nemanjai.
ZarkoCA requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Remove the previous error and add support for special handling of small
complex types as in PPC64 ELF ABI. As in, generate code to load from
varargs location and pack it in a temp variable, then return a pointer to
the struct.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106393

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix32-complex-varargs.c
  clang/test/CodeGen/ppc64-varargs-complex.c
  llvm/test/CodeGen/PowerPC/aix32-complex-vararg.ll
  llvm/test/CodeGen/PowerPC/aix64-complex-vararg.ll

Index: llvm/test/CodeGen/PowerPC/aix64-complex-vararg.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix64-complex-vararg.ll
@@ -0,0 +1,510 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
+; RUN:  -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefix=64BIT %s
+
+@cdbl = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cdbl1 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cdbl2 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cdbl3 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cflt = local_unnamed_addr global { float, float } zeroinitializer, align 4
+@cflt1 = local_unnamed_addr global { float, float } zeroinitializer, align 4
+@cflt2 = local_unnamed_addr global { float, float } zeroinitializer, align 4
+@cflt3 = local_unnamed_addr global { float, float } zeroinitializer, align 4
+@cldbl = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cldbl1 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cldbl2 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cldbl3 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+
+define { double, double } @foo1(double %x.coerce0, double %x.coerce1, ...) local_unnamed_addr {
+; 64BIT-LABEL: foo1:
+; 64BIT:   # %bb.0: # %entry
+; 64BIT-NEXT:ld 3, L..C0(2) # %const.0
+; 64BIT-NEXT:std 5, 64(1)
+; 64BIT-NEXT:std 6, 72(1)
+; 64BIT-NEXT:lfd 4, 64(1)
+; 64BIT-NEXT:lfd 5, 72(1)
+; 64BIT-NEXT:std 7, 80(1)
+; 64BIT-NEXT:std 8, 88(1)
+; 64BIT-NEXT:lfs 0, 0(3)
+; 64BIT-NEXT:std 9, 96(1)
+; 64BIT-NEXT:addi 3, 1, 64
+; 64BIT-NEXT:std 10, 104(1)
+; 64BIT-NEXT:fadd 3, 1, 0
+; 64BIT-NEXT:fadd 0, 2, 0
+; 64BIT-NEXT:fadd 3, 3, 4
+; 64BIT-NEXT:fadd 0, 0, 5
+; 64BIT-NEXT:lfdu 4, 16(3)
+; 64BIT-NEXT:lfd 5, 88(1)
+; 64BIT-NEXT:fadd 3, 3, 1
+; 64BIT-NEXT:fadd 0, 0, 2
+; 64BIT-NEXT:fadd 3, 3, 4
+; 64BIT-NEXT:fadd 0, 0, 5
+; 64BIT-NEXT:lfd 4, 96(1)
+; 64BIT-NEXT:lfd 5, 104(1)
+; 64BIT-NEXT:fadd 3, 3, 1
+; 64BIT-NEXT:fadd 0, 0, 2
+; 64BIT-NEXT:fadd 3, 3, 4
+; 64BIT-NEXT:fadd 0, 0, 5
+; 64BIT-NEXT:lfd 4, 112(1)
+; 64BIT-NEXT:lfd 5, 120(1)
+; 64BIT-NEXT:fadd 3, 3, 1
+; 64BIT-NEXT:fadd 0, 0, 2
+; 64BIT-NEXT:fadd 3, 3, 4
+; 64BIT-NEXT:fadd 0, 0, 5
+; 64BIT-NEXT:fadd 1, 3, 1
+; 64BIT-NEXT:fadd 0, 0, 2
+; 64BIT-NEXT:lfd 2, 128(1)
+; 64BIT-NEXT:lfd 3, 136(1)
+; 64BIT-NEXT:fadd 1, 1, 2
+; 64BIT-NEXT:fadd 2, 0, 3
+; 64BIT-NEXT:blr
+entry:
+  %arg = alloca i8*, align 8
+  %0 = bitcast i8** %arg to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  call void @llvm.va_start(i8* nonnull %0)
+  %add.r = fadd double %x.coerce0, 0.00e+00
+  %add.i = fadd double %x.coerce1, 0.00e+00
+  %argp.cur = load i8*, i8** %arg, align 8
+  %argp.next = getelementptr inbounds i8, i8* %argp.cur, i64 16
+  store i8* %argp.next, i8** %arg, align 8
+  %.realp = bitcast i8* %argp.cur to double*
+  %.real = load double, double* %.realp, align 8
+  %.imagp = getelementptr inbounds i8, i8* %argp.cur, i64 8
+  %1 = bitcast i8* %.imagp to double*
+  %.imag = load double, double* %1, align 8
+  %add.r4 = fadd double %add.r, %.real
+  %add.i5 = fadd double %add.i, %.imag
+  %add.r.1 = fadd double %add.r4, %x.coerce0
+  %add.i.1 = fadd double %add.i5, %x.coerce1
+  %argp.next.1 = getelementptr inbounds i8, i8* %argp.cur, i64 32
+  %.realp.1 = bitcast i8* %argp.next to double*
+  %.real.1 = load double, double* %.realp.1, align 8
+  %.imagp.1 = getelementptr inbounds i8, i8* %argp.cur, i64 24
+  %2 = bitcast i8* %.imagp.1 to double*
+  %.imag.1 = load double, double* %2, align 8
+  %add.r4.1 = fadd double %add.r.1, %.real.1
+  %add.i5.1 = fadd double %add.i.1, %.imag.1
+  %add.r.2 = fadd double %add.r4.1, %x.coerce0
+  %add.i.2 = fadd double %add.i5.1, %x.coerce1
+  %argp.next.2 = getele

[PATCH] D106409: [PowerPC] Add diagnostic for out of range values for vec_cts,vec_ctf

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA created this revision.
ZarkoCA added reviewers: bmahjour, nemanjai, jsji, PowerPC.
Herald added subscribers: shchenz, kbarton.
ZarkoCA requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

LLVM (llc) will crash when a user specifies a number out of the allowed range 
(0-31) for b.
This patch provides a clang diagnostic so we error out gracefully and point out 
the user error.

Further documentation for the builtins can be found here:
https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.0?topic=functions-vec-ctf
https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.0?topic=functions-vec-cts


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106409

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-error.c


Index: clang/test/CodeGen/builtins-ppc-error.c
===
--- clang/test/CodeGen/builtins-ppc-error.c
+++ clang/test/CodeGen/builtins-ppc-error.c
@@ -50,6 +50,7 @@
 void testCTF(int index) {
   vec_ctf(vsi, index); //expected-error {{argument to 
'__builtin_altivec_vcfsx' must be a constant integer}} expected-error 
{{argument to '__builtin_altivec_vcfux' must be a constant integer}}
   vec_ctf(vui, index); //expected-error {{argument to 
'__builtin_altivec_vcfsx' must be a constant integer}} expected-error 
{{argument to '__builtin_altivec_vcfux' must be a constant integer}}
+  vec_ctf(vsi, 32); //expected-error 1+ {{argument value 32 is outside the 
valid range [0, 31]}}
 }
 
 void testVCFSX(int index) {
@@ -62,7 +63,7 @@
 
 void testCTS(int index) {
   vec_cts(vf, index); //expected-error {{argument to 
'__builtin_altivec_vctsxs' must be a constant integer}}
-
+  vec_cts(vf, 32);//expected-error {{argument value 32 is outside the 
valid range [0, 31]}}
 }
 
 void testVCTSXS(int index) {
@@ -71,7 +72,7 @@
 
 void testCTU(int index) {
   vec_ctu(vf, index); //expected-error {{argument to 
'__builtin_altivec_vctuxs' must be a constant integer}}
-
+  vec_ctu(vf, 32);//expected-error {{argument value 32 is outside the 
valid range [0, 31]}}
 }
 
 void testVCTUXS(int index) {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3351,6 +3351,11 @@
   case PPC::BI__builtin_tabortdci:
 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) ||
SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+  case PPC::BI__builtin_altivec_vctsxs:
+  case PPC::BI__builtin_altivec_vctuxs:
+  case PPC::BI__builtin_altivec_vcfsx:
+  case PPC::BI__builtin_altivec_vcfux:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
   case PPC::BI__builtin_altivec_dst:
   case PPC::BI__builtin_altivec_dstt:
   case PPC::BI__builtin_altivec_dstst:


Index: clang/test/CodeGen/builtins-ppc-error.c
===
--- clang/test/CodeGen/builtins-ppc-error.c
+++ clang/test/CodeGen/builtins-ppc-error.c
@@ -50,6 +50,7 @@
 void testCTF(int index) {
   vec_ctf(vsi, index); //expected-error {{argument to '__builtin_altivec_vcfsx' must be a constant integer}} expected-error {{argument to '__builtin_altivec_vcfux' must be a constant integer}}
   vec_ctf(vui, index); //expected-error {{argument to '__builtin_altivec_vcfsx' must be a constant integer}} expected-error {{argument to '__builtin_altivec_vcfux' must be a constant integer}}
+  vec_ctf(vsi, 32); //expected-error 1+ {{argument value 32 is outside the valid range [0, 31]}}
 }
 
 void testVCFSX(int index) {
@@ -62,7 +63,7 @@
 
 void testCTS(int index) {
   vec_cts(vf, index); //expected-error {{argument to '__builtin_altivec_vctsxs' must be a constant integer}}
-
+  vec_cts(vf, 32);//expected-error {{argument value 32 is outside the valid range [0, 31]}}
 }
 
 void testVCTSXS(int index) {
@@ -71,7 +72,7 @@
 
 void testCTU(int index) {
   vec_ctu(vf, index); //expected-error {{argument to '__builtin_altivec_vctuxs' must be a constant integer}}
-
+  vec_ctu(vf, 32);//expected-error {{argument value 32 is outside the valid range [0, 31]}}
 }
 
 void testVCTUXS(int index) {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3351,6 +3351,11 @@
   case PPC::BI__builtin_tabortdci:
 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) ||
SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+  case PPC::BI__builtin_altivec_vctsxs:
+  case PPC::BI__builtin_altivec_vctuxs:
+  case PPC::BI__builtin_altivec_vcfsx:
+  case PPC::BI__builtin_altivec_vcfux:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
   case PPC::BI__builtin_altivec_dst:
   case PPC::BI__builtin_altivec_dstt:
   case PPC::BI__builtin_altivec_dstst:
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[PATCH] D106393: [PowerPC][AIX] Add support for varargs for complex types on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 360535.
ZarkoCA added a comment.

- Fix comment to also describe what happens in 32bit mode


Repository:
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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix32-complex-varargs.c
  clang/test/CodeGen/ppc64-varargs-complex.c
  llvm/test/CodeGen/PowerPC/aix32-complex-vararg.ll
  llvm/test/CodeGen/PowerPC/aix64-complex-vararg.ll

Index: llvm/test/CodeGen/PowerPC/aix64-complex-vararg.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix64-complex-vararg.ll
@@ -0,0 +1,510 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
+; RUN:  -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefix=64BIT %s
+
+@cdbl = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cdbl1 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cdbl2 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cdbl3 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cflt = local_unnamed_addr global { float, float } zeroinitializer, align 4
+@cflt1 = local_unnamed_addr global { float, float } zeroinitializer, align 4
+@cflt2 = local_unnamed_addr global { float, float } zeroinitializer, align 4
+@cflt3 = local_unnamed_addr global { float, float } zeroinitializer, align 4
+@cldbl = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cldbl1 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cldbl2 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+@cldbl3 = local_unnamed_addr global { double, double } zeroinitializer, align 8
+
+define { double, double } @foo1(double %x.coerce0, double %x.coerce1, ...) local_unnamed_addr {
+; 64BIT-LABEL: foo1:
+; 64BIT:   # %bb.0: # %entry
+; 64BIT-NEXT:ld 3, L..C0(2) # %const.0
+; 64BIT-NEXT:std 5, 64(1)
+; 64BIT-NEXT:std 6, 72(1)
+; 64BIT-NEXT:lfd 4, 64(1)
+; 64BIT-NEXT:lfd 5, 72(1)
+; 64BIT-NEXT:std 7, 80(1)
+; 64BIT-NEXT:std 8, 88(1)
+; 64BIT-NEXT:lfs 0, 0(3)
+; 64BIT-NEXT:std 9, 96(1)
+; 64BIT-NEXT:addi 3, 1, 64
+; 64BIT-NEXT:std 10, 104(1)
+; 64BIT-NEXT:fadd 3, 1, 0
+; 64BIT-NEXT:fadd 0, 2, 0
+; 64BIT-NEXT:fadd 3, 3, 4
+; 64BIT-NEXT:fadd 0, 0, 5
+; 64BIT-NEXT:lfdu 4, 16(3)
+; 64BIT-NEXT:lfd 5, 88(1)
+; 64BIT-NEXT:fadd 3, 3, 1
+; 64BIT-NEXT:fadd 0, 0, 2
+; 64BIT-NEXT:fadd 3, 3, 4
+; 64BIT-NEXT:fadd 0, 0, 5
+; 64BIT-NEXT:lfd 4, 96(1)
+; 64BIT-NEXT:lfd 5, 104(1)
+; 64BIT-NEXT:fadd 3, 3, 1
+; 64BIT-NEXT:fadd 0, 0, 2
+; 64BIT-NEXT:fadd 3, 3, 4
+; 64BIT-NEXT:fadd 0, 0, 5
+; 64BIT-NEXT:lfd 4, 112(1)
+; 64BIT-NEXT:lfd 5, 120(1)
+; 64BIT-NEXT:fadd 3, 3, 1
+; 64BIT-NEXT:fadd 0, 0, 2
+; 64BIT-NEXT:fadd 3, 3, 4
+; 64BIT-NEXT:fadd 0, 0, 5
+; 64BIT-NEXT:fadd 1, 3, 1
+; 64BIT-NEXT:fadd 0, 0, 2
+; 64BIT-NEXT:lfd 2, 128(1)
+; 64BIT-NEXT:lfd 3, 136(1)
+; 64BIT-NEXT:fadd 1, 1, 2
+; 64BIT-NEXT:fadd 2, 0, 3
+; 64BIT-NEXT:blr
+entry:
+  %arg = alloca i8*, align 8
+  %0 = bitcast i8** %arg to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  call void @llvm.va_start(i8* nonnull %0)
+  %add.r = fadd double %x.coerce0, 0.00e+00
+  %add.i = fadd double %x.coerce1, 0.00e+00
+  %argp.cur = load i8*, i8** %arg, align 8
+  %argp.next = getelementptr inbounds i8, i8* %argp.cur, i64 16
+  store i8* %argp.next, i8** %arg, align 8
+  %.realp = bitcast i8* %argp.cur to double*
+  %.real = load double, double* %.realp, align 8
+  %.imagp = getelementptr inbounds i8, i8* %argp.cur, i64 8
+  %1 = bitcast i8* %.imagp to double*
+  %.imag = load double, double* %1, align 8
+  %add.r4 = fadd double %add.r, %.real
+  %add.i5 = fadd double %add.i, %.imag
+  %add.r.1 = fadd double %add.r4, %x.coerce0
+  %add.i.1 = fadd double %add.i5, %x.coerce1
+  %argp.next.1 = getelementptr inbounds i8, i8* %argp.cur, i64 32
+  %.realp.1 = bitcast i8* %argp.next to double*
+  %.real.1 = load double, double* %.realp.1, align 8
+  %.imagp.1 = getelementptr inbounds i8, i8* %argp.cur, i64 24
+  %2 = bitcast i8* %.imagp.1 to double*
+  %.imag.1 = load double, double* %2, align 8
+  %add.r4.1 = fadd double %add.r.1, %.real.1
+  %add.i5.1 = fadd double %add.i.1, %.imag.1
+  %add.r.2 = fadd double %add.r4.1, %x.coerce0
+  %add.i.2 = fadd double %add.i5.1, %x.coerce1
+  %argp.next.2 = getelementptr inbounds i8, i8* %argp.cur, i64 48
+  %.realp.2 = bitcast i8* %argp.next.1 to double*
+  %.real.2 = load double, double* %.realp.2, align 8
+  %.imagp.2 = getelementptr inbounds i8, i8* %argp.cur, i64 40
+  %3 = bitcast i8* %.imagp.2 to double*
+  %.imag.2 = load double, double* %3, align 8
+  %add

[PATCH] D106393: [PowerPC][AIX] Add support for varargs for complex types on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:4577-4583
+  // If we have a complex type and the base type is smaller than 8 bytes,
+  // the ABI calls for the real and imaginary parts to be right-adjusted
+  // in separate doublewords. However, Clang expects us to produce a
+  // pointer to a structure with the two parts packed tightly. So generate
+  // loads of the real and imaginary parts relative to the va_list pointer,
+  // and store them to a temporary structure. We do the same as the PPC64ABI
+  // here.

hubert.reinterpretcast wrote:
> The 32-bit tests suggest that the "8 bytes"/"doublewords" in the above are 
> not always so.
Yes, I missed updating that part of the comment previously, thank you.


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[PATCH] D106688: [AIX] Pass the -b option to linker on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/lib/Driver/ToolChains/CommonArgs.cpp:262-269
+  if (T.isOSAIX()) {
+// Pass -b prefix for AIX linker.
+A.claim();
+A.render(Args, CmdArgs);
+continue;
+  } else {
+TC.getDriver().Diag(diag::err_drv_unsupported_opt)

Can this be reversed so the error check is first for `(!T.isOSAIX())` instead? 
Then you don't need the `else`. 



Comment at: clang/test/Driver/Xlinker-args.c:15-16
+
+// RUN: %clang -target powerpc-unknown-aix -### \
+// RUN:   -b one %s 2> %t
+// RUN: FileCheck -check-prefix=AIX < %t %s

Does this mean that we need space between `-b` and the linker option when using 
clang normally? Or this an artifact of the way we need to write tests? 


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[PATCH] D106688: [AIX] Pass the -b option to linker on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA accepted this revision.
ZarkoCA added a comment.
This revision is now accepted and ready to land.

LGTM with small nit, thanks.




Comment at: clang/lib/Driver/ToolChains/CommonArgs.cpp:263
+  if (!T.isOSAIX()) {
+TC.getDriver().Diag(diag::err_drv_unsupported_opt)
+<< A.getAsString(Args);

nit, I prefer this error message but it's up to you. 


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[PATCH] D106688: [AIX] Pass the -b option to linker on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/lib/Driver/ToolChains/CommonArgs.cpp:263
+  if (!T.isOSAIX()) {
+TC.getDriver().Diag(diag::err_drv_unsupported_opt)
+<< A.getAsString(Args);

anjankgk wrote:
> ZarkoCA wrote:
> > nit, I prefer this error message but it's up to you. 
> I intentionally chose that error msg (without target mention) since that's 
> the one the original option threw (existing '-b' option which was defined as 
> unsupported for all the platforms).
I see, that makes sense.

But now with your patch this option is supported even if only for the AIX 
target. So we could make the case to use the suggested error message. That 
said, I am still fine with what you choose. 


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[PATCH] D107063: Set TargetCPUName for AIX to default to pwr7.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added a comment.

Thanks @jamieschmeiser this change LGTM but I'll defer to 
@hubert.reinterpretcast for final approval.


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[PATCH] D107105: [AIX] Pass the -b option to linker on AIX (with fix to build break)

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added a comment.

Thanks for the quick turn around and fix @anjankgk, LGTM.


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[PATCH] D106900: [PowerPC][AIX] Packed zero-width bitfields do not affect alignment.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA accepted this revision.
ZarkoCA added a comment.

LGTM also. Just a comment typo.




Comment at: clang/lib/AST/RecordLayoutBuilder.cpp:1779
+  // On AIX, zero-width bitfields pad out to the natural alignment boundary,
+  // but dont increase the alignment greater than the MaxFieldAlignment, or 1
+  // if packed.





Comment at: clang/lib/AST/RecordLayoutBuilder.cpp:1779
+  // On AIX, zero-width bitfields pad out to the natural alignment boundary,
+  // but dont increase the alignment greater than the MaxFieldAlignment, or 1
+  // if packed.

ZarkoCA wrote:
> 



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[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 406086.
ZarkoCA added a comment.

- Moved AIX check to its own function to hopefully avoid Arg and ArgTy getting 
out of sync
- Rebased and removed LIT test cases workaround


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Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Analysis/padding_c.c
  clang/test/Analysis/padding_cpp.cpp
  clang/test/CXX/drs/dr6xx.cpp
  clang/test/Sema/aix-attr-align.c
  clang/test/SemaTemplate/instantiate-attr.cpp

Index: clang/test/SemaTemplate/instantiate-attr.cpp
===
--- clang/test/SemaTemplate/instantiate-attr.cpp
+++ clang/test/SemaTemplate/instantiate-attr.cpp
@@ -1,7 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-
-// RUN: %clang_cc1 -fsyntax-only -verify -Wno-aix-compat %s
+// RUN: %clang_cc1 -fsyntax-only -verify %s
 // expected-no-diagnostics
 template 
 struct A {
Index: clang/test/Sema/aix-attr-align.c
===
--- clang/test/Sema/aix-attr-align.c
+++ clang/test/Sema/aix-attr-align.c
@@ -6,17 +6,43 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only %s
 
 struct S {
-  int a[8] __attribute__((aligned(8))); // no-warning
+  int a[8] __attribute__((aligned(8)));  // no-warning
+  int b[8] __attribute__((aligned(16))); // no-warning
+  int c[2] __attribute__((aligned(32))); // no-warning
 };
 
 struct T {
-  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  int a[4] __attribute__((aligned(16))); // no-warning
 };
 
 struct U {
-  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  int a[2] __attribute__((aligned(32))); // no-warning
 };
 
 int a[8] __attribute__((aligned(8)));  // no-warning
 int b[4] __attribute__((aligned(16))); // no-warning
 int c[2] __attribute__((aligned(32))); // no-warning
+
+void baz(int *);
+static void static_baz(int *b) {
+  b = b + 1;
+}
+
+void foo(int p1, int p2, int p3, int p4, int p5, int p6, int p7, int p8,
+ struct S s) {
+  baz(s.a); // no-warning
+  baz(s.b); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  baz(s.c); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+
+  baz(a); // no-warning
+  baz(b); // no-warning
+  baz(c); // no-warning
+
+  static_baz(s.a); // no-warning
+  static_baz(s.b); // no-warning
+  static_baz(s.c); // no-warning
+
+  static_baz(a); // no-warning
+  static_baz(b); // no-warning
+  static_baz(c); // no-warning
+}
Index: clang/test/CXX/drs/dr6xx.cpp
===
--- clang/test/CXX/drs/dr6xx.cpp
+++ clang/test/CXX/drs/dr6xx.cpp
@@ -1,10 +1,8 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
+// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
 
 namespace std {
   struct type_info {};
Index: clang/test/Analysis/padding_cpp.cpp
===
--- clang/test/Analysis/padding_cpp.cpp
+++ clang/test/Analysis/padding_cpp.cpp
@@ -1,6 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-// RUN: %clang_analyze_cc1 -st

[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/include/clang/Sema/Sema.h:12693-12695
   void CheckArgAlignment(SourceLocation Loc, NamedDecl *FDecl,
- StringRef ParamName, QualType ArgTy, QualType 
ParamTy);
+ StringRef ParamName, QualType ArgTy, QualType ParamTy,
+ const Expr *Arg = nullptr);

ZarkoCA wrote:
> ZarkoCA wrote:
> > aaron.ballman wrote:
> > > I'm not keen on passing both `Arg` and `ArgTy` such that they can get out 
> > > of sync. Do all of the places calling `CheckArgAlignment()` have access 
> > > to the `Expr` so that we can require it be passed (and drop the `ArgTy` 
> > > parameter)?
> > Thanks, that is something I overlooked. 
> > 
> > It seems like I can do this everywhere except the call from 
> > `Sema::CheckConstructorCall`. Trying to figure out whether it's something 
> > I'm missing. 
> Thanks for the through review, I think I addressed everything but this 
> comment. I agree with your concern about having `Arg` and `ArgTy` getting out 
> of sync. I need to spend more time on that particular call from 
> `Sema::CheckConstructorCall` and see what can be done. 
@aaron.ballman I moved the check to its own function and only pass `Expr *Arg` 
to it. I think this should avoid them getting out of sync. 


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[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 406620.
ZarkoCA added a comment.

- Add note for diagnostic pointing to declaration of the struct member
- cleaned up use of unneeded variable


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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Analysis/padding_c.c
  clang/test/Analysis/padding_cpp.cpp
  clang/test/CXX/drs/dr6xx.cpp
  clang/test/Sema/aix-attr-align.c
  clang/test/SemaTemplate/instantiate-attr.cpp

Index: clang/test/SemaTemplate/instantiate-attr.cpp
===
--- clang/test/SemaTemplate/instantiate-attr.cpp
+++ clang/test/SemaTemplate/instantiate-attr.cpp
@@ -1,7 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-
-// RUN: %clang_cc1 -fsyntax-only -verify -Wno-aix-compat %s
+// RUN: %clang_cc1 -fsyntax-only -verify %s
 // expected-no-diagnostics
 template 
 struct A {
Index: clang/test/Sema/aix-attr-align.c
===
--- clang/test/Sema/aix-attr-align.c
+++ clang/test/Sema/aix-attr-align.c
@@ -6,17 +6,43 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only %s
 
 struct S {
-  int a[8] __attribute__((aligned(8))); // no-warning
+  int a[8] __attribute__((aligned(8)));  // no-warning
+  int b[8] __attribute__((aligned(16))); // expected-note {{'b' declared here}}
+  int c[2] __attribute__((aligned(32))); // expected-note {{'c' declared here}}
 };
 
 struct T {
-  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  int a[4] __attribute__((aligned(16))); // no-warning
 };
 
 struct U {
-  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  int a[2] __attribute__((aligned(32))); // no-warning
 };
 
 int a[8] __attribute__((aligned(8)));  // no-warning
 int b[4] __attribute__((aligned(16))); // no-warning
 int c[2] __attribute__((aligned(32))); // no-warning
+
+void baz(int *);
+static void static_baz(int *b) {
+  b = b + 1;
+}
+
+void foo(int p1, int p2, int p3, int p4, int p5, int p6, int p7, int p8,
+ struct S s) {
+  baz(s.a); // no-warning
+  baz(s.b); // expected-warning {{16 byte requested alignment for a struct member used as an argument is 16 bytes or greater which is not binary compatible with IBM XL C/C++ for AIX 16.1.0 or older}}
+  baz(s.c); // expected-warning {{32 byte requested alignment for a struct member used as an argument is 16 bytes or greater which is not binary compatible with IBM XL C/C++ for AIX 16.1.0 or older}}
+
+  baz(a); // no-warning
+  baz(b); // no-warning
+  baz(c); // no-warning
+
+  static_baz(s.a); // no-warning
+  static_baz(s.b); // no-warning
+  static_baz(s.c); // no-warning
+
+  static_baz(a); // no-warning
+  static_baz(b); // no-warning
+  static_baz(c); // no-warning
+}
Index: clang/test/CXX/drs/dr6xx.cpp
===
--- clang/test/CXX/drs/dr6xx.cpp
+++ clang/test/CXX/drs/dr6xx.cpp
@@ -1,10 +1,8 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
+// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
 
 namespace std {
   struct type_info {};
Index: clang/test/Analysis/padding_cpp.cpp
===
--- clang/test/Analysis/padding_cpp.cpp
+++ clang/test/Analysis/padding_cpp.cpp
@@ -

[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 4 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:5220-5221
+  Context.toCharUnitsFromBits(AA->getAlignment(Context));
+  if (Alignment.getQuantity() >= 16)
+Diag(Loc, diag::warn_not_xl_compatible) << FD;
+}

aaron.ballman wrote:
> I think it'd probably be helpful to tell the user which alignment was 
> calculated (it may not be obvious from the context because the alignment 
> could be hidden behind a macro or something).
I tried to address in slightly modifying the warning message to emit the 
offending alignment and also adding a note for the declaration as you suggested 
elsewhere. 



Comment at: clang/test/Sema/aix-attr-align.c:34-35
+  baz(s.a); // no-warning
+  baz(s.b); // expected-warning {{requesting an alignment of 16 bytes or 
greater for struct members is not binary compatible with IBM XL C/C++ for AIX 
16.1.0 and older}}
+  baz(s.c); // expected-warning {{requesting an alignment of 16 bytes or 
greater for struct members is not binary compatible with IBM XL C/C++ for AIX 
16.1.0 and older}}
+

aaron.ballman wrote:
> This diagnostic is a bit odd to me. It says there's a request for alignment, 
> but there's no such request on this line. So it's not clear how the user is 
> supposed to react to the diagnostic. While the current code makes it somewhat 
> obvious because there's only one field in the expression, imagine code like 
> `quux(s.a, s.b);` where it's less clear as to which field causes the 
> diagnostic from looking at the call site.
> 
> Personally, I found the old diagnostics to be more clear as to what the issue 
> is. I think we should put the warning on the declaration involving the 
> alignment request, and we should add a note to the call site where the 
> diagnostic is generated from (or vice versa). WDYT?
That's a good point actually, there's nothing on the line that would be obvious 
to a user. 

I opted to warn at the use of struct member and to make a note where it was 
declared. This will hopefully help with determining which struct member is 
causing this warning instead of searching the code for its cause. I have a 
slight preference for doing it this way instead of the other way but can change 
it if preferred. 


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[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 406822.
ZarkoCA added a comment.

- Warn on declaration of struct member and add note for call


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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Analysis/padding_c.c
  clang/test/Analysis/padding_cpp.cpp
  clang/test/CXX/drs/dr6xx.cpp
  clang/test/Sema/aix-attr-align.c
  clang/test/SemaTemplate/instantiate-attr.cpp

Index: clang/test/SemaTemplate/instantiate-attr.cpp
===
--- clang/test/SemaTemplate/instantiate-attr.cpp
+++ clang/test/SemaTemplate/instantiate-attr.cpp
@@ -1,7 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-
-// RUN: %clang_cc1 -fsyntax-only -verify -Wno-aix-compat %s
+// RUN: %clang_cc1 -fsyntax-only -verify %s
 // expected-no-diagnostics
 template 
 struct A {
Index: clang/test/Sema/aix-attr-align.c
===
--- clang/test/Sema/aix-attr-align.c
+++ clang/test/Sema/aix-attr-align.c
@@ -6,17 +6,43 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only %s
 
 struct S {
-  int a[8] __attribute__((aligned(8))); // no-warning
+  int a[8] __attribute__((aligned(8)));  // no-warning
+  int b[8] __attribute__((aligned(16))); // expected-warning {{16 byte requested alignment for a struct member used as an argument is 16 bytes or greater which is not binary compatible with IBM XL C/C++ for AIX 16.1.0 or older}}
+  int c[2] __attribute__((aligned(32))); // expected-warning {{32 byte requested alignment for a struct member used as an argument is 16 bytes or greater which is not binary compatible with IBM XL C/C++ for AIX 16.1.0 or older}}
 };
 
 struct T {
-  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  int a[4] __attribute__((aligned(16))); // no-warning
 };
 
 struct U {
-  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  int a[2] __attribute__((aligned(32))); // no-warning
 };
 
 int a[8] __attribute__((aligned(8)));  // no-warning
 int b[4] __attribute__((aligned(16))); // no-warning
 int c[2] __attribute__((aligned(32))); // no-warning
+
+void baz(int *);
+static void static_baz(int *b) {
+  b = b + 1;
+}
+
+void foo(int p1, int p2, int p3, int p4, int p5, int p6, int p7, int p8,
+ struct S s) {
+  baz(s.a); // no-note
+  baz(s.b); // expected-note {{called by 'b'}}
+  baz(s.c); // expected-note {{called by 'c'}}
+
+  baz(a); // no-note
+  baz(b); // no-note
+  baz(c); // no-note
+
+  static_baz(s.a); // no-note
+  static_baz(s.b); // no-note
+  static_baz(s.c); // no-note
+
+  static_baz(a); // no-note
+  static_baz(b); // no-note
+  static_baz(c); // no-note
+}
Index: clang/test/CXX/drs/dr6xx.cpp
===
--- clang/test/CXX/drs/dr6xx.cpp
+++ clang/test/CXX/drs/dr6xx.cpp
@@ -1,10 +1,8 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
+// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
 
 namespace std {
   struct type_info {};
Index: clang/test/Analysis/padding_cpp.cpp
===
--- clang/test/Analysis/padding_cpp.cpp
+++ clang/test/Analysis/padding_cpp.cpp
@@ -1,6 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being

[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/Sema/aix-attr-align.c:34-35
+  baz(s.a); // no-warning
+  baz(s.b); // expected-warning {{requesting an alignment of 16 bytes or 
greater for struct members is not binary compatible with IBM XL C/C++ for AIX 
16.1.0 and older}}
+  baz(s.c); // expected-warning {{requesting an alignment of 16 bytes or 
greater for struct members is not binary compatible with IBM XL C/C++ for AIX 
16.1.0 and older}}
+

aaron.ballman wrote:
> ZarkoCA wrote:
> > aaron.ballman wrote:
> > > This diagnostic is a bit odd to me. It says there's a request for 
> > > alignment, but there's no such request on this line. So it's not clear 
> > > how the user is supposed to react to the diagnostic. While the current 
> > > code makes it somewhat obvious because there's only one field in the 
> > > expression, imagine code like `quux(s.a, s.b);` where it's less clear as 
> > > to which field causes the diagnostic from looking at the call site.
> > > 
> > > Personally, I found the old diagnostics to be more clear as to what the 
> > > issue is. I think we should put the warning on the declaration involving 
> > > the alignment request, and we should add a note to the call site where 
> > > the diagnostic is generated from (or vice versa). WDYT?
> > That's a good point actually, there's nothing on the line that would be 
> > obvious to a user. 
> > 
> > I opted to warn at the use of struct member and to make a note where it was 
> > declared. This will hopefully help with determining which struct member is 
> > causing this warning instead of searching the code for its cause. I have a 
> > slight preference for doing it this way instead of the other way but can 
> > change it if preferred. 
> I'd like to understand why you have a preference for this way around.
> 
> The use is the point in time at which we know there's a problem, so I 
> definitely agree with waiting until the struct member is used to diagnose 
> anything.
> 
> But, to my thinking, the use is not the cause of the issue; the declaration 
> is what's problematic. With that perspective, it seems like we want the 
> warning and the note the other way around: warn about the structure member 
> declaration being the issue, and note where the use that triggered the 
> complaint about the declaration. Then the warning diagnostic is associated 
> most closely with the code that needs to be adjusted by the user in order to 
> silence the warning. This also makes it easier for the user to silence the 
> warning with pragmas (you can put the suppression mechanism in one place, at 
> the declaration site, instead of sprinkling it all over at the use sites).
> Then the warning diagnostic is associated most closely with the code that 
> needs to be adjusted by the user in order to silence the warning.

Thanks, that's a good point and your additional argument about silencing it 
with pragmas at a single place has convinced me to switch it up. 



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[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 406843.
ZarkoCA added a comment.

- Shorten warning message
- Add new note


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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Analysis/padding_c.c
  clang/test/Analysis/padding_cpp.cpp
  clang/test/CXX/drs/dr6xx.cpp
  clang/test/Sema/aix-attr-align.c
  clang/test/SemaTemplate/instantiate-attr.cpp

Index: clang/test/SemaTemplate/instantiate-attr.cpp
===
--- clang/test/SemaTemplate/instantiate-attr.cpp
+++ clang/test/SemaTemplate/instantiate-attr.cpp
@@ -1,7 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-
-// RUN: %clang_cc1 -fsyntax-only -verify -Wno-aix-compat %s
+// RUN: %clang_cc1 -fsyntax-only -verify %s
 // expected-no-diagnostics
 template 
 struct A {
Index: clang/test/Sema/aix-attr-align.c
===
--- clang/test/Sema/aix-attr-align.c
+++ clang/test/Sema/aix-attr-align.c
@@ -6,17 +6,43 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only %s
 
 struct S {
-  int a[8] __attribute__((aligned(8))); // no-warning
+  int a[8] __attribute__((aligned(8)));  // no-warning
+  int b[8] __attribute__((aligned(16))); // expected-warning {{alignment of 16 bytes or greater for a struct member is not binary compatible with IBM XL C/C++ for AIX 16.1.0 or older}}
+  int c[2] __attribute__((aligned(32))); // expected-warning {{alignment of 16 bytes or greater for a struct member is not binary compatible with IBM XL C/C++ for AIX 16.1.0 or older}}
 };
 
 struct T {
-  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  int a[4] __attribute__((aligned(16))); // no-warning
 };
 
 struct U {
-  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+  int a[2] __attribute__((aligned(32))); // no-warning
 };
 
 int a[8] __attribute__((aligned(8)));  // no-warning
 int b[4] __attribute__((aligned(16))); // no-warning
 int c[2] __attribute__((aligned(32))); // no-warning
+
+void baz(int *);
+static void static_baz(int *b) {
+  b = b + 1;
+}
+
+void foo(int p1, int p2, int p3, int p4, int p5, int p6, int p7, int p8,
+ struct S s) {
+  baz(s.a); // no-note
+  baz(s.b); // expected-note {{'b' used with potentially incompatible alignment here}}
+  baz(s.c); // expected-note {{'c' used with potentially incompatible alignment here}}
+
+  baz(a); // no-note
+  baz(b); // no-note
+  baz(c); // no-note
+
+  static_baz(s.a); // no-note
+  static_baz(s.b); // no-note
+  static_baz(s.c); // no-note
+
+  static_baz(a); // no-note
+  static_baz(b); // no-note
+  static_baz(c); // no-note
+}
Index: clang/test/CXX/drs/dr6xx.cpp
===
--- clang/test/CXX/drs/dr6xx.cpp
+++ clang/test/CXX/drs/dr6xx.cpp
@@ -1,10 +1,8 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
+// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
 
 namespace std {
   struct type_info {};
Index: clang/test/Analysis/padding_cpp.cpp
===
--- clang/test/Analysis/padding_cpp.cpp
+++ clang/test/Analysis/padding_cpp.cpp
@@ -1,6 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-// RUN: %clang

[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:3299-3301
+: Warning<" %0 byte requested alignment for a struct member used as an"
+  " argument is 16 bytes or greater which is not binary"
+  " compatible with IBM XL C/C++ for AIX 16.1.0 or older">,

aaron.ballman wrote:
> How about this slight rewording from the old form? (Have to re-flow to 80 
> cols.)
> 
> I had previously suggested adding the requested alignment before but now that 
> we're closely tying the diagnostic to the structure member, I think this form 
> is okay (and it's shorter, which is what I was hoping to accomplish).
Yes, I cringed a bit seeing it at 3 lines. Thanks. 



Comment at: clang/lib/Sema/SemaChecking.cpp:5221
+<< (unsigned)Alignment.getQuantity() << FD;
+Diag(Loc, diag::note_called_by) << FD->getDeclName();
+  }

aaron.ballman wrote:
> I don't think this note is the correct one to use (it looks weird in the test 
> cases). I think you'll want to add a new note along the lines of:
> ```
> def note_misaligned_member_used_here : Note<
>   "%0 used with potentially incompatible alignment here">;
> ```
> And you should pass in `FD` rather than `FD->getDeclName()` (the diagnostics 
> engine knows how to print the names of `NamedDecl` subclasses and has special 
> logic for that.
Ah yes, this seems much clearer to the user now IMO, thanks


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[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct member is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added a comment.

After offline discussion with @sfertile , the warning should occur only when 
the struct member is passed on the stack. I will be updating the patch shortly.

@aaron.ballman Thank you for the thorough reviews comments and sorry for the 
churn.


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[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 443812.
ZarkoCA added a comment.

- Rebase and add FDecl check before calling checkAIXMemberAlignment()


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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Analysis/padding_c.c
  clang/test/Analysis/padding_cpp.cpp
  clang/test/CXX/drs/dr6xx.cpp
  clang/test/Sema/aix-attr-align.c
  clang/test/SemaTemplate/instantiate-attr.cpp

Index: clang/test/SemaTemplate/instantiate-attr.cpp
===
--- clang/test/SemaTemplate/instantiate-attr.cpp
+++ clang/test/SemaTemplate/instantiate-attr.cpp
@@ -1,7 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-
-// RUN: %clang_cc1 -fsyntax-only -verify -Wno-aix-compat %s
+// RUN: %clang_cc1 -fsyntax-only -verify %s
 // expected-no-diagnostics
 template 
 struct A {
Index: clang/test/Sema/aix-attr-align.c
===
--- clang/test/Sema/aix-attr-align.c
+++ clang/test/Sema/aix-attr-align.c
@@ -5,18 +5,37 @@
 // RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify=off -Wno-aix-compat -fsyntax-only %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only %s
 
-struct S {
-  int a[8] __attribute__((aligned(8))); // no-warning
+// We do not warn on any declaration with a member aligned 16. Only when the struct is passed byval.
+struct R {
+  int b[8] __attribute__((aligned(16))); // no-warning
 };
 
-struct T {
-  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+struct S {
+  int a[8] __attribute__((aligned(8)));  // no-warning
+  int b[8] __attribute__((aligned(16))); // expected-warning {{alignment of 16 bytes for a struct member is not binary compatible with IBM XL C/C++ for AIX 16.1.0 or older}}
 };
 
-struct U {
-  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+struct T {
+  int a[8] __attribute__((aligned(8))); // no-warning
+  int b[8] __attribute__((aligned(4))); // no-warning
 };
 
 int a[8] __attribute__((aligned(8)));  // no-warning
 int b[4] __attribute__((aligned(16))); // no-warning
-int c[2] __attribute__((aligned(32))); // no-warning
+
+void baz(int a, int b, int *c, int d, int *e, int f, struct S);
+void jaz(int a, int b, int *c, int d, int *e, int f, struct T);
+void vararg_baz(int a,...);
+static void static_baz(int a, int b, int *c, int d, int *e, int f, struct S sp2) {
+  a = *sp2.b + *c + *e;
+}
+
+void foo(int p1, int p2, int p3, int p4, int p5, int p6, int p7, int p8,
+ struct S s, struct T t) {
+
+  baz(p1, p2, s.b, p3, b, p5, s);// expected-note {{passing byval argument 's' with potentially incompatible alignment here}}
+  jaz(p1, p2, a, p3, s.a, p5, t);// no-note
+  jaz(p1, p2, s.b, p3, b, p5, t);// no-note
+  vararg_baz(p1, p2, s.b, p3, b, p5, s); // no-note
+  static_baz(p1, p2, s.b, p3, b, p5, s); // no-note
+}
Index: clang/test/CXX/drs/dr6xx.cpp
===
--- clang/test/CXX/drs/dr6xx.cpp
+++ clang/test/CXX/drs/dr6xx.cpp
@@ -1,10 +1,8 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
+// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
 
 namespace std {
   struct type_info {};
Index: clang/test/Analysis/padding_cpp.cpp

[PATCH] D118350: [Clang][Sema][AIX][PowerPC] Emit byval alignment warning only when struct is passed to a function

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa61b202d4e3b: [Clang][Sema][AIX][PowerPC] Emit byval 
alignment warning only when struct is… (authored by ZarkoCA).

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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Analysis/padding_c.c
  clang/test/Analysis/padding_cpp.cpp
  clang/test/CXX/drs/dr6xx.cpp
  clang/test/Sema/aix-attr-align.c
  clang/test/SemaTemplate/instantiate-attr.cpp

Index: clang/test/SemaTemplate/instantiate-attr.cpp
===
--- clang/test/SemaTemplate/instantiate-attr.cpp
+++ clang/test/SemaTemplate/instantiate-attr.cpp
@@ -1,7 +1,4 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-
-// RUN: %clang_cc1 -fsyntax-only -verify -Wno-aix-compat %s
+// RUN: %clang_cc1 -fsyntax-only -verify %s
 // expected-no-diagnostics
 template 
 struct A {
Index: clang/test/Sema/aix-attr-align.c
===
--- clang/test/Sema/aix-attr-align.c
+++ clang/test/Sema/aix-attr-align.c
@@ -5,18 +5,37 @@
 // RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -verify=off -Wno-aix-compat -fsyntax-only %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux -verify=off -fsyntax-only %s
 
-struct S {
-  int a[8] __attribute__((aligned(8))); // no-warning
+// We do not warn on any declaration with a member aligned 16. Only when the struct is passed byval.
+struct R {
+  int b[8] __attribute__((aligned(16))); // no-warning
 };
 
-struct T {
-  int a[4] __attribute__((aligned(16))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+struct S {
+  int a[8] __attribute__((aligned(8)));  // no-warning
+  int b[8] __attribute__((aligned(16))); // expected-warning {{alignment of 16 bytes for a struct member is not binary compatible with IBM XL C/C++ for AIX 16.1.0 or older}}
 };
 
-struct U {
-  int a[2] __attribute__((aligned(32))); // expected-warning {{requesting an alignment of 16 bytes or greater for struct members is not binary compatible with IBM XL C/C++ for AIX 16.1.0 and older}}
+struct T {
+  int a[8] __attribute__((aligned(8))); // no-warning
+  int b[8] __attribute__((aligned(4))); // no-warning
 };
 
 int a[8] __attribute__((aligned(8)));  // no-warning
 int b[4] __attribute__((aligned(16))); // no-warning
-int c[2] __attribute__((aligned(32))); // no-warning
+
+void baz(int a, int b, int *c, int d, int *e, int f, struct S);
+void jaz(int a, int b, int *c, int d, int *e, int f, struct T);
+void vararg_baz(int a,...);
+static void static_baz(int a, int b, int *c, int d, int *e, int f, struct S sp2) {
+  a = *sp2.b + *c + *e;
+}
+
+void foo(int p1, int p2, int p3, int p4, int p5, int p6, int p7, int p8,
+ struct S s, struct T t) {
+
+  baz(p1, p2, s.b, p3, b, p5, s);// expected-note {{passing byval argument 's' with potentially incompatible alignment here}}
+  jaz(p1, p2, a, p3, s.a, p5, t);// no-note
+  jaz(p1, p2, s.b, p3, b, p5, t);// no-note
+  vararg_baz(p1, p2, s.b, p3, b, p5, s); // no-note
+  static_baz(p1, p2, s.b, p3, b, p5, s); // no-note
+}
Index: clang/test/CXX/drs/dr6xx.cpp
===
--- clang/test/CXX/drs/dr6xx.cpp
+++ clang/test/CXX/drs/dr6xx.cpp
@@ -1,10 +1,8 @@
-// FIXME -Wno-aix-compat added temporarily while the diagnostic is being
-// refined.
-// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
-// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -Wno-aix-compat
+// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
+// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking
 
 namespace std {
   struct type_info {};
Index: clang/

[PATCH] D88105: [NFC] [PPC] Add PowerPC expected IR tests for C99 complex

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/CodeGen/powerpc-c99complex.c:1
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux -emit-llvm %s -o - | 
FileCheck %s --check-prefixes=PPC64LNX
+// RUN: %clang_cc1 -triple powerpc-unknown-linux -emit-llvm %s -o - | 
FileCheck %s --check-prefix=PPC32LNX

Can you add ppc64le as well? 


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[PATCH] D88105: [NFC] [PPC] Add PowerPC expected IR tests for C99 complex

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/CodeGen/powerpc-c99complex.c:7
+  return x;
+// PPC64LNX-LABEL:   define { float, float } @foo1(float %x.{{.*}}, float 
%x.{{.*}}) #0 {
+// PPC64LNX: ret { float, float }

Nit: I don't think you need the `#0` here and anywhere below.



Comment at: clang/test/CodeGen/powerpc-c99complex.c:19-20
+  return x;
+// PPC64LNX-LABEL:   define { double, double } @foo2(double %x.{{.*}}, 
double %x.{{.*}}) #0 {
+// PPC64LNX: ret { double, double }
+

Nit: please line up these lines with the ones below. 



Comment at: clang/test/CodeGen/powerpc-c99complex.c:34-39
+// PPC32LNX-LABEL: define void @foo3({ ppc_fp128, ppc_fp128 }* noalias sret 
align 16 %agg.result, { ppc_fp128, ppc_fp128 }* byval({ ppc_fp128, ppc_fp128 }) 
align 16 %x) #0 {
+// PPC32LNX:   [[RETREAL:%.*]] = getelementptr inbounds { ppc_fp128, 
ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %agg.result, i32 0, i32 0
+// PPC32LNX-NEXT:  [[RETIMAG:%.*]] = getelementptr inbounds { ppc_fp128, 
ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %agg.result, i32 0, i32 1
+// PPC32LNX-NEXT:  store ppc_fp128 %{{.*}}, ppc_fp128* [[RETREAL]], align 16
+// PPC32LNX-NEXT:  store ppc_fp128 %{{.*}}, ppc_fp128* [[RETIMAG]], align 16
+}

Nit: Can the formatting be fixed so the lines line up? 


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[PATCH] D88105: [NFC] [PPC] Add PowerPC expected IR tests for C99 complex

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA accepted this revision.
ZarkoCA added a comment.

Thanks for doing the formatting changes.


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[PATCH] D88105: [NFC] [PPC] Add PowerPC expected IR tests for C99 complex

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added a comment.

In D88105#2292266 , @nemanjai wrote:

> This clearly changes behaviour and should thereby not have the `[NFC]` tag.

Looks like it accidentally includes https://reviews.llvm.org/D88130.


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[PATCH] D88105: [NFC] [PPC] Add PowerPC expected IR tests for C99 complex

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG64b8a633a872: [NFC] [PPC] Add PowerPC expected IR tests for 
C99 complex (authored by cebowleratibm, committed by ZarkoCA).

Changed prior to commit:
  https://reviews.llvm.org/D88105?vs=293917&id=294222#toc

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Files:
  clang/test/CodeGen/powerpc-c99complex.c


Index: clang/test/CodeGen/powerpc-c99complex.c
===
--- /dev/null
+++ clang/test/CodeGen/powerpc-c99complex.c
@@ -0,0 +1,39 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux -emit-llvm %s -o - | 
FileCheck %s --check-prefixes=PPC64LNX
+// RUN: %clang_cc1 -triple ppc64le-unknown-linux -emit-llvm %s -o - | 
FileCheck %s --check-prefixes=PPC64LNX
+// RUN: %clang_cc1 -triple powerpc-unknown-linux -emit-llvm %s -o - | 
FileCheck %s --check-prefix=PPC32LNX
+
+_Complex float foo1(_Complex float x) {
+  return x;
+// PPC64LNX-LABEL:   define { float, float } @foo1(float %x.{{.*}}, float 
%x.{{.*}}) #0 {
+// PPC64LNX: ret { float, float }
+
+// PPC32LNX-LABEL:   define void @foo1({ float, float }* noalias sret 
align 4 %agg.result, { float, float }* byval({ float, float }) align 4 %x) #0 {
+// PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { float, 
float }, { float, float }* %agg.result, i32 0, i32 0
+// PPC32LNX-NEXT:[[RETIMAG:%.*]] = getelementptr inbounds { float, 
float }, { float, float }* %agg.result, i32 0, i32 1
+// PPC32LNX-NEXT:store float %{{.*}}, float* [[RETREAL]], align 4
+// PPC32LNX-NEXT:store float %{{.*}}, float* [[RETIMAG]], align 4
+}
+
+_Complex double foo2(_Complex double x) {
+  return x;
+// PPC64LNX-LABEL:   define { double, double } @foo2(double %x.{{.*}}, 
double %x.{{.*}}) #0 {
+// PPC64LNX: ret { double, double }
+
+// PPC32LNX-LABEL:   define void @foo2({ double, double }* noalias sret 
align 8 %agg.result, { double, double }* byval({ double, double }) align 8 %x) 
#0 {
+// PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { double, 
double }, { double, double }* %agg.result, i32 0, i32 0
+// PPC32LNX-NEXT:[[RETIMAG:%.*]] = getelementptr inbounds { double, 
double }, { double, double }* %agg.result, i32 0, i32 1
+// PPC32LNX-NEXT:store double %{{.*}}, double* [[RETREAL]], align 8
+// PPC32LNX-NEXT:store double %{{.*}}, double* [[RETIMAG]], align 8
+}
+
+_Complex long double foo3(_Complex long double x) {
+  return x;
+// PPC64LNX-LABEL:  define { ppc_fp128, ppc_fp128 } @foo3(ppc_fp128 
%x.{{.*}}, ppc_fp128 %x.{{.*}}) #0 {
+// PPC64LNX:ret { ppc_fp128, ppc_fp128 }
+
+// PPC32LNX-LABEL:  define void @foo3({ ppc_fp128, ppc_fp128 }* noalias 
sret align 16 %agg.result, { ppc_fp128, ppc_fp128 }* byval({ ppc_fp128, 
ppc_fp128 }) align 16 %x) #0 {
+// PPC32LNX:[[RETREAL:%.*]] = getelementptr inbounds { ppc_fp128, 
ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %agg.result, i32 0, i32 0
+// PPC32LNX-NEXT:   [[RETIMAG:%.*]] = getelementptr inbounds { ppc_fp128, 
ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %agg.result, i32 0, i32 1
+// PPC32LNX-NEXT:   store ppc_fp128 %{{.*}}, ppc_fp128* [[RETREAL]], align 
16
+// PPC32LNX-NEXT:   store ppc_fp128 %{{.*}}, ppc_fp128* [[RETIMAG]], align 
16
+}


Index: clang/test/CodeGen/powerpc-c99complex.c
===
--- /dev/null
+++ clang/test/CodeGen/powerpc-c99complex.c
@@ -0,0 +1,39 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefixes=PPC64LNX
+// RUN: %clang_cc1 -triple ppc64le-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefixes=PPC64LNX
+// RUN: %clang_cc1 -triple powerpc-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=PPC32LNX
+
+_Complex float foo1(_Complex float x) {
+  return x;
+// PPC64LNX-LABEL:   define { float, float } @foo1(float %x.{{.*}}, float %x.{{.*}}) #0 {
+// PPC64LNX: ret { float, float }
+
+// PPC32LNX-LABEL:   define void @foo1({ float, float }* noalias sret align 4 %agg.result, { float, float }* byval({ float, float }) align 4 %x) #0 {
+// PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { float, float }, { float, float }* %agg.result, i32 0, i32 0
+// PPC32LNX-NEXT:[[RETIMAG:%.*]] = getelementptr inbounds { float, float }, { float, float }* %agg.result, i32 0, i32 1
+// PPC32LNX-NEXT:store float %{{.*}}, float* [[RETREAL]], align 4
+// PPC32LNX-NEXT:store float %{{.*}}, float* [[RETIMAG]], align 4
+}
+
+_Complex double foo2(_Complex double x) {
+  return x;
+// PPC64LNX-LABEL:   define { double, double } @foo2(double %x.{{.*}}, double %x.{{.*}}) #0 {
+// PPC64LNX: ret { double, double }
+
+// PPC32LNX-LABEL:   define void @foo2(

[PATCH] D88130: [PPC] [AIX] Implement calling convention IR for C99 complex types on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA accepted this revision.
ZarkoCA added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D88130: [PPC] [AIX] Implement calling convention IR for C99 complex types on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf330d9f163f6: [PPC] [AIX] Implement calling convention IR 
for C99 complex types on AIX (authored by cebowleratibm, committed by ZarkoCA).

Changed prior to commit:
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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-complex.c
  clang/test/CodeGen/powerpc-c99complex.c

Index: clang/test/CodeGen/powerpc-c99complex.c
===
--- clang/test/CodeGen/powerpc-c99complex.c
+++ clang/test/CodeGen/powerpc-c99complex.c
@@ -1,39 +1,44 @@
-// RUN: %clang_cc1 -triple powerpc64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefixes=PPC64LNX
-// RUN: %clang_cc1 -triple ppc64le-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefixes=PPC64LNX
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOLDBL128
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOLDBL128
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LDBL128
+// RUN: %clang_cc1 -triple ppc64le-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LDBL128
 // RUN: %clang_cc1 -triple powerpc-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=PPC32LNX
 
 _Complex float foo1(_Complex float x) {
   return x;
-// PPC64LNX-LABEL:   define { float, float } @foo1(float %x.{{.*}}, float %x.{{.*}}) #0 {
-// PPC64LNX: ret { float, float }
+// CHECK-LABEL: define { float, float } @foo1(float %x.{{.*}}, float %x.{{.*}}) #0 {
+// CHECK:   ret { float, float }
 
-// PPC32LNX-LABEL:   define void @foo1({ float, float }* noalias sret align 4 %agg.result, { float, float }* byval({ float, float }) align 4 %x) #0 {
-// PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { float, float }, { float, float }* %agg.result, i32 0, i32 0
-// PPC32LNX-NEXT:[[RETIMAG:%.*]] = getelementptr inbounds { float, float }, { float, float }* %agg.result, i32 0, i32 1
-// PPC32LNX-NEXT:store float %{{.*}}, float* [[RETREAL]], align 4
-// PPC32LNX-NEXT:store float %{{.*}}, float* [[RETIMAG]], align 4
+// PPC32LNX-LABEL:  define void @foo1({ float, float }* noalias sret align 4 %agg.result, { float, float }* byval({ float, float }) align 4 %x) #0 {
+// PPC32LNX:[[RETREAL:%.*]] = getelementptr inbounds { float, float }, { float, float }* %agg.result, i32 0, i32 0
+// PPC32LNX-NEXT:   [[RETIMAG:%.*]] = getelementptr inbounds { float, float }, { float, float }* %agg.result, i32 0, i32 1
+// PPC32LNX-NEXT:   store float %{{.*}}, float* [[RETREAL]], align 4
+// PPC32LNX-NEXT:   store float %{{.*}}, float* [[RETIMAG]], align 4
 }
 
 _Complex double foo2(_Complex double x) {
   return x;
-// PPC64LNX-LABEL:   define { double, double } @foo2(double %x.{{.*}}, double %x.{{.*}}) #0 {
-// PPC64LNX: ret { double, double }
+// CHECK-LABEL: define { double, double } @foo2(double %x.{{.*}}, double %x.{{.*}}) #0 {
+// CHECK:   ret { double, double }
 
-// PPC32LNX-LABEL:   define void @foo2({ double, double }* noalias sret align 8 %agg.result, { double, double }* byval({ double, double }) align 8 %x) #0 {
-// PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { double, double }, { double, double }* %agg.result, i32 0, i32 0
-// PPC32LNX-NEXT:[[RETIMAG:%.*]] = getelementptr inbounds { double, double }, { double, double }* %agg.result, i32 0, i32 1
-// PPC32LNX-NEXT:store double %{{.*}}, double* [[RETREAL]], align 8
-// PPC32LNX-NEXT:store double %{{.*}}, double* [[RETIMAG]], align 8
+// PPC32LNX-LABEL:  define void @foo2({ double, double }* noalias sret align 8 %agg.result, { double, double }* byval({ double, double }) align 8 %x) #0 {
+// PPC32LNX:[[RETREAL:%.*]] = getelementptr inbounds { double, double }, { double, double }* %agg.result, i32 0, i32 0
+// PPC32LNX-NEXT:   [[RETIMAG:%.*]] = getelementptr inbounds { double, double }, { double, double }* %agg.result, i32 0, i32 1
+// PPC32LNX-NEXT:   store double %{{.*}}, double* [[RETREAL]], align 8
+// PPC32LNX-NEXT:   store double %{{.*}}, double* [[RETIMAG]], align 8
 }
 
 _Complex long double foo3(_Complex long double x) {
   return x;
-// PPC64LNX-LABEL:  define { ppc_fp128, ppc_fp128 } @foo3(ppc_fp128 %x.{{.*}}, ppc_fp128 %x.{{.*}}) #0 {
-// PPC64LNX:ret { ppc_fp128, ppc_fp128 }
+// CHECK-NOLDBL128-LABEL:   define { double, double } @foo3(do

[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 305136.
ZarkoCA retitled this revision from "[AIX] Add mvecnvol and mnovecnvol options 
to enable the AIX extended and default vector ABIs. " to "[AIX] Add 
mabi=vec-extabi options to enable the AIX extended and default vector ABIs. ".
ZarkoCA edited the summary of this revision.
ZarkoCA added a comment.

Addressed comments:


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Preprocessor/aix-vec_extabi.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-default-vec-abi.ll
  llvm/test/CodeGen/PowerPC/aix-func-align.ll
  llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
  llvm/test/CodeGen/PowerPC/aix-internal.ll
  llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
  llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
  llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-return55.ll
  llvm/test/CodeGen/PowerPC/aix-space.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
  llvm/test/CodeGen/PowerPC/aix32-crsave.mir
  llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
  llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
  llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
  llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

Index: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
===
--- llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -7,7 +7,7 @@
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
Index: llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
===
--- llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/aix32-crsave.mir

[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 8 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:532
   Options.EmitCallSiteInfo = CodeGenOpts.EmitCallSiteInfo;
+  Options.AIXExtendedAltivecABI = CodeGenOpts.AIXExtendedAltivecABI;
   Options.ValueTrackingVariableLocations =

Xiangling_L wrote:
> The ABI specifies `When the option to use nonvolatile vector registers is 
> enalbed. the compilation environment must also predefine __EXTABI__`. I 
> didn't see this. Should we also cover this in this patch?
Thanks, that was an oversight. 



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4571
   }
 
+  if (Arg *A =

Xiangling_L wrote:
> On clang, when we do: 
> `clang -target powerpc-ibm-aix-xcoff -maltivec -S -emit-llvm 
> test_faltivec.c`,  clang driver passes `-target-cpu pwr4` as default arch to 
> frontend without issuing any error.
> 
> However, with XL, we have: 
> `"-qaltivec" is not compatible with "-qarch=pwr4". "-qnoaltivec" is being 
> set.`  The same error will be issued if `pwr5` is used as well. 
> 
> So I suppose for AIX in clang, when user use `-maltivec` without specifying 
> arch level, we can do:
> 1)  by default pass `-target-cpu pwr6` to frontend 
> or  2) issue error for "-qarch=pwr4"+ enable altivec
> or 3) issue error for `-qacrh = pwr4` + diable altivec like XL does?
> 
> Also we should emit error when user use `-maltivec` with -mcpu=pwr5.
I think what XL does is probably the correct thing but in clang/llvm it looks 
like the hasAltivec setting is determined by the cpu level and the compiler 
simply ignores it when it's not supported by the cpu.  

For now, I'd like to follow the existing logic as all the other PPC targets and 
then I can follow up with a patch that emits an error when selecting altivec 
when the cpu doesn't support it.   



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4579
+
+bool haveMaltivec = false;
+

Xiangling_L wrote:
> I would suggest `s/haveMaltivec/HasAltivec` to be consistent with other 
> places where if altivec enabled is tested.
I reworked this so that I hopefully remove any confusion. 



Comment at: llvm/lib/CodeGen/CommandFlags.cpp:489
 Options.FloatABIType = getFloatABIForCalls();
+  Options.AIXExtendedAltivecABI = getAIXExtendedAltivecABI();
   Options.NoZerosInBSS = getDontPlaceZerosInBSS();

Xiangling_L wrote:
> Should we also check `-vecnvol` option is used for AIX only somewhere?
Is there a way to check whether an llc option is target specific?



Comment at: llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll:4
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < 
\
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple 
powerpc64-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s

Xiangling_L wrote:
> May I ask why would we want to add -vecnvol for those testcases? As I 
> noticed, they don't need altivec feature enabled.
It is odd but those test cases hit the error 
`llvm/lib/Target/PowerPC/PPCISelLowering.cpp:6908` when that wasn't enabled.  
However, adding `mattr=-altivec` also suppresses it. It seems like specifying 
`mcpu=pwr4` doesn't not completely remove all altivec opts? 


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[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 305150.
ZarkoCA added a comment.

Rebased and addressed comments.


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Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

Index: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -0,0 +1,308 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs -mcpu=pwr7 \
+; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM64 %s
+
+
+define dso_local void @vec_regs() {
+entry:
+  call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32: name:vec_regs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:stack:
+
+; MIR32: liveins: $v20, $v26, $v31
+
+; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR32: INLINEASM
+
+; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG: $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32: BLR implicit $lr, implicit $rm
+
+; MIR64: name:vec_regs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:stack:
+
+; MIR64: liveins: $v20, $v26, $v31
+
+; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64: INLINEASM
+
+; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG: $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64: BLR8 implicit $lr8, implicit $rm
+
+
+; ASM32-LABEL:   .vec_regs:
+
+; ASM32: li {{[0-9]+}}, -192
+; ASM32-DAG: stxvd2x 52, 1, {{[0-9]+}}   # 16-byte Folded Spill
+; ASM32-DA

[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked an inline comment as done.
ZarkoCA added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:184
   if (TM.isPPC64()) {
-if (Subtarget.hasAltivec())
+if (Subtarget.hasAltivec()) {
+  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())

sfertile wrote:
> I suggest doing the error checking once before  getting into the 
> 32-bit/64-bit blocks.
Thanks, good suggestion, I moved it up right at the beginning of the function. 


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[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:235
+return TM.isPPC64()
+   ? (Subtarget.hasAltivec() ? CSR_64_AllRegs_Altivec_RegMask
+ : CSR_PPC64_RegMask)

sfertile wrote:
> `CSR_64_AllRegs_Altivec_RegMask` should be `CSR_PPC64_Altivec_RegMask`.  FWIW 
> I don't think this is testable without D86476. If that's the case, then it 
> should go in that patch, not this patch. 
Are you suggesting that I also leave the error in if I were to move this change 
to D84676? 


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[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 306509.
ZarkoCA marked 3 inline comments as done.
ZarkoCA added a comment.

Addressed comments: 
Added and fixed test cases and changed option selection logic.


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Preprocessor/aix-vec_extabi.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-func-align.ll
  llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
  llvm/test/CodeGen/PowerPC/aix-internal.ll
  llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
  llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
  llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-return55.ll
  llvm/test/CodeGen/PowerPC/aix-space.ll
  llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
  llvm/test/CodeGen/PowerPC/aix32-crsave.mir
  llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
  llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
  llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
  llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

Index: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
===
--- llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -7,7 +7,7 @@
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
Index: llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
===
--- llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/aix32-crsave.mir
===
--- llvm/test/CodeGen/PowerPC/aix32-crsave.mir
+++ llvm/test/CodeGen/PowerPC/aix32-crsave.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x m

[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 10 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4616
+  if (Args.hasArg(options::OPT_maltivec) &&
+  (Triple.isOSAIX() || Triple.isOSBinFormatXCOFF())) {
+for (const Arg *A : Args) {

Xiangling_L wrote:
> I am wondering what cases are not covered by `Triple.isOSAIX()`? Why do we 
> also query `Triple.isOSBinFormatXCOFF()`?
The path isn't selected if someone were to select -powerpc-unknown-xcoff as a 
target for example.  It looks like the Triple.isOSAIX() is true when we we have 
aix in the target triple. 



Comment at: clang/test/CodeGen/altivec.c:2
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown 
-emit-llvm %s -o - | FileCheck %s
-
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple 
powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple 
powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s

Xiangling_L wrote:
> Based on the code added in `BackendUtil:551`, should we also add a case for 
> compiling a source to assembly?
Added in lines 15-18



Comment at: llvm/include/llvm/Target/TargetOptions.h:179
 
+/// AIXExtendedAltivecABI - This flag returns true when -mabi=vec-extabi is
+/// specified. The code generator is then able to use both volatile and

Xiangling_L wrote:
> -mabi=vec-extabi is the FE option, should we s/-mabi=vec-extabi/-vec-extabi?
Good catch, fixed. 



Comment at: llvm/lib/CodeGen/CommandFlags.cpp:287
+  static cl::opt AIXExtendedAltivecABI(
+  "vec-extabi", cl::desc("Enable the AIX Extended Altivec ABI."),
+  cl::init(false));

Xiangling_L wrote:
> Can we add a testcase for this backend option?
Added in llvm/test/CodeGen/PowerPC/aix-vec-abi.c


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[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 306515.
ZarkoCA marked an inline comment as done.
ZarkoCA added a comment.

Rebase and remove regmask altivec change.


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Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

Index: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -0,0 +1,308 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs -mcpu=pwr7 \
+; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM64 %s
+
+
+define dso_local void @vec_regs() {
+entry:
+  call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32: name:vec_regs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:stack:
+
+; MIR32: liveins: $v20, $v26, $v31
+
+; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR32: INLINEASM
+
+; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG: $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32: BLR implicit $lr, implicit $rm
+
+; MIR64: name:vec_regs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:stack:
+
+; MIR64: liveins: $v20, $v26, $v31
+
+; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64: INLINEASM
+
+; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG: $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64: BLR8 implicit $lr8, implicit $rm
+
+
+; ASM32-LABEL:   .vec_regs:
+
+; ASM32: li {{[0-9]+}}, -192
+; ASM32-DAG: stxvd2x 52, 1, {{[0-9]

[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 6 inline comments as done.
ZarkoCA added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:235
+return TM.isPPC64()
+   ? (Subtarget.hasAltivec() ? CSR_64_AllRegs_Altivec_RegMask
+ : CSR_PPC64_RegMask)

sfertile wrote:
> ZarkoCA wrote:
> > sfertile wrote:
> > > `CSR_64_AllRegs_Altivec_RegMask` should be `CSR_PPC64_Altivec_RegMask`.  
> > > FWIW I don't think this is testable without D86476. If that's the case, 
> > > then it should go in that patch, not this patch. 
> > Are you suggesting that I also leave the error in if I were to move this 
> > change to D84676? 
> Can you still run the tests that are part of this commit with that error in? 
> My understanding was that it didn't interfere, but I didn't verify that. If 
> we can still run the tests then yes leave the error in. If we can't then it 
> probably gives us a clue about how to test the change in this patch without 
> needing D84676, in which case we can keep the change and simply add the 
> testing that exercises it.
No, you were right those changes can't be tested. Just needed some 
clarification, thanks. 


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[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 306545.
ZarkoCA marked an inline comment as done.
ZarkoCA added a comment.

Fixed failing test cases.


CHANGES SINCE LAST ACTION
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Files:
  llvm/include/llvm/Target/TargetMachine.h
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
@@ -3,12 +3,12 @@
 ; the test in this file should be merged into aix-xcoff-data.ll with additional
 ; tests for XCOFF object files.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple powerpc-ibm-aix-xcoff  -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 
 @magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2
Index: llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
@@ -1,10 +1,10 @@
 ; This file tests the codegen of mergeable const in AIX assembly.
 ; This file also tests mergeable const in XCOFF object file generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
Index: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -0,0 +1,308 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs -mcpu=pwr7 \
+; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM64 %s
+
+
+define dso_local void @vec_regs() {
+entry:
+  call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32: name:vec_regs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: d

[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 5 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/lib/Frontend/CompilerInvocation.cpp:1443
 
+  if (Arg *A =
+  Args.getLastArg(OPT_mabi_EQ_vec_default, OPT_mabi_EQ_vec_extabi)) {

Xiangling_L wrote:
> Should we also check if target feature altivec[`-target-feature +altivec`] is 
> enabled when using these two options? If so, we should also add related 
> testcases.
Both of these options require that -maltivec is also selected which sets 
`-target-feature +altivec`.



Comment at: clang/test/CodeGen/altivec.c:2
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown 
-emit-llvm %s -o - | FileCheck %s
-
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple 
powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple 
powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s

Xiangling_L wrote:
> ZarkoCA wrote:
> > Xiangling_L wrote:
> > > Based on the code added in `BackendUtil:551`, should we also add a case 
> > > for compiling a source to assembly?
> > Added in lines 15-18
> > Added in lines 15-18
> 
> Sorry, I should make my point clearer. Based on current testcases, there are 
> two things:
> 
> 1. line 15-18 are actually duplication to 10,11, 13. 14. Because all of them 
> are testing if the driver will emit error when not specifying -maltivec with 
> -mabi=vec-default/-mabi=vec-extabi, i.e compiling from .c to .ll and .c to .s 
> won't affect how driver works,
> 
> 2. `BackendUtil:551` The code I mentioned is actually affecting how BE 
> behaves when we enable AIX altivec in the FE[or driver]. So the testcase I am 
> looking for is something like:
> 
> ```
> // RUN:  %clang -target powerpc-unknown-aix -S -maltivec -mabi=vec-extabi %s  
> | FileCheck  %s
> // CHECK: LLVM ERROR: the extended Altivec AIX ABI is not yet supported
> ```
As far as I understand, testing the assembly path is a bit tricky mainly due to 
how Altivec is determined to be on for all powerpc targets.  

The tests in this file won't trigger the Altivec ABI errors because they are 
calling convention ABIs and there is no parameter passing or returns.  In fact, 
they will generate assembly because the default CPU has the Altivec attribute 
enabled.

I wrote tests that will use the Altivec calling convention ABI in those cases 
we  trigger earlier errors such as "vector type is unimplemented on AIX". 

But, I did a test which shows that the driver passes the `-mabi=vec-extabi` 
option. 



Comment at: llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll:2
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff 
-filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple 
powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj  --symbols %t.o | FileCheck %s
 

Xiangling_L wrote:
> I am not sure if this is for all testcases where you add `-mattr=-altivec`, 
> but I tried the first three. They all passed without this option. Could you 
> double check this?
You're right,it doesn't look like it's needed any longer. 


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[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 306696.
ZarkoCA marked an inline comment as done.
ZarkoCA added a comment.

Addressed comments and added a test to check whether the driver passes these 
options.


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/CodeGen/ppc64-vector.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix-vec-abi.ll

Index: llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
@@ -0,0 +1,12 @@
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+
+define void @vec_callee(<4 x i32> %vec1) {
+ret void 
+}
+
+; DFLTERROR:  LLVM ERROR: the default Altivec AIX ABI is not yet supported
+; VEXTERROR:  LLVM ERROR: the extended Altivec AIX ABI is not yet supported
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6968,6 +6968,16 @@
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
+  if (ValVT.isVector() && !State.getMachineFunction()
+   .getTarget()
+   .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the default Altivec AIX ABI is not yet supported");
+
+  if (ValVT.isVector() && State.getMachineFunction()
+  .getTarget()
+  .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the extended Altivec AIX ABI is not yet supported");
+
   assert((!ValVT.isInteger() ||
   (ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) &&
  "Integer argument exceeds register size: should have been legalized");
Index: llvm/lib/CodeGen/CommandFlags.cpp
===
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -58,6 +58,7 @@
 CGOPT(bool, EnableNoNaNsFPMath)
 CGOPT(bool, EnableNoSignedZerosFPMath)
 CGOPT(bool, EnableNoTrappingFPMath)
+CGOPT(bool, EnableAIXExtendedAltivecABI)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math)
 CGOPT(bool, EnableHonorSignDependentRoundingFPMath)
@@ -282,6 +283,11 @@
   cl::init(false));
   CGBINDOPT(DontPlaceZerosInBSS);
 
+  static cl::opt EnableAIXExtendedAltivecABI(
+  "vec-extabi", cl::desc("Enable the AIX Extended Altivec ABI."),
+  cl::init(false));
+  CGBINDOPT(EnableAIXExtendedAltivecABI);
+
   static cl::opt EnableGuaranteedTailCallOpt(
   "tailcallopt",
   cl::desc(
@@ -516,6 +522,7 @@
   getEnableHonorSignDependentRoundingFPMath();
   if (getFloatABIForCalls() != FloatABI::Default)
 Options.FloatABIType = getFloatABIForCalls();
+  Options.EnableAIXExtendedAltivecABI = getEnableAIXExtendedAltivecABI();
   Options.NoZerosInBSS = getDontPlaceZerosInBSS();
   Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt();
   Options.StackAlignmentOverride = getOverrideStackAlignment();
Index: llvm/include/llvm/Target/TargetOptions.h
===
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -124,6 +124,7 @@
 TargetOptions()
 : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
   NoTrappingFPMath(true), NoSignedZerosFPMath(false),
+  EnableAIXExtendedAltivecABI(false),
   HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
   GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
   EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
@@ -175,6 +176,12 @@
 /// argument

[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI and add clang and llvm option

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 298409.
ZarkoCA retitled this revision from "[PPC][AIX] Add vector callee saved 
registers for AIX extended vector ABI" to "[PPC][AIX] Add vector callee saved 
registers for AIX extended vector ABI and add clang and llvm option".
ZarkoCA edited the summary of this revision.
ZarkoCA added a comment.
Herald added subscribers: cfe-commits, dang, dmgreen, arphaman.
Herald added a project: clang.

Added `mvecnvol`/`mnovecnvol` options in clang and `vecnvol` option in llc
Addressed other comments related to formatting and test case regex usage. 
Updated test cases that fail when `vecnvol` is enabled.


Repository:
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
  llvm/test/CodeGen/PowerPC/aix-default-vec-abi.ll
  llvm/test/CodeGen/PowerPC/aix-func-align.ll
  llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
  llvm/test/CodeGen/PowerPC/aix-internal.ll
  llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
  llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
  llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-return55.ll
  llvm/test/CodeGen/PowerPC/aix-space.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
  llvm/test/CodeGen/PowerPC/aix32-crsave.mir
  llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
  llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
  llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
  llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

Index: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
===
--- llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -7,7 +7,7 @@
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -vecnvol \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
Index: llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
===
--- llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -vecnvol \
 ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr

[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI and add clang and llvm option

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 5 inline comments as done.
ZarkoCA added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll:4
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \

Xiangling_L wrote:
> The comments here let me think should we also implement an equivalent option 
> for `llc` to control which ABI to be enabled in addition to the frontend or 
> driver option?
Yes, good point, I added that as well. 



Comment at: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll:81
+
+; ASM32: li {{[0-9]+}}, -192
+; ASM32-DAG: stxvd2x 52, 1, {{[0-9]+}}   # 16-byte 
Folded Spill

Xiangling_L wrote:
> Xiangling_L wrote:
> > Can we line up all comments?
> I am suggesting to use things like `[[REG1:[0-9]+]]`  to match registers, use 
> `{{[0-9]+}}` to match numerical values if we need to. The same comments apply 
> to all testcases.
I'd rather not use any variables unless we need to use them later. 



Comment at: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll:120
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:- { id: 0, type: spill-slot, offset: -144, size: 16, 
alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v31', callee-saved-restored: 
true, debug-info-variable: '',

Xiangling_L wrote:
> Thank you for adding this testcase.  I think it would be better if we also 
> test`r13`/`x14`, `f14`, `v20`, then we can observe the padding added in. 
Good suggestion, I added. 



Comment at: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll:2
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN: FileCheck --check-prefix=MIR32 %s

hubert.reinterpretcast wrote:
> ZarkoCA wrote:
> > Xiangling_L wrote:
> > > ZarkoCA wrote:
> > > > Xiangling_L wrote:
> > > > > sfertile wrote:
> > > > > > Minor nit: align this with the first argument in the preceeding 
> > > > > > line.
> > > > > The ABI mentioned AIX5.3 is the first AIX release to enable vector 
> > > > > programming, and there are arch like pwr4 is not compatible with 
> > > > > altivec. Since this is our first altivec patch, it looks it's the 
> > > > > right place to add `report_fatal_error` for arch level which doesn't 
> > > > > support altivec.
> > > > While I think that's a good suggestion, none of the other PPC targets 
> > > > do anything similar.  If you choose an arch that doesn't support 
> > > > altivec while selecting a CPU that doesn't support it they quietly 
> > > > don't generate the altivec instructions.  
> > > > 
> > > > Also, as things are, we do have a report fatal error when ever someone 
> > > > tries using vector types in the front end and in the back end.  
> > > I see. The only reason why I raise it up is because XL gives an error 
> > > when using altivec with unsupported arch.
> > I see a warning and xlc and xlclang: 
> > `1506-1162 (W) The altivec option is not supported for the target 
> > architecture and is ignored.` 
> > Additionally with xlclang we get from the altivec.h header included in 
> > xlclang if an unsupported arch is specified.  
> > 
> > But this has me thinking that it is a good idea to follow through with your 
> > suggestion of an error. 
> Since the extended ABI vector-enabled mode is not the safe default (certain 
> call sequences involving functions compiled using the default ABI can bypass 
> restoration of the non-volatile register values), we should 
> `report_fatal_error` unless if the extended ABI is explicitly enabled.
> 
> Example:
> ```
> [ uses non-volatile vector registers ]
> vv   calls
> [ not vector-extended ABI-aware ] -- calls setjmp
> vv   calls
> [ uses non-volatile vector registers ]
> vv   calls
> [ not vector-extended ABI-aware ] -- calls longjmp
> ```
> 
> This follows the precedent for the `llc` default for data sections: Even for 
> `llc`, we do not enable the "unsafe" mode by default.
> 
I added the options to toggle between the two Altivec ABIs. 


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[PATCH] D89443: [PowerPC][AIX] Make `__vector [un]signed long` an error

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA accepted this revision.
ZarkoCA added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: clang/lib/Sema/DeclSpec.cpp:1200
+  // It has also been historically deprecated on AIX (as an alias for
+  // "vector int" in both 32-bit and 64-bit modes) and was made unsupported
+  // in the Clang-based XL compiler since the deprecated type has a number

minor nit, prefer to divide the comment in 2 sentences.  


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[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 307192.
ZarkoCA marked 3 inline comments as done.
ZarkoCA added a comment.

Addressed some of the comments.


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix-vec-abi.ll

Index: llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
@@ -0,0 +1,12 @@
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+
+define void @vec_callee(<4 x i32> %vec1) {
+ret void 
+}
+
+; DFLTERROR:  LLVM ERROR: the default Altivec AIX ABI is not yet supported
+; VEXTERROR:  LLVM ERROR: the extended Altivec AIX ABI is not yet supported
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6968,6 +6968,16 @@
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
+  if (ValVT.isVector() && !State.getMachineFunction()
+   .getTarget()
+   .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the default Altivec AIX ABI is not yet supported");
+
+  if (ValVT.isVector() && State.getMachineFunction()
+  .getTarget()
+  .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the extended Altivec AIX ABI is not yet supported");
+
   assert((!ValVT.isInteger() ||
   (ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) &&
  "Integer argument exceeds register size: should have been legalized");
Index: llvm/lib/CodeGen/CommandFlags.cpp
===
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -58,6 +58,7 @@
 CGOPT(bool, EnableNoNaNsFPMath)
 CGOPT(bool, EnableNoSignedZerosFPMath)
 CGOPT(bool, EnableNoTrappingFPMath)
+CGOPT(bool, EnableAIXExtendedAltivecABI)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math)
 CGOPT(bool, EnableHonorSignDependentRoundingFPMath)
@@ -282,6 +283,11 @@
   cl::init(false));
   CGBINDOPT(DontPlaceZerosInBSS);
 
+  static cl::opt EnableAIXExtendedAltivecABI(
+  "vec-extabi", cl::desc("Enable the AIX Extended Altivec ABI."),
+  cl::init(false));
+  CGBINDOPT(EnableAIXExtendedAltivecABI);
+
   static cl::opt EnableGuaranteedTailCallOpt(
   "tailcallopt",
   cl::desc(
@@ -516,6 +522,7 @@
   getEnableHonorSignDependentRoundingFPMath();
   if (getFloatABIForCalls() != FloatABI::Default)
 Options.FloatABIType = getFloatABIForCalls();
+  Options.EnableAIXExtendedAltivecABI = getEnableAIXExtendedAltivecABI();
   Options.NoZerosInBSS = getDontPlaceZerosInBSS();
   Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt();
   Options.StackAlignmentOverride = getOverrideStackAlignment();
Index: llvm/include/llvm/Target/TargetOptions.h
===
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -124,6 +124,7 @@
 TargetOptions()
 : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
   NoTrappingFPMath(true), NoSignedZerosFPMath(false),
+  EnableAIXExtendedAltivecABI(false),
   HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
   GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
   EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
@@ -175,6 +176,12 @@
 /// argument or result as insignificant.
 unsigned NoSignedZ

[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 307405.
ZarkoCA added a comment.

Went back to old option selection logic as updated version did not emit an 
error when selecting 'maltivec` but not `mabi=vec-extabi`.

Fixed formatting.


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix-vec-abi.ll

Index: llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
@@ -0,0 +1,12 @@
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+
+define void @vec_callee(<4 x i32> %vec1) {
+ret void 
+}
+
+; DFLTERROR:  LLVM ERROR: the default Altivec AIX ABI is not yet supported
+; VEXTERROR:  LLVM ERROR: the extended Altivec AIX ABI is not yet supported
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6968,6 +6968,16 @@
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
+  if (ValVT.isVector() && !State.getMachineFunction()
+   .getTarget()
+   .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the default Altivec AIX ABI is not yet supported");
+
+  if (ValVT.isVector() && State.getMachineFunction()
+  .getTarget()
+  .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the extended Altivec AIX ABI is not yet supported");
+
   assert((!ValVT.isInteger() ||
   (ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) &&
  "Integer argument exceeds register size: should have been legalized");
Index: llvm/lib/CodeGen/CommandFlags.cpp
===
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -58,6 +58,7 @@
 CGOPT(bool, EnableNoNaNsFPMath)
 CGOPT(bool, EnableNoSignedZerosFPMath)
 CGOPT(bool, EnableNoTrappingFPMath)
+CGOPT(bool, EnableAIXExtendedAltivecABI)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math)
 CGOPT(bool, EnableHonorSignDependentRoundingFPMath)
@@ -282,6 +283,11 @@
   cl::init(false));
   CGBINDOPT(DontPlaceZerosInBSS);
 
+  static cl::opt EnableAIXExtendedAltivecABI(
+  "vec-extabi", cl::desc("Enable the AIX Extended Altivec ABI."),
+  cl::init(false));
+  CGBINDOPT(EnableAIXExtendedAltivecABI);
+
   static cl::opt EnableGuaranteedTailCallOpt(
   "tailcallopt",
   cl::desc(
@@ -516,6 +522,7 @@
   getEnableHonorSignDependentRoundingFPMath();
   if (getFloatABIForCalls() != FloatABI::Default)
 Options.FloatABIType = getFloatABIForCalls();
+  Options.EnableAIXExtendedAltivecABI = getEnableAIXExtendedAltivecABI();
   Options.NoZerosInBSS = getDontPlaceZerosInBSS();
   Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt();
   Options.StackAlignmentOverride = getOverrideStackAlignment();
Index: llvm/include/llvm/Target/TargetOptions.h
===
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -124,6 +124,7 @@
 TargetOptions()
 : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
   NoTrappingFPMath(true), NoSignedZerosFPMath(false),
+  EnableAIXExtendedAltivecABI(false),
   HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
   GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
   EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
@@ -175,6 

[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 7 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/test/CodeGen/altivec.c:7
+ 
+// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -target 
powerpc-unknown-aix %s -o - | FileCheck %s
+// RUN: not %clang -S -emit-llvm -mabi=vec-default -target powerpc-unknown-aix 
%s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER

Xiangling_L wrote:
> When user specify `-maltivec / -target-feature +altivec`  without using any 
> abi option,  the compiler will assume default altivec abi. In this situation, 
> since default abi hasn’t been implemented, we should emit an error. So can we 
> also add testcases for :
> 
> ```
> // RUN: not %clang -S -emit-llvm -maltivec -target powerpc-unknown-aix %s 
> 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
> and
> // RUN: not %clang_cc1 -target-feature +altivec -triple powerpc-unknown-aix 
> -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
> ```
That's a good catch, the error was able to be generated previously but 
reworking the logic in Clang.cpp with the previous diff caused it to not be 
emitted.  I went back to the older logic which emits the error in cases like 
where `maltivec` is specified without `mabi=vec-extabi`.

As for the cc1 error, currently the not vector types error catch that before we 
emit the Altivec ABI error since at this time there isn't a good way to check 
for `target-feature +altivec` in cc1. 



Comment at: llvm/test/CodeGen/PowerPC/aix-vec-abi.ll:1
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | 
FileCheck %s --check-prefix=DFLTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | 
FileCheck %s --check-prefix=DFLTERROR

Xiangling_L wrote:
> May I ask why we use `pwr8` for this test?
Sorry for missing this earlier, I wanted to specify a CPU that has Altivec 
instructions enabled so that hasAltivec true without the user specifying it. 


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[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 307449.
ZarkoCA added a comment.

Simplified option logic as per suggestion.
Removed stray isXCOFF reference.


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix-vec-abi.ll

Index: llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
@@ -0,0 +1,12 @@
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+
+define void @vec_callee(<4 x i32> %vec1) {
+ret void 
+}
+
+; DFLTERROR:  LLVM ERROR: the default Altivec AIX ABI is not yet supported
+; VEXTERROR:  LLVM ERROR: the extended Altivec AIX ABI is not yet supported
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6968,6 +6968,16 @@
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
+  if (ValVT.isVector() && !State.getMachineFunction()
+   .getTarget()
+   .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the default Altivec AIX ABI is not yet supported");
+
+  if (ValVT.isVector() && State.getMachineFunction()
+  .getTarget()
+  .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the extended Altivec AIX ABI is not yet supported");
+
   assert((!ValVT.isInteger() ||
   (ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) &&
  "Integer argument exceeds register size: should have been legalized");
Index: llvm/lib/CodeGen/CommandFlags.cpp
===
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -58,6 +58,7 @@
 CGOPT(bool, EnableNoNaNsFPMath)
 CGOPT(bool, EnableNoSignedZerosFPMath)
 CGOPT(bool, EnableNoTrappingFPMath)
+CGOPT(bool, EnableAIXExtendedAltivecABI)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math)
 CGOPT(bool, EnableHonorSignDependentRoundingFPMath)
@@ -282,6 +283,11 @@
   cl::init(false));
   CGBINDOPT(DontPlaceZerosInBSS);
 
+  static cl::opt EnableAIXExtendedAltivecABI(
+  "vec-extabi", cl::desc("Enable the AIX Extended Altivec ABI."),
+  cl::init(false));
+  CGBINDOPT(EnableAIXExtendedAltivecABI);
+
   static cl::opt EnableGuaranteedTailCallOpt(
   "tailcallopt",
   cl::desc(
@@ -516,6 +522,7 @@
   getEnableHonorSignDependentRoundingFPMath();
   if (getFloatABIForCalls() != FloatABI::Default)
 Options.FloatABIType = getFloatABIForCalls();
+  Options.EnableAIXExtendedAltivecABI = getEnableAIXExtendedAltivecABI();
   Options.NoZerosInBSS = getDontPlaceZerosInBSS();
   Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt();
   Options.StackAlignmentOverride = getOverrideStackAlignment();
Index: llvm/include/llvm/Target/TargetOptions.h
===
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -124,6 +124,7 @@
 TargetOptions()
 : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
   NoTrappingFPMath(true), NoSignedZerosFPMath(false),
+  EnableAIXExtendedAltivecABI(false),
   HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
   GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
   EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
@@ -175,6 +176,12 @@
 /// argument or result as insignificant.
 unsigned NoSigne

[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 7 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4624
+
+  if (Triple.isOSAIX()) {
+if (Args.hasArg(options::OPT_maltivec) &&

Xiangling_L wrote:
> line 4624 to line 4635 can be simplified to :
> 
> ```
>   if (Triple.isOSAIX() && Args.hasArg(options::OPT_maltivec) {
> if (Args.hasArg(options::OPT_mabi_EQ_vec_extabi)) {
>   CmdArgs.push_back("-mabi=vec-extabi");
> } else {
>   D.Diag(diag::err_aix_default_altivec_abi);
> }
>   }
> ```
> 
> or even simplify line 4617 -4636 to the following if it works:
> 
> ```
>   if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ_vec_extabi,
>options::OPT_mabi_EQ_vec_default)) {
> if (!Triple.isOSAIX())
>   D.Diag(diag::err_drv_unsupported_opt_for_target)
>   << A->getSpelling() << RawTriple.str();
> 
> if (!Args.hasArg(options::OPT_maltivec))
>   D.Diag(diag::err_aix_altivec);
> 
> if (Args.hasArg(options::OPT_mabi_EQ_vec_default))
>   D.Diag(diag::err_aix_default_altivec_abi);
> 
> CmdArgs.push_back("-mabi=vec-extabi");
>   } else if (Triple.isOSAIX() && Args.hasArg(options::OPT_maltivec) {
>   D.Diag(diag::err_aix_default_altivec_abi);
>   }
> ```
I really like the first suggestion, thank you. 



Comment at: clang/lib/Frontend/CompilerInvocation.cpp:1445
+  Args.getLastArg(OPT_mabi_EQ_vec_default, OPT_mabi_EQ_vec_extabi)) {
+if (!T.isOSAIX() || !T.isOSBinFormatXCOFF())
+  Diags.Report(diag::err_drv_unsupported_opt_for_target)

Xiangling_L wrote:
> Hi Zarko, is the above comment missed being addressed?
Sorry, that one snuck back in there after I thought I removed it. 


Repository:
  rG LLVM Github Monorepo

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[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
ZarkoCA marked 2 inline comments as done.
Closed by commit rGc92f29b05e68: [AIX] Add mabi=vec-extabi options to enable 
the AIX extended and default vector… (authored by ZarkoCA).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89684/new/

https://reviews.llvm.org/D89684

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix-vec-abi.ll

Index: llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-vec-abi.ll
@@ -0,0 +1,12 @@
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
+
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi 2>&1 | FileCheck %s --check-prefix=VEXTERROR
+
+define void @vec_callee(<4 x i32> %vec1) {
+ret void 
+}
+
+; DFLTERROR:  LLVM ERROR: the default Altivec AIX ABI is not yet supported
+; VEXTERROR:  LLVM ERROR: the extended Altivec AIX ABI is not yet supported
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6968,6 +6968,16 @@
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
+  if (ValVT.isVector() && !State.getMachineFunction()
+   .getTarget()
+   .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the default Altivec AIX ABI is not yet supported");
+
+  if (ValVT.isVector() && State.getMachineFunction()
+  .getTarget()
+  .Options.EnableAIXExtendedAltivecABI)
+report_fatal_error("the extended Altivec AIX ABI is not yet supported");
+
   assert((!ValVT.isInteger() ||
   (ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) &&
  "Integer argument exceeds register size: should have been legalized");
Index: llvm/lib/CodeGen/CommandFlags.cpp
===
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -58,6 +58,7 @@
 CGOPT(bool, EnableNoNaNsFPMath)
 CGOPT(bool, EnableNoSignedZerosFPMath)
 CGOPT(bool, EnableNoTrappingFPMath)
+CGOPT(bool, EnableAIXExtendedAltivecABI)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math)
 CGOPT(bool, EnableHonorSignDependentRoundingFPMath)
@@ -282,6 +283,11 @@
   cl::init(false));
   CGBINDOPT(DontPlaceZerosInBSS);
 
+  static cl::opt EnableAIXExtendedAltivecABI(
+  "vec-extabi", cl::desc("Enable the AIX Extended Altivec ABI."),
+  cl::init(false));
+  CGBINDOPT(EnableAIXExtendedAltivecABI);
+
   static cl::opt EnableGuaranteedTailCallOpt(
   "tailcallopt",
   cl::desc(
@@ -516,6 +522,7 @@
   getEnableHonorSignDependentRoundingFPMath();
   if (getFloatABIForCalls() != FloatABI::Default)
 Options.FloatABIType = getFloatABIForCalls();
+  Options.EnableAIXExtendedAltivecABI = getEnableAIXExtendedAltivecABI();
   Options.NoZerosInBSS = getDontPlaceZerosInBSS();
   Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt();
   Options.StackAlignmentOverride = getOverrideStackAlignment();
Index: llvm/include/llvm/Target/TargetOptions.h
===
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -124,6 +124,7 @@
 TargetOptions()
 : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
   NoTrappingFPMath(true), NoSignedZerosFPMath(false),
+  EnableAIXExtendedAltivecABI(false),
   HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
   GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
   EnableFastISel(false), EnableGlobalISel(false), UseI

[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 307499.
ZarkoCA added a comment.

Seems a few test cases require `mattr=-altivec` to pass with this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88676/new/

https://reviews.llvm.org/D88676

Files:
  llvm/include/llvm/Target/TargetMachine.h
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
  llvm/test/CodeGen/PowerPC/aix-func-align.ll
  llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
  llvm/test/CodeGen/PowerPC/aix-internal.ll
  llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
  llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
  llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-return55.ll
  llvm/test/CodeGen/PowerPC/aix-space.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
  llvm/test/CodeGen/PowerPC/aix32-crsave.mir
  llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
  llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
  llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
  llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

Index: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
===
--- llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -1,13 +1,13 @@
-# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 \
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE
 
-# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 \
+# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
Index: llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
===
--- llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
 
 ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/Po

[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbe7d425edc64: [PPC][AIX] Add vector callee saved registers 
for AIX extended vector ABI (authored by ZarkoCA).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88676/new/

https://reviews.llvm.org/D88676

Files:
  llvm/include/llvm/Target/TargetMachine.h
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
  llvm/test/CodeGen/PowerPC/aix-func-align.ll
  llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
  llvm/test/CodeGen/PowerPC/aix-internal.ll
  llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
  llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
  llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-return55.ll
  llvm/test/CodeGen/PowerPC/aix-space.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
  llvm/test/CodeGen/PowerPC/aix32-crsave.mir
  llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
  llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
  llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
  llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

Index: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
===
--- llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -1,13 +1,13 @@
-# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 \
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE
 
-# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 \
+# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
Index: llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
===
--- llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
 
 ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: 

[PATCH] D92117: [AIX] Enabling vectory types for AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA created this revision.
ZarkoCA added reviewers: cebowleratibm, sfertile, jasonliu, Xiangling_L, 
hubert.reinterpretcast.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
ZarkoCA requested review of this revision.

This patch enables vector types for AIX.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92117

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-altivec.c
  clang/test/CodeGen/aix-vector.c

Index: clang/test/CodeGen/aix-vector.c
===
--- clang/test/CodeGen/aix-vector.c
+++ /dev/null
@@ -1,10 +0,0 @@
-// REQUIRES: powerpc-registered-target
-// RUN: not %clang_cc1 -triple powerpc-unknown-aix  -target-feature +altivec \
-// RUN:   -emit-llvm -o - %s 2>&1 | FileCheck %s
-// RUN: not %clang_cc1 -triple powerpc64-unknown-aix  -target-feature +altivec \
-// RUN:   -emit-llvm -o - %s 2>&1 | FileCheck %s
-
-// CHECK: fatal error: error in backend: vector type is not supported on AIX yet
-vector signed int retVector(vector signed int x) {
-  return x;
-}
Index: clang/test/CodeGen/aix-altivec.c
===
--- /dev/null
+++ clang/test/CodeGen/aix-altivec.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
+vector float foo1(vector float x) { return x; }
+// CHECK:  define <4 x float> @foo1(<4 x float> %x) #0 {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <4 x float>, align 16
+// CHECK:store <4 x float> %x, <4 x float>* %x.addr, align 16
+// CHECK:%0 = load <4 x float>, <4 x float>* %x.addr, align 16
+// CHECK:ret <4 x float> %0
+// CHECK:  }
+vector double foo2(vector double x) { return x; }
+// CHECK:  define <2 x double> @foo2(<2 x double> %x) #0 {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <2 x double>, align 16
+// CHECK:store <2 x double> %x, <2 x double>* %x.addr, align 16
+// CHECK:%0 = load <2 x double>, <2 x double>* %x.addr, align 16
+// CHECK:ret <2 x double> %0
+// CHECK:  }
+vector int foo3(vector int x) { return x; }
+// CHECK:  define <4 x i32> @foo3(<4 x i32> %x) #0 {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <4 x i32>, align 16
+// CHECK:store <4 x i32> %x, <4 x i32>* %x.addr, align 16
+// CHECK:%0 = load <4 x i32>, <4 x i32>* %x.addr, align 16
+// CHECK:ret <4 x i32> %0
+// CHECK:  }
+vector short int foo4(vector short int x) { return x; }
+// CHECK:  define <8 x i16> @foo4(<8 x i16> %x) #0 {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <8 x i16>, align 16
+// CHECK:store <8 x i16> %x, <8 x i16>* %x.addr, align 16
+// CHECK:%0 = load <8 x i16>, <8 x i16>* %x.addr, align 16
+// CHECK:ret <8 x i16> %0
+// CHECK:  }
+vector char foo5(vector char x) { return x; }
+// CHECK:  define <16 x i8> @foo5(<16 x i8> %x) #0 {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <16 x i8>, align 16
+// CHECK:store <16 x i8> %x, <16 x i8>* %x.addr, align 16
+// CHECK:%0 = load <16 x i8>, <16 x i8>* %x.addr, align 16
+// CHECK:ret <16 x i8> %0
+// CHECK:  }
+
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -4514,7 +4514,7 @@
 return ABIArgInfo::getDirect();
 
   if (RetTy->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return ABIArgInfo::getDirect();
 
   if (RetTy->isVoidType())
 return ABIArgInfo::getIgnore();
@@ -4533,7 +4533,7 @@
 return ABIArgInfo::getDirect();
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return ABIArgInfo::getDirect();
 
   if (isAggregateTypeForABI(Ty)) {
 // Records with non-trivial destructors/copy-constructors should not be
@@ -4558,7 +4558,7 @@
 Ty = CTy->getElementType();
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return CharUnits::fromQuantity(16);
 
   // If the structure contains a vector type, the alignment is 16.
   if (isRecordWithSIMDVectorType(getContext(), Ty))
@@ -4573,7 +4573,8 @@
 llvm::report_fatal_error("complex type is not supported on AIX yet");
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+llvm::report_fatal_error(
+"vector types are not yet supported for variadic functions on AIX");
 
   auto TypeInfo = getContext().getTypeInfoInChars(Ty);
   TypeInfo.Align = getParamTypeAlignment(Ty);
___
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[PATCH] D92117: [AIX] Enabling vector types for AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 307748.
ZarkoCA added a comment.

Added regex and variable for function attribute


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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-altivec.c
  clang/test/CodeGen/aix-vector.c

Index: clang/test/CodeGen/aix-vector.c
===
--- clang/test/CodeGen/aix-vector.c
+++ /dev/null
@@ -1,10 +0,0 @@
-// REQUIRES: powerpc-registered-target
-// RUN: not %clang_cc1 -triple powerpc-unknown-aix  -target-feature +altivec \
-// RUN:   -emit-llvm -o - %s 2>&1 | FileCheck %s
-// RUN: not %clang_cc1 -triple powerpc64-unknown-aix  -target-feature +altivec \
-// RUN:   -emit-llvm -o - %s 2>&1 | FileCheck %s
-
-// CHECK: fatal error: error in backend: vector type is not supported on AIX yet
-vector signed int retVector(vector signed int x) {
-  return x;
-}
Index: clang/test/CodeGen/aix-altivec.c
===
--- /dev/null
+++ clang/test/CodeGen/aix-altivec.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
+vector float foo1(vector float x) { return x; }
+// CHECK:  define <4 x float> @foo1(<4 x float> %x) [[ATTR:#[0-9]+]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <4 x float>, align 16
+// CHECK:store <4 x float> %x, <4 x float>* %x.addr, align 16
+// CHECK:%0 = load <4 x float>, <4 x float>* %x.addr, align 16
+// CHECK:ret <4 x float> %0
+// CHECK:  }
+vector double foo2(vector double x) { return x; }
+// CHECK:  define <2 x double> @foo2(<2 x double> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <2 x double>, align 16
+// CHECK:store <2 x double> %x, <2 x double>* %x.addr, align 16
+// CHECK:%0 = load <2 x double>, <2 x double>* %x.addr, align 16
+// CHECK:ret <2 x double> %0
+// CHECK:  }
+vector int foo3(vector int x) { return x; }
+// CHECK:  define <4 x i32> @foo3(<4 x i32> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <4 x i32>, align 16
+// CHECK:store <4 x i32> %x, <4 x i32>* %x.addr, align 16
+// CHECK:%0 = load <4 x i32>, <4 x i32>* %x.addr, align 16
+// CHECK:ret <4 x i32> %0
+// CHECK:  }
+vector short int foo4(vector short int x) { return x; }
+// CHECK:  define <8 x i16> @foo4(<8 x i16> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <8 x i16>, align 16
+// CHECK:store <8 x i16> %x, <8 x i16>* %x.addr, align 16
+// CHECK:%0 = load <8 x i16>, <8 x i16>* %x.addr, align 16
+// CHECK:ret <8 x i16> %0
+// CHECK:  }
+vector char foo5(vector char x) { return x; }
+// CHECK:  define <16 x i8> @foo5(<16 x i8> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <16 x i8>, align 16
+// CHECK:store <16 x i8> %x, <16 x i8>* %x.addr, align 16
+// CHECK:%0 = load <16 x i8>, <16 x i8>* %x.addr, align 16
+// CHECK:ret <16 x i8> %0
+// CHECK:  }
+
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -4514,7 +4514,7 @@
 return ABIArgInfo::getDirect();
 
   if (RetTy->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return ABIArgInfo::getDirect();
 
   if (RetTy->isVoidType())
 return ABIArgInfo::getIgnore();
@@ -4533,7 +4533,7 @@
 return ABIArgInfo::getDirect();
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return ABIArgInfo::getDirect();
 
   if (isAggregateTypeForABI(Ty)) {
 // Records with non-trivial destructors/copy-constructors should not be
@@ -4558,7 +4558,7 @@
 Ty = CTy->getElementType();
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return CharUnits::fromQuantity(16);
 
   // If the structure contains a vector type, the alignment is 16.
   if (isRecordWithSIMDVectorType(getContext(), Ty))
@@ -4573,7 +4573,8 @@
 llvm::report_fatal_error("complex type is not supported on AIX yet");
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+llvm::report_fatal_error(
+"vector types are not yet supported for variadic functions on AIX");
 
   auto TypeInfo = getContext().getTypeInfoInChars(Ty);
   TypeInfo.Align = getParamTypeAlignment(Ty);
___
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[PATCH] D78903: [Driver] Add option -fproc-stat-report

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/Driver/report-stat.c:1
+// RUN: %clang -c -fproc-stat-report %s | FileCheck %s
+// CHECK: clang{{.*}}: output={{.*}}.o, total={{[0-9.]+}} ms, user={{[0-9.]+}} 
ms, mem={{[0-9]+}} Kb

Hi @sepavloff, is it possible to add `-fintegrated-as` to the clang invocation? 
 

As it is, the test fails on our AIX target because we don't use the integrated 
assembler by default. 


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[PATCH] D92117: [AIX] Enabling vector type arguments and return for AIX

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGff8e8c1b14ea: [AIX] Enabling vector type arguments and 
return for AIX (authored by ZarkoCA).

Repository:
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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix-altivec.c
  clang/test/CodeGen/aix-vector.c

Index: clang/test/CodeGen/aix-vector.c
===
--- clang/test/CodeGen/aix-vector.c
+++ /dev/null
@@ -1,10 +0,0 @@
-// REQUIRES: powerpc-registered-target
-// RUN: not %clang_cc1 -triple powerpc-unknown-aix  -target-feature +altivec \
-// RUN:   -emit-llvm -o - %s 2>&1 | FileCheck %s
-// RUN: not %clang_cc1 -triple powerpc64-unknown-aix  -target-feature +altivec \
-// RUN:   -emit-llvm -o - %s 2>&1 | FileCheck %s
-
-// CHECK: fatal error: error in backend: vector type is not supported on AIX yet
-vector signed int retVector(vector signed int x) {
-  return x;
-}
Index: clang/test/CodeGen/aix-altivec.c
===
--- /dev/null
+++ clang/test/CodeGen/aix-altivec.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
+vector float foo1(vector float x) { return x; }
+// CHECK:  define <4 x float> @foo1(<4 x float> %x) [[ATTR:#[0-9]+]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <4 x float>, align 16
+// CHECK:store <4 x float> %x, <4 x float>* %x.addr, align 16
+// CHECK:%0 = load <4 x float>, <4 x float>* %x.addr, align 16
+// CHECK:ret <4 x float> %0
+// CHECK:  }
+vector double foo2(vector double x) { return x; }
+// CHECK:  define <2 x double> @foo2(<2 x double> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <2 x double>, align 16
+// CHECK:store <2 x double> %x, <2 x double>* %x.addr, align 16
+// CHECK:%0 = load <2 x double>, <2 x double>* %x.addr, align 16
+// CHECK:ret <2 x double> %0
+// CHECK:  }
+vector int foo3(vector int x) { return x; }
+// CHECK:  define <4 x i32> @foo3(<4 x i32> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <4 x i32>, align 16
+// CHECK:store <4 x i32> %x, <4 x i32>* %x.addr, align 16
+// CHECK:%0 = load <4 x i32>, <4 x i32>* %x.addr, align 16
+// CHECK:ret <4 x i32> %0
+// CHECK:  }
+vector short int foo4(vector short int x) { return x; }
+// CHECK:  define <8 x i16> @foo4(<8 x i16> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <8 x i16>, align 16
+// CHECK:store <8 x i16> %x, <8 x i16>* %x.addr, align 16
+// CHECK:%0 = load <8 x i16>, <8 x i16>* %x.addr, align 16
+// CHECK:ret <8 x i16> %0
+// CHECK:  }
+vector char foo5(vector char x) { return x; }
+// CHECK:  define <16 x i8> @foo5(<16 x i8> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <16 x i8>, align 16
+// CHECK:store <16 x i8> %x, <16 x i8>* %x.addr, align 16
+// CHECK:%0 = load <16 x i8>, <16 x i8>* %x.addr, align 16
+// CHECK:ret <16 x i8> %0
+// CHECK:  }
+
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -4514,7 +4514,7 @@
 return ABIArgInfo::getDirect();
 
   if (RetTy->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return ABIArgInfo::getDirect();
 
   if (RetTy->isVoidType())
 return ABIArgInfo::getIgnore();
@@ -4533,7 +4533,7 @@
 return ABIArgInfo::getDirect();
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return ABIArgInfo::getDirect();
 
   if (isAggregateTypeForABI(Ty)) {
 // Records with non-trivial destructors/copy-constructors should not be
@@ -4558,7 +4558,7 @@
 Ty = CTy->getElementType();
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return CharUnits::fromQuantity(16);
 
   // If the structure contains a vector type, the alignment is 16.
   if (isRecordWithSIMDVectorType(getContext(), Ty))
@@ -4573,7 +4573,8 @@
 llvm::report_fatal_error("complex type is not supported on AIX yet");
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+llvm::report_fatal_error(
+"vector types are not yet supported for variadic functions on AIX");
 
   auto TypeInfo = getContext().getTypeInfoInChars(Ty);
   TypeInfo.Align = getParamTypeAlignment(Ty);
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[PATCH] D78903: [Driver] Add option -fproc-stat-report

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/Driver/report-stat.c:1
+// RUN: %clang -c -fproc-stat-report %s | FileCheck %s
+// CHECK: clang{{.*}}: output={{.*}}.o, total={{[0-9.]+}} ms, user={{[0-9.]+}} 
ms, mem={{[0-9]+}} Kb

ZarkoCA wrote:
> Hi @sepavloff, is it possible to add `-fintegrated-as` to the clang 
> invocation?  
> 
> As it is, the test fails on our AIX target because we don't use the 
> integrated assembler by default. 
fyi, I added the option in  `979bcbd3a6f7ea784f2098ad4cf613fbd6b09e38` 


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[PATCH] D89684: [AIX] Add mvecnvol and mnovecnvol options to enable the AIX extended and default vector ABIs.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA created this revision.
ZarkoCA added reviewers: Xiangling_L, cebowleratibm, sfertile.
Herald added subscribers: llvm-commits, cfe-commits, dang, dmgreen, arphaman, 
kbarton, hiraditya, nemanjai.
Herald added projects: clang, LLVM.
ZarkoCA requested review of this revision.

Added support for the options mvecnvol and mnovecnvol which are analogous to 
qvecnvol and qnovecnvol when using XL on AIX.
The extended Altivec ABI on AIX is enabled using mvecnvol in clang and vecnvol 
in llc.


Repository:
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https://reviews.llvm.org/D89684

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-default-vec-abi.ll
  llvm/test/CodeGen/PowerPC/aix-func-align.ll
  llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
  llvm/test/CodeGen/PowerPC/aix-internal.ll
  llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
  llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
  llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-return55.ll
  llvm/test/CodeGen/PowerPC/aix-space.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
  llvm/test/CodeGen/PowerPC/aix32-crsave.mir
  llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
  llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
  llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
  llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

Index: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
===
--- llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -7,7 +7,7 @@
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -vecnvol \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
Index: llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
===
--- llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -vecnvol \
 ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
===
--- llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/aix32-crsave.mir
===
--- llvm/test/CodeGen/PowerPC/aix32-crsave.mir
+++ llvm/tes

[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 298991.
ZarkoCA marked 3 inline comments as done.
ZarkoCA retitled this revision from "[PPC][AIX] Add vector callee saved 
registers for AIX extended vector ABI and add clang and llvm option" to 
"[PPC][AIX] Add vector callee saved registers for AIX extended vector ABI".
ZarkoCA edited the summary of this revision.
ZarkoCA added a comment.

Separated the option portion of the previous diff (now found here: 
https://reviews.llvm.org/D89684).
Addressed other comments.


Repository:
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Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

Index: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -0,0 +1,308 @@
+ RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vecnvol -verify-machineinstrs -mcpu=pwr7 \
+; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM64 %s
+
+
+define dso_local void @vec_regs() {
+entry:
+  call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32: name:vec_regs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:stack:
+
+; MIR32: liveins: $v20, $v26, $v31
+
+; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR32: INLINEASM
+
+; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG: $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32: BLR implicit $lr, implicit $rm
+
+; MIR64: name:vec_regs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:stack:
+
+; MIR64: liveins: $v20, $v26, $v31
+
+; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64: INLINEASM
+
+; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; M

[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 298994.
ZarkoCA added a comment.

Fixed typo in test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88676/new/

https://reviews.llvm.org/D88676

Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

Index: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -0,0 +1,308 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vecnvol -verify-machineinstrs -mcpu=pwr7 \
+; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM64 %s
+
+
+define dso_local void @vec_regs() {
+entry:
+  call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32: name:vec_regs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:stack:
+
+; MIR32: liveins: $v20, $v26, $v31
+
+; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR32: INLINEASM
+
+; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG: $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32: BLR implicit $lr, implicit $rm
+
+; MIR64: name:vec_regs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:- { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:- { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:- { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:stack:
+
+; MIR64: liveins: $v20, $v26, $v31
+
+; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64: INLINEASM
+
+; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG: $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64: BLR8 implicit $lr8, implicit $rm
+
+
+; ASM32-LABEL:   .vec_regs:
+
+; ASM32: li {{[0-9]+}}, -192
+; ASM32-DAG: stxvd2x 52, 1, {{[0-9]+}}   # 16-byte Folded Spill
+; ASM32-DAG: li {{[0-9]+}

[PATCH] D102064: Parse vector bool when stdbool.h and altivec.h are included

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 344785.
ZarkoCA added a comment.

- Rename test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102064/new/

https://reviews.llvm.org/D102064

Files:
  clang/include/clang/Parse/Parser.h
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/Parser.cpp
  clang/test/Parser/altivec-zvector-bool.c

Index: clang/test/Parser/altivec-zvector-bool.c
===
--- /dev/null
+++ clang/test/Parser/altivec-zvector-bool.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=powerpc64-ibm-aix-xcoff \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=powerpc-ibm-aix-xcoff \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=powerpc-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=s390x-linux-gnu -target-cpu arch11 \
+// RUN:-fzvector -fsyntax-only %s
+// RUN: %clang_cc1 -triple=s390x-ibm-zos -target-cpu arch11 \
+// RUN:-fzvector -fsyntax-only %s
+
+__vector bool char bc;
+__vector bool short bsh;
+__vector bool short int bshi;
+__vector bool int bi;
+__vector _Bool char Bc;
+__vector _Bool short Bsh;
+__vector _Bool short int Bshi;
+__vector _Bool int Bi;
Index: clang/lib/Parse/Parser.cpp
===
--- clang/lib/Parse/Parser.cpp
+++ clang/lib/Parse/Parser.cpp
@@ -503,10 +503,12 @@
 
   Ident_vector = nullptr;
   Ident_bool = nullptr;
+  Ident_Bool = nullptr;
   Ident_pixel = nullptr;
   if (getLangOpts().AltiVec || getLangOpts().ZVector) {
 Ident_vector = &PP.getIdentifierTable().get("vector");
 Ident_bool = &PP.getIdentifierTable().get("bool");
+Ident_Bool = &PP.getIdentifierTable().get("_Bool");
   }
   if (getLangOpts().AltiVec)
 Ident_pixel = &PP.getIdentifierTable().get("pixel");
Index: clang/lib/Parse/ParseDecl.cpp
===
--- clang/lib/Parse/ParseDecl.cpp
+++ clang/lib/Parse/ParseDecl.cpp
@@ -7334,6 +7334,7 @@
   case tok::kw_float:
   case tok::kw_double:
   case tok::kw_bool:
+  case tok::kw__Bool:
   case tok::kw___bool:
   case tok::kw___pixel:
 Tok.setKind(tok::kw___vector);
@@ -7343,7 +7344,8 @@
   Tok.setKind(tok::kw___vector);
   return true;
 }
-if (Next.getIdentifierInfo() == Ident_bool) {
+if (Next.getIdentifierInfo() == Ident_bool ||
+Next.getIdentifierInfo() == Ident_Bool) {
   Tok.setKind(tok::kw___vector);
   return true;
 }
@@ -7368,6 +7370,7 @@
 case tok::kw_float:
 case tok::kw_double:
 case tok::kw_bool:
+case tok::kw__Bool:
 case tok::kw___bool:
 case tok::kw___pixel:
   isInvalid = DS.SetTypeAltiVecVector(true, Loc, PrevSpec, DiagID, Policy);
@@ -7377,8 +7380,10 @@
 isInvalid = DS.SetTypeAltiVecVector(true, Loc, PrevSpec, DiagID,Policy);
 return true;
   }
-  if (Next.getIdentifierInfo() == Ident_bool) {
-isInvalid = DS.SetTypeAltiVecVector(true, Loc, PrevSpec, DiagID,Policy);
+  if (Next.getIdentifierInfo() == Ident_bool ||
+  Next.getIdentifierInfo() == Ident_Bool) {
+isInvalid =
+DS.SetTypeAltiVecVector(true, Loc, PrevSpec, DiagID, Policy);
 return true;
   }
   break;
Index: clang/include/clang/Parse/Parser.h
===
--- clang/include/clang/Parse/Parser.h
+++ clang/include/clang/Parse/Parser.h
@@ -118,10 +118,12 @@
   /// Ident_super - IdentifierInfo for "super", to support fast
   /// comparison.
   IdentifierInfo *Ident_super;
-  /// Ident_vector, Ident_bool - cached IdentifierInfos for "vector" and
-  /// "bool" fast comparison.  Only present if AltiVec or ZVector are enabled.
+  /// Ident_vector, Ident_bool, Ident_Bool - cached IdentifierInfos for "vector"
+  /// and "bool" fast comparison.  Only present if AltiVec or ZVector are
+  /// enabled.
   IdentifierInfo *Ident_vector;
   IdentifierInfo *Ident_bool;
+  IdentifierInfo *Ident_Bool;
   /// Ident_pixel - cached IdentifierInfos for "pixel" fast comparison.
   /// Only present if AltiVec enabled.
   IdentifierInfo *Ident_pixel;
@@ -879,6 +881,7 @@
 
 if (Tok.getIdentifierInfo() != Ident_vector &&
 Tok.getIdentifierInfo() != Ident_bool &&
+Tok.getIdentifierInfo() != Ident_Bool &&
 (!getLangOpts().AltiVec || Tok.getIdentifierInfo() != Ident_pixel))
   return false;
 
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[PATCH] D102064: Parse vector bool when stdbool.h and altivec.h are included

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8fa168fc50ba: Parse vector bool when stdbool.h and altivec.h 
are included (authored by ZarkoCA).

Changed prior to commit:
  https://reviews.llvm.org/D102064?vs=344785&id=345157#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102064/new/

https://reviews.llvm.org/D102064

Files:
  clang/include/clang/Parse/Parser.h
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/Parser.cpp
  clang/test/Parser/altivec-zvector-bool.c

Index: clang/test/Parser/altivec-zvector-bool.c
===
--- /dev/null
+++ clang/test/Parser/altivec-zvector-bool.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=powerpc64-ibm-aix-xcoff \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=powerpc-ibm-aix-xcoff \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=powerpc-unknown-linux-gnu \
+// RUN:-target-feature +altivec -fsyntax-only %s
+// RUN: %clang_cc1 -triple=s390x-linux-gnu -target-cpu arch11 \
+// RUN:-fzvector -fsyntax-only %s
+// RUN: %clang_cc1 -triple=s390x-ibm-zos -target-cpu arch11 \
+// RUN:-fzvector -fsyntax-only %s
+
+__vector bool char bc;
+__vector bool short bsh;
+__vector bool short int bshi;
+__vector bool int bi;
+__vector _Bool char bc;
+__vector _Bool short bsh;
+__vector _Bool short int bshi;
+__vector _Bool int bi;
Index: clang/lib/Parse/Parser.cpp
===
--- clang/lib/Parse/Parser.cpp
+++ clang/lib/Parse/Parser.cpp
@@ -503,10 +503,12 @@
 
   Ident_vector = nullptr;
   Ident_bool = nullptr;
+  Ident_Bool = nullptr;
   Ident_pixel = nullptr;
   if (getLangOpts().AltiVec || getLangOpts().ZVector) {
 Ident_vector = &PP.getIdentifierTable().get("vector");
 Ident_bool = &PP.getIdentifierTable().get("bool");
+Ident_Bool = &PP.getIdentifierTable().get("_Bool");
   }
   if (getLangOpts().AltiVec)
 Ident_pixel = &PP.getIdentifierTable().get("pixel");
Index: clang/lib/Parse/ParseDecl.cpp
===
--- clang/lib/Parse/ParseDecl.cpp
+++ clang/lib/Parse/ParseDecl.cpp
@@ -7334,6 +7334,7 @@
   case tok::kw_float:
   case tok::kw_double:
   case tok::kw_bool:
+  case tok::kw__Bool:
   case tok::kw___bool:
   case tok::kw___pixel:
 Tok.setKind(tok::kw___vector);
@@ -7343,7 +7344,8 @@
   Tok.setKind(tok::kw___vector);
   return true;
 }
-if (Next.getIdentifierInfo() == Ident_bool) {
+if (Next.getIdentifierInfo() == Ident_bool ||
+Next.getIdentifierInfo() == Ident_Bool) {
   Tok.setKind(tok::kw___vector);
   return true;
 }
@@ -7368,6 +7370,7 @@
 case tok::kw_float:
 case tok::kw_double:
 case tok::kw_bool:
+case tok::kw__Bool:
 case tok::kw___bool:
 case tok::kw___pixel:
   isInvalid = DS.SetTypeAltiVecVector(true, Loc, PrevSpec, DiagID, Policy);
@@ -7377,8 +7380,10 @@
 isInvalid = DS.SetTypeAltiVecVector(true, Loc, PrevSpec, DiagID,Policy);
 return true;
   }
-  if (Next.getIdentifierInfo() == Ident_bool) {
-isInvalid = DS.SetTypeAltiVecVector(true, Loc, PrevSpec, DiagID,Policy);
+  if (Next.getIdentifierInfo() == Ident_bool ||
+  Next.getIdentifierInfo() == Ident_Bool) {
+isInvalid =
+DS.SetTypeAltiVecVector(true, Loc, PrevSpec, DiagID, Policy);
 return true;
   }
   break;
Index: clang/include/clang/Parse/Parser.h
===
--- clang/include/clang/Parse/Parser.h
+++ clang/include/clang/Parse/Parser.h
@@ -118,10 +118,12 @@
   /// Ident_super - IdentifierInfo for "super", to support fast
   /// comparison.
   IdentifierInfo *Ident_super;
-  /// Ident_vector, Ident_bool - cached IdentifierInfos for "vector" and
-  /// "bool" fast comparison.  Only present if AltiVec or ZVector are enabled.
+  /// Ident_vector, Ident_bool, Ident_Bool - cached IdentifierInfos for "vector"
+  /// and "bool" fast comparison.  Only present if AltiVec or ZVector are
+  /// enabled.
   IdentifierInfo *Ident_vector;
   IdentifierInfo *Ident_bool;
+  IdentifierInfo *Ident_Bool;
   /// Ident_pixel - cached IdentifierInfos for "pixel" fast comparison.
   /// Only present if AltiVec enabled.
   IdentifierInfo *Ident_pixel;
@@ -879,6 +881,7 @@
 
 if (Tok.getIdentifierInfo() != Ident_vector &&
 Tok.getIdentifierInfo() != Ident_bool &&
+Tok.getIdentifierInfo() != Ident_Bool &&
 (!getLangOpts().Al

[PATCH] D100991: Fix parsing of vector keyword in presence of conflicting uses.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/Parser/altivec-non-type-vector.c:1
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix-xcoff -target-feature 
+altivec -fsyntax-only %s
+

Can you add tests for 64bit BE/LE linux and 32bit AIX/BE linux in this the 
subsequent test cases? 


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https://reviews.llvm.org/D100991

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[PATCH] D100991: Fix parsing of vector keyword in presence of conflicting uses.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/Parser/altivec-non-type-vector.c:1-24
+// RUN: %clang_cc1 -target-feature +altivec -fsyntax-only %s -triple 
powerpc64-ibm-aix
+// RUN: %clang_cc1 -target-feature +altivec -fsyntax-only %s -triple 
powerpc64-ibm-aix-xcoff
+// RUN: %clang_cc1 -target-feature +altivec -fsyntax-only %s -triple 
powerpc64le-ibm-linux-gnu
+// RUN: %clang_cc1 -target-feature +altivec -fsyntax-only %s -triple 
powerpc64le-linux-unknown
+// RUN: %clang_cc1 -target-feature +altivec -fsyntax-only %s -triple 
powerpc64le-unknown-linux
+// RUN: %clang_cc1 -target-feature +altivec -fsyntax-only %s -triple 
powerpc64le-unknown-linux-gnu
+// RUN: %clang_cc1 -target-feature +altivec -fsyntax-only %s -triple 
powerpc64le-unknown-unknown

Sorry, didn't mean to imply you needed all of these.  These should suffice. 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100991/new/

https://reviews.llvm.org/D100991

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[PATCH] D100991: Fix parsing of vector keyword in presence of conflicting uses.

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA accepted this revision.
ZarkoCA added a comment.
This revision is now accepted and ready to land.

LGTM, thanks.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100991/new/

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[PATCH] D94986: Remove requirement for -maltivec to be used when using -mabi=vec-extabi or -mabi=vec-default when not using vector code

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 318971.
ZarkoCA marked an inline comment as done.
ZarkoCA edited the summary of this revision.
ZarkoCA added a comment.

- Emit error message only when option is active
- Changed description of patch


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94986/new/

https://reviews.llvm.org/D94986

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/altivec.c


Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -2,23 +2,17 @@
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpcle-unknown-unknown 
-emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc64-unknown-unknown 
-emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang_cc1 -target-feature +altivec -triple 
powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-LE
-// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple 
powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
-// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple 
powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -triple 
powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -triple 
powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
- 
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -target 
powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang -S -emit-llvm -maltivec -target powerpc-unknown-aix %s 2>&1 
| FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -target powerpc64-unknown-aix %s 
2>&1 | FileCheck %s --check-prefix=AIX-ERROR 
-// RUN: not %clang -S -emit-llvm -mabi=vec-default -target powerpc-unknown-aix 
%s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -emit-llvm -mabi=vec-extabi -target powerpc-unknown-aix 
%s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -target 
powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang -S -emit-llvm -mabi=vec-default -target 
powerpc64-unknown-aix %s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -emit-llvm -mabi=vec-extabi -target 
powerpc64-unknown-aix %s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -mabi=vec-default -target powerpc-unknown-aix %s 2>&1  | 
FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -mabi=vec-extabi -target powerpc-unknown-aix %s 2>&1  | 
FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -mabi=vec-default -target powerpc64-unknown-aix %s 2>&1  
| FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -mabi=vec-extabi -target powerpc64-unknown-aix %s 2>&1  
| FileCheck  %s --check-prefix=AIX-ATVER
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 
-triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 
-triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
+// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu 
pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
+// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu 
pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
+
+// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target 
powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
+// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target 
powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR 
+// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target 
powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target 
powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 
-triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
+// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 
-triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
 // Check initialization
 
 vector int test0 = (vector int)(1);   // CHECK: @test0 ={{.*}} global <4 x 
i32> 
@@ -63,4 +57,

[PATCH] D94986: Remove requirement for -maltivec to be used when using -mabi=vec-extabi or -mabi=vec-default when not using vector code

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
ZarkoCA marked an inline comment as done.
Closed by commit rG028d7a36681f: Remove requirement for -maltivec to be used 
when using -mabi=vec-extabi or… (authored by ZarkoCA).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94986/new/

https://reviews.llvm.org/D94986

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/altivec.c


Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -2,23 +2,17 @@
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpcle-unknown-unknown 
-emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc64-unknown-unknown 
-emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang_cc1 -target-feature +altivec -triple 
powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-LE
-// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple 
powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
-// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple 
powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -triple 
powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -triple 
powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
- 
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -target 
powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang -S -emit-llvm -maltivec -target powerpc-unknown-aix %s 2>&1 
| FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -target powerpc64-unknown-aix %s 
2>&1 | FileCheck %s --check-prefix=AIX-ERROR 
-// RUN: not %clang -S -emit-llvm -mabi=vec-default -target powerpc-unknown-aix 
%s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -emit-llvm -mabi=vec-extabi -target powerpc-unknown-aix 
%s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -target 
powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang -S -emit-llvm -mabi=vec-default -target 
powerpc64-unknown-aix %s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -emit-llvm -mabi=vec-extabi -target 
powerpc64-unknown-aix %s 2>&1  | FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -mabi=vec-default -target powerpc-unknown-aix %s 2>&1  | 
FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -mabi=vec-extabi -target powerpc-unknown-aix %s 2>&1  | 
FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -mabi=vec-default -target powerpc64-unknown-aix %s 2>&1  
| FileCheck  %s --check-prefix=AIX-ATVER
-// RUN: not %clang -S -mabi=vec-extabi -target powerpc64-unknown-aix %s 2>&1  
| FileCheck  %s --check-prefix=AIX-ATVER
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 
-triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 
-triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
+// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu 
pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
+// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu 
pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
+
+// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target 
powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
+// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target 
powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR 
+// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target 
powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target 
powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 
-triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
+// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 
-triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
 // Check initialization
 
 vector int test0 = (vector int)(1);   // CHECK

[PATCH] D95702: [AIX] Improve option processing for mabi=vec-extabi and mabi=vec=defaul

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA created this revision.
ZarkoCA added reviewers: hubert.reinterpretcast, cebowleratibm.
ZarkoCA added a project: PowerPC.
ZarkoCA requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Opening this revision to better address comments by @hubert.reinterpretcast in 
https://reviews.llvm.org/rGcaaaebcde462


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95702

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/altivec.c


Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -6,9 +6,6 @@
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 
-triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
 // RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu 
pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
 // RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu 
pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
-
-// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target 
powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target 
powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR 
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target 
powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target 
powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 
-triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -4669,23 +4669,15 @@
 }
   }
 
-  if (Triple.isOSAIX() && Args.hasArg(options::OPT_maltivec)) {
-if (Args.getLastArg(options::OPT_mabi_EQ_vec_extabi)) {
-  CmdArgs.push_back("-mabi=vec-extabi");
-} else {
-  D.Diag(diag::err_aix_default_altivec_abi);
-}
-  }
-
   if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ_vec_extabi,
options::OPT_mabi_EQ_vec_default)) {
 if (!Triple.isOSAIX())
   D.Diag(diag::err_drv_unsupported_opt_for_target)
   << A->getSpelling() << RawTriple.str();
-if (A->getOption().getID() == options::OPT_mabi_EQ_vec_default)
-  D.Diag(diag::err_aix_default_altivec_abi);
 if (A->getOption().getID() == options::OPT_mabi_EQ_vec_extabi)
   CmdArgs.push_back("-mabi=vec-extabi");
+else
+  D.Diag(diag::err_aix_default_altivec_abi);
   }
 
   if (Arg *A = Args.getLastArg(options::OPT_Wframe_larger_than_EQ)) {


Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -6,9 +6,6 @@
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
 // RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-
-// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR 
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -4669,23 +4669,15 @@
 }
   }
 
-  if (Triple.isOSAIX() && Args.hasArg(options::OPT_maltivec)) {
-if (Args.getLastArg(options::OPT_mabi_EQ_vec_extabi)) {
-  CmdArgs.push_back("-mabi=vec-extabi");
-} else {
-  D.Diag(diag::err_aix_default_altivec_abi);

[PATCH] D95702: [AIX] Improve option processing for mabi=vec-extabi and mabi=vec=defaul

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGeb3426a528d5: [AIX] Improve option processing for 
mabi=vec-extabi and mabi=vec=defaul (authored by ZarkoCA).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95702/new/

https://reviews.llvm.org/D95702

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/altivec.c


Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -6,9 +6,6 @@
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 
-triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
 // RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu 
pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
 // RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu 
pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
-
-// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target 
powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target 
powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR 
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target 
powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target 
powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 
-triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s 
--check-prefix=AIX-ERROR
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -4669,23 +4669,15 @@
 }
   }
 
-  if (Triple.isOSAIX() && Args.hasArg(options::OPT_maltivec)) {
-if (Args.getLastArg(options::OPT_mabi_EQ_vec_extabi)) {
-  CmdArgs.push_back("-mabi=vec-extabi");
-} else {
-  D.Diag(diag::err_aix_default_altivec_abi);
-}
-  }
-
   if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ_vec_extabi,
options::OPT_mabi_EQ_vec_default)) {
 if (!Triple.isOSAIX())
   D.Diag(diag::err_drv_unsupported_opt_for_target)
   << A->getSpelling() << RawTriple.str();
-if (A->getOption().getID() == options::OPT_mabi_EQ_vec_default)
-  D.Diag(diag::err_aix_default_altivec_abi);
 if (A->getOption().getID() == options::OPT_mabi_EQ_vec_extabi)
   CmdArgs.push_back("-mabi=vec-extabi");
+else
+  D.Diag(diag::err_aix_default_altivec_abi);
   }
 
   if (Arg *A = Args.getLastArg(options::OPT_Wframe_larger_than_EQ)) {


Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -6,9 +6,6 @@
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
 // RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-
-// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -mcpu=pwr8 -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR 
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -4669,23 +4669,15 @@
 }
   }
 
-  if (Triple.isOSAIX() && Args.hasArg(options::OPT_maltivec)) {
-if (Args.getLastArg(options::OPT_mabi_EQ_vec_extabi)) {
-  CmdArgs.push_back("-mabi=vec-extabi");
-} else {
-  D.Diag(diag::err_aix_default_altivec_abi);
-}
-  }
-
   if (Arg *A = Args.getL

[PATCH] D106393: [PowerPC][AIX] Add support for varargs for complex types on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1b0a71c5fc05: [PowerPC][AIX] Add support for varargs for 
complex types on AIX (authored by ZarkoCA).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106393/new/

https://reviews.llvm.org/D106393

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aix32-complex-varargs.c
  clang/test/CodeGen/ppc64-varargs-complex.c

Index: clang/test/CodeGen/ppc64-varargs-complex.c
===
--- clang/test/CodeGen/ppc64-varargs-complex.c
+++ clang/test/CodeGen/ppc64-varargs-complex.c
@@ -1,5 +1,6 @@
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
Index: clang/test/CodeGen/aix32-complex-varargs.c
===
--- /dev/null
+++ clang/test/CodeGen/aix32-complex-varargs.c
@@ -0,0 +1,66 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+void testva (int n, ...)
+{
+  va_list ap;
+
+  _Complex int i   = va_arg(ap, _Complex int);
+// CHECK:  %[[VAR40:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]]
+// CHECK-NEXT:  %[[VAR41:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR40]]
+// CHECK-NEXT:  store i8* %[[VAR41]], i8** %[[VAR100]], align 4
+// CHECK-NEXT:  %[[VAR4:[A-Za-z0-9.]+]] = bitcast i8* %[[VAR40]] to { i32, i32 }*
+// CHECK-NEXT:  %[[VAR6:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR4]], i32 0, i32 0
+// CHECK-NEXT:  %[[VAR7:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR6]]
+// CHECK-NEXT:  %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR4]], i32 0, i32 1
+// CHECK-NEXT:  %[[VAR9:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR8]]
+// CHECK-NEXT:  %[[VAR10:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VARINT:[A-Za-z0-9.]+]], i32 0, i32 0
+// CHECK-NEXT:  %[[VAR11:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VARINT]], i32 0, i32 1
+// CHECK-NEXT:  store i32 %[[VAR7]], i32* %[[VAR10]]
+// CHECK-NEXT:  store i32 %[[VAR9]], i32* %[[VAR11]]
+
+  _Complex short s = va_arg(ap, _Complex short);
+// CHECK:  %[[VAR50:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]]
+// CHECK-NEXT:  %[[VAR51:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR50]]
+// CHECK-NEXT:  store i8* %[[VAR51]], i8** %[[VAR100]], align 4
+// CHECK-NEXT:  %[[VAR12:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR50]], i32 2
+// CHECK-NEXT:  %[[VAR13:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR50]], i32 6
+// CHECK-NEXT:  %[[VAR14:[A-Za-z0-9.]+]] = bitcast i8* %[[VAR12]] to i16*
+// CHECK-NEXT:  %[[VAR15:[A-Za-z0-9.]+]] = bitcast i8* %[[VAR13]] to i16*
+// CHECK-NEXT:  %[[VAR16:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR14]], align 2
+// CHECK-NEXT:  %[[VAR17:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR15]], align 2
+// CHECK-NEXT:  %[[VAR18:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR19:[A-Za-z0-9.]+]], i32 0, i32 0
+// CHECK-NEXT:  %[[VAR20:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR19]], i32 0, i32 1
+// CHECK-NEXT:  store i16 %[[VAR16]], i16* %[[VAR18]]
+// CHECK-NEXT:  store i16 %[[VAR17]], i16* %[[VAR20]]
+
+
+  _Complex char c  = va_arg(ap, _Complex char);
+// CHECK:  %[[VAR60:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]]
+// CHECK-NEXT:  %[[VAR61:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR60]]
+// CHECK-NEXT:  store i8* %[[VAR61]], i8** %[[VAR100]], align 4
+// CHECK-NEXT:  %[[VAR21:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR60]], i32 3
+// CHECK-NEXT:  %[[VAR22:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR60]], i32 7
+// CHECK-NEXT:  %[[VAR23:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR21]]
+// CHECK-NEXT:  %[[VAR24:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR22]]
+// CHECK-NEXT:  %[[VAR25:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR26:[A-Za-z0-9.]+]], i32 0, i32 0
+// CHECK-NEXT:  %[[VAR27:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR26]], i32 0, i32 1
+// CHECK-NEXT:  store i8 %[[VAR23]], i8* %[[VAR25]]
+// CHECK-NEXT:  store i8 %[[VAR24]], i8* %[[VAR27]]
+
+
+  _Complex float f = va_arg(ap, _Complex float);
+// CHECK:  %[[VAR70:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR71:[A-Za-z0-9.]+]], i32 8
+// CHECK-NEXT:  store i8* %[[VAR70]], i8** %[[VAR100:[A-Za-z0-9.]+]]
+// CHECK-NEXT:  %[[VAR28:[A-Za-z0-9.]+]] = bitcast i8* %[[VAR71]] to { float, float }*
+// CHECK-NEXT:  %[[VAR29:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }, { float, float }* %[[VAR28]], i32 0, i32 0
+// CHECK-NEXT:  %[[VAR30:[A-Za-z0-9.]+]] = load fl

[PATCH] D106409: [PowerPC] Truncate results for out of range values for vec_cts,vec_ctf

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added a comment.

Ping.


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[PATCH] D106409: [PowerPC] Truncate results for out of range values for vec_cts,vec_ctf

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 376630.
ZarkoCA edited the summary of this revision.
ZarkoCA added a comment.
Herald added a subscriber: steven.zhang.

- Only truncate **b** and not result
- Add a proper test case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D106409

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/ppc-vec_ct-truncate.c

Index: clang/test/CodeGen/ppc-vec_ct-truncate.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-vec_ct-truncate.c
@@ -0,0 +1,90 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -triple powerpc64-ibm-aix-xcoff -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -triple powerpc64-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr8 | FileCheck %s
+#include 
+vector double a1 = {-1.234e-5, 1.2345};
+vector double a2 = {-1.234e-5, 1.2345};
+vector signed int vd1, vd2;
+vector double vd3 = {0.234, 1.234};
+vector float vf1 = {0.234, 1.234, 2.345, 3.456};
+vector float vf2 = {0.234, 1.234, 2.345, 3.456};
+vector float vf3 = {0.234, 1.234, 2.345, 3.456};
+vector float vf4 = {0.234, 1.234, 2.345, 3.456};
+vector float vf5 = {0.234, 1.234, 2.345, 3.456};
+vector signed int vsi1 = {1, 2, 3, 4};
+vector signed int vsi2 = {1, 2, 3, 4};
+vector signed int vsi3 = {1, 2, 3, 4};
+vector signed int vsi4 = {1, 2, 3, 4};
+vector long long int vl1 = {50, 10};
+vector long long int vl2 = {50, 10};
+vector double vd;
+vector float vf;
+vector signed long long vsll;
+vector unsigned int vsi5;
+vector unsigned int vsi6;
+vector unsigned long long vull;
+
+void test() {
+  // CHECK-LABEL: @test(
+  // CHECK-NEXT:  entry:
+  // CHECK-LE-LABEL: @test(
+  // CHECK-LE-NEXT:  entry:
+
+  vd1 = vec_cts(a1, 31);
+  //  CHECK:   [[TMP0:%.*]] = load <2 x double>, <2 x double>* @a1, align 16
+  //  CHECK-NEXT:  fmul <2 x double> [[TMP0]], 
+
+  vd2 = vec_cts(a2, 500);
+  // CHECK:[[TMP4:%.*]] = load <2 x double>, <2 x double>* @a2, align 16
+  // CHECK-NEXT:   fmul <2 x double> [[TMP4]], 
+
+  vsi3 = vec_ctu(vf1, 31);
+  // CHECK:[[TMP8:%.*]] = load <4 x float>, <4 x float>* @vf1, align 16
+  // CHECK-NEXT:   call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> [[TMP8]], i32 31)
+
+  vsi4 = vec_ctu(vf2, 500);
+  // CHECK:[[TMP10:%.*]] = load <4 x float>, <4 x float>* @vf2, align 16
+  // CHECK-NEXT:   call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> [[TMP10]], i32 20)
+
+  vull = vec_ctul(vf1, 31);
+  // CHECK:[[TMP12:%.*]] = load <4 x float>, <4 x float>* @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP12]], 
+
+  vull = vec_ctul(vf3, 500);
+  // CHECK:[[TMP21:%.*]] = load <4 x float>, <4 x float>* @vf3, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP21]], 
+
+  vsll = vec_ctsl(vf4, 31);
+  // CHECK:[[TMP30:%.*]] = load <4 x float>, <4 x float>* @vf4, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP30]], 
+
+  vsll = vec_ctsl(vf5, 500);
+  // CHECK:[[TMP39:%.*]] = load <4 x float>, <4 x float>* @vf5, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP39]], 
+
+  vf = vec_ctf(vsi1, 31);
+  // CHECK:[[TMP48:%.*]] = load <4 x i32>, <4 x i32>* @vsi1, align 16
+  // CHECK-NEXT:   call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[TMP48]], i32 31)
+
+  vf = vec_ctf(vsi2, 500);
+  // CHECK:[[TMP50:%.*]] = load <4 x i32>, <4 x i32>* @vsi2, align 16
+  // CHECK-NEXT:   call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[TMP50]], i32 20)
+
+  vd = vec_ctd(vsi3, 31);
+  // CHECK:[[TMP53:%.*]] = load <4 x i32>, <4 x i32>* @vsi3, align 16
+  // CHECK:[[TMP83:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP82:%.*]])
+  // CHECK-NEXT:   fmul <2 x double> [[TMP83]], 
+
+  vd = vec_ctd(vsi4, 500);
+
+  // CHECK:[[TMP84:%.*]] = load <4 x i32>, <4 x i32>* @vsi4, align 16
+  // CHECK:[[TMP115:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP114:%.*]])
+  // CHECK-NEXT:   fmul <2 x double> [[TMP115]], 
+}
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -3178,64 +3178,69 @@
 #ifdef __XL_COMPAT_ALTIVEC__
 #define vec_ctf(__a, __b)  \
   _Generic((__a), vector int   \
-   : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)),  \
+   : (vector float)__builtin_altivec

[PATCH] D106409: [PowerPC] Truncate exponent parameter for vec_cts,vec_ctf

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked an inline comment as done.
ZarkoCA added inline comments.



Comment at: clang/lib/Headers/altivec.h:3178
+  : (__builtin_vsx_xvcvuxdsp((vector unsigned long long)(__a)) *   
\
+ (vector float)(vector unsigned)((0x7f - (__b)) << 23 & 0x1F)),
\
+vector signed long long
\

nemanjai wrote:
> Hmm... aren't you truncating the wrong thing here (and for all the other 
> shifted ones? Shouldn't it be something like:
> ```
> (vector float)(vector unsigned)((0x7f - ((__b) & 0x1F)) << 23)),
> ```
Thanks, I wasn't doing the truncation correctly. Redid to what I think is 
correct now. 


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[PATCH] D102094: [AIX][PowerPC] Remove error when specifying mabi=vec-default on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 353721.
ZarkoCA marked an inline comment as done.
ZarkoCA added a comment.

Addressed comments:

- Removed redundant `elseif` and CHECK


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c

Index: clang/test/Preprocessor/aix-vec_extabi.c
===
--- clang/test/Preprocessor/aix-vec_extabi.c
+++ clang/test/Preprocessor/aix-vec_extabi.c
@@ -2,11 +2,11 @@
 // RUN:   | FileCheck %s -check-prefix=EXTABI
 // RUN: %clang  -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-extabi %s -o - 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=EXTABI
-// RUN: not %clang  -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
+// RUN: %clang  -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DFLTABI
-// RUN: not %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DFLTABI
 
 
-// EXTABI:  #define __EXTABI__
-// DFLTABI: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI
+// EXTABI:  #define __EXTABI__
+// DFLTABI-NOT: #define __EXTABI__
Index: clang/test/Driver/aix-vec-extabi.c
===
--- clang/test/Driver/aix-vec-extabi.c
+++ clang/test/Driver/aix-vec-extabi.c
@@ -1,10 +1,10 @@
 // RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-extabi %s 2>&1 | \
-// RUN:  FileCheck %s
-
-// CHECK: "-cc1"
-// CHECK-SAME: "-mabi=vec-extabi"
-
+// RUN:  FileCheck %s --check-prefix=EXTABI
 // RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-default %s 2>&1 | \
-// RUN:  FileCheck %s --check-prefix=ERROR
+// RUN:  FileCheck %s --check-prefix=DFLTABI
+
+// EXTABI:   "-cc1"
+// EXTABI-SAME:  "-mabi=vec-extabi"
 
-// ERROR: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI
+// DFLTABI:  "-cc1"
+// DFLTABI-SAME: "-mabi=vec-default"
Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -4,12 +4,12 @@
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 --target=powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 --target=powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 --target=powerpc-unknown-ai

[PATCH] D102094: [AIX][PowerPC] Remove error when specifying mabi=vec-default on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked 2 inline comments as done.
ZarkoCA added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4779
   CmdArgs.push_back("-mabi=vec-extabi");
+else if (A->getOption().getID() == options::OPT_mabi_EQ_vec_default)
+  CmdArgs.push_back("-mabi=vec-default");

jsji wrote:
> Why we need to check this if the default is to set it to `-mabi=vec-default` 
> in below else?
I think my reasoning was to map `-mabi=vec-default` to something specific but 
we don't need it. 



Comment at: clang/test/Driver/aix-vec-extabi.c:11
+// DFLTABI-SAME: "-mabi=vec-default"
+// DFLTABI-NOT:  "-mabi=vec-default"

jsji wrote:
> Why we need to explicitly `DFLTABI-NOT:  "-mabi=vec-default"`
It's not required, removed. 


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[PATCH] D102094: [AIX][PowerPC] Remove error when specifying mabi=vec-default on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 353748.
ZarkoCA marked 2 inline comments as done.
ZarkoCA added a comment.

- Updated test case


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c

Index: clang/test/Preprocessor/aix-vec_extabi.c
===
--- clang/test/Preprocessor/aix-vec_extabi.c
+++ clang/test/Preprocessor/aix-vec_extabi.c
@@ -2,11 +2,11 @@
 // RUN:   | FileCheck %s -check-prefix=EXTABI
 // RUN: %clang  -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-extabi %s -o - 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=EXTABI
-// RUN: not %clang  -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
+// RUN: %clang  -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DFLTABI
-// RUN: not %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DFLTABI
 
 
-// EXTABI:  #define __EXTABI__
-// DFLTABI: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI
+// EXTABI:  #define __EXTABI__
+// DFLTABI-NOT: #define __EXTABI__
Index: clang/test/Driver/aix-vec-extabi.c
===
--- clang/test/Driver/aix-vec-extabi.c
+++ clang/test/Driver/aix-vec-extabi.c
@@ -1,10 +1,18 @@
+// RUN:  %clang -### -target powerpc-unknown-aix -S %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=NOEXTABI
+// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=NOEXTABI
+// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-default %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=DFLTABI
+// RUN:  %clang -### -target powerpc-unknown-aix -S -mabi=vec-extabi %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=EXTABI
 // RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-extabi %s 2>&1 | \
-// RUN:  FileCheck %s
-
-// CHECK: "-cc1"
-// CHECK-SAME: "-mabi=vec-extabi"
+// RUN:  FileCheck %s --check-prefix=EXTABI
+/
+// NOEXTABI-NOT: "-mabi=vec-extabi"
 
-// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-default %s 2>&1 | \
-// RUN:  FileCheck %s --check-prefix=ERROR
+// EXTABI:   "-cc1"
+// EXTABI-SAME:  "-mabi=vec-extabi"
 
-// ERROR: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI
+// DFLTABI:  "-cc1"
+// DFLTABI-SAME: "-mabi=vec-default"
Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -4,12 +4,12 @@
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o

[PATCH] D102094: [AIX][PowerPC] Remove error when specifying mabi=vec-default on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA added inline comments.



Comment at: clang/test/Driver/aix-vec-extabi.c:3
+// RUN:  FileCheck %s --check-prefix=EXTABI
 // RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec 
-mabi=vec-default %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=DFLTABI

jsji wrote:
> How about RUN line without `-mabi`? 
> and without `-maltivec`?
> and `-mabi=vec-extabi` without `-maltivec`?
Thanks, added those. Since `-mabi-vec-extabi` is a codegen option I think it 
makes sense to make sure it's not active when only `-maltivec` or nothing is 
specified on the command line. Does that work? 


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[PATCH] D102094: [AIX][PowerPC] Remove error when specifying mabi=vec-default on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 353787.
ZarkoCA added a comment.

Use `--implicit-check-not`


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c

Index: clang/test/Preprocessor/aix-vec_extabi.c
===
--- clang/test/Preprocessor/aix-vec_extabi.c
+++ clang/test/Preprocessor/aix-vec_extabi.c
@@ -2,11 +2,11 @@
 // RUN:   | FileCheck %s -check-prefix=EXTABI
 // RUN: %clang  -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-extabi %s -o - 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=EXTABI
-// RUN: not %clang  -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
+// RUN: %clang  -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DFLTABI
-// RUN: not %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DFLTABI
 
 
-// EXTABI:  #define __EXTABI__
-// DFLTABI: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI
+// EXTABI:  #define __EXTABI__
+// DFLTABI-NOT: #define __EXTABI__
Index: clang/test/Driver/aix-vec-extabi.c
===
--- clang/test/Driver/aix-vec-extabi.c
+++ clang/test/Driver/aix-vec-extabi.c
@@ -1,10 +1,16 @@
-// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-extabi %s 2>&1 | \
-// RUN:  FileCheck %s
-
-// CHECK: "-cc1"
-// CHECK-SAME: "-mabi=vec-extabi"
-
+// RUN:  %clang -### -target powerpc-unknown-aix -S %s 2>&1 | \
+// RUN:  FileCheck %s --implicit-check-not=-mabi=vec-extabi
+// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec %s 2>&1 | \
+// RUN:  FileCheck %s --implicit-check-not=-mabi=vec-extabi
 // RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-default %s 2>&1 | \
-// RUN:  FileCheck %s --check-prefix=ERROR
+// RUN:  FileCheck %s --check-prefix=DFLTABI --implicit-check-not=-mabi=vec-extabi
+// RUN:  %clang -### -target powerpc-unknown-aix -S -mabi=vec-extabi %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=EXTABI
+// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-extabi %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=EXTABI
+/
+// EXTABI:   "-cc1"
+// EXTABI-SAME:  "-mabi=vec-extabi"
 
-// ERROR: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI
+// DFLTABI:  "-cc1"
+// DFLTABI-SAME: "-mabi=vec-default"
Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -4,12 +4,12 @@
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o - | Fi

[PATCH] D102094: [AIX][PowerPC] Remove error when specifying mabi=vec-default on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA marked an inline comment as done.
ZarkoCA added inline comments.



Comment at: clang/test/Driver/aix-vec-extabi.c:12
+/
+// NOEXTABI-NOT: "-mabi=vec-extabi"
 

jsji wrote:
> Why not use `--implicit-check-not`?
Thank you, I wasn't aware of this option before this.  


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[PATCH] D102094: [AIX][PowerPC] Remove error when specifying mabi=vec-default on AIX

[Zarko Todorovski via Phabricator via cfe-commits]

ZarkoCA updated this revision to Diff 353806.
ZarkoCA marked an inline comment as done.
ZarkoCA added a comment.

check for `vec-extabi` instead of `-mabi=vec-extabi`


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/altivec.c
  clang/test/Driver/aix-vec-extabi.c
  clang/test/Driver/aix-vec_extabi.c
  clang/test/Preprocessor/aix-vec_extabi.c

Index: clang/test/Preprocessor/aix-vec_extabi.c
===
--- clang/test/Preprocessor/aix-vec_extabi.c
+++ clang/test/Preprocessor/aix-vec_extabi.c
@@ -2,11 +2,11 @@
 // RUN:   | FileCheck %s -check-prefix=EXTABI
 // RUN: %clang  -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-extabi %s -o - 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=EXTABI
-// RUN: not %clang  -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
+// RUN: %clang  -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DFLTABI
-// RUN: not %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DFLTABI
 
 
-// EXTABI:  #define __EXTABI__
-// DFLTABI: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI
+// EXTABI:  #define __EXTABI__
+// DFLTABI-NOT: #define __EXTABI__
Index: clang/test/Driver/aix-vec_extabi.c
===
--- /dev/null
+++ clang/test/Driver/aix-vec_extabi.c
@@ -0,0 +1,16 @@
+// RUN:  %clang -### -target powerpc-unknown-aix -S %s 2>&1 | \
+// RUN:  FileCheck %s --implicit-check-not=vec-extabi
+// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec %s 2>&1 | \
+// RUN:  FileCheck %s --implicit-check-not=vec-extabi
+// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-default %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=DFLTABI --implicit-check-not=vec-extabi
+// RUN:  %clang -### -target powerpc-unknown-aix -S -mabi=vec-extabi %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=EXTABI
+// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-extabi %s 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=EXTABI
+/
+// EXTABI:   "-cc1"
+// EXTABI-SAME:  "-mabi=vec-extabi"
+
+// DFLTABI:  "-cc1"
+// DFLTABI-SAME: "-mabi=vec-default"
Index: clang/test/Driver/aix-vec-extabi.c
===
--- clang/test/Driver/aix-vec-extabi.c
+++ /dev/null
@@ -1,10 +0,0 @@
-// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-extabi %s 2>&1 | \
-// RUN:  FileCheck %s
-
-// CHECK: "-cc1"
-// CHECK-SAME: "-mabi=vec-extabi"
-
-// RUN:  %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-default %s 2>&1 | \
-// RUN:  FileCheck %s --check-prefix=ERROR
-
-// ERROR: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI
Index: clang/test/CodeGen/altivec.c
===
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -4,12 +4,12 @@
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -target-cpu pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -mcpu=pwr8 -target powerpc64-unknown-aix %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
-// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
-// RUN: not %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck