Re: [PATCH] D50850: clang: Add triples support for MIPS r6
I updated N32 patch for clang. Simon Atanasyan via Phabricator 于2018年9月27日周四 下午8:23写道： > > atanasyan added a comment. > > Could you please update the patch against the current trunk? > > > Repository: > rC Clang > > https://reviews.llvm.org/D50850 > > > -- YunQiang Su ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Clang/MIPS: Use -mnan value for -mabs if not specified (PR #71157)
wzssyqa wrote: @brad0 can you have a look at this? https://github.com/llvm/llvm-project/pull/71157 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] MIPS/libunwind: Use -mfp64 if compiler is FPXX (PR #68521)
wzssyqa wrote: @brad0 can you have a look at this PR? https://github.com/llvm/llvm-project/pull/68521 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Clang/MIPS: Use -mnan value for -mabs if not specified (PR #71157)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/71157
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008. Let's
use this behaivor by default.
With this commit, `clang -target mips -mnan=2008 -c fabs.c` will imply
`-mabs=2008`.
And of course, `clang -mnan=2008 -mabs=legacy` can continue workable like
previous.
>From feabd6fd561ff7af2f21b7c649fe8a4cc1ac6343 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Fri, 3 Nov 2023 03:30:52 -0400
Subject: [PATCH] Clang/MIPS: Use -mnan value for -mabs if not specified
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008.
Let's use this behaivor by default.
With this commit, `clang -target mips -mnan=2008 -c fabs.c` will
imply `-mabs=2008`.
And of course, `clang -mnan=2008 -mabs=legacy` can continue workable
like previous.
---
clang/lib/Driver/ToolChains/Arch/Mips.cpp | 8 ++--
clang/test/Driver/mips-features.c | 8
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index f9f14c01b2b9f01..fe9d112b8800b17 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -221,6 +221,7 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
bool IsN64 = ABIName == "64";
bool IsPIC = false;
bool NonPIC = false;
+ bool HasNaN2008Opt = false;
Arg *LastPICArg = Args.getLastArg(options::OPT_fPIC, options::OPT_fno_PIC,
options::OPT_fpic, options::OPT_fno_pic,
@@ -285,9 +286,10 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
if (Arg *A = Args.getLastArg(options::OPT_mnan_EQ)) {
StringRef Val = StringRef(A->getValue());
if (Val == "2008") {
- if (mips::getIEEE754Standard(CPUName) & mips::Std2008)
+ if (mips::getIEEE754Standard(CPUName) & mips::Std2008) {
Features.push_back("+nan2008");
- else {
+HasNaN2008Opt = true;
+ } else {
Features.push_back("-nan2008");
D.Diag(diag::warn_target_unsupported_nan2008) << CPUName;
}
@@ -323,6 +325,8 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
D.Diag(diag::err_drv_unsupported_option_argument)
<< A->getSpelling() << Val;
}
+ } else if (HasNaN2008Opt) {
+Features.push_back("+abs2008");
}
AddTargetFeature(Args, Features, options::OPT_msingle_float,
diff --git a/clang/test/Driver/mips-features.c
b/clang/test/Driver/mips-features.c
index 5ae566774959f18..fc1b5894f539377 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -214,6 +214,14 @@
// RUN: -mnan=legacy -mnan=2008 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-NAN2008 %s
// CHECK-NAN2008: "-target-feature" "+nan2008"
+// CHECK-NAN2008: "-target-feature" "+abs2008"
+//
+// -mnan=2008 -mabs=legacy
+// RUN: %clang -target mips-linux-gnu -march=mips32r3 -### -c %s \
+// RUN: -mabs=legacy -mnan=2008 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-ABSLEGACYNAN2008 %s
+// CHECK-ABSLEGACYNAN2008: "-target-feature" "+nan2008"
+// CHECK-ABSLEGACYNAN2008: "-target-feature" "-abs2008"
//
// -mnan=legacy
// RUN: %clang -target mips-linux-gnu -march=mips32r3 -### -c %s \
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[libunwind] MIPS/libunwind: Use -mfp64 if compiler is FPXX (PR #68521)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/68521
>From 6053822322fd1594b46bf77c8b168ad802a7c534 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Sun, 8 Oct 2023 07:12:45 -0400
Subject: [PATCH] MIPS/libunwind: Use -mfp64 if compiler is FPXX
Libunwind supports FP64 and FP32 modes, but not FPXX.
The reason is that, FP64 and FP32 have different way to save/restore
FPRs. If libunwind is built as FPXX, we have no idea which one should
we use.
If libunwind is built as FP64, it will interoperatable with FPXX/FP64
APPs, and if it is built as FP32, it will interoperatable with
FP32/FPXX. Currently most of O32 APPs are FPXX or FP64, while few are FP32.
So if the compiler is FPXX, which is the default value of most toolchain,
let's switch it to FP64.
---
libunwind/CMakeLists.txt | 19 +++
1 file changed, 19 insertions(+)
diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt
index 84f8ce296a7410b..387d4b43b5746a6 100644
--- a/libunwind/CMakeLists.txt
+++ b/libunwind/CMakeLists.txt
@@ -21,6 +21,7 @@ set(LIBUNWIND_LIBCXX_PATH
"${CMAKE_CURRENT_LIST_DIR}/../libcxx" CACHE PATH
"Specify path to libc++ source.")
include(GNUInstallDirs)
+include(CheckSymbolExists)
#===
# Setup CMake Options
@@ -101,6 +102,20 @@ endif()
option(LIBUNWIND_HIDE_SYMBOLS
"Do not export any symbols from the static library."
${LIBUNWIND_DEFAULT_HIDE_SYMBOLS})
+# If toolchain is FPXX, we switch to FP64 to save the full FPRs. See:
+#
https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
+check_symbol_exists(__mips_hard_float "" __MIPSHF)
+check_symbol_exists(_ABIO32 "" __MIPS_O32)
+if (__MIPSHF AND __MIPS_O32)
+ file(WRITE
${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/mips_is_fpxx.c
+"#if __mips_fpr != 0\n"
+"# error\n"
+"#endif\n")
+ try_compile(MIPS_FPABI_FPXX ${CMAKE_BINARY_DIR}
+${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/mips_is_fpxx.c
+CMAKE_FLAGS -DCMAKE_C_LINK_EXECUTABLE='echo')
+endif()
+
#===
# Configure System
#===
@@ -184,6 +199,10 @@ if (WIN32)
add_compile_flags_if_supported(-Wno-dll-attribute-on-redeclaration)
endif()
+if (MIPS_FPABI_FPXX)
+ add_compile_flags(-mfp64)
+endif()
+
# Get feature flags.
# Exceptions
# Catches C++ exceptions only and tells the compiler to assume that extern C
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[clang] Clang/MIPS: Use -mnan value for -mabs if not specified (PR #71157)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/71157
>From 4e1b075a26db2831d981bad61ae883ede890bd58 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Fri, 3 Nov 2023 03:30:52 -0400
Subject: [PATCH] Clang/MIPS: Use -mnan value for -mabs if not specified
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008.
Let's use this behaivor by default.
With this commit, `clang -target mips -mnan=2008 -c fabs.c` will
imply `-mabs=2008`.
And of course, `clang -mnan=2008 -mabs=legacy` can continue workable
like previous.
---
clang/lib/Driver/ToolChains/Arch/Mips.cpp | 8 ++--
clang/test/Driver/mips-features.c | 8 +++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index f9f14c01b2b9f0..fe9d112b8800b1 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -221,6 +221,7 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
bool IsN64 = ABIName == "64";
bool IsPIC = false;
bool NonPIC = false;
+ bool HasNaN2008Opt = false;
Arg *LastPICArg = Args.getLastArg(options::OPT_fPIC, options::OPT_fno_PIC,
options::OPT_fpic, options::OPT_fno_pic,
@@ -285,9 +286,10 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
if (Arg *A = Args.getLastArg(options::OPT_mnan_EQ)) {
StringRef Val = StringRef(A->getValue());
if (Val == "2008") {
- if (mips::getIEEE754Standard(CPUName) & mips::Std2008)
+ if (mips::getIEEE754Standard(CPUName) & mips::Std2008) {
Features.push_back("+nan2008");
- else {
+HasNaN2008Opt = true;
+ } else {
Features.push_back("-nan2008");
D.Diag(diag::warn_target_unsupported_nan2008) << CPUName;
}
@@ -323,6 +325,8 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
D.Diag(diag::err_drv_unsupported_option_argument)
<< A->getSpelling() << Val;
}
+ } else if (HasNaN2008Opt) {
+Features.push_back("+abs2008");
}
AddTargetFeature(Args, Features, options::OPT_msingle_float,
diff --git a/clang/test/Driver/mips-features.c
b/clang/test/Driver/mips-features.c
index 5ae566774959f1..fad6009ffb89ba 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -213,7 +213,13 @@
// RUN: %clang -target mips-linux-gnu -march=mips32r3 -### -c %s \
// RUN: -mnan=legacy -mnan=2008 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-NAN2008 %s
-// CHECK-NAN2008: "-target-feature" "+nan2008"
+// CHECK-NAN2008: "-target-feature" "+nan2008" "-target-feature" "+abs2008"
+//
+// -mnan=2008 -mabs=legacy
+// RUN: %clang -target mips-linux-gnu -march=mips32r3 -### -c %s \
+// RUN: -mabs=legacy -mnan=2008 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-ABSLEGACYNAN2008 %s
+// CHECK-ABSLEGACYNAN2008: "-target-feature" "+nan2008" "-target-feature"
"-abs2008"
//
// -mnan=legacy
// RUN: %clang -target mips-linux-gnu -march=mips32r3 -### -c %s \
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[clang] [compiler-rt] Sanitizer prer6 (PR #76894)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/76894
On MIPS pre-R6, instruction b can only work within 64KiB,
which is not enough now.
We need the help of GOT.
For __mips64, we can get GOT by:
lui $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)
daddu $t8, $t8, $t9
daddiu $t8, $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)
And then get the address of __interceptor_func, and jump to it
ld $t9, %got_disp(__interceptor_" SANITIZER_STRINGIFY(func) ")($t8)
jr $t9
MIPS/O32 has .cpload, which can help to generate 3 instructions to get GOT.
MIPSr6 has instruction bc, which can jump long enough.
>From 4e1b075a26db2831d981bad61ae883ede890bd58 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Fri, 3 Nov 2023 03:30:52 -0400
Subject: [PATCH 1/2] Clang/MIPS: Use -mnan value for -mabs if not specified
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008.
Let's use this behaivor by default.
With this commit, `clang -target mips -mnan=2008 -c fabs.c` will
imply `-mabs=2008`.
And of course, `clang -mnan=2008 -mabs=legacy` can continue workable
like previous.
---
clang/lib/Driver/ToolChains/Arch/Mips.cpp | 8 ++--
clang/test/Driver/mips-features.c | 8 +++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index f9f14c01b2b9f0..fe9d112b8800b1 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -221,6 +221,7 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
bool IsN64 = ABIName == "64";
bool IsPIC = false;
bool NonPIC = false;
+ bool HasNaN2008Opt = false;
Arg *LastPICArg = Args.getLastArg(options::OPT_fPIC, options::OPT_fno_PIC,
options::OPT_fpic, options::OPT_fno_pic,
@@ -285,9 +286,10 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
if (Arg *A = Args.getLastArg(options::OPT_mnan_EQ)) {
StringRef Val = StringRef(A->getValue());
if (Val == "2008") {
- if (mips::getIEEE754Standard(CPUName) & mips::Std2008)
+ if (mips::getIEEE754Standard(CPUName) & mips::Std2008) {
Features.push_back("+nan2008");
- else {
+HasNaN2008Opt = true;
+ } else {
Features.push_back("-nan2008");
D.Diag(diag::warn_target_unsupported_nan2008) << CPUName;
}
@@ -323,6 +325,8 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
D.Diag(diag::err_drv_unsupported_option_argument)
<< A->getSpelling() << Val;
}
+ } else if (HasNaN2008Opt) {
+Features.push_back("+abs2008");
}
AddTargetFeature(Args, Features, options::OPT_msingle_float,
diff --git a/clang/test/Driver/mips-features.c
b/clang/test/Driver/mips-features.c
index 5ae566774959f1..fad6009ffb89ba 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -213,7 +213,13 @@
// RUN: %clang -target mips-linux-gnu -march=mips32r3 -### -c %s \
// RUN: -mnan=legacy -mnan=2008 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-NAN2008 %s
-// CHECK-NAN2008: "-target-feature" "+nan2008"
+// CHECK-NAN2008: "-target-feature" "+nan2008" "-target-feature" "+abs2008"
+//
+// -mnan=2008 -mabs=legacy
+// RUN: %clang -target mips-linux-gnu -march=mips32r3 -### -c %s \
+// RUN: -mabs=legacy -mnan=2008 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-ABSLEGACYNAN2008 %s
+// CHECK-ABSLEGACYNAN2008: "-target-feature" "+nan2008" "-target-feature"
"-abs2008"
//
// -mnan=legacy
// RUN: %clang -target mips-linux-gnu -march=mips32r3 -### -c %s \
>From 9893b37053f02f679fcef2961b1e6872d8cf20b3 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Thu, 4 Jan 2024 13:07:41 +0800
Subject: [PATCH 2/2] Sanitizer/MIPS: fix build fail on pre-R6
On MIPS pre-R6, instruction b can only work within 64KiB,
which is not enough now.
We need the help of GOT.
For __mips64, we can get GOT by:
lui $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)
daddu $t8, $t8, $t9
daddiu $t8, $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)
And then get the address of __interceptor_func, and jump to it
ld $t9, %got_disp(__interceptor_" SANITIZER_STRINGIFY(func) ")($t8)
jr $t9
MIPS/O32 has .cpload, which can help to generate 3 instructions to get GOT.
MIPSr6 has instruction bc, which can jump long enough.
---
compiler-rt/lib/interception/interception.h | 5 +++--
.../lib/sanitizer_common/sanitizer_asm.h | 21 +++
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/compiler-rt/lib/interception/interception.h
b/compiler-rt/lib/interception/interception.h
index 9d8b60b2eef58c..58e969378a9082 100644
--- a/compiler-rt/lib/interception/interception.h
+++ b/compiler-rt/lib/interception/interception.h
@@ -205,8 +205,9 @@ cons
[clang] [compiler-rt] Sanitizer prer6 (PR #76894)
wzssyqa wrote: @brad0 https://github.com/llvm/llvm-project/pull/76894 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)
https://github.com/wzssyqa created https://github.com/llvm/llvm-project/pull/85174 MIPSr6 ISA requires normal load/store instructions support misunaligned memory access, while it is not always do so by hardware. On some microarchitectures or some corner cases it may need support by OS. Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't support them, instead, r6 requires lw instruction support misunaligned memory access. So, if -mno-unaligned-access is used for pre-R6, lwl/lwr won't be disabled. If -mno-unaligned-access is used for r6 and the access is not well aligned, some lb/lh instructions will be used to replace lw. This is useful for OS kernels. >From a74a9bbd2ff2c6589db4c9756cf809c22e98fa64 Mon Sep 17 00:00:00 2001 From: YunQiang Su Date: Thu, 14 Mar 2024 11:48:36 +0800 Subject: [PATCH] MIPS: Support -m(no-)unaligned-access for r6 MIPSr6 ISA requires normal load/store instructions support misunaligned memory access, while it is not always do so by hardware. On some microarchitectures or some corner cases it may need support by OS. Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't support them, instead, r6 requires lw instruction support misunaligned memory access. So, if -mno-unaligned-access is used for pre-R6, lwl/lwr won't be disabled. If -mno-unaligned-access is used for r6 and the access is not well aligned, some lb/lh instructions will be used to replace lw. This is useful for OS kernels. --- clang/include/clang/Driver/Options.td | 4 +- clang/lib/Driver/ToolChains/Arch/Mips.cpp | 2 + clang/test/Driver/mips-features.c | 26 +++ llvm/lib/Target/Mips/Mips.td | 4 ++ llvm/lib/Target/Mips/MipsISelLowering.cpp | 16 - llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 11 ++- llvm/lib/Target/Mips/MipsSubtarget.cpp| 1 + llvm/lib/Target/Mips/MipsSubtarget.h | 7 +- llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 10 +-- .../CodeGen/Mips/no-unaligned-access-r6.ll| 69 +++ 10 files changed, 138 insertions(+), 12 deletions(-) create mode 100644 llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 1fac7b6f0093d8..6d3645f0a66828 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4696,9 +4696,9 @@ def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group, " (RISC-V only)")>; def munaligned_access : Flag<["-"], "munaligned-access">, Group, - HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch/RISC-V only)">; + HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch/MIPS/RISC-V only)">; def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group, - HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch/RISC-V only)">; + HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch/MIPS/RISC-V only)">; def munaligned_symbols : Flag<["-"], "munaligned-symbols">, Group, HelpText<"Expect external char-aligned symbols to be without ABI alignment (SystemZ only)">; def mno_unaligned_symbols : Flag<["-"], "mno-unaligned-symbols">, Group, diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp index fe9d112b8800b1..1de11811dccbc1 100644 --- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp +++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp @@ -341,6 +341,8 @@ void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple, "dspr2"); AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa, "msa"); + AddTargetFeature(Args, Features, options::OPT_mno_unaligned_access, + options::OPT_munaligned_access, "no-unaligned-access"); // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32 // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and diff --git a/clang/test/Driver/mips-features.c b/clang/test/Driver/mips-features.c index fd06b1400c3123..9e724b34e869d4 100644 --- a/clang/test/Driver/mips-features.c +++ b/clang/test/Driver/mips-features.c @@ -462,3 +462,29 @@ // RUN: -mrelax-pic-calls -mno-relax-pic-calls 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NO-RELAX-PIC-CALLS %s // CHECK-NO-RELAX-PIC-CALLS: "-mllvm" "-mips-jalr-reloc=0" +// +// -mno-unaligned-access +// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \ +// RUN: -munaligned-access -mno-strict-align \ +// RUN: -mno-unaligned-access 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-NO-UNALIGNED-ACCESS %s +// CHECK-NO-UNALIGNED-ACCESS: "-target-feature" "+no-unaligned-access" +// +// -munaligned-access +// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \ +// RUN: -mno-unaligned-access -mstrict-align \ +// RUN: -munaligned-access 2>&1 \ +// RUN: | FileCheck --check
[clang] [clang] Better bitfield access units (PR #65742)
wzssyqa wrote: > For MIPSr6, it is just like AARCH64, since some microarchitecture doesn't > support mis-unaligned well in hardware level, so we need an options to > disable it: kernel may need it. > > For GCC, we have `-mno-unalgined-access`. We need also add this option to > clang. https://github.com/llvm/llvm-project/pull/85174 Add -m(no-)unaligned-access for MIPSr6. https://github.com/llvm/llvm-project/pull/65742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Don't alias -mstrict-align to -mno-unaligned-access (PR #85350)
@@ -321,9 +321,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
}
}
- if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
- options::OPT_munaligned_access)) {
-if (A->getOption().matches(options::OPT_mno_unaligned_access))
+ if (Arg *A = Args.getLastArg(
+ options::OPT_mstrict_align, options::OPT_mno_strict_align,
+ options::OPT_mno_unaligned_access, options::OPT_munaligned_access)) {
+if (A->getOption().matches(options::OPT_mstrict_align) ||
+A->getOption().matches(options::OPT_mno_unaligned_access))
wzssyqa wrote:
Why keep `mno_unaligned_access` for AArch64 while remove it from RISC-V and
LoongArch?
In fact `mno_unaligned_access` is not supported by GCC for AArch64?
https://github.com/llvm/llvm-project/pull/85350
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[clang] [Driver] Don't alias -mstrict-align to -mno-unaligned-access (PR #85350)
@@ -321,9 +321,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
}
}
- if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
- options::OPT_munaligned_access)) {
-if (A->getOption().matches(options::OPT_mno_unaligned_access))
+ if (Arg *A = Args.getLastArg(
+ options::OPT_mstrict_align, options::OPT_mno_strict_align,
+ options::OPT_mno_unaligned_access, options::OPT_munaligned_access)) {
+if (A->getOption().matches(options::OPT_mstrict_align) ||
+A->getOption().matches(options::OPT_mno_unaligned_access))
wzssyqa wrote:
LGTM.
I will add `strict_align` for MIPSr6 to GCC, and rebase my PR to LLVM.
https://github.com/llvm/llvm-project/pull/85350
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[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/85174
>From e75523f5ab1bb58a495afdd30203a0c7c93c7ec4 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)strict-align for r6
MIPSr6 ISA requires normal load/store instructions support
misunaligned memory access, while it is not always do so
by hardware. On some microarchitectures or some corner cases
it may need support by OS.
Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't
support them, instead, r6 requires lw instruction support
misunaligned memory access. So, if -mstrict-align is used for
pre-R6, lwl/lwr won't be disabled.
If -mstrict-align is used for r6 and the access is not well
aligned, some lb/lh instructions will be used to replace lw.
This is useful for OS kernels.
To be back-compatible with GCC, -m(no-)unaligned-access are also
added as Neg-Alias of -m(no-)strict-align.
---
clang/include/clang/Driver/Options.td | 4 +-
clang/lib/Driver/ToolChains/Arch/Mips.cpp | 13
clang/test/Driver/mips-features.c | 26 +++
llvm/lib/Target/Mips/Mips.td | 4 ++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 16 -
llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 11 ++-
llvm/lib/Target/Mips/MipsSubtarget.cpp| 2 +-
llvm/lib/Target/Mips/MipsSubtarget.h | 7 +-
llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 10 +--
.../CodeGen/Mips/no-unaligned-access-r6.ll| 69 +++
10 files changed, 149 insertions(+), 13 deletions(-)
create mode 100644 llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index acb7592e98100a..6567e7a7a9a745 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4704,9 +4704,9 @@ def mrvv_vector_bits_EQ : Joined<["-"],
"mrvv-vector-bits=">, Group,
" (RISC-V only)")>;
def munaligned_access : Flag<["-"], "munaligned-access">, Group,
- HelpText<"Allow memory accesses to be unaligned (AArch32 only)">;
+ HelpText<"Allow memory accesses to be unaligned (AArch32/MIPSr6 only)">;
def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
- HelpText<"Force all memory accesses to be aligned (AArch32 only)">;
+ HelpText<"Force all memory accesses to be aligned (AArch32/MIPSr6 only)">;
def munaligned_symbols : Flag<["-"], "munaligned-symbols">, Group,
HelpText<"Expect external char-aligned symbols to be without ABI alignment
(SystemZ only)">;
def mno_unaligned_symbols : Flag<["-"], "mno-unaligned-symbols">,
Group,
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index fe9d112b8800b1..b6c8a897106f20 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -341,6 +341,19 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
"dspr2");
AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
+ AddTargetFeature(Args, Features, options::OPT_mstrict_align,
+ options::OPT_mno_strict_align, "strict-align");
+ AddTargetFeature(Args, Features, options::OPT_mno_unaligned_access,
+ options::OPT_munaligned_access, "strict-align");
+ if (Arg *A = Args.getLastArg(
+ options::OPT_mstrict_align, options::OPT_mno_strict_align,
+ options::OPT_mno_unaligned_access, options::OPT_munaligned_access)) {
+if (A->getOption().matches(options::OPT_mstrict_align) ||
+A->getOption().matches(options::OPT_mno_unaligned_access))
+ Features.push_back(Args.MakeArgString("+strict-align"));
+else
+ Features.push_back(Args.MakeArgString("-strict-align"));
+ }
// Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
// pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
diff --git a/clang/test/Driver/mips-features.c
b/clang/test/Driver/mips-features.c
index fd06b1400c3123..5e92dccaa02abb 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -462,3 +462,29 @@
// RUN: -mrelax-pic-calls -mno-relax-pic-calls 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-NO-RELAX-PIC-CALLS %s
// CHECK-NO-RELAX-PIC-CALLS: "-mllvm" "-mips-jalr-reloc=0"
+//
+// -mno-unaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mno-unaligned-access 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-STRICT-ALIGN %s
+// CHECK-STRICT-ALIGN: "-target-feature" "+strict-align"
+//
+// -munaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -munaligned-access 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-NO-STRICT-ALIGN %s
+//
[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/85174 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/85174
>From 7e1cf74f4fc9271e88b62462ea9a38826fd3ee38 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)strict-align for r6
MIPSr6 ISA requires normal load/store instructions support
misunaligned memory access, while it is not always do so
by hardware. On some microarchitectures or some corner cases
it may need support by OS.
Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't
support them, instead, r6 requires lw instruction support
misunaligned memory access. So, if -mstrict-align is used for
pre-R6, lwl/lwr won't be disabled.
If -mstrict-align is used for r6 and the access is not well
aligned, some lb/lh instructions will be used to replace lw.
This is useful for OS kernels.
To be back-compatible with GCC, -m(no-)unaligned-access are also
added as Neg-Alias of -m(no-)strict-align.
---
clang/include/clang/Driver/Options.td | 4 +-
clang/lib/Driver/ToolChains/Arch/Mips.cpp | 9 +++
clang/test/Driver/mips-features.c | 26 +++
llvm/lib/Target/Mips/Mips.td | 4 ++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 16 -
llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 11 ++-
llvm/lib/Target/Mips/MipsSubtarget.cpp| 2 +-
llvm/lib/Target/Mips/MipsSubtarget.h | 7 +-
llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 10 +--
.../CodeGen/Mips/no-unaligned-access-r6.ll| 69 +++
10 files changed, 145 insertions(+), 13 deletions(-)
create mode 100644 llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index acb7592e98100a..6567e7a7a9a745 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4704,9 +4704,9 @@ def mrvv_vector_bits_EQ : Joined<["-"],
"mrvv-vector-bits=">, Group,
" (RISC-V only)")>;
def munaligned_access : Flag<["-"], "munaligned-access">, Group,
- HelpText<"Allow memory accesses to be unaligned (AArch32 only)">;
+ HelpText<"Allow memory accesses to be unaligned (AArch32/MIPSr6 only)">;
def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
- HelpText<"Force all memory accesses to be aligned (AArch32 only)">;
+ HelpText<"Force all memory accesses to be aligned (AArch32/MIPSr6 only)">;
def munaligned_symbols : Flag<["-"], "munaligned-symbols">, Group,
HelpText<"Expect external char-aligned symbols to be without ABI alignment
(SystemZ only)">;
def mno_unaligned_symbols : Flag<["-"], "mno-unaligned-symbols">,
Group,
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index fe9d112b8800b1..74a8874a3ea2b7 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -341,6 +341,15 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
"dspr2");
AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
+ if (Arg *A = Args.getLastArg(
+ options::OPT_mstrict_align, options::OPT_mno_strict_align,
+ options::OPT_mno_unaligned_access, options::OPT_munaligned_access)) {
+if (A->getOption().matches(options::OPT_mstrict_align) ||
+A->getOption().matches(options::OPT_mno_unaligned_access))
+ Features.push_back(Args.MakeArgString("+strict-align"));
+else
+ Features.push_back(Args.MakeArgString("-strict-align"));
+ }
// Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
// pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
diff --git a/clang/test/Driver/mips-features.c
b/clang/test/Driver/mips-features.c
index fd06b1400c3123..5e92dccaa02abb 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -462,3 +462,29 @@
// RUN: -mrelax-pic-calls -mno-relax-pic-calls 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-NO-RELAX-PIC-CALLS %s
// CHECK-NO-RELAX-PIC-CALLS: "-mllvm" "-mips-jalr-reloc=0"
+//
+// -mno-unaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mno-unaligned-access 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-STRICT-ALIGN %s
+// CHECK-STRICT-ALIGN: "-target-feature" "+strict-align"
+//
+// -munaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -munaligned-access 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-NO-STRICT-ALIGN %s
+// CHECK-NO-STRICT-ALIGN: "-target-feature" "-strict-align"
+//
+// -mstrict-align
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mstrict-align 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-S
[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)
https://github.com/wzssyqa closed https://github.com/llvm/llvm-project/pull/85174 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] MIPS/Clang: Set HasUnalignedAccess false if +strict-align (PR #87256)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/87256
TargetInfo has HasUnalignedAccess support now. For MIPSr6, we should set it
according strict-align.
For pre-R6, we always set strict-align and HasUnalignedAccess to false.
>From ecee40e72582c98e74e89d3aff97a832ece3fd70 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 2 Apr 2024 00:20:55 +0800
Subject: [PATCH] MIPS/Clang: Set HasUnalignedAccess false if +strict-align
TargetInfo has HasUnalignedAccess support now. For MIPSr6,
we should set it according strict-align.
For pre-R6, we always set strict-align and HasUnalignedAccess to
false.
---
clang/lib/Basic/Targets/Mips.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index c9dcf434c93b0b..f5ce1bc735a700 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -318,6 +318,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
FPMode = isFP64Default() ? FP64 : FPXX;
NoOddSpreg = false;
bool OddSpregGiven = false;
+bool StrictAlign = false;
for (const auto &Feature : Features) {
if (Feature == "+single-float")
@@ -330,6 +331,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
IsMicromips = true;
else if (Feature == "+mips32r6" || Feature == "+mips64r6")
HasUnalignedAccess = true;
+ else if (Feature == "+strict-align")
+StrictAlign = true;
else if (Feature == "+dsp")
DspRev = std::max(DspRev, DSP1);
else if (Feature == "+dspr2")
@@ -368,6 +371,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
if (FPMode == FPXX && !OddSpregGiven)
NoOddSpreg = true;
+if (StrictAlign)
+ HasUnalignedAccess = false;
+
setDataLayout();
return true;
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[clang] MIPS/Clang: Set HasUnalignedAccess false if +strict-align (PR #87257)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/87257
TargetInfo has HasUnalignedAccess support now. For MIPSr6, we should set it
according strict-align.
For pre-R6, we always set strict-align and HasUnalignedAccess to false.
>From ecee40e72582c98e74e89d3aff97a832ece3fd70 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 2 Apr 2024 00:20:55 +0800
Subject: [PATCH] MIPS/Clang: Set HasUnalignedAccess false if +strict-align
TargetInfo has HasUnalignedAccess support now. For MIPSr6,
we should set it according strict-align.
For pre-R6, we always set strict-align and HasUnalignedAccess to
false.
---
clang/lib/Basic/Targets/Mips.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index c9dcf434c93b0b..f5ce1bc735a700 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -318,6 +318,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
FPMode = isFP64Default() ? FP64 : FPXX;
NoOddSpreg = false;
bool OddSpregGiven = false;
+bool StrictAlign = false;
for (const auto &Feature : Features) {
if (Feature == "+single-float")
@@ -330,6 +331,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
IsMicromips = true;
else if (Feature == "+mips32r6" || Feature == "+mips64r6")
HasUnalignedAccess = true;
+ else if (Feature == "+strict-align")
+StrictAlign = true;
else if (Feature == "+dsp")
DspRev = std::max(DspRev, DSP1);
else if (Feature == "+dspr2")
@@ -368,6 +371,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
if (FPMode == FPXX && !OddSpregGiven)
NoOddSpreg = true;
+if (StrictAlign)
+ HasUnalignedAccess = false;
+
setDataLayout();
return true;
___
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[clang] MIPS/Clang: Set HasUnalignedAccess false if +strict-align (PR #87257)
@@ -330,6 +331,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
IsMicromips = true;
else if (Feature == "+mips32r6" || Feature == "+mips64r6")
HasUnalignedAccess = true;
+ else if (Feature == "+strict-align")
+StrictAlign = true;
wzssyqa wrote:
We cannot due to that +strict-align may be listed before +mips32/64.
I have some try. In all my try, +mips32/64 appeared before +strict-align.
But I am not sure that +mips32/64 will always appear before +strict-align.
https://github.com/llvm/llvm-project/pull/87257
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[clang] Clang: Return new layout path if cannot find CRT (PR #87319)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/87319
In ToolChain::getCompilerRT:
If none is found, use a file name from the new layout, which may get
printed in an error message, aiding users in knowing what Clang is
looking for.
But in current code, the old layout is printed if no libclang_rt.builtin is
found with cmd like:
./bin/clang --target=aarch64-linux-gnu -rtlib=compiler-rt hello.c
aarch64-linux-gnu/bin/ld: cannot find
/lib/clang/19/lib/linux/libclang_rt.builtins-aarch64.a: No such file or
directory
>From 2c8132f08eedfe522ca4dcdcc5bbb11ffb629dd2 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 2 Apr 2024 15:50:23 +0800
Subject: [PATCH] Clang: Return new layout path if cannot find CRT
In ToolChain::getCompilerRT:
// If none is found, use a file name from the new layout, which may get
// printed in an error message, aiding users in knowing what Clang is
// looking for.
But in current code, the old layout is printed if no
libclang_rt.builtin is found with cmd like:
./bin/clang --target=aarch64-linux-gnu -rtlib=compiler-rt hello.c
---
clang/lib/Driver/ToolChain.cpp | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 03450fc0f57b93..3b5960992a9dd1 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -692,12 +692,21 @@ std::string ToolChain::getCompilerRT(const ArgList &Args,
StringRef Component,
buildCompilerRTBasename(Args, Component, Type, /*AddArch=*/true);
SmallString<128> OldPath(getCompilerRTPath());
llvm::sys::path::append(OldPath, CRTBasename);
- if (Path.empty() || getVFS().exists(OldPath))
+ if (getVFS().exists(OldPath))
return std::string(OldPath);
// If none is found, use a file name from the new layout, which may get
// printed in an error message, aiding users in knowing what Clang is
// looking for.
+ if (Path.empty()) {
+CRTBasename =
+buildCompilerRTBasename(Args, Component, Type, /*AddArch=*/false);
+SmallString<128> NewP(D.ResourceDir);
+llvm::sys::path::append(NewP, "lib");
+llvm::sys::path::append(NewP, getTriple().str());
+llvm::sys::path::append(NewP, CRTBasename);
+return std::string(NewP);
+ }
return std::string(Path);
}
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[clang] Clang: Return new layout path if cannot find CRT (PR #87319)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/87319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] MIPS/libunwind: Use -mfp64 if compiler is FPXX (PR #68521)
https://github.com/wzssyqa closed https://github.com/llvm/llvm-project/pull/68521 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] MIPS/clang: Disallow constraint f for softfloat (PR #79116)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From afacadad3f6654c60609a8d024ab9b6c0123195d Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then
LLVM meet an internal error.
'r' is rejected by LLVM by:
couldn't allocate input reg for constraint 'r'
Fixes: #64241
---
clang/lib/Basic/Targets/Mips.h| 3 ++
clang/test/Driver/mips-float.c| 47 +++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +++--
3 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c..2b8ad6645e605 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/Driver/mips-float.c b/clang/test/Driver/mips-float.c
index 2f1b813a15322..34cf7fdfb9b79 100644
--- a/clang/test/Driver/mips-float.c
+++ b/clang/test/Driver/mips-float.c
@@ -102,3 +102,50 @@
// CHECK-ABI-SOFT-MIPS16: "-target-feature" "+mips16"
// CHECK-ABI-SOFT-MIPS16: "-msoft-float"
// CHECK-ABI-SOFT-MIPS16: "-mfloat-abi" "soft"
+
+/// On MIPS, don't accept constraint "f" for soft-float.
+// RUN: not %clang -S %s -o %t.s 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float \
+// RUN: -DSOFT_FLOAT_NO_CONSTRAINT_F \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-NO-F %s
+// CHECK-SOFTFLOAT-ASM-NO-F: error: invalid input constraint 'f' in asm
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float* p) {
+float result = *p;
+__asm__("" ::"f"(result));
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
+
+/// On MIPS, accept constraint "r" for soft-float.
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=32 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=float \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-3232 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-3232: lw $2, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=32 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=double \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-3264 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-3264: lw $2, 4($4)
+// CHECK-SOFTFLOAT-ASM-USE-R-3264: lw $3, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=64 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=float \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-6432 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-6432: lw $2, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=64 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=double \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-6464 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-6464: ld $2, 0($4)
+
+#ifdef SOFT_FLOAT_USE_CONSTRAINT_R
+void read_float(FLOAT* p) {
+FLOAT result = *p;
+__asm__("" ::"r"(result));
+}
+#endif // SOFT_FLOAT_USE_CONSTRAINT_R
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d431d3d91494f..88b226eaaccfa 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return s
[llvm] [clang] MIPS/clang: Disallow constraint f for softfloat (PR #79116)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/79116 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [llvm] [clang] MIPS/clang: Disallow constraint f for softfloat (PR #79116)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From afacadad3f6654c60609a8d024ab9b6c0123195d Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then
LLVM meet an internal error.
'r' is rejected by LLVM by:
couldn't allocate input reg for constraint 'r'
Fixes: #64241
---
clang/lib/Basic/Targets/Mips.h| 3 ++
clang/test/Driver/mips-float.c| 47 +++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +++--
3 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c..2b8ad6645e605 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/Driver/mips-float.c b/clang/test/Driver/mips-float.c
index 2f1b813a15322..34cf7fdfb9b79 100644
--- a/clang/test/Driver/mips-float.c
+++ b/clang/test/Driver/mips-float.c
@@ -102,3 +102,50 @@
// CHECK-ABI-SOFT-MIPS16: "-target-feature" "+mips16"
// CHECK-ABI-SOFT-MIPS16: "-msoft-float"
// CHECK-ABI-SOFT-MIPS16: "-mfloat-abi" "soft"
+
+/// On MIPS, don't accept constraint "f" for soft-float.
+// RUN: not %clang -S %s -o %t.s 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float \
+// RUN: -DSOFT_FLOAT_NO_CONSTRAINT_F \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-NO-F %s
+// CHECK-SOFTFLOAT-ASM-NO-F: error: invalid input constraint 'f' in asm
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float* p) {
+float result = *p;
+__asm__("" ::"f"(result));
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
+
+/// On MIPS, accept constraint "r" for soft-float.
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=32 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=float \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-3232 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-3232: lw $2, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=32 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=double \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-3264 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-3264: lw $2, 4($4)
+// CHECK-SOFTFLOAT-ASM-USE-R-3264: lw $3, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=64 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=float \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-6432 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-6432: lw $2, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=64 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=double \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-6464 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-6464: ld $2, 0($4)
+
+#ifdef SOFT_FLOAT_USE_CONSTRAINT_R
+void read_float(FLOAT* p) {
+FLOAT result = *p;
+__asm__("" ::"r"(result));
+}
+#endif // SOFT_FLOAT_USE_CONSTRAINT_R
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d431d3d91494f..88b226eaaccfa 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return s
[clang] [llvm] MIPS/clang: Disallow constraint f for softfloat (PR #79116)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 009bd230a51a1790e6691ae3f104f57af311272f Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then
LLVM meet an internal error.
'r' is rejected by LLVM by:
couldn't allocate input reg for constraint 'r'
Fixes: #64241
---
clang/lib/Basic/Targets/Mips.h| 3 ++
clang/test/Driver/mips-float.c| 47 +++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +++--
3 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c..2b8ad6645e605 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/Driver/mips-float.c b/clang/test/Driver/mips-float.c
index 2f1b813a15322..34cf7fdfb9b79 100644
--- a/clang/test/Driver/mips-float.c
+++ b/clang/test/Driver/mips-float.c
@@ -102,3 +102,50 @@
// CHECK-ABI-SOFT-MIPS16: "-target-feature" "+mips16"
// CHECK-ABI-SOFT-MIPS16: "-msoft-float"
// CHECK-ABI-SOFT-MIPS16: "-mfloat-abi" "soft"
+
+/// On MIPS, don't accept constraint "f" for soft-float.
+// RUN: not %clang -S %s -o %t.s 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float \
+// RUN: -DSOFT_FLOAT_NO_CONSTRAINT_F \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-NO-F %s
+// CHECK-SOFTFLOAT-ASM-NO-F: error: invalid input constraint 'f' in asm
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float* p) {
+float result = *p;
+__asm__("" ::"f"(result));
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
+
+/// On MIPS, accept constraint "r" for soft-float.
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=32 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=float \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-3232 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-3232: lw $2, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=32 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=double \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-3264 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-3264: lw $2, 4($4)
+// CHECK-SOFTFLOAT-ASM-USE-R-3264: lw $3, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=64 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=float \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-6432 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-6432: lw $2, 0($4)
+//
+// RUN: %clang -S %s -o - -O2 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float -mabi=64 \
+// RUN: -DSOFT_FLOAT_USE_CONSTRAINT_R -DFLOAT=double \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-USE-R-6464 %s
+// CHECK-SOFTFLOAT-ASM-USE-R-6464: ld $2, 0($4)
+
+#ifdef SOFT_FLOAT_USE_CONSTRAINT_R
+void read_float(FLOAT* p) {
+FLOAT result = *p;
+__asm__("" ::"r"(result));
+}
+#endif // SOFT_FLOAT_USE_CONSTRAINT_R
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index b2812f87914df..97e830cec27ca 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return s
[clang] [llvm] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/79116 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/79116 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From af69ccc8182f8a1e86637b75a8fb1e717b157354 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then
LLVM meet an internal error.
'r' is rejected by LLVM by:
couldn't allocate input reg for constraint 'r'
Fixes: #64241
---
clang/lib/Basic/Targets/Mips.h| 3 +++
.../CodeGen/Mips/inline-asm-constraints.c | 18 +
clang/test/Sema/inline-asm-validate-mips.c| 8 ++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +---
.../Mips/inlineasm-constraints-softfloat.ll | 25 +++
5 files changed, 61 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CodeGen/Mips/inline-asm-constraints.c
create mode 100644 clang/test/Sema/inline-asm-validate-mips.c
create mode 100644 llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c..2b8ad6645e605 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 0..0a4cb0b34570e
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN:-DSOFT_FLOAT_CONSTRAINT_R \
+// RUN:-DFLOAT=float -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_SINGLE
+
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN:-DSOFT_FLOAT_CONSTRAINT_R \
+// RUN:-DFLOAT=double -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_DOUBLE
+
+#ifdef SOFT_FLOAT_CONSTRAINT_R
+// SOFT_FLOAT_CONSTRAINT_R_SINGLE: call void asm sideeffect "",
"r,~{$1}"(float %2) #1, !srcloc !2
+// SOFT_FLOAT_CONSTRAINT_R_DOUBLE: call void asm sideeffect "",
"r,~{$1}"(double %2) #1, !srcloc !2
+void read_float(FLOAT* p) {
+FLOAT result = *p;
+__asm__("" ::"r"(result));
+}
+#endif // SOFT_FLOAT_CONSTRAINT_R
diff --git a/clang/test/Sema/inline-asm-validate-mips.c
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 0..a56c75f0859a6
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple mips -target-feature +soft-float
-DSOFT_FLOAT_NO_CONSTRAINT_F -fsyntax-only -verify %s
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float* p) {
+float result = *p;
+__asm__("" ::"f"(result)); // expected-error{{invalid input constraint 'f'
in asm}}
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index b2812f87914df..97e830cec27ca 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR64RegClass);
// This will generate an error message
return std::make_pair(0U, nullptr);
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
b/llvm/test/CodeGen/Mips/inlinea
[llvm] [clang] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/79116 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] MIPS/libunwind: Use -mfp64 if compiler is FPXX (PR #68521)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/68521
>From 65db5951e3c30b6c2a112b590839fad6b8ec2944 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Sun, 8 Oct 2023 07:12:45 -0400
Subject: [PATCH] MIPS/libunwind: Use -mfp64 if compiler is FPXX
Libunwind supports FP64 and FP32 modes, but not FPXX.
The reason is that, FP64 and FP32 have different way to save/restore
FPRs. If libunwind is built as FPXX, we have no idea which one should
we use.
If libunwind is built as FP64, it will interoperatable with FPXX/FP64
APPs, and if it is built as FP32, it will interoperatable with
FP32/FPXX. Currently most of O32 APPs are FPXX or FP64, while few are FP32.
So if the compiler is FPXX, which is the default value of most toolchain,
let's switch it to FP64.
---
libunwind/CMakeLists.txt | 19 +++
1 file changed, 19 insertions(+)
diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt
index bb1b052f61d87..806d5a783ec39 100644
--- a/libunwind/CMakeLists.txt
+++ b/libunwind/CMakeLists.txt
@@ -21,6 +21,7 @@ set(LIBUNWIND_LIBCXX_PATH
"${CMAKE_CURRENT_LIST_DIR}/../libcxx" CACHE PATH
"Specify path to libc++ source.")
include(GNUInstallDirs)
+include(CheckSymbolExists)
#===
# Setup CMake Options
@@ -96,6 +97,20 @@ endif()
option(LIBUNWIND_HIDE_SYMBOLS
"Do not export any symbols from the static library."
${LIBUNWIND_DEFAULT_HIDE_SYMBOLS})
+# If toolchain is FPXX, we switch to FP64 to save the full FPRs. See:
+#
https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
+check_symbol_exists(__mips_hard_float "" __MIPSHF)
+check_symbol_exists(_ABIO32 "" __MIPS_O32)
+if (__MIPSHF AND __MIPS_O32)
+ file(WRITE
${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/mips_is_fpxx.c
+"#if __mips_fpr != 0\n"
+"# error\n"
+"#endif\n")
+ try_compile(MIPS_FPABI_FPXX ${CMAKE_BINARY_DIR}
+${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/mips_is_fpxx.c
+CMAKE_FLAGS -DCMAKE_C_LINK_EXECUTABLE='echo')
+endif()
+
#===
# Configure System
#===
@@ -179,6 +194,10 @@ if (WIN32)
add_compile_flags_if_supported(-Wno-dll-attribute-on-redeclaration)
endif()
+if (MIPS_FPABI_FPXX)
+ add_compile_flags(-mfp64)
+endif()
+
# Get feature flags.
# Exceptions
# Catches C++ exceptions only and tells the compiler to assume that extern C
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[libunwind] MIPS/libunwind: Use -mfp64 if compiler is FPXX (PR #68521)
wzssyqa wrote: Fangrui Song ***@***.***> 于2024年2月6日周二 13:36写道： > Libunwind supports FP64 and FP32 modes, but not FPXX. The reason is that, > FP64 and FP32 have different way to save/restore FPRs. If libunwind is > built as FPXX, we have no idea which one should we use. > > Can you edit the description to name the code that doesn't support FPXX? > > > It's not due to the code bug, but rather the nature of FPXX. FPXX is an ABI which uses only a common subset of FR=1(FP64) and FR=0 (FP32). So that FPXX binaries can link with both FP64 and FP32 ones, aka. FPXX + FP32 -> FP32 FPXX + FP64 -> FP64 While for libunwind, we should save/restore all of FPRs. If we use FPXX, we can only save/restore a common subset of FPRs, instead of superset. https://github.com/llvm/llvm-project/pull/68521 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] MIPS/libunwind: Use -mfp64 if compiler is FPXX (PR #68521)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/68521 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] MIPS/clang: Disallow constraint f for softfloat (PR #79116)
wzssyqa wrote: @MaskRay https://github.com/llvm/llvm-project/pull/79116 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] MIPS/clang: Disallow constraint f for softfloat (PR #79116)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/79116
Currently, clang accpets contraint f for softfloat, then LLVM meet an internal
error.
See: #64241
>From f01ce8f18a8cfaed41b4cfdd8b039abfc76aefd4 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Disallow constraint f for softfloat
Currently, clang accpets contraint f for softfloat, then
LLVM meet an internal error.
See: #64241
---
clang/lib/Basic/Targets/Mips.h | 3 +++
clang/test/Driver/mips-float.c | 14 ++
2 files changed, 17 insertions(+)
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c73..2b8ad6645e605fc 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/Driver/mips-float.c b/clang/test/Driver/mips-float.c
index 2f1b813a153224c..bbf17abfb13839f 100644
--- a/clang/test/Driver/mips-float.c
+++ b/clang/test/Driver/mips-float.c
@@ -102,3 +102,17 @@
// CHECK-ABI-SOFT-MIPS16: "-target-feature" "+mips16"
// CHECK-ABI-SOFT-MIPS16: "-msoft-float"
// CHECK-ABI-SOFT-MIPS16: "-mfloat-abi" "soft"
+
+/// On MIPS, don't accept constraint "f" for soft-float.
+// RUN: not %clang -S %s -o %t.s 2>&1 \
+// RUN: -target mips-linux-gnu -msoft-float \
+// RUN: -DSOFT_FLOAT_NO_CONSTRAINT_F \
+// RUN: | FileCheck --check-prefix=CHECK-SOFTFLOAT-ASM-NO-F %s
+// CHECK-SOFTFLOAT-ASM-NO-F: error: invalid input constraint 'f' in asm
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float* p) {
+float result = *p;
+__asm__("" ::"f"(result));
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
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[libunwind] MIPS/libunwind: Use -mfp64 if compiler is FPXX (PR #68521)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/68521
Libunwind supports FP64 and FP32 modes, but not FPXX. The reason is that, FP64
and FP32 have different way to save/restore FPRs. If libunwind is built as
FPXX, we have no idea which one should we use.
If libunwind is built as FP64, it will interoperatable with FPXX/FP64 APPs, and
if it is built as FP32, it will interoperatable with FP32/FPXX. Currently most
of O32 APPs are FPXX or FP64, while few are FP32.
So if the compiler is FPXX, which is the default value of most toolchain, let's
switch it to FP64.
>From dad17bc3806edd2055fae654a023f4c5473a8276 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Sun, 8 Oct 2023 07:12:45 -0400
Subject: [PATCH] MIPS/libunwind: Use -mfp64 if compiler is FPXX
Libunwind supports FP64 and FP32 modes, but not FPXX.
The reason is that, FP64 and FP32 have different way to save/restore
FPRs. If libunwind is built as FPXX, we have no idea which one should
we use.
If libunwind is built as FP64, it will interoperatable with FPXX/FP64
APPs, and if it is built as FP32, it will interoperatable with
FP32/FPXX. Currently most of O32 APPs are FPXX or FP64, while few are FP32.
So if the compiler is FPXX, which is the default value of most toolchain,
let's switch it to FP64.
---
libunwind/CMakeLists.txt | 19 +++
1 file changed, 19 insertions(+)
diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt
index 84f8ce296a7410b..387d4b43b5746a6 100644
--- a/libunwind/CMakeLists.txt
+++ b/libunwind/CMakeLists.txt
@@ -21,6 +21,7 @@ set(LIBUNWIND_LIBCXX_PATH
"${CMAKE_CURRENT_LIST_DIR}/../libcxx" CACHE PATH
"Specify path to libc++ source.")
include(GNUInstallDirs)
+include(CheckSymbolExists)
#===
# Setup CMake Options
@@ -101,6 +102,20 @@ endif()
option(LIBUNWIND_HIDE_SYMBOLS
"Do not export any symbols from the static library."
${LIBUNWIND_DEFAULT_HIDE_SYMBOLS})
+# If toolchain is FPXX, we switch to FP64 to save the full FPRs. See:
+#
https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
+check_symbol_exists(__mips_hard_float "" __MIPSHF)
+check_symbol_exists(_ABIO32 "" __MIPS_O32)
+if (__MIPSHF AND __MIPS_O32)
+ file(WRITE
${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/mips_is_fpxx.c
+"#if __mips_fpr != 0\n"
+"# error\n"
+"#endif\n")
+ try_compile(MIPS_FPABI_FPXX ${CMAKE_BINARY_DIR}
+${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/mips_is_fpxx.c
+CMAKE_FLAGS -DCMAKE_C_LINK_EXECUTABLE='echo')
+endif()
+
#===
# Configure System
#===
@@ -184,6 +199,10 @@ if (WIN32)
add_compile_flags_if_supported(-Wno-dll-attribute-on-redeclaration)
endif()
+if (MIPS_FPABI_FPXX)
+ add_compile_flags(-mfp64)
+endif()
+
# Get feature flags.
# Exceptions
# Catches C++ exceptions only and tells the compiler to assume that extern C
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[clang] [llvm] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 0ea3b2be9d364a042c7e7114b0f72fc3c144d2a0 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then
LLVM meet an internal error.
'r' is rejected by LLVM by:
couldn't allocate input reg for constraint 'r'
Fixes: #64241
---
clang/lib/Basic/Targets/Mips.h| 3 +++
.../CodeGen/Mips/inline-asm-constraints.c | 18 +
clang/test/Sema/inline-asm-validate-mips.c| 8 ++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +---
.../Mips/inlineasm-constraints-softfloat.ll | 25 +++
5 files changed, 61 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CodeGen/Mips/inline-asm-constraints.c
create mode 100644 clang/test/Sema/inline-asm-validate-mips.c
create mode 100644 llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c7..2b8ad6645e605f 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 00..0a4cb0b34570e6
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN:-DSOFT_FLOAT_CONSTRAINT_R \
+// RUN:-DFLOAT=float -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_SINGLE
+
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN:-DSOFT_FLOAT_CONSTRAINT_R \
+// RUN:-DFLOAT=double -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_DOUBLE
+
+#ifdef SOFT_FLOAT_CONSTRAINT_R
+// SOFT_FLOAT_CONSTRAINT_R_SINGLE: call void asm sideeffect "",
"r,~{$1}"(float %2) #1, !srcloc !2
+// SOFT_FLOAT_CONSTRAINT_R_DOUBLE: call void asm sideeffect "",
"r,~{$1}"(double %2) #1, !srcloc !2
+void read_float(FLOAT* p) {
+FLOAT result = *p;
+__asm__("" ::"r"(result));
+}
+#endif // SOFT_FLOAT_CONSTRAINT_R
diff --git a/clang/test/Sema/inline-asm-validate-mips.c
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 00..5a123cc5fa79c3
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple mips -target-feature +soft-float
-DSOFT_FLOAT_NO_CONSTRAINT_F -fsyntax-only -verify %s
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float p) {
+float result = p;
+__asm__("" ::"f"(result)); // expected-error{{invalid input constraint 'f'
in asm}}
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index b2812f87914df7..97e830cec27cad 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR64RegClass);
// This will generate an error message
return std::make_pair(0U, nullptr);
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
b/llvm/test/CodeGen/Mips/i
[clang] [llvm] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
@@ -0,0 +1,25 @@
+; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -march=mips64 < %s | FileCheck %s --check-prefix=MIPS64
+
+define dso_local void @read_double(double* nocapture noundef readonly %0)
local_unnamed_addr #0 {
wzssyqa wrote:
Thanks.
https://github.com/llvm/llvm-project/pull/79116
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[clang] [llvm] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple mips -target-feature +soft-float
-DSOFT_FLOAT_NO_CONSTRAINT_F -fsyntax-only -verify %s
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float* p) {
wzssyqa wrote:
Oh, yes. we can use `float p` here.
https://github.com/llvm/llvm-project/pull/79116
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[clang] [llvm] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 838394878054831066e563fa243665ba6d68d824 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then
LLVM meet an internal error.
'r' is rejected by LLVM by:
couldn't allocate input reg for constraint 'r'
Fixes: #64241
---
clang/lib/Basic/Targets/Mips.h| 3 +++
.../CodeGen/Mips/inline-asm-constraints.c | 18 +
clang/test/Sema/inline-asm-validate-mips.c| 8 ++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +---
.../Mips/inlineasm-constraints-softfloat.ll | 25 +++
5 files changed, 61 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CodeGen/Mips/inline-asm-constraints.c
create mode 100644 clang/test/Sema/inline-asm-validate-mips.c
create mode 100644 llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c7..2b8ad6645e605f 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 00..0a4cb0b34570e6
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN:-DSOFT_FLOAT_CONSTRAINT_R \
+// RUN:-DFLOAT=float -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_SINGLE
+
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN:-DSOFT_FLOAT_CONSTRAINT_R \
+// RUN:-DFLOAT=double -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_DOUBLE
+
+#ifdef SOFT_FLOAT_CONSTRAINT_R
+// SOFT_FLOAT_CONSTRAINT_R_SINGLE: call void asm sideeffect "",
"r,~{$1}"(float %2) #1, !srcloc !2
+// SOFT_FLOAT_CONSTRAINT_R_DOUBLE: call void asm sideeffect "",
"r,~{$1}"(double %2) #1, !srcloc !2
+void read_float(FLOAT* p) {
+FLOAT result = *p;
+__asm__("" ::"r"(result));
+}
+#endif // SOFT_FLOAT_CONSTRAINT_R
diff --git a/clang/test/Sema/inline-asm-validate-mips.c
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 00..5a123cc5fa79c3
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple mips -target-feature +soft-float
-DSOFT_FLOAT_NO_CONSTRAINT_F -fsyntax-only -verify %s
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float p) {
+float result = p;
+__asm__("" ::"f"(result)); // expected-error{{invalid input constraint 'f'
in asm}}
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index b2812f87914df7..97e830cec27cad 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR64RegClass);
// This will generate an error message
return std::make_pair(0U, nullptr);
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
b/llvm/test/CodeGen/Mips/i
[clang] [clang] Better bitfield access units (PR #65742)
wzssyqa wrote: For MIPSr6, it is just like AARCH64, since some microarchitecture doesn't support mis-unaligned well in hardware level, so we need an options to disable it: kernel may need it. For GCC, we have `-mno-unalgined-access`. We need also add this option to clang. https://github.com/llvm/llvm-project/pull/65742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] Better bitfield access units (PR #65742)
wzssyqa wrote: > `-mno-unalgined-access` has been added since clang17: > https://reviews.llvm.org/D149946 This option is for LoongArch instead of MIPSr6. https://github.com/llvm/llvm-project/pull/65742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] MIPS/clang: Fix asm constraint for softfloat (PR #79116)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 0da681135e785b01d67b0cef02581e0bba028ef3 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then
LLVM meet an internal error.
'r' is rejected by LLVM by:
couldn't allocate input reg for constraint 'r'
Fixes: #64241
---
clang/lib/Basic/Targets/Mips.h| 3 +++
.../CodeGen/Mips/inline-asm-constraints.c | 18 +
clang/test/Sema/inline-asm-validate-mips.c| 8 ++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +---
.../Mips/inlineasm-constraints-softfloat.ll | 25 +++
5 files changed, 61 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CodeGen/Mips/inline-asm-constraints.c
create mode 100644 clang/test/Sema/inline-asm-validate-mips.c
create mode 100644 llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c7..2b8ad6645e605f 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 00..0a4cb0b34570e6
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN:-DSOFT_FLOAT_CONSTRAINT_R \
+// RUN:-DFLOAT=float -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_SINGLE
+
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN:-DSOFT_FLOAT_CONSTRAINT_R \
+// RUN:-DFLOAT=double -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_DOUBLE
+
+#ifdef SOFT_FLOAT_CONSTRAINT_R
+// SOFT_FLOAT_CONSTRAINT_R_SINGLE: call void asm sideeffect "",
"r,~{$1}"(float %2) #1, !srcloc !2
+// SOFT_FLOAT_CONSTRAINT_R_DOUBLE: call void asm sideeffect "",
"r,~{$1}"(double %2) #1, !srcloc !2
+void read_float(FLOAT* p) {
+FLOAT result = *p;
+__asm__("" ::"r"(result));
+}
+#endif // SOFT_FLOAT_CONSTRAINT_R
diff --git a/clang/test/Sema/inline-asm-validate-mips.c
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 00..5a123cc5fa79c3
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple mips -target-feature +soft-float
-DSOFT_FLOAT_NO_CONSTRAINT_F -fsyntax-only -verify %s
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float p) {
+float result = p;
+__asm__("" ::"f"(result)); // expected-error{{invalid input constraint 'f'
in asm}}
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index b2812f87914df7..97e830cec27cad 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR64RegClass);
// This will generate an error message
return std::make_pair(0U, nullptr);
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
b/llvm/test/CodeGen/Mips/i
[clang] [clang] Better bitfield access units (PR #65742)
@@ -132,6 +132,7 @@ class LLVM_LIBRARY_VISIBILITY LoongArch64TargetInfo
: LoongArchTargetInfo(Triple, Opts) {
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
IntMaxType = Int64Type = SignedLong;
+HasCheapUnalignedBitfieldAccess = true;
wzssyqa wrote:
Only set it to true when -mno-unaligned-access.
https://github.com/llvm/llvm-project/pull/65742
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[clang] [clang] Better bitfield access units (PR #65742)
@@ -132,6 +132,7 @@ class LLVM_LIBRARY_VISIBILITY LoongArch64TargetInfo
: LoongArchTargetInfo(Triple, Opts) {
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
IntMaxType = Int64Type = SignedLong;
+HasCheapUnalignedBitfieldAccess = true;
wzssyqa wrote:
Same to MIPS, while there is no -mno-unaligned-access for MIPS yet. I will add
it support.
https://github.com/llvm/llvm-project/pull/65742
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[clang] [clang] Better bitfield access units (PR #65742)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/65742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] Better bitfield access units (PR #65742)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/65742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] Better bitfield access units (PR #65742)
@@ -132,6 +132,7 @@ class LLVM_LIBRARY_VISIBILITY LoongArch64TargetInfo
: LoongArchTargetInfo(Triple, Opts) {
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
IntMaxType = Int64Type = SignedLong;
+HasCheapUnalignedBitfieldAccess = true;
wzssyqa wrote:
> > Only set it to true when -mno-unaligned-access.
>
> In `LoongArchTargetInfo::handleTargetFeatures()`, we can handle the feature
> `-ual`.
Maybe it's true, while you may need it if you need to build a generic kernel
image for both microarchitectures.
https://github.com/llvm/llvm-project/pull/65742
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[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
@@ -368,14 +368,22 @@ macro(construct_compiler_rt_default_triple)
"Default triple for which compiler-rt runtimes will be built.")
endif()
- if ("${CMAKE_C_COMPILER_ID}" MATCHES "Clang")
+ if(CMAKE_C_COMPILER_ID MATCHES "Clang")
set(option_prefix "")
if (CMAKE_C_SIMULATE_ID MATCHES "MSVC")
set(option_prefix "/clang:")
endif()
-execute_process(COMMAND ${CMAKE_C_COMPILER}
${option_prefix}--target=${COMPILER_RT_DEFAULT_TARGET_TRIPLE}
${option_prefix}-print-target-triple
-OUTPUT_VARIABLE COMPILER_RT_DEFAULT_TARGET_TRIPLE
-OUTPUT_STRIP_TRAILING_WHITESPACE)
+set(print_target_triple ${CMAKE_C_COMPILER}
${option_prefix}--target=${COMPILER_RT_DEFAULT_TARGET_TRIPLE}
${option_prefix}-print-target-triple)
+execute_process(COMMAND ${print_target_triple}
+ RESULT_VARIABLE result
+ OUTPUT_VARIABLE output
+ OUTPUT_STRIP_TRAILING_WHITESPACE)
+if(result EQUAL 0)
+ set(COMPILER_RT_DEFAULT_TARGET_TRIPLE ${output})
+else()
+ string(REPLACE ";" " " print_target_triple "${print_target_triple}")
+ message(WARNING "Failed to execute `${print_target_triple}` to normalize
target triple.")
wzssyqa wrote:
Maybe you are right. I tested with some quite bad --target values, it will
output the original values.
So, I think that it will be safe. Anyway, a warning is OK for me as I think
that it won't be used at all.
https://github.com/llvm/llvm-project/pull/89425
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[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
@@ -183,6 +183,24 @@ message(STATUS "LLVM default target triple:
${LLVM_DEFAULT_TARGET_TRIPLE}")
set(LLVM_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}")
+if(CMAKE_C_COMPILER_ID MATCHES "Clang")
+ set(option_prefix "")
+ if (CMAKE_C_SIMULATE_ID MATCHES "MSVC")
+set(option_prefix "/clang:")
+ endif()
+ set(print_target_triple ${CMAKE_C_COMPILER}
${option_prefix}--target=${LLVM_DEFAULT_TARGET_TRIPLE}
${option_prefix}-print-target-triple)
+ execute_process(COMMAND ${print_target_triple}
+RESULT_VARIABLE result
+OUTPUT_VARIABLE output
+OUTPUT_STRIP_TRAILING_WHITESPACE)
+ if(result EQUAL 0)
+set(LLVM_DEFAULT_TARGET_TRIPLE ${output})
+ else()
+string(REPLACE ";" " " print_target_triple "${print_target_triple}")
wzssyqa wrote:
Since most of the CIs monitor the commit only. I have no idea how to trigger
them before commit.
https://github.com/llvm/llvm-project/pull/89425
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[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
wzssyqa wrote: > @wzssyqa Is it OK with you if I go ahead and merge this PR? I plan to follow > up with further improvements but this is necessary to fix the build of LLVM > runtime libraries in the bootstrapping build. It is OK for me, while I have no permission to approve such a patch. https://github.com/llvm/llvm-project/pull/89425 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Ensure ToolChain::LibraryPaths is not empty (PR #87866)
https://github.com/wzssyqa approved this pull request. https://github.com/llvm/llvm-project/pull/87866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Clang: Return new layout path if cannot find CRT (PR #87319)
https://github.com/wzssyqa closed https://github.com/llvm/llvm-project/pull/87319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Clang: Return new layout path if cannot find CRT (PR #87319)
wzssyqa wrote: Replaced by: https://github.com/llvm/llvm-project/issues/87150 https://github.com/llvm/llvm-project/pull/87319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #87866)
wzssyqa wrote: For me, I think that it is a good idea to always warn/hint the full/normalized path. For compatible reason, we can still try to find libraries in old-style or non-full/normalized paths, while should not hint them. https://github.com/llvm/llvm-project/pull/87866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Look for compiler-rt from subdir given by --target (PR #88334)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/88334
Currently, clang looks for compiler-rt only from the normalized triple subdir.
While if we are configured with a non-normalized triple with
-DLLVM_DEFAULT_TARGET_TRIPLE, such as triples without vendor section, clang
will fail to find compiler_rt.
Let's look for compiler_rt from the subdir with name from --target option, too.
To archive this, we add a new member called Origin to class Triple.
Fixes: #87150.
>From a4d6590cf3cecf90b3914933313749e8aad03210 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Mon, 1 Apr 2024 17:17:08 +0800
Subject: [PATCH] Look for compiler-rt from subdir given by --target
Currently, clang looks for compiler-rt only from the normalized
triple subdir. While if we are configured with a non-normalized
triple with -DLLVM_DEFAULT_TARGET_TRIPLE, such as triples without
vendor section, clang will fail to find compiler_rt.
Let's look for compiler_rt from the subdir with name from --target
option.
To archive this, we add a new member called Origin to class Triple.
Fixes: #87150.
---
clang/lib/Driver/Driver.cpp | 1 +
clang/lib/Driver/ToolChain.cpp | 6 ++
llvm/include/llvm/TargetParser/Triple.h | 6 ++
llvm/lib/TargetParser/Triple.cpp| 6 +++---
4 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index e7335a61b10c53..4a0c939039eb31 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -516,6 +516,7 @@ static llvm::Triple computeTargetTriple(const Driver &D,
TargetTriple = A->getValue();
llvm::Triple Target(llvm::Triple::normalize(TargetTriple));
+ Target.setOrigin(TargetTriple);
// GNU/Hurd's triples should have been -hurd-gnu*, but were historically made
// -gnu* only, and we can not change this, so we have to detect that case as
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 237092ed07e5dc..57f27a61c4060b 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -755,6 +755,12 @@ std::optional
ToolChain::getTargetSubDirPath(StringRef BaseDir) const {
auto getPathForTriple =
[&](const llvm::Triple &Triple) -> std::optional {
+if (!Triple.getOrigin().empty()) {
+ SmallString<128> Po(BaseDir);
+ llvm::sys::path::append(Po, Triple.getOrigin());
+ if (getVFS().exists(Po))
+return std::string(Po);
+}
SmallString<128> P(BaseDir);
llvm::sys::path::append(P, Triple.str());
if (getVFS().exists(P))
diff --git a/llvm/include/llvm/TargetParser/Triple.h
b/llvm/include/llvm/TargetParser/Triple.h
index f256e2b205a889..a2fc28ada0ca31 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -298,6 +298,8 @@ class Triple {
private:
std::string Data;
+ StringRef Origin = StringRef();
+
/// The parsed arch type.
ArchType Arch{};
@@ -425,6 +427,8 @@ class Triple {
const std::string &getTriple() const { return Data; }
+ const StringRef getOrigin() const { return Origin; }
+
/// Get the architecture (first) component of the triple.
StringRef getArchName() const;
@@ -1058,6 +1062,8 @@ class Triple {
/// @name Mutators
/// @{
+ void setOrigin(StringRef Orig) { Origin = Orig; };
+
/// Set the architecture (first) component of the triple to a known type.
void setArch(ArchType Kind, SubArchType SubArch = NoSubArch);
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index 624679ff507a7f..ce44903d0f7d70 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -928,9 +928,9 @@ static Triple::ObjectFormatType getDefaultFormat(const
Triple &T) {
/// This stores the string representation and parses the various pieces into
/// enum members.
Triple::Triple(const Twine &Str)
-: Data(Str.str()), Arch(UnknownArch), SubArch(NoSubArch),
- Vendor(UnknownVendor), OS(UnknownOS), Environment(UnknownEnvironment),
- ObjectFormat(UnknownObjectFormat) {
+: Data(Str.str()), Origin(Str.getSingleStringRef()), Arch(UnknownArch),
+ SubArch(NoSubArch), Vendor(UnknownVendor), OS(UnknownOS),
+ Environment(UnknownEnvironment), ObjectFormat(UnknownObjectFormat) {
// Do minimal parsing by hand here.
SmallVector Components;
StringRef(Data).split(Components, '-', /*MaxSplit*/ 3);
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[clang] [llvm] Look for compiler-rt from subdir given by --target (PR #88334)
https://github.com/wzssyqa converted_to_draft https://github.com/llvm/llvm-project/pull/88334 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #87866)
wzssyqa wrote: @aeubanks The problem is that in your configure, the libclang_rt is please in `/lib/clang/19/lib/linux/libclang_rt.builtins-arm-android.a`, instead of `/lib/clang/19/lib/arm-unknown-linux-android/libclang_rt.builtins.a`. https://github.com/llvm/llvm-project/pull/87866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Look for compiler-rt from subdir given by --target (PR #88334)
wzssyqa wrote: Configure cmd ``` cmake ../llvm -G Ninja -DLLVM_DEFAULT_TARGET_TRIPLE=aarch64-linux-gnu -DLLVM_USE_LINKER=lld -DLLVM_ENABLE_RUNTIMES="compiler-rt;libunwind" -DLLVM_ENABLE_PROJECTS="mlir;clang;clang-tools-extra;lld" -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DCMAKE_BUILD_TYPE=RelWithDebInfo ``` Note, in `-DLLVM_DEFAULT_TARGET_TRIPLE=aarch64-linux-gnu`, there is no `unknown` aka vendor section. With this configure, `libclang_rt.builtin.a` is present in ``` ./lib/clang/19/lib/aarch64-linux-gnu/ ``` While clang expects it in ``` ./lib/clang/19/lib/aarch64-unknown-linux-gnu/ Note "unknown" ``` The reason is that in `computeTargetTriple`, the line ``` llvm::Triple Target(llvm::Triple::normalize(TargetTriple)); ``` convert the triple to normalize. https://github.com/llvm/llvm-project/pull/88334 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #87866)
wzssyqa wrote: > > @aeubanks The problem is that in your configure, the libclang_rt is placed > > in `/lib/clang/19/lib/linux/libclang_rt.builtins-arm-android.a`, > > instead of > > `/lib/clang/19/lib/arm-unknown-linux-android/libclang_rt.builtins.a`. > > The point is that both locations were supposed to be accepted, as they were > before - this PR was not supposed to be a policy change that affects that. Yes. After the patch, both locations are accepted. This patch doesn't break it. The current problem is that in some test cases, `-resource-dir` option are missing. For details: 1. with `--sysroot` option, clang will try to find libclang_rt there. In the failure case, it fails to find. 2. then, clang try to look for libclang_rt from `lib/clang/19/lib/arm-unknown-android/libclang_rt.builtin.a`, and failed. 3. clang try to look for libclang_rt from `lib/clang/19/lib/linux/libclang_rt.builtin-arm-android.a`, and success. Thus the file name of libclang_rt is different with the one in test cases. 4. If 3) failed, clang will fallback to `lib/clang/19/lib/arm-unknown-android/libclang_rt.builtin.a`, then test case success. So, we can add `-resource-dir` to skip 3 for test case. https://github.com/llvm/llvm-project/pull/87866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Look for compiler-rt from subdir given by --target (PR #88334)
wzssyqa wrote: > It's better to do some normalization in CMake. I will try to work in CMake, then. https://github.com/llvm/llvm-project/pull/88334 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #87866)
wzssyqa wrote: [xx.patch](https://github.com/llvm/llvm-project/files/14948921/xx.patch) @aeubanks can you help to test this patch? https://github.com/llvm/llvm-project/pull/87866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #88661)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/88661
Follow-up to #81037.
ToolChain::LibraryPaths holds the new compiler-rt library directory (e.g.
`/tmp/Debug/lib/clang/19/lib/x86_64-unknown-linux-gnu`). However, it might be
empty when the directory does not exist (due to the `if (getVFS().exists(P))`
change in https://reviews.llvm.org/D158475).
If neither the old/new compiler-rt library directories exists, we would suggest
the undesired old compiler-rt file name:
```
% /tmp/Debug/bin/clang++ a.cc -fsanitize=memory -o a
ld.lld: error: cannot open
/tmp/Debug/lib/clang/19/lib/linux/libclang_rt.msan-x86_64.a: No such file or
directory
clang++: error: linker command failed with exit code 1 (use -v to see
invocation)
```
With this change, we will correctly suggest the new compiler-rt file name.
Fix #87150
Pull Request: https://github.com/llvm/llvm-project/pull/87866
>From b8b5c72fefe3e9cbd9782727df75c8bb6eaeec2f Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Mon, 8 Apr 2024 16:51:34 -0700
Subject: [PATCH] Ensure ToolChain::LibraryPaths is not empty for non-Darwin
Follow-up to #81037.
ToolChain::LibraryPaths holds the new compiler-rt library directory
(e.g. `/tmp/Debug/lib/clang/19/lib/x86_64-unknown-linux-gnu`). However,
it might be empty when the directory does not exist (due to the `if
(getVFS().exists(P))` change in https://reviews.llvm.org/D158475).
If neither the old/new compiler-rt library directories exists, we would
suggest the undesired old compiler-rt file name:
```
% /tmp/Debug/bin/clang++ a.cc -fsanitize=memory -o a
ld.lld: error: cannot open
/tmp/Debug/lib/clang/19/lib/linux/libclang_rt.msan-x86_64.a: No such file or
directory
clang++: error: linker command failed with exit code 1 (use -v to see
invocation)
```
With this change, we will correctly suggest the new compiler-rt file name.
Fix #87150
Pull Request: https://github.com/llvm/llvm-project/pull/87866
---
clang/lib/Driver/ToolChain.cpp| 8 -
clang/test/Driver/arm-compiler-rt.c | 14
clang/test/Driver/cl-link.c | 16 -
clang/test/Driver/compiler-rt-unwind.c| 6 ++--
clang/test/Driver/coverage-ld.c | 8 ++---
clang/test/Driver/instrprof-ld.c | 16 -
clang/test/Driver/linux-ld.c | 8 +++--
clang/test/Driver/mingw-sanitizers.c | 16 -
clang/test/Driver/msp430-toolchain.c | 4 +--
.../Driver/print-libgcc-file-name-clangrt.c | 12 +++
clang/test/Driver/print-runtime-dir.c | 6
clang/test/Driver/riscv32-toolchain-extra.c | 6 ++--
clang/test/Driver/riscv32-toolchain.c | 6 ++--
clang/test/Driver/riscv64-toolchain-extra.c | 6 ++--
clang/test/Driver/riscv64-toolchain.c | 6 ++--
clang/test/Driver/sanitizer-ld.c | 36 +++
clang/test/Driver/wasm-toolchain.c| 18 +-
clang/test/Driver/wasm-toolchain.cpp | 16 -
clang/test/Driver/windows-cross.c | 18 +-
clang/test/Driver/zos-ld.c| 12 +++
.../test/Driver/msvc-dependent-lib-flags.f90 | 8 ++---
21 files changed, 127 insertions(+), 119 deletions(-)
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 03450fc0f57b93..237092ed07e5dc 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -796,7 +796,13 @@ ToolChain::getTargetSubDirPath(StringRef BaseDir) const {
std::optional ToolChain::getRuntimePath() const {
SmallString<128> P(D.ResourceDir);
llvm::sys::path::append(P, "lib");
- return getTargetSubDirPath(P);
+ if (auto Ret = getTargetSubDirPath(P))
+return Ret;
+ // Darwin does not use per-target runtime directory.
+ if (Triple.isOSDarwin())
+return {};
+ llvm::sys::path::append(P, Triple.str());
+ return std::string(P);
}
std::optional ToolChain::getStdlibPath() const {
diff --git a/clang/test/Driver/arm-compiler-rt.c
b/clang/test/Driver/arm-compiler-rt.c
index 5e9e528400d08e..cb6c29f48a7814 100644
--- a/clang/test/Driver/arm-compiler-rt.c
+++ b/clang/test/Driver/arm-compiler-rt.c
@@ -10,47 +10,47 @@
// RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \
// RUN: -rtlib=compiler-rt -### %s 2>&1 \
// RUN: | FileCheck %s -check-prefix ARM-GNUEABI
-// ARM-GNUEABI: "{{.*[/\\]}}libclang_rt.builtins-arm.a"
+// ARM-GNUEABI: "{{.*[/\\]}}libclang_rt.builtins.a"
// RUN: %clang -target arm-linux-gnueabi \
// RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \
// RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \
// RUN: -rtlib=compiler-rt -mfloat-abi=hard -### %s 2>&1 \
// RUN: | FileCheck %s -check-prefix ARM-GNUEABI-ABI
-// ARM-GNUEABI-ABI: "{{.*[/\\]}}libclang_rt.builtins-armhf.a"
+// ARM-GNUEABI-ABI: "{{.*[/\\]}}libclang_rt.builtins.a"
// RUN: %clang -target arm-linux-gnueabihf \
// RUN: --sysroo
[clang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #87866)
wzssyqa wrote: New PR with my resource-dir patch: https://github.com/llvm/llvm-project/pull/88661 https://github.com/llvm/llvm-project/pull/87866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #88661)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/88661 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -16055,6 +16145,90 @@ of the two arguments. -0.0 is considered to be less than +0.0 for this intrinsic. Note that these are the semantics specified in the draft of IEEE 754-2019. +.. _i_minimumnum: + +'``llvm.minimumnum.*``' Intrinsic +^ + +Syntax: +""" + +This is an overloaded intrinsic. You can use ``llvm.minimumnum`` on any +floating-point or vector of floating-point type. Not all targets support +all types however. + +:: + + declare float @llvm.minimumnum.f32(float %Val0, float %Val1) + declare double@llvm.minimumnum.f64(double %Val0, double %Val1) + declare x86_fp80 @llvm.minimumnum.f80(x86_fp80 %Val0, x86_fp80 %Val1) + declare fp128 @llvm.minimumnum.f128(fp128 %Val0, fp128 %Val1) + declare ppc_fp128 @llvm.minimumnum.ppcf128(ppc_fp128 %Val0, ppc_fp128 %Val1) + +Overview: +" + +The '``llvm.minimumnum.*``' intrinsics return the minimum of the two +arguments, not propagating NaNs and treating -0.0 as less than +0.0. + + +Arguments: +"" + +The arguments and return value are floating-point numbers of the same +type. + +Semantics: +"" +If both operands are NaNs (including sNaN), returns qNaN. If one operand +is NaN (including sNaN) and another operand is a number, return the number. +Otherwise returns the lesser of the two arguments. -0.0 is considered to +be less than +0.0 for this intrinsic. + +Note that these are the semantics of minimumNumber specified in IEEE 754-2019. wzssyqa wrote: No. minimumNumber returns NaN only when both are NaN. ``` minimumNumber(x, y) is x if x < y, y if y < x, and the number if one operand is a number and the other is a NaN. For this operation, −0 compares less than +0. If x = y and signs are the same it is either x or y. If both operands are NaNs, a quiet NaN is returned, according to 6.2. If either operand is a signaling NaN, an invalid operation exception is signaled, but unless both operands are NaNs, the signaling NaN is otherwise ignored and not converted to a quiet NaN as stated in 6.2 for other operations. ``` https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -15883,6 +15883,95 @@ The returned value is completely identical to the input except for the sign bit; in particular, if the input is a NaN, then the quiet/signaling bit and payload are perfectly preserved. +.. _i_fminmax_family: + +'``llvm.min.*``' Intrinsics Comparation +^^^ + +Standard: +" + +IEEE754 and ISO C define some min/max operations, and they have some differences +on working with qNaN/sNaN and +0.0/-0.0. Here is the list: + +.. list-table:: + :header-rows: 2 + + * - ``ISO C`` + - fmin/fmax + - none + - fmininum/fmaximum + - fminimum_num/fmaximum_num + + * - ``IEEE754`` + - none + - nimNUM/maxNUM (2008) + - minimum/maximum (2019) + - minimumNumber/maximumNumber (2019) + + * - ``+0.0 vs -0.0`` + - either one + - +0.0 > -0.0 wzssyqa wrote: Thanks. You are right. I was confused by the hardware implementations of some hardware. ARM/MIPSr6/PowerPC implement +0.0>-0.0. https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -15883,6 +15883,95 @@ The returned value is completely identical to the input except for the sign bit; in particular, if the input is a NaN, then the quiet/signaling bit and payload are perfectly preserved. +.. _i_fminmax_family: + +'``llvm.min.*``' Intrinsics Comparation +^^^ + +Standard: +" + +IEEE754 and ISO C define some min/max operations, and they have some differences +on working with qNaN/sNaN and +0.0/-0.0. Here is the list: + +.. list-table:: + :header-rows: 2 + + * - ``ISO C`` + - fmin/fmax + - none + - fmininum/fmaximum + - fminimum_num/fmaximum_num + + * - ``IEEE754`` + - none + - nimNUM/maxNUM (2008) + - minimum/maximum (2019) + - minimumNumber/maximumNumber (2019) + + * - ``+0.0 vs -0.0`` + - either one + - +0.0 > -0.0 + - +0.0 > -0.0 + - +0.0 > -0.0 + + * - ``NUM/qNaN vs sNaN`` + - qNaN, invalid exception + - qNaN, invalid exception + - qNaN, invalid exception + - NUM/qNaN, invalid exception + + * - ``NUM/qNaN vs qNaN`` + - NUM/qNaN, no excpetion wzssyqa wrote: And I split it to `NUM vs qNaN` and `qNaN vs qNaN`. https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -15883,6 +15883,95 @@ The returned value is completely identical to the input except for the sign bit; in particular, if the input is a NaN, then the quiet/signaling bit and payload are perfectly preserved. +.. _i_fminmax_family: + +'``llvm.min.*``' Intrinsics Comparation +^^^ + +Standard: +" + +IEEE754 and ISO C define some min/max operations, and they have some differences +on working with qNaN/sNaN and +0.0/-0.0. Here is the list: + +.. list-table:: + :header-rows: 2 + + * - ``ISO C`` + - fmin/fmax + - none + - fmininum/fmaximum + - fminimum_num/fmaximum_num + + * - ``IEEE754`` + - none + - nimNUM/maxNUM (2008) + - minimum/maximum (2019) + - minimumNumber/maximumNumber (2019) + + * - ``+0.0 vs -0.0`` + - either one + - +0.0 > -0.0 + - +0.0 > -0.0 + - +0.0 > -0.0 + + * - ``NUM/qNaN vs sNaN`` + - qNaN, invalid exception + - qNaN, invalid exception + - qNaN, invalid exception + - NUM/qNaN, invalid exception + + * - ``NUM/qNaN vs qNaN`` + - NUM/qNaN, no excpetion wzssyqa wrote: For more details about sNaN on constrained intrinsics, we may need to update them in future PRs. Since this PR is only about add `minimumnum and maximumnum`. https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -15868,6 +15868,51 @@ The returned value is completely identical to the input except for the sign bit; in particular, if the input is a NaN, then the quiet/signaling bit and payload are perfectly preserved. +.. _i_fminmax_family: + +'``llvm.min.*``' Intrinsics Comparation +^^^ + +.. list-table:: + :header-rows: 1 + :widths: 16 28 28 28 + + * - Operation + - minnum/maxnum + - minimum/maximum + - minimumnum/maximumnum + + * - ``NUM vs qNaN`` + - NUM, no exception + - qNaN, no exception + - qNaN, no exception + + * - ``NUM vs sNaN`` + - qNaN, invalid exception + - qNaN, invalid exception + - NUM, invalid exception + + * - ``qNaN vs sNaN`` + - qNaN, invalid exception + - qNaN, invalid exception + - qNaN, invalid exception + + * - ``sNaN vs sNaN`` + - qNaN, invalid exception + - qNaN, invalid exception + - qNaN, invalid exception + + * - ``+0.0 vs -0.0`` + - either one + - +0.0(max)/-0.0(min) + - +0.0(max)/-0.0(min) + + * - ``NUM vs NUM`` + - larger(max)/smaller(min) + - larger(max)/smaller(min) + - larger(max)/smaller(min) wzssyqa wrote: Sorry, I guess that I am not full understanding "LLVM's NaN-handling policy". As my understanding, for fmax*, we should fellow the libc's semantics. https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -15868,6 +15868,51 @@ The returned value is completely identical to the input except for the sign bit; in particular, if the input is a NaN, then the quiet/signaling bit and payload are perfectly preserved. +.. _i_fminmax_family: + +'``llvm.min.*``' Intrinsics Comparation +^^^ + +.. list-table:: + :header-rows: 1 + :widths: 16 28 28 28 + + * - Operation + - minnum/maxnum + - minimum/maximum + - minimumnum/maximumnum + + * - ``NUM vs qNaN`` + - NUM, no exception + - qNaN, no exception + - qNaN, no exception + + * - ``NUM vs sNaN`` + - qNaN, invalid exception + - qNaN, invalid exception + - NUM, invalid exception + + * - ``qNaN vs sNaN`` + - qNaN, invalid exception + - qNaN, invalid exception + - qNaN, invalid exception + + * - ``sNaN vs sNaN`` + - qNaN, invalid exception + - qNaN, invalid exception + - qNaN, invalid exception + + * - ``+0.0 vs -0.0`` + - either one + - +0.0(max)/-0.0(min) + - +0.0(max)/-0.0(min) + + * - ``NUM vs NUM`` + - larger(max)/smaller(min) + - larger(max)/smaller(min) + - larger(max)/smaller(min) wzssyqa wrote: For constrained ones, I guess that we should add more details in another PR(s). https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
https://github.com/wzssyqa closed https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Clang: Support minimumnum and maximumnum intrinsics (PR #96281)
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/96281
We just introduce llvm.minimumnum and llvm.maximumnum intrinsics support to
llvm. Let's support them in Clang.
See: #93033
>From 5605426ee61ec58cad701103a43922b67792ccaf Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Fri, 21 Jun 2024 14:28:42 +0800
Subject: [PATCH] Clang: Support minimumnum and maximumnum intrinsics
We just introduce llvm.minimumnum and llvm.maximumnum intrinsics
support to llvm. Let's support them in Clang.
See: #93033
---
clang/include/clang/Basic/Builtins.td | 28 +++
clang/lib/CodeGen/CGBuiltin.cpp | 24
.../Tooling/Inclusions/Stdlib/CSymbolMap.inc | 6
.../Inclusions/Stdlib/StdSymbolMap.inc| 18
clang/test/CodeGen/builtins.c | 18
clang/test/CodeGen/math-libcalls.c| 25 +
6 files changed, 119 insertions(+)
diff --git a/clang/include/clang/Basic/Builtins.td
b/clang/include/clang/Basic/Builtins.td
index 9342b6bc75fc8..d8093a7772b65 100644
--- a/clang/include/clang/Basic/Builtins.td
+++ b/clang/include/clang/Basic/Builtins.td
@@ -215,6 +215,18 @@ def FminF16F128 : Builtin, F16F128MathTemplate {
let Prototype = "T(T, T)";
}
+def FmaximumNumF16F128 : Builtin, F16F128MathTemplate {
+ let Spellings = ["__builtin_fmaximum_num"];
+ let Attributes = [FunctionWithBuiltinPrefix, NoThrow, Const, Constexpr];
+ let Prototype = "T(T, T)";
+}
+
+def FminimumNumF16F128 : Builtin, F16F128MathTemplate {
+ let Spellings = ["__builtin_fminimum_num"];
+ let Attributes = [FunctionWithBuiltinPrefix, NoThrow, Const, Constexpr];
+ let Prototype = "T(T, T)";
+}
+
def Atan2F128 : Builtin {
let Spellings = ["__builtin_atan2f128"];
let Attributes = [FunctionWithBuiltinPrefix, NoThrow,
ConstIgnoringErrnoAndExceptions];
@@ -3636,6 +3648,22 @@ def Fmin : FPMathTemplate, LibBuiltin<"math.h"> {
let OnlyBuiltinPrefixedAliasIsConstexpr = 1;
}
+def FmaximumNum : FPMathTemplate, LibBuiltin<"math.h"> {
+ let Spellings = ["fmaximum_num"];
+ let Attributes = [NoThrow, Const];
+ let Prototype = "T(T, T)";
+ let AddBuiltinPrefixedAlias = 1;
+ let OnlyBuiltinPrefixedAliasIsConstexpr = 1;
+}
+
+def FminimumNum : FPMathTemplate, LibBuiltin<"math.h"> {
+ let Spellings = ["fminimum_num"];
+ let Attributes = [NoThrow, Const];
+ let Prototype = "T(T, T)";
+ let AddBuiltinPrefixedAlias = 1;
+ let OnlyBuiltinPrefixedAliasIsConstexpr = 1;
+}
+
def Hypot : FPMathTemplate, LibBuiltin<"math.h"> {
let Spellings = ["hypot"];
let Attributes = [NoThrow, ConstIgnoringErrnoAndExceptions];
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2516ed4508242..a9f2245305ec2 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -2794,6 +2794,30 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
Intrinsic::minnum,
Intrinsic::experimental_constrained_minnum));
+case Builtin::BIfmaximum_num:
+case Builtin::BIfmaximum_numf:
+case Builtin::BIfmaximum_numl:
+case Builtin::BI__builtin_fmaximum_num:
+case Builtin::BI__builtin_fmaximum_numf:
+case Builtin::BI__builtin_fmaximum_numf16:
+case Builtin::BI__builtin_fmaximum_numl:
+case Builtin::BI__builtin_fmaximum_numf128:
+ return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(
+ *this, E, Intrinsic::maximumnum,
+ Intrinsic::experimental_constrained_maximumnum));
+
+case Builtin::BIfminimum_num:
+case Builtin::BIfminimum_numf:
+case Builtin::BIfminimum_numl:
+case Builtin::BI__builtin_fminimum_num:
+case Builtin::BI__builtin_fminimum_numf:
+case Builtin::BI__builtin_fminimum_numf16:
+case Builtin::BI__builtin_fminimum_numl:
+case Builtin::BI__builtin_fminimum_numf128:
+ return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(
+ *this, E, Intrinsic::minimumnum,
+ Intrinsic::experimental_constrained_minimumnum));
+
// fmod() is a special-case. It maps to the frem instruction rather than an
// LLVM intrinsic.
case Builtin::BIfmod:
diff --git a/clang/lib/Tooling/Inclusions/Stdlib/CSymbolMap.inc
b/clang/lib/Tooling/Inclusions/Stdlib/CSymbolMap.inc
index 463ce921f0672..af2dcb632fbb6 100644
--- a/clang/lib/Tooling/Inclusions/Stdlib/CSymbolMap.inc
+++ b/clang/lib/Tooling/Inclusions/Stdlib/CSymbolMap.inc
@@ -475,6 +475,12 @@ SYMBOL(fmaxl, None, )
SYMBOL(fmin, None, )
SYMBOL(fminf, None, )
SYMBOL(fminl, None, )
+SYMBOL(fmaximum_num, None, )
+SYMBOL(fmaximum_numf, None, )
+SYMBOL(fmaximum_numfl, None, )
+SYMBOL(fminimum_num, None, )
+SYMBOL(fminimum_numf, None, )
+SYMBOL(fminimum_numl, None, )
SYMBOL(fmod, None, )
SYMBOL(fmodf, None, )
SYMBOL(fmodl, None, )
diff --git a/clang/lib/Tooling/Inclusions/Stdlib/StdSymbolMap.inc
b/clang/lib/Tooling/Inclusio
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
wzssyqa wrote: @nikic thanks. Please also revert https://github.com/llvm/llvm-project/commit/225d8fc8eb24fb797154c1ef6dcbe5ba033142da https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
wzssyqa wrote: @nikic Thanks. I submit an RFC now https://discourse.llvm.org/t/rfc-fix-llvm-min-f-and-llvm-max-f-intrinsics/79735 https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Clang: Support minimumnum and maximumnum intrinsics (PR #96281)
@@ -3636,6 +3648,22 @@ def Fmin : FPMathTemplate, LibBuiltin<"math.h"> {
let OnlyBuiltinPrefixedAliasIsConstexpr = 1;
}
+def FmaximumNum : FPMathTemplate, LibBuiltin<"math.h"> {
wzssyqa wrote:
Oh, newer libc does have this function:
https://www.gnu.org/software/libc/manual/html_node/Misc-FP-Arithmetic.html
https://github.com/llvm/llvm-project/pull/96281
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[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
wzssyqa wrote: Since we need to reuse some logic of `minnum/maxnum` to implement `minimumnum/maximumnum`, let's add them before switch the behavior of `minnum/maxnum`. Known not working ports, will be fixed in future PRs: 1. X86: the current `minnum/maxnum` cannot process +0 vs -0 as `minimumnum/maximumnum` expected. 2. ARM(32): has some interaction with the behavior of `minnum/maxnum`. 3. PowerPC: has some interaction with the behavior of `minnum/maxnum`: need define `fcanonicalize`. https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
wzssyqa wrote: @peterwaller-arm I noticed that in `llvm/test/CodeGen/AArch64/combine_andor_with_cmps.ll`, `FMAXNUM_IEEE` is claimed that it is not supported. While I noticed that `fmaxnm` follows the rules of `maxNUM` of IEEE754-2008. Is there any other limitation of `fmaxnm`? https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
wzssyqa wrote: TODO: implement for architectures that don't have `fmin/fmax` instructions: This is the example of MIPS pre-R6: ``` mins: .setnoreorder .setnomacro mtc1$0,$f1 add.s $f0,$f12,$f1 add.s $f13,$f13,$f1 c.un.s $fcc0,$f0,$f0 movt.s $f0,$f13,$fcc0 c.un.s $fcc0,$f13,$f13 movt.s $f13,$f0,$fcc0 c.ult.s $fcc0,$f13,$f0 movt.s $f0,$f13,$fcc0 jr $31 ``` https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -16049,6 +16094,84 @@ of the two arguments. -0.0 is considered to be less than +0.0 for this intrinsic. Note that these are the semantics specified in the draft of IEEE 754-2019. +.. _i_minimumnum: + +'``llvm.minimumnum.*``' Intrinsic +^ + +Syntax: +""" + +This is an overloaded intrinsic. You can use ``llvm.minimumnum`` on any +floating-point or vector of floating-point type. Not all targets support +all types however. + +:: + + declare float @llvm.minimumnum.f32(float %Val0, float %Val1) + declare double@llvm.minimumnum.f64(double %Val0, double %Val1) + declare x86_fp80 @llvm.minimumnum.f80(x86_fp80 %Val0, x86_fp80 %Val1) + declare fp128 @llvm.minimumnum.f128(fp128 %Val0, fp128 %Val1) + declare ppc_fp128 @llvm.minimumnum.ppcf128(ppc_fp128 %Val0, ppc_fp128 %Val1) + +Overview: +" + +The '``llvm.minimumnum.*``' intrinsics return the minimum of the two +arguments, not propagating NaNs and treating -0.0 as less than +0.0. + + +Arguments: +"" + +The arguments and return value are floating-point numbers of the same +type. + +Semantics: +"" +If both operands are NaNs, returns qNaN. Otherwise returns the lesser +of the two arguments. -0.0 is considered to be less than +0.0 for this +intrinsic. Note that these are the semantics specified in IEEE 754-2019. wzssyqa wrote: > Needs to spell out the signaling nan behavior. If we're fixing minnum's snan > behavior to match IEEE, this is identical except with the stronger guarantee > for signed zero ordering. The documentation should also explicitly state this > is the only difference, to help reduce confusion. Alternatively, we could add > an immediate bool parameter to minnum/maxnum for whether the ordering of 0 is > guaranteed > OK. I will add more details here. > I hate the naming mess we've ended up with here, but I guess C23 has damned > us. If you're going to match the C23 names, this should be `llvm.minimum.num` > with an extra _ In fact, in my initial version of patch, I use _, then I get `llvm.minimum.num`. I considered it as a problem, since it cost some time to know in fact I should use `llvm.minimum.num` instead of `llvm.minimum_num` :( https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
wzssyqa wrote: > > 3. PowerPC: has some interaction with the behavior of `minnum/maxnum`: need > > define `fcanonicalize`. > > AMDGPU has the same handling. This is to break the signaling nan handling > from IEEE to the broken old glibc libm behavior. If we fix the definition to > match IEEE, this is no longer necessary and the operation is directly legal Added to TODO list. https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -631,6 +631,46 @@ TEST(APFloatTest, Maximum) {
EXPECT_TRUE(std::isnan(maximum(nan, f1).convertToDouble()));
}
+TEST(APFloatTest, MinimumNumber) {
+ APFloat f1(1.0);
+ APFloat f2(2.0);
+ APFloat zp(0.0);
+ APFloat zn(-0.0);
+ APFloat nan = APFloat::getNaN(APFloat::IEEEdouble());
+ APFloat snan = APFloat::getSNaN(APFloat::IEEEdouble());
+
+ EXPECT_EQ(1.0, minimumnum(f1, f2).convertToDouble());
+ EXPECT_EQ(1.0, minimumnum(f2, f1).convertToDouble());
+ EXPECT_EQ(-0.0, minimumnum(zp, zn).convertToDouble());
+ EXPECT_EQ(-0.0, minimumnum(zn, zp).convertToDouble());
wzssyqa wrote:
Let's add some new isNegtive tests.
https://github.com/llvm/llvm-project/pull/93841
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[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/93841 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -9130,6 +9142,15 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
if (visitBinaryFloatCall(I, ISD::FMAXNUM))
return;
break;
+ case LibFunc_fminimum_num:
+ case LibFunc_fminimum_numf:
+if (visitBinaryFloatCall(I, ISD::FMINIMUMNUM))
+ return;
+break;
+ case LibFunc_fmaximum_num:
wzssyqa wrote:
LibFunc_fminimum_numl
LibFunc_fmaximum_numf
LibFunc_fmaximum_numl
Add. Should we add something like `fmaximum_numfN` and `fmaximum_numfNx `?
https://github.com/llvm/llvm-project/pull/93841
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[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -9130,6 +9142,15 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
if (visitBinaryFloatCall(I, ISD::FMAXNUM))
return;
break;
+ case LibFunc_fminimum_num:
+ case LibFunc_fminimum_numf:
+if (visitBinaryFloatCall(I, ISD::FMINIMUMNUM))
+ return;
+break;
+ case LibFunc_fmaximum_num:
wzssyqa wrote:
If need, I think that we need to a new patch, since neither other libcalls
have them.
https://github.com/llvm/llvm-project/pull/93841
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[clang] [llvm] Intrinsic: introduce minimumnum and maximumnum (PR #93841)
@@ -32,27 +32,29 @@ class StoreInst;
/// These are the kinds of recurrences that we support.
enum class RecurKind {
- None, ///< Not a recurrence.
- Add, ///< Sum of integers.
- Mul, ///< Product of integers.
- Or, ///< Bitwise or logical OR of integers.
- And, ///< Bitwise or logical AND of integers.
- Xor, ///< Bitwise or logical XOR of integers.
- SMin, ///< Signed integer min implemented in terms of select(cmp()).
- SMax, ///< Signed integer max implemented in terms of select(cmp()).
- UMin, ///< Unsigned integer min implemented in terms of select(cmp()).
- UMax, ///< Unsigned integer max implemented in terms of select(cmp()).
- FAdd, ///< Sum of floats.
- FMul, ///< Product of floats.
- FMin, ///< FP min implemented in terms of select(cmp()).
- FMax, ///< FP max implemented in terms of select(cmp()).
- FMinimum, ///< FP min with llvm.minimum semantics
- FMaximum, ///< FP max with llvm.maximum semantics
- FMulAdd, ///< Sum of float products with llvm.fmuladd(a * b + sum).
- IAnyOf, ///< Any_of reduction with select(icmp(),x,y) where one of (x,y) is
-///< loop invariant, and both x and y are integer type.
- FAnyOf///< Any_of reduction with select(fcmp(),x,y) where one of (x,y) is
-///< loop invariant, and both x and y are integer type.
+ None,///< Not a recurrence.
+ Add, ///< Sum of integers.
+ Mul, ///< Product of integers.
+ Or, ///< Bitwise or logical OR of integers.
+ And, ///< Bitwise or logical AND of integers.
+ Xor, ///< Bitwise or logical XOR of integers.
+ SMin,///< Signed integer min implemented in terms of select(cmp()).
+ SMax,///< Signed integer max implemented in terms of select(cmp()).
+ UMin,///< Unsigned integer min implemented in terms of select(cmp()).
+ UMax,///< Unsigned integer max implemented in terms of select(cmp()).
+ FAdd,///< Sum of floats.
+ FMul,///< Product of floats.
+ FMin,///< FP min implemented in terms of select(cmp()).
+ FMax,///< FP max implemented in terms of select(cmp()).
+ FMinimum,///< FP min with llvm.minimum semantics
+ FMaximum,///< FP max with llvm.maximum semantics
+ FMinimumnum, ///< FP min with llvm.minimumnum semantics
+ FMaximumnum, ///< FP max with llvm.maximumnum semantics
wzssyqa wrote:
Removed from this PR, and add them into TODOs.
https://github.com/llvm/llvm-project/pull/93841
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[clang] [flang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #88661)
wzssyqa wrote: 9f43a41db37253685c5ed428c215528eb92bbd43 1693009679313282afbed38778dd3fad62641e1b Landed as the above commits. https://github.com/llvm/llvm-project/pull/88661 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #88661)
https://github.com/wzssyqa closed https://github.com/llvm/llvm-project/pull/88661 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin (PR #87866)
wzssyqa wrote: See: https://github.com/llvm/llvm-project/pull/87866 Can you have a try to add an extra option ``` -resource-dir=%S/Inputs/resource_dir ``` https://github.com/llvm/llvm-project/pull/87866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
wzssyqa wrote: Does it really needed? https://github.com/llvm/llvm-project/pull/89425 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/89425 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
https://github.com/wzssyqa requested changes to this pull request. https://github.com/llvm/llvm-project/pull/89425 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
@@ -142,7 +142,7 @@ if(WIN32 OR LLVM_WINSYSROOT)
set(RUNTIMES_${target}_CMAKE_MODULE_LINKER_FLAGS ${WINDOWS_LINK_FLAGS} CACHE
STRING "")
endif()
-foreach(target
aarch64-unknown-linux-gnu;armv7-unknown-linux-gnueabihf;i386-unknown-linux-gnu;riscv64-unknown-linux-gnu;x86_64-unknown-linux-gnu)
+foreach(target
aarch64-linux-gnu;armv7-linux-gnueabihf;i386-linux-gnu;riscv64-linux-gnu;x86_64-linux-gnu)
wzssyqa wrote:
It seems offtopic of commit msg?
Since the normalize format of `aarch64-linux-gnu` is just
aarch64-unknown-linux-gnu, why do we need to modify them?
https://github.com/llvm/llvm-project/pull/89425
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[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
@@ -181,6 +181,20 @@ message(STATUS "LLVM default target triple:
${LLVM_DEFAULT_TARGET_TRIPLE}")
set(LLVM_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}")
+if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE)
+ set(print_target_triple ${CMAKE_CXX_COMPILER}
--target=${LLVM_RUNTIME_TRIPLE} -print-target-triple)
+ execute_process(COMMAND ${print_target_triple}
+RESULT_VARIABLE result
+OUTPUT_VARIABLE output
+OUTPUT_STRIP_TRAILING_WHITESPACE)
+ if(result EQUAL 0)
+set(LLVM_RUNTIME_TRIPLE ${output})
wzssyqa wrote:
`LLVM_RUNTIME_TRIPLE` seem to be not used? I cannot find this symbol by `grep`.
https://github.com/llvm/llvm-project/pull/89425
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[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
@@ -28,6 +28,19 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) if (NOT LLVM_RUNTIMES_BUILD) load_llvm_config() endif() + if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE) wzssyqa wrote: With my patch, `libclang_rt.builtin` has been installed to per_target runtime dir. I don't think that this one is needed. And `if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR` is not needed here: it is just set the triple. If `LLVM_ENABLE_PER_TARGET_RUNTIME_DIR=off`, the libraries will still install to non-per-target dir. And `if(NOT APPLE)` is not needed either. ``` $ ./bin/clang --target=air64-apple-ios16.0 -print-target-triple air64-apple-ios16.0 $ ./bin/clang --target=arm64-apple-darwin23.4.0 -print-target-triple arm64-apple-darwin23.4.0 ``` https://github.com/llvm/llvm-project/pull/89425 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
@@ -28,6 +28,19 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR)
if (NOT LLVM_RUNTIMES_BUILD)
load_llvm_config()
endif()
+ if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE)
+set(print_target_triple ${CMAKE_CXX_COMPILER}
--target=${LLVM_RUNTIME_TRIPLE} -print-target-triple)
wzssyqa wrote:
I am wondering that whether `CMAKE_CXX_COMPILER` is defined for
`compiler-rt/lib/builtins`.
All source of this library is pure C/ASM.
In fact when I worked on my PR, I did meet this problem.
My configure cmd is
```
cmake ../llvm -G Ninja -DLLVM_ENABLE_PER_TARGET_RUNTIME_DIR=off
-DLLVM_DEFAULT_TARGET_TRIPLE=aarch64-linux-gnu -DLLVM_USE_LINKER=lld
-DLLVM_ENABLE_RUNTIMES="compiler-rt;libunwind"
-DLLVM_ENABLE_PROJECTS="mlir;clang;clang-tools-extra;lld"
-DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++
-DCMAKE_BUILD_TYPE=RelWithDebInfo
```
https://github.com/llvm/llvm-project/pull/89425
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[clang] [compiler-rt] [llvm] [CMake] Use Clang to infer the target triple (PR #89425)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/89425 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Improve error when a compiler-rt library is not found (PR #81037)
@@ -656,19 +656,29 @@ std::string ToolChain::getCompilerRT(const ArgList &Args,
StringRef Component,
// Check for runtime files in the new layout without the architecture first.
std::string CRTBasename =
buildCompilerRTBasename(Args, Component, Type, /*AddArch=*/false);
+ SmallString<128> Path;
for (const auto &LibPath : getLibraryPaths()) {
SmallString<128> P(LibPath);
llvm::sys::path::append(P, CRTBasename);
if (getVFS().exists(P))
return std::string(P);
+if (Path.empty())
+ Path = P;
}
+ if (getTriple().isOSAIX())
+Path.clear();
- // Fall back to the old expected compiler-rt name if the new one does not
- // exist.
+ // Check the filename for the old layout if the new one does not exist.
CRTBasename =
buildCompilerRTBasename(Args, Component, Type, /*AddArch=*/true);
- SmallString<128> Path(getCompilerRTPath());
- llvm::sys::path::append(Path, CRTBasename);
+ SmallString<128> OldPath(getCompilerRTPath());
+ llvm::sys::path::append(OldPath, CRTBasename);
+ if (Path.empty() || getVFS().exists(OldPath))
+return std::string(OldPath);
+
+ // If none is found, use a file name from the new layout, which may get
+ // printed in an error message, aiding users in knowing what Clang is
+ // looking for.
wzssyqa wrote:
It is only about warning msg.
Clang will try to find libraries for both new and old style paths.
If you'd like to put the libraries in old style path/filename, you can use
`-DLLVM_ENABLE_PER_TARGET_RUNTIME_DIR=OFF`.
Of course, even with the above configure option, if clang cannot find a
library, it will warn with new style path.
https://github.com/llvm/llvm-project/pull/81037
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[clang] [libcxx] [llvm] Triple::normalize: Set OS for 3-component triple with none as middle (PR #89638)
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/89638
>From a40bf92dcdaa64c2ca73d9276972c8cd47750210 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Apr 2024 01:36:17 +0800
Subject: [PATCH] Triple::normalize: Set OS for 3-component triple with none as
middle
If the middle component of a 3-component triple fails to parse as known
Arch/Vendor/OS/Env, it will fallback as Vendor. While for some cases,
we may wish to recognize it as OS, such as `arm64-none-elf`.
In this patch, we will set OS as `none`, if:
1) Arch is found;
2) Env is found;
3) OS is not found and thus is set as empty;
4) Vendor is not found while is set as "none",
we will swap Component[2] and Component[3].
Use this new triple for these tests:
- libcxx/utils/ci/run-buildbot
- clang/test/Driver/print-multi-selection-flags.c
- llvm/unittests/TargetParser/TripleTest.cpp
Fixes: #89582.
---
clang/test/Driver/print-multi-selection-flags.c | 14 +++---
libcxx/utils/ci/run-buildbot| 2 +-
llvm/lib/TargetParser/Triple.cpp| 7 +++
llvm/unittests/TargetParser/TripleTest.cpp | 2 +-
4 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/clang/test/Driver/print-multi-selection-flags.c
b/clang/test/Driver/print-multi-selection-flags.c
index 06a12db9d97792..9f58d1b557fd74 100644
--- a/clang/test/Driver/print-multi-selection-flags.c
+++ b/clang/test/Driver/print-multi-selection-flags.c
@@ -5,27 +5,27 @@
// CHECK-FUCHSIA: --target=aarch64-unknown-fuchsia
// RUN: %clang -print-multi-flags-experimental --target=arm-none-eabi
-mfloat-abi=soft -fno-exceptions -fno-rtti | FileCheck
--check-prefix=CHECK-ARMV4T %s
-// CHECK-ARMV4T: --target=armv4t-none-unknown-eabi
+// CHECK-ARMV4T: --target=armv4t-unknown-none-eabi
// CHECK-ARMV4T: -mfloat-abi=soft
// CHECK-ARMV4T: -mfpu=none
// RUN: %clang -print-multi-flags-experimental --target=armv7em-none-eabi
-mfloat-abi=softfp | FileCheck --check-prefix=CHECK-SOFTFP %s
-// CHECK-SOFTFP: --target=thumbv7em-none-unknown-eabi
+// CHECK-SOFTFP: --target=thumbv7em-unknown-none-eabi
// CHECK-SOFTFP: -mfloat-abi=softfp
// CHECK-SOFTFP: -mfpu=fpv4-sp-d16
// RUN: %clang -print-multi-flags-experimental --target=arm-none-eabihf
-march=armv7em -mfpu=fpv5-d16 | FileCheck --check-prefix=CHECK-HARD %s
-// CHECK-HARD: --target=thumbv7em-none-unknown-eabihf
+// CHECK-HARD: --target=thumbv7em-unknown-none-eabihf
// CHECK-HARD: -mfloat-abi=hard
// CHECK-HARD: -mfpu=fpv5-d16
// RUN: %clang -print-multi-flags-experimental --target=arm-none-eabi
-mfloat-abi=soft -march=armv8-m.main+nofp | FileCheck
--check-prefix=CHECK-V8MMAIN-NOFP %s
-// CHECK-V8MMAIN-NOFP: --target=thumbv8m.main-none-unknown-eabi
+// CHECK-V8MMAIN-NOFP: --target=thumbv8m.main-unknown-none-eabi
// CHECK-V8MMAIN-NOFP: -mfloat-abi=soft
// CHECK-V8MMAIN-NOFP: -mfpu=none
// RUN: %clang -print-multi-flags-experimental --target=arm-none-eabi
-mfloat-abi=hard -march=armv8.1m.main+mve.fp | FileCheck
--check-prefix=CHECK-MVE %s
-// CHECK-MVE: --target=thumbv8.1m.main-none-unknown-eabihf
+// CHECK-MVE: --target=thumbv8.1m.main-unknown-none-eabihf
// CHECK-MVE: -march=thumbv8.1m.main{{.*}}+mve{{.*}}+mve.fp{{.*}}
// CHECK-MVE: -mfloat-abi=hard
// CHECK-MVE: -mfpu=fp-armv8-fullfp16-sp-d16
@@ -51,10 +51,10 @@
// CHECK-M85_NO_FP_DP: -mfpu=fp-armv8-fullfp16-sp-d16
// RUN: %clang -print-multi-flags-experimental --target=aarch64-none-elf
-march=armv8-a+lse | FileCheck --check-prefix=CHECK-LSE %s
-// CHECK-LSE: --target=aarch64-none-unknown-elf
+// CHECK-LSE: --target=aarch64-unknown-none-elf
// CHECK-LSE: -march=armv8-a{{.*}}+lse{{.*}}
// RUN: %clang -print-multi-flags-experimental --target=aarch64-none-elf
-march=armv8.5-a+sve+sve2 | FileCheck --check-prefix=CHECK-SVE2 %s
// RUN: %clang -print-multi-flags-experimental --target=aarch64-none-elf
-march=armv9-a| FileCheck --check-prefix=CHECK-SVE2 %s
-// CHECK-SVE2: --target=aarch64-none-unknown-elf
+// CHECK-SVE2: --target=aarch64-unknown-none-elf
// CHECK-SVE2: -march=armv{{.*}}-a{{.*}}+simd{{.*}}+sve{{.*}}+sve2{{.*}}
diff --git a/libcxx/utils/ci/run-buildbot b/libcxx/utils/ci/run-buildbot
index 60307a7d4f350a..3523a29e4f4613 100755
--- a/libcxx/utils/ci/run-buildbot
+++ b/libcxx/utils/ci/run-buildbot
@@ -217,7 +217,7 @@ function test-armv7m-picolibc() {
"${@}"
${NINJA} -vC "${BUILD_DIR}/compiler-rt" install
-mv "${BUILD_DIR}/install/lib/armv7m-none-unknown-eabi"/*
"${BUILD_DIR}/install/lib"
+mv "${BUILD_DIR}/install/lib/armv7m-unknown-none-eabi"/*
"${BUILD_DIR}/install/lib"
check-runtimes
}
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index 77fdf31d4865c0..07f3df4145dad4 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -1149,6 +1149,13 @@ std::string Triple::normalize(StringRef Str) {
}
}
+ // For 3-component triples, the
[clang] [libcxx] [llvm] Triple::normalize: Set OS for 3-component triple with none as middle (PR #89638)
https://github.com/wzssyqa edited https://github.com/llvm/llvm-project/pull/89638 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
