[clang] [Clang][RISCV] Introduce tuple types for RVV bfloat16 (PR #72216)
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/72216
The first commit extends the capacity from the compiler infrastructure, and the
second commit continues the effort in #71140 to introduce tuple types for
bfloat16.
>From e34bbbf5ebd1444aab843f3919faf68ae8d1cda9 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Mon, 13 Nov 2023 23:03:00 -0800
Subject: [PATCH 1/2] [Clang] Extend cap of NUM_PREDEF_TYPE_IDS from 500 to 600
Introducing the RVV tuple types for bfloat16 will exceed the cap and hit
the static assert. This commit extends it.
---
clang/include/clang/Serialization/ASTBitCodes.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h
b/clang/include/clang/Serialization/ASTBitCodes.h
index 5c32fbc079c9a65..9044c46fc671963 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDEF_TYPE_IDS = 600;
// Ensure we do not overrun the predefined types we reserved
// in the enum PredefinedTypeIDs above.
>From 68e29d46cee5258d74f3d24b318ba50132f5e00f Mon Sep 17 00:00:00 2001
From: eopXD
Date: Mon, 13 Nov 2023 23:12:41 -0800
Subject: [PATCH 2/2] [Clang][RISCV] Add tuple types for RVV bfloat16 types
---
clang/include/clang/Basic/RISCVVTypes.def | 56 +++
.../clang/Support/RISCVVIntrinsicUtils.h | 5 +-
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 3 +
.../rvv-intrinsic-datatypes.cpp | 55 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 +-
5 files changed, 120 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index af44cdcd53e5bd0..6620de8ad50e01e 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -452,6 +452,62 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x4_t",
RvvFloat64m2x4, RvvFloat64m2x4Ty, 2
RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4x2_t", RvvFloat64m4x2, RvvFloat64m4x2Ty,
4, 64, 2)
+//===- BFloat16 tuple types
-===//
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x2_t", RvvBFloat16mf4x2,
RvvBFloat16mf4x2Ty,
+ 1, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x3_t", RvvBFloat16mf4x3,
RvvBFloat16mf4x3Ty,
+ 1, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x4_t", RvvBFloat16mf4x4,
RvvBFloat16mf4x4Ty,
+ 1, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x5_t", RvvBFloat16mf4x5,
RvvBFloat16mf4x5Ty,
+ 1, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x6_t", RvvBFloat16mf4x6,
RvvBFloat16mf4x6Ty,
+ 1, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x7_t", RvvBFloat16mf4x7,
RvvBFloat16mf4x7Ty,
+ 1, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x8_t", RvvBFloat16mf4x8,
RvvBFloat16mf4x8Ty,
+ 1, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x2_t", RvvBFloat16mf2x2,
RvvBFloat16mf2x2Ty,
+ 2, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x3_t", RvvBFloat16mf2x3,
RvvBFloat16mf2x3Ty,
+ 2, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x4_t", RvvBFloat16mf2x4,
RvvBFloat16mf2x4Ty,
+ 2, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x5_t", RvvBFloat16mf2x5,
RvvBFloat16mf2x5Ty,
+ 2, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x6_t", RvvBFloat16mf2x6,
RvvBFloat16mf2x6Ty,
+ 2, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x7_t", RvvBFloat16mf2x7,
RvvBFloat16mf2x7Ty,
+ 2, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x8_t", RvvBFloat16mf2x8,
RvvBFloat16mf2x8Ty,
+ 2, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x2_t", RvvBFloat16m1x2,
RvvBFloat16m1x2Ty,
+ 4, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x3_t", RvvBFloat16m1x3,
RvvBFloat16m1x3Ty,
+ 4, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x4_t", RvvBFloat16m1x4,
RvvBFloat16m1x4Ty,
+ 4, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x5_t", RvvBFloat16m1x5,
RvvBFloat16m1x5Ty,
+ 4, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x6_t", RvvBFloat16m1x6,
RvvBFloat16m1x6Ty,
+ 4, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x7_t", RvvBFloat16m1x7,
RvvBFloat16m1x7Ty,
+ 4, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x8_t", RvvBFloat16m1x8,
RvvBFloat16m1x8Ty,
+ 4, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x2_t", RvvBFloat16m2x2,
RvvBFloat16m2x2Ty,
+
[clang] [llvm] [RISCV] Remove experimental from Vector Crypto extensions (PR #74213)
eopXD wrote: The intrinsics for vector crypto is not a formalized version yet. To be safe, I think we should have an experimental tag to guard the intrinsics, while the extension is ratified and do indeed don't need the experimental. https://github.com/llvm/llvm-project/pull/74213 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Introduce tuple types for RVV bfloat16 (PR #72216)
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/72216 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Revert "[Clang][RISCV] Introduce tuple types for RVV bfloat16 (#72216)" (PR #72367)
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/72367
This reverts commit 8434b0b9d39b7ffcd1f7f7b5746151e293620e0d. #72216
This commit broke the multiple buildbots, looks like the extension in
`NUM_PREDEF_TYPE_IDS` might have broken some inheriting usages, causing
indeterminate results for the compiler. Investigating the issue now.
>From 778651c915af68710d3a7d39cdfa010f1bc8edf8 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Wed, 15 Nov 2023 01:57:51 -0800
Subject: [PATCH] Revert "[Clang][RISCV] Introduce tuple types for RVV bfloat16
(#72216)"
This reverts commit 8434b0b9d39b7ffcd1f7f7b5746151e293620e0d.
---
clang/include/clang/Basic/RISCVVTypes.def | 56 ---
.../include/clang/Serialization/ASTBitCodes.h | 2 +-
.../clang/Support/RISCVVIntrinsicUtils.h | 5 +-
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 3 -
.../rvv-intrinsic-datatypes.cpp | 55 --
clang/utils/TableGen/RISCVVEmitter.cpp| 4 +-
6 files changed, 4 insertions(+), 121 deletions(-)
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index 6620de8ad50e01e..af44cdcd53e5bd0 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -452,62 +452,6 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x4_t",
RvvFloat64m2x4, RvvFloat64m2x4Ty, 2
RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4x2_t", RvvFloat64m4x2, RvvFloat64m4x2Ty,
4, 64, 2)
-//===- BFloat16 tuple types
-===//
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x2_t", RvvBFloat16mf4x2,
RvvBFloat16mf4x2Ty,
- 1, 16, 2)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x3_t", RvvBFloat16mf4x3,
RvvBFloat16mf4x3Ty,
- 1, 16, 3)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x4_t", RvvBFloat16mf4x4,
RvvBFloat16mf4x4Ty,
- 1, 16, 4)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x5_t", RvvBFloat16mf4x5,
RvvBFloat16mf4x5Ty,
- 1, 16, 5)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x6_t", RvvBFloat16mf4x6,
RvvBFloat16mf4x6Ty,
- 1, 16, 6)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x7_t", RvvBFloat16mf4x7,
RvvBFloat16mf4x7Ty,
- 1, 16, 7)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x8_t", RvvBFloat16mf4x8,
RvvBFloat16mf4x8Ty,
- 1, 16, 8)
-
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x2_t", RvvBFloat16mf2x2,
RvvBFloat16mf2x2Ty,
- 2, 16, 2)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x3_t", RvvBFloat16mf2x3,
RvvBFloat16mf2x3Ty,
- 2, 16, 3)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x4_t", RvvBFloat16mf2x4,
RvvBFloat16mf2x4Ty,
- 2, 16, 4)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x5_t", RvvBFloat16mf2x5,
RvvBFloat16mf2x5Ty,
- 2, 16, 5)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x6_t", RvvBFloat16mf2x6,
RvvBFloat16mf2x6Ty,
- 2, 16, 6)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x7_t", RvvBFloat16mf2x7,
RvvBFloat16mf2x7Ty,
- 2, 16, 7)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x8_t", RvvBFloat16mf2x8,
RvvBFloat16mf2x8Ty,
- 2, 16, 8)
-
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x2_t", RvvBFloat16m1x2,
RvvBFloat16m1x2Ty,
- 4, 16, 2)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x3_t", RvvBFloat16m1x3,
RvvBFloat16m1x3Ty,
- 4, 16, 3)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x4_t", RvvBFloat16m1x4,
RvvBFloat16m1x4Ty,
- 4, 16, 4)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x5_t", RvvBFloat16m1x5,
RvvBFloat16m1x5Ty,
- 4, 16, 5)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x6_t", RvvBFloat16m1x6,
RvvBFloat16m1x6Ty,
- 4, 16, 6)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x7_t", RvvBFloat16m1x7,
RvvBFloat16m1x7Ty,
- 4, 16, 7)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x8_t", RvvBFloat16m1x8,
RvvBFloat16m1x8Ty,
- 4, 16, 8)
-
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x2_t", RvvBFloat16m2x2,
RvvBFloat16m2x2Ty,
- 8, 16, 2)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x3_t", RvvBFloat16m2x3,
RvvBFloat16m2x3Ty,
- 8, 16, 3)
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x4_t", RvvBFloat16m2x4,
RvvBFloat16m2x4Ty,
- 8, 16, 4)
-
-RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m4x2_t", RvvBFloat16m4x2,
RvvBFloat16m4x2Ty,
- 16, 16, 2)
-
#undef RVV_VECTOR_TYPE_BFLOAT
#undef RVV_VECTOR_TYPE_FLOAT
#undef RVV_VECTOR_TYPE_INT
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h
b/clang/include/clang/Serialization/ASTBitCodes.h
index 9044c46fc671963..5c32fbc079c9a65 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1101,7 +1101,7 @@ enum P
[clang] Revert "[Clang][RISCV] Introduce tuple types for RVV bfloat16 (#72216)" (PR #72367)
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/72367 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/72370
This PR attempts to recommit the PR (#72216) with a safe-bounded TypeID that
will not cause indeterminate results for the compiler.
>From 78e3ab20f5e527563b7645635b7147fdda8ba4b9 Mon Sep 17 00:00:00 2001
From: "Yueh-Ting (eop) Chen"
Date: Wed, 15 Nov 2023 13:50:14 +0800
Subject: [PATCH 1/2] [Clang][RISCV] Introduce tuple types for RVV bfloat16
(#72216)
The first commit extends the capacity from the compiler infrastructure,
and the second commit continues the effort in #71140 to introduce tuple
types for bfloat16.
---
clang/include/clang/Basic/RISCVVTypes.def | 56 +++
.../include/clang/Serialization/ASTBitCodes.h | 2 +-
.../clang/Support/RISCVVIntrinsicUtils.h | 5 +-
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 3 +
.../rvv-intrinsic-datatypes.cpp | 55 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 +-
6 files changed, 121 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index af44cdcd53e5bd0..6620de8ad50e01e 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -452,6 +452,62 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x4_t",
RvvFloat64m2x4, RvvFloat64m2x4Ty, 2
RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4x2_t", RvvFloat64m4x2, RvvFloat64m4x2Ty,
4, 64, 2)
+//===- BFloat16 tuple types
-===//
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x2_t", RvvBFloat16mf4x2,
RvvBFloat16mf4x2Ty,
+ 1, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x3_t", RvvBFloat16mf4x3,
RvvBFloat16mf4x3Ty,
+ 1, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x4_t", RvvBFloat16mf4x4,
RvvBFloat16mf4x4Ty,
+ 1, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x5_t", RvvBFloat16mf4x5,
RvvBFloat16mf4x5Ty,
+ 1, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x6_t", RvvBFloat16mf4x6,
RvvBFloat16mf4x6Ty,
+ 1, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x7_t", RvvBFloat16mf4x7,
RvvBFloat16mf4x7Ty,
+ 1, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x8_t", RvvBFloat16mf4x8,
RvvBFloat16mf4x8Ty,
+ 1, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x2_t", RvvBFloat16mf2x2,
RvvBFloat16mf2x2Ty,
+ 2, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x3_t", RvvBFloat16mf2x3,
RvvBFloat16mf2x3Ty,
+ 2, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x4_t", RvvBFloat16mf2x4,
RvvBFloat16mf2x4Ty,
+ 2, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x5_t", RvvBFloat16mf2x5,
RvvBFloat16mf2x5Ty,
+ 2, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x6_t", RvvBFloat16mf2x6,
RvvBFloat16mf2x6Ty,
+ 2, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x7_t", RvvBFloat16mf2x7,
RvvBFloat16mf2x7Ty,
+ 2, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x8_t", RvvBFloat16mf2x8,
RvvBFloat16mf2x8Ty,
+ 2, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x2_t", RvvBFloat16m1x2,
RvvBFloat16m1x2Ty,
+ 4, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x3_t", RvvBFloat16m1x3,
RvvBFloat16m1x3Ty,
+ 4, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x4_t", RvvBFloat16m1x4,
RvvBFloat16m1x4Ty,
+ 4, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x5_t", RvvBFloat16m1x5,
RvvBFloat16m1x5Ty,
+ 4, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x6_t", RvvBFloat16m1x6,
RvvBFloat16m1x6Ty,
+ 4, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x7_t", RvvBFloat16m1x7,
RvvBFloat16m1x7Ty,
+ 4, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x8_t", RvvBFloat16m1x8,
RvvBFloat16m1x8Ty,
+ 4, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x2_t", RvvBFloat16m2x2,
RvvBFloat16m2x2Ty,
+ 8, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x3_t", RvvBFloat16m2x3,
RvvBFloat16m2x3Ty,
+ 8, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x4_t", RvvBFloat16m2x4,
RvvBFloat16m2x4Ty,
+ 8, 16, 4)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m4x2_t", RvvBFloat16m4x2,
RvvBFloat16m4x2Ty,
+ 16, 16, 2)
+
#undef RVV_VECTOR_TYPE_BFLOAT
#undef RVV_VECTOR_TYPE_FLOAT
#undef RVV_VECTOR_TYPE_INT
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h
b/clang/include/clang/Serialization/ASTBitCodes.h
index 5c32fbc079c9a65..9044c46fc671963 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72370
>From 78e3ab20f5e527563b7645635b7147fdda8ba4b9 Mon Sep 17 00:00:00 2001
From: "Yueh-Ting (eop) Chen"
Date: Wed, 15 Nov 2023 13:50:14 +0800
Subject: [PATCH 1/3] [Clang][RISCV] Introduce tuple types for RVV bfloat16
(#72216)
The first commit extends the capacity from the compiler infrastructure,
and the second commit continues the effort in #71140 to introduce tuple
types for bfloat16.
---
clang/include/clang/Basic/RISCVVTypes.def | 56 +++
.../include/clang/Serialization/ASTBitCodes.h | 2 +-
.../clang/Support/RISCVVIntrinsicUtils.h | 5 +-
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 3 +
.../rvv-intrinsic-datatypes.cpp | 55 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 +-
6 files changed, 121 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index af44cdcd53e5bd0..6620de8ad50e01e 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -452,6 +452,62 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x4_t",
RvvFloat64m2x4, RvvFloat64m2x4Ty, 2
RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4x2_t", RvvFloat64m4x2, RvvFloat64m4x2Ty,
4, 64, 2)
+//===- BFloat16 tuple types
-===//
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x2_t", RvvBFloat16mf4x2,
RvvBFloat16mf4x2Ty,
+ 1, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x3_t", RvvBFloat16mf4x3,
RvvBFloat16mf4x3Ty,
+ 1, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x4_t", RvvBFloat16mf4x4,
RvvBFloat16mf4x4Ty,
+ 1, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x5_t", RvvBFloat16mf4x5,
RvvBFloat16mf4x5Ty,
+ 1, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x6_t", RvvBFloat16mf4x6,
RvvBFloat16mf4x6Ty,
+ 1, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x7_t", RvvBFloat16mf4x7,
RvvBFloat16mf4x7Ty,
+ 1, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x8_t", RvvBFloat16mf4x8,
RvvBFloat16mf4x8Ty,
+ 1, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x2_t", RvvBFloat16mf2x2,
RvvBFloat16mf2x2Ty,
+ 2, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x3_t", RvvBFloat16mf2x3,
RvvBFloat16mf2x3Ty,
+ 2, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x4_t", RvvBFloat16mf2x4,
RvvBFloat16mf2x4Ty,
+ 2, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x5_t", RvvBFloat16mf2x5,
RvvBFloat16mf2x5Ty,
+ 2, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x6_t", RvvBFloat16mf2x6,
RvvBFloat16mf2x6Ty,
+ 2, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x7_t", RvvBFloat16mf2x7,
RvvBFloat16mf2x7Ty,
+ 2, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x8_t", RvvBFloat16mf2x8,
RvvBFloat16mf2x8Ty,
+ 2, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x2_t", RvvBFloat16m1x2,
RvvBFloat16m1x2Ty,
+ 4, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x3_t", RvvBFloat16m1x3,
RvvBFloat16m1x3Ty,
+ 4, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x4_t", RvvBFloat16m1x4,
RvvBFloat16m1x4Ty,
+ 4, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x5_t", RvvBFloat16m1x5,
RvvBFloat16m1x5Ty,
+ 4, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x6_t", RvvBFloat16m1x6,
RvvBFloat16m1x6Ty,
+ 4, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x7_t", RvvBFloat16m1x7,
RvvBFloat16m1x7Ty,
+ 4, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x8_t", RvvBFloat16m1x8,
RvvBFloat16m1x8Ty,
+ 4, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x2_t", RvvBFloat16m2x2,
RvvBFloat16m2x2Ty,
+ 8, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x3_t", RvvBFloat16m2x3,
RvvBFloat16m2x3Ty,
+ 8, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x4_t", RvvBFloat16m2x4,
RvvBFloat16m2x4Ty,
+ 8, 16, 4)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m4x2_t", RvvBFloat16m4x2,
RvvBFloat16m4x2Ty,
+ 16, 16, 2)
+
#undef RVV_VECTOR_TYPE_BFLOAT
#undef RVV_VECTOR_TYPE_FLOAT
#undef RVV_VECTOR_TYPE_INT
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h
b/clang/include/clang/Serialization/ASTBitCodes.h
index 5c32fbc079c9a65..9044c46fc671963 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDE
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72370
>From 78e3ab20f5e527563b7645635b7147fdda8ba4b9 Mon Sep 17 00:00:00 2001
From: "Yueh-Ting (eop) Chen"
Date: Wed, 15 Nov 2023 13:50:14 +0800
Subject: [PATCH 1/3] [Clang][RISCV] Introduce tuple types for RVV bfloat16
(#72216)
The first commit extends the capacity from the compiler infrastructure,
and the second commit continues the effort in #71140 to introduce tuple
types for bfloat16.
---
clang/include/clang/Basic/RISCVVTypes.def | 56 +++
.../include/clang/Serialization/ASTBitCodes.h | 2 +-
.../clang/Support/RISCVVIntrinsicUtils.h | 5 +-
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 3 +
.../rvv-intrinsic-datatypes.cpp | 55 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 +-
6 files changed, 121 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index af44cdcd53e5bd0..6620de8ad50e01e 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -452,6 +452,62 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x4_t",
RvvFloat64m2x4, RvvFloat64m2x4Ty, 2
RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4x2_t", RvvFloat64m4x2, RvvFloat64m4x2Ty,
4, 64, 2)
+//===- BFloat16 tuple types
-===//
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x2_t", RvvBFloat16mf4x2,
RvvBFloat16mf4x2Ty,
+ 1, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x3_t", RvvBFloat16mf4x3,
RvvBFloat16mf4x3Ty,
+ 1, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x4_t", RvvBFloat16mf4x4,
RvvBFloat16mf4x4Ty,
+ 1, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x5_t", RvvBFloat16mf4x5,
RvvBFloat16mf4x5Ty,
+ 1, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x6_t", RvvBFloat16mf4x6,
RvvBFloat16mf4x6Ty,
+ 1, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x7_t", RvvBFloat16mf4x7,
RvvBFloat16mf4x7Ty,
+ 1, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x8_t", RvvBFloat16mf4x8,
RvvBFloat16mf4x8Ty,
+ 1, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x2_t", RvvBFloat16mf2x2,
RvvBFloat16mf2x2Ty,
+ 2, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x3_t", RvvBFloat16mf2x3,
RvvBFloat16mf2x3Ty,
+ 2, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x4_t", RvvBFloat16mf2x4,
RvvBFloat16mf2x4Ty,
+ 2, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x5_t", RvvBFloat16mf2x5,
RvvBFloat16mf2x5Ty,
+ 2, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x6_t", RvvBFloat16mf2x6,
RvvBFloat16mf2x6Ty,
+ 2, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x7_t", RvvBFloat16mf2x7,
RvvBFloat16mf2x7Ty,
+ 2, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x8_t", RvvBFloat16mf2x8,
RvvBFloat16mf2x8Ty,
+ 2, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x2_t", RvvBFloat16m1x2,
RvvBFloat16m1x2Ty,
+ 4, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x3_t", RvvBFloat16m1x3,
RvvBFloat16m1x3Ty,
+ 4, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x4_t", RvvBFloat16m1x4,
RvvBFloat16m1x4Ty,
+ 4, 16, 4)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x5_t", RvvBFloat16m1x5,
RvvBFloat16m1x5Ty,
+ 4, 16, 5)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x6_t", RvvBFloat16m1x6,
RvvBFloat16m1x6Ty,
+ 4, 16, 6)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x7_t", RvvBFloat16m1x7,
RvvBFloat16m1x7Ty,
+ 4, 16, 7)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x8_t", RvvBFloat16m1x8,
RvvBFloat16m1x8Ty,
+ 4, 16, 8)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x2_t", RvvBFloat16m2x2,
RvvBFloat16m2x2Ty,
+ 8, 16, 2)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x3_t", RvvBFloat16m2x3,
RvvBFloat16m2x3Ty,
+ 8, 16, 3)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x4_t", RvvBFloat16m2x4,
RvvBFloat16m2x4Ty,
+ 8, 16, 4)
+
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m4x2_t", RvvBFloat16m4x2,
RvvBFloat16m4x2Ty,
+ 16, 16, 2)
+
#undef RVV_VECTOR_TYPE_BFLOAT
#undef RVV_VECTOR_TYPE_FLOAT
#undef RVV_VECTOR_TYPE_INT
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h
b/clang/include/clang/Serialization/ASTBitCodes.h
index 5c32fbc079c9a65..9044c46fc671963 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDE
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
eopXD wrote: @antmox The test case failure should be resolved with the latest commit. Its not any indeterminate result detected by CI, just that I missed an update to the test case that is expecting deterministic TypeID. If CI passed, based on previous approval, should be good and safe to land it. https://github.com/llvm/llvm-project/pull/72370 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/72370 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDEF_TYPE_IDS = 502;
eopXD wrote:
It is not the problem of 502 or 600. The test case failure in
`clang/test/Modules/decl-params-determinisim.m` is because it is expecting the
original TypeID before change, and updating the capacity `NUM_PREDEF_TYPE_IDS`
here changes the result and so the test case needs to be updated.
https://github.com/llvm/llvm-project/pull/72370
___
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https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDEF_TYPE_IDS = 502;
eopXD wrote:
I extended `NUM_PREDEF_TYPE_IDS` to the least required, and left a note inside
the test case to let future developers be aware that the test case it
intertwine with the constant.
https://github.com/llvm/llvm-project/pull/72370
___
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[clang] [Clang][RISCV] Remove duplicate functions isRVVSizelessBuiltinType. NFC (PR #67089)
eopXD wrote: Ping. https://github.com/llvm/llvm-project/pull/67089 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Remove duplicate functions isRVVSizelessBuiltinType. NFC (PR #67089)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67089
>From 0c449af2049f32103a4f7edf5852f317f6454a23 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 23:17:22 -0700
Subject: [PATCH] [Clang][RISCV] Remove duplicate functions
isRVVSizelessBuiltinType. NFC
`isRVVSizelessBuiltinType` and `isRVVType` has the same functionality.
This commit removes the former since we have more variants available in
`isRVVType`.
---
clang/include/clang/AST/Type.h | 3 ---
clang/lib/AST/ASTContext.cpp| 14 ++
clang/lib/AST/Type.cpp | 15 +--
clang/lib/Sema/SemaExpr.cpp | 8
clang/lib/Sema/SemaOverload.cpp | 3 +--
5 files changed, 12 insertions(+), 31 deletions(-)
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 6c147eb8f640623..4c1f5dfc35f6a7e 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -2117,9 +2117,6 @@ class alignas(TypeAlignment) Type : public
ExtQualsTypeCommonBase {
/// Returns true for SVE scalable vector types.
bool isSVESizelessBuiltinType() const;
- /// Returns true for RVV scalable vector types.
- bool isRVVSizelessBuiltinType() const;
-
/// Check if this is a WebAssembly Externref Type.
bool isWebAssemblyExternrefType() const;
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 4f54791b4c1e5ce..67e26204fa41f23 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -9521,10 +9521,9 @@ static uint64_t getRVVTypeSize(ASTContext &Context,
const BuiltinType *Ty) {
bool ASTContext::areCompatibleRVVTypes(QualType FirstType,
QualType SecondType) {
- assert(
- ((FirstType->isRVVSizelessBuiltinType() && SecondType->isVectorType()) ||
- (FirstType->isVectorType() && SecondType->isRVVSizelessBuiltinType()))
&&
- "Expected RVV builtin type and vector type!");
+ assert(((FirstType->isRVVType() && SecondType->isVectorType()) ||
+ (FirstType->isVectorType() && SecondType->isRVVType())) &&
+ "Expected RVV builtin type and vector type!");
auto IsValidCast = [this](QualType FirstType, QualType SecondType) {
if (const auto *BT = FirstType->getAs()) {
@@ -9546,10 +9545,9 @@ bool ASTContext::areCompatibleRVVTypes(QualType
FirstType,
bool ASTContext::areLaxCompatibleRVVTypes(QualType FirstType,
QualType SecondType) {
- assert(
- ((FirstType->isRVVSizelessBuiltinType() && SecondType->isVectorType()) ||
- (FirstType->isVectorType() && SecondType->isRVVSizelessBuiltinType()))
&&
- "Expected RVV builtin type and vector type!");
+ assert(((FirstType->isRVVType() && SecondType->isVectorType()) ||
+ (FirstType->isVectorType() && SecondType->isRVVType())) &&
+ "Expected RVV builtin type and vector type!");
auto IsLaxCompatible = [this](QualType FirstType, QualType SecondType) {
const auto *BT = FirstType->getAs();
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index c8e452e2feab0bf..5e1ceafb80f3892 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -2403,7 +2403,7 @@ bool Type::isWebAssemblyTableType() const {
bool Type::isSizelessType() const { return isSizelessBuiltinType(); }
bool Type::isSizelessVectorType() const {
- return isSVESizelessBuiltinType() || isRVVSizelessBuiltinType();
+ return isSVESizelessBuiltinType() || isRVVType();
}
bool Type::isSVESizelessBuiltinType() const {
@@ -2420,19 +2420,6 @@ bool Type::isSVESizelessBuiltinType() const {
return false;
}
-bool Type::isRVVSizelessBuiltinType() const {
- if (const BuiltinType *BT = getAs()) {
-switch (BT->getKind()) {
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
- return true;
-default:
- return false;
-}
- }
- return false;
-}
-
bool Type::isSveVLSBuiltinType() const {
if (const BuiltinType *BT = getAs()) {
switch (BT->getKind()) {
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index fc39d6149c1cc65..b58a7c1989c1add 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -8272,7 +8272,7 @@ bool Sema::isValidRVVBitcast(QualType srcTy, QualType
destTy) {
assert(srcTy->isVectorType() || destTy->isVectorType());
auto ValidScalableConversion = [](QualType FirstType, QualType SecondType) {
-if (!FirstType->isRVVSizelessBuiltinType())
+if (!FirstType->isRVVType())
return false;
const auto *VecTy = SecondType->getAs();
@@ -10254,8 +10254,8 @@ Sema::CheckAssignmentConstraints(QualType LHSType,
ExprResult &RHS,
}
// Allow assignments between fixed-length and sizeless RVV vectors.
-if ((LHSType->isRVVSizelessBuiltinType() && RHSType->isVectorType()) ||
-(LHSType->isVectorType() && RHSType->isRVVSizelessBuiltinType())) {
+if ((LHSType->
[clang] [Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/72463
First few commits are NFC, and then followed by commits to add intrinsics to
support the RVV Bfloat16 types.
Intrinsics specification:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293
>From 2091781c4cf201e078a702bdd17bc66a3a608177 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Tue, 14 Nov 2023 00:52:47 -0800
Subject: [PATCH] [Clang][RISCV] Simplify variable name and its guarded
condition. NFC
Zvfh implies Zvfhmin, the minimum requirement for the intrinsics guarded
by the variable is Zvfhmin.
---
clang/include/clang/Basic/riscv_vector.td | 44 +--
.../clang/Support/RISCVVIntrinsicUtils.h | 2 +-
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 5 +--
clang/utils/TableGen/RISCVVEmitter.cpp| 37
4 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 682f1d5c8af68c0..eb6dec33c18bef2 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -117,7 +117,7 @@ multiclass RVVIndexedLoad {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
-RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
[]) in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
if !not(IsFloat.val) then {
@@ -128,7 +128,7 @@ multiclass RVVIndexedLoad {
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
- RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+ RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
["RV64"]) in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
if !not(IsFloat.val) then {
@@ -222,7 +222,7 @@ multiclass RVVIndexedStore {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, MaskedIRName = op #
"_mask",
- RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+ RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
[]) in {
def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
if !not(IsFloat.val) then {
@@ -233,7 +233,7 @@ multiclass RVVIndexedStore {
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op #
"_mask",
-RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
["RV64"]) in {
def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
if !not(IsFloat.val) then {
@@ -681,7 +681,7 @@ let HasBuiltinAlias = false,
def vlm: RVVVLEMaskBuiltin;
defm vle8: RVVVLEBuiltin<["c"]>;
defm vle16: RVVVLEBuiltin<["s"]>;
-let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in
defm vle16_h: RVVVLEBuiltin<["x"]>;
defm vle32: RVVVLEBuiltin<["i","f"]>;
defm vle64: RVVVLEBuiltin<["l","d"]>;
@@ -689,7 +689,7 @@ defm vle64: RVVVLEBuiltin<["l","d"]>;
def vsm : RVVVSEMaskBuiltin;
defm vse8 : RVVVSEBuiltin<["c"]>;
defm vse16: RVVVSEBuiltin<["s"]>;
-let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vse16_h: RVVVSEBuiltin<["x"]>;
defm vse32: RVVVSEBuiltin<["i","f"]>;
defm vse64: RVVVSEBuiltin<["l","d"]>;
@@ -697,14 +697,14 @@ defm vse64: RVVVSEBuiltin<["l","d"]>;
// 7.5. Vector Strided Instructions
defm vlse8: RVVVLSEBuiltin<["c"]>;
defm vlse16: RVVVLSEBuiltin<["s"]>;
-let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vlse16_h: RVVVLSEBuiltin<["x"]>;
defm vlse32: RVVVLSEBuiltin<["i","f"]>;
defm vlse64: RVVVLSEBuiltin<["l","d"]>;
defm vsse8 : RVVVSSEBuiltin<["c"]>;
defm vsse16: RVVVSSEBuiltin<["s"]>;
-let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vsse16_h: RVVVSSEBuiltin<["x"]>;
defm vsse32: RVVVSSEBuiltin<["i","f"]>;
defm vsse64: RVVVSSEBuiltin<["l","d"]>;
@@ -719,7 +719,7 @@ defm : RVVIndexedStore<"vsoxei">;
// 7.7. Unit-stride Fault-Only-First Loads
defm vle8ff: RVVVLEFFBuiltin<["c"]>;
defm vle16ff: RVVVLEFFBuiltin<["s"]>;
-let Name = "vle16ff_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vle16f
[clang] [Work-in-Progress][Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/72463 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Work-in-Progress][Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72463
>From 2091781c4cf201e078a702bdd17bc66a3a608177 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Tue, 14 Nov 2023 00:52:47 -0800
Subject: [PATCH 1/2] [Clang][RISCV] Simplify variable name and its guarded
condition. NFC
Zvfh implies Zvfhmin, the minimum requirement for the intrinsics guarded
by the variable is Zvfhmin.
---
clang/include/clang/Basic/riscv_vector.td | 44 +--
.../clang/Support/RISCVVIntrinsicUtils.h | 2 +-
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 5 +--
clang/utils/TableGen/RISCVVEmitter.cpp| 37
4 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 682f1d5c8af68c0..eb6dec33c18bef2 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -117,7 +117,7 @@ multiclass RVVIndexedLoad {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
-RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
[]) in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
if !not(IsFloat.val) then {
@@ -128,7 +128,7 @@ multiclass RVVIndexedLoad {
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
- RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+ RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
["RV64"]) in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
if !not(IsFloat.val) then {
@@ -222,7 +222,7 @@ multiclass RVVIndexedStore {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, MaskedIRName = op #
"_mask",
- RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+ RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
[]) in {
def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
if !not(IsFloat.val) then {
@@ -233,7 +233,7 @@ multiclass RVVIndexedStore {
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op #
"_mask",
-RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
["RV64"]) in {
def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
if !not(IsFloat.val) then {
@@ -681,7 +681,7 @@ let HasBuiltinAlias = false,
def vlm: RVVVLEMaskBuiltin;
defm vle8: RVVVLEBuiltin<["c"]>;
defm vle16: RVVVLEBuiltin<["s"]>;
-let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in
defm vle16_h: RVVVLEBuiltin<["x"]>;
defm vle32: RVVVLEBuiltin<["i","f"]>;
defm vle64: RVVVLEBuiltin<["l","d"]>;
@@ -689,7 +689,7 @@ defm vle64: RVVVLEBuiltin<["l","d"]>;
def vsm : RVVVSEMaskBuiltin;
defm vse8 : RVVVSEBuiltin<["c"]>;
defm vse16: RVVVSEBuiltin<["s"]>;
-let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vse16_h: RVVVSEBuiltin<["x"]>;
defm vse32: RVVVSEBuiltin<["i","f"]>;
defm vse64: RVVVSEBuiltin<["l","d"]>;
@@ -697,14 +697,14 @@ defm vse64: RVVVSEBuiltin<["l","d"]>;
// 7.5. Vector Strided Instructions
defm vlse8: RVVVLSEBuiltin<["c"]>;
defm vlse16: RVVVLSEBuiltin<["s"]>;
-let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vlse16_h: RVVVLSEBuiltin<["x"]>;
defm vlse32: RVVVLSEBuiltin<["i","f"]>;
defm vlse64: RVVVLSEBuiltin<["l","d"]>;
defm vsse8 : RVVVSSEBuiltin<["c"]>;
defm vsse16: RVVVSSEBuiltin<["s"]>;
-let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vsse16_h: RVVVSSEBuiltin<["x"]>;
defm vsse32: RVVVSSEBuiltin<["i","f"]>;
defm vsse64: RVVVSSEBuiltin<["l","d"]>;
@@ -719,7 +719,7 @@ defm : RVVIndexedStore<"vsoxei">;
// 7.7. Unit-stride Fault-Only-First Loads
defm vle8ff: RVVVLEFFBuiltin<["c"]>;
defm vle16ff: RVVVLEFFBuiltin<["s"]>;
-let Name = "vle16ff_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in
defm vle16ff: RVVVLEFFBuiltin<["x"]>;
defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
@@ -738,7 +738,7 @@ multic
[clang] [Work-in-Progress][Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72463
>From 2091781c4cf201e078a702bdd17bc66a3a608177 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Tue, 14 Nov 2023 00:52:47 -0800
Subject: [PATCH 1/3] [Clang][RISCV] Simplify variable name and its guarded
condition. NFC
Zvfh implies Zvfhmin, the minimum requirement for the intrinsics guarded
by the variable is Zvfhmin.
---
clang/include/clang/Basic/riscv_vector.td | 44 +--
.../clang/Support/RISCVVIntrinsicUtils.h | 2 +-
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 5 +--
clang/utils/TableGen/RISCVVEmitter.cpp| 37
4 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 682f1d5c8af68c0..eb6dec33c18bef2 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -117,7 +117,7 @@ multiclass RVVIndexedLoad {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
-RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
[]) in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
if !not(IsFloat.val) then {
@@ -128,7 +128,7 @@ multiclass RVVIndexedLoad {
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
- RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+ RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
["RV64"]) in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
if !not(IsFloat.val) then {
@@ -222,7 +222,7 @@ multiclass RVVIndexedStore {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, MaskedIRName = op #
"_mask",
- RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+ RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
[]) in {
def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
if !not(IsFloat.val) then {
@@ -233,7 +233,7 @@ multiclass RVVIndexedStore {
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op #
"_mask",
-RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
["RV64"]) in {
def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
if !not(IsFloat.val) then {
@@ -681,7 +681,7 @@ let HasBuiltinAlias = false,
def vlm: RVVVLEMaskBuiltin;
defm vle8: RVVVLEBuiltin<["c"]>;
defm vle16: RVVVLEBuiltin<["s"]>;
-let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in
defm vle16_h: RVVVLEBuiltin<["x"]>;
defm vle32: RVVVLEBuiltin<["i","f"]>;
defm vle64: RVVVLEBuiltin<["l","d"]>;
@@ -689,7 +689,7 @@ defm vle64: RVVVLEBuiltin<["l","d"]>;
def vsm : RVVVSEMaskBuiltin;
defm vse8 : RVVVSEBuiltin<["c"]>;
defm vse16: RVVVSEBuiltin<["s"]>;
-let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vse16_h: RVVVSEBuiltin<["x"]>;
defm vse32: RVVVSEBuiltin<["i","f"]>;
defm vse64: RVVVSEBuiltin<["l","d"]>;
@@ -697,14 +697,14 @@ defm vse64: RVVVSEBuiltin<["l","d"]>;
// 7.5. Vector Strided Instructions
defm vlse8: RVVVLSEBuiltin<["c"]>;
defm vlse16: RVVVLSEBuiltin<["s"]>;
-let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vlse16_h: RVVVLSEBuiltin<["x"]>;
defm vlse32: RVVVLSEBuiltin<["i","f"]>;
defm vlse64: RVVVLSEBuiltin<["l","d"]>;
defm vsse8 : RVVVSSEBuiltin<["c"]>;
defm vsse16: RVVVSSEBuiltin<["s"]>;
-let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in
defm vsse16_h: RVVVSSEBuiltin<["x"]>;
defm vsse32: RVVVSSEBuiltin<["i","f"]>;
defm vsse64: RVVVSSEBuiltin<["l","d"]>;
@@ -719,7 +719,7 @@ defm : RVVIndexedStore<"vsoxei">;
// 7.7. Unit-stride Fault-Only-First Loads
defm vle8ff: RVVVLEFFBuiltin<["c"]>;
defm vle16ff: RVVVLEFFBuiltin<["s"]>;
-let Name = "vle16ff_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in
defm vle16ff: RVVVLEFFBuiltin<["x"]>;
defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
@@ -738,7 +738,7 @@ multic
[clang] [Work-in-Progress][Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72463
>From 8a3db304250683dcd03cc56a5332d03ecdcff140 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Wed, 15 Nov 2023 18:10:54 -0800
Subject: [PATCH 1/2] [Clang][RISCV] Type alignment for the type recording
required extensions. NFC
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 5 +++--
clang/utils/TableGen/RISCVVEmitter.cpp | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 49ce32553da81eb..11eba8df5040550 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -485,7 +485,8 @@ class RVVIntrinsic {
// RVVRequire should be sync'ed with target features, but only
// required features used in riscv_vector.td.
-enum RVVRequire : uint16_t {
+using RVVRequireT = uint16_t;
+enum RVVRequire : RVVRequireT {
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
RVV_REQ_ZvfhminOrZvfh = 1 << 1,
@@ -536,7 +537,7 @@ struct RVVIntrinsicRecord {
uint8_t OverloadedSuffixSize;
// Required target features for this intrinsic.
- uint16_t RequiredExtensions;
+ RVVRequireT RequiredExtensions;
// Supported type, mask of BasicType.
uint8_t TypeRangeMask;
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index cf731e8414a3b83..0fd9009f679cedd 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -46,7 +46,7 @@ struct SemaRecord {
unsigned Log2LMULMask;
// Required extensions for this intrinsic.
- unsigned RequiredExtensions;
+ RVVRequireT RequiredExtensions;
// Prototype for this intrinsic.
SmallVector Prototype;
>From f3bdd76d81cf07f0d240ebc1b2ace5a9dc8fa320 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Wed, 15 Nov 2023 19:24:54 -0800
Subject: [PATCH 2/2] [Clang][RISCV] Add vle16 intrinsic for RVV bfloat16 type
---
clang/include/clang/Basic/riscv_vector.td | 2 +
.../clang/Support/RISCVVIntrinsicUtils.h | 5 +-
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 10 ++
.../non-policy/non-overloaded/vle16.c | 132 ++
.../zvfbfmin-error.c | 24
clang/utils/TableGen/RISCVVEmitter.cpp| 1 +
6 files changed, 172 insertions(+), 2 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/bfloat16-intrinsics/non-policy/non-overloaded/vle16.c
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfbfmin-error.c
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 682f1d5c8af68c0..3d245637096b68e 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -683,6 +683,8 @@ defm vle8: RVVVLEBuiltin<["c"]>;
defm vle16: RVVVLEBuiltin<["s"]>;
let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
defm vle16_h: RVVVLEBuiltin<["x"]>;
+let Name = "vle16_v", RequiredFeatures = ["Zvfbfmin"] in
+ defm vle16_b: RVVVLEBuiltin<["b"]>;
defm vle32: RVVVLEBuiltin<["i","f"]>;
defm vle64: RVVVLEBuiltin<["l","d"]>;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 11eba8df5040550..38a8e5970b4add3 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -485,7 +485,7 @@ class RVVIntrinsic {
// RVVRequire should be sync'ed with target features, but only
// required features used in riscv_vector.td.
-using RVVRequireT = uint16_t;
+using RVVRequireT = uint32_t;
enum RVVRequire : RVVRequireT {
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
@@ -504,8 +504,9 @@ enum RVVRequire : RVVRequireT {
RVV_REQ_Zvknhb = 1 << 13,
RVV_REQ_Zvksed = 1 << 14,
RVV_REQ_Zvksh = 1 << 15,
+ RVV_REQ_Zvfbfmin = 1 << 16,
- LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
+ LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvfbfmin)
};
// Raw RVV intrinsic info, used to expand later.
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 9a5aecf669a07df..536778c1d1ad179 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -288,6 +288,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
}
}
+ if (BaseType == BasicType::BFloat16) {
+if (Record.RequiredExtensions & RVV_REQ_Zvfbfmin) {
+ if (!TI.hasFeature("experimental-zvfbfmin"))
+continue;
+} else {
+ llvm_unreachable_internal(
+ "Non-basic BFloat16 intrinsics are not implemented yet.");
+}
+ }
+
// Expanded with different LMUL.
for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3
diff --git
a/clang/test/C
[clang] [Work-in-Progress][Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72463
>From 8a3db304250683dcd03cc56a5332d03ecdcff140 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Wed, 15 Nov 2023 18:10:54 -0800
Subject: [PATCH 1/2] [Clang][RISCV] Type alignment for the type recording
required extensions. NFC
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 5 +++--
clang/utils/TableGen/RISCVVEmitter.cpp | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 49ce32553da81eb..11eba8df5040550 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -485,7 +485,8 @@ class RVVIntrinsic {
// RVVRequire should be sync'ed with target features, but only
// required features used in riscv_vector.td.
-enum RVVRequire : uint16_t {
+using RVVRequireT = uint16_t;
+enum RVVRequire : RVVRequireT {
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
RVV_REQ_ZvfhminOrZvfh = 1 << 1,
@@ -536,7 +537,7 @@ struct RVVIntrinsicRecord {
uint8_t OverloadedSuffixSize;
// Required target features for this intrinsic.
- uint16_t RequiredExtensions;
+ RVVRequireT RequiredExtensions;
// Supported type, mask of BasicType.
uint8_t TypeRangeMask;
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index cf731e8414a3b83..0fd9009f679cedd 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -46,7 +46,7 @@ struct SemaRecord {
unsigned Log2LMULMask;
// Required extensions for this intrinsic.
- unsigned RequiredExtensions;
+ RVVRequireT RequiredExtensions;
// Prototype for this intrinsic.
SmallVector Prototype;
>From 554283f5ab88c62ce0410fe795a48939db11a229 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 16 Nov 2023 00:47:11 -0800
Subject: [PATCH 2/2] [Clang][RISCV] Add vle16 intrinsic for RVV bfloat16 type
---
clang/include/clang/Basic/riscv_vector.td | 2 +
.../clang/Support/RISCVVIntrinsicUtils.h | 5 +-
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 10 ++
.../non-policy/non-overloaded/vle16.c | 132 ++
.../zvfbfmin-error.c | 24
clang/utils/TableGen/RISCVVEmitter.cpp| 38 ++---
6 files changed, 191 insertions(+), 20 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/bfloat16-intrinsics/non-policy/non-overloaded/vle16.c
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfbfmin-error.c
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 682f1d5c8af68c0..3d245637096b68e 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -683,6 +683,8 @@ defm vle8: RVVVLEBuiltin<["c"]>;
defm vle16: RVVVLEBuiltin<["s"]>;
let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
defm vle16_h: RVVVLEBuiltin<["x"]>;
+let Name = "vle16_v", RequiredFeatures = ["Zvfbfmin"] in
+ defm vle16_b: RVVVLEBuiltin<["b"]>;
defm vle32: RVVVLEBuiltin<["i","f"]>;
defm vle64: RVVVLEBuiltin<["l","d"]>;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 11eba8df5040550..38a8e5970b4add3 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -485,7 +485,7 @@ class RVVIntrinsic {
// RVVRequire should be sync'ed with target features, but only
// required features used in riscv_vector.td.
-using RVVRequireT = uint16_t;
+using RVVRequireT = uint32_t;
enum RVVRequire : RVVRequireT {
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
@@ -504,8 +504,9 @@ enum RVVRequire : RVVRequireT {
RVV_REQ_Zvknhb = 1 << 13,
RVV_REQ_Zvksed = 1 << 14,
RVV_REQ_Zvksh = 1 << 15,
+ RVV_REQ_Zvfbfmin = 1 << 16,
- LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
+ LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvfbfmin)
};
// Raw RVV intrinsic info, used to expand later.
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 9a5aecf669a07df..536778c1d1ad179 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -288,6 +288,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
}
}
+ if (BaseType == BasicType::BFloat16) {
+if (Record.RequiredExtensions & RVV_REQ_Zvfbfmin) {
+ if (!TI.hasFeature("experimental-zvfbfmin"))
+continue;
+} else {
+ llvm_unreachable_internal(
+ "Non-basic BFloat16 intrinsics are not implemented yet.");
+}
+ }
+
// Expanded with different LMUL.
for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3
diff --git
a/clang/t
[clang] [Work-in-Progress][Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/72463 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/72370 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (PR #72370)
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDEF_TYPE_IDS = 502;
eopXD wrote:
Yes you are right. My mistake here. Update the PR description.
https://github.com/llvm/llvm-project/pull/72370
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[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)
@@ -7,534 +7,2189 @@
#include
-// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4
-// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4(
+// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT:ret poison
//
-vfloat16mf4_t test_vundefined_f16mf4() {
- return __riscv_vundefined_f16mf4();
-}
+vfloat16mf4_t test_vundefined_f16mf4() { return __riscv_vundefined_f16mf4(); }
eopXD wrote:
I added script under rvv-intrinsic-doc to apply clang-format to auto-generated
test cases.
https://github.com/llvm/llvm-project/pull/70354
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[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)
eopXD wrote: A gentle ping now that we have this inside the spec. https://github.com/llvm/llvm-project/pull/70355 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)
@@ -1,4 +1,4 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 eopXD wrote: I guess this is something new inside the `update_cc_test_check.py` script. https://github.com/llvm/llvm-project/pull/70354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/70354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/70355 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
https://github.com/eopXD approved this pull request. Sorry I did not do this before you. The patch looks good, I would say we also need tuples of bf16 for completeness. But I will be adding a suite of intrinsics around BFloat16 (https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293) so we can probably do that after this landed too. I would recommend to mention that vector bfloat16 types is introduced in the title of this PR. https://github.com/llvm/llvm-project/pull/71140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
eopXD wrote: Approval is upon addressing Craig's comment. https://github.com/llvm/llvm-project/pull/71140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Refactor checkRVVTypeSupport to use BuiltinVectorTypeInfo. (PR #74949)
https://github.com/eopXD approved this pull request. Looks good. If I understand correctly, you mean that `vbool64_t` should emit diagnosis of requiring `zve64x` and should not emit error of `zve32x.` https://github.com/llvm/llvm-project/pull/74949 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Prevent checkRVVTypeSupport from issuing more than 1 diagnostic. (PR #74950)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/74950 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Prevent checkRVVTypeSupport from issuing more than 1 diagnostic. (PR #74950)
https://github.com/eopXD approved this pull request. Looks good since we have just landed #74949. https://github.com/llvm/llvm-project/pull/74950 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #67018)
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/67018
This commit fixes compilation issue for RVV tuple types as OutputOperand for
inline asm. The LLVM IR generated by the test case added is currently not
handled successfully in the backend, which also needs a fix too.
>From 1e02945f9cbfa4b7abfa47c8e94366d71d747c36 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Expressing the type as a structure in inline asm calls will complicate
the current code case, so instead, the return type is set to be
a single scalable vector, then reconstructed with `vector.extract` and
`insertvalue`.
A follow-up commit will deal with details when associated with
InputOperands.
---
clang/lib/CodeGen/CGStmt.cpp | 70 ++-
.../rvv-inline-asm.c | 41 +++
2 files changed, 109 insertions(+), 2 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 6674aa2409a5947..0dd79903802f328 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -19,6 +19,7 @@
#include "clang/AST/Expr.h"
#include "clang/AST/Stmt.h"
#include "clang/AST/StmtVisitor.h"
+#include "clang/AST/Type.h"
#include "clang/Basic/Builtins.h"
#include "clang/Basic/DiagnosticSema.h"
#include "clang/Basic/PrettyStackTrace.h"
@@ -29,10 +30,13 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/MDBuilder.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/SaveAndRestore.h"
#include
@@ -2392,6 +2396,27 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
} else if (TruncTy->isVectorTy()) {
Tmp = Builder.CreateBitCast(Tmp, TruncTy);
+ } else if (TruncTy->isStructTy()) {
+auto *STy = cast(TruncTy);
+auto *VTy = cast(STy->getElementType(0));
+
+assert(ResultRegQualTys[i]->isRVVType() &&
+ STy->containsHomogeneousScalableVectorTypes() &&
+ "Must be dealing with RVV tuple type");
+
+unsigned MinElts = VTy->getElementCount().getKnownMinValue();
+llvm::Value *StructValue = llvm::PoisonValue::get(STy);
+
+for (unsigned Idx = 0, TupleSize = STy->getNumElements();
+ Idx != TupleSize; ++Idx) {
+ llvm::Value *IdxValue =
+ llvm::ConstantInt::get(CGM.Int64Ty, Idx * MinElts);
+ llvm::Value *SubVec = Builder.CreateExtractVector(VTy, Tmp,
IdxValue);
+
+ StructValue = Builder.CreateInsertValue(StructValue, SubVec, Idx);
+}
+
+Tmp = StructValue;
}
}
@@ -2399,7 +2424,13 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+ unsigned Size;
+ if (ResultRegQualTys[i]->isRVVType() && TruncTy->isStructTy()) {
+Size = cast(
+ cast(TruncTy)->getElementType(0))
+ ->getScalarSizeInBits();
+ } else
+Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
Builder.CreateStore(Tmp, A);
@@ -2524,11 +2555,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm calls will complicate
+ // the current code case, so instead, the return type is set to be a
+ // single scalable vector, then reconstructed with `vector.extract` and
+ // `insertvalue`. The type is derived here, and the reconstruction is
done
+ // under EmitAsmStores.
+ if (QTy->isRVVType() && isa(Ty)) {
+// Flatten the structure into a single ScalableVectorType
+auto *STy = cast(Ty);
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ isa(STy->getElementType(0)) &&
+ "Dealing with RVV tuple (aggregate with homogeneous scalable "
+ "vectors
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #67018)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67018
>From 565785dd4938355c738a792676f8c4b1f9684329 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Expressing the type as a structure in inline asm calls will complicate
the current code base, so instead, the return type is set to be
a single scalable vector, then reconstructed with `vector.extract` and
`insertvalue`.
A follow-up commit will deal with details when associated with
InputOperands.
---
clang/lib/CodeGen/CGStmt.cpp | 70 ++-
.../rvv-inline-asm.c | 41 +++
2 files changed, 109 insertions(+), 2 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 6674aa2409a5947..0dd79903802f328 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -19,6 +19,7 @@
#include "clang/AST/Expr.h"
#include "clang/AST/Stmt.h"
#include "clang/AST/StmtVisitor.h"
+#include "clang/AST/Type.h"
#include "clang/Basic/Builtins.h"
#include "clang/Basic/DiagnosticSema.h"
#include "clang/Basic/PrettyStackTrace.h"
@@ -29,10 +30,13 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/MDBuilder.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/SaveAndRestore.h"
#include
@@ -2392,6 +2396,27 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
} else if (TruncTy->isVectorTy()) {
Tmp = Builder.CreateBitCast(Tmp, TruncTy);
+ } else if (TruncTy->isStructTy()) {
+auto *STy = cast(TruncTy);
+auto *VTy = cast(STy->getElementType(0));
+
+assert(ResultRegQualTys[i]->isRVVType() &&
+ STy->containsHomogeneousScalableVectorTypes() &&
+ "Must be dealing with RVV tuple type");
+
+unsigned MinElts = VTy->getElementCount().getKnownMinValue();
+llvm::Value *StructValue = llvm::PoisonValue::get(STy);
+
+for (unsigned Idx = 0, TupleSize = STy->getNumElements();
+ Idx != TupleSize; ++Idx) {
+ llvm::Value *IdxValue =
+ llvm::ConstantInt::get(CGM.Int64Ty, Idx * MinElts);
+ llvm::Value *SubVec = Builder.CreateExtractVector(VTy, Tmp,
IdxValue);
+
+ StructValue = Builder.CreateInsertValue(StructValue, SubVec, Idx);
+}
+
+Tmp = StructValue;
}
}
@@ -2399,7 +2424,13 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+ unsigned Size;
+ if (ResultRegQualTys[i]->isRVVType() && TruncTy->isStructTy()) {
+Size = cast(
+ cast(TruncTy)->getElementType(0))
+ ->getScalarSizeInBits();
+ } else
+Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
Builder.CreateStore(Tmp, A);
@@ -2524,11 +2555,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm calls will complicate
+ // the current code case, so instead, the return type is set to be a
+ // single scalable vector, then reconstructed with `vector.extract` and
+ // `insertvalue`. The type is derived here, and the reconstruction is
done
+ // under EmitAsmStores.
+ if (QTy->isRVVType() && isa(Ty)) {
+// Flatten the structure into a single ScalableVectorType
+auto *STy = cast(Ty);
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ isa(STy->getElementType(0)) &&
+ "Dealing with RVV tuple (aggregate with homogeneous scalable "
+ "vectors");
+
+auto *VecTy = cast(STy->getElementType(0));
+
+Ty = llvm::ScalableVectorType::get(VecTy->getScalarType(),
+ STy->getNumElements() *
+
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #67018)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #67018)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67018
>From a26eb9fe0c09fc0fd504d261874630d8b5edae26 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Expressing the type as a structure in inline asm calls will complicate
the current code base, so instead, the return type is set to be
a single scalable vector, then reconstructed with `vector.extract` and
`insertvalue`.
A follow-up commit will deal with details when associated with
InputOperands.
---
clang/lib/CodeGen/CGStmt.cpp | 69 ++-
.../rvv-inline-asm.c | 41 +++
2 files changed, 108 insertions(+), 2 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 6674aa2409a5947..948539ea546084e 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -19,6 +19,7 @@
#include "clang/AST/Expr.h"
#include "clang/AST/Stmt.h"
#include "clang/AST/StmtVisitor.h"
+#include "clang/AST/Type.h"
#include "clang/Basic/Builtins.h"
#include "clang/Basic/DiagnosticSema.h"
#include "clang/Basic/PrettyStackTrace.h"
@@ -29,10 +30,13 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/MDBuilder.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/SaveAndRestore.h"
#include
@@ -2392,6 +2396,26 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
} else if (TruncTy->isVectorTy()) {
Tmp = Builder.CreateBitCast(Tmp, TruncTy);
+ } else if (TruncTy->isStructTy() && ResultRegQualTys[i]->isRVVType()) {
+auto *STy = cast(TruncTy);
+auto *VTy = cast(STy->getElementType(0));
+
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ "Must be dealing with RVV tuple type");
+
+unsigned MinElts = VTy->getElementCount().getKnownMinValue();
+llvm::Value *StructValue = llvm::PoisonValue::get(STy);
+
+for (unsigned Idx = 0, TupleSize = STy->getNumElements();
+ Idx != TupleSize; ++Idx) {
+ llvm::Value *IdxValue =
+ llvm::ConstantInt::get(CGM.Int64Ty, Idx * MinElts);
+ llvm::Value *SubVec = Builder.CreateExtractVector(VTy, Tmp,
IdxValue);
+
+ StructValue = Builder.CreateInsertValue(StructValue, SubVec, Idx);
+}
+
+Tmp = StructValue;
}
}
@@ -2399,7 +2423,13 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+ unsigned Size;
+ if (ResultRegQualTys[i]->isRVVType() && TruncTy->isStructTy()) {
+Size = cast(
+ cast(TruncTy)->getElementType(0))
+ ->getScalarSizeInBits();
+ } else
+Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
Builder.CreateStore(Tmp, A);
@@ -2524,11 +2554,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm calls will complicate
+ // the current code case, so instead, the return type is set to be a
+ // single scalable vector, then reconstructed with `vector.extract` and
+ // `insertvalue`. The type is derived here, and the reconstruction is
done
+ // under EmitAsmStores.
+ if (QTy->isRVVType() && isa(Ty)) {
+// Flatten the structure into a single ScalableVectorType
+auto *STy = cast(Ty);
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ isa(STy->getElementType(0)) &&
+ "Dealing with RVV tuple (aggregate with homogeneous scalable "
+ "vectors");
+
+auto *VecTy = cast(STy->getElementType(0));
+
+Ty = llvm::ScalableVectorType::get(VecTy->getScalarType(),
+ STy->getNumElements() *
+
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #67018)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #67018)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Remove duplicate functions isRVVSizelessBuiltinType. NFC (PR #67089)
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/67089
`isRVVSizelessBuiltinType` and `isRVVType` has the same functionality. This
commit removes the former since we have more variants available in `isRVVType`.
>From 483240e16d800e52783dcfaf52eae81fb1dfca7c Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 23:17:22 -0700
Subject: [PATCH] [Clang][RISCV] Remove duplicate functions
isRVVSizelessBuiltinType. NFC
`isRVVSizelessBuiltinType` and `isRVVType` has the same functionality.
This commit removes the former since we have more variants available in
`isRVVType`.
---
clang/include/clang/AST/Type.h | 3 ---
clang/lib/AST/ASTContext.cpp| 14 ++
clang/lib/AST/Type.cpp | 15 +--
clang/lib/Sema/SemaExpr.cpp | 8
clang/lib/Sema/SemaOverload.cpp | 3 +--
5 files changed, 12 insertions(+), 31 deletions(-)
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 4799f89db82fa7f..f4eb57e19d9370d 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -2061,9 +2061,6 @@ class alignas(8) Type : public ExtQualsTypeCommonBase {
/// Returns true for SVE scalable vector types.
bool isSVESizelessBuiltinType() const;
- /// Returns true for RVV scalable vector types.
- bool isRVVSizelessBuiltinType() const;
-
/// Check if this is a WebAssembly Externref Type.
bool isWebAssemblyExternrefType() const;
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 4b1d9e86797b778..c670624b21f14ec 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -9571,10 +9571,9 @@ static uint64_t getRVVTypeSize(ASTContext &Context,
const BuiltinType *Ty) {
bool ASTContext::areCompatibleRVVTypes(QualType FirstType,
QualType SecondType) {
- assert(
- ((FirstType->isRVVSizelessBuiltinType() && SecondType->isVectorType()) ||
- (FirstType->isVectorType() && SecondType->isRVVSizelessBuiltinType()))
&&
- "Expected RVV builtin type and vector type!");
+ assert(((FirstType->isRVVType() && SecondType->isVectorType()) ||
+ (FirstType->isVectorType() && SecondType->isRVVType())) &&
+ "Expected RVV builtin type and vector type!");
auto IsValidCast = [this](QualType FirstType, QualType SecondType) {
if (const auto *BT = FirstType->getAs()) {
@@ -9596,10 +9595,9 @@ bool ASTContext::areCompatibleRVVTypes(QualType
FirstType,
bool ASTContext::areLaxCompatibleRVVTypes(QualType FirstType,
QualType SecondType) {
- assert(
- ((FirstType->isRVVSizelessBuiltinType() && SecondType->isVectorType()) ||
- (FirstType->isVectorType() && SecondType->isRVVSizelessBuiltinType()))
&&
- "Expected RVV builtin type and vector type!");
+ assert(((FirstType->isRVVType() && SecondType->isVectorType()) ||
+ (FirstType->isVectorType() && SecondType->isRVVType())) &&
+ "Expected RVV builtin type and vector type!");
auto IsLaxCompatible = [this](QualType FirstType, QualType SecondType) {
const auto *BT = FirstType->getAs();
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index c08ebfb7f142b35..d0be891122c8fc9 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -2372,7 +2372,7 @@ bool Type::isIncompleteType(NamedDecl **Def) const {
}
bool Type::isSizelessBuiltinType() const {
- if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+ if (isSVESizelessBuiltinType() || isRVVType())
return true;
if (const BuiltinType *BT = getAs()) {
@@ -2420,19 +2420,6 @@ bool Type::isSVESizelessBuiltinType() const {
return false;
}
-bool Type::isRVVSizelessBuiltinType() const {
- if (const BuiltinType *BT = getAs()) {
-switch (BT->getKind()) {
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
- return true;
-default:
- return false;
-}
- }
- return false;
-}
-
bool Type::isSveVLSBuiltinType() const {
if (const BuiltinType *BT = getAs()) {
switch (BT->getKind()) {
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 92496b03ecabe54..dd1080a1085f07c 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -8223,7 +8223,7 @@ bool Sema::isValidRVVBitcast(QualType srcTy, QualType
destTy) {
assert(srcTy->isVectorType() || destTy->isVectorType());
auto ValidScalableConversion = [](QualType FirstType, QualType SecondType) {
-if (!FirstType->isRVVSizelessBuiltinType())
+if (!FirstType->isRVVType())
return false;
const auto *VecTy = SecondType->getAs();
@@ -10212,8 +10212,8 @@ Sema::CheckAssignmentConstraints(QualType LHSType,
ExprResult &RHS,
}
// Allow assignments between fixed-length and sizeless RVV vectors.
-if ((LHSType->isRVVSizelessBuiltinType() && RHSType->isVectorType()) ||
-
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #67018)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67109)
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/67109
This PR is based on #67018. This PR fixes compilation issue for RVV tuple types
as InputOperands for inline asm.
---
Currently the compiler generates https://godbolt.org/z/djebPfqxf for tuple type
as inline asm inputs and cannot be code generated successfully
https://godbolt.org/z/na7T19Krc. This PR fixes Clang by generating
https://godbolt.org/z/MsovoxbY9 instead, which can be successfully handled by
the back-end.
A follow-up PR will handle interactions of RVV tuple type InputOperands and
OutputOperands correctly.
>From a26eb9fe0c09fc0fd504d261874630d8b5edae26 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH 1/3] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Expressing the type as a structure in inline asm calls will complicate
the current code base, so instead, the return type is set to be
a single scalable vector, then reconstructed with `vector.extract` and
`insertvalue`.
A follow-up commit will deal with details when associated with
InputOperands.
---
clang/lib/CodeGen/CGStmt.cpp | 69 ++-
.../rvv-inline-asm.c | 41 +++
2 files changed, 108 insertions(+), 2 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 6674aa2409a5947..948539ea546084e 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -19,6 +19,7 @@
#include "clang/AST/Expr.h"
#include "clang/AST/Stmt.h"
#include "clang/AST/StmtVisitor.h"
+#include "clang/AST/Type.h"
#include "clang/Basic/Builtins.h"
#include "clang/Basic/DiagnosticSema.h"
#include "clang/Basic/PrettyStackTrace.h"
@@ -29,10 +30,13 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/MDBuilder.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/SaveAndRestore.h"
#include
@@ -2392,6 +2396,26 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
} else if (TruncTy->isVectorTy()) {
Tmp = Builder.CreateBitCast(Tmp, TruncTy);
+ } else if (TruncTy->isStructTy() && ResultRegQualTys[i]->isRVVType()) {
+auto *STy = cast(TruncTy);
+auto *VTy = cast(STy->getElementType(0));
+
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ "Must be dealing with RVV tuple type");
+
+unsigned MinElts = VTy->getElementCount().getKnownMinValue();
+llvm::Value *StructValue = llvm::PoisonValue::get(STy);
+
+for (unsigned Idx = 0, TupleSize = STy->getNumElements();
+ Idx != TupleSize; ++Idx) {
+ llvm::Value *IdxValue =
+ llvm::ConstantInt::get(CGM.Int64Ty, Idx * MinElts);
+ llvm::Value *SubVec = Builder.CreateExtractVector(VTy, Tmp,
IdxValue);
+
+ StructValue = Builder.CreateInsertValue(StructValue, SubVec, Idx);
+}
+
+Tmp = StructValue;
}
}
@@ -2399,7 +2423,13 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+ unsigned Size;
+ if (ResultRegQualTys[i]->isRVVType() && TruncTy->isStructTy()) {
+Size = cast(
+ cast(TruncTy)->getElementType(0))
+ ->getScalarSizeInBits();
+ } else
+Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
Builder.CreateStore(Tmp, A);
@@ -2524,11 +2554,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm calls will complicate
+ // the current code case, so instead, the return type is set to be a
+ // single scalable vector, then reconstructed with `vector.extract` and
+ // `insertvalue`. The type is derived here, and the reconstruction is
done
+ // under EmitAsmStores.
+ if (QTy->isRVVType() && isa(Ty)) {
+// F
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67109)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67109 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67018
>From dc77e5c7bca87badecc314b24cab4c10be0e02fa Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Expressing the type as a structure in inline asm calls will complicate
the current code base, so instead, the return type is set to be
a single scalable vector, then reconstructed with `vector.extract` and
`insertvalue`.
A follow-up commit will deal with details when associated with
InputOperands.
---
clang/lib/CodeGen/CGStmt.cpp | 52 ++-
.../rvv-inline-asm.c | 41 +++
2 files changed, 91 insertions(+), 2 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 6674aa2409a5947..755f30b9c9e6369 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -29,6 +29,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
@@ -2392,6 +2393,26 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
} else if (TruncTy->isVectorTy()) {
Tmp = Builder.CreateBitCast(Tmp, TruncTy);
+ } else if (TruncTy->isStructTy() && ResultRegQualTys[i]->isRVVType()) {
+auto *STy = cast(TruncTy);
+auto *VTy = cast(STy->getElementType(0));
+
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ "Must be dealing with RVV tuple type");
+
+unsigned MinElts = VTy->getElementCount().getKnownMinValue();
+llvm::Value *StructValue = llvm::PoisonValue::get(STy);
+
+for (unsigned Idx = 0, TupleSize = STy->getNumElements();
+ Idx != TupleSize; ++Idx) {
+ llvm::Value *IdxValue =
+ llvm::ConstantInt::get(CGM.Int64Ty, Idx * MinElts);
+ llvm::Value *SubVec = Builder.CreateExtractVector(VTy, Tmp,
IdxValue);
+
+ StructValue = Builder.CreateInsertValue(StructValue, SubVec, Idx);
+}
+
+Tmp = StructValue;
}
}
@@ -2399,7 +2420,13 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+ unsigned Size;
+ if (ResultRegQualTys[i]->isRVVType() && TruncTy->isStructTy()) {
+Size = cast(
+ cast(TruncTy)->getElementType(0))
+ ->getScalarSizeInBits();
+ } else
+Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
Builder.CreateStore(Tmp, A);
@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm calls will complicate
+ // the current code case, so instead, the return type is set to be a
+ // single scalable vector, then reconstructed with `vector.extract` and
+ // `insertvalue`. The type is derived here, and the reconstruction is
done
+ // under EmitAsmStores.
+ if (QTy->isRVVType() && isa(Ty)) {
+// Flatten the structure into a single ScalableVectorType
+auto *STy = cast(Ty);
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ isa(STy->getElementType(0)) &&
+ "Dealing with RVV tuple (aggregate with homogeneous scalable "
+ "vectors");
+
+auto *VecTy = cast(STy->getElementType(0));
+
+Ty = llvm::ScalableVectorType::get(VecTy->getScalarType(),
+ STy->getNumElements() *
+ VecTy->getMinNumElements());
+ }
+
const bool RequiresCast = Info.allowsRegister() &&
(getTargetHooks().isScalarizableAsmOperand(*this, Ty) ||
Ty->isAggregateType());
- ResultTruncRegTypes.push_back(Ty);
ResultTypeRequiresCast.push_back(RequiresCast);
if (RequiresCast) {
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67109)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67109
>From dc77e5c7bca87badecc314b24cab4c10be0e02fa Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH 1/3] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Expressing the type as a structure in inline asm calls will complicate
the current code base, so instead, the return type is set to be
a single scalable vector, then reconstructed with `vector.extract` and
`insertvalue`.
A follow-up commit will deal with details when associated with
InputOperands.
---
clang/lib/CodeGen/CGStmt.cpp | 52 ++-
.../rvv-inline-asm.c | 41 +++
2 files changed, 91 insertions(+), 2 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 6674aa2409a5947..755f30b9c9e6369 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -29,6 +29,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
@@ -2392,6 +2393,26 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
} else if (TruncTy->isVectorTy()) {
Tmp = Builder.CreateBitCast(Tmp, TruncTy);
+ } else if (TruncTy->isStructTy() && ResultRegQualTys[i]->isRVVType()) {
+auto *STy = cast(TruncTy);
+auto *VTy = cast(STy->getElementType(0));
+
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ "Must be dealing with RVV tuple type");
+
+unsigned MinElts = VTy->getElementCount().getKnownMinValue();
+llvm::Value *StructValue = llvm::PoisonValue::get(STy);
+
+for (unsigned Idx = 0, TupleSize = STy->getNumElements();
+ Idx != TupleSize; ++Idx) {
+ llvm::Value *IdxValue =
+ llvm::ConstantInt::get(CGM.Int64Ty, Idx * MinElts);
+ llvm::Value *SubVec = Builder.CreateExtractVector(VTy, Tmp,
IdxValue);
+
+ StructValue = Builder.CreateInsertValue(StructValue, SubVec, Idx);
+}
+
+Tmp = StructValue;
}
}
@@ -2399,7 +2420,13 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+ unsigned Size;
+ if (ResultRegQualTys[i]->isRVVType() && TruncTy->isStructTy()) {
+Size = cast(
+ cast(TruncTy)->getElementType(0))
+ ->getScalarSizeInBits();
+ } else
+Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
Builder.CreateStore(Tmp, A);
@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm calls will complicate
+ // the current code case, so instead, the return type is set to be a
+ // single scalable vector, then reconstructed with `vector.extract` and
+ // `insertvalue`. The type is derived here, and the reconstruction is
done
+ // under EmitAsmStores.
+ if (QTy->isRVVType() && isa(Ty)) {
+// Flatten the structure into a single ScalableVectorType
+auto *STy = cast(Ty);
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ isa(STy->getElementType(0)) &&
+ "Dealing with RVV tuple (aggregate with homogeneous scalable "
+ "vectors");
+
+auto *VecTy = cast(STy->getElementType(0));
+
+Ty = llvm::ScalableVectorType::get(VecTy->getScalarType(),
+ STy->getNumElements() *
+ VecTy->getMinNumElements());
+ }
+
const bool RequiresCast = Info.allowsRegister() &&
(getTargetHooks().isScalarizableAsmOperand(*this, Ty) ||
Ty->isAggregateType());
- ResultTruncRegTypes.push_back(Ty);
ResultTypeRequiresCast.push_back(RequiresCast);
if (RequiresCast) {
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-a
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
eopXD wrote: > Does this mean the backend register allocation will pick a large LMUL > register the same size as the whole tuple and force the register to be overly > aligned? For example an lmul=1 seg2 tuple can use v0+v1, or v1+v2, or v2+v3, > etc. But lmul=2 can only use v0+v1, v2+v3, v4+v5, etc. Yes you are correct. The current approach will set restrictions since we will allocate the registers to be the multiplier of the LMUL in the back end. Let me try and work through how I can break them up. https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67018
>From 6f232ccd6dd273b9eecec7f583877a3a5a3696c3 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Get pass validation check for homogeneous scalable vector types in
InlineAsm::verify.
Handle RVV tuple types correctly under CGStmt.cpp:EmitAsmStores, since
we can allow direct store for the tuple types.
A follow-up commit will deal with details when associated with
InputOperands.
---
clang/lib/CodeGen/CGStmt.cpp | 38 +++
.../rvv-inline-asm.c | 29 ++
llvm/lib/IR/InlineAsm.cpp | 11 +-
3 files changed, 61 insertions(+), 17 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 6674aa2409a5947..bb9606178de8a3f 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -29,6 +29,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
@@ -2399,22 +2400,27 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
- Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
- if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
-Builder.CreateStore(Tmp, A);
-continue;
- }
+ if (ResultRegQualTys[i]->isRVVType() && Tmp->getType()->isStructTy()) {
+Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
+Dest = CGF.MakeAddrLValue(A, ResultRegQualTys[i]);
+ } else {
+unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
+if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
+ Builder.CreateStore(Tmp, A);
+ continue;
+}
- QualType Ty =
- CGF.getContext().getIntTypeForBitwidth(Size, /*Signed=*/false);
- if (Ty.isNull()) {
-const Expr *OutExpr = S.getOutputExpr(i);
-CGM.getDiags().Report(OutExpr->getExprLoc(),
- diag::err_store_value_to_reg);
-return;
+QualType Ty =
+CGF.getContext().getIntTypeForBitwidth(Size, /*Signed=*/false);
+if (Ty.isNull()) {
+ const Expr *OutExpr = S.getOutputExpr(i);
+ CGM.getDiags().Report(OutExpr->getExprLoc(),
+diag::err_store_value_to_reg);
+ return;
+}
+Dest = CGF.MakeAddrLValue(A, Ty);
}
- Dest = CGF.MakeAddrLValue(A, Ty);
}
CGF.EmitStoreThroughLValue(RValue::get(Tmp), Dest);
}
@@ -2531,7 +2537,9 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultTruncRegTypes.push_back(Ty);
ResultTypeRequiresCast.push_back(RequiresCast);
- if (RequiresCast) {
+ // Allow RVV tuple type (aggregate of homogeneous scalable vector) to be
+ // pushed into return type of inline asm call.
+ if (RequiresCast && !(QTy->isRVVType() && Ty->isStructTy())) {
unsigned Size = getContext().getTypeSize(QTy);
Ty = llvm::IntegerType::get(getLLVMContext(), Size);
}
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
new file mode 100644
index 000..6d517714179893f
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
@@ -0,0 +1,29 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
+#include
+
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x -disable-O0-optnone
\
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @foo(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call { ,
} asm "#NOP", "=^vr"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void foo() {
+ vint32m1x2_t v0;
+ asm ("#NOP" : "=vr" (v0));
+}
+
+// CHECK-LABEL: define dso_local void @bar(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm calls will complicate
+ // the current code case, so instead, the return type is set to be a
+ // single scalable vector, then reconstructed with `vector.extract` and
+ // `insertvalue`. The type is derived here, and the reconstruction is
done
+ // under EmitAsmStores.
+ if (QTy->isRVVType() && isa(Ty)) {
+// Flatten the structure into a single ScalableVectorType
+auto *STy = cast(Ty);
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ isa(STy->getElementType(0)) &&
+ "Dealing with RVV tuple (aggregate with homogeneous scalable "
+ "vectors");
+
+auto *VecTy = cast(STy->getElementType(0));
+
+Ty = llvm::ScalableVectorType::get(VecTy->getScalarType(),
+ STy->getNumElements() *
+ VecTy->getMinNumElements());
eopXD wrote:
Yes, the initial approach will fall into this hazard. The updated approach to
have them as the structure type we are expecting will avoid falling into this
problem.
https://github.com/llvm/llvm-project/pull/67018
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[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
https://github.com/eopXD resolved https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
eopXD wrote: Change: Updated the approach to get pass inline asm verifications and handle them correctly under `EmitAsmStores`. https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67109)
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67109
>From 6f232ccd6dd273b9eecec7f583877a3a5a3696c3 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH 1/3] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Get pass validation check for homogeneous scalable vector types in
InlineAsm::verify.
Handle RVV tuple types correctly under CGStmt.cpp:EmitAsmStores, since
we can allow direct store for the tuple types.
A follow-up commit will deal with details when associated with
InputOperands.
---
clang/lib/CodeGen/CGStmt.cpp | 38 +++
.../rvv-inline-asm.c | 29 ++
llvm/lib/IR/InlineAsm.cpp | 11 +-
3 files changed, 61 insertions(+), 17 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 6674aa2409a5947..bb9606178de8a3f 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -29,6 +29,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
@@ -2399,22 +2400,27 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
- Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
- if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
-Builder.CreateStore(Tmp, A);
-continue;
- }
+ if (ResultRegQualTys[i]->isRVVType() && Tmp->getType()->isStructTy()) {
+Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
+Dest = CGF.MakeAddrLValue(A, ResultRegQualTys[i]);
+ } else {
+unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
+if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
+ Builder.CreateStore(Tmp, A);
+ continue;
+}
- QualType Ty =
- CGF.getContext().getIntTypeForBitwidth(Size, /*Signed=*/false);
- if (Ty.isNull()) {
-const Expr *OutExpr = S.getOutputExpr(i);
-CGM.getDiags().Report(OutExpr->getExprLoc(),
- diag::err_store_value_to_reg);
-return;
+QualType Ty =
+CGF.getContext().getIntTypeForBitwidth(Size, /*Signed=*/false);
+if (Ty.isNull()) {
+ const Expr *OutExpr = S.getOutputExpr(i);
+ CGM.getDiags().Report(OutExpr->getExprLoc(),
+diag::err_store_value_to_reg);
+ return;
+}
+Dest = CGF.MakeAddrLValue(A, Ty);
}
- Dest = CGF.MakeAddrLValue(A, Ty);
}
CGF.EmitStoreThroughLValue(RValue::get(Tmp), Dest);
}
@@ -2531,7 +2537,9 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultTruncRegTypes.push_back(Ty);
ResultTypeRequiresCast.push_back(RequiresCast);
- if (RequiresCast) {
+ // Allow RVV tuple type (aggregate of homogeneous scalable vector) to be
+ // pushed into return type of inline asm call.
+ if (RequiresCast && !(QTy->isRVVType() && Ty->isStructTy())) {
unsigned Size = getContext().getTypeSize(QTy);
Ty = llvm::IntegerType::get(getLLVMContext(), Size);
}
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
new file mode 100644
index 000..6d517714179893f
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
@@ -0,0 +1,29 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
+#include
+
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x -disable-O0-optnone
\
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @foo(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call { ,
} asm "#NOP", "=^vr"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void foo() {
+ vint32m1x2_t v0;
+ asm ("#NOP" : "=vr" (v0));
+}
+
+// CHECK-LABEL: define dso_local void @bar(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0
[clang] [Clang][RISCV] Handle RVV tuple types correctly as InputOperands for inline asm (PR #67109)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67109 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as InputOperands for inline asm (PR #67109)
eopXD wrote: Change: Rebase upon change of parent PR. https://github.com/llvm/llvm-project/pull/67109 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Remove duplicate functions isRVVSizelessBuiltinType. NFC (PR #67089)
eopXD wrote: Ping. https://github.com/llvm/llvm-project/pull/67089 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)
@@ -0,0 +1,57 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \ +# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN:| FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \ +# RUN:| llvm-objdump -d --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod - \ +# RUN:| FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \ +# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sf.vqmaccu.2x8x2 v8, v4, v20 eopXD wrote: >From intuition I would say the motivation to mask a matrix multiplication may >not be strong? To split matrixes, tiling are done. So a masked version is >probably not needed. (This is my own personal guess though. Not a math library >expert here to back this up with experience. https://github.com/llvm/llvm-project/pull/68295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD review_requested https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD review_requested https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD created
https://github.com/llvm/llvm-project/pull/65778:
Using ValueDecl will cause error for OpenMP. Decl should do the work.
>From 559c8a27f34c983822bb00dfd45c71798c7ecb36 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause error for OpenMP. Decl should do the work.
---
clang/include/clang/Sema/Sema.h | 2 +-
clang/lib/Sema/SemaChecking.cpp | 2 +-
clang/lib/Sema/SemaDecl.cpp | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 4fd0e6bd5982a71..5c7207062741b52 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -13726,7 +13726,7 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 3932d9cd07d9864..3b4ac613da76aa8 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5514,7 +5514,7 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const
TargetInfo &TI,
return false;
}
-void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
+void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
const TargetInfo &TI = Context.getTargetInfo();
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index d6e090ee496eb30..37060f668b7acf3 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8866,7 +8866,7 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
if (T->isRVVType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
}
/// Perform semantic checking on a newly-created variable
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[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD review_requested https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD review_requested https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD updated
https://github.com/llvm/llvm-project/pull/65778:
>From ebffa141090d5274db8a88b5450325e34316a18b Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause error for OpenMP. Decl should do the work.
---
clang/include/clang/Sema/Sema.h| 2 +-
clang/lib/Sema/SemaChecking.cpp| 2 +-
clang/lib/Sema/SemaDecl.cpp| 2 +-
clang/test/Sema/riscv-vector-with-openmp.c | 12
4 files changed, 15 insertions(+), 3 deletions(-)
create mode 100644 clang/test/Sema/riscv-vector-with-openmp.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 4fd0e6bd5982a71..5c7207062741b52 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -13726,7 +13726,7 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 3932d9cd07d9864..3b4ac613da76aa8 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5514,7 +5514,7 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const
TargetInfo &TI,
return false;
}
-void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
+void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
const TargetInfo &TI = Context.getTargetInfo();
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index d6e090ee496eb30..37060f668b7acf3 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8866,7 +8866,7 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
if (T->isRVVType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
}
/// Perform semantic checking on a newly-created variable
diff --git a/clang/test/Sema/riscv-vector-with-openmp.c
b/clang/test/Sema/riscv-vector-with-openmp.c
new file mode 100644
index 000..2408152f9848e36
--- /dev/null
+++ b/clang/test/Sema/riscv-vector-with-openmp.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -disable-O0-optnone -o - -fsyntax-only -fopenmp %s -verify
+// REQUIRES: riscv-registered-target
+// expected-no-diagnostics
+#include
+
+void foo() {
+ #pragma omp parallel
+ {
+vint32m1_t i32m1;
+ }
+}
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[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD updated
https://github.com/llvm/llvm-project/pull/65778:
>From 8226aecca0e5ebcf17465122cd2df6cfd1b5e5c9 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause error for OpenMP. Decl should do the work.
---
clang/include/clang/Sema/Sema.h| 2 +-
clang/lib/Sema/SemaChecking.cpp| 2 +-
clang/lib/Sema/SemaDecl.cpp| 2 +-
clang/test/Sema/riscv-vector-with-openmp.c | 11 +++
4 files changed, 14 insertions(+), 3 deletions(-)
create mode 100644 clang/test/Sema/riscv-vector-with-openmp.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 4fd0e6bd5982a71..5c7207062741b52 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -13726,7 +13726,7 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 3932d9cd07d9864..3b4ac613da76aa8 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5514,7 +5514,7 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const
TargetInfo &TI,
return false;
}
-void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
+void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
const TargetInfo &TI = Context.getTargetInfo();
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index d6e090ee496eb30..37060f668b7acf3 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8866,7 +8866,7 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
if (T->isRVVType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
}
/// Perform semantic checking on a newly-created variable
diff --git a/clang/test/Sema/riscv-vector-with-openmp.c
b/clang/test/Sema/riscv-vector-with-openmp.c
new file mode 100644
index 000..5858fb99ed82d46
--- /dev/null
+++ b/clang/test/Sema/riscv-vector-with-openmp.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -disable-O0-optnone -o - -fsyntax-only -fopenmp %s -verify
+// REQUIRES: riscv-registered-target
+// expected-no-diagnostics
+
+void foo() {
+ #pragma omp parallel
+ {
+__rvv_int32m1_t i32m1;
+ }
+}
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[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD updated
https://github.com/llvm/llvm-project/pull/65778:
>From 90764baf1616f4a150a10f63df0b0ea6bde0a86a Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause error for OpenMP. Decl should do the work.
---
clang/include/clang/Sema/Sema.h| 2 +-
clang/lib/Sema/SemaChecking.cpp| 2 +-
clang/lib/Sema/SemaDecl.cpp| 2 +-
clang/test/Sema/riscv-vector-with-openmp.c | 11 +++
4 files changed, 14 insertions(+), 3 deletions(-)
create mode 100644 clang/test/Sema/riscv-vector-with-openmp.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 4fd0e6bd5982a71..5c7207062741b52 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -13726,7 +13726,7 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 3932d9cd07d9864..3b4ac613da76aa8 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5514,7 +5514,7 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const
TargetInfo &TI,
return false;
}
-void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
+void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
const TargetInfo &TI = Context.getTargetInfo();
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index d6e090ee496eb30..37060f668b7acf3 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8866,7 +8866,7 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
if (T->isRVVType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
}
/// Perform semantic checking on a newly-created variable
diff --git a/clang/test/Sema/riscv-vector-with-openmp.c
b/clang/test/Sema/riscv-vector-with-openmp.c
new file mode 100644
index 000..699650f6b1ff27f
--- /dev/null
+++ b/clang/test/Sema/riscv-vector-with-openmp.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -fopenmp %s
+// REQUIRES: riscv-registered-target
+
+// expected-no-diagnostics
+
+void foo() {
+ #pragma omp parallel
+ {
+__rvv_int32m1_t i32m1;
+ }
+}
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[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD resolved https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD resolved https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD resolved https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD review_requested https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD review_requested https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD updated
https://github.com/llvm/llvm-project/pull/65778:
>From 91e607dd38475ceae604c794e40bd1721aa7dae4 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause error for OpenMP. Decl should do the work.
---
clang/include/clang/Sema/Sema.h | 2 +-
clang/lib/Sema/SemaChecking.cpp | 2 +-
clang/lib/Sema/SemaDecl.cpp | 2 +-
clang/test/SemaOpenMP/riscv-vector-with-openmp.c | 12
4 files changed, 15 insertions(+), 3 deletions(-)
create mode 100644 clang/test/SemaOpenMP/riscv-vector-with-openmp.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 4fd0e6bd5982a71..5c7207062741b52 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -13726,7 +13726,7 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 3932d9cd07d9864..3b4ac613da76aa8 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5514,7 +5514,7 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const
TargetInfo &TI,
return false;
}
-void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
+void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
const TargetInfo &TI = Context.getTargetInfo();
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index d6e090ee496eb30..37060f668b7acf3 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8866,7 +8866,7 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
if (T->isRVVType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
}
/// Perform semantic checking on a newly-created variable
diff --git a/clang/test/SemaOpenMP/riscv-vector-with-openmp.c
b/clang/test/SemaOpenMP/riscv-vector-with-openmp.c
new file mode 100644
index 000..5dae3eb9ce0b0a2
--- /dev/null
+++ b/clang/test/SemaOpenMP/riscv-vector-with-openmp.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -fsyntax-only \
+// RUN: -verify -fopenmp %s
+// REQUIRES: riscv-registered-target
+
+// expected-no-diagnostics
+
+void foo() {
+ #pragma omp parallel
+ {
+__rvv_int32m1_t i32m1;
+ }
+}
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[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD resolved https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD review_requested https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD resolved https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
eopXD wrote: @jrtc27 Anymore comments before merging this? https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD review_requested https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use Decl for checkRVVTypeSupport (PR #65778)
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/65778 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)
eopXD wrote: Maybe test coverage? https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Update counters to version 2p0 (PR #66323)
eopXD wrote: Your commit bumps both the counter and timer extension, which makes your commit message inaccurate. https://github.com/llvm/llvm-project/pull/66323 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Update counters to version 2p0 (PR #66323)
eopXD wrote: Sorry, that was a mis-statement. There are two counter extensions you are bumping. Anyway, rewording the commit message is a nit from me. https://github.com/llvm/llvm-project/pull/66323 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Update Zicntr and Zihpm to version 2p0 (PR #66323)
@@ -629,7 +629,7 @@ TEST(getTargetFeatureForExtension,
RetrieveTargetFeatureFromOneExt) {
TEST(RiscvExtensionsHelp, CheckExtensions) {
std::string ExpectedOutput =
-R"(All available -march extensions for RISC-V
+ R"(All available -march extensions for RISC-V
eopXD wrote:
This change doesn't seem necessary
https://github.com/llvm/llvm-project/pull/66323
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[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)
eopXD wrote: > > Maybe test coverage with `-I %resource_dir`? > > Which file should I place the test? `clang/test/Headers/` https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)
@@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s +// REQUIRES: riscv-registered-target + +// expected-no-diagnostics + +#include eopXD wrote: Does this test case help verify we have `sifive_vector.h` installed? https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)
@@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s +// REQUIRES: riscv-registered-target + +// expected-no-diagnostics + +#include eopXD wrote: I think we can't :( https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)
https://github.com/eopXD resolved https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)
https://github.com/eopXD approved this pull request. https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
