[PATCH] D134007: [Clang][CUDA][NFC] Rename 'addDeviceDepences' to 'addDeviceDependences' in DeviceActionBuilder.

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I think this method's name maybe `addDeviceDependences` not `addDeviceDepences`.


Repository:
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https://reviews.llvm.org/D134007

Files:
  clang/lib/Driver/Driver.cpp


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -2733,7 +2733,7 @@
 
 /// Update the state to include the provided host action \a HostAction as a
 /// dependency of the current device action. By default it is inactive.
-virtual ActionBuilderReturnCode addDeviceDepences(Action *HostAction) {
+virtual ActionBuilderReturnCode addDeviceDependences(Action *HostAction) {
   return ABRT_Inactive;
 }
 
@@ -2821,7 +2821,7 @@
   Action::OffloadKind OFKind)
 : DeviceActionBuilder(C, Args, Inputs, OFKind) {}
 
-ActionBuilderReturnCode addDeviceDepences(Action *HostAction) override {
+ActionBuilderReturnCode addDeviceDependences(Action *HostAction) override {
   // While generating code for CUDA, we only depend on the host input 
action
   // to trigger the creation of all the CUDA device actions.
 
@@ -3600,7 +3600,7 @@
   if (!SB->isValid())
 continue;
 
-  auto RetCode = SB->addDeviceDepences(HostAction);
+  auto RetCode = SB->addDeviceDependences(HostAction);
 
   // Host dependences for device actions are not compatible with that same
   // action being ignored.


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -2733,7 +2733,7 @@
 
 /// Update the state to include the provided host action \a HostAction as a
 /// dependency of the current device action. By default it is inactive.
-virtual ActionBuilderReturnCode addDeviceDepences(Action *HostAction) {
+virtual ActionBuilderReturnCode addDeviceDependences(Action *HostAction) {
   return ABRT_Inactive;
 }
 
@@ -2821,7 +2821,7 @@
   Action::OffloadKind OFKind)
 : DeviceActionBuilder(C, Args, Inputs, OFKind) {}
 
-ActionBuilderReturnCode addDeviceDepences(Action *HostAction) override {
+ActionBuilderReturnCode addDeviceDependences(Action *HostAction) override {
   // While generating code for CUDA, we only depend on the host input action
   // to trigger the creation of all the CUDA device actions.
 
@@ -3600,7 +3600,7 @@
   if (!SB->isValid())
 continue;
 
-  auto RetCode = SB->addDeviceDepences(HostAction);
+  auto RetCode = SB->addDeviceDependences(HostAction);
 
   // Host dependences for device actions are not compatible with that same
   // action being ignored.
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[PATCH] D134007: [Clang][CUDA][NFC] Rename 'addDeviceDepences' to 'addDeviceDependences' in DeviceActionBuilder.

[WangLian via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5ed25e4df6a7: [CUDA][NFC] Rename 
'addDeviceDepences' to 'addDeviceDependences' in… (authored 
by Jimerlife).

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Files:
  clang/lib/Driver/Driver.cpp


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -2736,7 +2736,7 @@
 
 /// Update the state to include the provided host action \a HostAction as a
 /// dependency of the current device action. By default it is inactive.
-virtual ActionBuilderReturnCode addDeviceDepences(Action *HostAction) {
+virtual ActionBuilderReturnCode addDeviceDependences(Action *HostAction) {
   return ABRT_Inactive;
 }
 
@@ -2824,7 +2824,7 @@
   Action::OffloadKind OFKind)
 : DeviceActionBuilder(C, Args, Inputs, OFKind) {}
 
-ActionBuilderReturnCode addDeviceDepences(Action *HostAction) override {
+ActionBuilderReturnCode addDeviceDependences(Action *HostAction) override {
   // While generating code for CUDA, we only depend on the host input 
action
   // to trigger the creation of all the CUDA device actions.
 
@@ -3603,7 +3603,7 @@
   if (!SB->isValid())
 continue;
 
-  auto RetCode = SB->addDeviceDepences(HostAction);
+  auto RetCode = SB->addDeviceDependences(HostAction);
 
   // Host dependences for device actions are not compatible with that same
   // action being ignored.


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -2736,7 +2736,7 @@
 
 /// Update the state to include the provided host action \a HostAction as a
 /// dependency of the current device action. By default it is inactive.
-virtual ActionBuilderReturnCode addDeviceDepences(Action *HostAction) {
+virtual ActionBuilderReturnCode addDeviceDependences(Action *HostAction) {
   return ABRT_Inactive;
 }
 
@@ -2824,7 +2824,7 @@
   Action::OffloadKind OFKind)
 : DeviceActionBuilder(C, Args, Inputs, OFKind) {}
 
-ActionBuilderReturnCode addDeviceDepences(Action *HostAction) override {
+ActionBuilderReturnCode addDeviceDependences(Action *HostAction) override {
   // While generating code for CUDA, we only depend on the host input action
   // to trigger the creation of all the CUDA device actions.
 
@@ -3603,7 +3603,7 @@
   if (!SB->isValid())
 continue;
 
-  auto RetCode = SB->addDeviceDepences(HostAction);
+  auto RetCode = SB->addDeviceDependences(HostAction);
 
   // Host dependences for device actions are not compatible with that same
   // action being ignored.
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[PATCH] D145146: [Driver][NFC] Remove some redundant code in Driver.cpp.

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`options::OPT_target` has been done in `Driver::BuildCompilation`, so I think 
this part of code is redundant.


Repository:
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Files:
  clang/lib/Driver/Driver.cpp


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -527,10 +527,6 @@
 StringRef TargetTriple,
 const ArgList &Args,
 StringRef DarwinArchName = "") {
-  // FIXME: Already done in Compilation *Driver::BuildCompilation
-  if (const Arg *A = Args.getLastArg(options::OPT_target))
-TargetTriple = A->getValue();
-
   llvm::Triple Target(llvm::Triple::normalize(TargetTriple));
 
   // GNU/Hurd's triples should have been -hurd-gnu*, but were historically made


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -527,10 +527,6 @@
 StringRef TargetTriple,
 const ArgList &Args,
 StringRef DarwinArchName = "") {
-  // FIXME: Already done in Compilation *Driver::BuildCompilation
-  if (const Arg *A = Args.getLastArg(options::OPT_target))
-TargetTriple = A->getValue();
-
   llvm::Triple Target(llvm::Triple::normalize(TargetTriple));
 
   // GNU/Hurd's triples should have been -hurd-gnu*, but were historically made
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[PATCH] D145146: [Driver][NFC] Remove some redundant code in Driver.cpp.

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Jimerlife added a comment.

ping...


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[PATCH] D118011: [RISCV] Adjust predicates and update intrinsic for clmul and clmulh in Zbkc extension

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Jimerlife updated this revision to Diff 402414.
Jimerlife retitled this revision from "[RISCV][NFC] Add "zbkc" predicate for 
clmul and clmulh pattern" to "[RISCV] Adjust predicates and update intrinsic 
for clmul and clmulh in Zbkc extension ".
Jimerlife edited the summary of this revision.
Jimerlife added a reviewer: kito-cheng.
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1. Add IR tests for clmul and clmulh in zbkc extension.
2. Updating BuiltinsRISCV.def, I rename "__builtin__riscv__clmul" to 
"__builtin_riscv_clmul_kc" in zbkc extension, because cannot share same name 
"__builtin__riscv_clmul" in zbc and zbkc extension.
3. Add C tests for clmul and clmulh in zbkc extension


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBC
+; RUN: llc -mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBKC
+
+declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+
+define i64 @clmul64(i64 %a, i64 %b) nounwind {
+; RV64ZBC-LABEL: clmul64:
+; RV64ZBC:   # %bb.0:
+; RV64ZBC-NEXT:clmul a0, a0, a1
+; RV64ZBC-NEXT:ret
+;
+; RV64ZBKC-LABEL: clmul64:
+; RV64ZBKC:   # %bb.0:
+; RV64ZBKC-NEXT:clmul a0, a0, a1
+; RV64ZBKC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+
+define i64 @clmul64h(i64 %a, i64 %b) nounwind {
+; RV64ZBC-LABEL: clmul64h:
+; RV64ZBC:   # %bb.0:
+; RV64ZBC-NEXT:clmulh a0, a0, a1
+; RV64ZBC-NEXT:ret
+;
+; RV64ZBKC-LABEL: clmul64h:
+; RV64ZBKC:   # %bb.0:
+; RV64ZBKC-NEXT:clmulh a0, a0, a1
+; RV64ZBKC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBC
+; RUN: llc -mtriple=riscv32 -mattr=+zbkc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBKC
+
+declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+
+define i32 @clmul32(i32 %a, i32 %b) nounwind {
+; RV32ZBC-LABEL: clmul32:
+; RV32ZBC:   # %bb.0:
+; RV32ZBC-NEXT:clmul a0, a0, a1
+; RV32ZBC-NEXT:ret
+;
+; RV32ZBKC-LABEL: clmul32:
+; RV32ZBKC:   # %bb.0:
+; RV32ZBKC-NEXT:clmul a0, a0, a1
+; RV32ZBKC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+
+define i32 @clmul32h(i32 %a, i32 %b) nounwind {
+; RV32ZBC-LABEL: clmul32h:
+; RV32ZBC:   # %bb.0:
+; RV32ZBC-NEXT:clmulh a0, a0, a1
+; RV32ZBC-NEXT:ret
+;
+; RV32ZBKC-LABEL: clmul32h:
+; RV32ZBKC:   # %bb.0:
+; RV32ZBKC-NEXT:clmulh a0, a0, a1
+; RV32ZBKC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1131,11 +1131,13 @@
   (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
-let Predicates = [HasStdExtZbc] in {
+let Predicates = [HasStdExtZbcOrZbkc] in {
 def : PatGprGpr;
 def : PatGprGpr;
+} // Predicates = [HasStdExtZbcOrZbkc]
+
+let Predicates = [HasStdExtZbc] in
 def : PatGprGpr;
-} // Predicates = [HasStdExtZbc]
 
 let Predicates = [HasStdExtZbe] in {
 def : PatGprGpr;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -88,9 +88,11 @@
   // Zbb
   def int_riscv_orc_b : BitManipGPRIntrinsics;
 
-  // Zbc
+  // ZbcorZbkc
   def int_riscv_clmul  : BitManipGPRGPRIntrinsics;
   def int_risc

[PATCH] D118011: [RISCV] Adjust predicates and update intrinsic for clmul and clmulh in Zbkc extension

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Jimerlife added a comment.

In D118011#3265071 , @craig.topper 
wrote:

> Will you also be updating clang's RISCVBuiltins.def?
>
> Can you add tests?

I update BuiltinsRISCV.def and add "__builtin_riscv_clmul_kc" intrinsic for 
zbkc extension, but I am not sure if the name is  appropriate.


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[PATCH] D118011: [RISCV] Adjust predicates and update intrinsic for clmul and clmulh in Zbkc extension

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Jimerlife added a comment.

In D118011#3265069 , @kito-cheng 
wrote:

> Actually this patch is NOT NFC, you fixed an issue that is: `zbkc` isn't 
> include `cmul` and `clmulh`.
>
> So I would suggest you:
>
> 1. Remove NFC from the title.
> 2. Add test case to test `cmul` and `clmulh` is available for `zbkc` after 
> this patch.

Thank you. I adjust patch according your suggestions.


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[PATCH] D118011: [RISCV] Adjust predicates and update intrinsic for clmul and clmulh in Zbkc extension

[WangLian via Phabricator via cfe-commits]

Jimerlife updated this revision to Diff 402426.
Jimerlife added a comment.

add spaces around "or"


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBC
+; RUN: llc -mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBKC
+
+declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+
+define i64 @clmul64(i64 %a, i64 %b) nounwind {
+; RV64ZBC-LABEL: clmul64:
+; RV64ZBC:   # %bb.0:
+; RV64ZBC-NEXT:clmul a0, a0, a1
+; RV64ZBC-NEXT:ret
+;
+; RV64ZBKC-LABEL: clmul64:
+; RV64ZBKC:   # %bb.0:
+; RV64ZBKC-NEXT:clmul a0, a0, a1
+; RV64ZBKC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+
+define i64 @clmul64h(i64 %a, i64 %b) nounwind {
+; RV64ZBC-LABEL: clmul64h:
+; RV64ZBC:   # %bb.0:
+; RV64ZBC-NEXT:clmulh a0, a0, a1
+; RV64ZBC-NEXT:ret
+;
+; RV64ZBKC-LABEL: clmul64h:
+; RV64ZBKC:   # %bb.0:
+; RV64ZBKC-NEXT:clmulh a0, a0, a1
+; RV64ZBKC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBC
+; RUN: llc -mtriple=riscv32 -mattr=+zbkc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBKC
+
+declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+
+define i32 @clmul32(i32 %a, i32 %b) nounwind {
+; RV32ZBC-LABEL: clmul32:
+; RV32ZBC:   # %bb.0:
+; RV32ZBC-NEXT:clmul a0, a0, a1
+; RV32ZBC-NEXT:ret
+;
+; RV32ZBKC-LABEL: clmul32:
+; RV32ZBKC:   # %bb.0:
+; RV32ZBKC-NEXT:clmul a0, a0, a1
+; RV32ZBKC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+
+define i32 @clmul32h(i32 %a, i32 %b) nounwind {
+; RV32ZBC-LABEL: clmul32h:
+; RV32ZBC:   # %bb.0:
+; RV32ZBC-NEXT:clmulh a0, a0, a1
+; RV32ZBC-NEXT:ret
+;
+; RV32ZBKC-LABEL: clmul32h:
+; RV32ZBKC:   # %bb.0:
+; RV32ZBKC-NEXT:clmulh a0, a0, a1
+; RV32ZBKC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1131,11 +1131,13 @@
   (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
-let Predicates = [HasStdExtZbc] in {
+let Predicates = [HasStdExtZbcOrZbkc] in {
 def : PatGprGpr;
 def : PatGprGpr;
+} // Predicates = [HasStdExtZbcOrZbkc]
+
+let Predicates = [HasStdExtZbc] in
 def : PatGprGpr;
-} // Predicates = [HasStdExtZbc]
 
 let Predicates = [HasStdExtZbe] in {
 def : PatGprGpr;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -88,9 +88,11 @@
   // Zbb
   def int_riscv_orc_b : BitManipGPRIntrinsics;
 
-  // Zbc
+  // Zbc or Zbkc
   def int_riscv_clmul  : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
+
+  // Zbc
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
   // Zbe
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN: | FileCheck %s  -check-prefix=RV64ZBKC
+
+// RV64ZBKC-LABEL: @clmul(
+// RV64ZBKC-NEXT:  entry:
+// RV64ZBKC-NEXT:[[A_ADDR:%.*]] = al

[PATCH] D116994: [RISCV] Add bfp and bfpw intrinsic in zbf extension

[WangLian via Phabricator via cfe-commits]

Jimerlife created this revision.
Jimerlife added reviewers: craig.topper, benshi001, asb, LevyHsu.
Jimerlife added a project: LLVM.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, hiraditya.
Jimerlife requested review of this revision.
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bfp
bfpw


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116994

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBF
+
+declare i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+
+define i64 @bfp64(i64 %a, i64 %b) nounwind {
+; RV64ZBF-LABEL: bfp64:
+; RV64ZBF:   # %bb.0:
+; RV64ZBF-NEXT:bfp a0, a0, a1
+; RV64ZBF-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bfpw.i64(i64 %a, i64 %b)
+
+define i64 @bfpw64(i64 %a, i64 %b) nounwind {
+; RV64ZBF-LABEL: bfpw64:
+; RV64ZBF:   # %bb.0:
+; RV64ZBF-NEXT:bfpw a0, a0, a1
+; RV64ZBF-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bfpw.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBF
+
+declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+
+define i32 @bfp32(i32 %a, i32 %b) nounwind {
+; RV32ZBF-LABEL: bfp32:
+; RV32ZBF:   # %bb.0:
+; RV32ZBF-NEXT:bfp a0, a0, a1
+; RV32ZBF-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1127,3 +1127,9 @@
 def : PatGpr;
 def : PatGpr;
 } // Predicates = [HasStdExtZbr, IsRV64]
+
+let Predicates = [HasStdExtZbf] in
+def : PatGprGpr;
+
+let Predicates = [HasStdExtZbf, IsRV64] in
+def : PatGprGpr;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -93,6 +93,10 @@
   def int_riscv_bcompress   : BitManipGPRGPRIntrinsics;
   def int_riscv_bdecompress : BitManipGPRGPRIntrinsics;
 
+  // Zbf
+  def int_riscv_bfp  : BitManipGPRGPRIntrinsics;
+  def int_riscv_bfpw : BitManipGPRGPRIntrinsics;
+
   // Zbp
   def int_riscv_grev  : BitManipGPRGPRIntrinsics;
   def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbf -emit-llvm %s -o - \
+// RUN: | FileCheck %s  -check-prefix=RV64ZBF
+
+// RV64ZBF-LABEL: @bfp(
+// RV64ZBF-NEXT:  entry:
+// RV64ZBF-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT:[[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBF-NEXT:store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBF-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBF-NEXT:[[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBF-NEXT:[[TMP2:%.*]] = call i64 @llvm.riscv.bfp.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBF-NEXT:ret i64 [[TMP2]]
+//
+long bfp(long a, long b) {
+  return __builtin_riscv_bfp(a, b);
+}
+
+// RV64ZBF-LABEL: @bfpw(
+// RV64ZBF-NEXT:  entry:
+// RV64ZBF-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT:[[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEX

[PATCH] D116994: [RISCV] Add bfp and bfpw intrinsic in zbf extension

[WangLian via Phabricator via cfe-commits]

Jimerlife updated this revision to Diff 399216.
Jimerlife edited the summary of this revision.
Jimerlife added a comment.

According to machine target, write two intrinsic __builtin_riscv_bfp_rv32 and 
__builtin_riscv_bfp_rv64.
Support __builtin_riscv_bfp_rv32 used in RV64 target.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116994/new/

https://reviews.llvm.org/D116994

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBF
+
+declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+
+define i32 @bfp32(i32 %a, i32 %b) nounwind {
+; RV64ZBF-LABEL: bfp32:
+; RV64ZBF:   # %bb.0:
+; RV64ZBF-NEXT:bfpw a0, a0, a1
+; RV64ZBF-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+
+define i64 @bfp64(i64 %a, i64 %b) nounwind {
+; RV64ZBF-LABEL: bfp64:
+; RV64ZBF:   # %bb.0:
+; RV64ZBF-NEXT:bfp a0, a0, a1
+; RV64ZBF-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBF
+
+declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+
+define i32 @bfp32(i32 %a, i32 %b) nounwind {
+; RV32ZBF-LABEL: bfp32:
+; RV32ZBF:   # %bb.0:
+; RV32ZBF-NEXT:bfp a0, a0, a1
+; RV32ZBF-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -43,6 +43,8 @@
 def riscv_shflw  : SDNode<"RISCVISD::SHFLW",  SDT_RISCVIntBinOpW>;
 def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
 def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
+def riscv_bfp: SDNode<"RISCVISD::BFP",SDTIntBinOp>;
+def riscv_bfpw   : SDNode<"RISCVISD::BFPW",   SDT_RISCVIntBinOpW>;
 def riscv_bcompress: SDNode<"RISCVISD::BCOMPRESS",   SDTIntBinOp>;
 def riscv_bcompressw   : SDNode<"RISCVISD::BCOMPRESSW",  SDT_RISCVIntBinOpW>;
 def riscv_bdecompress  : SDNode<"RISCVISD::BDECOMPRESS", SDTIntBinOp>;
@@ -1127,3 +1129,9 @@
 def : PatGpr;
 def : PatGpr;
 } // Predicates = [HasStdExtZbr, IsRV64]
+
+let Predicates = [HasStdExtZbf] in
+def : PatGprGpr;
+
+let Predicates = [HasStdExtZbf, IsRV64] in
+def : PatGprGpr;
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -120,6 +120,13 @@
   BCOMPRESSW,
   BDECOMPRESS,
   BDECOMPRESSW,
+  // The bit field place (bfp) instruction places up to XLEN/2 LSB bits from rs2
+  // into the value in rs1. The upper bits of rs2 control the length of the bit
+  // field and target position. The layout of rs2 is chosen in a way that makes
+  // it possible to construct rs2 easily using pack[h] instructions and/or
+  // andi/lui.
+  BFP,
+  BFPW,
   // Vector Extension
   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
   // for the VL value to be used for the operation.
@@ -361,8 +368,7 @@
 const APInt &DemandedElts,
 TargetLoweringOpt &TLO) const override;
 
-  void computeKnownBitsForTargetNode(const SDValue Op,
- KnownBits &Known,
+  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
  const APInt &DemandedElts,
  const SelectionDAG &DAG,
  unsigned Depth) const override;
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
==

[PATCH] D116994: [RISCV] Add bfp and bfpw intrinsic in zbf extension

[WangLian via Phabricator via cfe-commits]

Jimerlife added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:36
 
+// zbf extension
+TARGET_BUILTIN(__builtin_riscv_bfp, "LiLiLi", "nc", "experimental-zbf")

craig.topper wrote:
> Capital Z
done



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:37
+// zbf extension
+TARGET_BUILTIN(__builtin_riscv_bfp, "LiLiLi", "nc", "experimental-zbf")
+TARGET_BUILTIN(__builtin_riscv_bfpw, "WiWiWi", "nc", "experimental-zbf,64bit")

craig.topper wrote:
> I think we should have `__builtin_riscv_bfp_32` and `__builtin_riscv_bfp_64`. 
> It's more convenient and portable for software to be written in terms of 
> number of bits being operated on rather than changing behavior based on xlen.
I have rewrite two intrinsics according to target machine



Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:98
+  def int_riscv_bfp  : BitManipGPRGPRIntrinsics;
+  def int_riscv_bfpw : BitManipGPRGPRIntrinsics;
+

craig.topper wrote:
> We only need one intrinsic. `BitManipGPRGPRIntrinsics` is type overloaded. We 
> can check the type in isel patterns.
Only save one intrinsic pattern.


Repository:
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[PATCH] D116994: [RISCV] Add bfp and bfpw intrinsic in zbf extension

[WangLian via Phabricator via cfe-commits]

Jimerlife updated this revision to Diff 399281.
Jimerlife added a comment.
Herald added a subscriber: jacquesguan.

format code


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116994/new/

https://reviews.llvm.org/D116994

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBF
+
+declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+
+define i32 @bfp32(i32 %a, i32 %b) nounwind {
+; RV64ZBF-LABEL: bfp32:
+; RV64ZBF:   # %bb.0:
+; RV64ZBF-NEXT:bfpw a0, a0, a1
+; RV64ZBF-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+
+define i64 @bfp64(i64 %a, i64 %b) nounwind {
+; RV64ZBF-LABEL: bfp64:
+; RV64ZBF:   # %bb.0:
+; RV64ZBF-NEXT:bfp a0, a0, a1
+; RV64ZBF-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBF
+
+declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+
+define i32 @bfp32(i32 %a, i32 %b) nounwind {
+; RV32ZBF-LABEL: bfp32:
+; RV32ZBF:   # %bb.0:
+; RV32ZBF-NEXT:bfp a0, a0, a1
+; RV32ZBF-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -43,6 +43,8 @@
 def riscv_shflw  : SDNode<"RISCVISD::SHFLW",  SDT_RISCVIntBinOpW>;
 def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
 def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
+def riscv_bfp: SDNode<"RISCVISD::BFP",SDTIntBinOp>;
+def riscv_bfpw   : SDNode<"RISCVISD::BFPW",   SDT_RISCVIntBinOpW>;
 def riscv_bcompress: SDNode<"RISCVISD::BCOMPRESS",   SDTIntBinOp>;
 def riscv_bcompressw   : SDNode<"RISCVISD::BCOMPRESSW",  SDT_RISCVIntBinOpW>;
 def riscv_bdecompress  : SDNode<"RISCVISD::BDECOMPRESS", SDTIntBinOp>;
@@ -1127,3 +1129,9 @@
 def : PatGpr;
 def : PatGpr;
 } // Predicates = [HasStdExtZbr, IsRV64]
+
+let Predicates = [HasStdExtZbf] in
+def : PatGprGpr;
+
+let Predicates = [HasStdExtZbf, IsRV64] in
+def : PatGprGpr;
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -120,6 +120,13 @@
   BCOMPRESSW,
   BDECOMPRESS,
   BDECOMPRESSW,
+  // The bit field place (bfp) instruction places up to XLEN/2 LSB bits from rs2
+  // into the value in rs1. The upper bits of rs2 control the length of the bit
+  // field and target position. The layout of rs2 is chosen in a way that makes
+  // it possible to construct rs2 easily using pack[h] instructions and/or
+  // andi/lui.
+  BFP,
+  BFPW,
   // Vector Extension
   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
   // for the VL value to be used for the operation.
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4185,6 +4185,9 @@
: RISCVISD::BDECOMPRESS;
 return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
   }
+  case Intrinsic::riscv_bfp:
+return DAG.getNode(RISCVISD::BFP, DL, XLenVT, Op.getOperand(1),
+   Op.getOperand(2));
   case Intrinsic::riscv_vmv_x_s:
 assert(Op.getValueType() == XLenVT && "Unexpected VT!");
 return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
@@ -6275,6 +6278,17 @@
   Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
   break;