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bfp
bfpw
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D116994
Files:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
Index: llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64ZBF
+
+declare i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+
+define i64 @bfp64(i64 %a, i64 %b) nounwind {
+; RV64ZBF-LABEL: bfp64:
+; RV64ZBF: # %bb.0:
+; RV64ZBF-NEXT: bfp a0, a0, a1
+; RV64ZBF-NEXT: ret
+ %tmp = call i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bfpw.i64(i64 %a, i64 %b)
+
+define i64 @bfpw64(i64 %a, i64 %b) nounwind {
+; RV64ZBF-LABEL: bfpw64:
+; RV64ZBF: # %bb.0:
+; RV64ZBF-NEXT: bfpw a0, a0, a1
+; RV64ZBF-NEXT: ret
+ %tmp = call i64 @llvm.riscv.bfpw.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32ZBF
+
+declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+
+define i32 @bfp32(i32 %a, i32 %b) nounwind {
+; RV32ZBF-LABEL: bfp32:
+; RV32ZBF: # %bb.0:
+; RV32ZBF-NEXT: bfp a0, a0, a1
+; RV32ZBF-NEXT: ret
+ %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1127,3 +1127,9 @@
def : PatGpr<int_riscv_crc32_d, CRC32D>;
def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
} // Predicates = [HasStdExtZbr, IsRV64]
+
+let Predicates = [HasStdExtZbf] in
+def : PatGprGpr<int_riscv_bfp, BFP>;
+
+let Predicates = [HasStdExtZbf, IsRV64] in
+def : PatGprGpr<int_riscv_bfpw, BFPW>;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -93,6 +93,10 @@
def int_riscv_bcompress : BitManipGPRGPRIntrinsics;
def int_riscv_bdecompress : BitManipGPRGPRIntrinsics;
+ // Zbf
+ def int_riscv_bfp : BitManipGPRGPRIntrinsics;
+ def int_riscv_bfpw : BitManipGPRGPRIntrinsics;
+
// Zbp
def int_riscv_grev : BitManipGPRGPRIntrinsics;
def int_riscv_gorc : BitManipGPRGPRIntrinsics;
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbf -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZBF
+
+// RV64ZBF-LABEL: @bfp(
+// RV64ZBF-NEXT: entry:
+// RV64ZBF-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBF-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBF-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBF-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBF-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.bfp.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBF-NEXT: ret i64 [[TMP2]]
+//
+long bfp(long a, long b) {
+ return __builtin_riscv_bfp(a, b);
+}
+
+// RV64ZBF-LABEL: @bfpw(
+// RV64ZBF-NEXT: entry:
+// RV64ZBF-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBF-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBF-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBF-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBF-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.bfpw.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBF-NEXT: ret i64 [[TMP2]]
+//
+long bfpw(long a, long b) {
+ return __builtin_riscv_bfpw(a, b);
+}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c
@@ -0,0 +1,18 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbf -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBF
+
+// RV32ZBF-LABEL: @bfp(
+// RV32ZBF-NEXT: entry:
+// RV32ZBF-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBF-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBF-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBF-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBF-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBF-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBF-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bfp.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBF-NEXT: ret i32 [[TMP2]]
+//
+long bfp(long a, long b) {
+ return __builtin_riscv_bfp(a, b);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18826,6 +18826,8 @@
case RISCV::BI__builtin_riscv_bcompress_64:
case RISCV::BI__builtin_riscv_bdecompress_32:
case RISCV::BI__builtin_riscv_bdecompress_64:
+ case RISCV::BI__builtin_riscv_bfp:
+ case RISCV::BI__builtin_riscv_bfpw:
case RISCV::BI__builtin_riscv_grev_32:
case RISCV::BI__builtin_riscv_grev_64:
case RISCV::BI__builtin_riscv_gorc_32:
@@ -18875,6 +18877,14 @@
ID = Intrinsic::riscv_bdecompress;
break;
+ // Zbf
+ case RISCV::BI__builtin_riscv_bfp:
+ ID = Intrinsic::riscv_bfp;
+ break;
+ case RISCV::BI__builtin_riscv_bfpw:
+ ID = Intrinsic::riscv_bfpw;
+ break;
+
// Zbp
case RISCV::BI__builtin_riscv_grev_32:
case RISCV::BI__builtin_riscv_grev_64:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===================================================================
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -33,6 +33,10 @@
TARGET_BUILTIN(__builtin_riscv_bdecompress_64, "WiWiWi", "nc",
"experimental-zbe,64bit")
+// zbf extension
+TARGET_BUILTIN(__builtin_riscv_bfp, "LiLiLi", "nc", "experimental-zbf")
+TARGET_BUILTIN(__builtin_riscv_bfpw, "WiWiWi", "nc", "experimental-zbf,64bit")
+
// Zbp extension
TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp")
TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit")
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