[clang] [llvm] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
wangpc-pp wrote: As @kito-cheng has pointed out, we should fix multilib issue before landing this. It seems we don't generate multilib for ilp32f and lp64f in riscv-gnu-toolchain? https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)
wangpc-pp wrote: Please reorginize the patch as @dtcxzyw suggested. :-) I didn't notice this extension before, so I may not be asking the right question here: These MOPs can be redefined, then, are we able to schedule them in compiler? Becase we don't know the cost of MOPs if we don't know how MOPs are used. For example, MOPs can be redefined as simple ALU instructions, or, it can be instructions with large cost like DIV/REM. I don't know how to model it now, but I don't think defining Sched resources for MOPs is the right way. https://github.com/llvm/llvm-project/pull/74824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)
wangpc-pp wrote: > Please reorganize the patch as @dtcxzyw suggested. :-) > > I didn't notice this extension before, so I may not be asking the right > question here: These MOPs can be redefined, then, are we able to schedule > them in compiler? Becase we don't know the cost of MOPs if we don't know how > MOPs are used. For example, MOPs can be redefined as simple ALU instructions, > or, it can be instructions with large cost like DIV/REM. I don't know how to > model it now, but I don't think defining Sched resources for MOPs is the > right way. Just checked similar extensions in ARM (like AUT, PAC, BTI, etc.), these extensions are defined in NOP encoding space and their schedule resources will be overrided by `InstRW`. https://github.com/llvm/llvm-project/pull/74824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Update the interface of sifive vqmaccqoq (PR #74284)
@@ -130,18 +138,18 @@ multiclass RVVVFNRCLIPBuiltinSet;
-defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
-defm sf_vqmaccus_2x8x2 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
-defm sf_vqmaccsu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
+defm sf_vqmaccu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v",
"vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
+defm sf_vqmacc_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v",
"vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
+defm sf_vqmaccus_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v",
"vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
+defm sf_vqmaccsu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v",
"vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
}
let UnMaskedPolicyScheme = HasPolicyOperand in
let RequiredFeatures = ["Xsfvqmaccqoq"] in {
-defm sf_vqmaccu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
-defm sf_vqmacc_4x8x4 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
-defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
-defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
+defm sf_vqmaccu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w",
"ww(FixedSEW:8)SUv(FixedSEW:8)Uw"]]>;
wangpc-pp wrote:
It causes assertion `VTM == VectorTypeModifier::NoModifier &&
"VectorTypeModifier should only have one modifier"`.
https://github.com/llvm/llvm-project/pull/74284
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[clang] [RISCV][NFC] Use AddTargetFeature to add fast-unaligned-access (PR #74280)
wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/74280 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][NFC] Use AddTargetFeature to add fast-unaligned-access (PR #74280)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/74280 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [libcxx] [llvm] [compiler-rt] [libc] [flang] [clang] [RISCV][MC] Add support for experimental Zimop extension (PR #75182)
https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/75182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)
wangpc-pp wrote: Add test in `clang/test/Driver/riscv-cpus.c`? https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)
@@ -222,6 +222,11 @@ // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s wangpc-pp wrote: Are there any `experimental` extensions? https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add sifive-p450 CPU. (PR #75760)
@@ -222,6 +222,11 @@ // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s +// MCPU-SIFIVE-P450: "-nostdsysteminc" "-target-cpu" "sifive-p450" +// MCPU-SIFIVE-P450-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintntl" "-target-feature" "+zihintpause" "-target-feature" "+zihpm" "-target-feature" "+zfhmin" "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbs" "-target-feature" "- wangpc-pp wrote: Why does this line end with `"-`? Copy/paste mistake? And this line is too long, please add some line breaks. https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)
@@ -222,6 +222,11 @@ // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s +// MCPU-SIFIVE-P450: "-nostdsysteminc" "-target-cpu" "sifive-p450" +// MCPU-SIFIVE-P450-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintntl" "-target-feature" "+zihintpause" "-target-feature" "+zihpm" "-target-feature" "+zfhmin" "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbs" "-target-feature" "- wangpc-pp wrote: I prefer to the form of `veyron-v1` test that there is exactly one line for one feature. We can just test features specified in `RISCVProcessorModel` definitions in `RISCVProcessors.td`. As for implied features, we can ignore them as there are test coverage in other tests and this is not the purpose of `riscv-cpus.c` I think. https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add sifive-p450 CPU. (PR #75760)
@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, [TuneSiFive7, TuneDLenFactor2]>; +def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel, + [Feature64Bit, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicbop, + FeatureStdExtZicbom, + FeatureStdExtZicboz, + FeatureStdExtZihintntl, + FeatureStdExtZihintpause, + FeatureStdExtZihpm, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZfhmin]>; + wangpc-pp wrote: I don't find the supported ISA description in datasheet, so I wonder if it's true that only `Zfhmin` is implemented. Should it be `Zfh`? https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add sifive-p450 CPU. (PR #75760)
https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)
https://github.com/wangpc-pp approved this pull request. I have similar patch before: https://reviews.llvm.org/D125947, so it LGTM as GCC's default behavior has changed. :-) But please wait for others' opinions. https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)
wangpc-pp wrote: > short version: GCC isn't change. long version: GCC's configure script isn't > change, it's configure script in riscv-gnu-toolchain So why is there a difference between GCC and riscv-gnu-toolchain? If we set `with_abi` to lp64f, what is the behavior? > > But I don't have strong opinion on this change since I believe user should > explicitly specify that, otherwise it's really to screw up to select > multi-lib or portability issue between different compilers. https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)
https://github.com/wangpc-pp approved this pull request. LGTM with nit. https://github.com/llvm/llvm-project/pull/73971 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/73971 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)
@@ -171,18 +171,12 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("-save-restore");
// -mno-unaligned-access is default, unless -munaligned-access is specified.
- bool HasV = llvm::is_contained(Features, "+zve32x");
if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
wangpc-pp wrote:
This whole sippet can be replaced by `tools::AddTargetFeature`.
https://github.com/llvm/llvm-project/pull/73971
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[clang] [clang][RISCVVEmitter] Remove no-op ptr-to-ptr bitcast (NFC) (PR #74179)
@@ -180,13 +180,10 @@ void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI,
raw_ostream &OS) {
return;
}
- // Cast pointer operand of vector load intrinsic.
for (const auto &I : enumerate(RVVI->getInputTypes())) {
wangpc-pp wrote:
Why not remove this `for` totally?
https://github.com/llvm/llvm-project/pull/74179
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[clang] [RISCV][NFC] Use AddTargetFeature to add fast-unaligned-access (PR #74280)
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/74280
We can reduce some code.
>From 1a9364a8b1e0eae320774253ac98a445daf7ec9f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 4 Dec 2023 14:11:19 +0800
Subject: [PATCH] [RISCV][NFC] Use AddTargetFeature to add
fast-unaligned-access
We can reduce some code.
---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 5d990ba78e5cc..0b696111e7d71 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -171,13 +171,8 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("-save-restore");
// -mno-unaligned-access is default, unless -munaligned-access is specified.
- if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
- options::OPT_mno_unaligned_access)) {
-if (A->getOption().matches(options::OPT_munaligned_access))
- Features.push_back("+fast-unaligned-access");
-else
- Features.push_back("-fast-unaligned-access");
- }
+ AddTargetFeature(Args, Features, options::OPT_munaligned_access,
+ options::OPT_mno_unaligned_access, "fast-unaligned-access");
// Now add any that the user explicitly requested on the command line,
// which may override the defaults.
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[clang] [llvm] [RFC][RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76357
This PR implements the draft
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36.
Currently, we replace specified profile in `-march` with standard
arch string.
We may need to pass it to backend so that we can emit an ELF attr
proposed by
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/409.
>From f9d4a2be0f1e1b8815d2feaebdc918d501c776da Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR implements the draft
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36.
Currently, we replace specified profile in `-march` with standard
arch string.
We may need to pass it to backend so that we can emit an ELF attr
proposed by
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/409.
---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 7 +-
clang/test/Driver/riscv-profiles.c| 79 +++
llvm/include/llvm/TargetParser/CMakeLists.txt | 1 +
.../llvm/TargetParser/RISCVTargetParser.h | 1 +
llvm/lib/Target/RISCV/RISCV.td| 6 ++
llvm/lib/Target/RISCV/RISCVProfiles.td| 70
llvm/lib/TargetParser/RISCVTargetParser.cpp | 24 ++
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 19 +
8 files changed, 205 insertions(+), 2 deletions(-)
create mode 100644 clang/test/Driver/riscv-profiles.c
create mode 100644 llvm/lib/Target/RISCV/RISCVProfiles.td
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 25b43cefce6b57..87ec51b89547c5 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -277,8 +277,11 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList
&Args,
// instead of `rv{XLEN}gc` though they are (currently) equivalent.
// 1. If `-march=` is specified, use it.
- if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
-return A->getValue();
+ if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
+StringRef Value = A->getValue();
+StringRef MArchFromProfile = llvm::RISCV::getMArchFromProfile(Value);
+return MArchFromProfile.empty() ? Value : MArchFromProfile;
+ }
// 2. Get march (isa string) based on `-mcpu=`
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
diff --git a/clang/test/Driver/riscv-profiles.c
b/clang/test/Driver/riscv-profiles.c
new file mode 100644
index 00..375d4fc10db6ca
--- /dev/null
+++ b/clang/test/Driver/riscv-profiles.c
@@ -0,0 +1,79 @@
+// RUN: %clang -### -c %s 2>&1 -march=RVI20U32 | FileCheck
-check-prefix=RVI20U32 %s
+// RVI20U32: "-target-cpu" "generic-rv32"
+// RVI20U32: "-target-feature" "-a"
+// RVI20U32: "-target-feature" "-c"
+// RVI20U32: "-target-feature" "-d"
+// RVI20U32: "-target-feature" "-f"
+// RVI20U32: "-target-feature" "-m"
+// RVI20U32: "-target-abi" "ilp32"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVI20U64 | FileCheck
-check-prefix=RVI20U64 %s
+// RVI20U64: "-target-cpu" "generic-rv64"
+// RVI20U64: "-target-feature" "-a"
+// RVI20U64: "-target-feature" "-c"
+// RVI20U64: "-target-feature" "-d"
+// RVI20U64: "-target-feature" "-f"
+// RVI20U64: "-target-feature" "-m"
+// RVI20U64: "-target-abi" "lp64"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVA20U64 | FileCheck
-check-prefix=RVA20U64 %s
+// RVA20U64: "-target-cpu" "generic-rv64"
+// RVA20U64: "-target-feature" "+m"
+// RVA20U64: "-target-feature" "+a"
+// RVA20U64: "-target-feature" "+f"
+// RVA20U64: "-target-feature" "+d"
+// RVA20U64: "-target-feature" "+c"
+// RVA20U64: "-target-feature" "+zicsr"
+// RVA20U64: "-target-abi" "lp64d"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVA20S64 | FileCheck
-check-prefix=RVA20S64 %s
+// RVA20S64: "-target-cpu" "generic-rv64"
+// RVA20S64: "-target-feature" "+m"
+// RVA20S64: "-target-feature" "+a"
+// RVA20S64: "-target-feature" "+f"
+// RVA20S64: "-target-feature" "+d"
+// RVA20S64: "-target-feature" "+c"
+// RVA20S64: "-target-feature" "+zicsr"
+// RVA20S64: "-target-feature" "+zifencei"
+// RVA20S64: "-target-abi" "lp64d"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVA22U64 | FileCheck
-check-prefix=RVA22U64 %s
+// RVA22U64: "-target-cpu" "generic-rv64"
+// RVA22U64: "-target-feature" "+m"
+// RVA22U64: "-target-feature" "+a"
+// RVA22U64: "-target-feature" "+f"
+// RVA22U64: "-target-feature" "+d"
+// RVA22U64: "-target-feature" "+c"
+// RVA22U64: "-target-feature" "+zicbom"
+// RVA22U64: "-target-feature" "+zicbop"
+// RVA22U64: "-target-feature" "+zicboz"
+// RVA22U64: "-target-feature" "+zicsr"
+// RVA22U64: "-target-feature" "+zihintpause"
+// RVA22U64: "-target-feature" "+zfhmin"
+// RVA22U64: "-target-feature" "+zba"
+// RVA22U64: "-target-feature" "+zbb"
+// RVA22U64: "-target-feature" "+zbs"
+// RVA22U64: "-target-feature" "+zkt"
+// RVA22U64: "-target-abi" "lp64d"
+
+// RUN: %
[clang] [llvm] [RFC][RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 806babf92282735c364b7ac88faa5256d04f2742 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR implements the draft
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36.
Currently, we replace specified profile in `-march` with standard
arch string.
We may need to pass it to backend so that we can emit an ELF attr
proposed by
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/409.
---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 7 +-
clang/test/Driver/riscv-profiles.c| 79 +++
llvm/include/llvm/TargetParser/CMakeLists.txt | 1 +
.../llvm/TargetParser/RISCVTargetParser.h | 1 +
llvm/lib/Target/RISCV/RISCV.td| 6 ++
llvm/lib/Target/RISCV/RISCVProfiles.td| 70
llvm/lib/TargetParser/RISCVTargetParser.cpp | 24 ++
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 19 +
8 files changed, 205 insertions(+), 2 deletions(-)
create mode 100644 clang/test/Driver/riscv-profiles.c
create mode 100644 llvm/lib/Target/RISCV/RISCVProfiles.td
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 25b43cefce6b57..87ec51b89547c5 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -277,8 +277,11 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList
&Args,
// instead of `rv{XLEN}gc` though they are (currently) equivalent.
// 1. If `-march=` is specified, use it.
- if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
-return A->getValue();
+ if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
+StringRef Value = A->getValue();
+StringRef MArchFromProfile = llvm::RISCV::getMArchFromProfile(Value);
+return MArchFromProfile.empty() ? Value : MArchFromProfile;
+ }
// 2. Get march (isa string) based on `-mcpu=`
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
diff --git a/clang/test/Driver/riscv-profiles.c
b/clang/test/Driver/riscv-profiles.c
new file mode 100644
index 00..375d4fc10db6ca
--- /dev/null
+++ b/clang/test/Driver/riscv-profiles.c
@@ -0,0 +1,79 @@
+// RUN: %clang -### -c %s 2>&1 -march=RVI20U32 | FileCheck
-check-prefix=RVI20U32 %s
+// RVI20U32: "-target-cpu" "generic-rv32"
+// RVI20U32: "-target-feature" "-a"
+// RVI20U32: "-target-feature" "-c"
+// RVI20U32: "-target-feature" "-d"
+// RVI20U32: "-target-feature" "-f"
+// RVI20U32: "-target-feature" "-m"
+// RVI20U32: "-target-abi" "ilp32"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVI20U64 | FileCheck
-check-prefix=RVI20U64 %s
+// RVI20U64: "-target-cpu" "generic-rv64"
+// RVI20U64: "-target-feature" "-a"
+// RVI20U64: "-target-feature" "-c"
+// RVI20U64: "-target-feature" "-d"
+// RVI20U64: "-target-feature" "-f"
+// RVI20U64: "-target-feature" "-m"
+// RVI20U64: "-target-abi" "lp64"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVA20U64 | FileCheck
-check-prefix=RVA20U64 %s
+// RVA20U64: "-target-cpu" "generic-rv64"
+// RVA20U64: "-target-feature" "+m"
+// RVA20U64: "-target-feature" "+a"
+// RVA20U64: "-target-feature" "+f"
+// RVA20U64: "-target-feature" "+d"
+// RVA20U64: "-target-feature" "+c"
+// RVA20U64: "-target-feature" "+zicsr"
+// RVA20U64: "-target-abi" "lp64d"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVA20S64 | FileCheck
-check-prefix=RVA20S64 %s
+// RVA20S64: "-target-cpu" "generic-rv64"
+// RVA20S64: "-target-feature" "+m"
+// RVA20S64: "-target-feature" "+a"
+// RVA20S64: "-target-feature" "+f"
+// RVA20S64: "-target-feature" "+d"
+// RVA20S64: "-target-feature" "+c"
+// RVA20S64: "-target-feature" "+zicsr"
+// RVA20S64: "-target-feature" "+zifencei"
+// RVA20S64: "-target-abi" "lp64d"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVA22U64 | FileCheck
-check-prefix=RVA22U64 %s
+// RVA22U64: "-target-cpu" "generic-rv64"
+// RVA22U64: "-target-feature" "+m"
+// RVA22U64: "-target-feature" "+a"
+// RVA22U64: "-target-feature" "+f"
+// RVA22U64: "-target-feature" "+d"
+// RVA22U64: "-target-feature" "+c"
+// RVA22U64: "-target-feature" "+zicbom"
+// RVA22U64: "-target-feature" "+zicbop"
+// RVA22U64: "-target-feature" "+zicboz"
+// RVA22U64: "-target-feature" "+zicsr"
+// RVA22U64: "-target-feature" "+zihintpause"
+// RVA22U64: "-target-feature" "+zfhmin"
+// RVA22U64: "-target-feature" "+zba"
+// RVA22U64: "-target-feature" "+zbb"
+// RVA22U64: "-target-feature" "+zbs"
+// RVA22U64: "-target-feature" "+zkt"
+// RVA22U64: "-target-abi" "lp64d"
+
+// RUN: %clang -### -c %s 2>&1 -march=RVA22S64 | FileCheck
-check-prefix=RVA22S64 %s
+// RVA22S64: "-target-cpu" "generic-rv64"
+// RVA22S64: "-target-feature" "+m"
+// RVA22S64: "-target-feature" "+a"
+// RVA22S64: "-target-feature" "+f"
+// RVA22S64: "-target-feature" "+d"
+// RVA22S64: "-target-feature" "+c"
+// RVA22S64: "-ta
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
wangpc-pp wrote: Should this be rebased on Zimop(https://github.com/llvm/llvm-project/pull/75182) commit? Though I don't know why it has been merged yet... https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
wangpc-pp wrote: It seems that the author of Zimop implementation doesn't have commit access. @yetingk Would you mind to commit it and rebase your PR on that? It will make this PR simpler. https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][NFC] Use RISCVISAInfo instead of string comparison (PR #76387)
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76387
The arch string may not start with rv32/rv64 if we have supported
profiles in `-march`.
>From ed8ebdb6f2133f84d1f5a8d2cd580dba4ceed922 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 15:58:10 +0800
Subject: [PATCH] [RISCV][NFC] Use RISCVISAInfo instead of string comparison
The arch string may not start with rv32/rv64 if we have supported
profiles in `-march`.
---
clang/lib/Driver/Driver.cpp | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index ff95c899c5f3d4..671a11f9811f5b 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -86,6 +86,7 @@
#include "llvm/Support/PrettyStackTrace.h"
#include "llvm/Support/Process.h"
#include "llvm/Support/Program.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/StringSaver.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/Support/raw_ostream.h"
@@ -670,10 +671,15 @@ static llvm::Triple computeTargetTriple(const Driver &D,
if (Args.hasArg(options::OPT_march_EQ) ||
Args.hasArg(options::OPT_mcpu_EQ)) {
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
- if (ArchName.starts_with_insensitive("rv32"))
-Target.setArch(llvm::Triple::riscv32);
- else if (ArchName.starts_with_insensitive("rv64"))
-Target.setArch(llvm::Triple::riscv64);
+ auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
+ ArchName, /*EnableExperimentalExtensions=*/true);
+ if (ISAInfo) {
+unsigned XLen = (*ISAInfo)->getXLen();
+if (XLen == 32)
+ Target.setArch(llvm::Triple::riscv32);
+else if (XLen == 64)
+ Target.setArch(llvm::Triple::riscv64);
+ }
}
}
___
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[clang] [RISCV][NFC] Use RISCVISAInfo instead of string comparison (PR #76387)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76387
>From ed8ebdb6f2133f84d1f5a8d2cd580dba4ceed922 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 15:58:10 +0800
Subject: [PATCH 1/2] [RISCV][NFC] Use RISCVISAInfo instead of string
comparison
The arch string may not start with rv32/rv64 if we have supported
profiles in `-march`.
---
clang/lib/Driver/Driver.cpp | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index ff95c899c5f3d4..671a11f9811f5b 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -86,6 +86,7 @@
#include "llvm/Support/PrettyStackTrace.h"
#include "llvm/Support/Process.h"
#include "llvm/Support/Program.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/StringSaver.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/Support/raw_ostream.h"
@@ -670,10 +671,15 @@ static llvm::Triple computeTargetTriple(const Driver &D,
if (Args.hasArg(options::OPT_march_EQ) ||
Args.hasArg(options::OPT_mcpu_EQ)) {
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
- if (ArchName.starts_with_insensitive("rv32"))
-Target.setArch(llvm::Triple::riscv32);
- else if (ArchName.starts_with_insensitive("rv64"))
-Target.setArch(llvm::Triple::riscv64);
+ auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
+ ArchName, /*EnableExperimentalExtensions=*/true);
+ if (ISAInfo) {
+unsigned XLen = (*ISAInfo)->getXLen();
+if (XLen == 32)
+ Target.setArch(llvm::Triple::riscv32);
+else if (XLen == 64)
+ Target.setArch(llvm::Triple::riscv64);
+ }
}
}
>From 24f77edf357eb5f6fef207ab79d8df725a1ec27f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 17:16:00 +0800
Subject: [PATCH 2/2] Handle the error case
---
clang/lib/Driver/Driver.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 671a11f9811f5b..a8b7d0587c2f3f 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -673,7 +673,10 @@ static llvm::Triple computeTargetTriple(const Driver &D,
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
ArchName, /*EnableExperimentalExtensions=*/true);
- if (ISAInfo) {
+ if (!ISAInfo) {
+// Ignore any error here, we assume it will be handled in another
place.
+consumeError(ISAInfo.takeError());
+ } else {
unsigned XLen = (*ISAInfo)->getXLen();
if (XLen == 32)
Target.setArch(llvm::Triple::riscv32);
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[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
wangpc-pp wrote:
Should these instructions be aliases of MOPs now?
https://github.com/llvm/llvm-project/pull/66043
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[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
wangpc-pp wrote:
Hmmm, I haven't looked at it in details, is this a document mistake? They
should have the same encoding.
https://github.com/llvm/llvm-project/pull/66043
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[llvm] [clang] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76395
This implements experimental support for the Zcmop extension as
specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.
This change adds only MC support.
>From 20fd01b09bb196cf53807b44161482d56a43920b Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 20:46:13 +0800
Subject: [PATCH] [RISCV][MC] Add support for experimental Zcmop extension
This implements experimental support for the Zcmop extension as
specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.
This change adds only MC support.
---
.../test/Preprocessor/riscv-target-features.c | 9
llvm/docs/RISCVUsage.rst | 3 ++
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td | 30 +
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++
llvm/test/MC/RISCV/rv32zcmop-invalid.s| 7
llvm/test/MC/RISCV/rvzcmop-valid.s| 42 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
10 files changed, 106 insertions(+)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td
create mode 100644 llvm/test/MC/RISCV/rv32zcmop-invalid.s
create mode 100644 llvm/test/MC/RISCV/rvzcmop-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 2111b3f1c5832b..661f1fb55159c7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -121,6 +121,7 @@
// CHECK-NOT: __riscv_zicfilp {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_zimop {{.*$}}
+// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
// CHECK-NOT: __riscv_zvbc {{.*$}}
@@ -1080,6 +1081,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
// CHECK-ZIMOP-EXT: __riscv_zimop 1000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zcmop0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv32i_zcmop0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
+// CHECK-ZCMOP-EXT: __riscv_zcmop 2000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu
-menable-experimental-extensions \
// RUN: -march=rv32iztso0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 3125f2d7c9cfdb..836a4e9ff08e55 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -224,6 +224,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zimop``
LLVM implements the `v0.1 proposed specification
`__.
+``experimental-zcmop``
+ LLVM implements the `v0.2 proposed specification
`__.
+
To use an experimental extension from `clang`, you must add
`-menable-experimental-extensions` to the command line, and specify the exact
version of the experimental extension you are using. To use an experimental
extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`,
`llvm-mc`), you must prefix the extension name with `experimental-`. Note that
you don't need to specify the version with internal tools, and shouldn't
include the `experimental-` prefix with `clang`.
Vendor Extensions
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index e71e96e3417e46..36d453a53c1057 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -191,6 +191,8 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zacas", RISCVExtensionVersion{1, 0}},
+{"zcmop", RISCVExtensionVersion{0, 2}},
+
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 4}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a6e7c15b50e978..adf3c84b586a25 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -693,6 +693,13 @@ def HasStdExtZimop :
Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
+def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop",
"HasStdExtZcmop", "true",
+ "'Zcmop' (Compressed
Ma
[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
wangpc-pp wrote:
I think I don't find any mistake, `sspush` uses `mop.rr` and `sspopchk` uses
`mop.r`.
> The 25th bit of sspopchk is 0 but but the 25th bit of all mop.r is 1.
This is wrong as it's `{ bits: 4, name: 0x7 }`, so its value is `0b0111`.
https://github.com/llvm/llvm-project/pull/66043
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[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76395
>From 20fd01b09bb196cf53807b44161482d56a43920b Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 20:46:13 +0800
Subject: [PATCH 1/3] [RISCV][MC] Add support for experimental Zcmop extension
This implements experimental support for the Zcmop extension as
specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.
This change adds only MC support.
---
.../test/Preprocessor/riscv-target-features.c | 9
llvm/docs/RISCVUsage.rst | 3 ++
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td | 30 +
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++
llvm/test/MC/RISCV/rv32zcmop-invalid.s| 7
llvm/test/MC/RISCV/rvzcmop-valid.s| 42 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
10 files changed, 106 insertions(+)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td
create mode 100644 llvm/test/MC/RISCV/rv32zcmop-invalid.s
create mode 100644 llvm/test/MC/RISCV/rvzcmop-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 2111b3f1c5832b..661f1fb55159c7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -121,6 +121,7 @@
// CHECK-NOT: __riscv_zicfilp {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_zimop {{.*$}}
+// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
// CHECK-NOT: __riscv_zvbc {{.*$}}
@@ -1080,6 +1081,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
// CHECK-ZIMOP-EXT: __riscv_zimop 1000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zcmop0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv32i_zcmop0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
+// CHECK-ZCMOP-EXT: __riscv_zcmop 2000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu
-menable-experimental-extensions \
// RUN: -march=rv32iztso0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 3125f2d7c9cfdb..836a4e9ff08e55 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -224,6 +224,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zimop``
LLVM implements the `v0.1 proposed specification
`__.
+``experimental-zcmop``
+ LLVM implements the `v0.2 proposed specification
`__.
+
To use an experimental extension from `clang`, you must add
`-menable-experimental-extensions` to the command line, and specify the exact
version of the experimental extension you are using. To use an experimental
extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`,
`llvm-mc`), you must prefix the extension name with `experimental-`. Note that
you don't need to specify the version with internal tools, and shouldn't
include the `experimental-` prefix with `clang`.
Vendor Extensions
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index e71e96e3417e46..36d453a53c1057 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -191,6 +191,8 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zacas", RISCVExtensionVersion{1, 0}},
+{"zcmop", RISCVExtensionVersion{0, 2}},
+
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 4}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a6e7c15b50e978..adf3c84b586a25 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -693,6 +693,13 @@ def HasStdExtZimop :
Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
+def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop",
"HasStdExtZcmop", "true",
+ "'Zcmop' (Compressed
May-Be-Operations)",
+ [FeatureStdExtZca]>;
+def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
+ Ass
[clang] [RISCV][NFC] Use RISCVISAInfo instead of string comparison (PR #76387)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76387
>From ed8ebdb6f2133f84d1f5a8d2cd580dba4ceed922 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 15:58:10 +0800
Subject: [PATCH 1/3] [RISCV][NFC] Use RISCVISAInfo instead of string
comparison
The arch string may not start with rv32/rv64 if we have supported
profiles in `-march`.
---
clang/lib/Driver/Driver.cpp | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index ff95c899c5f3d4..671a11f9811f5b 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -86,6 +86,7 @@
#include "llvm/Support/PrettyStackTrace.h"
#include "llvm/Support/Process.h"
#include "llvm/Support/Program.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/StringSaver.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/Support/raw_ostream.h"
@@ -670,10 +671,15 @@ static llvm::Triple computeTargetTriple(const Driver &D,
if (Args.hasArg(options::OPT_march_EQ) ||
Args.hasArg(options::OPT_mcpu_EQ)) {
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
- if (ArchName.starts_with_insensitive("rv32"))
-Target.setArch(llvm::Triple::riscv32);
- else if (ArchName.starts_with_insensitive("rv64"))
-Target.setArch(llvm::Triple::riscv64);
+ auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
+ ArchName, /*EnableExperimentalExtensions=*/true);
+ if (ISAInfo) {
+unsigned XLen = (*ISAInfo)->getXLen();
+if (XLen == 32)
+ Target.setArch(llvm::Triple::riscv32);
+else if (XLen == 64)
+ Target.setArch(llvm::Triple::riscv64);
+ }
}
}
>From 24f77edf357eb5f6fef207ab79d8df725a1ec27f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 17:16:00 +0800
Subject: [PATCH 2/3] Handle the error case
---
clang/lib/Driver/Driver.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 671a11f9811f5b..a8b7d0587c2f3f 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -673,7 +673,10 @@ static llvm::Triple computeTargetTriple(const Driver &D,
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
ArchName, /*EnableExperimentalExtensions=*/true);
- if (ISAInfo) {
+ if (!ISAInfo) {
+// Ignore any error here, we assume it will be handled in another
place.
+consumeError(ISAInfo.takeError());
+ } else {
unsigned XLen = (*ISAInfo)->getXLen();
if (XLen == 32)
Target.setArch(llvm::Triple::riscv32);
>From 9574308a1032fb4da3d5db61d144b51f832f6000 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Wed, 27 Dec 2023 14:30:00 +0800
Subject: [PATCH 3/3] Use llvm::errorToBool
---
clang/lib/Driver/Driver.cpp | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index a8b7d0587c2f3f..ed1169ac45029f 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -77,6 +77,7 @@
#include "llvm/Option/OptTable.h"
#include "llvm/Option/Option.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Error.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ExitCodes.h"
#include "llvm/Support/FileSystem.h"
@@ -673,10 +674,7 @@ static llvm::Triple computeTargetTriple(const Driver &D,
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
ArchName, /*EnableExperimentalExtensions=*/true);
- if (!ISAInfo) {
-// Ignore any error here, we assume it will be handled in another
place.
-consumeError(ISAInfo.takeError());
- } else {
+ if (!llvm::errorToBool(ISAInfo.takeError())) {
unsigned XLen = (*ISAInfo)->getXLen();
if (XLen == 32)
Target.setArch(llvm::Triple::riscv32);
___
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[clang] [RISCV][NFC] Use errorToBool (PR #76429)
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76429
To reduce calls to `consumeError`.
>From 0d8426ffb1202ceca97b25c0dd47d516c1be280e Mon Sep 17 00:00:00 2001
From: wangpc
Date: Wed, 27 Dec 2023 14:41:30 +0800
Subject: [PATCH] [RISCV][NFC] Use errorToBool
To reduce calls to `consumeError`.
---
clang/lib/Basic/Targets/RISCV.cpp | 3 +--
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++
clang/lib/Driver/ToolChains/Clang.cpp | 7 ++-
clang/lib/Driver/ToolChains/Gnu.cpp| 12
4 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 685462961ee35a..6bc57a83a2d5ae 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -416,8 +416,7 @@ static void handleFullArchString(StringRef FullArchStr,
Features.push_back("__RISCV_TargetAttrNeedOverride");
auto RII = llvm::RISCVISAInfo::parseArchString(
FullArchStr, /* EnableExperimentalExtension */ true);
- if (!RII) {
-consumeError(RII.takeError());
+ if (llvm::errorToBool(RII.takeError())) {
// Forward the invalid FullArchStr.
Features.push_back("+" + FullArchStr.str());
} else {
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 8ae47d1680bd22..0717e3b813e1e2 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -215,10 +215,8 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const
llvm::Triple &Triple) {
auto ParseResult = llvm::RISCVISAInfo::parseArchString(
Arch, /* EnableExperimentalExtension */ true);
- if (!ParseResult)
-// Ignore parsing error, just go 3rd step.
-consumeError(ParseResult.takeError());
- else
+ // Ignore parsing error, just go 3rd step.
+ if (!llvm::errorToBool(ParseResult.takeError()))
return (*ParseResult)->computeDefaultABI();
// 3. Choose a default based on the triple
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 70dc7e54aca125..acfa119805068d 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2072,12 +2072,9 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
StringRef Arch = riscv::getRISCVArch(Args, Triple);
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
Arch, /*EnableExperimentalExtensions*/ true);
-if (!ISAInfo) {
- // Ignore parsing error.
- consumeError(ISAInfo.takeError());
-} else {
+// Ignore parsing error.
+if (!errorToBool(ISAInfo.takeError()))
MinVLen = (*ISAInfo)->getMinVLen();
-}
// If the value is "zvl", use MinVLen from march. Otherwise, try to parse
// as integer as long as we have a MinVLen.
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 38361d6889a1c8..a610a94a39a2b4 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1741,11 +1741,9 @@ selectRISCVMultilib(const MultilibSet &RISCVMultilibSet,
StringRef Arch,
llvm::RISCVISAInfo::parseArchString(
Arch, /*EnableExperimentalExtension=*/true,
/*ExperimentalExtensionVersionCheck=*/false);
- if (!ParseResult) {
-// Ignore any error here, we assume it will be handled in another place.
-consumeError(ParseResult.takeError());
+ // Ignore any error here, we assume it will be handled in another place.
+ if (llvm::errorToBool(ParseResult.takeError()))
return false;
- }
auto &ISAInfo = *ParseResult;
@@ -1780,10 +1778,8 @@ selectRISCVMultilib(const MultilibSet &RISCVMultilibSet,
StringRef Arch,
llvm::RISCVISAInfo::parseArchString(
Flag, /*EnableExperimentalExtension=*/true,
/*ExperimentalExtensionVersionCheck=*/false);
- if (!MLConfigParseResult) {
-// Ignore any error here, we assume it will handled in another place.
-llvm::consumeError(MLConfigParseResult.takeError());
-
+ // Ignore any error here, we assume it will handled in another place.
+ if (llvm::errorToBool(MLConfigParseResult.takeError())) {
// We might get a parsing error if rv32e in the list, we could just
skip
// that and process the rest of multi-lib configs.
Skip = true;
___
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[clang] [RISCV][NFC] Use RISCVISAInfo instead of string comparison (PR #76387)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76387
>From ed8ebdb6f2133f84d1f5a8d2cd580dba4ceed922 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 15:58:10 +0800
Subject: [PATCH 1/4] [RISCV][NFC] Use RISCVISAInfo instead of string
comparison
The arch string may not start with rv32/rv64 if we have supported
profiles in `-march`.
---
clang/lib/Driver/Driver.cpp | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index ff95c899c5f3d4..671a11f9811f5b 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -86,6 +86,7 @@
#include "llvm/Support/PrettyStackTrace.h"
#include "llvm/Support/Process.h"
#include "llvm/Support/Program.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/StringSaver.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/Support/raw_ostream.h"
@@ -670,10 +671,15 @@ static llvm::Triple computeTargetTriple(const Driver &D,
if (Args.hasArg(options::OPT_march_EQ) ||
Args.hasArg(options::OPT_mcpu_EQ)) {
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
- if (ArchName.starts_with_insensitive("rv32"))
-Target.setArch(llvm::Triple::riscv32);
- else if (ArchName.starts_with_insensitive("rv64"))
-Target.setArch(llvm::Triple::riscv64);
+ auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
+ ArchName, /*EnableExperimentalExtensions=*/true);
+ if (ISAInfo) {
+unsigned XLen = (*ISAInfo)->getXLen();
+if (XLen == 32)
+ Target.setArch(llvm::Triple::riscv32);
+else if (XLen == 64)
+ Target.setArch(llvm::Triple::riscv64);
+ }
}
}
>From 24f77edf357eb5f6fef207ab79d8df725a1ec27f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 17:16:00 +0800
Subject: [PATCH 2/4] Handle the error case
---
clang/lib/Driver/Driver.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 671a11f9811f5b..a8b7d0587c2f3f 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -673,7 +673,10 @@ static llvm::Triple computeTargetTriple(const Driver &D,
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
ArchName, /*EnableExperimentalExtensions=*/true);
- if (ISAInfo) {
+ if (!ISAInfo) {
+// Ignore any error here, we assume it will be handled in another
place.
+consumeError(ISAInfo.takeError());
+ } else {
unsigned XLen = (*ISAInfo)->getXLen();
if (XLen == 32)
Target.setArch(llvm::Triple::riscv32);
>From 9574308a1032fb4da3d5db61d144b51f832f6000 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Wed, 27 Dec 2023 14:30:00 +0800
Subject: [PATCH 3/4] Use llvm::errorToBool
---
clang/lib/Driver/Driver.cpp | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index a8b7d0587c2f3f..ed1169ac45029f 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -77,6 +77,7 @@
#include "llvm/Option/OptTable.h"
#include "llvm/Option/Option.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Error.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ExitCodes.h"
#include "llvm/Support/FileSystem.h"
@@ -673,10 +674,7 @@ static llvm::Triple computeTargetTriple(const Driver &D,
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
ArchName, /*EnableExperimentalExtensions=*/true);
- if (!ISAInfo) {
-// Ignore any error here, we assume it will be handled in another
place.
-consumeError(ISAInfo.takeError());
- } else {
+ if (!llvm::errorToBool(ISAInfo.takeError())) {
unsigned XLen = (*ISAInfo)->getXLen();
if (XLen == 32)
Target.setArch(llvm::Triple::riscv32);
>From 0d9385c6507f8118615ac4715bba2cde1ca426ed Mon Sep 17 00:00:00 2001
From: wangpc
Date: Wed, 27 Dec 2023 15:06:58 +0800
Subject: [PATCH 4/4] Remove unnecessary include
---
clang/lib/Driver/Driver.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index ed1169ac45029f..9b2f2a37480983 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -77,7 +77,6 @@
#include "llvm/Option/OptTable.h"
#include "llvm/Option/Option.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Error.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ExitCodes.h"
#include "llvm/Support/FileSystem.h"
___
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[llvm] [clang] [RFC][RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From 965c1c682d16a3f47c563a301c89e3717bf4d1c5 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. We may need to pass it to backend so that we can emit an ELF attr proposed by https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/409. --- clang/test/Driver/riscv-profiles.c | 105 + llvm/lib/Support/RISCVISAInfo.cpp | 43 ++ llvm/lib/Target/RISCV/RISCV.td | 6 ++ llvm/lib/Target/RISCV/RISCVProfiles.td | 70 + llvm/lib/Target/RISCV/RISCVSubtarget.h | 14 5 files changed, 238 insertions(+) create mode 100644 clang/test/Driver/riscv-profiles.c create mode 100644 llvm/lib/Target/RISCV/RISCVProfiles.td diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..7f54d0d885c7d7 --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,105 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-cpu" "generic-rv64" +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" +// RVI20U32: "-target-abi" "ilp32" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-cpu" "generic-rv64" +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" +// RVI20U64: "-target-abi" "lp64" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-cpu" "generic-rv64" +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-cpu" "generic-rv64" +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-cpu" "generic-rv64" +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" +// RVA22U64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-cpu" "generic-rv64" +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+zicsr" +// RVA22S64: "-target-feature" "+zifencei" +// RVA22S64: "-target-feature" "+zihintpause" +// RVA22S64: "-target-feature" "+zfhmin" +// RVA22S64: "-target-feature" "+zba" +// RVA22S64: "-target-feature" "+zbb" +// RVA22S64: "-target-feature" "+zbs" +// RVA22S64: "-target-feature" "+zkt" +// RVA22S64: "-target-feature" "+svinval" +// RVA22S64: "-target-feature" "+svpbmt" +// RVA22S64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64_zfa | FileCheck -check-prefix=PROFILE-WITH-ADDITIONAL %s +// PROFILE-WITH-ADDITIONAL: "-target-cpu" "generic-rv64" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+m" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+a" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+f" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+d" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+c" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbom" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+z
[clang] [llvm] [RFC][RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From f4ca1ac0dedf5af0d9ddf05f7a67f30091b296ee Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. We may need to pass it to backend so that we can emit an ELF attr proposed by https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/409. --- clang/test/Driver/riscv-profiles.c | 105 + llvm/lib/Support/RISCVISAInfo.cpp | 44 +++ llvm/lib/Target/RISCV/RISCV.td | 6 ++ llvm/lib/Target/RISCV/RISCVProfiles.td | 70 + llvm/lib/Target/RISCV/RISCVSubtarget.h | 14 5 files changed, 239 insertions(+) create mode 100644 clang/test/Driver/riscv-profiles.c create mode 100644 llvm/lib/Target/RISCV/RISCVProfiles.td diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..7f54d0d885c7d7 --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,105 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-cpu" "generic-rv64" +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" +// RVI20U32: "-target-abi" "ilp32" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-cpu" "generic-rv64" +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" +// RVI20U64: "-target-abi" "lp64" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-cpu" "generic-rv64" +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-cpu" "generic-rv64" +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-cpu" "generic-rv64" +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" +// RVA22U64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-cpu" "generic-rv64" +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+zicsr" +// RVA22S64: "-target-feature" "+zifencei" +// RVA22S64: "-target-feature" "+zihintpause" +// RVA22S64: "-target-feature" "+zfhmin" +// RVA22S64: "-target-feature" "+zba" +// RVA22S64: "-target-feature" "+zbb" +// RVA22S64: "-target-feature" "+zbs" +// RVA22S64: "-target-feature" "+zkt" +// RVA22S64: "-target-feature" "+svinval" +// RVA22S64: "-target-feature" "+svpbmt" +// RVA22S64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64_zfa | FileCheck -check-prefix=PROFILE-WITH-ADDITIONAL %s +// PROFILE-WITH-ADDITIONAL: "-target-cpu" "generic-rv64" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+m" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+a" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+f" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+d" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+c" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbom" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+
[clang] [RISCV][NFC] Use errorToBool (PR #76429)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/76429 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][NFC] Use RISCVISAInfo instead of string comparison (PR #76387)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/76387 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/76395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RFC][RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From fa079e4be8b1b043b635a494b8c0bcc5aa79092b Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. We may need to pass it to backend so that we can emit an ELF attr proposed by https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/409. --- clang/test/Driver/riscv-profiles.c | 112 +++ llvm/include/llvm/Support/RISCVISAInfo.h | 4 +- llvm/lib/Support/RISCVISAInfo.cpp| 51 +++ llvm/lib/Target/RISCV/RISCV.td | 6 ++ llvm/lib/Target/RISCV/RISCVProfiles.td | 70 ++ llvm/lib/Target/RISCV/RISCVSubtarget.h | 14 +++ llvm/test/CodeGen/RISCV/attributes.ll| 15 +++ 7 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 clang/test/Driver/riscv-profiles.c create mode 100644 llvm/lib/Target/RISCV/RISCVProfiles.td diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..d41d68e078b976 --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,112 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-cpu" "generic-rv32" +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" +// RVI20U32: "-target-feature" "+rvi20u32" +// RVI20U32: "-target-abi" "ilp32" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-cpu" "generic-rv64" +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" +// RVI20U64: "-target-feature" "+rvi20u64" +// RVI20U64: "-target-abi" "lp64" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-cpu" "generic-rv64" +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-feature" "+rva20u64" +// RVA20U64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-cpu" "generic-rv64" +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-feature" "+rva20s64" +// RVA20S64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-cpu" "generic-rv64" +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" +// RVA22U64: "-target-feature" "+rva22u64" +// RVA22U64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-cpu" "generic-rv64" +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+zicsr" +// RVA22S64: "-target-feature" "+zifencei" +// RVA22S64: "-target-feature" "+zihintpause" +// RVA22S64: "-target-feature" "+zfhmin" +// RVA22S64: "-target-feature" "+zba" +// RVA22S64: "-target-feature" "+zbb" +// RVA22S64: "-target-feature" "+zbs" +// RVA22S64: "-target-feature" "+zkt" +// RVA22S64: "-target-feature" "+svinval" +// RVA22S64: "-target-feature" "+svpbmt" +// RVA22S64: "-target-feature" "+rva22s64" +// RVA22S64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64_zfa | FileCheck -check-prefix=PROFILE-WITH-ADDITIONAL %s +// PROFILE-WITH-ADDITIONAL: "-target-
[clang] [llvm] [RFC][RISCV] Support RISC-V Profiles in -march option (PR #76357)
W-angler wrote: Current implementation is based on the comment(https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36#issuecomment-1867859642), not the RFC. @dtcxzyw https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add B extension (PR #76893)
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76893
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
Though it hasn't been ratified, I set its version to `1.0`.
>From 52ed8e07f759546454798b6590ba01cbb6a08651 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
Though it hasn't been ratified, I set its version to `1.0`.
---
clang/test/Preprocessor/riscv-target-features.c | 12
llvm/docs/RISCVUsage.rst| 1 +
llvm/lib/Support/RISCVISAInfo.cpp | 3 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 8
llvm/test/CodeGen/RISCV/attributes.ll | 4
5 files changed, 28 insertions(+)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02d8d34116f804..783edfe7301a5f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -5,6 +5,7 @@
// CHECK-NOT: __riscv_a {{.*$}}
// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
// CHECK-NOT: __riscv_c {{.*$}}
// CHECK-NOT: __riscv_compressed {{.*$}}
// CHECK-NOT: __riscv_d {{.*$}}
@@ -150,6 +151,17 @@
// CHECK-A-EXT: __riscv_a 2001000{{$}}
// CHECK-A-EXT: __riscv_atomic 1
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ic -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 99c7146825f5ee..05634702595018 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
ExtensionStatus
=== =
``A``Supported
+ ``B``Supported
``C``Supported
``D``Supported
``F``Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..f9c5bd2eb2bdbb 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -51,6 +51,7 @@ static const char *RISCVGImplications[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExtensions[] = {
{"a", RISCVExtensionVersion{2, 1}},
+{"b", RISCVExtensionVersion{1, 0}},
{"c", RISCVExtensionVersion{2, 0}},
{"d", RISCVExtensionVersion{2, 2}},
{"e", RISCVExtensionVersion{2, 0}},
@@ -997,6 +998,7 @@ Error RISCVISAInfo::checkDependency() {
return Error::success();
}
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
static const char *ImpliedExtsD[] = {"f"};
static const char *ImpliedExtsF[] = {"zicsr"};
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1071,6 +1073,7 @@ struct ImpliedExtsEntry {
// Note: The table needs to be sorted by name.
static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
{{"d"}, {ImpliedExtsD}},
{{"f"}, {ImpliedExtsF}},
{{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 59b202606dadaf..0201f4837733a0 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -202,6 +202,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+ [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+ AssemblerPredicate<(all_of FeatureStdExtB),
+ "'B' (the collection of the Zba, Zbb, Zbs
extensions)">;
+
def FeatureStdExtZbkb
: SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
"'Zbkb' (Bitmanip instructions for Cryptography)
[llvm] [clang] [RISCV] Add B extension (PR #76893)
wangpc-pp wrote: > > I would suggest set it as 0.1 rather than 1.0, and I gonna to ask Ved to > > add version info as well... > > Then also needs to move behind -menable-experimental-extensions. Yes, this is why I set version to 1.0. All implied extensions are ratified but when we want to use `b` to reduce some character in -march, we need to specify `-menable-experimental-extensions` instead. (I hope B extension can be ratified soon...) https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
wangpc-pp wrote: > @wangpc-pp did you have interested on helping psABI side? it would be great > if you can help since I suspect I don't have enough bandwidth to deal with > that soon. Yes, I'm glad to. I think what we need to do is to fix some Zdinx issues? :-) And, I think I have to explain the background here: I started to maintain this patch about two years ago when I was in T-head, since they have some old RV32E cores (AFAIK, SiFive has RV32E cores too?) and some customers needed the support of RV32E/ilp32e. Now, both T-head and SiFive didn't release RV32E cores any more, and the RVI doesn't put its focuses on RVE too I think. But I don't think there is no vendor that developed or developing their own RV32E implementations. Now I am no longer working at T-head and my current work is not about RV32E, so I don't have environment to test it. But I think this patch can work just fine since it has been used in T-head's downstream for a long time (since LLVM 13, IIRC) and @zixuan-wu has reported several issues (already solved) before. Apart from vendors' need, the request is mainly from Rust language community I think. IIUC, this is for the Rust implementation of SBI (https://github.com/rustsbi/rustsbi). They are using T-head E902 (rv32em?) and RV32E core from SiFive. So, yeah, I will try my best to fix the ABI issue, but I think we still need the help of the RISC-V community. I will contact with T-head guys to see if they are interested in this. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
@@ -42,9 +42,10 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ const auto ISAInfoFeatures = (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false);
+ Features.insert(Features.end(), ISAInfoFeatures.begin(),
+ ISAInfoFeatures.end());
wangpc-pp wrote:
```suggestion
llvm::append_range(Features, (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
/*IgnoreUnknown=*/false));
```
https://github.com/llvm/llvm-project/pull/76942
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[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
wangpc-pp wrote:
> Side note: shouldn't we also update `compiler-rt/lib/builtins/riscv/{save,
> restore}.S`? E.g. with something like this:
> [...]
> (I don't remember why exactly since I did it a long time ago, but for some
> reason I do have this patch in my LLVM fork, so it probably was necessary for
> _something_.)
Oh, it may be about stack alignment issue for libcalls. I may have fixed it.
As for your diffs, it seems that you only handle the
`__riscv_save/restore_[2|1|0]`, which is incomplete. And the code is not
different with non-rve cases?
https://github.com/llvm/llvm-project/pull/76777
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[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
wangpc-pp wrote: > > As for your diffs, it seems that you only handle the > > `__riscv_save/restore_[2|1|0]`, which is incomplete. And the code is not > > different with non-rve cases? > > Yes, I mostly copy-pasted the existing code and removed all of the code > dealing with registers not available on RV32E, so having only > `__riscv_save/restore_[2|1|0]` is intended I suppose because there are only > this many saved registers on RV32E. (There's probably a better way of doing > it, and it looks like I screwed up the RV64E part of the patch.) > > If I remember correctly I think I did this because otherwise compiling > `compiler-rt` was not possible for RV32E and the compilation was spewing out > errors about the unavailable registers? But I need to check this again once I > finish porting this newest version of the patch to the most recent version of > Rust. Oh, I see. My previous comment was wrong. I just checked GCC implementation, we do need to handle RVE cases (but GCC still lacks of RV64E handling). LLVM hasn't handled this mainly because we haven't support RVE now, I think. Can you fire a PR for these changes? I think we should support it in compiler-rt once we have merge this PR. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/77424
`A` extension has been split into two parts: Zaamo (Atomic Memory
Operations) and Zalrsc (Load-Reserved/Store-Conditional). See also
https://github.com/riscv/riscv-zaamo-zalrsc.
This patch adds the basic compiler support.
Tests for `A` extension are reused.
>From a16ff19b7666060db74bebd4cb7e7132776285a7 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 9 Jan 2024 16:12:40 +0800
Subject: [PATCH] [RISCV] Add experimental support of Zaamo and Zalrsc
`A` extension has been split into two parts: Zaamo (Atomic Memory
Operations) and Zalrsc (Load-Reserved/Store-Conditional). See also
https://github.com/riscv/riscv-zaamo-zalrsc.
This patch adds the basic compiler support.
Tests for `A` extension are reused.
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
.../test/Preprocessor/riscv-target-features.c | 19 +++
llvm/docs/RISCVUsage.rst | 2 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 26 ++-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 +-
llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 32 ++--
.../RISCV/atomic-cmpxchg-branch-on-result.ll | 4 +
.../test/CodeGen/RISCV/atomic-cmpxchg-flag.ll | 2 +
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll | 8 +
llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll | 4 +
llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll | 4 +
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 8 +
llvm/test/CodeGen/RISCV/atomic-signext.ll | 4 +
.../CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll | 4 +
llvm/test/CodeGen/RISCV/attributes.ll | 8 +
llvm/test/MC/RISCV/rv32i-invalid.s| 2 +-
llvm/test/MC/RISCV/rv32zaamo-invalid.s| 11 ++
llvm/test/MC/RISCV/rv32zaamo-valid.s | 122 ++
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 7 +
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 36
llvm/test/MC/RISCV/rv64zaamo-invalid.s| 11 ++
llvm/test/MC/RISCV/rv64zaamo-valid.s | 157 ++
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 7 +
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 42 +
llvm/unittests/Support/RISCVISAInfoTest.cpp | 2 +
26 files changed, 515 insertions(+), 18 deletions(-)
create mode 100644 llvm/test/MC/RISCV/rv32zaamo-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zaamo-valid.s
create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zaamo-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zaamo-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-valid.s
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..7aff435b715ca1 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -176,7 +176,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__riscv_muldiv");
}
- if (ISAInfo->hasExtension("a")) {
+ if (ISAInfo->hasExtension("a") || ISAInfo->hasExtension("zaamo")) {
Builder.defineMacro("__riscv_atomic");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02d8d34116f804..69ba912880f800 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -114,7 +114,9 @@
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_ssaia {{.*$}}
+// CHECK-NOT: __riscv_zaamo {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
+// CHECK-NOT: __riscv_zalrsc {{.*$}}
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
@@ -1025,6 +1027,15 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
// CHECK-SSAIA-EXT: __riscv_ssaia 100{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zaamo0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zaamo0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
+// CHECK-ZAAMO-EXT: __riscv_atomic 1
+// CHECK-ZAAMO-EXT: __riscv_zaamo 1000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zacas1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
@@ -1033,6 +1044,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 100{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zalrsc0p1
[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)
@@ -0,0 +1,11 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zaamo < %s 2>&1 | FileCheck %s wangpc-pp wrote: This can be done in the future, I think. Current implementation refers to the `Zmmul` (which is a sub-extension of M extension). The case is the same for `Zaamo` and `Zalrsc` I think. https://github.com/llvm/llvm-project/pull/77424 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -17,6 +17,13 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, AssemblerPredicate<(all_of FeatureStdExtZicsr), "'Zicsr' (CSRs)">; +def FeatureStdExtI +: SubtargetFeature<"i", "HasStdExtI", "true", + "'I' (Base Integer Instruction Set)">; +def HasStdExtI : Predicate<"Subtarget->hasStdExtI()">, + AssemblerPredicate<(all_of FeatureStdExtI), + "'I' (Base Integer Instruction Set)">; + wangpc-pp wrote: For `RVE`, we will have some command lines like `-target-feature -i` in clang driver, which will cause error as we don't have `i` extension in backend. This fixes this error. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -83,13 +88,14 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF) const {
}
BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ const RISCVSubtarget &STI = MF.getSubtarget();
wangpc-pp wrote:
This should be a rebase mistake.
https://github.com/llvm/llvm-project/pull/76777
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[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) wangpc-pp wrote: The psABI says: > If used with an ISA that has any of the registers x16-x31 and f0-f31, then > these registers are considered temporaries. So I think we should. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -386,6 +393,11 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
if (llvm::is_contained(Features, "+experimental"))
HasExperimental = true;
+ if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
+Diags.Report(diag::err_invalid_feature_combination)
+<< "ILP32E cannot be used with the D ISA extension";
+return false;
+ }
wangpc-pp wrote:
Yes, I think we should!
(Sigh...even RISC-V International has forgotten RVE, as many new ISA extensions
don't even think about impacts on RVE 😞).
https://github.com/llvm/llvm-project/pull/76777
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[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][doc] Add blank line before lists (PR #77573)
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/77573 The doc is not correctly rendered with missing blank lines. >From 2d249aefa1bfa91f41a3866c4203eff041415546 Mon Sep 17 00:00:00 2001 From: wangpc Date: Wed, 10 Jan 2024 17:54:27 +0800 Subject: [PATCH] [Clang][doc] Add blank line before lists The doc is not correctly rendered with missing blank lines. --- clang/docs/LanguageExtensions.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 23a7f4f5d5b926..c1420079f75118 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -829,6 +829,7 @@ to ``float``; see below for more information on this emulation. see below. * ``_Float16`` is supported on the following targets: + * 32-bit ARM (natively on some architecture versions) * 64-bit ARM (AArch64) (natively on ARMv8.2a and above) * AMDGPU (natively) @@ -837,6 +838,7 @@ to ``float``; see below for more information on this emulation. * RISC-V (natively if Zfh or Zhinx is available) * ``__bf16`` is supported on the following targets (currently never natively): + * 32-bit ARM * 64-bit ARM (AArch64) * RISC-V ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][doc] Add blank line before lists (PR #77573)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/77573 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) wangpc-pp wrote: Though it's nearly impossible to have such configuration in real application, I saved x15-x16 in https://github.com/llvm/llvm-project/pull/76777/commits/20ffba38548c823d6ef286bcad63385087438d57. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)
wangpc-pp wrote:
I think we will add attributes automatically?
```shell
~/workspace# cat a.S
.globl foo
.p2align1
.type foo,@function
foo:
ret
~/workspace# clang -march=rv64gcv -c a.S
~/workspace# llvm-readobj -A a.o
File: a.o
Format: elf64-littleriscv
Arch: riscv64
AddressSize: 64bit
LoadName:
BuildAttributes {
FormatVersion: 0x41
Section 1 {
SectionLength: 157
Vendor: riscv
Tag: Tag_File (0x1)
Size: 147
FileAttributes {
Attribute {
Tag: 5
TagName: arch
Value:
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
}
}
}
}
```
https://github.com/llvm/llvm-project/pull/85063
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH 1/2] [RISCV] Support RISC-V Profiles in -march option This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. --- clang/docs/ReleaseNotes.rst| 1 + clang/test/Driver/riscv-profiles.c | 312 + llvm/lib/Support/RISCVISAInfo.cpp | 65 ++ 3 files changed, 378 insertions(+) create mode 100644 clang/test/Driver/riscv-profiles.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index bce27dc8c4a996..a072bf4a5ff4b0 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -408,6 +408,7 @@ RISC-V Support ^^ - ``__attribute__((rvv_vector_bits(N)))`` is now supported for RVV vbool*_t types. +- Profile names in ``-march`` option is now supported. CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..904f0c371f4442 --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,312 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+ziccamoa" +// RVA20U64: "-target-feature" "+ziccif" +// RVA20U64: "-target-feature" "+zicclsm" +// RVA20U64: "-target-feature" "+ziccrse" +// RVA20U64: "-target-feature" "+zicntr" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-feature" "+za128rs" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+ziccamoa" +// RVA20S64: "-target-feature" "+ziccif" +// RVA20S64: "-target-feature" "+zicclsm" +// RVA20S64: "-target-feature" "+ziccrse" +// RVA20S64: "-target-feature" "+zicntr" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-feature" "+za128rs" +// RVA20S64: "-target-feature" "+ssccptr" +// RVA20S64: "-target-feature" "+sstvala" +// RVA20S64: "-target-feature" "+sstvecd" +// RVA20S64: "-target-feature" "+svade" +// RVA20S64: "-target-feature" "+svbare" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zic64b" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+ziccamoa" +// RVA22U64: "-target-feature" "+ziccif" +// RVA22U64: "-target-feature" "+zicclsm" +// RVA22U64: "-target-feature" "+ziccrse" +// RVA22U64: "-target-feature" "+zicntr" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zihpm" +// RVA22U64: "-target-feature" "+za64rs" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zic64b" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+ziccamoa" +// RVA22S64: "-target-feature" "+ziccif" +// RVA22S64: "-target-feature" "+zicclsm" +// RVA22S64: "-target-feature" "+ziccrse" +// RVA22S64: "-target-feature" "+zicntr"
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
wangpc-pp wrote:
What should I do?
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH 1/3] [RISCV] Support RISC-V Profiles in -march option This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. --- clang/docs/ReleaseNotes.rst| 1 + clang/test/Driver/riscv-profiles.c | 312 + llvm/lib/Support/RISCVISAInfo.cpp | 65 ++ 3 files changed, 378 insertions(+) create mode 100644 clang/test/Driver/riscv-profiles.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index bce27dc8c4a996..a072bf4a5ff4b0 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -408,6 +408,7 @@ RISC-V Support ^^ - ``__attribute__((rvv_vector_bits(N)))`` is now supported for RVV vbool*_t types. +- Profile names in ``-march`` option is now supported. CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..904f0c371f4442 --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,312 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+ziccamoa" +// RVA20U64: "-target-feature" "+ziccif" +// RVA20U64: "-target-feature" "+zicclsm" +// RVA20U64: "-target-feature" "+ziccrse" +// RVA20U64: "-target-feature" "+zicntr" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-feature" "+za128rs" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+ziccamoa" +// RVA20S64: "-target-feature" "+ziccif" +// RVA20S64: "-target-feature" "+zicclsm" +// RVA20S64: "-target-feature" "+ziccrse" +// RVA20S64: "-target-feature" "+zicntr" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-feature" "+za128rs" +// RVA20S64: "-target-feature" "+ssccptr" +// RVA20S64: "-target-feature" "+sstvala" +// RVA20S64: "-target-feature" "+sstvecd" +// RVA20S64: "-target-feature" "+svade" +// RVA20S64: "-target-feature" "+svbare" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zic64b" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+ziccamoa" +// RVA22U64: "-target-feature" "+ziccif" +// RVA22U64: "-target-feature" "+zicclsm" +// RVA22U64: "-target-feature" "+ziccrse" +// RVA22U64: "-target-feature" "+zicntr" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zihpm" +// RVA22U64: "-target-feature" "+za64rs" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zic64b" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+ziccamoa" +// RVA22S64: "-target-feature" "+ziccif" +// RVA22S64: "-target-feature" "+zicclsm" +// RVA22S64: "-target-feature" "+ziccrse" +// RVA22S64: "-target-feature" "+zicntr"
[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
wangpc-pp wrote: I support adding these builtins personally, but I think we need more discussions on the design. We can achieve the same thing via inline assemblies, that's true. But, from the compiler side, inline assemblies are kind of barriers, we can't do a lot of optimizations/reorderings if inline assemblies exist. If we make it a builtin, these limitations can be loosed I think. https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
wangpc-pp wrote: > > > I support adding these builtins personally, but I think we need more > > > discussions on the design. We can achieve the same thing via inline > > > assemblies, that's true. But, from the compiler side, inline assemblies > > > are kind of barriers, we can't do a lot of optimizations/reorderings if > > > inline assemblies exist. If we make it a builtin, these limitations can > > > be loosed I think. > > > > > > Inline assembly is only a barrier to moving load/stores and other side > > effecting instructions. And only if the inline assembly is marked volatile > > or has "memory" clobber. It should not affect moving arithmetic. I think > > these CSR intrinsics would also need to be barriers against load/stores and > > other side effects to be the most conservative to access any CSR. > > Yes, exactly; you have no clue what the semantics of the CSR are (if you did, > you'd have a named intrinsic, like `__builtin_readcyclecounter()`) because it > is just an arbitrary number. > > Also, in what world do you need compiler optimisations around general CSR > accesses? That's normally relatively cold performance-non-critical code... Thanks for replying. I may not think it clearly. There are many ways to do the same thing. I think this PR wouldn't be the last time that someone try to add these builtins: * https://reviews.llvm.org/D71778 * https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/8 https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)
wangpc-pp wrote: > We discussed this on the sync-up call and @preames very rightly pointed out > that we should take a step back here...from a user perspective, what does > specifying a profile via `-mcpu` provide that specifying it via `-march` > doesn't? We weren't able to answer that in the call, but perhaps we're > missing something? Thanks! I was off the meeting because of some real-life issues. :-) The story is: 1. I was implementing the profile name in `-march`, and I exposed profiles as subtarget features at the first time. So that we can use `-mattr=+` and simplify the definitions of processors. You may see the context in https://github.com/llvm/llvm-project/pull/76357#discussion_r1517343360. 2. @topperc suggested that we may not need these features and we can factor out some feature lists and may add `-mcpu=generic-`. I like this idea and so I created this PR. As for the difference, we can specify `-mcpu` for `llc` and other tools, which is not the case for `-march`? I hope we can simplify the commands when we try to do some tests. (Though this is an use for compiler developers, not for real users). https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
wangpc-pp wrote:
Is there a global constructor/destructor if it is inside a function and lazily
initialized?
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
wangpc-pp wrote: GCC gained its `__arm_rsr` and `__arm_wsr` support last year (October, 2023): https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631855.html. So there is no stable released GCC version that supports these builtins. Clang supported these builtins about nine years ago: https://reviews.llvm.org/D9697. But as we know, clang is not the default compiler in most OS distributions. People may not even know these features. We can see some usages (ignore the gcc/llvm packages) via Debain Code Search: http://codesearch.debian.net/search?q=__arm_rsr&literal=1. So I think it's mainly a problem left over by history: ``` // Although the ARM ACLE does have a specification for __arm_rsr/__arm_wsr // for reading and writing to the status registers, they are not implemented // by GCC, so we need to resort to inline assembly. ``` As for RISCV, the software ecosystem is growing. So I just think we should do the right thing ASAP. https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Don't alias -mstrict-align to -mno-unaligned-access (PR #85350)
https://github.com/wangpc-pp approved this pull request. LGTM. cc @asb @topperc Some context of RISCV target: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/62 https://github.com/llvm/llvm-project/pull/85350 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
wangpc-pp wrote: > Should we use strings like ARM does so we can get register by name? Good point! We may provide two kinds of builtins: one by name, and another by CSR number. We should continue @lenary's proposal and discuss it in https://github.com/riscv-non-isa/riscv-toolchain-conventions or https://github.com/riscv-non-isa/riscv-c-api-doc. https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH] [RISCV] Support RISC-V Profiles in -march option This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. --- clang/docs/ReleaseNotes.rst| 1 + clang/test/Driver/riscv-profiles.c | 312 + llvm/lib/Support/RISCVISAInfo.cpp | 64 ++ 3 files changed, 377 insertions(+) create mode 100644 clang/test/Driver/riscv-profiles.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 125d51c42d507f..08c6d45d60c4dc 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -455,6 +455,7 @@ RISC-V Support ^^ - ``__attribute__((rvv_vector_bits(N)))`` is now supported for RVV vbool*_t types. +- Profile names in ``-march`` option is now supported. CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..904f0c371f4442 --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,312 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+ziccamoa" +// RVA20U64: "-target-feature" "+ziccif" +// RVA20U64: "-target-feature" "+zicclsm" +// RVA20U64: "-target-feature" "+ziccrse" +// RVA20U64: "-target-feature" "+zicntr" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-feature" "+za128rs" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+ziccamoa" +// RVA20S64: "-target-feature" "+ziccif" +// RVA20S64: "-target-feature" "+zicclsm" +// RVA20S64: "-target-feature" "+ziccrse" +// RVA20S64: "-target-feature" "+zicntr" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-feature" "+za128rs" +// RVA20S64: "-target-feature" "+ssccptr" +// RVA20S64: "-target-feature" "+sstvala" +// RVA20S64: "-target-feature" "+sstvecd" +// RVA20S64: "-target-feature" "+svade" +// RVA20S64: "-target-feature" "+svbare" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zic64b" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+ziccamoa" +// RVA22U64: "-target-feature" "+ziccif" +// RVA22U64: "-target-feature" "+zicclsm" +// RVA22U64: "-target-feature" "+ziccrse" +// RVA22U64: "-target-feature" "+zicntr" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zihpm" +// RVA22U64: "-target-feature" "+za64rs" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zic64b" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+ziccamoa" +// RVA22S64: "-target-feature" "+ziccif" +// RVA22S64: "-target-feature" "+zicclsm" +// RVA22S64: "-target-feature" "+ziccrse" +// RVA22S64: "-target-feature" "+zicntr" +//
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
+{"rvi20u32", "rv32i"},
+{"rvi20u64", "rv64i"},
+{"rva20u64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},
+{"rva20s64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"
+ "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},
+{"rva22u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_"
+ "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},
+{"rva22s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_"
+ "ssccptr_"
+ "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},
+{"rva23u64",
+ "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_zfa_"
+ "zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
+{"rva23s64",
+ "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_"
+ "zawrs_"
+ "zfa_zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_"
+ "shcounterenw_"
+ "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"
+ "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"
+ "svbare_svinval_svnapot_svpbmt"},
+{"rvb23u64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"
+ "zimop0p1_za64rs_zawrs_zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt"},
+{"rvb23s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_"
+ "zawrs_"
+ "zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_"
+ "sstvala_sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},
+{"rvm23u32",
+ "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop0p1_"
+ "zca_zcb_zce_zcmop0p2_zcmp_zcmt_zba_zbb_zbs"},
+};
+
+auto FoundProfile = llvm::find_if(
+SupportedProfiles,
+[Arch](const std::pair &Profile) {
+ return Arch.starts_with(Profile.first);
+});
+
+if (FoundProfile == SupportedProfiles.end())
+ return createStringError(errc::invalid_argument, "unsupported profile");
+
+NewArch = FoundProfile->second;
+StringRef ArchWithoutProfile = Arch.substr(FoundProfile->first.size());
+if (!ArchWithoutProfile.empty()) {
+ if (!ArchWithoutProfile.starts_with("_"))
+return createStringError(
+errc::invalid_argument,
+"additional extensions must be after separator '_'");
+ NewArch += ArchWithoutProfile.str();
+}
+Arch = NewArch;
wangpc-pp wrote:
Applied.
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
wangpc-pp wrote:
I go back to use a global static array of RISCVProfile.
https://github.com/llvm/llvm-project/pull/76357
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
wangpc-pp wrote: There is a Windows failure that I can't reproduce: https://buildkite.com/llvm-project/github-pull-requests/builds/46331 Can someone help me to figure out what is wrong? https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH 1/2] [RISCV] Support RISC-V Profiles in -march option This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. --- clang/docs/ReleaseNotes.rst| 1 + clang/test/Driver/riscv-profiles.c | 312 + llvm/lib/Support/RISCVISAInfo.cpp | 64 ++ 3 files changed, 377 insertions(+) create mode 100644 clang/test/Driver/riscv-profiles.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 125d51c42d507f..08c6d45d60c4dc 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -455,6 +455,7 @@ RISC-V Support ^^ - ``__attribute__((rvv_vector_bits(N)))`` is now supported for RVV vbool*_t types. +- Profile names in ``-march`` option is now supported. CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..904f0c371f4442 --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,312 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+ziccamoa" +// RVA20U64: "-target-feature" "+ziccif" +// RVA20U64: "-target-feature" "+zicclsm" +// RVA20U64: "-target-feature" "+ziccrse" +// RVA20U64: "-target-feature" "+zicntr" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-feature" "+za128rs" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+ziccamoa" +// RVA20S64: "-target-feature" "+ziccif" +// RVA20S64: "-target-feature" "+zicclsm" +// RVA20S64: "-target-feature" "+ziccrse" +// RVA20S64: "-target-feature" "+zicntr" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-feature" "+za128rs" +// RVA20S64: "-target-feature" "+ssccptr" +// RVA20S64: "-target-feature" "+sstvala" +// RVA20S64: "-target-feature" "+sstvecd" +// RVA20S64: "-target-feature" "+svade" +// RVA20S64: "-target-feature" "+svbare" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zic64b" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+ziccamoa" +// RVA22U64: "-target-feature" "+ziccif" +// RVA22U64: "-target-feature" "+zicclsm" +// RVA22U64: "-target-feature" "+ziccrse" +// RVA22U64: "-target-feature" "+zicntr" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zihpm" +// RVA22U64: "-target-feature" "+za64rs" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zic64b" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+ziccamoa" +// RVA22S64: "-target-feature" "+ziccif" +// RVA22S64: "-target-feature" "+zicclsm" +// RVA22S64: "-target-feature" "+ziccrse" +// RVA22S64: "-target-feature" "+zicntr"
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH 1/3] [RISCV] Support RISC-V Profiles in -march option This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. --- clang/docs/ReleaseNotes.rst| 1 + clang/test/Driver/riscv-profiles.c | 312 + llvm/lib/Support/RISCVISAInfo.cpp | 64 ++ 3 files changed, 377 insertions(+) create mode 100644 clang/test/Driver/riscv-profiles.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 125d51c42d507f..08c6d45d60c4dc 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -455,6 +455,7 @@ RISC-V Support ^^ - ``__attribute__((rvv_vector_bits(N)))`` is now supported for RVV vbool*_t types. +- Profile names in ``-march`` option is now supported. CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..904f0c371f4442 --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,312 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+ziccamoa" +// RVA20U64: "-target-feature" "+ziccif" +// RVA20U64: "-target-feature" "+zicclsm" +// RVA20U64: "-target-feature" "+ziccrse" +// RVA20U64: "-target-feature" "+zicntr" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-feature" "+za128rs" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+ziccamoa" +// RVA20S64: "-target-feature" "+ziccif" +// RVA20S64: "-target-feature" "+zicclsm" +// RVA20S64: "-target-feature" "+ziccrse" +// RVA20S64: "-target-feature" "+zicntr" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-feature" "+za128rs" +// RVA20S64: "-target-feature" "+ssccptr" +// RVA20S64: "-target-feature" "+sstvala" +// RVA20S64: "-target-feature" "+sstvecd" +// RVA20S64: "-target-feature" "+svade" +// RVA20S64: "-target-feature" "+svbare" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zic64b" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+ziccamoa" +// RVA22U64: "-target-feature" "+ziccif" +// RVA22U64: "-target-feature" "+zicclsm" +// RVA22U64: "-target-feature" "+ziccrse" +// RVA22U64: "-target-feature" "+zicntr" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zihpm" +// RVA22U64: "-target-feature" "+za64rs" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zic64b" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+ziccamoa" +// RVA22S64: "-target-feature" "+ziccif" +// RVA22S64: "-target-feature" "+zicclsm" +// RVA22S64: "-target-feature" "+ziccrse" +// RVA22S64: "-target-feature" "+zicntr"
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From 26245679b0f40b510e628aaed091739e9931c29c Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/5] [clang] Enable sized deallocation by default in C++14
onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
Differential Revision: https://reviews.llvm.org/D112921
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 4 +
clang/include/clang/Basic/SizedDeallocation.h | 44
clang/include/clang/Driver/Options.td | 5 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 41 ++-
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/dr292.cpp | 6 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
41 files changed, 458 insertions(+), 104 deletions(-)
create mode 100644 clang/include/clang/Basic/SizedDeallocation.h
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 6f6ce7c6
[clang] [clang-format] Add Options to break inside the TableGen DAGArg. (PR #83149)
wangpc-pp wrote: This breaks CI `Test documentation build` like: https://github.com/llvm/llvm-project/actions/runs/8339765845/job/22822367034 https://github.com/llvm/llvm-project/pull/83149 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
wangpc-pp wrote: > > > There is a Windows failure that I can't reproduce: > > > https://buildkite.com/llvm-project/github-pull-requests/builds/46331 Can > > > someone help me to figure out what is wrong? > > > > > > I'm not certain what's going on yet, but it smells a bit like the > > interpreter needs to know about sized deallocations now being on by default > > (this may be exposing an existing bug rather than introducing a new one). > > CC @vgvassilev > > I am shooting in the dark here, too. Can you forward declare the new operator > delete here: > > https://github.com/llvm/llvm-project/blob/e2e3624fae669f85de1445bf7037ff29feb30905/clang/lib/Interpreter/Interpreter.cpp#L262 It's still failing. :-( https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
wangpc-pp wrote:
> > Not entirely certain what you're asking, but MSVC CRT does have a
> > definition for sized delete:
> > ```
> > _CRT_SECURITYCRITICAL_ATTRIBUTE
> > void __CRTDECL operator delete(void* const block, size_t const) noexcept
> > {
> > operator delete(block);
> > }
> > ```
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > in `crt\src\vcruntime\delete_scalar_size.cpp`
>
> In that case for this test (or likely the entire interpreter library) we will
> have export that symbol with the linker. Something similar is done here:
> https://github.com/llvm/llvm-project/pull/84769/files#diff-d7f5dca2bd540f1b18ba90a66497b6b12e40fd07058b70f0fdec638c8e97406eR14-R71
> as part of #84769. Unfortunately, this is the only reliable way as of today
> to export crt symbols to the JIT. cc: @lhames, @fsfod.
So should I wait for landing this PR or is there a workaround to fix this
problem?
https://github.com/llvm/llvm-project/pull/83774
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 6e755c5 - Revert "[RISCV] Support RISC-V Profiles in -march option (#76357)"
Author: Wang Pengcheng Date: 2024-03-22T18:49:25+08:00 New Revision: 6e755c51a916dc521ffe89738bcab47a5442ad06 URL: https://github.com/llvm/llvm-project/commit/6e755c51a916dc521ffe89738bcab47a5442ad06 DIFF: https://github.com/llvm/llvm-project/commit/6e755c51a916dc521ffe89738bcab47a5442ad06.diff LOG: Revert "[RISCV] Support RISC-V Profiles in -march option (#76357)" This reverts commit 66f88de80599ec4461b0fdac3d1e396b6e83052d as there are some failures. Added: Modified: clang/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp Removed: clang/test/Driver/riscv-profiles.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 005cdebc0d8ace..fd12bb41be47a3 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -520,7 +520,6 @@ RISC-V Support ^^ - ``__attribute__((rvv_vector_bits(N)))`` is now supported for RVV vbool*_t types. -- Profile names in ``-march`` option are now supported. CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c deleted file mode 100644 index 904f0c371f4442..00 --- a/clang/test/Driver/riscv-profiles.c +++ /dev/null @@ -1,312 +0,0 @@ -// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s -// RVI20U32: "-target-feature" "-a" -// RVI20U32: "-target-feature" "-c" -// RVI20U32: "-target-feature" "-d" -// RVI20U32: "-target-feature" "-f" -// RVI20U32: "-target-feature" "-m" - -// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s -// RVI20U64: "-target-feature" "-a" -// RVI20U64: "-target-feature" "-c" -// RVI20U64: "-target-feature" "-d" -// RVI20U64: "-target-feature" "-f" -// RVI20U64: "-target-feature" "-m" - -// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s -// RVA20U64: "-target-feature" "+m" -// RVA20U64: "-target-feature" "+a" -// RVA20U64: "-target-feature" "+f" -// RVA20U64: "-target-feature" "+d" -// RVA20U64: "-target-feature" "+c" -// RVA20U64: "-target-feature" "+ziccamoa" -// RVA20U64: "-target-feature" "+ziccif" -// RVA20U64: "-target-feature" "+zicclsm" -// RVA20U64: "-target-feature" "+ziccrse" -// RVA20U64: "-target-feature" "+zicntr" -// RVA20U64: "-target-feature" "+zicsr" -// RVA20U64: "-target-feature" "+za128rs" - -// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s -// RVA20S64: "-target-feature" "+m" -// RVA20S64: "-target-feature" "+a" -// RVA20S64: "-target-feature" "+f" -// RVA20S64: "-target-feature" "+d" -// RVA20S64: "-target-feature" "+c" -// RVA20S64: "-target-feature" "+ziccamoa" -// RVA20S64: "-target-feature" "+ziccif" -// RVA20S64: "-target-feature" "+zicclsm" -// RVA20S64: "-target-feature" "+ziccrse" -// RVA20S64: "-target-feature" "+zicntr" -// RVA20S64: "-target-feature" "+zicsr" -// RVA20S64: "-target-feature" "+zifencei" -// RVA20S64: "-target-feature" "+za128rs" -// RVA20S64: "-target-feature" "+ssccptr" -// RVA20S64: "-target-feature" "+sstvala" -// RVA20S64: "-target-feature" "+sstvecd" -// RVA20S64: "-target-feature" "+svade" -// RVA20S64: "-target-feature" "+svbare" - -// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s -// RVA22U64: "-target-feature" "+m" -// RVA22U64: "-target-feature" "+a" -// RVA22U64: "-target-feature" "+f" -// RVA22U64: "-target-feature" "+d" -// RVA22U64: "-target-feature" "+c" -// RVA22U64: "-target-feature" "+zic64b" -// RVA22U64: "-target-feature" "+zicbom" -// RVA22U64: "-target-feature" "+zicbop" -// RVA22U64: "-target-feature" "+zicboz" -// RVA22U64: "-target-feature" "+ziccamoa" -// RVA22U64: "-target-feature" "+ziccif" -// RVA22U64: "-target-feature" "+zicclsm" -// RVA22U64: "-target-feature" "+ziccrse" -// RVA22U64: "-target-feature" "+zicntr" -// RVA22U64: "-target-feature" "+zicsr" -// RVA22U64: "-target-feature" "+zihintpause" -// RVA22U64: "-target-feature" "+zihpm" -// RVA22U64: "-target-feature" "+za64rs" -// RVA22U64: "-target-feature" "+zfhmin" -// RVA22U64: "-target-feature" "+zba" -// RVA22U64: "-target-feature" "+zbb" -// RVA22U64: "-target-feature" "+zbs" -// RVA22U64: "-target-feature" "+zkt" - -// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s -// RVA22S64: "-target-feature" "+m" -// RVA22S64: "-target-feature" "+a" -// RVA22S64: "-target-feature" "+f" -// RVA22S64: "-target-feature" "+d" -// RVA22S64: "-target-feature" "+c" -// RVA22S64: "-target-feature" "+zic64b" -// RVA22S64: "-target-feature" "+zicbom" -// RVA22S64: "-target-feature" "+zicbop" -// RVA22S64: "-target-feature" "+zicboz" -// RVA22S64: "-target-feature" "+ziccamoa" -// RVA22S64: "-target-feature" "+ziccif" -// RVA22S64: "-target-feature" "+zicclsm" -// RVA22S64: "-target-feature" "+ziccrse" -// RVA22S64: "-target-feature" "+zicntr" -// RVA22S64: "-target
[clang] b44771f - [RISCV] Support RISC-V Profiles in -march option (#76357)
Author: Wang Pengcheng Date: 2024-03-22T23:21:11+08:00 New Revision: b44771f480385fa93ba7719a57e759e19747e709 URL: https://github.com/llvm/llvm-project/commit/b44771f480385fa93ba7719a57e759e19747e709 DIFF: https://github.com/llvm/llvm-project/commit/b44771f480385fa93ba7719a57e759e19747e709.diff LOG: [RISCV] Support RISC-V Profiles in -march option (#76357) This PR implements the draft https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36. Currently, we replace specified profile in `-march` with standard arch string. This is recommitted as 66f88de was reverted because of failures caused by lacking `--target` option. Added: clang/test/Driver/riscv-profiles.c Modified: clang/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp Removed: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 45b2e01af997c5..d6e179ca9d6904 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -520,6 +520,7 @@ RISC-V Support ^^ - ``__attribute__((rvv_vector_bits(N)))`` is now supported for RVV vbool*_t types. +- Profile names in ``-march`` option are now supported. CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c new file mode 100644 index 00..0227487015ba7c --- /dev/null +++ b/clang/test/Driver/riscv-profiles.c @@ -0,0 +1,324 @@ +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rvi20u32 \ +// RUN: | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvi20u64 \ +// RUN: | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva20u64 \ +// RUN: | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+ziccamoa" +// RVA20U64: "-target-feature" "+ziccif" +// RVA20U64: "-target-feature" "+zicclsm" +// RVA20U64: "-target-feature" "+ziccrse" +// RVA20U64: "-target-feature" "+zicntr" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-feature" "+za128rs" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva20s64 \ +// RUN: | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+ziccamoa" +// RVA20S64: "-target-feature" "+ziccif" +// RVA20S64: "-target-feature" "+zicclsm" +// RVA20S64: "-target-feature" "+ziccrse" +// RVA20S64: "-target-feature" "+zicntr" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-feature" "+za128rs" +// RVA20S64: "-target-feature" "+ssccptr" +// RVA20S64: "-target-feature" "+sstvala" +// RVA20S64: "-target-feature" "+sstvecd" +// RVA20S64: "-target-feature" "+svade" +// RVA20S64: "-target-feature" "+svbare" + +// RUN: %clang --target=riscv64 --target=riscv64 -### -c %s 2>&1 -march=rva22u64 \ +// RUN: | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zic64b" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+ziccamoa" +// RVA22U64: "-target-feature" "+ziccif" +// RVA22U64: "-target-feature" "+zicclsm" +// RVA22U64: "-target-feature" "+ziccrse" +// RVA22U64: "-target-feature" "+zicntr" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zihpm" +// RVA22U64: "-target-feature" "+za64rs" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" + +// RUN: %clang --target=riscv64 --target=riscv64 -### -c %s 2>&1 -march=rva22s64 \ +// RUN: | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/2] [clang] Enable sized deallocation by default in C++14
onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
Differential Revision: https://reviews.llvm.org/D112921
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 5 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/dr292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
40 files changed, 436 insertions(+), 111 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index d6e179ca9d6904..489679d8c0c681 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -83,6 +83,11 @@ secti
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/3] [clang] Enable sized deallocation by default in C++14
onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
Differential Revision: https://reviews.llvm.org/D112921
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 5 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/dr292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
40 files changed, 436 insertions(+), 111 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index d6e179ca9d6904..489679d8c0c681 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -83,6 +83,11 @@ secti
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/4] [clang] Enable sized deallocation by default in C++14
onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
Differential Revision: https://reviews.llvm.org/D112921
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 5 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/dr292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
40 files changed, 436 insertions(+), 111 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index d6e179ca9d6904..489679d8c0c681 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -83,6 +83,11 @@ secti
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/5] [clang] Enable sized deallocation by default in C++14
onwards
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
Differential Revision: https://reviews.llvm.org/D112921
---
.../clangd/unittests/FindTargetTests.cpp | 4 +-
.../checkers/misc/new-delete-overloads.cpp| 10 -
clang/docs/ReleaseNotes.rst | 5 +
clang/include/clang/Driver/Options.td | 5 +-
clang/lib/Driver/ToolChains/Clang.cpp | 13 +-
clang/lib/Driver/ToolChains/Darwin.cpp| 58 -
clang/lib/Driver/ToolChains/Darwin.h | 4 +
clang/lib/Driver/ToolChains/ZOS.cpp | 6 +
clang/test/AST/ast-dump-expr-json.cpp | 2 +-
clang/test/AST/ast-dump-expr.cpp | 2 +-
clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +-
.../basic.stc.dynamic.deallocation/p2.cpp | 2 +-
clang/test/CXX/drs/dr292.cpp | 17 +-
.../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +-
.../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +-
.../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +-
.../CodeGenCXX/cxx2a-destroying-delete.cpp| 4 +-
clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +-
clang/test/CodeGenCXX/delete.cpp | 12 +-
clang/test/CodeGenCXX/dllimport.cpp | 4 +-
clang/test/CodeGenCXX/new.cpp | 6 +-
.../coro-aligned-alloc-2.cpp | 2 -
.../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +-
clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 -
clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +-
clang/test/CodeGenCoroutines/pr56919.cpp | 9 +-
clang/test/Lexer/cxx-features.cpp | 20 +-
clang/test/PCH/cxx1z-aligned-alloc.cpp| 10 +-
clang/test/SemaCXX/MicrosoftExtensions.cpp| 8 +-
.../SemaCXX/builtin-operator-new-delete.cpp | 2 +-
.../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +-
.../unavailable_aligned_allocation.cpp| 15 +-
.../StaticAnalyzer/CallEventTest.cpp | 2 +-
clang/www/cxx_status.html | 11 +-
.../support.dynamic/libcpp_deallocate.sh.cpp | 3 +
.../sized_delete_array14.pass.cpp | 8 +-
.../new.delete.single/sized_delete14.pass.cpp | 8 +-
40 files changed, 436 insertions(+), 111 deletions(-)
diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
[[delete]] x;
}
)cpp";
- EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+ // Sized deallocation is enabled by default in C++14 onwards.
+ EXPECT_DECLS("CXXDeleteExpr",
+ "void operator delete(void *, unsigned long) noexcept");
}
TEST_F(TargetDeclTest, DependentExprs) {
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
// CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has
no matching declaration of 'operator delete' at the same scope
void *operator new(size_t size) noexcept(false);
-struct T {
- // Sized deallocations are not enabled by default, and so this new/delete
pair
- // does not match. However, we expect only one warning, for the new, because
- // the operator delete is a placement delete and we do not warn on
mismatching
- // placement operations.
- // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new'
has no matching declaration of 'operator delete' at the same scope
- void *operator new(size_t size) noexcept;
- void operator delete(void *ptr, size_t) noexcept; // ok only if sized
deallocation is enabled
-};
-
struct U {
void *operator new(size_t size) noexcept;
void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index d6e179ca9d6904..489679d8c0c681 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -83,6 +83,11 @@ secti
[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 --- clang/test/Driver/riscv-cpus.c| 319 ++ clang/test/Misc/target-invalid-cpu-note.c | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++- 3 files changed, 539 insertions(+), 12 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..a285f0f9c41f54 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -302,3 +302,322 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// Check profile CPUs + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s +// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s +// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s +// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+m" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+a" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+f" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+d" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+c" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s +// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s +// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicb
[clang] [llvm] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84448 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/84448 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
+
+ # RTTI/C++ symbols
+ set(clangInterpreter_exports ${clangInterpreter_exports} ??_7type_info@@6B@
+?__type_info_root_node@@3U__type_info_node@@A
+?nothrow@std@@3Unothrow_t@1@B
+ )
+
+ # Compiler added symbols for static variables. NOT for VStudio < 2015
+ set(clangInterpreter_exports ${clangInterpreter_exports} _Init_thread_abort
_Init_thread_epoch
+_Init_thread_footer _Init_thread_header _tls_index
+ )
+
+ if(CMAKE_SIZEOF_VOID_P EQUAL 8)
+# new/delete variants needed when linking to static msvc runtime (esp.
Debug)
+set(clangInterpreter_exports ${clangInterpreter_exports}
+ ??2@YAPEAX_K@Z
+ ??3@YAXPEAX@Z
+ ??_U@YAPEAX_K@Z
+ ??_V@YAXPEAX@Z
+ ??3@YAXPEAX_K@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z
+
??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z
+ ?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z
+)
+ else()
+set(clangInterpreter_exports ${clangInterpreter_exports}
+ ??2@YAPAXI@Z
+ ??3@YAXPAX@Z
+ ??3@YAXPAXI@Z
+ ??_U@YAPAXI@Z
+ ??_V@YAXPAX@Z
+ ??_V@YAXPAXI@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@H@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@M@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@N@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@PBX@Z
+
??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@P6AAAV01@AAV01@@Z@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@D@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@PBD@Z
+ ?_Facet_Register@std@@YAXPAV_Facet_base@1@@Z
+)
+ endif()
+
+ # List to '/EXPORT:sym0 /EXPORT:sym1 /EXPORT:sym2 ...'
+ foreach(sym ${clangInterpreter_exports})
+set(clangInterpreter_link_str "${clangInterpreter_link_str}
/EXPORT:${sym}")
+ endforeach(sym ${clangInterpreter_exports})
+
+ set_property(TARGET clangInterpreter APPEND_STRING PROPERTY LINK_FLAGS
${clangInterpreter_link_str})
+
+endif(MSVC)
wangpc-pp wrote:
It seems using `target_link_options ` doesn't work. So I added all exports to
`ClangReplInterpreterTests` and `clang-repl`.
https://github.com/llvm/llvm-project/pull/83774
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
wangpc-pp wrote: Windows CI is passed now, many thanks to @AaronBallman @vgvassilev! I may land this in a few days if there is no more comment. :-) https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
+
+ # RTTI/C++ symbols
+ set(clangInterpreter_exports ${clangInterpreter_exports} ??_7type_info@@6B@
+?__type_info_root_node@@3U__type_info_node@@A
+?nothrow@std@@3Unothrow_t@1@B
+ )
+
+ # Compiler added symbols for static variables. NOT for VStudio < 2015
+ set(clangInterpreter_exports ${clangInterpreter_exports} _Init_thread_abort
_Init_thread_epoch
+_Init_thread_footer _Init_thread_header _tls_index
+ )
+
+ if(CMAKE_SIZEOF_VOID_P EQUAL 8)
+# new/delete variants needed when linking to static msvc runtime (esp.
Debug)
+set(clangInterpreter_exports ${clangInterpreter_exports}
+ ??2@YAPEAX_K@Z
+ ??3@YAXPEAX@Z
+ ??_U@YAPEAX_K@Z
+ ??_V@YAXPEAX@Z
+ ??3@YAXPEAX_K@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z
+
??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z
+ ?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z
+)
+ else()
+set(clangInterpreter_exports ${clangInterpreter_exports}
+ ??2@YAPAXI@Z
+ ??3@YAXPAX@Z
+ ??3@YAXPAXI@Z
+ ??_U@YAPAXI@Z
+ ??_V@YAXPAX@Z
+ ??_V@YAXPAXI@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@H@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@M@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@N@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@PBX@Z
+
??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@P6AAAV01@AAV01@@Z@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@D@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@PBD@Z
+ ?_Facet_Register@std@@YAXPAV_Facet_base@1@@Z
+)
+ endif()
+
+ # List to '/EXPORT:sym0 /EXPORT:sym1 /EXPORT:sym2 ...'
+ foreach(sym ${clangInterpreter_exports})
+set(clangInterpreter_link_str "${clangInterpreter_link_str}
/EXPORT:${sym}")
+ endforeach(sym ${clangInterpreter_exports})
+
+ set_property(TARGET clangInterpreter APPEND_STRING PROPERTY LINK_FLAGS
${clangInterpreter_link_str})
+
+endif(MSVC)
wangpc-pp wrote:
Yeah, I hope so. But I'm really not familiar with cmake. :-(
Maybe we can make it a TODO and fix it in #84769?
https://github.com/llvm/llvm-project/pull/83774
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
+
+ # RTTI/C++ symbols
+ set(clangInterpreter_exports ${clangInterpreter_exports} ??_7type_info@@6B@
+?__type_info_root_node@@3U__type_info_node@@A
+?nothrow@std@@3Unothrow_t@1@B
+ )
+
+ # Compiler added symbols for static variables. NOT for VStudio < 2015
+ set(clangInterpreter_exports ${clangInterpreter_exports} _Init_thread_abort
_Init_thread_epoch
+_Init_thread_footer _Init_thread_header _tls_index
+ )
+
+ if(CMAKE_SIZEOF_VOID_P EQUAL 8)
+# new/delete variants needed when linking to static msvc runtime (esp.
Debug)
+set(clangInterpreter_exports ${clangInterpreter_exports}
+ ??2@YAPEAX_K@Z
+ ??3@YAXPEAX@Z
+ ??_U@YAPEAX_K@Z
+ ??_V@YAXPEAX@Z
+ ??3@YAXPEAX_K@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z
+
??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z
+ ?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z
+)
+ else()
+set(clangInterpreter_exports ${clangInterpreter_exports}
+ ??2@YAPAXI@Z
+ ??3@YAXPAX@Z
+ ??3@YAXPAXI@Z
+ ??_U@YAPAXI@Z
+ ??_V@YAXPAX@Z
+ ??_V@YAXPAXI@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@H@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@M@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@N@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@PBX@Z
+
??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@P6AAAV01@AAV01@@Z@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@D@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@PBD@Z
+ ?_Facet_Register@std@@YAXPAV_Facet_base@1@@Z
+)
+ endif()
+
+ # List to '/EXPORT:sym0 /EXPORT:sym1 /EXPORT:sym2 ...'
+ foreach(sym ${clangInterpreter_exports})
+set(clangInterpreter_link_str "${clangInterpreter_link_str}
/EXPORT:${sym}")
+ endforeach(sym ${clangInterpreter_exports})
+
+ set_property(TARGET clangInterpreter APPEND_STRING PROPERTY LINK_FLAGS
${clangInterpreter_link_str})
+
+endif(MSVC)
wangpc-pp wrote:
See commit aae9c11511c6bd8b41cfc879cfe3197578d52068.
I tried to add these exports to `clangInterpreter` component and hoped these
link options can be transitive to its users like `clang-repl` and
`ClangReplInterpreterTests`. But it didn't work after
aae9c11511c6bd8b41cfc879cfe3197578d52068 because the unit tests were still
failed.
I am not a cmake expert, so I have to add exports to `clang-repl` and
`ClangReplInterpreterTests` to make sure unit tests are passed, but the cmake
code may be too duplicated in this way.
https://github.com/llvm/llvm-project/pull/83774
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
+
+ # RTTI/C++ symbols
+ set(clangInterpreter_exports ${clangInterpreter_exports} ??_7type_info@@6B@
+?__type_info_root_node@@3U__type_info_node@@A
+?nothrow@std@@3Unothrow_t@1@B
+ )
+
+ # Compiler added symbols for static variables. NOT for VStudio < 2015
+ set(clangInterpreter_exports ${clangInterpreter_exports} _Init_thread_abort
_Init_thread_epoch
+_Init_thread_footer _Init_thread_header _tls_index
+ )
+
+ if(CMAKE_SIZEOF_VOID_P EQUAL 8)
+# new/delete variants needed when linking to static msvc runtime (esp.
Debug)
+set(clangInterpreter_exports ${clangInterpreter_exports}
+ ??2@YAPEAX_K@Z
+ ??3@YAXPEAX@Z
+ ??_U@YAPEAX_K@Z
+ ??_V@YAXPEAX@Z
+ ??3@YAXPEAX_K@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z
+
??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z
+ ?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z
+)
+ else()
+set(clangInterpreter_exports ${clangInterpreter_exports}
+ ??2@YAPAXI@Z
+ ??3@YAXPAX@Z
+ ??3@YAXPAXI@Z
+ ??_U@YAPAXI@Z
+ ??_V@YAXPAX@Z
+ ??_V@YAXPAXI@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@H@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@M@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@N@Z
+ ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@PBX@Z
+
??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@P6AAAV01@AAV01@@Z@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@D@Z
+
??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@PBD@Z
+ ?_Facet_Register@std@@YAXPAV_Facet_base@1@@Z
+)
+ endif()
+
+ # List to '/EXPORT:sym0 /EXPORT:sym1 /EXPORT:sym2 ...'
+ foreach(sym ${clangInterpreter_exports})
+set(clangInterpreter_link_str "${clangInterpreter_link_str}
/EXPORT:${sym}")
+ endforeach(sym ${clangInterpreter_exports})
+
+ set_property(TARGET clangInterpreter APPEND_STRING PROPERTY LINK_FLAGS
${clangInterpreter_link_str})
+
+endif(MSVC)
wangpc-pp wrote:
Will this cmake duplication block this PR? Maybe we can fix it in the future?
https://github.com/llvm/llvm-project/pull/83774
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[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)
wangpc-pp wrote: Ping for comments. https://github.com/llvm/llvm-project/pull/79975 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][TableGen] Add Features to TargetBuiltin (PR #80279)
wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/80279 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][TableGen] Add Features to TargetBuiltin (PR #80279)
wangpc-pp wrote: > The changes seem reasonable to me but I'd feel more comfortable if the > functionality was also being used (so that we'd get test coverage verifying > its correctness). Do you think it would be reasonable to include the RISCV > changes as well? Yeah, I separated RISCV changes into another PR(https://github.com/llvm/llvm-project/pull/80280). https://github.com/llvm/llvm-project/pull/80279 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][TableGen] Add Features to TargetBuiltin (PR #80279)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/80279 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)
https://github.com/wangpc-pp commented: The code is OK I think. One question: how will these builtins be used? Are their semantics bound to specific extensions that extend MOPs? https://github.com/llvm/llvm-project/pull/79971 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
