[flang] [clang] [mlir] [clang-tools-extra] [libcxx] [libc] [compiler-rt] [llvm] [AsmWriter] Ensure getMnemonic doesn't return invalid pointers (PR #75783)
https://github.com/tmatheson-arm approved this pull request. LGMT, surprised this didn't blow up earlier. https://github.com/llvm/llvm-project/pull/75783 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/75947
- [AArch64] add missing test case for v9.4-A
- [AArch64] Add FEAT_PAuthLR assembler support
- [AArch64] Codegen support for FEAT_PAuthLR
>From 3b1722f0cf3c0dd80ca5736724c77c36608b112b Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From df263e1d4aab1f099cdedfdc37670eb17c65696c Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 9 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 517 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index d1dbced2466eae..f727da0fdb765d 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,8 +622,13 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
- "Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+ "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
//===--===//
// Architectures.
@@ -810,7 +815,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 690ac0dcda6212..cb63d8726744d4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class Clea
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From d3201659d87260acaf1d20a96705e290caf21693 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From 1d4208d53830e0ef8dadad9be12e7ef2b53c6190 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 516 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} = 0b1101011
[lldb] [clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From d3201659d87260acaf1d20a96705e290caf21693 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From 1d4208d53830e0ef8dadad9be12e7ef2b53c6190 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 516 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} = 0b1101011
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From a6039367acca5de4c925925c1cefc56097ae496a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From b84addbf39d1734f1b860dba1e9a6acab3558ae7 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 516 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} = 0b1101011
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From a6039367acca5de4c925925c1cefc56097ae496a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From a5baa372f55196fe6ac0fe7979fbd736ba82f411 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 29
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 517 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} = 0b1101011
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From 29eb3db45ac1782d6cdcff106bd6088f06bbc680 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From 6db8387da6aa6ad533559ee147e01b990c27deee Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 9 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 29
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 518 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index db92a94e40e4b5..97e92a57a7ff4b 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,8 +622,13 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
- "Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+"Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
//===--===//
// Architectures.
@@ -810,7 +815,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 690ac0dcda6212..cb63d8726744d4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string a
[clang] 92dc23c - [AArch64] add missing test case for v9.4-A
Author: Tomas Matheson Date: 2023-12-21T14:18:33Z New Revision: 92dc23c0e054183e8adf41aad2a2609cefc392c0 URL: https://github.com/llvm/llvm-project/commit/92dc23c0e054183e8adf41aad2a2609cefc392c0 DIFF: https://github.com/llvm/llvm-project/commit/92dc23c0e054183e8adf41aad2a2609cefc392c0.diff LOG: [AArch64] add missing test case for v9.4-A Added: Modified: clang/test/Preprocessor/aarch64-target-features.c Removed: diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index db89aa7b608ad5..b3da54162da04b 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -600,6 +600,7 @@ // RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s // RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s // RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s +// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s // RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s // CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1 // CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 5992ce9 - [AArch64] Codegen support for FEAT_PAuthLR
Author: Tomas Matheson Date: 2023-12-21T14:18:33Z New Revision: 5992ce90b8c0fac06436c3c86621fbf6d5398ee5 URL: https://github.com/llvm/llvm-project/commit/5992ce90b8c0fac06436c3c86621fbf6d5398ee5 DIFF: https://github.com/llvm/llvm-project/commit/5992ce90b8c0fac06436c3c86621fbf6d5398ee5.diff LOG: [AArch64] Codegen support for FEAT_PAuthLR - Adds a new +pc option to -mbranch-protection that will enable the use of PC as a diversifier in PAC branch protection code. - When +pauth-lr is enabled (-march=armv9.5a+pauth-lr) in combination with -mbranch-protection=pac-ret+pc, the new 9.5-a instructions (pacibsppc, retaasppc, etc) are used. Documentation for the relevant instructions can be found here: https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/ Co-authored-by: Lucas Prates Added: clang/test/Driver/aarch64-pauth-lr.c llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll Modified: clang/include/clang/Basic/LangOptions.def clang/include/clang/Basic/TargetInfo.h clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/AArch64.cpp clang/lib/Basic/Targets/ARM.cpp clang/lib/CodeGen/CodeGenModule.cpp clang/lib/CodeGen/Targets/AArch64.cpp clang/lib/Driver/ToolChains/Clang.cpp clang/test/CodeGen/aarch64-branch-protection-attr.c clang/test/Driver/aarch64-v95a.c llvm/include/llvm/TargetParser/AArch64TargetParser.h llvm/include/llvm/TargetParser/ARMTargetParserCommon.h llvm/lib/Target/AArch64/AArch64InstrInfo.cpp llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h llvm/lib/Target/AArch64/AArch64PointerAuth.cpp llvm/lib/TargetParser/ARMTargetParserCommon.cpp llvm/test/CodeGen/AArch64/sign-return-address.ll llvm/unittests/TargetParser/TargetParserTest.cpp Removed: diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 152d9f65f86dbe..21abc346cf17ac 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -456,6 +456,7 @@ ENUM_LANGOPT(SignReturnAddressScope, SignReturnAddressScopeKind, 2, SignReturnAd ENUM_LANGOPT(SignReturnAddressKey, SignReturnAddressKeyKind, 1, SignReturnAddressKeyKind::AKey, "Key used for return address signing") LANGOPT(BranchTargetEnforcement, 1, 0, "Branch-target enforcement enabled") +LANGOPT(BranchProtectionPAuthLR, 1, 0, "Use PC as a diversifier using PAuthLR NOP instructions.") LANGOPT(SpeculativeLoadHardening, 1, 0, "Speculative load hardening enabled") diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index aa0f5023104a1a..ac3c324c6c29c4 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -1372,6 +1372,7 @@ class TargetInfo : public TransferrableTargetInfo, LangOptions::SignReturnAddressKeyKind SignKey = LangOptions::SignReturnAddressKeyKind::AKey; bool BranchTargetEnforcement = false; +bool BranchProtectionPAuthLR = false; }; /// Determine if the Architecture in this TargetInfo supports branch diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 1b02087425b751..965d402af2d7b3 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6999,6 +6999,8 @@ def msign_return_address_key_EQ : Joined<["-"], "msign-return-address-key=">, Values<"a_key,b_key">; def mbranch_target_enforce : Flag<["-"], "mbranch-target-enforce">, MarshallingInfoFlag>; +def mbranch_protection_pauth_lr : Flag<["-"], "mbranch-protection-pauth-lr">, + MarshallingInfoFlag>; def fno_dllexport_inlines : Flag<["-"], "fno-dllexport-inlines">, MarshallingInfoNegativeFlag>; def cfguard_no_checks : Flag<["-"], "cfguard-no-checks">, diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index def16c032c869e..3ee39133fcee72 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -225,6 +225,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef, BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey; BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement; + BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR; return true; } diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index ce7e4d4639ceac..6e1842fc64e505 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -419,6 +419,7 @@ bool ARMTargetInfo::validateBranchProtection(StringRef Spec, StringRef Arch, BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey; BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement; + BPI.BranchProtectionPAuthLR = PBP.BranchProtec
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
tmatheson-arm wrote: Manually merged to avoid squashing the commits: 92dc23c0e054183e8adf41aad2a2609cefc392c0 934b1099cbf14fa3f86a269dff957da8e5fb619f 5992ce90b8c0fac06436c3c86621fbf6d5398ee5 https://github.com/llvm/llvm-project/pull/75947 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/75947 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 9f0f558 - Revert "[AArch64] Codegen support for FEAT_PAuthLR"
Author: Tomas Matheson
Date: 2023-12-21T16:25:55Z
New Revision: 9f0f5587426a4ff24b240018cf8bf3acc3c566ae
URL:
https://github.com/llvm/llvm-project/commit/9f0f5587426a4ff24b240018cf8bf3acc3c566ae
DIFF:
https://github.com/llvm/llvm-project/commit/9f0f5587426a4ff24b240018cf8bf3acc3c566ae.diff
LOG: Revert "[AArch64] Codegen support for FEAT_PAuthLR"
This reverts commit 5992ce90b8c0fac06436c3c86621fbf6d5398ee5.
Builtbot failures with expensive checks enabled.
Added:
Modified:
clang/include/clang/Basic/LangOptions.def
clang/include/clang/Basic/TargetInfo.h
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/CodeGen/Targets/AArch64.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/CodeGen/aarch64-branch-protection-attr.c
clang/test/Driver/aarch64-v95a.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/include/llvm/TargetParser/ARMTargetParserCommon.h
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
llvm/lib/TargetParser/ARMTargetParserCommon.cpp
llvm/test/CodeGen/AArch64/sign-return-address.ll
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
clang/test/Driver/aarch64-pauth-lr.c
llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
diff --git a/clang/include/clang/Basic/LangOptions.def
b/clang/include/clang/Basic/LangOptions.def
index 21abc346cf17ac..152d9f65f86dbe 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -456,7 +456,6 @@ ENUM_LANGOPT(SignReturnAddressScope,
SignReturnAddressScopeKind, 2, SignReturnAd
ENUM_LANGOPT(SignReturnAddressKey, SignReturnAddressKeyKind, 1,
SignReturnAddressKeyKind::AKey,
"Key used for return address signing")
LANGOPT(BranchTargetEnforcement, 1, 0, "Branch-target enforcement enabled")
-LANGOPT(BranchProtectionPAuthLR, 1, 0, "Use PC as a diversifier using PAuthLR
NOP instructions.")
LANGOPT(SpeculativeLoadHardening, 1, 0, "Speculative load hardening enabled")
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index ac3c324c6c29c4..aa0f5023104a1a 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1372,7 +1372,6 @@ class TargetInfo : public TransferrableTargetInfo,
LangOptions::SignReturnAddressKeyKind SignKey =
LangOptions::SignReturnAddressKeyKind::AKey;
bool BranchTargetEnforcement = false;
-bool BranchProtectionPAuthLR = false;
};
/// Determine if the Architecture in this TargetInfo supports branch
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 2b93ddf033499c..9678165bfd98e8 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -7000,8 +7000,6 @@ def msign_return_address_key_EQ : Joined<["-"],
"msign-return-address-key=">,
Values<"a_key,b_key">;
def mbranch_target_enforce : Flag<["-"], "mbranch-target-enforce">,
MarshallingInfoFlag>;
-def mbranch_protection_pauth_lr : Flag<["-"], "mbranch-protection-pauth-lr">,
- MarshallingInfoFlag>;
def fno_dllexport_inlines : Flag<["-"], "fno-dllexport-inlines">,
MarshallingInfoNegativeFlag>;
def cfguard_no_checks : Flag<["-"], "cfguard-no-checks">,
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 3ee39133fcee72..def16c032c869e 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -225,7 +225,6 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
- BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
return true;
}
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 6e1842fc64e505..ce7e4d4639ceac 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -419,7 +419,6 @@ bool ARMTargetInfo::validateBranchProtection(StringRef
Spec, StringRef Arch,
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
- BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
return true;
}
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index d78f2594a23764..b2e173d0d6949e 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1106,9 +1106,6 @@ void CodeGenModule::Release() {
if (LangOpts.BranchTargetEnforcement)
[clang] 7bd1721 - Re-land "[AArch64] Codegen support for FEAT_PAuthLR" (#75947)
Author: Tomas Matheson
Date: 2023-12-21T18:32:55Z
New Revision: 7bd17212ef23a72ea224a037126d33d3e02553fe
URL:
https://github.com/llvm/llvm-project/commit/7bd17212ef23a72ea224a037126d33d3e02553fe
DIFF:
https://github.com/llvm/llvm-project/commit/7bd17212ef23a72ea224a037126d33d3e02553fe.diff
LOG: Re-land "[AArch64] Codegen support for FEAT_PAuthLR" (#75947)
This reverts commit 9f0f5587426a4ff24b240018cf8bf3acc3c566ae.
Fix expensive checks failure by properly marking register def for ADR.
Added:
clang/test/Driver/aarch64-pauth-lr.c
llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
Modified:
clang/include/clang/Basic/LangOptions.def
clang/include/clang/Basic/TargetInfo.h
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/CodeGen/Targets/AArch64.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/CodeGen/aarch64-branch-protection-attr.c
clang/test/Driver/aarch64-v95a.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/include/llvm/TargetParser/ARMTargetParserCommon.h
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
llvm/lib/TargetParser/ARMTargetParserCommon.cpp
llvm/test/CodeGen/AArch64/sign-return-address.ll
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
diff --git a/clang/include/clang/Basic/LangOptions.def
b/clang/include/clang/Basic/LangOptions.def
index 152d9f65f86dbe..21abc346cf17ac 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -456,6 +456,7 @@ ENUM_LANGOPT(SignReturnAddressScope,
SignReturnAddressScopeKind, 2, SignReturnAd
ENUM_LANGOPT(SignReturnAddressKey, SignReturnAddressKeyKind, 1,
SignReturnAddressKeyKind::AKey,
"Key used for return address signing")
LANGOPT(BranchTargetEnforcement, 1, 0, "Branch-target enforcement enabled")
+LANGOPT(BranchProtectionPAuthLR, 1, 0, "Use PC as a diversifier using PAuthLR
NOP instructions.")
LANGOPT(SpeculativeLoadHardening, 1, 0, "Speculative load hardening enabled")
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index aa0f5023104a1a..ac3c324c6c29c4 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1372,6 +1372,7 @@ class TargetInfo : public TransferrableTargetInfo,
LangOptions::SignReturnAddressKeyKind SignKey =
LangOptions::SignReturnAddressKeyKind::AKey;
bool BranchTargetEnforcement = false;
+bool BranchProtectionPAuthLR = false;
};
/// Determine if the Architecture in this TargetInfo supports branch
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 9678165bfd98e8..2b93ddf033499c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -7000,6 +7000,8 @@ def msign_return_address_key_EQ : Joined<["-"],
"msign-return-address-key=">,
Values<"a_key,b_key">;
def mbranch_target_enforce : Flag<["-"], "mbranch-target-enforce">,
MarshallingInfoFlag>;
+def mbranch_protection_pauth_lr : Flag<["-"], "mbranch-protection-pauth-lr">,
+ MarshallingInfoFlag>;
def fno_dllexport_inlines : Flag<["-"], "fno-dllexport-inlines">,
MarshallingInfoNegativeFlag>;
def cfguard_no_checks : Flag<["-"], "cfguard-no-checks">,
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index def16c032c869e..3ee39133fcee72 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -225,6 +225,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
+ BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
return true;
}
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index ce7e4d4639ceac..6e1842fc64e505 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -419,6 +419,7 @@ bool ARMTargetInfo::validateBranchProtection(StringRef
Spec, StringRef Arch,
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
+ BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
return true;
}
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index b2e173d0d6949e..d78f2594a23764 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1106,6 +1106,9 @@ void CodeGenModule::Release() {
if (LangOpt
[llvm] [clang] [AArch64] Assembly support for the Armv9.5-A Memory System Extensions (PR #76237)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76237 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/83277 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [NFC][ARM][AArch64] Deduplicated code. (PR #82785)
@@ -1369,13 +1369,20 @@ class TargetInfo : public TransferrableTargetInfo,
}
struct BranchProtectionInfo {
-LangOptions::SignReturnAddressScopeKind SignReturnAddr =
-LangOptions::SignReturnAddressScopeKind::None;
-LangOptions::SignReturnAddressKeyKind SignKey =
-LangOptions::SignReturnAddressKeyKind::AKey;
-bool BranchTargetEnforcement = false;
-bool BranchProtectionPAuthLR = false;
-bool GuardedControlStack = false;
+LangOptions::SignReturnAddressScopeKind SignReturnAddr;
+LangOptions::SignReturnAddressKeyKind SignKey;
+bool BranchTargetEnforcement;
+bool BranchProtectionPAuthLR;
+bool GuardedControlStack;
+
+BranchProtectionInfo() = default;
+
+const char *getSignReturnAddrStr() const {
+ static const char *SignReturnAddrStr[] = {"none", "non-leaf", "all"};
+ assert(static_cast(SignReturnAddr) <= 2 &&
+ "Unexpected SignReturnAddressScopeKind");
+ return SignReturnAddrStr[static_cast(SignReturnAddr)];
+}
tmatheson-arm wrote:
```suggestion
const char *getSignReturnAddrStr() const {
switch (SignReturnAddr) {
case None:
return "none";
case NonLeaf:
return "non-leaf";
case All:
return "all";
}
assert(false && "Unexpected SignReturnAddressScopeKind");
}
```
https://github.com/llvm/llvm-project/pull/82785
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[clang] [NFC][ARM][AArch64] Deduplicated code. (PR #82785)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/82785 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/83277 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [flang] [clang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
https://github.com/tmatheson-arm commented: This looks like a great improvement over the existing system to me. https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -3,8 +3,7 @@ // FEAT_D128 is optional (off by default) for v9.4a and older, and can be enabled using +d128 // RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a%s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a+d128 %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a+nod128 %s 2>&1 | FileCheck %s --check-prefix=DISABLED +// RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a+nod128 %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // ENABLED: "-target-feature" "+d128" // NOT_ENABLED-NOT: "-target-feature" "+d128" -// DISABLED: "-target-feature" "-d128" tmatheson-arm wrote: So features that are explicitly disabled with a `+noXYZ` will no longer appear in the `-cc1` command line as `-taget-feature -XYZ`? Is that always the case, what about for features that are on by default? https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -308,6 +312,104 @@ inline constexpr ExtensionInfo Extensions[] = {
};
// clang-format on
+struct ExtensionSet {
+ // Set of extensions which are currently enabled.
+ ExtensionBitset Enabled;
+ // Set of extensions which have been enabled or disabled at any point. Used
+ // to avoid cluttering the cc1 command-line with lots of unneeded features.
+ ExtensionBitset Touched;
+ // Base architecture version, which we need to know because some feature
+ // dependencies change depending on this.
+ const ArchInfo *BaseArch;
+
+ ExtensionSet() : Enabled(), Touched(), BaseArch(nullptr) {}
+
+ // Enable the given architecture extension, and any other extensions it
+ // depends on. Does not change the base architecture, or follow dependencies
+ // between features which are only related by required arcitecture versions.
+ void enable(ArchExtKind E);
+
+ // Disable the given architecture extension, and any other extensions which
+ // depend on it. Does not change the base architecture, or follow
+ // dependencies between features which are only related by required
+ // arcitecture versions.
+ void disable(ArchExtKind E);
+
+ // Add default extensions for the given CPU. Records the base architecture,
+ // to later resolve dependencies which depend on it.
+ void addCPUDefaults(const CpuInfo &CPU);
+
+ // Add default extensions for the given architecture version. Records the
+ // base architecture, to later resolve dependencies which depend on it.
+ void addArchDefaults(const ArchInfo &Arch);
+
+ // Add or remove a feature based on a modifier string. The string must be of
tmatheson-arm wrote:
I'm a bit unclear on the terminology. Often "extension" is taken to mean
something which has an entry in `ArchExtKind`, whereas "feature" is an LLVM
backend feature. In the Arm ARM they are referred to as extensions and there is
no concept of features.
Should this be "Add or remove an extension"?
https://github.com/llvm/llvm-project/pull/78270
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[flang] [clang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,20 +1,21 @@ // RAS is off by default for v8a, but can be enabled by +ras (this is not architecturally valid) // RUN: %clang --target=aarch64-none-elf -march=armv8a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s +// RUN: %clang --target=aarch64-none-elf -march=armv8.2a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -march=armv8-a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=generic+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // CHECK-RAS: "-target-feature" "+ras" -// RUN: %clang --target=aarch64-none-elf -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s -// RUN: %clang --target=aarch64-none-elf -mcpu=generic+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s -// CHECK-NORAS: "-target-feature" "-ras" +// RUN: %clang --target=aarch64-none-elf -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ABSENT %s +// RUN: %clang --target=aarch64-none-elf -mcpu=generic+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ABSENT %s +// CHECK-ABSENT-NOT: "-target-feature" ++ras" tmatheson-arm wrote: typo? https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ return E;
+ assert(false && "Invalid extension ID");
+}
+
+void AArch64::ExtensionSet::enable(ArchExtKind E) {
+ if (Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+
+ Touched.set(E);
+ Enabled.set(E);
+
+ // Recursively enable all features that this one depends on. This handles all
+ // of the simple cases, where the behaviour doesn't depend on the base
+ // architecture version.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Later)
+ enable(Dep.Earlier);
+
+ // Special cases for dependencies which vary depending on the base
+ // architecture version.
+ if (BaseArch) {
+// +sve implies +f32mm if the base architecture is v8.6A+ or v9.1A+
+// It isn't the case in general that sve implies both f64mm and f32mm
+if (E == AEK_SVE && BaseArch->is_superset(ARMV8_6A))
+ enable(AEK_F32MM);
+
+// +fp16 implies +fp16fml for v8.4A+, but not v9.0-A+
+if (E == AEK_FP16 && BaseArch->is_superset(ARMV8_4A) &&
+!BaseArch->is_superset(ARMV9A))
+ enable(AEK_FP16FML);
+
+// For all architectures, +crypto enables +aes and +sha2.
+if (E == AEK_CRYPTO) {
+ enable(AEK_AES);
+ enable(AEK_SHA2);
+}
+
+// For v8.4A+ and v9.0A+, +crypto also enables +sha3 and +sm4.
+if (E == AEK_CRYPTO && BaseArch->is_superset(ARMV8_4A)) {
+ enable(AEK_SHA3);
+ enable(AEK_SM4);
+}
+ }
+}
+
+void AArch64::ExtensionSet::disable(ArchExtKind E) {
+ // -crypto always disables aes, sha2, sha3 and sm4, even for architectures
+ // where the latter two would not be enabled by +crypto.
+ if (E == AEK_CRYPTO) {
+disable(AEK_AES);
+disable(AEK_SHA2);
+disable(AEK_SHA3);
+disable(AEK_SM4);
+ }
+
+ if (!Enabled.test(E))
+return;
tmatheson-arm wrote:
Does it matter that this won't disable dependent extensions, like it would do
if the current extension was enabled?
https://github.com/llvm/llvm-project/pull/78270
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[clang] [llvm] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,25 +1,25 @@
// RUN: %clang --target=aarch64 -### -c %s 2>&1 | FileCheck
-check-prefix=GENERIC-V8A %s
// RUN: %clang --target=aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck
-check-prefix=GENERIC-V8A %s
-// GENERIC-V8A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic" "-target-feature" "+neon" "-target-feature" "+v8a"
+// GENERIC-V8A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic" "-target-feature" "+v8a"
tmatheson-arm wrote:
Is something specific happening with neon/noneon, and shouldn't it be checked
for here?
https://github.com/llvm/llvm-project/pull/78270
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[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ return E;
+ assert(false && "Invalid extension ID");
+}
+
+void AArch64::ExtensionSet::enable(ArchExtKind E) {
+ if (Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+
+ Touched.set(E);
+ Enabled.set(E);
+
+ // Recursively enable all features that this one depends on. This handles all
+ // of the simple cases, where the behaviour doesn't depend on the base
+ // architecture version.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Later)
+ enable(Dep.Earlier);
tmatheson-arm wrote:
One concern I have is that `ExtensionDependencies` expresses the dependencies
as a directed graph, but in reality we probably just want a tree, as this code
assumes.
https://github.com/llvm/llvm-project/pull/78270
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[llvm] [flang] [clang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,9 +1,9 @@ // RUN: %clang -### --target=aarch64-none-elf -march=armv8.4a+memtag %s 2>&1 | FileCheck %s // RUN: %clang -### --target=aarch64-none-elf -march=armv8.5a+memtag %s 2>&1 | FileCheck %s +// RUN: %clang -### --target=aarch64-none-elf -mcpu=cortex-a510 %s 2>&1 | FileCheck %s // CHECK: "-target-feature" "+mte" -// RUN: %clang -### --target=aarch64-none-elf -march=armv8.4a+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE -// RUN: %clang -### --target=aarch64-none-elf -march=armv8.5a+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE +// RUN: %clang -### --target=aarch64-none-elf -mcpu=cortex-a510+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE tmatheson-arm wrote: This seems like a material change to what is being tested, it might be better split out. (Applies to several files where `-march` has been substituted with `-mcpu`) https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ return E;
+ assert(false && "Invalid extension ID");
+}
+
+void AArch64::ExtensionSet::enable(ArchExtKind E) {
+ if (Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+
+ Touched.set(E);
+ Enabled.set(E);
+
+ // Recursively enable all features that this one depends on. This handles all
+ // of the simple cases, where the behaviour doesn't depend on the base
+ // architecture version.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Later)
+ enable(Dep.Earlier);
+
+ // Special cases for dependencies which vary depending on the base
+ // architecture version.
+ if (BaseArch) {
+// +sve implies +f32mm if the base architecture is v8.6A+ or v9.1A+
+// It isn't the case in general that sve implies both f64mm and f32mm
+if (E == AEK_SVE && BaseArch->is_superset(ARMV8_6A))
+ enable(AEK_F32MM);
+
+// +fp16 implies +fp16fml for v8.4A+, but not v9.0-A+
+if (E == AEK_FP16 && BaseArch->is_superset(ARMV8_4A) &&
+!BaseArch->is_superset(ARMV9A))
+ enable(AEK_FP16FML);
+
+// For all architectures, +crypto enables +aes and +sha2.
+if (E == AEK_CRYPTO) {
+ enable(AEK_AES);
+ enable(AEK_SHA2);
+}
+
+// For v8.4A+ and v9.0A+, +crypto also enables +sha3 and +sm4.
+if (E == AEK_CRYPTO && BaseArch->is_superset(ARMV8_4A)) {
+ enable(AEK_SHA3);
+ enable(AEK_SM4);
+}
+ }
+}
+
+void AArch64::ExtensionSet::disable(ArchExtKind E) {
+ // -crypto always disables aes, sha2, sha3 and sm4, even for architectures
+ // where the latter two would not be enabled by +crypto.
+ if (E == AEK_CRYPTO) {
+disable(AEK_AES);
+disable(AEK_SHA2);
+disable(AEK_SHA3);
+disable(AEK_SM4);
+ }
+
+ if (!Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Disable " << lookupExtensionByID(E).Name <<
"\n");
+
+ Touched.set(E);
+ Enabled.reset(E);
+
+ // Recursively disable all features that depends on this one.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Earlier)
+ disable(Dep.Later);
+}
+
+void AArch64::ExtensionSet::toLLVMFeatureList(
+std::vector &Features) const {
+ if (BaseArch && !BaseArch->ArchFeature.empty())
+Features.push_back(BaseArch->ArchFeature);
+
+ for (const auto &E : Extensions) {
+if (E.Feature.empty() || !Touched.test(E.ID))
+ continue;
+if (Enabled.test(E.ID))
+ Features.push_back(E.Feature);
+else
+ Features.push_back(E.NegFeature);
tmatheson-arm wrote:
When exactly do we need negative features?
https://github.com/llvm/llvm-project/pull/78270
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[flang] [clang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -711,10 +819,10 @@ StringRef getArchExtFeature(StringRef ArchExt); StringRef resolveCPUAlias(StringRef CPU); // Information by Name -std::optional getArchForCpu(StringRef CPU); tmatheson-arm wrote: Why the switch back to raw pointers from std::optional? This seems to undo what was done in https://reviews.llvm.org/D142539 Does this new implementation rely on there being one global copy of `ArchInfo`? A while back I tried to make this work so that `ArchInfo::operator==` made use of this address, but that ended up being unworkable so we switched to allowing copying of `ArchInfo` objects. https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,49 +1,51 @@
// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme %s -### 2>&1 |
FileCheck %s --check-prefix=SME-IMPLY
-// SME-IMPLY: "-target-feature" "+sme" "-target-feature" "+bf16"
+// SME-IMPLY: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme"
// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme %s -### 2>&1 |
FileCheck %s --check-prefix=NOSME
-// NOSME: "-target-feature" "-sme"
+// NOSME-NOT: "-target-feature" "{{\+|-}}sme"
// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosme %s -### 2>&1
| FileCheck %s --check-prefix=SME-REVERT
// SME-REVERT-NOT: "-target-feature" "+sme"
-// SME-REVERT: "-target-feature" "+bf16" "-target-feature" "-sme"
"-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+// SME-REVERT: "-target-feature" "+bf16"{{.*}} "-target-feature" "-sme"
tmatheson-arm wrote:
So here, `+sme+nosme` should no longer explicitly remove `sme-f64f64` etc,
which are dependencies of `+sme`, instead they default to off and are not
mentioned on the `-cc1` command line? In other words, there is no behaviour
change here, iiuc.
Do we have any later checks that the features are reassembled correctly? Checks
for preprocessor macros maybe.
https://github.com/llvm/llvm-project/pull/78270
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[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -308,6 +312,104 @@ inline constexpr ExtensionInfo Extensions[] = {
};
// clang-format on
+struct ExtensionSet {
+ // Set of extensions which are currently enabled.
+ ExtensionBitset Enabled;
+ // Set of extensions which have been enabled or disabled at any point. Used
+ // to avoid cluttering the cc1 command-line with lots of unneeded features.
+ ExtensionBitset Touched;
+ // Base architecture version, which we need to know because some feature
+ // dependencies change depending on this.
+ const ArchInfo *BaseArch;
tmatheson-arm wrote:
What does this point to exactly? What owns the thing it points to?
https://github.com/llvm/llvm-project/pull/78270
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[clang] [llvm] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,20 +1,21 @@ // RAS is off by default for v8a, but can be enabled by +ras (this is not architecturally valid) // RUN: %clang --target=aarch64-none-elf -march=armv8a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s +// RUN: %clang --target=aarch64-none-elf -march=armv8.2a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -march=armv8-a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=generic+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // CHECK-RAS: "-target-feature" "+ras" -// RUN: %clang --target=aarch64-none-elf -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s -// RUN: %clang --target=aarch64-none-elf -mcpu=generic+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s -// CHECK-NORAS: "-target-feature" "-ras" +// RUN: %clang --target=aarch64-none-elf -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ABSENT %s +// RUN: %clang --target=aarch64-none-elf -mcpu=generic+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ABSENT %s +// CHECK-ABSENT-NOT: "-target-feature" ++ras" // RAS is on by default for v8.2a, but can be disabled by +noras -// FIXME: in the current implementation, RAS is not on by default at all for v8.2a (the test says it all...) -// RUN: %clang --target=aarch64 -march=armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=V82ARAS %s -// RUN: %clang --target=aarch64 -march=armv8.2-a -### -c %s 2>&1 | FileCheck -check-prefix=V82ARAS %s +// RUN: %clang --target=aarch64 -march=armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-RAS %s +// RUN: %clang --target=aarch64 -march=armv8.2-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-RAS %s // V82ARAS-NOT: "-target-feature" "+ras" // V82ARAS-NOT: "-target-feature" "-ras" tmatheson-arm wrote: This check-prefix is no longer in use https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -3,15 +3,14 @@ // FEAT_ITE is optional (off by default) for v8.9a/9.4a and older, and can be enabled using +ite // RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a+ite %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a+noite %s 2>&1 | FileCheck %s --check-prefix=DISABLED +// RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a+noite %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // RUN: %clang -### --target=aarch64-none-elf -march=armv9.3-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // RUN: %clang -### --target=aarch64-none-elf -march=armv9.3-a+ite %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### --target=aarch64-none-elf -march=armv9.3-a+noite %s 2>&1 | FileCheck %s --check-prefix=DISABLED +// RUN: %clang -### --target=aarch64-none-elf -march=armv9.3-a+noite %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // FEAT_ITE is invalid before v8 // RUN: not %clang -### --target=arm-none-none-eabi -march=armv7-a+ite %s 2>&1 | FileCheck %s --check-prefix=INVALID // INVALID: error: unsupported argument 'armv7-a+ite' to option '-march=' // ENABLED: "-target-feature" "+ite" // NOT_ENABLED-NOT: "-target-feature" "+ite" tmatheson-arm wrote: Should this also check that the negative case isn't present? (Applies to many other files too.) https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [llvm] [clang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ return E;
+ assert(false && "Invalid extension ID");
+}
+
+void AArch64::ExtensionSet::enable(ArchExtKind E) {
+ if (Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+
+ Touched.set(E);
+ Enabled.set(E);
+
+ // Recursively enable all features that this one depends on. This handles all
+ // of the simple cases, where the behaviour doesn't depend on the base
+ // architecture version.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Later)
+ enable(Dep.Earlier);
+
+ // Special cases for dependencies which vary depending on the base
+ // architecture version.
+ if (BaseArch) {
+// +sve implies +f32mm if the base architecture is v8.6A+ or v9.1A+
+// It isn't the case in general that sve implies both f64mm and f32mm
+if (E == AEK_SVE && BaseArch->is_superset(ARMV8_6A))
+ enable(AEK_F32MM);
+
+// +fp16 implies +fp16fml for v8.4A+, but not v9.0-A+
+if (E == AEK_FP16 && BaseArch->is_superset(ARMV8_4A) &&
+!BaseArch->is_superset(ARMV9A))
+ enable(AEK_FP16FML);
+
+// For all architectures, +crypto enables +aes and +sha2.
+if (E == AEK_CRYPTO) {
+ enable(AEK_AES);
+ enable(AEK_SHA2);
+}
+
+// For v8.4A+ and v9.0A+, +crypto also enables +sha3 and +sm4.
+if (E == AEK_CRYPTO && BaseArch->is_superset(ARMV8_4A)) {
+ enable(AEK_SHA3);
+ enable(AEK_SM4);
+}
+ }
tmatheson-arm wrote:
This logic is so much nicer than what we currently have.
https://github.com/llvm/llvm-project/pull/78270
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[clang] 01b9e61 - [Clang][Codegen] Truncate initializers of union bitfield members
Author: Tomas Matheson
Date: 2021-01-28T09:19:19Z
New Revision: 01b9e613c28b833327ab4de93d0638a5c8d3514f
URL:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f
DIFF:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f.diff
LOG: [Clang][Codegen] Truncate initializers of union bitfield members
If an initial value is given for a bitfield that does not fit in the
bitfield, the value should be truncated. Constant folding for
expressions did not account for this truncation in the case of union
member functions, despite a warning being emitted. In some contexts,
evaluation of expressions was not enabled unless C++11, ROPI or RWPI
was enabled.
Differential Revision: https://reviews.llvm.org/D93101
Added:
Modified:
clang/lib/AST/ExprConstant.cpp
clang/test/CodeGenCXX/bitfield-layout.cpp
Removed:
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index c1973720e49a..0f0c33b0ac85 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -9798,7 +9798,14 @@ bool RecordExprEvaluator::VisitInitListExpr(const
InitListExpr *E) {
ThisOverrideRAII ThisOverride(*Info.CurrentCall, &This,
isa(InitExpr));
-return EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr);
+if (EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr)) {
+ if (Field->isBitField())
+return truncateBitfieldValue(Info, InitExpr, Result.getUnionValue(),
+ Field);
+ return true;
+}
+
+return false;
}
if (!Result.hasValue())
diff --git a/clang/test/CodeGenCXX/bitfield-layout.cpp
b/clang/test/CodeGenCXX/bitfield-layout.cpp
index 49b196253f3c..79dbf9c691c4 100644
--- a/clang/test/CodeGenCXX/bitfield-layout.cpp
+++ b/clang/test/CodeGenCXX/bitfield-layout.cpp
@@ -2,6 +2,7 @@
// RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 |
FileCheck %s
// RUN: %clang_cc1 %s -triple=aarch64_be-none-eabi -emit-llvm -o - -O3 |
FileCheck %s
// RUN: %clang_cc1 %s -triple=thumbv7_be-none-eabi -emit-llvm -o - -O3 |
FileCheck %s
+// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -emit-llvm -o - -O3
-std=c++11 | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LP64 %s
// CHECK-LP64: %union.Test1 = type { i32, [4 x i8] }
union Test1 {
@@ -84,3 +85,68 @@ int test_init() {
// CHECK: ret i32 0
return 0;
}
+
+extern "C" {
+int test_trunc_int() {
+ union {
+int i : 4; // truncated to 0b == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_int()
+// CHECK: ret i32 -1
+
+int test_trunc_three_bits() {
+ union {
+int i : 3; // truncated to 0b111 == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_three_bits()
+// CHECK: ret i32 -1
+
+int test_trunc_1() {
+ union {
+int i : 1; // truncated to 0b1 == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_1()
+// CHECK: ret i32 -1
+
+int test_trunc_zero() {
+ union {
+int i : 4; // truncated to 0b == 0
+ } const U = {80}; // 0b0101
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_zero()
+// CHECK: ret i32 0
+
+int test_constexpr() {
+ union {
+int i : 3; // truncated to 0b111 == -1
+ } const U = {1 + 2 + 4 + 8}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_constexpr()
+// CHECK: ret i32 -1
+
+int test_notrunc() {
+ union {
+int i : 12; // not truncated
+ } const U = {1 + 2 + 4 + 8}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_notrunc()
+// CHECK: ret i32 15
+
+long long test_trunc_long_long() {
+ union {
+long long i : 14; // truncated to 0b0001001101 ==
+ } const U = {0b010001001101};
+ return U.i;
+}
+// CHECK: define dso_local i64 @test_trunc_long_long()
+// CHECK: ret i64 3917
+}
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[clang] 01b9e61 - [Clang][Codegen] Truncate initializers of union bitfield members
Author: Tomas Matheson
Date: 2021-01-28T09:19:19Z
New Revision: 01b9e613c28b833327ab4de93d0638a5c8d3514f
URL:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f
DIFF:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f.diff
LOG: [Clang][Codegen] Truncate initializers of union bitfield members
If an initial value is given for a bitfield that does not fit in the
bitfield, the value should be truncated. Constant folding for
expressions did not account for this truncation in the case of union
member functions, despite a warning being emitted. In some contexts,
evaluation of expressions was not enabled unless C++11, ROPI or RWPI
was enabled.
Differential Revision: https://reviews.llvm.org/D93101
Added:
Modified:
clang/lib/AST/ExprConstant.cpp
clang/test/CodeGenCXX/bitfield-layout.cpp
Removed:
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index c1973720e49a..0f0c33b0ac85 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -9798,7 +9798,14 @@ bool RecordExprEvaluator::VisitInitListExpr(const
InitListExpr *E) {
ThisOverrideRAII ThisOverride(*Info.CurrentCall, &This,
isa(InitExpr));
-return EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr);
+if (EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr)) {
+ if (Field->isBitField())
+return truncateBitfieldValue(Info, InitExpr, Result.getUnionValue(),
+ Field);
+ return true;
+}
+
+return false;
}
if (!Result.hasValue())
diff --git a/clang/test/CodeGenCXX/bitfield-layout.cpp
b/clang/test/CodeGenCXX/bitfield-layout.cpp
index 49b196253f3c..79dbf9c691c4 100644
--- a/clang/test/CodeGenCXX/bitfield-layout.cpp
+++ b/clang/test/CodeGenCXX/bitfield-layout.cpp
@@ -2,6 +2,7 @@
// RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 |
FileCheck %s
// RUN: %clang_cc1 %s -triple=aarch64_be-none-eabi -emit-llvm -o - -O3 |
FileCheck %s
// RUN: %clang_cc1 %s -triple=thumbv7_be-none-eabi -emit-llvm -o - -O3 |
FileCheck %s
+// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -emit-llvm -o - -O3
-std=c++11 | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LP64 %s
// CHECK-LP64: %union.Test1 = type { i32, [4 x i8] }
union Test1 {
@@ -84,3 +85,68 @@ int test_init() {
// CHECK: ret i32 0
return 0;
}
+
+extern "C" {
+int test_trunc_int() {
+ union {
+int i : 4; // truncated to 0b == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_int()
+// CHECK: ret i32 -1
+
+int test_trunc_three_bits() {
+ union {
+int i : 3; // truncated to 0b111 == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_three_bits()
+// CHECK: ret i32 -1
+
+int test_trunc_1() {
+ union {
+int i : 1; // truncated to 0b1 == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_1()
+// CHECK: ret i32 -1
+
+int test_trunc_zero() {
+ union {
+int i : 4; // truncated to 0b == 0
+ } const U = {80}; // 0b0101
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_zero()
+// CHECK: ret i32 0
+
+int test_constexpr() {
+ union {
+int i : 3; // truncated to 0b111 == -1
+ } const U = {1 + 2 + 4 + 8}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_constexpr()
+// CHECK: ret i32 -1
+
+int test_notrunc() {
+ union {
+int i : 12; // not truncated
+ } const U = {1 + 2 + 4 + 8}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_notrunc()
+// CHECK: ret i32 15
+
+long long test_trunc_long_long() {
+ union {
+long long i : 14; // truncated to 0b0001001101 ==
+ } const U = {0b010001001101};
+ return U.i;
+}
+// CHECK: define dso_local i64 @test_trunc_long_long()
+// CHECK: ret i64 3917
+}
___
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cfe-commits@lists.llvm.org
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[clang] 103bbdd - [ARM] Move Triple::getARMCPUForArch into ARMTargetParser
Author: Tomas Matheson
Date: 2022-11-09T11:52:35Z
New Revision: 103bbddde66f4157b52c2b6d7532c1dd0dfcaf94
URL:
https://github.com/llvm/llvm-project/commit/103bbddde66f4157b52c2b6d7532c1dd0dfcaf94
DIFF:
https://github.com/llvm/llvm-project/commit/103bbddde66f4157b52c2b6d7532c1dd0dfcaf94.diff
LOG: [ARM] Move Triple::getARMCPUForArch into ARMTargetParser
This is very backend specific so either belongs in Toolchains/ARM or in
ARMTargetParser. Since it is used in lldb, ARMTargetParser made more sense.
This is part of an effort to move information about ARM/AArch64 architecture
versions, extensions and CPUs into their respective TargetParsers.
Differential Revision: https://reviews.llvm.org/D137564
Added:
Modified:
clang/lib/Driver/ToolChains/Arch/ARM.cpp
lldb/source/Utility/ArchSpec.cpp
llvm/include/llvm/ADT/Triple.h
llvm/include/llvm/Support/ARMTargetParser.h
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Support/Triple.cpp
llvm/unittests/ADT/TripleTest.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index 67dec7cadada5..bbf466ba847de 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -938,7 +938,7 @@ StringRef arm::getARMCPUForMArch(StringRef Arch, const
llvm::Triple &Triple) {
// We need to return an empty string here on invalid MArch values as the
// various places that call this function can't cope with a null result.
- return Triple.getARMCPUForArch(MArch);
+ return llvm::ARM::getARMCPUForArch(Triple, MArch);
}
/// getARMTargetCPU - Get the (LLVM) name of the ARM cpu we are targeting.
@@ -971,7 +971,8 @@ llvm::ARM::ArchKind arm::getLLVMArchKindForARM(StringRef
CPU, StringRef Arch,
if (ArchKind == llvm::ARM::ArchKind::INVALID)
// In case of generic Arch, i.e. "arm",
// extract arch from default cpu of the Triple
- ArchKind = llvm::ARM::parseCPUArch(Triple.getARMCPUForArch(ARMArch));
+ ArchKind =
+ llvm::ARM::parseCPUArch(llvm::ARM::getARMCPUForArch(Triple,
ARMArch));
} else {
// FIXME: horrible hack to get around the fact that Cortex-A7 is only an
// armv7k triple if it's actually been specified via "-arch armv7k".
diff --git a/lldb/source/Utility/ArchSpec.cpp
b/lldb/source/Utility/ArchSpec.cpp
index 126bedc209232..e1d7ee3ee276d 100644
--- a/lldb/source/Utility/ArchSpec.cpp
+++ b/lldb/source/Utility/ArchSpec.cpp
@@ -16,6 +16,7 @@
#include "llvm/BinaryFormat/COFF.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/BinaryFormat/MachO.h"
+#include "llvm/Support/ARMTargetParser.h"
#include "llvm/Support/Compiler.h"
using namespace lldb;
@@ -638,7 +639,7 @@ std::string ArchSpec::GetClangTargetCPU() const {
}
if (GetTriple().isARM())
-cpu = GetTriple().getARMCPUForArch("").str();
+cpu = llvm::ARM::getARMCPUForArch(GetTriple(), "").str();
return cpu;
}
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index dc96398dba999..5aba2730c5a8b 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -1024,12 +1024,6 @@ class Triple {
/// architecture if no such variant can be found.
llvm::Triple getLittleEndianArchVariant() const;
- /// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
- ///
- /// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
- /// string then the triple's arch name is used.
- StringRef getARMCPUForArch(StringRef Arch = StringRef()) const;
-
/// Tests whether the target triple is little endian.
///
/// \returns true if the triple is little endian, false otherwise.
diff --git a/llvm/include/llvm/Support/ARMTargetParser.h
b/llvm/include/llvm/Support/ARMTargetParser.h
index 5fb4090395c07..32cc31db5936a 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.h
+++ b/llvm/include/llvm/Support/ARMTargetParser.h
@@ -296,6 +296,12 @@ unsigned parseArchVersion(StringRef Arch);
void fillValidCPUArchList(SmallVectorImpl &Values);
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
+/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
+///
+/// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
+/// string then the triple's arch name is used.
+StringRef getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch = {});
+
} // namespace ARM
} // namespace llvm
diff --git a/llvm/lib/Support/ARMTargetParser.cpp
b/llvm/lib/Support/ARMTargetParser.cpp
index a68244a5e38af..43cbb409b0f04 100644
--- a/llvm/lib/Support/ARMTargetParser.cpp
+++ b/llvm/lib/Support/ARMTargetParser.cpp
@@ -643,3 +643,72 @@ StringRef ARM::computeDefaultTargetABI(const Triple &TT,
StringRef CPU) {
return "aapcs";
}
}
+
+StringRef ARM::getARMC
[clang] a6aaa96 - [AArch64] Assembly support for FEAT_LRCPC3
Author: Tomas Matheson
Date: 2022-11-25T18:59:07Z
New Revision: a6aaa969f7caec58a994142f8d855861cf3a1463
URL:
https://github.com/llvm/llvm-project/commit/a6aaa969f7caec58a994142f8d855861cf3a1463
DIFF:
https://github.com/llvm/llvm-project/commit/a6aaa969f7caec58a994142f8d855861cf3a1463.diff
LOG: [AArch64] Assembly support for FEAT_LRCPC3
This patch implements assembly support for the 2022 A-Profile Architecture
extension FEAT_LRCPC3. FEAT_LRCPC3 is AArch64 only and introduces new
variants of load/store instructions with release consistency ordering.
Specs for individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/
This feature is optionally available from v8.2a and therefore not enabled by
default.
Contributors:
Lucas Prates
Sam Elliot
Son Tuan Vu
Tomas Matheson
Differential Revision: https://reviews.llvm.org/D138579
Added:
clang/test/Driver/aarch64-lrcpc3.c
llvm/test/MC/AArch64/armv8.9a-lrcpc3.s
llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
Modified:
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/MC/AArch64/arm64-memory.s
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/test/Driver/aarch64-lrcpc3.c
b/clang/test/Driver/aarch64-lrcpc3.c
new file mode 100644
index 0..27b522d74c5f8
--- /dev/null
+++ b/clang/test/Driver/aarch64-lrcpc3.c
@@ -0,0 +1,26 @@
+// Test that target feature FEAT_RCPC3 is implemented and available correctly
+
+// FEAT_RCPC3 is optional for v8.2a onwards, and can be enabled with +rcpc3
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a %s
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+rcpc3 %s
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+norcpc3 %s
2>&1 | FileCheck %s --check-prefix=DISABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a %s
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+rcpc3 %s
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+norcpc3 %s
2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// FEAT_RCPC3 is optional (off by default) for v8.8a/9.3a and older, and can
be enabled using +rcpc3
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.2-a %s
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.2-a+rcpc3 %s
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.2-a+norcpc3 %s
2>&1 | FileCheck %s --check-prefix=DISABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9-a %s
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9-a+rcpc3 %s
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9-a+norcpc3 %s
2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// FEAT_RCPC3 is invalid before v8
+// RUN: %clang -### -target arm-none-none-eabi -march=armv7-a+rcpc3 %s
2>&1 | FileCheck %s --check-prefix=INVALID
+
+// INVALID: error: unsupported argument 'armv7-a+rcpc3' to option '-march='
+// ENABLED: "-target-feature" "+rcpc3"
+// NOT_ENABLED-NOT: "-target-feature" "+rcpc3"
+// DISABLED: "-target-feature" "-rcpc3"
+
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def
b/llvm/include/llvm/Support/AArch64TargetParser.def
index f016c9147a7bb..6fd68872e96c1 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -152,6 +152,7 @@ AARCH64_ARCH_EXT_NAME("hbc", AArch64::AEK_HBC,
"+hbc",
AARCH64_ARCH_EXT_NAME("mops", AArch64::AEK_MOPS,"+mops",
"-mops")
AARCH64_ARCH_EXT_NAME("pmuv3",AArch64::AEK_PERFMON, "+perfmon",
"-perfmon")
AARCH64_ARCH_EXT_NAME("cssc", AArch64::AEK_CSSC,"+cssc",
"-cssc")
+AARCH64_ARCH_EXT_NAME("rcpc3",AArch64::AEK_RCPC3, "+rcpc3",
"-rcpc3")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h
b/llvm/include/llvm/Support/AArch64TargetParser.h
index 4d069a6b67831..3261e3f5b5eae 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -77,6 +77,7 @@ enum ArchEx
[clang] f57f086 - [AArch64TargetParser] getArchFeatures -> getArchFeature
Author: Tomas Matheson
Date: 2022-12-01T12:50:17Z
New Revision: f57f086714bc7a1399acf05d5ca1d665237cd725
URL:
https://github.com/llvm/llvm-project/commit/f57f086714bc7a1399acf05d5ca1d665237cd725
DIFF:
https://github.com/llvm/llvm-project/commit/f57f086714bc7a1399acf05d5ca1d665237cd725.diff
LOG: [AArch64TargetParser] getArchFeatures -> getArchFeature
Differential Revision: https://reviews.llvm.org/D138753
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index fb3d0b553542a..c36e942cf46ac 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -810,12 +810,9 @@ ParsedTargetAttr
AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
// Parse the architecture version, adding the required features to
// Ret.Features.
- std::vector FeatureStrs;
- if (ArchKind == llvm::AArch64::ArchKind::INVALID ||
- !llvm::AArch64::getArchFeatures(ArchKind, FeatureStrs))
+ if (ArchKind == llvm::AArch64::ArchKind::INVALID)
continue;
- for (auto R : FeatureStrs)
-Ret.Features.push_back(R.str());
+ Ret.Features.push_back(llvm::AArch64::getArchFeature(ArchKind).str());
// Add any extra features, after the +
SplitAndAddFeatures(Split.second, Ret.Features);
} else if (Feature.startswith("cpu=")) {
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 2a5c4718d084a..2a1269316bc75 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,8 +135,9 @@ static bool DecodeAArch64Mcpu(const Driver &D, StringRef
Mcpu, StringRef &CPU,
Features.push_back("+neon");
} else {
ArchKind = llvm::AArch64::parseCPUArch(CPU);
-if (!llvm::AArch64::getArchFeatures(ArchKind, Features))
+if (ArchKind == llvm::AArch64::ArchKind::INVALID)
return false;
+Features.push_back(llvm::AArch64::getArchFeature(ArchKind));
uint64_t Extension = llvm::AArch64::getDefaultExtensions(CPU, ArchKind);
if (!llvm::AArch64::getExtensionFeatures(Extension, Features))
@@ -160,9 +161,9 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, StringRef
March,
llvm::AArch64::ArchKind ArchKind = llvm::AArch64::parseArch(Split.first);
if (Split.first == "native")
ArchKind =
llvm::AArch64::getCPUArchKind(llvm::sys::getHostCPUName().str());
- if (ArchKind == llvm::AArch64::ArchKind::INVALID ||
- !llvm::AArch64::getArchFeatures(ArchKind, Features))
+ if (ArchKind == llvm::AArch64::ArchKind::INVALID)
return false;
+ Features.push_back(llvm::AArch64::getArchFeature(ArchKind));
// Enable SVE2 by default on Armv9-A.
// It can still be disabled if +nosve2 is present.
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h
b/llvm/include/llvm/Support/AArch64TargetParser.h
index ccee51f6bc1e8..5347c4e1f5e34 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -160,7 +160,7 @@ inline ArchKind &operator--(ArchKind &Kind) {
bool getExtensionFeatures(uint64_t Extensions,
std::vector &Features);
-bool getArchFeatures(ArchKind AK, std::vector &Features);
+StringRef getArchFeature(ArchKind AK);
StringRef getArchName(ArchKind AK);
StringRef getSubArch(ArchKind AK);
diff --git a/llvm/lib/Support/AArch64TargetParser.cpp
b/llvm/lib/Support/AArch64TargetParser.cpp
index e13b061eabb2d..aecb193e409a8 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -80,12 +80,8 @@ StringRef AArch64::resolveCPUAlias(StringRef CPU) {
.Default(CPU);
}
-bool AArch64::getArchFeatures(AArch64::ArchKind AK,
- std::vector &Features) {
- if (AK == ArchKind::INVALID)
-return false;
- Features.push_back(AArch64ARCHNames[static_cast(AK)].ArchFeature);
- return true;
+StringRef AArch64::getArchFeature(AArch64::ArchKind AK) {
+ return AArch64ARCHNames[static_cast(AK)].ArchFeature;
}
StringRef AArch64::getArchName(AArch64::ArchKind AK) {
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 8556bd7c6d875..53290c6e8c196 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6889,7 +6889,7 @@ bool AArch64AsmParser::parseDirectiveArch(SMLoc L) {
// Get the architecture and extension features.
std::v
[clang] 450de80 - [AArch64] Improve TargetParser API
Author: Tomas Matheson
Date: 2022-12-01T12:50:23Z
New Revision: 450de8008bb0ccb5dfc9dd69b6f5b434158772bd
URL:
https://github.com/llvm/llvm-project/commit/450de8008bb0ccb5dfc9dd69b6f5b434158772bd
DIFF:
https://github.com/llvm/llvm-project/commit/450de8008bb0ccb5dfc9dd69b6f5b434158772bd.diff
LOG: [AArch64] Improve TargetParser API
The TargetParser depends heavily on a collection of macros and enums to tie
together information about architectures, CPUs and extensions. Over time this
has led to some pretty awkward API choices. For example, recently a custom
operator-- has been added to the enum, which effectively turns iteration into
a graph traversal and makes the ordering of the macro calls in the header
significant. More generally there is a lot of string <-> enum conversion
going on. I think this shows the extent to which the current data structures
are constraining us, and the need for a rethink.
Key changes:
- Get rid of Arch enum, which is used to bind fields together. Instead of
passing around ArchKind, use the named ArchInfo objects directly or via
references.
- The list of all known ArchInfo becomes an array of pointers.
- ArchKind::operator-- is replaced with ArchInfo::implies(), which defines
which architectures are predecessors to each other. This allows features
from predecessor architectures to be added in a more intuitive way.
- Free functions of the form f(ArchKind) are converted to ArchInfo::f(). Some
functions become unnecessary and are deleted.
- Version number and profile are added to the ArchInfo. This makes comparison
of architectures easier and moves a couple of functions out of clang and
into AArch64TargetParser.
- clang::AArch64TargetInfo ArchInfo is initialised to Armv8a not INVALID.
- AArch64::ArchProfile which is distinct from ARM::ArchProfile
- Give things sensible names and add some comments.
Differential Revision: https://reviews.llvm.org/D138792
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/include/llvm/Support/VersionTuple.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c36e942cf46ac..edc4fdca26378 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -45,28 +45,6 @@ const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
#include "clang/Basic/BuiltinsAArch64.def"
};
-static StringRef getArchVersionString(llvm::AArch64::ArchKind Kind) {
- switch (Kind) {
- case llvm::AArch64::ArchKind::ARMV9A:
- case llvm::AArch64::ArchKind::ARMV9_1A:
- case llvm::AArch64::ArchKind::ARMV9_2A:
- case llvm::AArch64::ArchKind::ARMV9_3A:
- case llvm::AArch64::ArchKind::ARMV9_4A:
-return "9";
- default:
-return "8";
- }
-}
-
-StringRef AArch64TargetInfo::getArchProfile() const {
- switch (ArchKind) {
- case llvm::AArch64::ArchKind::ARMV8R:
-return "R";
- default:
-return "A";
- }
-}
-
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts)
: TargetInfo(Triple), ABI("aapcs") {
@@ -170,7 +148,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
return Name == "generic" ||
- llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID;
+ llvm::AArch64::parseCpu(Name).Arch != llvm::AArch64::INVALID;
}
bool AArch64TargetInfo::setCPU(const std::string &Name) {
@@ -298,8 +276,10 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
- Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind));
- Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + getArchProfile() + "'");
+ Builder.defineMacro("__ARM_ARCH",
+ std::to_string(ArchInfo->Version.getMajor()));
+ Builder.defineMacro("__ARM_ARCH_PROFILE",
+ std::string("'") + (char)ArchInfo->Profile + "'");
Builder.defineMacro("__ARM_64BIT_STATE", "1");
Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
@@ -464,52 +444,34 @@ void AArch64TargetInfo::getTargetDefines(const
LangOptions &Opts,
if (HasD128)
Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
- switch (ArchKind) {
- default:
-break;
- case llvm::AArch64::ArchKind::ARMV8_1A:
+ if (*ArchInfo == llvm::AArch64::ARMV8_1A)
getTargetDefinesARMV81A(Opts, Builder);
-
[clang] d1ef4b0 - Revert "[AArch64] Improve TargetParser API"
Author: Tomas Matheson
Date: 2022-12-01T13:06:54Z
New Revision: d1ef4b0a8da152fe4282f97c7c49f4930a3c66a2
URL:
https://github.com/llvm/llvm-project/commit/d1ef4b0a8da152fe4282f97c7c49f4930a3c66a2
DIFF:
https://github.com/llvm/llvm-project/commit/d1ef4b0a8da152fe4282f97c7c49f4930a3c66a2.diff
LOG: Revert "[AArch64] Improve TargetParser API"
Buildbots unhappy about constexpr function.
This reverts commit 450de8008bb0ccb5dfc9dd69b6f5b434158772bd.
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/include/llvm/Support/VersionTuple.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index edc4fdca26378..c36e942cf46ac 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -45,6 +45,28 @@ const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
#include "clang/Basic/BuiltinsAArch64.def"
};
+static StringRef getArchVersionString(llvm::AArch64::ArchKind Kind) {
+ switch (Kind) {
+ case llvm::AArch64::ArchKind::ARMV9A:
+ case llvm::AArch64::ArchKind::ARMV9_1A:
+ case llvm::AArch64::ArchKind::ARMV9_2A:
+ case llvm::AArch64::ArchKind::ARMV9_3A:
+ case llvm::AArch64::ArchKind::ARMV9_4A:
+return "9";
+ default:
+return "8";
+ }
+}
+
+StringRef AArch64TargetInfo::getArchProfile() const {
+ switch (ArchKind) {
+ case llvm::AArch64::ArchKind::ARMV8R:
+return "R";
+ default:
+return "A";
+ }
+}
+
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts)
: TargetInfo(Triple), ABI("aapcs") {
@@ -148,7 +170,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
return Name == "generic" ||
- llvm::AArch64::parseCpu(Name).Arch != llvm::AArch64::INVALID;
+ llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID;
}
bool AArch64TargetInfo::setCPU(const std::string &Name) {
@@ -276,10 +298,8 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
- Builder.defineMacro("__ARM_ARCH",
- std::to_string(ArchInfo->Version.getMajor()));
- Builder.defineMacro("__ARM_ARCH_PROFILE",
- std::string("'") + (char)ArchInfo->Profile + "'");
+ Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind));
+ Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + getArchProfile() + "'");
Builder.defineMacro("__ARM_64BIT_STATE", "1");
Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
@@ -444,34 +464,52 @@ void AArch64TargetInfo::getTargetDefines(const
LangOptions &Opts,
if (HasD128)
Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
- if (*ArchInfo == llvm::AArch64::ARMV8_1A)
+ switch (ArchKind) {
+ default:
+break;
+ case llvm::AArch64::ArchKind::ARMV8_1A:
getTargetDefinesARMV81A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_2A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_2A:
getTargetDefinesARMV82A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_3A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_3A:
getTargetDefinesARMV83A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_4A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_4A:
getTargetDefinesARMV84A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_5A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_5A:
getTargetDefinesARMV85A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_6A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_6A:
getTargetDefinesARMV86A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_7A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_7A:
getTargetDefinesARMV87A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_8A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_8A:
getTargetDefinesARMV88A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_9A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_9A:
getTargetDefinesARMV89A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV9A)
+break;
+ case llvm::AArch64::ArchKind::ARMV9A:
getTargetDefinesARMV9A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV9_1A)
+break;
+ case llvm::AArch64::ArchKind::ARMV9_1A:
getTargetDefinesARMV91A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV9_2A)
+break;
[clang] e83f150 - [AArch64] Improve TargetParser API
Author: Tomas Matheson
Date: 2022-12-01T15:30:07Z
New Revision: e83f1502f1be7a2a3b9a33f5a73867767e78ba6b
URL:
https://github.com/llvm/llvm-project/commit/e83f1502f1be7a2a3b9a33f5a73867767e78ba6b
DIFF:
https://github.com/llvm/llvm-project/commit/e83f1502f1be7a2a3b9a33f5a73867767e78ba6b.diff
LOG: [AArch64] Improve TargetParser API
Re-land with constexpr StringRef::substr():
The TargetParser depends heavily on a collection of macros and enums to tie
together information about architectures, CPUs and extensions. Over time this
has led to some pretty awkward API choices. For example, recently a custom
operator-- has been added to the enum, which effectively turns iteration into
a graph traversal and makes the ordering of the macro calls in the header
significant. More generally there is a lot of string <-> enum conversion
going on. I think this shows the extent to which the current data structures
are constraining us, and the need for a rethink.
Key changes:
- Get rid of Arch enum, which is used to bind fields together. Instead of
passing around ArchKind, use the named ArchInfo objects directly or via
references.
- The list of all known ArchInfo becomes an array of pointers.
- ArchKind::operator-- is replaced with ArchInfo::implies(), which defines
which architectures are predecessors to each other. This allows features
from predecessor architectures to be added in a more intuitive way.
- Free functions of the form f(ArchKind) are converted to ArchInfo::f(). Some
functions become unnecessary and are deleted.
- Version number and profile are added to the ArchInfo. This makes comparison
of architectures easier and moves a couple of functions out of clang and
into AArch64TargetParser.
- clang::AArch64TargetInfo ArchInfo is initialised to Armv8a not INVALID.
- AArch64::ArchProfile which is distinct from ARM::ArchProfile
- Give things sensible names and add some comments.
Differential Revision: https://reviews.llvm.org/D138792
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
llvm/include/llvm/ADT/StringRef.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/include/llvm/Support/VersionTuple.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c36e942cf46ac..edc4fdca26378 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -45,28 +45,6 @@ const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
#include "clang/Basic/BuiltinsAArch64.def"
};
-static StringRef getArchVersionString(llvm::AArch64::ArchKind Kind) {
- switch (Kind) {
- case llvm::AArch64::ArchKind::ARMV9A:
- case llvm::AArch64::ArchKind::ARMV9_1A:
- case llvm::AArch64::ArchKind::ARMV9_2A:
- case llvm::AArch64::ArchKind::ARMV9_3A:
- case llvm::AArch64::ArchKind::ARMV9_4A:
-return "9";
- default:
-return "8";
- }
-}
-
-StringRef AArch64TargetInfo::getArchProfile() const {
- switch (ArchKind) {
- case llvm::AArch64::ArchKind::ARMV8R:
-return "R";
- default:
-return "A";
- }
-}
-
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts)
: TargetInfo(Triple), ABI("aapcs") {
@@ -170,7 +148,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
return Name == "generic" ||
- llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID;
+ llvm::AArch64::parseCpu(Name).Arch != llvm::AArch64::INVALID;
}
bool AArch64TargetInfo::setCPU(const std::string &Name) {
@@ -298,8 +276,10 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
- Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind));
- Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + getArchProfile() + "'");
+ Builder.defineMacro("__ARM_ARCH",
+ std::to_string(ArchInfo->Version.getMajor()));
+ Builder.defineMacro("__ARM_ARCH_PROFILE",
+ std::string("'") + (char)ArchInfo->Profile + "'");
Builder.defineMacro("__ARM_64BIT_STATE", "1");
Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
@@ -464,52 +444,34 @@ void AArch64TargetInfo::getTargetDefines(const
LangOptions &Opts,
if (HasD128)
Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
- switch (ArchKind) {
- default:
-break;
- case llvm::AArch64::ArchKind::ARMV8_1A:
+ if (*Ar
[clang] 541a137 - Revert "[AArch64] Improve TargetParser API"
Author: Tomas Matheson
Date: 2022-12-05T11:09:03Z
New Revision: 541a1371c05d77bb70a6173127d6544b9571dbab
URL:
https://github.com/llvm/llvm-project/commit/541a1371c05d77bb70a6173127d6544b9571dbab
DIFF:
https://github.com/llvm/llvm-project/commit/541a1371c05d77bb70a6173127d6544b9571dbab.diff
LOG: Revert "[AArch64] Improve TargetParser API"
This reverts commit e83f1502f1be7a2a3b9a33f5a73867767e78ba6b.
Did not build with C++20 and caused problems with dynamic libs.
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
llvm/include/llvm/ADT/StringRef.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/include/llvm/Support/VersionTuple.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 476bfcf9c41f6..c5fce62bc501f 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -45,6 +45,28 @@ const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
#include "clang/Basic/BuiltinsAArch64.def"
};
+static StringRef getArchVersionString(llvm::AArch64::ArchKind Kind) {
+ switch (Kind) {
+ case llvm::AArch64::ArchKind::ARMV9A:
+ case llvm::AArch64::ArchKind::ARMV9_1A:
+ case llvm::AArch64::ArchKind::ARMV9_2A:
+ case llvm::AArch64::ArchKind::ARMV9_3A:
+ case llvm::AArch64::ArchKind::ARMV9_4A:
+return "9";
+ default:
+return "8";
+ }
+}
+
+StringRef AArch64TargetInfo::getArchProfile() const {
+ switch (ArchKind) {
+ case llvm::AArch64::ArchKind::ARMV8R:
+return "R";
+ default:
+return "A";
+ }
+}
+
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts)
: TargetInfo(Triple), ABI("aapcs") {
@@ -148,7 +170,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
return Name == "generic" ||
- llvm::AArch64::parseCpu(Name).Arch != llvm::AArch64::INVALID;
+ llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID;
}
bool AArch64TargetInfo::setCPU(const std::string &Name) {
@@ -276,10 +298,8 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
- Builder.defineMacro("__ARM_ARCH",
- std::to_string(ArchInfo->Version.getMajor()));
- Builder.defineMacro("__ARM_ARCH_PROFILE",
- std::string("'") + (char)ArchInfo->Profile + "'");
+ Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind));
+ Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + getArchProfile() + "'");
Builder.defineMacro("__ARM_64BIT_STATE", "1");
Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
@@ -444,34 +464,52 @@ void AArch64TargetInfo::getTargetDefines(const
LangOptions &Opts,
if (HasD128)
Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
- if (*ArchInfo == llvm::AArch64::ARMV8_1A)
+ switch (ArchKind) {
+ default:
+break;
+ case llvm::AArch64::ArchKind::ARMV8_1A:
getTargetDefinesARMV81A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_2A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_2A:
getTargetDefinesARMV82A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_3A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_3A:
getTargetDefinesARMV83A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_4A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_4A:
getTargetDefinesARMV84A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_5A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_5A:
getTargetDefinesARMV85A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_6A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_6A:
getTargetDefinesARMV86A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_7A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_7A:
getTargetDefinesARMV87A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_8A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_8A:
getTargetDefinesARMV88A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV8_9A)
+break;
+ case llvm::AArch64::ArchKind::ARMV8_9A:
getTargetDefinesARMV89A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV9A)
+break;
+ case llvm::AArch64::ArchKind::ARMV9A:
getTargetDefinesARMV9A(Opts, Builder);
- if (*ArchInfo == llvm::AArch64::ARMV9_1A)
+break;
+ case llvm::AArch64::ArchKind::ARMV9_1A:
getTargetDefinesARMV91A(Opts, Builder);
[clang] d022f32 - Revert "[ARM] __ARM_ARCH macro definition fix (#81493)"
Author: Tomas Matheson
Date: 2024-02-19T12:19:16Z
New Revision: d022f32c73c57b59a9121eba909f5034e89c628e
URL:
https://github.com/llvm/llvm-project/commit/d022f32c73c57b59a9121eba909f5034e89c628e
DIFF:
https://github.com/llvm/llvm-project/commit/d022f32c73c57b59a9121eba909f5034e89c628e.diff
LOG: Revert "[ARM] __ARM_ARCH macro definition fix (#81493)"
This reverts commit 89c1bf1230e011f2f0e43554c278205fa1819de5.
This has been unimplemenented for a while, and GCC does not implement
it, therefore we need to consider whether we should just deprecate it
in the ACLE instead.
Added:
Modified:
clang/docs/ReleaseNotes.rst
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/Basic/Targets/ARM.h
clang/test/Preprocessor/arm-target-features.c
llvm/include/llvm/TargetParser/ARMTargetParser.h
llvm/lib/TargetParser/ARMTargetParser.cpp
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 45ace4191592d3..649ad655905af2 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -292,8 +292,6 @@ X86 Support
Arm and AArch64 Support
^^^
-- Fixed the incorrect definition of the __ARM_ARCH macro for architectures
greater than or equal to v8.1.
-
Android Support
^^^
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index dd0218e6ebed81..68032961451d90 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -367,20 +367,8 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
-
- // __ARM_ARCH is defined as an integer value indicating the current ARM ISA.
- // For ISAs up to and including v8, __ARM_ARCH is equal to the major version
- // number. For ISAs from v8.1 onwards, __ARM_ARCH is scaled up to include the
- // minor version number, e.g. for ARM architecture ARMvX.Y:
- // __ARM_ARCH = X * 100 + Y.
- if (ArchInfo->Version.getMajor() == 8 && ArchInfo->Version.getMinor() == 0)
-Builder.defineMacro("__ARM_ARCH",
-std::to_string(ArchInfo->Version.getMajor()));
- else
-Builder.defineMacro("__ARM_ARCH",
-std::to_string(ArchInfo->Version.getMajor() * 100 +
- ArchInfo->Version.getMinor().value()));
-
+ Builder.defineMacro("__ARM_ARCH",
+ std::to_string(ArchInfo->Version.getMajor()));
Builder.defineMacro("__ARM_ARCH_PROFILE",
std::string("'") + (char)ArchInfo->Profile + "'");
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index cd7fb95259d9db..55b71557452fa0 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -130,7 +130,6 @@ void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) {
SubArch = llvm::ARM::getSubArch(ArchKind);
ArchProfile = llvm::ARM::parseArchProfile(SubArch);
ArchVersion = llvm::ARM::parseArchVersion(SubArch);
- ArchMinorVersion = llvm::ARM::parseArchMinorVersion(SubArch);
// cache CPU related strings
CPUAttr = getCPUAttr();
@@ -737,16 +736,9 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (!CPUAttr.empty())
Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
- // __ARM_ARCH is defined as an integer value indicating the current ARM ISA.
- // For ISAs up to and including v8, __ARM_ARCH is equal to the major version
- // number. For ISAs from v8.1 onwards, __ARM_ARCH is scaled up to include the
- // minor version number, e.g. for ARM architecture ARMvX.Y:
- // __ARM_ARCH = X * 100 + Y.
- if (ArchVersion >= 9 || ArchMinorVersion != 0)
-Builder.defineMacro("__ARM_ARCH",
-Twine(ArchVersion * 100 + ArchMinorVersion));
- else
-Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
+ // ACLE 6.4.1 ARM/Thumb instruction set architecture
+ // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
+ Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
if (ArchVersion >= 8) {
// ACLE 6.5.7 Crypto Extension
diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h
index df06e4d120637a..71322a094f5edb 100644
--- a/clang/lib/Basic/Targets/ARM.h
+++ b/clang/lib/Basic/Targets/ARM.h
@@ -60,7 +60,6 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public
TargetInfo {
llvm::ARM::ArchKind ArchKind = llvm::ARM::ArchKind::ARMV4T;
llvm::ARM::ProfileKind ArchProfile;
unsigned ArchVersion;
- unsigned ArchMinorVersion;
LLVM_PREFERRED_TYPE(FPUMode)
unsigned FPU : 5;
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-
[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/96628 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] Bring initFeatureMap back to AArch64TargetInfo. (PR #96832)
tmatheson-arm wrote: Thank you for the example, I understand what is happening how. - Before #94279, we used to add CPU features in `AArch64::initFeatureMap`. - In #94279, we decided that actually you should do that in the Driver, which should put all `-target-features` it wants on the -cc1 command line. The Driver is responsible for expanding the CPU (and architecture) feature dependencies and their interaction with any modifiers on the command line. - This means that when `initFeatureMap` runs in `clang`, `FeaturesAsWritten` is populated with the CPU features and is used to initialise the `FeatureMap`. - In contrast, you are not using the `Driver`, and do not populate `FeaturesAsWritten` with the CPU features. - Instead, you expect `initFeatureMap` to add CPU features. This is not unreasonable, given that the CPU is passed the function and several other backends add CPU features at this stage. [This bit of code](https://github.com/llvm/llvm-project/pull/94279/files#diff-2ccae12096c75c4b8422ea0d2fdf6b195896d2554d62cce604e8fcb56a78ef62L1057-L1067) used to crudely add the CPU features to the end of the feature list. However there are some problems with that approach, which we attempted to rectify in #94279: - CPU features that were explicitly disabled on the command line could actually end up enabled in the backend - The architecture features (i.e. implied by `-march`) were not treated the same way as the CPU features (`-mcpu`) For example, if you wrote: `clang -mcpu=cortex-a75+norcpc -###`, you would see all the Cortex-A75 features expanded on the `-cc1` command line, but with RCPC disabled: `-target-feature -rcpc`. But in this case, `AArch64::initFeatureMap` would have re-added `+rcpc`, overriding the command line. (This is technically not the case after [this line](https://github.com/llvm/llvm-project/pull/94279/files#diff-2ccae12096c75c4b8422ea0d2fdf6b195896d2554d62cce604e8fcb56a78ef62L1092) was added, but the general point is that `initFeatureMap` broke feature dependency resolution in ways that are difficult to reason about). There doesn't seem to be a way to specify an architecture in `TargetOptions`, which looks odd to me. That means there is no way to select e.g. `armv9.4-a` in your example, except by manually adding the features in `TargetOptions::Features` or `TargetOptions::FeaturesAsWritten`. So the way that we set up the AArch64 backend in #94279 is to require you to calculate your feature set up front, which are then trivially passed through by the default `TargetInfo::initFeatureMap`. I'm not sure there is a clear answer on this one. I can't see a way to easily let `AArch64:: initFeatureMap` add CPU features again without breaking the dependency resolution. I am open to suggestions though. If you wanted to go the route of building the feature list before calling `initFeatureMap`, the functions `tools::getTargetFeatures` and `aarch64::getAArch64TargetFeatures` can do that for you. Currently they require a `const Driver &D`, but fundamentally I think they just need a `DiagnosticsEngine&` so that could be changed. I'm open to other suggestions too. https://github.com/llvm/llvm-project/pull/96832 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)
@@ -445,4 +445,21 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (Args.getLastArg(options::OPT_mno_bti_at_return_twice))
Features.push_back("+no-bti-at-return-twice");
+
+ // Parse AArch64 CPU Features
+ const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
tmatheson-arm wrote:
Feels like this should be done in
`getAArch64ArchFeaturesFromMcpu`/`DecodeAArch64Mcpu`
https://github.com/llvm/llvm-project/pull/97749
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[clang] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)
@@ -445,4 +445,21 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (Args.getLastArg(options::OPT_mno_bti_at_return_twice))
Features.push_back("+no-bti-at-return-twice");
+
+ // Parse AArch64 CPU Features
+ const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
+ StringRef CPUName;
+
+ if (CPUArg) {
+CPUName = CPUArg->getValue();
+if (CPUName == "native") {
+ llvm::StringMap HostFeatures;
+ if (llvm::sys::getHostCPUFeatures(HostFeatures)) {
+for (auto &F : HostFeatures) {
+ Features.push_back(
+Args.MakeArgString((F.second ? "+" : "-") + F.first()));
+}
tmatheson-arm wrote:
```suggestion
for (auto &[Name, Enabled] : HostFeatures) {
Features.push_back(
Args.MakeArgString((Enabled ? "+" : "-") + Name));
}
```
https://github.com/llvm/llvm-project/pull/97749
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[clang] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97749 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/97824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
@@ -15,22 +15,23 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/Host.h"
+#include
+
using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- StringMap features;
-
- if (!sys::getHostCPUFeatures(features))
+ if (std::optional> features =
+ sys::getHostCPUFeatures(features)) {
+if ((*features)["sse"])
tmatheson-arm wrote:
Maybe
```suggestion
if (features->lookup("sse"))
```
which does the same, but doesn't insert the default entry into the map.
https://github.com/llvm/llvm-project/pull/97824
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[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
@@ -22,13 +22,13 @@ using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- if (std::optional> features =
+ if (const std::optional> features =
sys::getHostCPUFeatures(features)) {
-if ((*features)["sse"])
+if (features->contains("sse"))
tmatheson-arm wrote:
`contains` will only check if the key exists in the map, but you want to
actually get the `bool` if it exists and default to `false` if it doesn't. I
think `lookup` fits better.
https://github.com/llvm/llvm-project/pull/97824
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[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PAC][ELF][AArch64] Encode signed GOT flag in PAuth core info (PR #96159)
https://github.com/tmatheson-arm approved this pull request. LGTM, just based on what I can see from implementation of the existing bits in the version field. https://github.com/llvm/llvm-project/pull/96159 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)
tmatheson-arm wrote: > Mind sticking it in a gist at least so folks can use it for downstream > subtargets? [Here you go](https://gist.github.com/tmatheson-arm/333dd14cc1c95ab4ac563ed615add95d) https://github.com/llvm/llvm-project/pull/97829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/97829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)
@@ -0,0 +1,24 @@ +// REQUIRES: aarch64-registered-target tmatheson-arm wrote: I've kept them as-is so that they still correspond to the [generating script](https://gist.github.com/tmatheson-arm/333dd14cc1c95ab4ac563ed615add95d). https://github.com/llvm/llvm-project/pull/97829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -261,9 +261,9 @@ __attribute__((target_version("jscvt"))) int
default_def_with_version_decls(void
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+lse,-v9.5a" }
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+neon,+rdm,-v9.5a" }
// CHECK: attributes #[[ATTR5:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8"
"target-features"="+dotprod,+fp-armv8,+neon,-v9.5a" }
-// CHECK: attributes #[[ATTR6:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+jsconv,+neon,-v9.5a" }
-// CHECK: attributes #[[ATTR7:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-features"="-v9.5a" }
-// CHECK: attributes #[[ATTR8:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-features"="+lse,-v9.5a" }
+// CHECK: attributes #[[ATTR6:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-features"="-v9.5a" }
+// CHECK: attributes #[[ATTR7:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-features"="+lse,-v9.5a" }
+// CHECK: attributes #[[ATTR8:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+jsconv,+neon,-v9.5a" }
tmatheson-arm wrote:
These attributes are not actually matched against anything, is there any point
testing them?
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
https://github.com/tmatheson-arm commented: It's really hard to tell what is changing here because the existing tests are so non-specific. https://github.com/llvm/llvm-project/pull/97761 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -4210,9 +4192,7 @@ void CodeGenModule::emitMultiVersionFunctions() {
return cast(Func);
};
-bool HasDefaultDecl = !FD->isTargetVersionMultiVersion();
-bool ShouldEmitResolver =
-!getContext().getTargetInfo().getTriple().isAArch64();
+bool ShouldEmitResolver = !getTarget().getTriple().isAArch64();
tmatheson-arm wrote:
```suggestion
// For AArch64, a resolver is only emitted if a function marked
target(default))
// is present and defined in this TU. For other architectures it is always
emitted.
bool ShouldEmitResolver = !getTarget().getTriple().isAArch64();
```
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97761 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -59,15 +59,22 @@ int bar() {
return m.goo(1) + foo(1) + foo();
}
+// Example to demonstrate that at the point of use we haven't yet seen the
default.
+// At that point a declaration for the unmangled symbol is emitted, which is
later
+// replaced by the ifunc symbol (once we have seen the default definition).
+__attribute__((target_version("aes"))) void fmv(void) {}
+void caller(void) { fmv(); }
+__attribute__((target_version("default"))) void fmv(void) {}
tmatheson-arm wrote:
How does it demonstrate this? The unmangled symbol doesn't appear in the
output, as far as I can see.
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -4224,10 +4204,8 @@ void CodeGenModule::emitMultiVersionFunctions() {
llvm::Function *Func = createFunction(CurFD);
Options.emplace_back(Func, TA->getArchitecture(), Feats);
} else if (const auto *TVA = CurFD->getAttr()) {
-bool HasDefaultDef = TVA->isDefaultVersion() &&
- CurFD->doesThisDeclarationHaveABody();
-HasDefaultDecl |= TVA->isDefaultVersion();
-ShouldEmitResolver |= (CurFD->isUsed() || HasDefaultDef);
+ShouldEmitResolver |= (TVA->isDefaultVersion() &&
+ CurFD->doesThisDeclarationHaveABody());
tmatheson-arm wrote:
```suggestion
if (TVA->isDefaultVersion() &&
CurFD->doesThisDeclarationHaveABody())
ShouldEmitResolver = true;
```
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -59,15 +59,22 @@ int bar() {
return m.goo(1) + foo(1) + foo();
}
+// Example to demonstrate that at the point of use we haven't yet seen the
default.
+// At that point a declaration for the unmangled symbol is emitted, which is
later
+// replaced by the ifunc symbol (once we have seen the default definition).
+__attribute__((target_version("aes"))) void fmv(void) {}
+void caller(void) { fmv(); }
+__attribute__((target_version("default"))) void fmv(void) {}
tmatheson-arm wrote:
I think we want to test the observable behaviour, not whatever is happening
internally. The test doesn't actually check the internals anyway, besides that
it doesn't crash. i.e. I would expect the comment to be something like:
> Test that an ifunc is generated and used when `default` is defined after the
> first use of the function
If we want to check the other case you mentioned, and
`update_cc_test_checks.py` can't generate a test for it automatically, it
should still be tested but it will have to be manually written.
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -11,7 +11,7 @@ int __attribute__((target_version("fp+aes"))) fmv(void) {
return 6; }
int __attribute__((target_version("crc+ls64_v"))) fmv(void) { return 7; }
int __attribute__((target_version("bti"))) fmv(void) { return 8; }
int __attribute__((target_version("sme2"))) fmv(void) { return 9; }
-int __attribute__((target_version("default"))) fmv(void);
+int __attribute__((target_version("default"))) fmv(void) { return 0; }
tmatheson-arm wrote:
I think `fmv_one` and `fmv_too` should be defined too, to keep the original
behaviour of this test unchanged, and then add a new, separate test for
checking the various behaviours of `default`
https://github.com/llvm/llvm-project/pull/97761
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[clang] [llvm] [AArch64] Attempt to further split the arch default and implied exts. (PR #106304)
tmatheson-arm wrote: Are you planning to follow through with this? https://github.com/llvm/llvm-project/pull/106304 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm created https://github.com/llvm/llvm-project/pull/104435 This adds a check that all ExtensionWithMArch which are marked as implied features for an architecture are also present in the list of default features. It doesn't make sense to have something mandatory but not on by default. There were a number of existing cases that violated this rule, and some changes to which features are mandatory (indicated by the Implies field): > FEAT_SPECRES is mandatory from Armv8.5. FeaturePredRes is added to the HasV8_5aOps.DefaultExts. > FEAT_DIT is mandatory from Armv8.4. FeatureDIT is added to the HasV8_4aOps.DefaultExts. FEAT_SSBS is not mandatory for any architecture. https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see that in the Arm ARM. FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts. Cortex-A710 does not appear to have SSBS https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en Removed from the Cortex-A710 and Oryon print-supported-extensions tests. https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/ Added to Apple A15/A16/A17 and (presumably?) M4 processor features. > FEAT_BTI is mandatory from Armv8.5. FeatureBranchTargetId is added to the DefaultExts > FEAT_FlagM is mandatory from Armv8.4. FeatureFlagM is added to the DefaultExts > In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is > implemented. FeatureDotProd is added to the HasV8_4aOps.DefaultExts. FIXME what about nofp here? > FEAT_SB is mandatory from Armv8.5. FeatureSB is added to HasV8_5aOps.DefaultExts. Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`. > FEAT_WFxT is mandatory from Armv8.7. FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts. > FEAT_CCIDX is OPTIONAL from Armv8.2. Removed from Implies and added to HasV8_3aOps.DefaultExts and HasV8_0rOps.DefaultExts. For v8-R, FEAT_CCIDX is not mandatory, removed. - Not implemented by cortex-r82, removed: https://developer.arm.com/documentation/102670/0300/?lang=en - Ditto cortex-r82ae >From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Thu, 15 Aug 2024 13:41:31 +0100 Subject: [PATCH] [AArch64] Add a check for invalid default features This adds a check that all ExtensionWithMArch which are marked as implied features for an architecture are also present in the list of default features. It doesn't make sense to have something mandatory but not on by default. There were a number of existing cases that violated this rule, and some changes to which features are mandatory (indicated by the Implies field): > FEAT_SPECRES is mandatory from Armv8.5. FeaturePredRes is added to the HasV8_5aOps.DefaultExts. > FEAT_DIT is mandatory from Armv8.4. FeatureDIT is added to the HasV8_4aOps.DefaultExts. FEAT_SSBS is not mandatory for any architecture. https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see that in the Arm ARM. FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts. Cortex-A710 does not appear to have SSBS https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en Removed from the Cortex-A710 and Oryon print-supported-extensions tests. https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/ Added to Apple A15/A16/A17 and (presumably?) M4 processor features. > FEAT_BTI is mandatory from Armv8.5. FeatureBranchTargetId is added to the DefaultExts > FEAT_FlagM is mandatory from Armv8.4. FeatureFlagM is added to the DefaultExts > In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is > implemented. FeatureDotProd is added to the HasV8_4aOps.DefaultExts. FIXME what about nofp here? > FEAT_SB is mandatory from Armv8.5. FeatureSB is added to HasV8_5aOps.DefaultExts. Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`. > FEAT_WFxT is mandatory from Armv8.7. FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts. > FEAT_CCIDX is OPTIONAL from Armv8.2. Removed from Implies and added to HasV8_3aOps.DefaultExts and HasV8_0rOps.DefaultExts. For v8-R, FEAT_CCIDX is not mandatory, removed. - Not implemented by cortex-r82, removed: https://developer.arm.com/documentation/102670/0300/?lang=en - Ditto cortex-r82ae --- clang/test/CodeGen/aarch64-targetattr.c | 12 +++ clang/test/Driver/arm-sb.c| 2 +- .../aarch64-cortex-a710.c | 1 - .../aarch64-cortex-r82.c | 1 - .../aarch64-cortex-r82ae.c| 1 - .../aarch64-oryon-1.c | 1 - .../Preprocessor/aarch64-target-features.c| 4 +-- llvm/lib/Target/AArch64/AArch64Features.td| 16 +- llvm/lib/Target/AArch64/AArch64Processors.td | 11 --- llv
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104435 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
tmatheson-arm wrote: > > Cortex-A710 does not appear to have SSBS > I believe this says it should be present: You're right, I'll fix that. I will also actually remove FeatureCCIDX from the 8.3 mandatory features. https://github.com/llvm/llvm-project/pull/104435 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 1/9] [AArch64] Add a check for invalid default features
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field):
> FEAT_SPECRES is mandatory from Armv8.5.
FeaturePredRes is added to the HasV8_5aOps.DefaultExts.
> FEAT_DIT is mandatory from Armv8.4.
FeatureDIT is added to the HasV8_4aOps.DefaultExts.
FEAT_SSBS is not mandatory for any architecture.
https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see
that in the Arm ARM.
FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts.
Cortex-A710 does not appear to have SSBS
https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en
Removed from the Cortex-A710 and Oryon print-supported-extensions tests.
https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/
Added to Apple A15/A16/A17 and (presumably?) M4 processor features.
> FEAT_BTI is mandatory from Armv8.5.
FeatureBranchTargetId is added to the DefaultExts
> FEAT_FlagM is mandatory from Armv8.4.
FeatureFlagM is added to the DefaultExts
> In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is
> implemented.
FeatureDotProd is added to the HasV8_4aOps.DefaultExts.
FIXME what about nofp here?
> FEAT_SB is mandatory from Armv8.5.
FeatureSB is added to HasV8_5aOps.DefaultExts.
Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`.
> FEAT_WFxT is mandatory from Armv8.7.
FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts.
> FEAT_CCIDX is OPTIONAL from Armv8.2.
Removed from Implies and added to HasV8_3aOps.DefaultExts and
HasV8_0rOps.DefaultExts.
For v8-R, FEAT_CCIDX is not mandatory, removed.
- Not implemented by cortex-r82, removed:
https://developer.arm.com/documentation/102670/0300/?lang=en
- Ditto cortex-r82ae
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-cortex-a710.c | 1 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
.../aarch64-oryon-1.c | 1 -
.../Preprocessor/aarch64-target-features.c| 4 +--
llvm/lib/Target/AArch64/AArch64Features.td| 16 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 11 ---
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../TargetParser/TargetParserTest.cpp | 21 ++--
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +--
14 files changed, 67 insertions(+), 41 deletions(-)
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/10] [AArch64] Add a check for invalid default features
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field):
> FEAT_SPECRES is mandatory from Armv8.5.
FeaturePredRes is added to the HasV8_5aOps.DefaultExts.
> FEAT_DIT is mandatory from Armv8.4.
FeatureDIT is added to the HasV8_4aOps.DefaultExts.
FEAT_SSBS is not mandatory for any architecture.
https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see
that in the Arm ARM.
FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts.
Cortex-A710 does not appear to have SSBS
https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en
Removed from the Cortex-A710 and Oryon print-supported-extensions tests.
https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/
Added to Apple A15/A16/A17 and (presumably?) M4 processor features.
> FEAT_BTI is mandatory from Armv8.5.
FeatureBranchTargetId is added to the DefaultExts
> FEAT_FlagM is mandatory from Armv8.4.
FeatureFlagM is added to the DefaultExts
> In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is
> implemented.
FeatureDotProd is added to the HasV8_4aOps.DefaultExts.
FIXME what about nofp here?
> FEAT_SB is mandatory from Armv8.5.
FeatureSB is added to HasV8_5aOps.DefaultExts.
Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`.
> FEAT_WFxT is mandatory from Armv8.7.
FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts.
> FEAT_CCIDX is OPTIONAL from Armv8.2.
Removed from Implies and added to HasV8_3aOps.DefaultExts and
HasV8_0rOps.DefaultExts.
For v8-R, FEAT_CCIDX is not mandatory, removed.
- Not implemented by cortex-r82, removed:
https://developer.arm.com/documentation/102670/0300/?lang=en
- Ditto cortex-r82ae
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-cortex-a710.c | 1 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
.../aarch64-oryon-1.c | 1 -
.../Preprocessor/aarch64-target-features.c| 4 +--
llvm/lib/Target/AArch64/AArch64Features.td| 16 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 11 ---
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../TargetParser/TargetParserTest.cpp | 21 ++--
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +--
14 files changed, 67 insertions(+), 41 deletions(-)
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-siz
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104435 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104435 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104435 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/11] [AArch64] Add a check for invalid default features
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field):
> FEAT_SPECRES is mandatory from Armv8.5.
FeaturePredRes is added to the HasV8_5aOps.DefaultExts.
> FEAT_DIT is mandatory from Armv8.4.
FeatureDIT is added to the HasV8_4aOps.DefaultExts.
FEAT_SSBS is not mandatory for any architecture.
https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see
that in the Arm ARM.
FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts.
Cortex-A710 does not appear to have SSBS
https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en
Removed from the Cortex-A710 and Oryon print-supported-extensions tests.
https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/
Added to Apple A15/A16/A17 and (presumably?) M4 processor features.
> FEAT_BTI is mandatory from Armv8.5.
FeatureBranchTargetId is added to the DefaultExts
> FEAT_FlagM is mandatory from Armv8.4.
FeatureFlagM is added to the DefaultExts
> In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is
> implemented.
FeatureDotProd is added to the HasV8_4aOps.DefaultExts.
FIXME what about nofp here?
> FEAT_SB is mandatory from Armv8.5.
FeatureSB is added to HasV8_5aOps.DefaultExts.
Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`.
> FEAT_WFxT is mandatory from Armv8.7.
FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts.
> FEAT_CCIDX is OPTIONAL from Armv8.2.
Removed from Implies and added to HasV8_3aOps.DefaultExts and
HasV8_0rOps.DefaultExts.
For v8-R, FEAT_CCIDX is not mandatory, removed.
- Not implemented by cortex-r82, removed:
https://developer.arm.com/documentation/102670/0300/?lang=en
- Ditto cortex-r82ae
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-cortex-a710.c | 1 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
.../aarch64-oryon-1.c | 1 -
.../Preprocessor/aarch64-target-features.c| 4 +--
llvm/lib/Target/AArch64/AArch64Features.td| 16 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 11 ---
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../TargetParser/TargetParserTest.cpp | 21 ++--
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +--
14 files changed, 67 insertions(+), 41 deletions(-)
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-siz
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
tmatheson-arm wrote: Fixed SSBS and CCIDX. > Does this also fix the "+nossbs" issue we saw earlier this week? Yes, added a test https://github.com/llvm/llvm-project/pull/104435/files#diff-e355e3951d191d3a32265d9bdeb101e4f49ddfa6049ef058cf9e1dfdf7c19ef3 https://github.com/llvm/llvm-project/pull/104435 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/12] [AArch64] Add a check for invalid default features
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field):
> FEAT_SPECRES is mandatory from Armv8.5.
FeaturePredRes is added to the HasV8_5aOps.DefaultExts.
> FEAT_DIT is mandatory from Armv8.4.
FeatureDIT is added to the HasV8_4aOps.DefaultExts.
FEAT_SSBS is not mandatory for any architecture.
https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see
that in the Arm ARM.
FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts.
Cortex-A710 does not appear to have SSBS
https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en
Removed from the Cortex-A710 and Oryon print-supported-extensions tests.
https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/
Added to Apple A15/A16/A17 and (presumably?) M4 processor features.
> FEAT_BTI is mandatory from Armv8.5.
FeatureBranchTargetId is added to the DefaultExts
> FEAT_FlagM is mandatory from Armv8.4.
FeatureFlagM is added to the DefaultExts
> In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is
> implemented.
FeatureDotProd is added to the HasV8_4aOps.DefaultExts.
FIXME what about nofp here?
> FEAT_SB is mandatory from Armv8.5.
FeatureSB is added to HasV8_5aOps.DefaultExts.
Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`.
> FEAT_WFxT is mandatory from Armv8.7.
FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts.
> FEAT_CCIDX is OPTIONAL from Armv8.2.
Removed from Implies and added to HasV8_3aOps.DefaultExts and
HasV8_0rOps.DefaultExts.
For v8-R, FEAT_CCIDX is not mandatory, removed.
- Not implemented by cortex-r82, removed:
https://developer.arm.com/documentation/102670/0300/?lang=en
- Ditto cortex-r82ae
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-cortex-a710.c | 1 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
.../aarch64-oryon-1.c | 1 -
.../Preprocessor/aarch64-target-features.c| 4 +--
llvm/lib/Target/AArch64/AArch64Features.td| 16 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 11 ---
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../TargetParser/TargetParserTest.cpp | 21 ++--
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +--
14 files changed, 67 insertions(+), 41 deletions(-)
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-siz
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
@@ -283,9 +311,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
-// The apple-latest alias is backend only, do not expose it to -mcpu.
-if (Name == "apple-latest")
- continue;
tmatheson-arm wrote:
This check is duplicated at line 260, unrelated to this change.
https://github.com/llvm/llvm-project/pull/104435
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[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/16] [AArch64] Add a check for invalid default features
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field):
> FEAT_SPECRES is mandatory from Armv8.5.
FeaturePredRes is added to the HasV8_5aOps.DefaultExts.
> FEAT_DIT is mandatory from Armv8.4.
FeatureDIT is added to the HasV8_4aOps.DefaultExts.
FEAT_SSBS is not mandatory for any architecture.
https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see
that in the Arm ARM.
FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts.
Cortex-A710 does not appear to have SSBS
https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en
Removed from the Cortex-A710 and Oryon print-supported-extensions tests.
https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/
Added to Apple A15/A16/A17 and (presumably?) M4 processor features.
> FEAT_BTI is mandatory from Armv8.5.
FeatureBranchTargetId is added to the DefaultExts
> FEAT_FlagM is mandatory from Armv8.4.
FeatureFlagM is added to the DefaultExts
> In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is
> implemented.
FeatureDotProd is added to the HasV8_4aOps.DefaultExts.
FIXME what about nofp here?
> FEAT_SB is mandatory from Armv8.5.
FeatureSB is added to HasV8_5aOps.DefaultExts.
Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`.
> FEAT_WFxT is mandatory from Armv8.7.
FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts.
> FEAT_CCIDX is OPTIONAL from Armv8.2.
Removed from Implies and added to HasV8_3aOps.DefaultExts and
HasV8_0rOps.DefaultExts.
For v8-R, FEAT_CCIDX is not mandatory, removed.
- Not implemented by cortex-r82, removed:
https://developer.arm.com/documentation/102670/0300/?lang=en
- Ditto cortex-r82ae
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-cortex-a710.c | 1 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
.../aarch64-oryon-1.c | 1 -
.../Preprocessor/aarch64-target-features.c| 4 +--
llvm/lib/Target/AArch64/AArch64Features.td| 16 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 11 ---
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../TargetParser/TargetParserTest.cpp | 21 ++--
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +--
14 files changed, 67 insertions(+), 41 deletions(-)
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-siz
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/17] [AArch64] Add a check for invalid default features
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field):
> FEAT_SPECRES is mandatory from Armv8.5.
FeaturePredRes is added to the HasV8_5aOps.DefaultExts.
> FEAT_DIT is mandatory from Armv8.4.
FeatureDIT is added to the HasV8_4aOps.DefaultExts.
FEAT_SSBS is not mandatory for any architecture.
https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see
that in the Arm ARM.
FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts.
Cortex-A710 does not appear to have SSBS
https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en
Removed from the Cortex-A710 and Oryon print-supported-extensions tests.
https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/
Added to Apple A15/A16/A17 and (presumably?) M4 processor features.
> FEAT_BTI is mandatory from Armv8.5.
FeatureBranchTargetId is added to the DefaultExts
> FEAT_FlagM is mandatory from Armv8.4.
FeatureFlagM is added to the DefaultExts
> In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is
> implemented.
FeatureDotProd is added to the HasV8_4aOps.DefaultExts.
FIXME what about nofp here?
> FEAT_SB is mandatory from Armv8.5.
FeatureSB is added to HasV8_5aOps.DefaultExts.
Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`.
> FEAT_WFxT is mandatory from Armv8.7.
FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts.
> FEAT_CCIDX is OPTIONAL from Armv8.2.
Removed from Implies and added to HasV8_3aOps.DefaultExts and
HasV8_0rOps.DefaultExts.
For v8-R, FEAT_CCIDX is not mandatory, removed.
- Not implemented by cortex-r82, removed:
https://developer.arm.com/documentation/102670/0300/?lang=en
- Ditto cortex-r82ae
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-cortex-a710.c | 1 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
.../aarch64-oryon-1.c | 1 -
.../Preprocessor/aarch64-target-features.c| 4 +--
llvm/lib/Target/AArch64/AArch64Features.td| 16 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 11 ---
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../TargetParser/TargetParserTest.cpp | 21 ++--
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +--
14 files changed, 67 insertions(+), 41 deletions(-)
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-siz
[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)
https://github.com/tmatheson-arm milestoned https://github.com/llvm/llvm-project/pull/104435 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][test] Split invalid-cpu-note tests (PR #104601)
@@ -0,0 +1,382 @@
+// Use --implicit-check-not={{[a-zA-Z0-9]}} to ensure no additional CPUs are
in these lists
+
+// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix X86 --implicit-check-not={{[a-zA-Z0-9]}}
+// X86: error: unknown target CPU 'not-a-cpu'
+// X86-NEXT: note: valid target CPU values are:
+// X86-SAME: i386,
+// X86-SAME: i486,
+// X86-SAME: winchip-c6,
+// X86-SAME: winchip2,
+// X86-SAME: c3,
+// X86-SAME: i586,
+// X86-SAME: pentium,
+// X86-SAME: pentium-mmx,
+// X86-SAME: pentiumpro,
+// X86-SAME: i686,
+// X86-SAME: pentium2,
+// X86-SAME: pentium3,
+// X86-SAME: pentium3m,
+// X86-SAME: pentium-m,
+// X86-SAME: c3-2,
+// X86-SAME: yonah,
+// X86-SAME: pentium4,
+// X86-SAME: pentium4m,
+// X86-SAME: prescott,
+// X86-SAME: nocona,
+// X86-SAME: core2,
+// X86-SAME: penryn,
+// X86-SAME: bonnell,
+// X86-SAME: atom,
+// X86-SAME: silvermont,
+// X86-SAME: slm,
+// X86-SAME: goldmont,
+// X86-SAME: goldmont-plus,
+// X86-SAME: tremont,
+// X86-SAME: nehalem,
+// X86-SAME: corei7,
+// X86-SAME: westmere,
+// X86-SAME: sandybridge,
+// X86-SAME: corei7-avx,
+// X86-SAME: ivybridge,
+// X86-SAME: core-avx-i,
+// X86-SAME: haswell,
+// X86-SAME: core-avx2,
+// X86-SAME: broadwell,
+// X86-SAME: skylake,
+// X86-SAME: skylake-avx512,
+// X86-SAME: skx,
+// X86-SAME: cascadelake,
+// X86-SAME: cooperlake,
+// X86-SAME: cannonlake,
+// X86-SAME: icelake-client,
+// X86-SAME: rocketlake,
+// X86-SAME: icelake-server,
+// X86-SAME: tigerlake,
+// X86-SAME: sapphirerapids,
+// X86-SAME: alderlake,
+// X86-SAME: raptorlake,
+// X86-SAME: meteorlake,
+// X86-SAME: arrowlake,
+// X86-SAME: arrowlake-s,
+// X86-SAME: lunarlake,
+// X86-SAME: gracemont,
+// X86-SAME: pantherlake,
+// X86-SAME: sierraforest,
+// X86-SAME: grandridge,
+// X86-SAME: graniterapids,
+// X86-SAME: graniterapids-d,
+// X86-SAME: emeraldrapids,
+// X86-SAME: clearwaterforest,
+// X86-SAME: knl,
+// X86-SAME: knm,
+// X86-SAME: lakemont,
+// X86-SAME: k6,
+// X86-SAME: k6-2,
+// X86-SAME: k6-3,
+// X86-SAME: athlon,
+// X86-SAME: athlon-tbird,
+// X86-SAME: athlon-xp,
+// X86-SAME: athlon-mp,
+// X86-SAME: athlon-4,
+// X86-SAME: k8,
+// X86-SAME: athlon64,
+// X86-SAME: athlon-fx,
+// X86-SAME: opteron,
+// X86-SAME: k8-sse3,
+// X86-SAME: athlon64-sse3,
+// X86-SAME: opteron-sse3,
+// X86-SAME: amdfam10,
+// X86-SAME: barcelona,
+// X86-SAME: btver1,
+// X86-SAME: btver2,
+// X86-SAME: bdver1,
+// X86-SAME: bdver2,
+// X86-SAME: bdver3,
+// X86-SAME: bdver4,
+// X86-SAME: znver1,
+// X86-SAME: znver2,
+// X86-SAME: znver3,
+// X86-SAME: znver4,
+// X86-SAME: x86-64,
+// X86-SAME: x86-64-v2,
+// X86-SAME: x86-64-v3,
+// X86-SAME: x86-64-v4,
+// X86-SAME: geode
+// X86-SAME: {{$}}
+
+// RUN: not %clang_cc1 -triple x86_64--- -target-cpu not-a-cpu -fsyntax-only
%s 2>&1 | FileCheck %s --check-prefix=X86_64
--implicit-check-not={{[a-zA-Z0-9]}}
tmatheson-arm wrote:
nit: Should we keep all run lines at the top of the file?
https://github.com/llvm/llvm-project/pull/104601
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[clang] [clang][test] Split invalid-cpu-note tests (PR #104601)
https://github.com/tmatheson-arm approved this pull request. Thanks. This will make downstream maintenance much easier after the initial merge. https://github.com/llvm/llvm-project/pull/104601 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][test] Split invalid-cpu-note tests (PR #104601)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104601 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] set AppleA14 architecture version to v8.4-a (PR #92600)
@@ -718,12 +718,16 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
+ // Apple A14 and M1 chips are based on Armv8.5-a but without BTI. Since there
tmatheson-arm wrote:
As you point out, the only publicly available documentation is the optimization
guide, and lists these cores as "8.5 without BTI". Here in the tablegen file it
is written as 8.4 plus all of the features from 8.5 which are supported. A
comment explaining the discrepancy seems reasonable to me. It also alerts
people that if any new backend feature is introduced that models something in
8.5, they need to manually add it to the list for these cores.
https://github.com/llvm/llvm-project/pull/92600
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[clang] [llvm] [AArch64] set AppleA14 architecture version to v8.4-a (PR #92600)
@@ -286,7 +286,6 @@ void AArch64TargetInfo::getTargetDefinesARMV84A(const
LangOptions &Opts,
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
- Builder.defineMacro("__ARM_FEATURE_BTI", "1");
tmatheson-arm wrote:
Maybe in a separate PR.
https://github.com/llvm/llvm-project/pull/92600
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[clang] [llvm] [AArch64] set AppleA14 architecture version to v8.4-a (PR #92600)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92600
>From 518b83ab69c4852f7e7ea71c17df3f58e8ff50ef Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 17 May 2024 21:39:17 +0100
Subject: [PATCH 1/4] [AArch64] set AppleA14 architecture version to 8.5
---
llvm/lib/Target/AArch64/AArch64Processors.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index f2286ae17dba5..96422758bc618 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -718,7 +718,7 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
- list AppleA14 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
+ list AppleA14 = [HasV8_5aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFRInt3264,
FeatureSpecRestrict, FeatureSSBS,
FeatureSB,
FeaturePredRes, FeatureCacheDeepPersist,
>From 74f6d426fa67b1f794a8ba2ac7c864830ee9c2b2 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 20 May 2024 12:38:52 +0100
Subject: [PATCH 2/4] make m1+a14 v8.4 instead
---
clang/lib/Basic/Targets/AArch64.cpp| 4 +++-
clang/test/Driver/aarch64-mac-cpus.c | 2 +-
clang/test/Preprocessor/aarch64-target-features.c | 8 +++-
.../llvm/TargetParser/AArch64TargetParser.h| 4 ++--
llvm/lib/Target/AArch64/AArch64Processors.td | 14 +-
llvm/test/DebugInfo/debug_frame_symbol.ll | 2 +-
.../AddressSanitizer/calls-only-smallfn.ll | 2 +-
.../Instrumentation/AddressSanitizer/calls-only.ll | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 8
9 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 5db1ce78c657f..692ec58235efe 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -286,7 +286,6 @@ void AArch64TargetInfo::getTargetDefinesARMV84A(const
LangOptions &Opts,
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
- Builder.defineMacro("__ARM_FEATURE_BTI", "1");
// Also include the Armv8.4 defines
getTargetDefinesARMV84A(Opts, Builder);
}
@@ -499,6 +498,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasPAuthLR)
Builder.defineMacro("__ARM_FEATURE_PAUTH_LR", "1");
+ if (HasBTI)
+Builder.defineMacro("__ARM_FEATURE_BTI", "1");
+
if (HasUnalignedAccess)
Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
diff --git a/clang/test/Driver/aarch64-mac-cpus.c
b/clang/test/Driver/aarch64-mac-cpus.c
index 5179731268950..488298cfd2d24 100644
--- a/clang/test/Driver/aarch64-mac-cpus.c
+++ b/clang/test/Driver/aarch64-mac-cpus.c
@@ -16,7 +16,7 @@
// RUN: %clang --target=arm64-apple-macos -mcpu=apple-m1 -### -c %s 2>&1 |
FileCheck --check-prefix=EXPLICIT-M1 %s
// CHECK: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-m1"
-// CHECK-SAME: "-target-feature" "+v8.5a"
+// CHECK-SAME: "-target-feature" "+v8.4a"
// EXPLICIT-A11: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a11"
// EXPLICIT-A7: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a7"
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index 82304a15a04a3..3f2c2929c7129 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -335,7 +335,7 @@
// CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature"
"+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse"
"-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
"-target-feature" "+neon"
// RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 |
FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
-// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm"
"-target-feature" "+zcz" "-target-feature" "+v8.5a" "-target-feature" "+aes"
"-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature"
"+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16"
"-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature"
"+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature"
"+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-
[clang] [llvm] [AArch64] set AppleA14 architecture version to v8.4-a (PR #92600)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92600
>From 518b83ab69c4852f7e7ea71c17df3f58e8ff50ef Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 17 May 2024 21:39:17 +0100
Subject: [PATCH 1/5] [AArch64] set AppleA14 architecture version to 8.5
---
llvm/lib/Target/AArch64/AArch64Processors.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index f2286ae17dba5..96422758bc618 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -718,7 +718,7 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
- list AppleA14 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
+ list AppleA14 = [HasV8_5aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFRInt3264,
FeatureSpecRestrict, FeatureSSBS,
FeatureSB,
FeaturePredRes, FeatureCacheDeepPersist,
>From 74f6d426fa67b1f794a8ba2ac7c864830ee9c2b2 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 20 May 2024 12:38:52 +0100
Subject: [PATCH 2/5] make m1+a14 v8.4 instead
---
clang/lib/Basic/Targets/AArch64.cpp| 4 +++-
clang/test/Driver/aarch64-mac-cpus.c | 2 +-
clang/test/Preprocessor/aarch64-target-features.c | 8 +++-
.../llvm/TargetParser/AArch64TargetParser.h| 4 ++--
llvm/lib/Target/AArch64/AArch64Processors.td | 14 +-
llvm/test/DebugInfo/debug_frame_symbol.ll | 2 +-
.../AddressSanitizer/calls-only-smallfn.ll | 2 +-
.../Instrumentation/AddressSanitizer/calls-only.ll | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 8
9 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 5db1ce78c657f..692ec58235efe 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -286,7 +286,6 @@ void AArch64TargetInfo::getTargetDefinesARMV84A(const
LangOptions &Opts,
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
- Builder.defineMacro("__ARM_FEATURE_BTI", "1");
// Also include the Armv8.4 defines
getTargetDefinesARMV84A(Opts, Builder);
}
@@ -499,6 +498,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasPAuthLR)
Builder.defineMacro("__ARM_FEATURE_PAUTH_LR", "1");
+ if (HasBTI)
+Builder.defineMacro("__ARM_FEATURE_BTI", "1");
+
if (HasUnalignedAccess)
Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
diff --git a/clang/test/Driver/aarch64-mac-cpus.c
b/clang/test/Driver/aarch64-mac-cpus.c
index 5179731268950..488298cfd2d24 100644
--- a/clang/test/Driver/aarch64-mac-cpus.c
+++ b/clang/test/Driver/aarch64-mac-cpus.c
@@ -16,7 +16,7 @@
// RUN: %clang --target=arm64-apple-macos -mcpu=apple-m1 -### -c %s 2>&1 |
FileCheck --check-prefix=EXPLICIT-M1 %s
// CHECK: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-m1"
-// CHECK-SAME: "-target-feature" "+v8.5a"
+// CHECK-SAME: "-target-feature" "+v8.4a"
// EXPLICIT-A11: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a11"
// EXPLICIT-A7: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a7"
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index 82304a15a04a3..3f2c2929c7129 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -335,7 +335,7 @@
// CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature"
"+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse"
"-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
"-target-feature" "+neon"
// RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 |
FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
-// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm"
"-target-feature" "+zcz" "-target-feature" "+v8.5a" "-target-feature" "+aes"
"-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature"
"+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16"
"-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature"
"+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature"
"+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-
[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)
https://github.com/tmatheson-arm approved this pull request. LGTM. The main change to point out is that the target attribute will no longer accept internal feature names. I don't think it should ever have done so, but we should get input from others. @davemgreen? There are references to existing code in [D137617](https://reviews.llvm.org/D137617) but no details. If this has been used for e.g. intrinsics definitions, I am surprised there are not more test failures. https://github.com/llvm/llvm-project/pull/94279 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/94279 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)
@@ -13665,9 +13665,9 @@ QualType
ASTContext::getCorrespondingSignedFixedPointType(QualType Ty) const {
}
// Given a list of FMV features, add each of their backend features to the
list.
tmatheson-arm wrote:
```suggestion
// Given a list of FMV features, return a concatenated list of the corresponding
// backend features (which might contain duplicates).
```
https://github.com/llvm/llvm-project/pull/94279
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[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)
@@ -48,5 +48,5 @@ int test_versions() {
return code();
}
// CHECK: attributes #0 = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-// CHECK: attributes #1 = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+neon" }
-// CHECK: attributes #2 = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
tmatheson-arm wrote:
I think this is ok. `-march=armv8-a+nosimd+sve` gives `-target-feature -neon`,
i.e. `+sve` does not imply `+simd`. The reason we don't see `+neon` here is
because the test uses a `-cc1` command line and does not specify
`-target-feature +neon`, as the driver would for the same triple. So the test
is maybe not actually representative of what would be done if going through the
driver, but the changes here look correct given that nothing asks for `+neon`.
`+simd` now implies `+fp-armv8` because `def FeatureNEON` says it does.
https://github.com/llvm/llvm-project/pull/94279
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[clang] [llvm] [AArch64] set AppleA14 architecture version to v8.4-a (PR #92600)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92600
>From 518b83ab69c4852f7e7ea71c17df3f58e8ff50ef Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 17 May 2024 21:39:17 +0100
Subject: [PATCH 1/5] [AArch64] set AppleA14 architecture version to 8.5
---
llvm/lib/Target/AArch64/AArch64Processors.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index f2286ae17dba5..96422758bc618 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -718,7 +718,7 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
- list AppleA14 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
+ list AppleA14 = [HasV8_5aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFRInt3264,
FeatureSpecRestrict, FeatureSSBS,
FeatureSB,
FeaturePredRes, FeatureCacheDeepPersist,
>From 74f6d426fa67b1f794a8ba2ac7c864830ee9c2b2 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 20 May 2024 12:38:52 +0100
Subject: [PATCH 2/5] make m1+a14 v8.4 instead
---
clang/lib/Basic/Targets/AArch64.cpp| 4 +++-
clang/test/Driver/aarch64-mac-cpus.c | 2 +-
clang/test/Preprocessor/aarch64-target-features.c | 8 +++-
.../llvm/TargetParser/AArch64TargetParser.h| 4 ++--
llvm/lib/Target/AArch64/AArch64Processors.td | 14 +-
llvm/test/DebugInfo/debug_frame_symbol.ll | 2 +-
.../AddressSanitizer/calls-only-smallfn.ll | 2 +-
.../Instrumentation/AddressSanitizer/calls-only.ll | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 8
9 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 5db1ce78c657f..692ec58235efe 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -286,7 +286,6 @@ void AArch64TargetInfo::getTargetDefinesARMV84A(const
LangOptions &Opts,
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
- Builder.defineMacro("__ARM_FEATURE_BTI", "1");
// Also include the Armv8.4 defines
getTargetDefinesARMV84A(Opts, Builder);
}
@@ -499,6 +498,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasPAuthLR)
Builder.defineMacro("__ARM_FEATURE_PAUTH_LR", "1");
+ if (HasBTI)
+Builder.defineMacro("__ARM_FEATURE_BTI", "1");
+
if (HasUnalignedAccess)
Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
diff --git a/clang/test/Driver/aarch64-mac-cpus.c
b/clang/test/Driver/aarch64-mac-cpus.c
index 5179731268950..488298cfd2d24 100644
--- a/clang/test/Driver/aarch64-mac-cpus.c
+++ b/clang/test/Driver/aarch64-mac-cpus.c
@@ -16,7 +16,7 @@
// RUN: %clang --target=arm64-apple-macos -mcpu=apple-m1 -### -c %s 2>&1 |
FileCheck --check-prefix=EXPLICIT-M1 %s
// CHECK: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-m1"
-// CHECK-SAME: "-target-feature" "+v8.5a"
+// CHECK-SAME: "-target-feature" "+v8.4a"
// EXPLICIT-A11: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a11"
// EXPLICIT-A7: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a7"
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index 82304a15a04a3..3f2c2929c7129 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -335,7 +335,7 @@
// CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature"
"+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse"
"-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
"-target-feature" "+neon"
// RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 |
FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
-// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm"
"-target-feature" "+zcz" "-target-feature" "+v8.5a" "-target-feature" "+aes"
"-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature"
"+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16"
"-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature"
"+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature"
"+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-
[clang] 1b13bc0 - [AArch64] fix Windows buildbot failure
Author: Tomas Matheson Date: 2024-06-10T14:47:23+01:00 New Revision: 1b13bc05fe4a3b7b4916387543f0a64d41909e83 URL: https://github.com/llvm/llvm-project/commit/1b13bc05fe4a3b7b4916387543f0a64d41909e83 DIFF: https://github.com/llvm/llvm-project/commit/1b13bc05fe4a3b7b4916387543f0a64d41909e83.diff LOG: [AArch64] fix Windows buildbot failure Introduced by 2cf14398c9341feddb419e7ff9c8c5623a3da3db (#94279). See also 6c369cf937b7d9acb98a1fc46b1340cef7703e12. The build system cannot track transitive dependencies on generated headers for some reason. Added: Modified: clang/lib/AST/CMakeLists.txt Removed: diff --git a/clang/lib/AST/CMakeLists.txt b/clang/lib/AST/CMakeLists.txt index a5d3dacfc1a84..0328666d59b1f 100644 --- a/clang/lib/AST/CMakeLists.txt +++ b/clang/lib/AST/CMakeLists.txt @@ -139,4 +139,6 @@ add_clang_library(clangAST omp_gen ClangDriverOptions intrinsics_gen + # These generated headers are included transitively. + AArch64TargetParserTableGen ) ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] set AppleA14 architecture version to v8.4-a (PR #92600)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/92600 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Reland "[AArch64] Decouple feature dependency expansion. (#94279)" (PR #95231)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/95231 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/95214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -521,7 +521,14 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_SHA3, AArch64::AEK_FP16,
AArch64::AEK_FP16FML})},
-
+// Technically apple-m4 is ARMv9.2a, but a quirk of LLVM defines v9.0 as
+// requiring SVE, which is optional according to the Arm ARM and not
+// supported by the core. ARMv8.7a is the next closest choice.
tmatheson-arm wrote:
>From the Arm ARM:
> FEAT_SVE2 is OPTIONAL from Armv9.0.
In LLVM, SVE2 is an `Implied` (read: mandatory) feature of 9.0-a (wrong), and
SVE and SVE2 are both on by default for the architecture:
```
def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
[HasV8_5aOps, FeatureMEC, FeatureSVE2],
!listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE,
FeatureSVE2])>;
```
It should be possible to remove SVE2 from the `Implied` list while keeping it
in the list of default extensions, which would avoid any user-facing changes.
I'm not sure why FEAT_MEC is enabled there either.
> FEAT_MEC is OPTIONAL from Armv9.2.
https://github.com/llvm/llvm-project/pull/95478
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