[PATCH] D48088: [PowerPC] The __float128 type should only be available on Power9

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC334613: [PowerPC] The __float128 type should only be 
available on Power9 (authored by stefanp, committed by ).
Herald added a subscriber: cfe-commits.

Repository:
  rC Clang

https://reviews.llvm.org/D48088

Files:
  lib/Basic/Targets/PPC.cpp
  lib/Basic/Targets/PPC.h
  test/Driver/ppc-f128-support-check.c
  test/Preprocessor/init.c
  test/Sema/float128-ld-incompatibility.cpp

Index: test/Driver/ppc-f128-support-check.c
===
--- test/Driver/ppc-f128-support-check.c
+++ test/Driver/ppc-f128-support-check.c
@@ -0,0 +1,20 @@
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=HASF128
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=power9 -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=HASF128
+
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=NOF128
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=NOF128
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=NOF128
+
+#ifdef __FLOAT128__
+static_assert(false, "__float128 enabled");
+#endif
+
+// HASF128: __float128 enabled
+// HASF128-NOT: option '-mfloat128' cannot be specified with
+// NOF128: option '-mfloat128' cannot be specified with
+
Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -6370,7 +6370,7 @@
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 //
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
 // PPC-FLOAT128:#define __FLOAT128__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-unknown-linux-gnu -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPC64-LINUX %s
Index: test/Sema/float128-ld-incompatibility.cpp
===
--- test/Sema/float128-ld-incompatibility.cpp
+++ test/Sema/float128-ld-incompatibility.cpp
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
-// RUN: -triple powerpc64le-unknown-linux-gnu -target-cpu pwr8 \
+// RUN: -triple powerpc64le-unknown-linux-gnu -target-cpu pwr9 \
 // RUN: -target-feature +float128 %s
 // RUN: %clang_cc1 -fsyntax-only -std=c++11 -triple x86_64-unknown-linux-gnu -Wno-unused-value -Wno-parentheses %s
 
Index: lib/Basic/Targets/PPC.h
===
--- lib/Basic/Targets/PPC.h
+++ lib/Basic/Targets/PPC.h
@@ -18,13 +18,38 @@
 #include "clang/Basic/TargetInfo.h"
 #include "clang/Basic/TargetOptions.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/Support/Compiler.h"
 
 namespace clang {
 namespace targets {
 
 // PPC abstract base class
 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
+
+  /// Flags for architecture specific defines.
+  typedef enum {
+ArchDefineNone = 0,
+ArchDefineName = 1 << 0, //  is substituted for arch name.
+ArchDefinePpcgr = 1 << 1,
+ArchDefinePpcsq = 1 << 2,
+ArchDefine440 = 1 << 3,
+ArchDefine603 = 1 << 4,
+ArchDefine604 = 1 << 5,
+ArchDefinePwr4 = 1 << 6,
+ArchDefinePwr5 = 1 << 7,
+ArchDefinePwr5x = 1 << 8,
+ArchDefinePwr6 = 1 << 9,
+ArchDefinePwr6x = 1 << 10,
+ArchDefinePwr7 = 1 << 11,
+ArchDefinePwr8 = 1 << 12,
+ArchDefinePwr9 = 1 << 13,
+ArchDefineA2 = 1 << 14,
+ArchDefineA2q = 1 << 15
+  } ArchDefineTypes;
+
+
+  ArchDefineTypes ArchDefs;
   static const Builtin::Info BuiltinInfo[];
   static const char *const GCCRegNames[];
   static const TargetInfo::GCCRegAlias GCCRegAliases[];
@@ -50,34 +75,13 @@
   : TargetInfo(Triple), HasAltivec(false), HasVSX(false),
 HasP8Vector(false), HasP8Crypto(false), HasDirectMove(false),
 HasQPX(false), HasHTM(false), HasBPERMD(false), HasExtDiv(false),
-HasP9Vector(false) {
+HasP9Vector(false), ArchDefs(ArchDefineNone) {
 SuitableAlign = 128;
 SimdDefaultAlign = 128;
 LongDoubleWidth = LongDoubleAlign = 128;
 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
   }
 
-  /// Flags for architecture specific defines.
-  typedef enum {
-ArchDefineNone = 0,
-ArchDefineName = 1 << 0, //  is substitute

[PATCH] D48184: [Power9] [CLANG] Add __float128 exponent GET and SET builtins

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC342911: [Power9] [CLANG] Add __float128 exponent GET and SET 
builtins (authored by stefanp, committed by ).
Herald added subscribers: cfe-commits, jsji, kristina.

Changed prior to commit:
  https://reviews.llvm.org/D48184?vs=151392&id=166721#toc

Repository:
  rC Clang

https://reviews.llvm.org/D48184

Files:
  include/clang/Basic/BuiltinsPPC.def
  test/CodeGen/builtins-ppc-p9-f128.c


Index: include/clang/Basic/BuiltinsPPC.def
===
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -431,6 +431,8 @@
 BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "")
 BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "")
+BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "")
+BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "")
 
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
Index: test/CodeGen/builtins-ppc-p9-f128.c
===
--- test/CodeGen/builtins-ppc-p9-f128.c
+++ test/CodeGen/builtins-ppc-p9-f128.c
@@ -48,3 +48,15 @@
 // CHECK-NEXT: ret double
 }
 
+__float128 insert_exp_qp(unsigned long long int b) {
+  return __builtin_vsx_scalar_insert_exp_qp(A, b);
+// CHECK: @llvm.ppc.scalar.insert.exp.qp(fp128 %{{.+}}, i64
+// CHECK-NEXT: ret fp128
+}
+
+unsigned long long int extract_exp() {
+  return __builtin_vsx_scalar_extract_expq(A);
+// CHECK: @llvm.ppc.scalar.extract.expq(fp128
+// CHECK-NEXT: ret i64
+}
+


Index: include/clang/Basic/BuiltinsPPC.def
===
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -431,6 +431,8 @@
 BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "")
 BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "")
+BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "")
+BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "")
 
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
Index: test/CodeGen/builtins-ppc-p9-f128.c
===
--- test/CodeGen/builtins-ppc-p9-f128.c
+++ test/CodeGen/builtins-ppc-p9-f128.c
@@ -48,3 +48,15 @@
 // CHECK-NEXT: ret double
 }
 
+__float128 insert_exp_qp(unsigned long long int b) {
+  return __builtin_vsx_scalar_insert_exp_qp(A, b);
+// CHECK: @llvm.ppc.scalar.insert.exp.qp(fp128 %{{.+}}, i64
+// CHECK-NEXT: ret fp128
+}
+
+unsigned long long int extract_exp() {
+  return __builtin_vsx_scalar_extract_expq(A);
+// CHECK: @llvm.ppc.scalar.extract.expq(fp128
+// CHECK-NEXT: ret i64
+}
+
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[PATCH] D47548: [Power9] Add __float128 builtins for Round To Odd

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC336579: [Power9] Add __float128 builtins for Round To Odd 
(authored by stefanp, committed by ).
Herald added a subscriber: cfe-commits.

Repository:
  rC Clang

https://reviews.llvm.org/D47548

Files:
  include/clang/Basic/BuiltinsPPC.def
  test/CodeGen/builtins-ppc-p9-f128.c


Index: include/clang/Basic/BuiltinsPPC.def
===
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -423,6 +423,14 @@
 BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")
 BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
 
+// Float 128 built-ins
+BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "")
+BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "")
+BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "")
+BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "")
+BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "")
+BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "")
+
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
 BUILTIN(__builtin_tend, "UiUIi", "")
Index: test/CodeGen/builtins-ppc-p9-f128.c
===
--- test/CodeGen/builtins-ppc-p9-f128.c
+++ test/CodeGen/builtins-ppc-p9-f128.c
@@ -0,0 +1,45 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
+// RUN:   -target-cpu pwr9 -target-feature +float128 -o - %s | FileCheck %s
+
+__float128 A;
+__float128 B;
+__float128 C;
+
+
+__float128 testSqrtOdd() {
+  return __builtin_sqrtf128_round_to_odd(A);
+// CHECK: @llvm.ppc.sqrtf128.round.to.odd(fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testFMAOdd() {
+  return __builtin_fmaf128_round_to_odd(A, B, C);
+// CHECK: @llvm.ppc.fmaf128.round.to.odd(fp128 %{{.+}}, fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testAddOdd() {
+  return __builtin_addf128_round_to_odd(A, B);
+// CHECK: @llvm.ppc.addf128.round.to.odd(fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testSubOdd() {
+  return __builtin_subf128_round_to_odd(A, B);
+// CHECK: @llvm.ppc.subf128.round.to.odd(fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testMulOdd() {
+  return __builtin_mulf128_round_to_odd(A, B);
+// CHECK: @llvm.ppc.mulf128.round.to.odd(fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testDivOdd() {
+  return __builtin_divf128_round_to_odd(A, B);
+// CHECK: @llvm.ppc.divf128.round.to.odd(fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+


Index: include/clang/Basic/BuiltinsPPC.def
===
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -423,6 +423,14 @@
 BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")
 BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
 
+// Float 128 built-ins
+BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "")
+BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "")
+BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "")
+BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "")
+BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "")
+BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "")
+
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
 BUILTIN(__builtin_tend, "UiUIi", "")
Index: test/CodeGen/builtins-ppc-p9-f128.c
===
--- test/CodeGen/builtins-ppc-p9-f128.c
+++ test/CodeGen/builtins-ppc-p9-f128.c
@@ -0,0 +1,45 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
+// RUN:   -target-cpu pwr9 -target-feature +float128 -o - %s | FileCheck %s
+
+__float128 A;
+__float128 B;
+__float128 C;
+
+
+__float128 testSqrtOdd() {
+  return __builtin_sqrtf128_round_to_odd(A);
+// CHECK: @llvm.ppc.sqrtf128.round.to.odd(fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testFMAOdd() {
+  return __builtin_fmaf128_round_to_odd(A, B, C);
+// CHECK: @llvm.ppc.fmaf128.round.to.odd(fp128 %{{.+}}, fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testAddOdd() {
+  return __builtin_addf128_round_to_odd(A, B);
+// CHECK: @llvm.ppc.addf128.round.to.odd(fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testSubOdd() {
+  return __builtin_subf128_round_to_odd(A, B);
+// CHECK: @llvm.ppc.subf128.round.to.odd(fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testMulOdd() {
+  return __builtin_mulf128_round_to_odd(A, B);
+// CHECK: @llvm.ppc.mulf128.round.to.odd(fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+__float128 testDivOdd() {
+  return __builtin_divf128_round_to_odd(A, B);
+// CHECK: @llvm.ppc.divf128.round.to.odd(fp128 %{{.+}}, fp128
+// CHECK-NEXT: ret fp128
+}
+
+
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[PATCH] D48482: [Power9] [CLANG] Add __float128 support for trunc to double round to odd

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC336596: [Power9] [CLANG] Add __float128 support for trunc to 
double round to odd (authored by stefanp, committed by ).
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D48482?vs=152466&id=154687#toc

Repository:
  rC Clang

https://reviews.llvm.org/D48482

Files:
  include/clang/Basic/BuiltinsPPC.def
  test/CodeGen/builtins-ppc-p9-f128.c


Index: include/clang/Basic/BuiltinsPPC.def
===
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -430,6 +430,7 @@
 BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "")
+BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "")
 
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
Index: test/CodeGen/builtins-ppc-p9-f128.c
===
--- test/CodeGen/builtins-ppc-p9-f128.c
+++ test/CodeGen/builtins-ppc-p9-f128.c
@@ -42,4 +42,9 @@
 // CHECK-NEXT: ret fp128
 }
 
+double testTruncOdd() {
+  return __builtin_truncf128_round_to_odd(A);
+// CHECK: @llvm.ppc.truncf128.round.to.odd(fp128
+// CHECK-NEXT: ret double
+}
 


Index: include/clang/Basic/BuiltinsPPC.def
===
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -430,6 +430,7 @@
 BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "")
+BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "")
 
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
Index: test/CodeGen/builtins-ppc-p9-f128.c
===
--- test/CodeGen/builtins-ppc-p9-f128.c
+++ test/CodeGen/builtins-ppc-p9-f128.c
@@ -42,4 +42,9 @@
 // CHECK-NEXT: ret fp128
 }
 
+double testTruncOdd() {
+  return __builtin_truncf128_round_to_odd(A);
+// CHECK: @llvm.ppc.truncf128.round.to.odd(fp128
+// CHECK-NEXT: ret double
+}
 
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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision.
stefanp added a comment.

LGTM


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision.
stefanp added a comment.

LGTM


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[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision as: stefanp.
stefanp added a comment.

LGTM.


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[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

The title of the patch mentions both zero extend and sign extend.
However, it seems that we only have instructions for the zero extend case. Is 
that right?
I see both types of tests in:
`test/CodeGen/builtins-ppc-p10vector.c`
But I only see codegen tests for the zreo extend version.
`test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll`

I bring it up because I want to make sure that this is intentional.




Comment at: clang/lib/Headers/altivec.h:16516
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_sext(signed long long __offset, signed char *__pointer) {

I'm a little confused about this.
Your function signature says we return `vector unsigned __int128` but the 
return statement casts to `unaligned_vec_si128`. Is that how this is supposed 
to look?



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14163
+  if (!ValidLDType || (LD->getValueType(0) != MVT::i128) ||
+  (LD->getExtensionType() != ISD::ZEXTLOAD))
+return SDValue();

It looks like you are doing this for zero extend only. 
What about `ISD::EXTLOAD`? In that case the upper bits are undefined anyway so 
we can just assume a zero extend right?



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:41
+
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; These test cases tests that zero extending loads utilize the Load VSX Vector 
Rightmost

nit:
Was this line auto-added?
Usually this comment is added at the top of the file by the script. I don't 
think it is required here.


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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Just a few nits for this patch.




Comment at: clang/lib/Headers/altivec.h:17158
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_sl(vector signed __int128 __a, vector unsigned __int128 __b) {
+  return __builtin_altivec_vslq((vector unsigned __int128) __a, __b);

nit:
Is this supposed to be `vec_slq`?



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:10
+
+define dso_local <1 x i128> @test_vec_slq(<1 x i128> %a, <1 x i128> %b) #0 {
+; CHECK-LABEL: test_vec_slq:

nit:
If you are going to use `#0` you can probably define `attributes #0 = { 
nounwind }` at the bottom of this file.



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:41
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vslq(<1 x i128>, <1 x i128>) #1
+

nit: 
You probably don't need the #1 as it is not defined anyway.


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[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision as: stefanp.
stefanp added a comment.

LGTM.

Please wait for Lei to give the approval as well before you commit.




Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \

NeHuang wrote:
> Do we also need to run for big endian?
I don't think it would hurt to add a BE run for this as well. the only thing to 
watch out for is the fact that this is not actually a new file. This test file 
already exists on master so I assume that this will be merged in (and not added 
as a new file). 


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[PATCH] D77542: [PowerPC] Treat 'Z' inline asm constraint as a true memory constraint

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision as: stefanp.
stefanp added a comment.

Other than the two missing `K`s in the test case as Amy pointed out LGTM.


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Most of my comments are related to the fact that we are now inserting P10 
 between P9  and 
Future and so a few things need to change for the Future code to sit on top of 
P10  now.




Comment at: clang/test/Preprocessor/init-ppc64.c:652
 // PPCFUTURE:#define _ARCH_PPCSQ 1
 // PPCFUTURE:#define _ARCH_PWR4 1
 // PPCFUTURE:#define _ARCH_PWR5 1

Since we are adding P10 between P9 and Future we should add another line here:
```
PPCFUTURE:#define _ARCH_PWR10 1
```



Comment at: llvm/lib/Target/PowerPC/PPC.td:340
+  list P10SpecificFeatures =
+[FeaturePrefixInstrs, FeaturePCRelativeMemops];
+  list P10InheritableFeatures =

I think these can be moved up to `P10AdditionalFeatures`. That way everything 
on P10 is now inheritable by future and we don't have to specify anything for 
`FutureSpecificFeatures`.



Comment at: llvm/lib/Target/PowerPC/PPC.td:351
   list FutureSpecificFeatures =
 [FeaturePrefixInstrs, FeaturePCRelativeMemops];
   list FutureInheritableFeatures =

These features are now no longer `FutureSpecificFeatures` I would think that 
they would now be part of Power10 and should be inherited by future CPU. 



Comment at: llvm/test/CodeGen/PowerPC/check-cpu.ll:11
 
 ; Test mcpu=future that should be recognized on PowerPC.
 

nit:
We should probably update this comment too.


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[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 358915.
stefanp added a comment.

Sorry for letting this patch sit for so long.

I have updated the tests to simplify them so that we only include the
intrinsics (As per a comment). This reduces quite a bit of clutter.

Added Sema Checking for the builtins that were created.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-abs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-alloca.c
  clang/test/CodeGen/builtins-ppc-xlcompat-bpermd.c
  clang/test/CodeGen/builtins-ppc-xlcompat-cipher.c
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc-xlcompat-div.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-expect.c
  clang/test/CodeGen/builtins-ppc-xlcompat-fma.c
  clang/test/CodeGen/builtins-ppc-xlcompat-memory.c
  clang/test/CodeGen/builtins-ppc-xlcompat-mode.c
  clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,39 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+
+// CHECK-LABEL: @testrotatel4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.*}}, i32 {{%.*}})
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testrotatel4(unsigned int rs, unsigned int shift) {
+  return __rotatel4(rs, shift);
+}
+
+// CHECK-LABEL: @testrotatel8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
+// CHECK-NEXT:ret i64 [[TMP]]
+//
+unsigned long long testrotatel8(unsigned long long rs, unsigned long long shift) {
+  return __rotatel8(rs, shift);
+}
+
+// CHECK-LABEL: @testrdlam(
+// CHECK: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
+// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 7
+// CHECK-NEXT:ret i64 [[TMP1]]
+//
+unsigned long long testrdlam(unsigned long long rs, unsigned int shift) {
+  // The third parameter is a mask that must be a constant that represents a
+  // contiguous bit field.
+  return __rdlam(rs, shift, 7);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
@@ -0,0 +1,63 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+// CHECK-LABEL: @testcntlz4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.ctlz.i32(i32 {{%.*}}, i1 false)
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testcntlz4(unsigned int value) {
+  return __cntlz4(value);
+}
+
+// CHECK-LABEL: @testcntlz8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.ctlz.i64(i64 {{%.*}}, i1 false)
+// CHECK-NEXT:[[CAST:%.*]] = trunc i64 [[TMP]] to i32
+// CHECK-NEXT:ret i32 [[CAST]]
+//
+unsigned int testcntlz8(unsigned long long value) {
+  return __cntlz8(value);
+}
+
+// CHECK-LABEL: @testcnttz4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.cttz.i32(i32 {{%.*}}, i1 false)
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testcnttz4(unsigned int value) {
+  return __cnttz4(value);
+}
+
+// CHECK-LABEL: @

[PATCH] D106065: [Clang] Add an empty builtins.h file.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: nemanjai, lei.
Herald added a subscriber: mgorny.
stefanp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

On Power PC some legacy compilers included a number of builtins in a
builtins.h header file. While this header file is not required to hold
builtins for clang some legacy code does try to include this file and so
this patch provides an empty version of that file.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106065

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/builtins.h
  clang/test/Headers/builtins-header.c


Index: clang/test/Headers/builtins-header.c
===
--- /dev/null
+++ clang/test/Headers/builtins-header.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffreestanding -emit-llvm 
-o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -ffreestanding 
-emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+// Verify that we can include 
+
+// CHECK: target triple = "powerpc64
Index: clang/lib/Headers/builtins.h
===
--- /dev/null
+++ clang/lib/Headers/builtins.h
@@ -0,0 +1,12 @@
+/*=== builtins.h - Standard header for extra builtins 
-===*\
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+\*===--===*/
+
+#ifndef __BUILTINS_H
+#define __BUILTINS_H
+
+#endif /* __BUILTINS_H */
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -38,6 +38,7 @@
   avxvnniintrin.h
   bmi2intrin.h
   bmiintrin.h
+  builtins.h
   __clang_cuda_builtin_vars.h
   __clang_cuda_math.h
   __clang_cuda_cmath.h


Index: clang/test/Headers/builtins-header.c
===
--- /dev/null
+++ clang/test/Headers/builtins-header.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffreestanding -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -ffreestanding -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+// Verify that we can include 
+
+// CHECK: target triple = "powerpc64
Index: clang/lib/Headers/builtins.h
===
--- /dev/null
+++ clang/lib/Headers/builtins.h
@@ -0,0 +1,12 @@
+/*=== builtins.h - Standard header for extra builtins -===*\
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+\*===--===*/
+
+#ifndef __BUILTINS_H
+#define __BUILTINS_H
+
+#endif /* __BUILTINS_H */
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -38,6 +38,7 @@
   avxvnniintrin.h
   bmi2intrin.h
   bmiintrin.h
+  builtins.h
   __clang_cuda_builtin_vars.h
   __clang_cuda_math.h
   __clang_cuda_cmath.h
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[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 359054.
stefanp added a comment.

Realized after I updated the patch that I got the darn tests wrong.
I've updated the patch and fixed that.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-abs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-alloca.c
  clang/test/CodeGen/builtins-ppc-xlcompat-bpermd.c
  clang/test/CodeGen/builtins-ppc-xlcompat-cipher.c
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc-xlcompat-div.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-expect.c
  clang/test/CodeGen/builtins-ppc-xlcompat-fma.c
  clang/test/CodeGen/builtins-ppc-xlcompat-memory.c
  clang/test/CodeGen/builtins-ppc-xlcompat-mode.c
  clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,39 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+
+// CHECK-LABEL: @testrotatel4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.*}}, i32 {{%.*}})
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testrotatel4(unsigned int rs, unsigned int shift) {
+  return __rotatel4(rs, shift);
+}
+
+// CHECK-LABEL: @testrotatel8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
+// CHECK-NEXT:ret i64 [[TMP]]
+//
+unsigned long long testrotatel8(unsigned long long rs, unsigned long long shift) {
+  return __rotatel8(rs, shift);
+}
+
+// CHECK-LABEL: @testrdlam(
+// CHECK: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
+// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 7
+// CHECK-NEXT:ret i64 [[TMP1]]
+//
+unsigned long long testrdlam(unsigned long long rs, unsigned int shift) {
+  // The third parameter is a mask that must be a constant that represents a
+  // contiguous bit field.
+  return __rdlam(rs, shift, 7);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
@@ -0,0 +1,63 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+// CHECK-LABEL: @testcntlz4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.ctlz.i32(i32 {{%.*}}, i1 false)
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testcntlz4(unsigned int value) {
+  return __cntlz4(value);
+}
+
+// CHECK-LABEL: @testcntlz8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.ctlz.i64(i64 {{%.*}}, i1 false)
+// CHECK-NEXT:[[CAST:%.*]] = trunc i64 [[TMP]] to i32
+// CHECK-NEXT:ret i32 [[CAST]]
+//
+unsigned int testcntlz8(unsigned long long value) {
+  return __cntlz8(value);
+}
+
+// CHECK-LABEL: @testcnttz4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.cttz.i32(i32 {{%.*}}, i1 false)
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testcnttz4(unsigned int value) {
+  return __cnttz4(value);
+}
+
+// CHECK-LABEL: @testcnttz8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.cttz.i64(i64 {{%.*}}, i1 false)
+// CHECK-NEXT:[[CAST:%.*]] = trunc i64

[PATCH] D106065: [Clang] Add an empty builtins.h file.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 359186.
stefanp added a comment.

Added comment to the builtins.h file.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106065/new/

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Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/builtins.h
  clang/test/Headers/builtins-header.c


Index: clang/test/Headers/builtins-header.c
===
--- /dev/null
+++ clang/test/Headers/builtins-header.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffreestanding -emit-llvm 
-o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -ffreestanding 
-emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+// Verify that we can include 
+
+// CHECK: target triple = "powerpc64
Index: clang/lib/Headers/builtins.h
===
--- /dev/null
+++ clang/lib/Headers/builtins.h
@@ -0,0 +1,16 @@
+/*=== builtins.h - Standard header for extra builtins 
-===*\
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+\*===--===*/
+
+/// Some legacy compilers have builtin definitions in a file named builtins.h.
+/// This header file has been added to allow compatibility with code that was
+/// written for those compilers. Code may have an include line for this file
+/// and to avoid an error an empty file with this name is provided.
+#ifndef __BUILTINS_H
+#define __BUILTINS_H
+
+#endif /* __BUILTINS_H */
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -38,6 +38,7 @@
   avxvnniintrin.h
   bmi2intrin.h
   bmiintrin.h
+  builtins.h
   __clang_cuda_builtin_vars.h
   __clang_cuda_math.h
   __clang_cuda_cmath.h


Index: clang/test/Headers/builtins-header.c
===
--- /dev/null
+++ clang/test/Headers/builtins-header.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffreestanding -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -ffreestanding -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+// Verify that we can include 
+
+// CHECK: target triple = "powerpc64
Index: clang/lib/Headers/builtins.h
===
--- /dev/null
+++ clang/lib/Headers/builtins.h
@@ -0,0 +1,16 @@
+/*=== builtins.h - Standard header for extra builtins -===*\
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+\*===--===*/
+
+/// Some legacy compilers have builtin definitions in a file named builtins.h.
+/// This header file has been added to allow compatibility with code that was
+/// written for those compilers. Code may have an include line for this file
+/// and to avoid an error an empty file with this name is provided.
+#ifndef __BUILTINS_H
+#define __BUILTINS_H
+
+#endif /* __BUILTINS_H */
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -38,6 +38,7 @@
   avxvnniintrin.h
   bmi2intrin.h
   bmiintrin.h
+  builtins.h
   __clang_cuda_builtin_vars.h
   __clang_cuda_math.h
   __clang_cuda_cmath.h
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[PATCH] D106065: [Clang] Add an empty builtins.h file.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp marked an inline comment as not done.
stefanp added inline comments.



Comment at: clang/test/Headers/builtins-header.c:1
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffreestanding -emit-llvm 
-o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -ffreestanding 
-emit-llvm -o - %s | FileCheck %s

nemanjai wrote:
> Does this need something like `REQUIRES: powerpc-registered-target`?
I don't think so... but I could be wrong. I am testing this using the Power PC 
triple but in reality there is nothing specifically Power PC about this header 
file. I think that it can be included on any target.


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[PATCH] D106065: [Clang] Add an empty builtins.h file.

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0bf4b81d57b0: [Clang] Add an empty builtins.h file. 
(authored by stefanp).

Repository:
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Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/builtins.h
  clang/test/Headers/builtins-header.c


Index: clang/test/Headers/builtins-header.c
===
--- /dev/null
+++ clang/test/Headers/builtins-header.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffreestanding -emit-llvm 
-o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -ffreestanding 
-emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+// Verify that we can include 
+
+// CHECK: target triple = "powerpc64
Index: clang/lib/Headers/builtins.h
===
--- /dev/null
+++ clang/lib/Headers/builtins.h
@@ -0,0 +1,16 @@
+/*=== builtins.h - Standard header for extra builtins 
-===*\
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+\*===--===*/
+
+/// Some legacy compilers have builtin definitions in a file named builtins.h.
+/// This header file has been added to allow compatibility with code that was
+/// written for those compilers. Code may have an include line for this file
+/// and to avoid an error an empty file with this name is provided.
+#ifndef __BUILTINS_H
+#define __BUILTINS_H
+
+#endif /* __BUILTINS_H */
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -38,6 +38,7 @@
   avxvnniintrin.h
   bmi2intrin.h
   bmiintrin.h
+  builtins.h
   __clang_cuda_builtin_vars.h
   __clang_cuda_math.h
   __clang_cuda_cmath.h


Index: clang/test/Headers/builtins-header.c
===
--- /dev/null
+++ clang/test/Headers/builtins-header.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffreestanding -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -ffreestanding -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+// Verify that we can include 
+
+// CHECK: target triple = "powerpc64
Index: clang/lib/Headers/builtins.h
===
--- /dev/null
+++ clang/lib/Headers/builtins.h
@@ -0,0 +1,16 @@
+/*=== builtins.h - Standard header for extra builtins -===*\
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+\*===--===*/
+
+/// Some legacy compilers have builtin definitions in a file named builtins.h.
+/// This header file has been added to allow compatibility with code that was
+/// written for those compilers. Code may have an include line for this file
+/// and to avoid an error an empty file with this name is provided.
+#ifndef __BUILTINS_H
+#define __BUILTINS_H
+
+#endif /* __BUILTINS_H */
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -38,6 +38,7 @@
   avxvnniintrin.h
   bmi2intrin.h
   bmiintrin.h
+  builtins.h
   __clang_cuda_builtin_vars.h
   __clang_cuda_math.h
   __clang_cuda_cmath.h
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[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 359459.
stefanp added a comment.

Addressed a number of comments.

Replaced with Ops[0], Ops[1] where possible.
Rebased on top of the patch that defines SemaValueIsRunOfOnes. That patch is now
comitted anyway.

Merged a number of the test files. I was not able to merge all of the test files
as some of the builtins required Power 8 and up or Power 9 and up. Did not merge
existing files. Also did not merge the complex test file as it requires a
different check for LE, BE, and AIX.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cipher.c
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-expect.c
  clang/test/CodeGen/builtins-ppc-xlcompat-macros.c
  clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -55,3 +55,30 @@
   /*shift = 31, mask = 0x1FF = 511*/
   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
 }
+
+// CHECK-LABEL: @testrotatel4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.*}}, i32 {{%.*}})
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testrotatel4(unsigned int rs, unsigned int shift) {
+  return __rotatel4(rs, shift);
+}
+
+// CHECK-LABEL: @testrotatel8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
+// CHECK-NEXT:ret i64 [[TMP]]
+//
+unsigned long long testrotatel8(unsigned long long rs, unsigned long long shift) {
+  return __rotatel8(rs, shift);
+}
+
+// CHECK-LABEL: @testrdlam(
+// CHECK: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
+// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 7
+// CHECK-NEXT:ret i64 [[TMP1]]
+//
+unsigned long long testrdlam(unsigned long long rs, unsigned int shift) {
+  // The third parameter is a mask that must be a constant that represents a
+  // contiguous bit field.
+  return __rdlam(rs, shift, 7);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
@@ -1,4 +1,4 @@
-// REQUIRES: powerpc-registered-target.
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
@@ -12,9 +12,7 @@
 extern unsigned long long ull;
 
 // CHECK-LABEL: @test_builtin_ppc_poppar4(
-// CHECK: [[TMP0:%.*]] = load i32, i32* @ui, align 4
-// CHECK-NEXT:[[TMP1:%.*]] = load i32, i32* @ui, align 4
-// CHECK-NEXT:[[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]])
+// CHECK: [[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 {{.*}})
 // CHECK-NEXT:[[TMP3:%.*]] = and i32 [[TMP2]], 1
 // CHECK-NEXT:ret i32 [[TMP3]]
 //
@@ -23,9 +21,7 @@
 }
 
 // CHECK-LABEL: @test_builtin_ppc_poppar8(
-// CHECK: [[TMP0:%.*]] = load i64, i64* @ull, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @ull, align 8
-// CHECK-NEXT:[[TMP2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP1]])
+// CHECK: [[TMP2:%.*]] = call i64 @llvm.ctpop.i64(i64 {{.*}})
 // CHECK-NEXT:[[TMP3:%.*]] = and i64 [[TMP2]], 1
 // CHECK-NEXT:[[CAST:%.*]] = trunc i64 [[TMP3]] to i32
 // CHECK-NEXT:ret i32 [[CAST]]
@@ -33,3 +29,54 @@
 int test_builtin_ppc_poppar8() {
  return __builtin_ppc_poppar8(ull);
 }
+
+// CHECK-LABEL: @testcntlz4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.ctlz.i32(i32 {{%.*}}, i1 false)
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testcntlz4(unsigned int value) {
+  return __cntlz4(value);
+}
+
+// CHECK-LABEL: @testcntlz8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.ctlz.i64(i64 {{%.*}}, i1 false)
+// CHECK-NEXT:[[CAST:%.*]] = trunc i64 [[TMP]] to i32
+// CHECK-NEXT:ret i32 [[CAST]]
+//
+unsigned int testcntlz8(unsigned long long value) {
+  return __cntlz8(value);
+}
+
+// CHECK-LABEL: @testcnttz4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.cttz.i32(i32 {{%.*}}, i1 false)
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testcnttz4(unsigned int value) {
+  return __cnttz4(value);
+}
+
+// CHECK-LABEL: @testcnttz8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.cttz.i64(i64 {{%.*}}, i1 false)
+// CHECK-NEX

[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp marked an inline comment as not done.
stefanp added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:9732
   "argument should be an 8-bit value shifted by a multiple of 8 bits, or in 
the form 0x??FF">;
+def err_argument_not_contiguous_bit_field : Error<
+  "argument %0 value should represent a contiguous bit field">;

nemanjai wrote:
> I think this comes from another patch that is up for review. You should base 
> this patch on top of that patch and mark the review as a dependency. It makes 
> the review easier if the review only contains code that is meant to go in 
> this commit.
Yes it does. That patch has actually already gone in so I've just rebased on 
top of it and solved this issue that way.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15257-15258
+const Expr *Ptr = E->getArg(1);
+Value *PtrValue = EmitScalarExpr(Ptr);
+Value *AlignmentValue = EmitScalarExpr(E->getArg(0));
+ConstantInt *AlignmentCI = cast(AlignmentValue);

nemanjai wrote:
> Are these two just `Ops[0], Ops[1]`?
Yes they are. I will replace where possible.


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[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG02cd937945f8: [PowerPC][Builtins] Added a number of builtins 
for compatibility with XL. (authored by stefanp).

Changed prior to commit:
  https://reviews.llvm.org/D104386?vs=359459&id=360111#toc

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cipher.c
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-expect.c
  clang/test/CodeGen/builtins-ppc-xlcompat-macros.c
  clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -55,3 +55,30 @@
   /*shift = 31, mask = 0x1FF = 511*/
   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
 }
+
+// CHECK-LABEL: @testrotatel4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.*}}, i32 {{%.*}})
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testrotatel4(unsigned int rs, unsigned int shift) {
+  return __rotatel4(rs, shift);
+}
+
+// CHECK-LABEL: @testrotatel8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
+// CHECK-NEXT:ret i64 [[TMP]]
+//
+unsigned long long testrotatel8(unsigned long long rs, unsigned long long shift) {
+  return __rotatel8(rs, shift);
+}
+
+// CHECK-LABEL: @testrdlam(
+// CHECK: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
+// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 7
+// CHECK-NEXT:ret i64 [[TMP1]]
+//
+unsigned long long testrdlam(unsigned long long rs, unsigned int shift) {
+  // The third parameter is a mask that must be a constant that represents a
+  // contiguous bit field.
+  return __rdlam(rs, shift, 7);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
@@ -1,4 +1,4 @@
-// REQUIRES: powerpc-registered-target.
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
@@ -12,9 +12,7 @@
 extern unsigned long long ull;
 
 // CHECK-LABEL: @test_builtin_ppc_poppar4(
-// CHECK: [[TMP0:%.*]] = load i32, i32* @ui, align 4
-// CHECK-NEXT:[[TMP1:%.*]] = load i32, i32* @ui, align 4
-// CHECK-NEXT:[[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]])
+// CHECK: [[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 {{.*}})
 // CHECK-NEXT:[[TMP3:%.*]] = and i32 [[TMP2]], 1
 // CHECK-NEXT:ret i32 [[TMP3]]
 //
@@ -23,9 +21,7 @@
 }
 
 // CHECK-LABEL: @test_builtin_ppc_poppar8(
-// CHECK: [[TMP0:%.*]] = load i64, i64* @ull, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @ull, align 8
-// CHECK-NEXT:[[TMP2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP1]])
+// CHECK: [[TMP2:%.*]] = call i64 @llvm.ctpop.i64(i64 {{.*}})
 // CHECK-NEXT:[[TMP3:%.*]] = and i64 [[TMP2]], 1
 // CHECK-NEXT:[[CAST:%.*]] = trunc i64 [[TMP3]] to i32
 // CHECK-NEXT:ret i32 [[CAST]]
@@ -33,3 +29,54 @@
 int test_builtin_ppc_poppar8() {
  return __builtin_ppc_poppar8(ull);
 }
+
+// CHECK-LABEL: @testcntlz4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.ctlz.i32(i32 {{%.*}}, i1 false)
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testcntlz4(unsigned int value) {
+  return __cntlz4(value);
+}
+
+// CHECK-LABEL: @testcntlz8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.ctlz.i64(i64 {{%.*}}, i1 false)
+// CHECK-NEXT:[[CAST:%.*]] = trunc i64 [[TMP]] to i32
+// CHECK-NEXT:ret i32 [[CAST]]
+//
+unsigned int testcntlz8(unsigned long long value) {
+  return __cntlz8(value);
+}
+
+// CHECK-LABEL: @testcnttz4(
+// CHECK: [[TMP:%.*]] = call i32 @llvm.cttz.i32(i32 {{%.*}}, i1 false)
+// CHECK-NEXT:ret i32 [[TMP]]
+//
+unsigned int testcnttz4(unsigned int value) {
+  return __cnttz4(value);
+}
+
+// CHECK-LABEL: @testcnttz8(
+// CHECK: [[TMP:%.*]] = call i64 @llvm.cttz.i64(i64 {{%.*}}, i1 false)
+// CHECK-NEXT:[[CAST:%.*]] = trunc i64 [[TMP]] to i32
+// CHECK-NEXT:ret i32 [[CAST]]
+//
+unsigned int testcnttz8(unsigned long long value) {
+  return __cnttz8(value);
+}
+
+// CH

[PATCH] D91279: [PowerPC] DForm instructions should be preferred when using zero register

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

In D91279#2390160 , @shchenz wrote:

> Using dform with offset 0 can save one register r0/X0, this is benefit for 
> register allocation? But adding it in `PPCPreEmitPeephole` pass which is 
> after register allocation will make the benefit gone.
> Maybe we need to do it before register allocation? For example at the place 
> where the x-form with zero register is generated.
>
> I checked one example `loadConstant` in  
> `test/CodeGen/PowerPC/f128-passByValue.ll`.
> We generate `LXVX $zero8, ` in ISEL because we meet the worst case and we 
> don't have d-form choice for the instruction selection. so we have to use 
> x-form and in x-form selection, we have to use zero/zero8 as the base and use 
> load address as the index. See `PPCTargetLowering::SelectAddressRegRegOnly`.
>
> I guess most cases are with same reason for generating x-form + zero 
> register, we meet the worst case in ISEL, so we have to use x-form + zero 
> register form, with this form, we can always select a powerpc load/store 
> instruction.
>
> For me, a better solution should be change the worst case handling in ISEL, 
> it is before RA and it is also transparent for types like STXVX/LXVX/ and 
> also LDX/STDX, LFDX/STFDX...

I'm just going to jump in to give a little more background. The initial reason 
we wanted to do this was to enable an optimization that actually happens in the 
linker after the code is emitted.
To get the idea you can look at this test:

  /llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll

Which contains this section:

  ; FIXME: we should always convert X-Form instructions that use
  ; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt.
  define dso_local void @ReadWrite128() local_unnamed_addr #0 {
  ; CHECK-LABEL: ReadWrite128:
  ; CHECK:   # %bb.0: # %entry
  ; CHECK-NEXT:pld r3, input128@got@pcrel(0), 1
  ; CHECK-NEXT:lxvx vs0, 0, r3
  ; CHECK-NEXT:pld r3, output128@got@pcrel(0), 1
  ; CHECK-NEXT:stxvx vs0, 0, r3
  ; CHECK-NEXT:blr
  entry:
%0 = load i128, i128* @input128, align 16
store i128 %0, i128* @output128, align 16
ret void
  }

When we have a GOT access like this it is possible for the compiler to mark the 
instruction with `R_PPC64_PCREL_OPT` and then the linker merges the two 
instructions into one and replaces the second instruction with a `nop`. The 
problem is that this opt can only be done if the second instruction is DForm. 
We noticed that when we implemented this optimization we could not catch all of 
the cases because in some situations (like the one above) we use the XForm 
instead of the DForm.

Having said that, we should try to do this before the PreEmitPeephole. The 
optimization that adds the `R_PPC64_PCREL_OPT` relocation is also in the 
PreEmitPeephole and I'm not sure if it will be detected if we do both things at 
the same time (both as in convert the XForm to a DForm and then have the same 
opt use that DForm to add the relocation).

I agree that ISel is a better place for this. If we cannot do this in ISel then 
we should still try to do this before we get to the PreEmitPeephole or at least 
make sure that both the DForm is present and that the `R_PPC64_PCREL_OPT` 
relocation is added as we expected in the same pass.


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[PATCH] D91279: [PowerPC] DForm instructions should be preferred when using zero register

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

In D91279#2400854 , @stefanp wrote:

> In D91279#2390160 , @shchenz wrote:
>
>> Using dform with offset 0 can save one register r0/X0, this is benefit for 
>> register allocation? But adding it in `PPCPreEmitPeephole` pass which is 
>> after register allocation will make the benefit gone.
>> Maybe we need to do it before register allocation? For example at the place 
>> where the x-form with zero register is generated.
>>
>> I checked one example `loadConstant` in  
>> `test/CodeGen/PowerPC/f128-passByValue.ll`.
>> We generate `LXVX $zero8, ` in ISEL because we meet the worst case and we 
>> don't have d-form choice for the instruction selection. so we have to use 
>> x-form and in x-form selection, we have to use zero/zero8 as the base and 
>> use load address as the index. See 
>> `PPCTargetLowering::SelectAddressRegRegOnly`.
>>
>> I guess most cases are with same reason for generating x-form + zero 
>> register, we meet the worst case in ISEL, so we have to use x-form + zero 
>> register form, with this form, we can always select a powerpc load/store 
>> instruction.
>>
>> For me, a better solution should be change the worst case handling in ISEL, 
>> it is before RA and it is also transparent for types like STXVX/LXVX/ and 
>> also LDX/STDX, LFDX/STFDX...
>
> I'm just going to jump in to give a little more background. The initial 
> reason we wanted to do this was to enable an optimization that actually 
> happens in the linker after the code is emitted.
> To get the idea you can look at this test:
>
>   /llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll
>
> Which contains this section:
>
>   ; FIXME: we should always convert X-Form instructions that use
>   ; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt.
>   define dso_local void @ReadWrite128() local_unnamed_addr #0 {
>   ; CHECK-LABEL: ReadWrite128:
>   ; CHECK:   # %bb.0: # %entry
>   ; CHECK-NEXT:pld r3, input128@got@pcrel(0), 1
>   ; CHECK-NEXT:lxvx vs0, 0, r3
>   ; CHECK-NEXT:pld r3, output128@got@pcrel(0), 1
>   ; CHECK-NEXT:stxvx vs0, 0, r3
>   ; CHECK-NEXT:blr
>   entry:
> %0 = load i128, i128* @input128, align 16
> store i128 %0, i128* @output128, align 16
> ret void
>   }
>
> When we have a GOT access like this it is possible for the compiler to mark 
> the instruction with `R_PPC64_PCREL_OPT` and then the linker merges the two 
> instructions into one and replaces the second instruction with a `nop`. The 
> problem is that this opt can only be done if the second instruction is DForm. 
> We noticed that when we implemented this optimization we could not catch all 
> of the cases because in some situations (like the one above) we use the XForm 
> instead of the DForm.
>
> Having said that, we should try to do this before the PreEmitPeephole. The 
> optimization that adds the `R_PPC64_PCREL_OPT` relocation is also in the 
> PreEmitPeephole and I'm not sure if it will be detected if we do both things 
> at the same time (both as in convert the XForm to a DForm and then have the 
> same opt use that DForm to add the relocation).
>
> I agree that ISel is a better place for this. If we cannot do this in ISel 
> then we should still try to do this before we get to the PreEmitPeephole or 
> at least make sure that both the DForm is present and that the 
> `R_PPC64_PCREL_OPT` relocation is added as we expected in the same pass.

After a discussion with the group I would like to correct what I said in the 
previous post.
There already is a plan to do this in ISel in a different patch. The reason we 
also want to do this optimization here is to try to catch situations where this 
pattern is not known in ISel and only appears after other optimizations later 
on. Ideally we do not want to have any situations where the XForm exists in the 
final binary and having this final check in the PreEmitPeephole should ensure 
that. Basically, we also want to do this check here to find anything that ISel 
may have missed.


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[PATCH] D88886: [Clang][unittests][NFC] Break up test in Callbacks.cpp

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added a reviewer: nemanjai.
Herald added a subscriber: mgorny.
Herald added a project: clang.
stefanp requested review of this revision.

The Callbacks.cpp test was taking a long time to compile on some build bots
causing timeouts. This patch splits up that test into five separate cpp
files and a header file.


Repository:
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https://reviews.llvm.org/D6

Files:
  clang/unittests/Tooling/CMakeLists.txt
  clang/unittests/Tooling/RecursiveASTVisitorTests/Callbacks.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksBinaryOperator.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCallExpr.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCommon.h
  
clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCompoundAssignOperator.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksLeaf.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp

Index: clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp
===
--- /dev/null
+++ clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp
@@ -0,0 +1,201 @@
+//===--- clang/unittests/Tooling/RecursiveASTVisitorTests/Callbacks.cpp ---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "CallbacksCommon.h"
+#include "TestVisitor.h"
+
+TEST(RecursiveASTVisitor, StmtCallbacks_TraverseUnaryOperator) {
+  class RecordingVisitor : public RecordingVisitorBase {
+  public:
+RecordingVisitor(ShouldTraversePostOrder ShouldTraversePostOrderValue)
+: RecordingVisitorBase(ShouldTraversePostOrderValue) {}
+
+bool TraverseUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::TraverseUnaryOperator(UO);
+  });
+  return true;
+}
+
+bool WalkUpFromStmt(Stmt *S) {
+  recordCallback(__func__, S,
+ [&]() { RecordingVisitorBase::WalkUpFromStmt(S); });
+  return true;
+}
+  };
+
+  StringRef Code = R"cpp(
+void test() {
+  1;
+  -2;
+  3;
+}
+)cpp";
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::No), Code,
+  R"txt(
+WalkUpFromStmt CompoundStmt
+WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromStmt UnaryOperator(-)
+  WalkUpFromStmt IntegerLiteral(2)
+WalkUpFromStmt IntegerLiteral(3)
+)txt"));
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::Yes), Code,
+  R"txt(
+WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromStmt IntegerLiteral(2)
+  WalkUpFromStmt UnaryOperator(-)
+WalkUpFromStmt IntegerLiteral(3)
+WalkUpFromStmt CompoundStmt
+)txt"));
+}
+
+TEST(RecursiveASTVisitor,
+ StmtCallbacks_TraverseUnaryOperator_WalkUpFromUnaryOperator) {
+  class RecordingVisitor : public RecordingVisitorBase {
+  public:
+RecordingVisitor(ShouldTraversePostOrder ShouldTraversePostOrderValue)
+: RecordingVisitorBase(ShouldTraversePostOrderValue) {}
+
+bool TraverseUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::TraverseUnaryOperator(UO);
+  });
+  return true;
+}
+
+bool WalkUpFromStmt(Stmt *S) {
+  recordCallback(__func__, S,
+ [&]() { RecordingVisitorBase::WalkUpFromStmt(S); });
+  return true;
+}
+
+bool WalkUpFromExpr(Expr *E) {
+  recordCallback(__func__, E,
+ [&]() { RecordingVisitorBase::WalkUpFromExpr(E); });
+  return true;
+}
+
+bool WalkUpFromUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::WalkUpFromUnaryOperator(UO);
+  });
+  return true;
+}
+  };
+
+  StringRef Code = R"cpp(
+void test() {
+  1;
+  -2;
+  3;
+}
+)cpp";
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::No), Code,
+  R"txt(
+WalkUpFromStmt CompoundStmt
+WalkUpFromExpr IntegerLiteral(1)
+  WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromUnaryOperator UnaryOperator(-)
+WalkUpFromExpr UnaryOperator(-)
+  WalkUpFromStmt UnaryOperator(-)
+  WalkUpFromExpr IntegerLiteral(2)
+WalkUpFromStmt IntegerLiteral(2)
+WalkUpFromExpr IntegerLiteral(3)
+  WalkUpFromStmt IntegerLiteral(3)
+)txt"));
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::Yes), Code,
+  R"txt(
+WalkUpFromExpr IntegerLiteral(1)
+  WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromExpr In

[PATCH] D88886: [Clang][unittests][NFC] Break up test in Callbacks.cpp

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Related to this please see Nemanja's comment on https://reviews.llvm.org/D82485.


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[PATCH] D88886: [Clang][unittests][NFC] Break up test in Callbacks.cpp

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 296970.
stefanp added a comment.

Added the missing header file.
Added the license comment.


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Files:
  clang/unittests/Tooling/CMakeLists.txt
  clang/unittests/Tooling/RecursiveASTVisitorTests/Callbacks.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksBinaryOperator.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCallExpr.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCommon.h
  
clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCompoundAssignOperator.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksLeaf.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp

Index: clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp
===
--- /dev/null
+++ clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp
@@ -0,0 +1,200 @@
+//===- unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "CallbacksCommon.h"
+
+TEST(RecursiveASTVisitor, StmtCallbacks_TraverseUnaryOperator) {
+  class RecordingVisitor : public RecordingVisitorBase {
+  public:
+RecordingVisitor(ShouldTraversePostOrder ShouldTraversePostOrderValue)
+: RecordingVisitorBase(ShouldTraversePostOrderValue) {}
+
+bool TraverseUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::TraverseUnaryOperator(UO);
+  });
+  return true;
+}
+
+bool WalkUpFromStmt(Stmt *S) {
+  recordCallback(__func__, S,
+ [&]() { RecordingVisitorBase::WalkUpFromStmt(S); });
+  return true;
+}
+  };
+
+  StringRef Code = R"cpp(
+void test() {
+  1;
+  -2;
+  3;
+}
+)cpp";
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::No), Code,
+  R"txt(
+WalkUpFromStmt CompoundStmt
+WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromStmt UnaryOperator(-)
+  WalkUpFromStmt IntegerLiteral(2)
+WalkUpFromStmt IntegerLiteral(3)
+)txt"));
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::Yes), Code,
+  R"txt(
+WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromStmt IntegerLiteral(2)
+  WalkUpFromStmt UnaryOperator(-)
+WalkUpFromStmt IntegerLiteral(3)
+WalkUpFromStmt CompoundStmt
+)txt"));
+}
+
+TEST(RecursiveASTVisitor,
+ StmtCallbacks_TraverseUnaryOperator_WalkUpFromUnaryOperator) {
+  class RecordingVisitor : public RecordingVisitorBase {
+  public:
+RecordingVisitor(ShouldTraversePostOrder ShouldTraversePostOrderValue)
+: RecordingVisitorBase(ShouldTraversePostOrderValue) {}
+
+bool TraverseUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::TraverseUnaryOperator(UO);
+  });
+  return true;
+}
+
+bool WalkUpFromStmt(Stmt *S) {
+  recordCallback(__func__, S,
+ [&]() { RecordingVisitorBase::WalkUpFromStmt(S); });
+  return true;
+}
+
+bool WalkUpFromExpr(Expr *E) {
+  recordCallback(__func__, E,
+ [&]() { RecordingVisitorBase::WalkUpFromExpr(E); });
+  return true;
+}
+
+bool WalkUpFromUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::WalkUpFromUnaryOperator(UO);
+  });
+  return true;
+}
+  };
+
+  StringRef Code = R"cpp(
+void test() {
+  1;
+  -2;
+  3;
+}
+)cpp";
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::No), Code,
+  R"txt(
+WalkUpFromStmt CompoundStmt
+WalkUpFromExpr IntegerLiteral(1)
+  WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromUnaryOperator UnaryOperator(-)
+WalkUpFromExpr UnaryOperator(-)
+  WalkUpFromStmt UnaryOperator(-)
+  WalkUpFromExpr IntegerLiteral(2)
+WalkUpFromStmt IntegerLiteral(2)
+WalkUpFromExpr IntegerLiteral(3)
+  WalkUpFromStmt IntegerLiteral(3)
+)txt"));
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::Yes), Code,
+  R"txt(
+WalkUpFromExpr IntegerLiteral(1)
+  WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromExpr IntegerLiteral(2)
+WalkUpFromStmt IntegerLiteral(2)
+  WalkUpFromUnaryOperator UnaryOperator(-)
+WalkUpFromExpr UnaryOperator(-)
+  WalkUpFromStmt UnaryOperator(-)
+Wa

[PATCH] D88886: [Clang][unittests][NFC] Break up test in Callbacks.cpp

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0741a2c9caca: [Clang][unittests][NFC] Break up test in 
Callbacks.cpp (authored by stefanp).

Repository:
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Files:
  clang/unittests/Tooling/CMakeLists.txt
  clang/unittests/Tooling/RecursiveASTVisitorTests/Callbacks.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksBinaryOperator.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCallExpr.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCommon.h
  
clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCompoundAssignOperator.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksLeaf.cpp
  clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp

Index: clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp
===
--- /dev/null
+++ clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp
@@ -0,0 +1,200 @@
+//===- unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "CallbacksCommon.h"
+
+TEST(RecursiveASTVisitor, StmtCallbacks_TraverseUnaryOperator) {
+  class RecordingVisitor : public RecordingVisitorBase {
+  public:
+RecordingVisitor(ShouldTraversePostOrder ShouldTraversePostOrderValue)
+: RecordingVisitorBase(ShouldTraversePostOrderValue) {}
+
+bool TraverseUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::TraverseUnaryOperator(UO);
+  });
+  return true;
+}
+
+bool WalkUpFromStmt(Stmt *S) {
+  recordCallback(__func__, S,
+ [&]() { RecordingVisitorBase::WalkUpFromStmt(S); });
+  return true;
+}
+  };
+
+  StringRef Code = R"cpp(
+void test() {
+  1;
+  -2;
+  3;
+}
+)cpp";
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::No), Code,
+  R"txt(
+WalkUpFromStmt CompoundStmt
+WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromStmt UnaryOperator(-)
+  WalkUpFromStmt IntegerLiteral(2)
+WalkUpFromStmt IntegerLiteral(3)
+)txt"));
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::Yes), Code,
+  R"txt(
+WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromStmt IntegerLiteral(2)
+  WalkUpFromStmt UnaryOperator(-)
+WalkUpFromStmt IntegerLiteral(3)
+WalkUpFromStmt CompoundStmt
+)txt"));
+}
+
+TEST(RecursiveASTVisitor,
+ StmtCallbacks_TraverseUnaryOperator_WalkUpFromUnaryOperator) {
+  class RecordingVisitor : public RecordingVisitorBase {
+  public:
+RecordingVisitor(ShouldTraversePostOrder ShouldTraversePostOrderValue)
+: RecordingVisitorBase(ShouldTraversePostOrderValue) {}
+
+bool TraverseUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::TraverseUnaryOperator(UO);
+  });
+  return true;
+}
+
+bool WalkUpFromStmt(Stmt *S) {
+  recordCallback(__func__, S,
+ [&]() { RecordingVisitorBase::WalkUpFromStmt(S); });
+  return true;
+}
+
+bool WalkUpFromExpr(Expr *E) {
+  recordCallback(__func__, E,
+ [&]() { RecordingVisitorBase::WalkUpFromExpr(E); });
+  return true;
+}
+
+bool WalkUpFromUnaryOperator(UnaryOperator *UO) {
+  recordCallback(__func__, UO, [&]() {
+RecordingVisitorBase::WalkUpFromUnaryOperator(UO);
+  });
+  return true;
+}
+  };
+
+  StringRef Code = R"cpp(
+void test() {
+  1;
+  -2;
+  3;
+}
+)cpp";
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::No), Code,
+  R"txt(
+WalkUpFromStmt CompoundStmt
+WalkUpFromExpr IntegerLiteral(1)
+  WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromUnaryOperator UnaryOperator(-)
+WalkUpFromExpr UnaryOperator(-)
+  WalkUpFromStmt UnaryOperator(-)
+  WalkUpFromExpr IntegerLiteral(2)
+WalkUpFromStmt IntegerLiteral(2)
+WalkUpFromExpr IntegerLiteral(3)
+  WalkUpFromStmt IntegerLiteral(3)
+)txt"));
+
+  EXPECT_TRUE(visitorCallbackLogEqual(
+  RecordingVisitor(ShouldTraversePostOrder::Yes), Code,
+  R"txt(
+WalkUpFromExpr IntegerLiteral(1)
+  WalkUpFromStmt IntegerLiteral(1)
+TraverseUnaryOperator UnaryOperator(-)
+  WalkUpFromExpr IntegerLiteral(2)
+WalkUpFromStmt IntegerLiteral(2)
+  WalkUpFro

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 348341.
stefanp added a comment.

Rebased revision to top of trunk.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2021,6 +2021,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2542,11 +2544,19 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmitTimePseudo<(

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 348387.
stefanp added a comment.

Updated author to Quinn.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2021,6 +2021,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2542,11 +2544,19 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmitTimePseudo<(outs), (i

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG62b5df7fe2b3: [PowerPC] Added multiple PowerPC builtins 
(authored by quinnp, committed by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2021,6 +2021,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2542,11 +2544,19 @@
 def EnforceIEIO 

[PATCH] D103615: [Clang] Add option for vector compare compatibility.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: nemanjai, lei, rsmith.
Herald added subscribers: dexonsmith, dang.
stefanp requested review of this revision.
Herald added a project: clang.

Added the option -vector-abi-compat=[default,gcc,xl]. The default behavior for
clang is for all vector compares to return a scalar unless the vectors being
compared are vector bool or vector pixel. In that case the compare returns a
vector. With the gcc case all vector compares return vectors and in the xl case
all vector compares return scalars.

This patch does not change the default behavior of clang.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103615

Files:
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-compat-pixel-bool-ternary.c
  clang/test/CodeGen/vector-compat-pixel-bool.c
  clang/test/CodeGen/vector-compat-ternary.c
  clang/test/CodeGen/vector-compat.c

Index: clang/test/CodeGen/vector-compat.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-compat.c
@@ -0,0 +1,160 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// Com: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// Com:   -vector-abi-compat=default -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -vector-abi-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// com: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// com:   -vector-abi-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+
+// CHECK-LABEL: @ui8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x

[PATCH] D94627: [PowerPC][PC Rel] Implement option to omit P10 instructions from stubs

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

I have a few comments. Most of them are nits but there is a functional issue as 
well.

For the testing:
Do we have a test for the `PPC64R2SaveStub` in the situation where the offset 
fits in 34 bits?




Comment at: lld/ELF/Driver.cpp:768
+  // This handles the --no-power10-stubs option.
+  bool NoP10 = args.hasArg(OPT_no_power10_stubs);
+

nit:
You can probably get rid of this temp and have the condition down below change 
to:
```
if (!args.hasArg(OPT_power10_stubs_eq) &&
args.hasArg(OPT_no_power10_stubs))
  return P10Stub::No;
```
Mainly because you only use `NoP10` in one place at this point.



Comment at: lld/ELF/Options.td:445
 
+def power10_stubs: F<"power10-stubs">, HelpText<"Alias for 
--power10-stubs=yes">;
+

nit:
This is not checked in `getP10StubOpt`.
This is no longer an alias for `power10-stubs=yes` it is an alias for default.



Comment at: lld/ELF/Thunks.cpp:932
+write32(buf + 4, addis); // addis r12, 0, top of offset
+write32(buf + 8, addi);  // addi  r12, r12, bottom of offset
+nextInstOffset = 12;

This sequence does not match with what you are using as an offset.
The `tocOffset` is the difference between the TOC pointer (in r2) and the 
address of the destination function (the callee). However, the add instructions 
are using that offset and adding it to zero (`addis r12, 0, top of offset`) 
which is not the TOC pointer. At the end of this sequence the register `r12` 
will not have the address of the callee but simply the difference between that 
address and the TOC pointer.

Since you have a valid `r2` and are computing the offset from the TOC pointer 
you should be adding to that.



Comment at: lld/ELF/Thunks.cpp:935
+  } else {
+write32(buf + 4, addi); // addi r12, 0, offset
+nextInstOffset = 8;

Same here as above.



Comment at: lld/ELF/Thunks.cpp:971
+uint32_t d = destination.getVA(addend);
+uint32_t off = d - getThunkTargetSym()->getVA();
+write32(buf + 0, 0x7c0802a6);  // mflr r12

nit:
The variable `d` is only used in one place so you can just inline it.
Also, for the future try to avoid single letter variable names.



Comment at: lld/ELF/Thunks.cpp:977
+write32(buf + 16, 0x3d8c | ha(off));   // addis r12,r11,off@ha
+write32(buf + 20, 0x398c | (uint16_t)(off)-8); // addi r12,r12,off@l
+nextInstOffset = 24;

You need to have the `off-8` in both cases. The way that this is done is quite 
confusing beause in one case you subtract 8 in the lambda and in the other you 
just subtract here inline. I would say just subtract in the computation of 
`off` and then you don't have to do it twice in two different places.

Secondly, instead of casting to `uint16_t` you are better off just using a mask 
(`off & 0x`).



Comment at: lld/ELF/Thunks.cpp:1010
+uint32_t d = destination.getVA(addend);
+uint32_t off = d - getThunkTargetSym()->getVA();
+write32(buf + 0, 0x7c0802a6);// mflr r12

nit:
Similar to above it is probably better to compute `off` with the `-8` included 
than to add the adjustment to the lambdas. 



Comment at: lld/ELF/Thunks.cpp:1057
+  if (config->Power10Stub == P10Stub::No) {
+auto ha = [](uint32_t v) -> uint16_t { return (v + 0x8000 - 8) >> 16; };
+uint32_t d = destination.getVA(addend);

I see that these lambdas are used in a lot of places to do the same thing. It 
might be better to have a static function instead of defining the same lambda 
three times.



Comment at: lld/ELF/Thunks.cpp:1059
+uint32_t d = destination.getVA(addend);
+uint32_t off = d - getThunkTargetSym()->getVA();
+write32(buf + 0, 0x7c0802a6);  // mflr r12

nit: Same as above. Just add compute the offset with the 8 difference here. 



Comment at: lld/test/ELF/ppc64-pcrel-call-to-toc.s:18
 
+# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s -o %t.o
+# RUN: ld.lld -T %t.script %t.o -o %t --no-power10-stubs

nit:
Do the LE version of the test instead of the BE version. 



Comment at: llvm/include/llvm/Object/ELF.h:94
+  LD_R12_NO_DISP = 0xE980,
+  LD_R12_TO_R12_NO_DISP = 0xE98C,
   MTCTR_R12 = 0x7D8903A6,

Are these two instruction masks used?


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[PATCH] D94627: [PowerPC][PC Rel] Implement option to omit P10 instructions from stubs

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

There is one more thing that does not look quite right. It may be an encoding 
problem for one of the instructions. I found it in the test but you will have 
to trace it back to the place where it is generated in order to fix it.




Comment at: lld/ELF/Driver.cpp:770
+
+  StringRef SelectedOpt = args.getLastArgValue(OPT_power10_stubs_eq);
+

MaskRay wrote:
> `value`
You may even be able to inline this since it is only used in one place that I 
can see.



Comment at: lld/ELF/Options.td:450
+def power10_stubs_eq:
+  J<"power10-stubs=">, HelpText<"Enables Power10 instsructions in all stubs 
without options, "
+ "options override previous flags."

nit:
Is this line too long? Or does it just appear too long in my browser. If the 
length is ok ignore my comment. 



Comment at: lld/ELF/Thunks.cpp:930
+uint64_t addi = ADDI_R12_TO_R12_NO_DISP | (tocOffset & 0x);
+const uint64_t addis = ADDIS_R12_TO_R2_NO_DISP | ((tocOffset >> 16) & 
0x);
+write32(buf + 4, addis); // addis r12, r2 , top of offset

nit:
You can mark both as const.
Also below in this same function.



Comment at: lld/test/ELF/ppc64-pcrel-call-to-toc.s:55
+# CHECK-NOP10-NEXT:  mtlr 12
+# CHECK-NOP10-NEXT:  addis 12, 12, -1
+# CHECK-NOP10-NEXT:  addi 12, 12, -24

This is not correct.
You should be adding to `r11` and not `r12` here.
ie.
```
addis 12, 11, -1
```
The encoding above may not be correct.


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[PATCH] D94627: [PowerPC][PC Rel] Implement option to omit Power10 instructions from stubs

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Just nits this time around.




Comment at: lld/ELF/Driver.cpp:765
+// instructions in stubs.
+static bool getP10StubOpt(opt::InputArgList &args) {
+

Conanap wrote:
> For this function here, I realize we can inline all the ifs into a giant 
> return statement - is there any opinions on this? I thought the if statements 
> might make this a bit more readable, but if it is preferred that there is 
> only 1 return statement I can make that change as well.
Personally I'm happy with it like this. I'm not a fan of huge if statements but 
I could be persuaded otherwise depending on what other reviewers have to say...



Comment at: lld/ELF/Options.td:451
+  J<"power10-stubs=">, HelpText<
+ "Enables Power10 instsructions in all stubs without 
options, "
+ "options override previous flags."

nit:
instsructions -> instructions 



Comment at: lld/ELF/Thunks.cpp:936
+const uint64_t addi = ADDI_R12_TO_R2_NO_DISP | (tocOffset & 0x);
+write32(buf + 4, addi); // addi r12, 2, offset
+nextInstOffset = 8;

nit:
addi r12, 2, offset -> addi r12, r2, offset



Comment at: lld/test/ELF/ppc64-pcrel-call-to-extern.s:110
+
+## .plt[2] - 0x10010010 = 0x10030158 - 0x10010010 = 0x20148 = 131416
 # CHECK-LABEL: <__plt_pcrel_callee_global_stother0>:

nit:
Same thing here. Please fix the comment.
`0x20148 = 131400` and not `131416`



Comment at: lld/test/ELF/ppc64-pcrel-call-to-extern.s:135
+
+## .plt[3] - 0x10020010 = 0x10030160 - 0x10020010 = 0x10150 = 65888
 # CHECK-LABEL: <__plt_pcrel_callee_global_stother1>:

nit:
Please fix these comments.
`0x10150` does not equal `65888`.



Comment at: lld/test/ELF/ppc64-pcrel-call-to-extern.s:160
+
+## .plt[4] - 0x10030010 = 0x10030168 - 0x10030010 = 0x150 = 360
 # CHECK-LABEL: <__plt_pcrel_callee_global_TOC>:

nit:
This comment too.
```
0x10030168 - 0x10030010 = 0x158
0x150 = 336
```
I'm not going to comment on all of these. Please take a look at the comments 
where numbers have changed and make sure that they are correct.



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[PATCH] D110653: [PowerPC] The builtins load8r and store8r are Power 7 plus.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: nemanjai, lei.
Herald added subscribers: shchenz, kbarton, hiraditya.
stefanp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added a subscriber: cfe-commits.

This patch makes sure that the builtins __builtin_ppc_load8r and
__ builtin_ppc_store8r are only available for Power 7 and up.
Currently the builtins seem to produce incorrect code if used for
Power 6 or before.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110653

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Driver/ppc-isa-features.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h

Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -147,6 +147,7 @@
   bool HasStoreFusion;
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
+  bool IsISA2_06;
   bool IsISA2_07;
   bool IsISA3_0;
   bool IsISA3_1;
@@ -322,6 +323,7 @@
 
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
+  bool isISA2_06() const { return IsISA2_06; }
   bool isISA2_07() const { return IsISA2_07; }
   bool isISA3_0() const { return IsISA3_0; }
   bool isISA3_1() const { return IsISA3_1; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -127,6 +127,7 @@
   HasStoreFusion = false;
   HasAddiLoadFusion = false;
   HasAddisLoadFusion = false;
+  IsISA2_06 = false;
   IsISA2_07 = false;
   IsISA3_0 = false;
   IsISA3_1 = false;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1182,6 +1182,7 @@
 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
 def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
 def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
+def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
 def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
 def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
 def HasFPU : Predicate<"Subtarget->hasFPU()">;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1302,9 +1302,12 @@
 def LDX  : XForm_1_memOp<31,  21, (outs g8rc:$rD), (ins memrr:$src),
 "ldx $rD, $src", IIC_LdStLD,
 [(set i64:$rD, (load XForm:$src))]>, isPPC64;
+
+let Predicates = [IsISA2_06] in {
 def LDBRX : XForm_1_memOp<31,  532, (outs g8rc:$rD), (ins memrr:$src),
   "ldbrx $rD, $src", IIC_LdStLoad,
   [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64;
+}
 
 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
 def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src),
@@ -1538,10 +1541,13 @@
   "stdx $rS, $dst", IIC_LdStSTD,
   [(store i64:$rS, XForm:$dst)]>, isPPC64,
   PPC970_DGroup_Cracked;
+
+let Predicates = [IsISA2_06] in {
 def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
   "stdbrx $rS, $dst", IIC_LdStStore,
   [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64,
   PPC970_DGroup_Cracked;
+}
 
 let mayStore = 1, hasNoSchedulingInfo = 1 in {
 // Normal 16-byte stores.
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -213,6 +213,9 @@
 def DeprecatedDST: SubtargetFeature<"", "DeprecatedDST", "true",
   "Treat vector data stream cache control instructions as deprecated">;
 
+def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
+  "true",
+  "Enable instructions in ISA 2.06.">;
 def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
   "true",
   "Enable instructions in ISA 2.07.">;
@@ -319,7 +322,8 @@
   FeatureMFTB,
   DeprecatedDST,
   FeatureTwoConstNR,
-  FeatureUnalig

[PATCH] D110653: [PowerPC] The builtins load8r and store8r are Power 7 plus.

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfb4e44c4e7da: [PowerPC] The builtins load8r and store8r are 
Power 7 plus. (authored by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Driver/ppc-isa-features.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h

Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -147,6 +147,7 @@
   bool HasStoreFusion;
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
+  bool IsISA2_06;
   bool IsISA2_07;
   bool IsISA3_0;
   bool IsISA3_1;
@@ -322,6 +323,7 @@
 
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
+  bool isISA2_06() const { return IsISA2_06; }
   bool isISA2_07() const { return IsISA2_07; }
   bool isISA3_0() const { return IsISA3_0; }
   bool isISA3_1() const { return IsISA3_1; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -127,6 +127,7 @@
   HasStoreFusion = false;
   HasAddiLoadFusion = false;
   HasAddisLoadFusion = false;
+  IsISA2_06 = false;
   IsISA2_07 = false;
   IsISA3_0 = false;
   IsISA3_1 = false;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1182,6 +1182,7 @@
 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
 def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
 def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
+def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
 def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
 def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
 def HasFPU : Predicate<"Subtarget->hasFPU()">;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1302,9 +1302,12 @@
 def LDX  : XForm_1_memOp<31,  21, (outs g8rc:$rD), (ins memrr:$src),
 "ldx $rD, $src", IIC_LdStLD,
 [(set i64:$rD, (load XForm:$src))]>, isPPC64;
+
+let Predicates = [IsISA2_06] in {
 def LDBRX : XForm_1_memOp<31,  532, (outs g8rc:$rD), (ins memrr:$src),
   "ldbrx $rD, $src", IIC_LdStLoad,
   [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64;
+}
 
 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
 def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src),
@@ -1538,10 +1541,13 @@
   "stdx $rS, $dst", IIC_LdStSTD,
   [(store i64:$rS, XForm:$dst)]>, isPPC64,
   PPC970_DGroup_Cracked;
+
+let Predicates = [IsISA2_06] in {
 def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
   "stdbrx $rS, $dst", IIC_LdStStore,
   [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64,
   PPC970_DGroup_Cracked;
+}
 
 let mayStore = 1, hasNoSchedulingInfo = 1 in {
 // Normal 16-byte stores.
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -213,6 +213,9 @@
 def DeprecatedDST: SubtargetFeature<"", "DeprecatedDST", "true",
   "Treat vector data stream cache control instructions as deprecated">;
 
+def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
+  "true",
+  "Enable instructions in ISA 2.06.">;
 def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
   "true",
   "Enable instructions in ISA 2.07.">;
@@ -319,7 +322,8 @@
   FeatureMFTB,
   DeprecatedDST,
   FeatureTwoConstNR,
-  FeatureUnalignedFloats];
+  FeatureUnalignedFloats,
+  Feature

[PATCH] D110771: [PowerPC] Fix __builtin_ppc_load2r to return short instead of int.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: lei, nemanjai.
Herald added subscribers: shchenz, kbarton, hiraditya.
stefanp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added a subscriber: cfe-commits.

This patch fixes the return value of the builtin __builtin_ppc_load2r to
correctly return short instead of int.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110771

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
@@ -52,12 +52,10 @@
 define dso_local zeroext i16 @test_builtin_ppc_load2r() {
 ; CHECK-64B-LABEL: test_builtin_ppc_load2r:
 ; CHECK-64B: lhbrx 3, 0, 3
-; CHECK-64B-NEXT:clrldi 3, 3, 48
 ; CHECK-64B-NEXT:blr
 
 ; CHECK-32B-LABEL: test_builtin_ppc_load2r:
 ; CHECK-32B: lhbrx 3, 0, 3
-; CHECK-32B-NEXT:clrlwi 3, 3, 16
 ; CHECK-32B-NEXT:blr
 entry:
   %0 = load i16*, i16** @us_addr, align 8
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15637,6 +15637,18 @@
   Known.Zero = ~1U;  // All bits but the low one are known to be zero.
   break;
 }
+break;
+  }
+  case ISD::INTRINSIC_W_CHAIN: {
+switch (cast(Op.getOperand(1))->getZExtValue()) {
+default:
+  break;
+case Intrinsic::ppc_load2r:
+  // Top bits are cleared for load2r (which is the same as lhbrx).
+  Known.Zero = 0x;
+  break;
+}
+break;
   }
   }
 }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1626,8 +1626,7 @@
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], 
[IntrNoMem]>;
   // load
   def int_ppc_load2r
-  : GCCBuiltin<"__builtin_ppc_load2r">,
-Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
+  : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
   def int_ppc_load4r
   : GCCBuiltin<"__builtin_ppc_load4r">,
 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
@@ -1,4 +1,4 @@
-// REQUIRES: powerpc-registered-target.
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15624,6 +15624,12 @@
 Value *Rotate = Builder.CreateCall(F, {Ops[0], Ops[0], ShiftAmt});
 return Builder.CreateAnd(Rotate, Ops[2]);
   }
+  case PPC::BI__builtin_ppc_load2r: {
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_load2r);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Value *LoadIntrinsic = Builder.CreateCall(F, Ops);
+return Builder.CreateTrunc(LoadIntrinsic, Int16Ty);
+  }
   // FMA variations
   case PPC::BI__builtin_vsx_xvmaddadp:
   case PPC::BI__builtin_vsx_xvmaddasp:
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -114,7 +114,7 @@
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load
-BUILTIN(__builtin_ppc_load2r, "UiUs*", "")
+BUILTIN(__builtin_ppc_load2r, "UsUs*", "")
 BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
 BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "")
 // store


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
@@ -52,12 +52,10 @@
 define dso_local zeroext i16 @test_builtin_ppc_load2r() {
 ; CHECK

[PATCH] D110771: [PowerPC] Fix __builtin_ppc_load2r to return short instead of int.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 376857.
stefanp added a comment.

Rebased and added signext test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110771/new/

https://reviews.llvm.org/D110771

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
@@ -52,12 +52,28 @@
 define dso_local zeroext i16 @test_builtin_ppc_load2r() {
 ; CHECK-64B-LABEL: test_builtin_ppc_load2r:
 ; CHECK-64B: lhbrx 3, 0, 3
-; CHECK-64B-NEXT:clrldi 3, 3, 48
 ; CHECK-64B-NEXT:blr
 
 ; CHECK-32B-LABEL: test_builtin_ppc_load2r:
 ; CHECK-32B: lhbrx 3, 0, 3
-; CHECK-32B-NEXT:clrlwi 3, 3, 16
+; CHECK-32B-NEXT:blr
+entry:
+  %0 = load i16*, i16** @us_addr, align 8
+  %1 = bitcast i16* %0 to i8*
+  %2 = call i32 @llvm.ppc.load2r(i8* %1)
+  %conv = trunc i32 %2 to i16
+  ret i16 %conv
+}
+
+define dso_local signext i16 @test_builtin_ppc_load2r_signext() {
+; CHECK-64B-LABEL: test_builtin_ppc_load2r_signext:
+; CHECK-64B: lhbrx 3, 0, 3
+; CHECK-64B-NEXT:extsh 3, 3
+; CHECK-64B-NEXT:blr
+
+; CHECK-32B-LABEL: test_builtin_ppc_load2r_signext:
+; CHECK-32B: lhbrx 3, 0, 3
+; CHECK-32B-NEXT:extsh 3, 3
 ; CHECK-32B-NEXT:blr
 entry:
   %0 = load i16*, i16** @us_addr, align 8
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15681,6 +15681,18 @@
   Known.Zero = ~1U;  // All bits but the low one are known to be zero.
   break;
 }
+break;
+  }
+  case ISD::INTRINSIC_W_CHAIN: {
+switch (cast(Op.getOperand(1))->getZExtValue()) {
+default:
+  break;
+case Intrinsic::ppc_load2r:
+  // Top bits are cleared for load2r (which is the same as lhbrx).
+  Known.Zero = 0x;
+  break;
+}
+break;
   }
   }
 }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1629,8 +1629,7 @@
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
   // load
   def int_ppc_load2r
-  : GCCBuiltin<"__builtin_ppc_load2r">,
-Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
+  : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
   def int_ppc_load4r
   : GCCBuiltin<"__builtin_ppc_load4r">,
 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
@@ -1,4 +1,4 @@
-// REQUIRES: powerpc-registered-target.
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15655,6 +15655,12 @@
 Value *Rotate = Builder.CreateCall(F, {Ops[0], Ops[0], ShiftAmt});
 return Builder.CreateAnd(Rotate, Ops[2]);
   }
+  case PPC::BI__builtin_ppc_load2r: {
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_load2r);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Value *LoadIntrinsic = Builder.CreateCall(F, Ops);
+return Builder.CreateTrunc(LoadIntrinsic, Int16Ty);
+  }
   // FMA variations
   case PPC::BI__builtin_vsx_xvmaddadp:
   case PPC::BI__builtin_vsx_xvmaddasp:
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -121,7 +121,7 @@
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load
-BUILTIN(__builtin_ppc_load2r, "UiUs*", "")
+BUILTIN(__builtin_ppc_load2r, "UsUs*", "")
 BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
 BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "")
 // store
___

[PATCH] D110771: [PowerPC] Fix __builtin_ppc_load2r to return short instead of int.

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4fc2f4979cf5: [PowerPC] Fix __builtin_ppc_load2r to return 
short instead of int. (authored by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110771/new/

https://reviews.llvm.org/D110771

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
@@ -52,12 +52,28 @@
 define dso_local zeroext i16 @test_builtin_ppc_load2r() {
 ; CHECK-64B-LABEL: test_builtin_ppc_load2r:
 ; CHECK-64B: lhbrx 3, 0, 3
-; CHECK-64B-NEXT:clrldi 3, 3, 48
 ; CHECK-64B-NEXT:blr
 
 ; CHECK-32B-LABEL: test_builtin_ppc_load2r:
 ; CHECK-32B: lhbrx 3, 0, 3
-; CHECK-32B-NEXT:clrlwi 3, 3, 16
+; CHECK-32B-NEXT:blr
+entry:
+  %0 = load i16*, i16** @us_addr, align 8
+  %1 = bitcast i16* %0 to i8*
+  %2 = call i32 @llvm.ppc.load2r(i8* %1)
+  %conv = trunc i32 %2 to i16
+  ret i16 %conv
+}
+
+define dso_local signext i16 @test_builtin_ppc_load2r_signext() {
+; CHECK-64B-LABEL: test_builtin_ppc_load2r_signext:
+; CHECK-64B: lhbrx 3, 0, 3
+; CHECK-64B-NEXT:extsh 3, 3
+; CHECK-64B-NEXT:blr
+
+; CHECK-32B-LABEL: test_builtin_ppc_load2r_signext:
+; CHECK-32B: lhbrx 3, 0, 3
+; CHECK-32B-NEXT:extsh 3, 3
 ; CHECK-32B-NEXT:blr
 entry:
   %0 = load i16*, i16** @us_addr, align 8
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15681,6 +15681,18 @@
   Known.Zero = ~1U;  // All bits but the low one are known to be zero.
   break;
 }
+break;
+  }
+  case ISD::INTRINSIC_W_CHAIN: {
+switch (cast(Op.getOperand(1))->getZExtValue()) {
+default:
+  break;
+case Intrinsic::ppc_load2r:
+  // Top bits are cleared for load2r (which is the same as lhbrx).
+  Known.Zero = 0x;
+  break;
+}
+break;
   }
   }
 }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1629,8 +1629,7 @@
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
   // load
   def int_ppc_load2r
-  : GCCBuiltin<"__builtin_ppc_load2r">,
-Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
+  : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
   def int_ppc_load4r
   : GCCBuiltin<"__builtin_ppc_load4r">,
 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
@@ -1,4 +1,4 @@
-// REQUIRES: powerpc-registered-target.
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15655,6 +15655,12 @@
 Value *Rotate = Builder.CreateCall(F, {Ops[0], Ops[0], ShiftAmt});
 return Builder.CreateAnd(Rotate, Ops[2]);
   }
+  case PPC::BI__builtin_ppc_load2r: {
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_load2r);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Value *LoadIntrinsic = Builder.CreateCall(F, Ops);
+return Builder.CreateTrunc(LoadIntrinsic, Int16Ty);
+  }
   // FMA variations
   case PPC::BI__builtin_vsx_xvmaddadp:
   case PPC::BI__builtin_vsx_xvmaddasp:
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -121,7 +121,7 @@
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load
-BUILTIN(__builtin_ppc_load2r, "UiUs*", "")
+BUILTIN(__builtin_ppc_load2r, "UsUs*", "")
 BUILTIN(__builtin_ppc_load4r, "UiUi*

[PATCH] D96512: [PowerPC] Add option for ROP Protection

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: lei, nemanjai.
Herald added subscribers: dang, shchenz, kbarton, hiraditya.
Herald added a reviewer: jansvoboda11.
stefanp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added a subscriber: cfe-commits.

Added -mrop-protection for Power PC to turn on codegen that provides some
protection from ROP attacks.

The option is off by default and can be turned on for Power 8, Power 9 and
Power 10.

This patch is for the option only. The feature will be implemented by a later
patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96512

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-mrop-protection-support-check.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/future-check-features.ll

Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
 
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -112,6 +112,7 @@
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasMMA;
+  bool HasROPProtection;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -273,6 +274,7 @@
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMMA() const { return HasMMA; }
+  bool hasROPProtection() const { return HasROPProtection; }
   bool pairedVectorMemops() const { return PairedVectorMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -87,6 +87,7 @@
   HasP9Vector = false;
   HasP9Altivec = false;
   HasMMA = false;
+  HasROPProtection = false;
   HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -252,6 +252,9 @@
   "Enable MMA instructions",
   [FeatureP8Vector, FeatureP9Altivec,
FeaturePairedVectorMemops]>;
+def FeatureROPProtection :
+  SubtargetFeature<"rop-protection", "HasROPProtection", "false",
+   "Add ROP protection">;
 
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -566,6 +566,7 @@
 // PPCPWR8-NOT:#define _ARCH_PWR6X 1
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
+// PPCPWR8-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -583,6 +584,7 @@
 // PPCPOWER8-NOT:#define _ARCH_PWR6X 1
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
+// PPCPOWER8-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -597,6 +599,7 @@
 // PPCPWR9-NOT:#define _ARCH_PWR6X 1
 // PPCPWR9:#define _ARCH_PWR7 1
 // PPCPWR9:#define _ARCH_PWR9 1
+// PPCPWR9-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER9 %s
 //
@@ -611,6 +614,7 @

[PATCH] D94627: [PowerPC][PC Rel] Implement option to omit Power10 instructions from stubs

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision as: stefanp.
stefanp added a comment.
This revision is now accepted and ready to land.

I just have one final nit otherwise LGTM. Feel free to fix that on commit.
Please wait a couple of days and see if @MaskRay has any further comments.




Comment at: lld/test/ELF/ppc64-pcrel-call-to-extern.s:135
+
+## .plt[3] - 0x10020010 = 0x10030160 - 0x10020010 = 0x10150 = 65888
 # CHECK-LABEL: <__plt_pcrel_callee_global_stother1>:

stefanp wrote:
> nit:
> Please fix these comments.
> `0x10150` does not equal `65888`.
nit:
I think these numbers are still wrong.
```
0x10030160 - 0x10020010 = 0x10150 not 0x10160
```
I think it should be: `0x10030170`


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[PATCH] D95458: [PowerPC] Exploit xxsplti32dx (constant materialization) for scalars

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp requested changes to this revision.
stefanp added inline comments.
This revision now requires changes to proceed.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:1321
   bool convertToNonDenormSingle(APFloat &ArgAPFloat);
+  bool checkNonDenormCannotConvertToSingle(APInt &ArgAPInt);
+  bool checkNonDenormCannotConvertToSingle(APFloat &ArgAPFloat);

Is the APInt version of this function used anywere?




Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:412
+  APFloat APFloatOfN = N->getValueAPF();
+  checkNonDenormCannotConvertToSingle(APFloatOfN);
+  uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() &

Why are we running this here?
We don't check the return of the function so we must assume that it returns 
true.
In that case the value of `APFloatOfN` won't change because 
`convertToNonDenormSingle` will only change the value of the parameter if it 
returns true. But `checkNonDenormCannotConvertToSingle` only returns true if 
`convertToNonDenormSingle` return false.



Comment at: llvm/test/CodeGen/PowerPC/constant-pool.ll:44
+; CHECK-NEXT:xxsplti32dx vs1, 0, 56623104
+; CHECK-NEXT:xxsplti32dx vs1, 1, -609716532
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1

I'm looking to understand this test case.
We are trying to materialize a special PowerPC long double (double-double). It 
seems that we have materialized one half of it and not the other half.

Is it because the first half is a denormal?
Why are we avoiding denormals anyway? It seems like we can completely specify a 
64 bit double with two `xxsplti32dx` instructions. 



Comment at: llvm/test/CodeGen/PowerPC/constant-pool.ll:363
+; CHECK-NEXT:stxv vs3, 32(r1) # 16-byte Folded Spill
+; CHECK-NEXT:xxsplti32dx vs3, 1, -343597384
+; CHECK-NEXT:# kill: def $f3 killed $f3 killed $vsl3

What is going on here?
It almost looks like we are spilling `vs3` half way through materializing a 
constant.


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[PATCH] D96512: [PowerPC] Add option for ROP Protection

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 324408.
stefanp added a comment.

Added missing FeatureROPProtection to P8AdditionalFeatures.

The P9  and P10  
features list will inherit from the P8  list.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96512/new/

https://reviews.llvm.org/D96512

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-mrop-protection-support-check.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/future-check-features.ll

Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
 
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -112,6 +112,7 @@
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasMMA;
+  bool HasROPProtection;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -273,6 +274,7 @@
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMMA() const { return HasMMA; }
+  bool hasROPProtection() const { return HasROPProtection; }
   bool pairedVectorMemops() const { return PairedVectorMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -87,6 +87,7 @@
   HasP9Vector = false;
   HasP9Altivec = false;
   HasMMA = false;
+  HasROPProtection = false;
   HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -252,6 +252,9 @@
   "Enable MMA instructions",
   [FeatureP8Vector, FeatureP9Altivec,
FeaturePairedVectorMemops]>;
+def FeatureROPProtection :
+  SubtargetFeature<"rop-protection", "HasROPProtection", "false",
+   "Add ROP protection">;
 
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
@@ -320,7 +323,8 @@
  FeatureDirectMove,
  FeatureICBT,
  FeaturePartwordAtomic,
- FeaturePredictableSelectIsExpensive
+ FeaturePredictableSelectIsExpensive,
+ FeatureROPProtection
 ];
 
   list P8SpecificFeatures = [FeatureAddiLoadFusion,
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -566,6 +566,7 @@
 // PPCPWR8-NOT:#define _ARCH_PWR6X 1
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
+// PPCPWR8-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -583,6 +584,7 @@
 // PPCPOWER8-NOT:#define _ARCH_PWR6X 1
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
+// PPCPOWER8-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -597,6 +599,7 @@
 // PPCPWR9-NOT:#define _ARCH_PWR6X 1
 // PPCPWR9:#define _ARCH_PWR7 1
 // PPCPWR9:#define _ARCH_PWR9 1
+// PPCPWR9-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -match-full-li

[PATCH] D96512: [PowerPC] Add option for ROP Protection

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb80357d46e22: [PowerPC] Add option for ROP Protection 
(authored by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96512/new/

https://reviews.llvm.org/D96512

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-mrop-protection-support-check.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/future-check-features.ll

Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
 
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -112,6 +112,7 @@
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasMMA;
+  bool HasROPProtection;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -273,6 +274,7 @@
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMMA() const { return HasMMA; }
+  bool hasROPProtection() const { return HasROPProtection; }
   bool pairedVectorMemops() const { return PairedVectorMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -87,6 +87,7 @@
   HasP9Vector = false;
   HasP9Altivec = false;
   HasMMA = false;
+  HasROPProtection = false;
   HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -252,6 +252,9 @@
   "Enable MMA instructions",
   [FeatureP8Vector, FeatureP9Altivec,
FeaturePairedVectorMemops]>;
+def FeatureROPProtection :
+  SubtargetFeature<"rop-protection", "HasROPProtection", "false",
+   "Add ROP protection">;
 
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
@@ -320,7 +323,8 @@
  FeatureDirectMove,
  FeatureICBT,
  FeaturePartwordAtomic,
- FeaturePredictableSelectIsExpensive
+ FeaturePredictableSelectIsExpensive,
+ FeatureROPProtection
 ];
 
   list P8SpecificFeatures = [FeatureAddiLoadFusion,
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -566,6 +566,7 @@
 // PPCPWR8-NOT:#define _ARCH_PWR6X 1
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
+// PPCPWR8-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -583,6 +584,7 @@
 // PPCPOWER8-NOT:#define _ARCH_PWR6X 1
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
+// PPCPOWER8-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -597,6 +599,7 @@
 // PPCPWR9-NOT:#define _ARCH_PWR6X 1
 // PPCPWR9:#define _ARCH_PWR7 1
 // PPCPWR9:#define _ARCH_PWR9 1
+// PPCPWR9-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER9 %s
 //
@@ -611,6 +614,7 @@
 // 

[PATCH] D103615: [Clang] Add option for vector compare compatibility.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

In D103615#2799498 , @bmahjour wrote:

> As far as I can see, there is no good reason for the special treatment of 
> vector bool/pixel going forward. Could we drop this special treatment, or at 
> least change the default to use scalar results across the board (consistent 
> with XL's behaviour and clang's current behaviour for most cases).

We can change this but I am hesitant to make the change immediately. I can 
leave the default behavior as-is for now and add a warning to say that this 
feature is going to be deprecated at a later date. After a couple of releases 
we can then change the default. I don't want to change defaults without giving 
users some kind of warning first.

As a result of this I'm going to change the name in the enum from `Default` to 
`Mixed` as it does not make sense to have it named Default if it's not going to 
be default in the long run.




Comment at: clang/include/clang/Driver/Options.td:3811
   MarshallingInfoFlag>;
+def vector_abi_compat : Joined<["-"], "vector-abi-compat=">, 
Flags<[CC1Option]>, Group,
+  HelpText<"Determines whether vector compare returns a vector or a scalar. 
Options: default, gcc, xl.">,

bmahjour wrote:
> I'm not sure the term "ABI" is really applicable. Maybe we should call it 
> "vector-compare-compat="
Sure. I can change the name to `vector-compare-compat`.



Comment at: clang/test/CodeGen/vector-compat-pixel-bool-ternary.c:6
+// RUN:   -vector-abi-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm 
%s -o - 2>&1| FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -vector-abi-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm 
%s -o - | FileCheck %s

bmahjour wrote:
> I only see the clang FE interface being tested. Does this have to be 
> specified through `-Xclang -vector-abi-compat=...` or is there a clang driver 
> option for it as well? I think we should have a clang driver option and have 
> at least one test for it.
This option works when it is passed immediately to clang.
I will add a couple of RUN lines to test this as well.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103615/new/

https://reviews.llvm.org/D103615

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[PATCH] D103615: [Clang] Add option for vector compare compatibility.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 351467.
stefanp added a comment.

Updated the name of the option to vector-compare compat.
Added clang test lines to the test cases.
Added deprecation warnings to the current default behaviour of vector bool and
vector pixel.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103615/new/

https://reviews.llvm.org/D103615

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-compat-pixel-bool-ternary.c
  clang/test/CodeGen/vector-compat-pixel-bool.c
  clang/test/CodeGen/vector-compat-ternary.c
  clang/test/CodeGen/vector-compat.c

Index: clang/test/CodeGen/vector-compat.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-compat.c
@@ -0,0 +1,162 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -vector-compare-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -vector-compare-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -vector-compare-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -vector-compare-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -vector-compare-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-N

[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: nemanjai, lei.
Herald added subscribers: shchenz, kbarton.
stefanp requested review of this revision.
Herald added a project: clang.

Added a number of different builtins that exist in the XL compiler. Most of
these builtins already exist in clang under a different name.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104386

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-abs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-alloca.c
  clang/test/CodeGen/builtins-ppc-xlcompat-bpermd.c
  clang/test/CodeGen/builtins-ppc-xlcompat-cipher.c
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc-xlcompat-div.c
  clang/test/CodeGen/builtins-ppc-xlcompat-expect.c
  clang/test/CodeGen/builtins-ppc-xlcompat-fma.c
  clang/test/CodeGen/builtins-ppc-xlcompat-memory.c
  clang/test/CodeGen/builtins-ppc-xlcompat-mode.c
  clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,175 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -D__ppc64__ \
+// RUN:-emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s --check-prefix=BE64
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -D__ppc64__ \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s --check-prefix=LE64
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:-emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s --check-prefix=BE32
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s --check-prefix=LE32
+
+// BE64-LABEL: @testrotatel4(
+// BE64-NEXT:  entry:
+// BE64-NEXT:[[RS_ADDR:%.*]] = alloca i32, align 4
+// BE64-NEXT:[[SHIFT_ADDR:%.*]] = alloca i32, align 4
+// BE64-NEXT:store i32 [[RS:%.*]], i32* [[RS_ADDR]], align 4
+// BE64-NEXT:store i32 [[SHIFT:%.*]], i32* [[SHIFT_ADDR]], align 4
+// BE64-NEXT:[[TMP0:%.*]] = load i32, i32* [[RS_ADDR]], align 4
+// BE64-NEXT:[[TMP1:%.*]] = load i32, i32* [[SHIFT_ADDR]], align 4
+// BE64-NEXT:[[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP0]], i32 [[TMP0]], i32 [[TMP1]])
+// BE64-NEXT:ret i32 [[TMP2]]
+//
+// LE64-LABEL: @testrotatel4(
+// LE64-NEXT:  entry:
+// LE64-NEXT:[[RS_ADDR:%.*]] = alloca i32, align 4
+// LE64-NEXT:[[SHIFT_ADDR:%.*]] = alloca i32, align 4
+// LE64-NEXT:store i32 [[RS:%.*]], i32* [[RS_ADDR]], align 4
+// LE64-NEXT:store i32 [[SHIFT:%.*]], i32* [[SHIFT_ADDR]], align 4
+// LE64-NEXT:[[TMP0:%.*]] = load i32, i32* [[RS_ADDR]], align 4
+// LE64-NEXT:[[TMP1:%.*]] = load i32, i32* [[SHIFT_ADDR]], align 4
+// LE64-NEXT:[[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP0]], i32 [[TMP0]], i32 [[TMP1]])
+// LE64-NEXT:ret i32 [[TMP2]]
+//
+// BE32-LABEL: @testrotatel4(
+// BE32-NEXT:  entry:
+// BE32-NEXT:[[RS_ADDR:%.*]] = alloca i32, align 4
+// BE32-NEXT:[[SHIFT_ADDR:%.*]] = alloca i32, align 4
+// BE32-NEXT:store i32 [[RS:%.*]], i32* [[RS_ADDR]], align 4
+// BE32-NEXT:store i32 [[SHIFT:%.*]], i32* [[SHIFT_ADDR]], align 4
+// BE32-NEXT:[[TMP0:%.*]] = load i32, i32* [[RS_ADDR]], align 4
+// BE32-NEXT:[[TMP1:%.*]] = load i32, i32* [[SHIFT_ADDR]], align 4
+// BE32-NEXT:[[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP0]], i32 [[TMP0]], i32 [[TMP1]])
+// BE32-NEXT:ret i32 [[TMP2]]
+//
+// LE32-LABEL: @testrotatel4(
+// LE32-NEXT:  entry:
+// LE32-NEXT:[[RS_ADDR:%.*]] = alloca i32, align 4
+// LE32-NEXT:[[SHIFT_ADDR:%.*]] = alloca i32, align 4
+// LE32-NEXT:store i32 [[RS:%.*]], i32* [[RS_ADDR]], align 4
+// LE32-NEXT:store i32 [[SHIFT:%.*]], i32* [[SHIFT_ADDR]], align 4
+// LE32-NEXT:[[TMP0:%.*]] = load i32, i32* [[RS_ADDR]], align 4
+// LE32-NEXT:[[TMP1:%.*]] = load i32, i32* [[SHIFT_ADDR]], align 4
+// LE32-NEXT:[[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP0]], i32 [[TMP0]], i32 [[TMP1]])
+// LE32-NEXT:ret i32 [[TMP2]]
+//
+unsigned int testrotatel4(unsigned int rs, unsigned int shift) {
+  return __rotatel4(rs, shift);
+}
+
+// BE64-LABEL: @testrotatel8(
+// BE64-NEXT:  entry:
+// BE64-NEXT:[[RS_ADDR:%.*]] = alloca i64, align 8
+// BE64-NEXT:[[SHIFT_ADDR:%.*]] = alloca i64, align 8
+// BE64-NEXT:store i64 [[RS:%.*]], i64* [[RS_ADDR]], align 8
+// BE64-NEXT:store i64 [[SHIFT:%.*]], i64* [[SHIFT_ADDR]], align 8
+// BE64-NEXT:[[TMP0:%.*]] = load i64, i64* [[RS_ADDR]], align 8
+// BE64-NEXT:[[TMP1:%.*]] = load i64, i64* [[SHIFT_ADDR]], align 8
+// BE64-NEXT:[[TMP2:%.*]] = call i64 @l

[PATCH] D103615: [Clang] Add option for vector compare compatibility.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 353126.
stefanp added a comment.

Moved if statement out of switch and added the Default=Mixed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103615/new/

https://reviews.llvm.org/D103615

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-compat-pixel-bool-ternary.c
  clang/test/CodeGen/vector-compat-pixel-bool.c
  clang/test/CodeGen/vector-compat-ternary.c
  clang/test/CodeGen/vector-compat.c

Index: clang/test/CodeGen/vector-compat.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-compat.c
@@ -0,0 +1,162 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -vector-compare-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -vector-compare-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -vector-compare-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -vector-compare-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -vector-compare-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+/

[PATCH] D107461: [PowerPC] Do not define __PRIVILEGED__

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: nemanjai, lei.
Herald added subscribers: shchenz, kbarton.
stefanp requested review of this revision.
Herald added a project: clang.

We do not want to define __PRIVILEGED__. There is no use case for the
definition and gcc does not define it. This patch removes that definition.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107461

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Driver/ppc-mprivileged-support-check.c
  clang/test/Preprocessor/init-ppc64.c

Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -565,7 +565,6 @@
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
 // PPCPWR8-NOT:#define __ROP_PROTECT__ 1
-// PPCPWR8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -584,7 +583,6 @@
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
 // PPCPOWER8-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -600,7 +598,6 @@
 // PPCPWR9:#define _ARCH_PWR7 1
 // PPCPWR9:#define _ARCH_PWR9 1
 // PPCPWR9-NOT:#define __ROP_PROTECT__ 1
-// PPCPWR9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER9 %s
 //
@@ -616,7 +613,6 @@
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 // PPCPOWER9-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
@@ -637,7 +633,6 @@
 // PPCPOWER10:#define __MMA__ 1
 // PPCPOWER10:#define __PCREL__ 1
 // PPCPOWER10-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER10-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
 //
@@ -658,7 +653,6 @@
 // PPCFUTURE:#define __MMA__ 1
 // PPCFUTURE:#define __PCREL__ 1
 // PPCFUTURE-NOT:#define __ROP_PROTECT__ 1
-// PPCFUTURE-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
 // PPC-MMA:#define __MMA__ 1
@@ -668,11 +662,6 @@
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +rop-protect -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-ROP %s
 // PPC-ROP:#define __ROP_PROTECT__ 1
 //
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// PPC-PRIV:#define __PRIVILEGED__ 1
-//
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
 // PPC-FLOAT128:#define __FLOAT128__ 1
 //
Index: clang/test/Driver/ppc-mprivileged-support-check.c
===
--- clang/test/Driver/ppc-mprivileged-support-check.c
+++ clang/test/Driver/ppc-mprivileged-support-check.c
@@ -1,26 +1,29 @@
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=pwr10 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=power10 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=pwr9 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=power9 -mprivileged %s 2>&1 | FileCheck %s

[PATCH] D107461: [PowerPC] Do not define __PRIVILEGED__

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 365278.
stefanp added a comment.

Revewiers had a good catch where I forgot to add an equals sign to check
in the test case. I've fixed that test now.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107461/new/

https://reviews.llvm.org/D107461

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Driver/ppc-mprivileged-support-check.c
  clang/test/Preprocessor/init-ppc64.c

Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -565,7 +565,6 @@
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
 // PPCPWR8-NOT:#define __ROP_PROTECT__ 1
-// PPCPWR8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -584,7 +583,6 @@
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
 // PPCPOWER8-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -600,7 +598,6 @@
 // PPCPWR9:#define _ARCH_PWR7 1
 // PPCPWR9:#define _ARCH_PWR9 1
 // PPCPWR9-NOT:#define __ROP_PROTECT__ 1
-// PPCPWR9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER9 %s
 //
@@ -616,7 +613,6 @@
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 // PPCPOWER9-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
@@ -637,7 +633,6 @@
 // PPCPOWER10:#define __MMA__ 1
 // PPCPOWER10:#define __PCREL__ 1
 // PPCPOWER10-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER10-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
 //
@@ -658,7 +653,6 @@
 // PPCFUTURE:#define __MMA__ 1
 // PPCFUTURE:#define __PCREL__ 1
 // PPCFUTURE-NOT:#define __ROP_PROTECT__ 1
-// PPCFUTURE-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
 // PPC-MMA:#define __MMA__ 1
@@ -668,11 +662,6 @@
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +rop-protect -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-ROP %s
 // PPC-ROP:#define __ROP_PROTECT__ 1
 //
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// PPC-PRIV:#define __PRIVILEGED__ 1
-//
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
 // PPC-FLOAT128:#define __FLOAT128__ 1
 //
Index: clang/test/Driver/ppc-mprivileged-support-check.c
===
--- clang/test/Driver/ppc-mprivileged-support-check.c
+++ clang/test/Driver/ppc-mprivileged-support-check.c
@@ -1,26 +1,29 @@
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=pwr10 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=power10 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=pwr9 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=power9 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-g

[PATCH] D107461: [PowerPC] Do not define __PRIVILEGED__

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa614a28772cb: [PowerPC] Do not define __PRIVILEGED__ 
(authored by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107461/new/

https://reviews.llvm.org/D107461

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Driver/ppc-mprivileged-support-check.c
  clang/test/Preprocessor/init-ppc64.c

Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -565,7 +565,6 @@
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
 // PPCPWR8-NOT:#define __ROP_PROTECT__ 1
-// PPCPWR8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -584,7 +583,6 @@
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
 // PPCPOWER8-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -600,7 +598,6 @@
 // PPCPWR9:#define _ARCH_PWR7 1
 // PPCPWR9:#define _ARCH_PWR9 1
 // PPCPWR9-NOT:#define __ROP_PROTECT__ 1
-// PPCPWR9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER9 %s
 //
@@ -616,7 +613,6 @@
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 // PPCPOWER9-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
@@ -637,7 +633,6 @@
 // PPCPOWER10:#define __MMA__ 1
 // PPCPOWER10:#define __PCREL__ 1
 // PPCPOWER10-NOT:#define __ROP_PROTECT__ 1
-// PPCPOWER10-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
 //
@@ -658,7 +653,6 @@
 // PPCFUTURE:#define __MMA__ 1
 // PPCFUTURE:#define __PCREL__ 1
 // PPCFUTURE-NOT:#define __ROP_PROTECT__ 1
-// PPCFUTURE-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
 // PPC-MMA:#define __MMA__ 1
@@ -668,11 +662,6 @@
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +rop-protect -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-ROP %s
 // PPC-ROP:#define __ROP_PROTECT__ 1
 //
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +privileged -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-PRIV %s
-// PPC-PRIV:#define __PRIVILEGED__ 1
-//
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
 // PPC-FLOAT128:#define __FLOAT128__ 1
 //
Index: clang/test/Driver/ppc-mprivileged-support-check.c
===
--- clang/test/Driver/ppc-mprivileged-support-check.c
+++ clang/test/Driver/ppc-mprivileged-support-check.c
@@ -1,26 +1,29 @@
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=pwr10 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=power10 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=pwr9 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
-// RUN:   -mcpu=power9 -mprivileged %s 2>&1 | FileCheck %s --check-prefix=HASPRIV
-// RUN: not %clang

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision.
stefanp added a comment.

Thank you for adding the `DiagGroup`.
LGTM.


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[PATCH] D103615: [Clang] Add option for vector compare compatibility.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 354422.
stefanp added a comment.

Updated the name of the option to cover all of the inconsistencies for vector
pixel/bool. Future patches will continue to use this option to define the
behaviour of these two types.

Reworded the warning message.
Added InGroup<> to the warning.
Set the default to Default.


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-compat-pixel-bool-ternary.c
  clang/test/CodeGen/vector-compat-pixel-bool.c
  clang/test/CodeGen/vector-compat-ternary.c
  clang/test/CodeGen/vector-compat.c

Index: clang/test/CodeGen/vector-compat.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-compat.c
@@ -0,0 +1,162 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[T

[PATCH] D103615: [Clang] Add option to handle behaviour of vector bool/vector pixel.

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc3fe847f9d90: [Clang] Add option to handle behaviour of 
vector bool/vector pixel. (authored by stefanp).

Repository:
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-compat-pixel-bool-ternary.c
  clang/test/CodeGen/vector-compat-pixel-bool.c
  clang/test/CodeGen/vector-compat-ternary.c
  clang/test/CodeGen/vector-compat.c

Index: clang/test/CodeGen/vector-compat.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-compat.c
@@ -0,0 +1,162 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:  

[PATCH] D103615: [Clang] Add option to handle behaviour of vector bool/vector pixel.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp reopened this revision.
stefanp added a comment.
This revision is now accepted and ready to land.

I'm sorry I missed the asserts requirement.
I will recommit this patch after I add `REQUIRES: asserts`.


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[PATCH] D103615: [Clang] Add option to handle behaviour of vector bool/vector pixel.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

In D103615#2847650 , @dblaikie wrote:

> In D103615#2847118 , @bmahjour 
> wrote:
>
>> In D103615#2847047 , @stefanp 
>> wrote:
>>
>>> I'm sorry I missed the asserts requirement.
>>> I will recommit this patch after I add `REQUIRES: asserts`.
>>
>> Instead of disabling the tests for non-assert builds, can we just remove the 
>> `entry:` checks at the beginning of each function? The rest of the IR checks 
>> should pass since they use a regexp so they should match for either named or 
>> unnamed instructions.
>
> (generally: disabling the test in non-asserts builds isn't the right path, 
> modifying the test so it doesn't depend on asserts IR naming is the right 
> path)
>
> Yes, probably removing the `entry:` check would be sufficient - give it a 
> test locally and see how it goes. (it does mean the "CHECK-NEXT" after that 
> (for the first instruction) would have to be a plain "CHECK" - so that the 
> test could pass both in the presence and absence of the entry label.

I've removed all of the `entry:` checks and changed for next line to `CHECK:` 
and that seems to be working with assertions off. I will recommit the patch 
like that if this is preferred.


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[PATCH] D103615: [Clang] Add option to handle behaviour of vector bool/vector pixel.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 355315.
stefanp added a comment.

Updated test cases to avoid failures on non assert builds.


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-compat-pixel-bool-ternary.c
  clang/test/CodeGen/vector-compat-pixel-bool.c
  clang/test/CodeGen/vector-compat-ternary.c
  clang/test/CodeGen/vector-compat.c

Index: clang/test/CodeGen/vector-compat.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-compat.c
@@ -0,0 +1,152 @@
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed short si16(vector signed short a, vector signed short b)

[PATCH] D103615: [Clang] Add option to handle behaviour of vector bool/vector pixel.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp updated this revision to Diff 355320.
stefanp added a comment.

Removed the lines that specified that checks were auto generated.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103615/new/

https://reviews.llvm.org/D103615

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-compat-pixel-bool-ternary.c
  clang/test/CodeGen/vector-compat-pixel-bool.c
  clang/test/CodeGen/vector-compat-ternary.c
  clang/test/CodeGen/vector-compat.c

Index: clang/test/CodeGen/vector-compat.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-compat.c
@@ -0,0 +1,152 @@
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed short si16(vector signed short a, vector signed s

[PATCH] D103615: [Clang] Add option to handle behaviour of vector bool/vector pixel.

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG90dfd059198e: [Clang] Add option to handle behaviour of 
vector bool/vector pixel. (authored by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103615/new/

https://reviews.llvm.org/D103615

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-compat-pixel-bool-ternary.c
  clang/test/CodeGen/vector-compat-pixel-bool.c
  clang/test/CodeGen/vector-compat-ternary.c
  clang/test/CodeGen/vector-compat.c

Index: clang/test/CodeGen/vector-compat.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-compat.c
@@ -0,0 +1,152 @@
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:[[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 

[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Overall I think this is fine. I just have a few nits.




Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:11
+int test_lwarx(volatile int* a) {
+  // CHECK: entry:
+  // CHECK: %0 = bitcast i32* %a to i8*

Please check that this "entry:" is printed out when asserts are on and when 
asserts are off you may want to remove it at this point.

I would prefer you check the name of the function instead of "entry". You can 
use `CHECK-LABEL` to do that. 



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-error.c:18
+}
+#endif

This entire test is for 32 bit Power PC. There is only one run line and that is 
what is specified.
Why are you checking the macros? 



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1529
+  def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
+  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,

nit:
Does this go past the 80 char limit?



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[PATCH] D105236: [PowerPC] Implement Load and Reserve and Store Conditional Builtins

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision.
stefanp added a comment.

Thank you!
LGTM.


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[PATCH] D95458: [PowerPC] Exploit xxsplti32dx (constant materialization) for scalars

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Comments relate to just cleaning up the patch a little.




Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8593
+  return !convertToNonDenormSingle(ArgAPFloat);
+}
+

I'm wondering if it would not be better to just inline this. It's just "not" of 
another call. That would simplify the patch a little.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15874
+  return convertToNonDenormSingle(APFloatOfImm) ||
+ checkNonDenormCannotConvertToSingle(APFloatOfImm);
 }

Isn't this just :
```
return convertToNonDenormSingle(APFloatOfImm) ||
   !convertToNonDenormSingle(APFloatOfImm);
```
Which is always true?

Basically the logic is that we can now materialize without a load any `f32` or 
any `f64`.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:1321
   bool convertToNonDenormSingle(APFloat &ArgAPFloat);
+  bool checkNonDenormCannotConvertToSingle(APInt &ArgAPInt);
+  bool checkNonDenormCannotConvertToSingle(APFloat &ArgAPFloat);

Conanap wrote:
> stefanp wrote:
> > Is the APInt version of this function used anywere?
> > 
> Hm I don't think so, although I implemented it for consistency with 
> `XXSPLTIDP` (`convertToNonDenormSingle`). I'll remove this if that is 
> preferred.
nit:
Ok, unless other reviewers disagree, just remove it.


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[PATCH] D95458: [PowerPC] Exploit xxsplti32dx (constant materialization) for scalars

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision.
stefanp added a comment.
This revision is now accepted and ready to land.

Thank you for adding this!
Other than one minor nit I think this LGTM.

Feel free to address nits on commits.




Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8834
+   &LosesInfo);
+  bool Success = (!LosesInfo && !APFloatToConvert.isDenormal());
+

nit:
You can just inline this. It is only used in one place.


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[PATCH] D98546: [PowerPC] Add __PCREL__ when PC Relative is enabled.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added a reviewer: nemanjai.
Herald added subscribers: shchenz, kbarton.
stefanp requested review of this revision.
Herald added a project: clang.

This patch adds the __PCREL__ define when PC Relative addressing is enabled.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98546

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Preprocessor/init-ppc64.c


Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -633,6 +633,7 @@
 // PPCPOWER10:#define _ARCH_PWR8 1
 // PPCPOWER10:#define _ARCH_PWR9 1
 // PPCPOWER10:#define __MMA__ 1
+// PPCPOWER10:#define __PCREL__ 1
 // PPCPOWER10-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none 
-target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines 
-check-prefix PPCFUTURE %s
@@ -652,6 +653,7 @@
 // PPCFUTURE:#define _ARCH_PWR9 1
 // PPCFUTURE:#define _ARCH_PWR_FUTURE 1
 // PPCFUTURE:#define __MMA__ 1
+// PPCFUTURE:#define __PCREL__ 1
 // PPCFUTURE-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none 
-target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | 
FileCheck -check-prefix PPC-MMA %s
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -199,6 +199,8 @@
 Builder.defineMacro("__ROP_PROTECTION__");
   if (HasP10Vector)
 Builder.defineMacro("__POWER10_VECTOR__");
+  if (HasPCRelativeMemops)
+Builder.defineMacro("__PCREL__");
 
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");


Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -633,6 +633,7 @@
 // PPCPOWER10:#define _ARCH_PWR8 1
 // PPCPOWER10:#define _ARCH_PWR9 1
 // PPCPOWER10:#define __MMA__ 1
+// PPCPOWER10:#define __PCREL__ 1
 // PPCPOWER10-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
@@ -652,6 +653,7 @@
 // PPCFUTURE:#define _ARCH_PWR9 1
 // PPCFUTURE:#define _ARCH_PWR_FUTURE 1
 // PPCFUTURE:#define __MMA__ 1
+// PPCFUTURE:#define __PCREL__ 1
 // PPCFUTURE-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -199,6 +199,8 @@
 Builder.defineMacro("__ROP_PROTECTION__");
   if (HasP10Vector)
 Builder.defineMacro("__POWER10_VECTOR__");
+  if (HasPCRelativeMemops)
+Builder.defineMacro("__PCREL__");
 
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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[PATCH] D98546: [PowerPC] Add __PCREL__ when PC Relative is enabled.

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG86f2a3d17878: [PowerPC] Add __PCREL__ when PC Relative is 
enabled. (authored by stefanp).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Preprocessor/init-ppc64.c


Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -633,6 +633,7 @@
 // PPCPOWER10:#define _ARCH_PWR8 1
 // PPCPOWER10:#define _ARCH_PWR9 1
 // PPCPOWER10:#define __MMA__ 1
+// PPCPOWER10:#define __PCREL__ 1
 // PPCPOWER10-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none 
-target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines 
-check-prefix PPCFUTURE %s
@@ -652,6 +653,7 @@
 // PPCFUTURE:#define _ARCH_PWR9 1
 // PPCFUTURE:#define _ARCH_PWR_FUTURE 1
 // PPCFUTURE:#define __MMA__ 1
+// PPCFUTURE:#define __PCREL__ 1
 // PPCFUTURE-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none 
-target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | 
FileCheck -check-prefix PPC-MMA %s
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -199,6 +199,8 @@
 Builder.defineMacro("__ROP_PROTECTION__");
   if (HasP10Vector)
 Builder.defineMacro("__POWER10_VECTOR__");
+  if (HasPCRelativeMemops)
+Builder.defineMacro("__PCREL__");
 
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");


Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -633,6 +633,7 @@
 // PPCPOWER10:#define _ARCH_PWR8 1
 // PPCPOWER10:#define _ARCH_PWR9 1
 // PPCPOWER10:#define __MMA__ 1
+// PPCPOWER10:#define __PCREL__ 1
 // PPCPOWER10-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
@@ -652,6 +653,7 @@
 // PPCFUTURE:#define _ARCH_PWR9 1
 // PPCFUTURE:#define _ARCH_PWR_FUTURE 1
 // PPCFUTURE:#define __MMA__ 1
+// PPCFUTURE:#define __PCREL__ 1
 // PPCFUTURE-NOT:#define __ROP_PROTECTION__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -199,6 +199,8 @@
 Builder.defineMacro("__ROP_PROTECTION__");
   if (HasP10Vector)
 Builder.defineMacro("__POWER10_VECTOR__");
+  if (HasPCRelativeMemops)
+Builder.defineMacro("__PCREL__");
 
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
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[PATCH] D135300: [PowerPC] Fix types for vcipher builtins.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: nemanjai, lei.
Herald added subscribers: shchenz, kbarton.
Herald added a project: All.
stefanp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

The documentation specifies that the parameters for the vcipher builtins are
vector unsigned char
The code used
vector unsigned long long

This patch fixes the types for the vcipher builtins.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135300

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
@@ -110,38 +110,38 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipher
-vector unsigned long long test_vcipher(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcipher
+vector unsigned char test_vcipher(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_altivec_crypto_vcipher(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipher
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipherlast
-vector unsigned long long test_vcipherlast(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcipherlast
+vector unsigned char test_vcipherlast(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_altivec_crypto_vcipherlast(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipherlast
 }
 
 // CHECK-LABEL: @test_vncipher
-vector unsigned long long test_vncipher(void)
+vector unsigned char test_vncipher(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_altivec_crypto_vncipher(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vncipher
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vncipherlast
-vector unsigned long long test_vncipherlast(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vncipherlast
+vector unsigned char test_vncipherlast(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_altivec_crypto_vncipherlast(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vncipherlast
 }
@@ -248,20 +248,20 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipher_e
-vector unsigned long long test_vcipher_e(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcipher_e
+vector unsigned char test_vcipher_e(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_crypto_vcipher(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipher
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipherlast_e
-vector unsigned long long test_vcipherlast_e(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcipherlast_e
+vector unsigned char test_vcipherlast_e(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_crypto_vcipherlast(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipherlast
 }
@@ -291,37 +291,37 @@
 }
 
 // CHECK-LABEL: @test_vec_cipher_be
-vector unsigned long long test_vec_cipher_be(void)
+vector unsigned char test_vec_cipher_be(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return vec_cipher_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipher
 }
 
 // CHECK-LABEL: @test_vec_cipherlast_be
-vector unsigned long long test_vec_cipherlast_be(void)
+vector unsigned char test_vec_cipherlast_be(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return vec_cipherlast_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipherlast
 }
 
 // CHECK-LABEL: @test_vec_ncipher_be
-vector unsigned long long test_vec_ncipher_be(void)
+vector unsigned char test_vec_ncipher_be(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return vec_ncipher_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vncipher
 }
 
 // CHECK-LABEL: @test_vec_ncipherlast_be
-vector unsigned long long test_vec_nciphe

[PATCH] D135300: [PowerPC] Fix types for vcipher builtins.

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0e2e1fc90a01: [PowerPC] Fix types for vcipher builtins. 
(authored by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135300/new/

https://reviews.llvm.org/D135300

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
@@ -110,38 +110,38 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipher
-vector unsigned long long test_vcipher(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcipher
+vector unsigned char test_vcipher(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_altivec_crypto_vcipher(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipher
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipherlast
-vector unsigned long long test_vcipherlast(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcipherlast
+vector unsigned char test_vcipherlast(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_altivec_crypto_vcipherlast(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipherlast
 }
 
 // CHECK-LABEL: @test_vncipher
-vector unsigned long long test_vncipher(void)
+vector unsigned char test_vncipher(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_altivec_crypto_vncipher(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vncipher
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vncipherlast
-vector unsigned long long test_vncipherlast(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vncipherlast
+vector unsigned char test_vncipherlast(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_altivec_crypto_vncipherlast(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vncipherlast
 }
@@ -248,20 +248,20 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipher_e
-vector unsigned long long test_vcipher_e(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcipher_e
+vector unsigned char test_vcipher_e(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_crypto_vcipher(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipher
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipherlast_e
-vector unsigned long long test_vcipherlast_e(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcipherlast_e
+vector unsigned char test_vcipherlast_e(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return __builtin_crypto_vcipherlast(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipherlast
 }
@@ -291,37 +291,37 @@
 }
 
 // CHECK-LABEL: @test_vec_cipher_be
-vector unsigned long long test_vec_cipher_be(void)
+vector unsigned char test_vec_cipher_be(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return vec_cipher_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipher
 }
 
 // CHECK-LABEL: @test_vec_cipherlast_be
-vector unsigned long long test_vec_cipherlast_be(void)
+vector unsigned char test_vec_cipherlast_be(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return vec_cipherlast_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipherlast
 }
 
 // CHECK-LABEL: @test_vec_ncipher_be
-vector unsigned long long test_vec_ncipher_be(void)
+vector unsigned char test_vec_ncipher_be(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  vector unsigned char a = B_INIT1
+  vector unsigned char b = B_INIT2
   return vec_ncipher_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vncipher
 }
 
 // CHECK-LABEL: @test_vec_ncipherlast_be
-vector unsigned long long test_vec_ncipherlast_be(void)
+vector unsigned char test_vec_ncipherlast_be(void)
 {
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
+  v

[PATCH] D135834: [PowerPC] Fix parameters for __builtin_crypto_vsbox

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added reviewers: lei, nemanjai.
Herald added subscribers: shchenz, kbarton.
Herald added a project: All.
stefanp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

The documentation specifies that the input and ouput for the builtin
__builtin_crypto_vsbox should be vector unsigned char.

This patch fixes this type for the builtin.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135834

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c


Index: clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
@@ -60,10 +60,10 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsbox
-vector unsigned long long test_vsbox(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsbox
+vector unsigned char test_vsbox(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return __builtin_altivec_crypto_vsbox(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
@@ -200,10 +200,10 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsbox_e
-vector unsigned long long test_vsbox_e(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsbox_e
+vector unsigned char test_vsbox_e(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return __builtin_crypto_vsbox(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
@@ -283,9 +283,9 @@
 }
 
 // CHECK-LABEL: @test_vec_sbox_be
-vector unsigned long long test_vec_sbox_be(void)
+vector unsigned char test_vec_sbox_be(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return vec_sbox_be(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -17323,8 +17323,8 @@
 #define vec_ncipherlast_be __builtin_altivec_crypto_vncipherlast
 
 #ifdef __VSX__
-static __inline__ vector unsigned long long __attribute__((__always_inline__))
-__builtin_crypto_vsbox(vector unsigned long long __a) {
+static __inline__ vector unsigned char __attribute__((__always_inline__))
+__builtin_crypto_vsbox(vector unsigned char __a) {
   return __builtin_altivec_crypto_vsbox(__a);
 }
 
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -418,7 +418,7 @@
 BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "")
 
 // P8 Crypto built-ins.
-BUILTIN(__builtin_altivec_crypto_vsbox, "V2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc", "")
 BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "")


Index: clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
@@ -60,10 +60,10 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsbox
-vector unsigned long long test_vsbox(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsbox
+vector unsigned char test_vsbox(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return __builtin_altivec_crypto_vsbox(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
@@ -200,10 +200,10 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsbox_e
-vector unsigned long long test_vsbox_e(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsbox_e
+vector unsigned char test_vsbox_e(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return __builtin_crypto_vsbox(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
@@ -283,9 +283,9 @@
 }
 
 // CHECK-LABEL: @test_vec_sbox_be
-vector unsigned long long test_vec_sbox_be(void)
+vector unsigned char test_vec_sbox_be(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return vec_sbox_be(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -17323,8 +17323,8 @@
 #define vec_ncipherlast_be __builtin_altivec_crypto_vncipherlast
 
 #ifdef __VSX__
-static __inline__ vector unsigned long long __attribute__((__al

[PATCH] D135834: [PowerPC] Fix parameters for __builtin_crypto_vsbox

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6897dbc46329: [PowerPC] Fix parameters for 
__builtin_crypto_vsbox (authored by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135834/new/

https://reviews.llvm.org/D135834

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c


Index: clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
@@ -60,10 +60,10 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsbox
-vector unsigned long long test_vsbox(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsbox
+vector unsigned char test_vsbox(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return __builtin_altivec_crypto_vsbox(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
@@ -200,10 +200,10 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsbox_e
-vector unsigned long long test_vsbox_e(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsbox_e
+vector unsigned char test_vsbox_e(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return __builtin_crypto_vsbox(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
@@ -283,9 +283,9 @@
 }
 
 // CHECK-LABEL: @test_vec_sbox_be
-vector unsigned long long test_vec_sbox_be(void)
+vector unsigned char test_vec_sbox_be(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return vec_sbox_be(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -17323,8 +17323,8 @@
 #define vec_ncipherlast_be __builtin_altivec_crypto_vncipherlast
 
 #ifdef __VSX__
-static __inline__ vector unsigned long long __attribute__((__always_inline__))
-__builtin_crypto_vsbox(vector unsigned long long __a) {
+static __inline__ vector unsigned char __attribute__((__always_inline__))
+__builtin_crypto_vsbox(vector unsigned char __a) {
   return __builtin_altivec_crypto_vsbox(__a);
 }
 
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -418,7 +418,7 @@
 BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "")
 
 // P8 Crypto built-ins.
-BUILTIN(__builtin_altivec_crypto_vsbox, "V2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc", "")
 BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "")


Index: clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
@@ -60,10 +60,10 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsbox
-vector unsigned long long test_vsbox(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsbox
+vector unsigned char test_vsbox(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return __builtin_altivec_crypto_vsbox(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
@@ -200,10 +200,10 @@
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsbox_e
-vector unsigned long long test_vsbox_e(void)
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsbox_e
+vector unsigned char test_vsbox_e(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return __builtin_crypto_vsbox(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
@@ -283,9 +283,9 @@
 }
 
 // CHECK-LABEL: @test_vec_sbox_be
-vector unsigned long long test_vec_sbox_be(void)
+vector unsigned char test_vec_sbox_be(void)
 {
-  vector unsigned long long a = D_INIT1
+  vector unsigned char a = B_INIT1
   return vec_sbox_be(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -17323,8 +17323,8 @@
 #define vec_ncipherlast_be __builtin_altivec_crypto_vncipherlast
 
 #ifdef __VSX__
-static __inline__ vector unsigned long long __attribute__((__always_inline__))
-__builtin_crypto_vsbox(vector unsigned long long __a) {
+static __inline__ vector unsigned char __attribute__((__always_inline__))
+__builtin_crypto_vsbox(vector 

[PATCH] D155544: [AIX][TLS] Add -maix-small-local-exec-tls option.

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision as: stefanp.
stefanp added a comment.
This revision is now accepted and ready to land.

I think this patch makes sense to me.
LGTM.




Comment at: llvm/test/CodeGen/PowerPC/check-aix-small-local-exec-tls-opt.ll:15
+
+; Make sure that the test was actually compiled successfully after using the
+; -maix-small-local-exec-tls option.

DiggerLin wrote:
> since the patch only add a new option "aix-small-local-exec-tls" , the the 
> backend implementation for this option in not in the patch, the behavior  of 
> the CodeGen do not change in the patch, I do not think we need the test case. 
I would actually prefer to have a test case here. We do need to check to make 
sure that the backend produces the correct error on Linux and produces valid 
codegen on AIX. 


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[PATCH] D70262: [PowerPC] Add new Future CPU for PowerPC

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5fcf89f77893: [PowerPC] Add new Future CPU for PowerPC 
(authored by stefanp).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D70262

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init.c

Index: clang/test/Preprocessor/init.c
===
--- clang/test/Preprocessor/init.c
+++ clang/test/Preprocessor/init.c
@@ -6452,6 +6452,22 @@
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 //
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
+//
+// PPCFUTURE:#define _ARCH_PPC 1
+// PPCFUTURE:#define _ARCH_PPC64 1
+// PPCFUTURE:#define _ARCH_PPCGR 1
+// PPCFUTURE:#define _ARCH_PPCSQ 1
+// PPCFUTURE:#define _ARCH_PWR4 1
+// PPCFUTURE:#define _ARCH_PWR5 1
+// PPCFUTURE:#define _ARCH_PWR5X 1
+// PPCFUTURE:#define _ARCH_PWR6 1
+// PPCFUTURE-NOT:#define _ARCH_PWR6X 1
+// PPCFUTURE:#define _ARCH_PWR7 1
+// PPCFUTURE:#define _ARCH_PWR8 1
+// PPCFUTURE:#define _ARCH_PWR9 1
+// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
+//
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
 // PPC-FLOAT128:#define __FLOAT128__ 1
 //
Index: clang/test/Misc/target-invalid-cpu-note.c
===
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -82,7 +82,7 @@
 // PPC-SAME: 8548, 970, g5, a2, a2q, e500, e500mc, e5500, power3, pwr3, power4,
 // PPC-SAME: pwr4, power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x,
 // PPC-SAME: power7, pwr7, power8, pwr8, power9, pwr9, powerpc, ppc, powerpc64,
-// PPC-SAME: ppc64, powerpc64le, ppc64le
+// PPC-SAME: ppc64, powerpc64le, ppc64le, future
 
 // RUN: not %clang_cc1 -triple mips--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix MIPS
 // MIPS: error: unknown target CPU 'not-a-cpu'
Index: clang/lib/Driver/ToolChains/Arch/PPC.cpp
===
--- clang/lib/Driver/ToolChains/Arch/PPC.cpp
+++ clang/lib/Driver/ToolChains/Arch/PPC.cpp
@@ -70,6 +70,7 @@
 .Case("power7", "pwr7")
 .Case("power8", "pwr8")
 .Case("power9", "pwr9")
+.Case("future", "future")
 .Case("pwr3", "pwr3")
 .Case("pwr4", "pwr4")
 .Case("pwr5", "pwr5")
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -43,9 +43,10 @@
 ArchDefinePwr7 = 1 << 11,
 ArchDefinePwr8 = 1 << 12,
 ArchDefinePwr9 = 1 << 13,
-ArchDefineA2 = 1 << 14,
-ArchDefineA2q = 1 << 15,
-ArchDefineE500 = 1 << 16
+ArchDefineFuture = 1 << 14,
+ArchDefineA2 = 1 << 15,
+ArchDefineA2q = 1 << 16,
+ArchDefineE500 = 1 << 17
   } ArchDefineTypes;
 
 
@@ -146,6 +147,11 @@
  ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+  .Case("future",
+ArchDefineFuture | ArchDefinePwr9 | ArchDefinePwr8 |
+ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
+ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
+ArchDefinePpcsq)
   .Cases("8548", "e500", ArchDefineE500)
   .Default(ArchDefineNone);
 }
@@ -166,6 +172,8 @@
  StringRef CPU,
  const std::vector &FeaturesVec) const override;
 
+  void addFutureSpecificFeatures(llvm::StringMap &Features) const;
+
   bool handleTargetFeatures(std::vector &Features,
 DiagnosticsEngine &Diags) override;
 
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -159,6 +159,8 @@
   }
   if (ArchDefs & ArchDefineE500)
 Builder.defineMacro("__NO_LWSYNC__");
+  if (ArchDefs & ArchDefineFuture)
+Builder.defineMacro("_ARCH_PWR_FUTURE");
 
   if (getTriple().getVendor() == llvm::Triple::BGQ) {
 Builder.defineMacro("__bg__");
@@ -319,6 +321,13 @@
 .Case("e500", true)
 .Default(false);
 
+  // Future CPU should include all 

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Overall I think that this looks fine to me as well.
I had a couple of minor comments and you may decide that you don't need to do 
either one so if that's the case just mention why in a comment and I will 
approve the patch.




Comment at: clang/include/clang/Basic/BuiltinsPPC.def:987
+
+UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*", false, "mma")
+UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false, "mma")

Based on the original implementation in `SemaBuiltinPPCMMACall` all of the 
`mma` builtins also require `paired-vector-memops`. 
Is this something that we still need?



Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c:47
 
-int test_test_data_class_f() {
-// CHECK-LABEL:   @test_test_data_class_f
-// CHECK: [[TMP:%.*]] = call i32 
@llvm.ppc.test.data.class.f32(float %0, i32 127)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __test_data_class(f, 127);
+// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_uo' needs target feature 
isa-v30-instructions,vsx
+// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_lt' needs target feature 
isa-v30-instructions,vsx

nit:
Should this be 
```
... needs target feature vsx
```
Instead of listing them both?

Fixing this might be more trouble than it's worth because you would have to 
edit `CodeGenFunction::checkTargetFeatures`. I just thought I would mention it.


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[PATCH] D140104: [clang][dataflow] Remove unused argument in getNullability

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added inline comments.



Comment at: clang/lib/Sema/SemaExpr.cpp:9072
 
   auto GetNullability = [&Ctx](QualType Ty) {
+Optional Kind = Ty->getNullability();

merrymeerkat wrote:
> barannikov88 wrote:
> > This now gives a warning
> > `clang/lib/Sema/SemaExpr.cpp:9072:27: warning: lambda capture 'Ctx' is not 
> > used [-Wunused-lambda-capture]`
> Thank you for pointing this out! This patch should resolve this: 
> https://reviews.llvm.org/D140211
Thank you for addressing this as it is breaking one of our bots:

https://lab.llvm.org/buildbot/#/builders/36/builds/28473


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[PATCH] D99185: [PowerPC] Change option to mrop-protect

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added a reviewer: nemanjai.
Herald added subscribers: jansvoboda11, dang, shchenz, kbarton, hiraditya.
stefanp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added a subscriber: cfe-commits.

In order to have the same option on power PC LLVM and power PC gcc
the option will be changed from -mrop-protection to -mrop-protect.

The feature will be off by default and turned on when the option is used.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99185

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-mrop-protection-support-check.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/future-check-features.ll

Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
 
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -112,7 +112,7 @@
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasMMA;
-  bool HasROPProtection;
+  bool HasROPProtect;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -274,7 +274,7 @@
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMMA() const { return HasMMA; }
-  bool hasROPProtection() const { return HasROPProtection; }
+  bool hasROPProtect() const { return HasROPProtect; }
   bool pairedVectorMemops() const { return PairedVectorMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -87,7 +87,7 @@
   HasP9Vector = false;
   HasP9Altivec = false;
   HasMMA = false;
-  HasROPProtection = false;
+  HasROPProtect = false;
   HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -252,9 +252,9 @@
   "Enable MMA instructions",
   [FeatureP8Vector, FeatureP9Altivec,
FeaturePairedVectorMemops]>;
-def FeatureROPProtection :
-  SubtargetFeature<"rop-protection", "HasROPProtection", "false",
-   "Add ROP protection">;
+def FeatureROPProtect :
+  SubtargetFeature<"rop-protect", "HasROPProtect", "true",
+   "Add ROP protect">;
 
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
@@ -323,8 +323,7 @@
  FeatureDirectMove,
  FeatureICBT,
  FeaturePartwordAtomic,
- FeaturePredictableSelectIsExpensive,
- FeatureROPProtection
+ FeaturePredictableSelectIsExpensive
 ];
 
   list P8SpecificFeatures = [FeatureAddiLoadFusion,
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -566,7 +566,7 @@
 // PPCPWR8-NOT:#define _ARCH_PWR6X 1
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
-// PPCPWR8-NOT:#define __ROP_PROTECTION__ 1
+// PPCPWR8-NOT:#define __ROP_PROTECT__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -584,7 +584,7 @@
 // PPCPOWER8-NOT:#define _ARCH_PWR6X 1
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
-// PPCPOWER8-NOT:#define __ROP_PROTECTION__ 1
+// PPCPOWER8-NOT:#define __ROP_PROTECT__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffre

[PATCH] D99193: [PowerPC] Add mprivileged option

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp created this revision.
stefanp added a reviewer: nemanjai.
Herald added subscribers: jansvoboda11, dang, shchenz, kbarton, hiraditya.
stefanp requested review of this revision.
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Add an option to tell the compiler that it can use privileged instructions.

This patch only adds the option. Backend implementation will be added in a
future patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99193

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-mprivileged-support-check.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/future-check-features.ll

Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
 
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -113,6 +113,7 @@
   bool HasPCRelativeMemops;
   bool HasMMA;
   bool HasROPProtect;
+  bool HasPrivileged;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -275,6 +276,7 @@
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMMA() const { return HasMMA; }
   bool hasROPProtect() const { return HasROPProtect; }
+  bool hasPrivileged() const { return HasPrivileged; }
   bool pairedVectorMemops() const { return PairedVectorMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -88,6 +88,7 @@
   HasP9Altivec = false;
   HasMMA = false;
   HasROPProtect = false;
+  HasPrivileged = false;
   HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -256,6 +256,10 @@
   SubtargetFeature<"rop-protect", "HasROPProtect", "true",
"Add ROP protect">;
 
+def FeaturePrivileged :
+  SubtargetFeature<"privileged", "HasPrivileged", "true",
+   "Add privileged instructions">;
+
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
"PredictableSelectIsExpensive",
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -567,6 +567,7 @@
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
 // PPCPWR8-NOT:#define __ROP_PROTECT__ 1
+// PPCPWR8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -585,6 +586,7 @@
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
 // PPCPOWER8-NOT:#define __ROP_PROTECT__ 1
+// PPCPOWER8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -600,6 +602,7 @@
 // PPCPWR9:#define _ARCH_PWR7 1
 // PPCPWR9:#define _ARCH_PWR9 1
 // PPCPWR9-NOT:#define __ROP_PROTECT__ 1
+// PPCPWR9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER9 %s
 //
@@ -615,6 +618,7 @@
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 // PPCPOWER9-NOT:#define __ROP_PROTECT__ 1
+// PPCPOWER9-NOT:#define __PRIVILEGED__ 1
 //

[PATCH] D99185: [PowerPC] Change option to mrop-protect

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG0e4f5f3ea6e1: [PowerPC] Change option to mrop-protect 
(authored by stefanp).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-mrop-protection-support-check.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/future-check-features.ll

Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protection \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
 
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -112,7 +112,7 @@
   bool HasPrefixInstrs;
   bool HasPCRelativeMemops;
   bool HasMMA;
-  bool HasROPProtection;
+  bool HasROPProtect;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -274,7 +274,7 @@
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMMA() const { return HasMMA; }
-  bool hasROPProtection() const { return HasROPProtection; }
+  bool hasROPProtect() const { return HasROPProtect; }
   bool pairedVectorMemops() const { return PairedVectorMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -87,7 +87,7 @@
   HasP9Vector = false;
   HasP9Altivec = false;
   HasMMA = false;
-  HasROPProtection = false;
+  HasROPProtect = false;
   HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -252,9 +252,9 @@
   "Enable MMA instructions",
   [FeatureP8Vector, FeatureP9Altivec,
FeaturePairedVectorMemops]>;
-def FeatureROPProtection :
-  SubtargetFeature<"rop-protection", "HasROPProtection", "false",
-   "Add ROP protection">;
+def FeatureROPProtect :
+  SubtargetFeature<"rop-protect", "HasROPProtect", "true",
+   "Add ROP protect">;
 
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
@@ -323,8 +323,7 @@
  FeatureDirectMove,
  FeatureICBT,
  FeaturePartwordAtomic,
- FeaturePredictableSelectIsExpensive,
- FeatureROPProtection
+ FeaturePredictableSelectIsExpensive
 ];
 
   list P8SpecificFeatures = [FeatureAddiLoadFusion,
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -566,7 +566,7 @@
 // PPCPWR8-NOT:#define _ARCH_PWR6X 1
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
-// PPCPWR8-NOT:#define __ROP_PROTECTION__ 1
+// PPCPWR8-NOT:#define __ROP_PROTECT__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -584,7 +584,7 @@
 // PPCPOWER8-NOT:#define _ARCH_PWR6X 1
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
-// PPCPOWER8-NOT:#define __ROP_PROTECTION__ 1
+// PPCPOWER8-NOT:#define __ROP_PROTECT__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -599,7 +599,7 @@
 // PPCPWR9-NOT:#define _ARCH_PWR6X 1
 // PPCPWR9:#define _ARCH_PWR7 1
 

[PATCH] D99193: [PowerPC] Add mprivileged option

[Stefan Pintilie via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG91f4c1113350: [PowerPC] Add mprivileged option (authored by 
stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99193/new/

https://reviews.llvm.org/D99193

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-mprivileged-support-check.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/future-check-features.ll

Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
 ; RUN:   -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
 
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -113,6 +113,7 @@
   bool HasPCRelativeMemops;
   bool HasMMA;
   bool HasROPProtect;
+  bool HasPrivileged;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -275,6 +276,7 @@
   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMMA() const { return HasMMA; }
   bool hasROPProtect() const { return HasROPProtect; }
+  bool hasPrivileged() const { return HasPrivileged; }
   bool pairedVectorMemops() const { return PairedVectorMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -88,6 +88,7 @@
   HasP9Altivec = false;
   HasMMA = false;
   HasROPProtect = false;
+  HasPrivileged = false;
   HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -256,6 +256,10 @@
   SubtargetFeature<"rop-protect", "HasROPProtect", "true",
"Add ROP protect">;
 
+def FeaturePrivileged :
+  SubtargetFeature<"privileged", "HasPrivileged", "true",
+   "Add privileged instructions">;
+
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
"PredictableSelectIsExpensive",
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -567,6 +567,7 @@
 // PPCPWR8:#define _ARCH_PWR7 1
 // PPCPWR8:#define _ARCH_PWR8 1
 // PPCPWR8-NOT:#define __ROP_PROTECT__ 1
+// PPCPWR8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER8 %s
 //
@@ -585,6 +586,7 @@
 // PPCPOWER8:#define _ARCH_PWR7 1
 // PPCPOWER8:#define _ARCH_PWR8 1
 // PPCPOWER8-NOT:#define __ROP_PROTECT__ 1
+// PPCPOWER8-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPWR9 %s
 //
@@ -600,6 +602,7 @@
 // PPCPWR9:#define _ARCH_PWR7 1
 // PPCPWR9:#define _ARCH_PWR9 1
 // PPCPWR9-NOT:#define __ROP_PROTECT__ 1
+// PPCPWR9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER9 %s
 //
@@ -615,6 +618,7 @@
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 // PPCPOWER9-NOT:#define __ROP_PROTECT__ 1
+// PPCPOWER9-NOT:#define __PRIVILEGED__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr10 -fno-signed-char < /dev/null | FileCheck -match-full-li