from:"Piyou Chen via Phabricator via cfe\-commits"

[PATCH] D151730: [RISCV] Support target attribute for function

2023-11-19 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added a comment.

ping


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[PATCH] D151730: [RISCV] Support target attribute for function

2023-11-20 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 558134.
BeMg added a comment.

1. reuse the find result
2. replace for loop with llvm::copy_if
3. use explicit std::vector declaration instead of auto


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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,46 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m \
+// RUN:  -target-feature +a -target-feature +save-restore \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @testDefault
+// CHECK-SAME: () #0 {
+void testDefault() {}
+// CHECK-LABEL: define dso_local void @testMultiAttrStr
+// CHECK-SAME: () #1 {
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void
+testMultiAttrStr() {}
+// CHECK-LABEL: define dso_local void @testSingleExtension
+// CHECK-SAME: () #2 {
+__attribute__((target("arch=+zbb"))) void testSingleExtension() {}
+// CHECK-LABEL: define dso_local void @testMultiExtension
+// CHECK-SAME: () #3 {
+__attribute__((target("arch=+zbb,+v,+zicond"))) void testMultiExtension() {}
+// CHECK-LABEL: define dso_local void @testFullArch
+// CHECK-SAME: () #4 {
+__attribute__((target("arch=rv64gc_zbb"))) void testFullArch() {}
+// CHECK-LABEL: define dso_local void @testFullArchButSmallThanCmdArch
+// CHECK-SAME: () #5 {
+__attribute__((target("arch=rv64im"))) void testFullArchButSmallThanCmdArch() {}
+// CHECK-LABEL: define dso_local void @testAttrArchAndAttrCpu
+// CHECK-SAME: () #6 {
+__attribute__((target("cpu=sifive-u54;arch=+zbb"))) void
+testAttrArchAndAttrCpu() {}
+// CHECK-LABEL: define dso_local void @testAttrFullArchAndAttrCpu
+// CHECK-SAME: () #7 {
+__attribute__((target("cpu=sifive-u54;arch=rv64im"))) void
+testAttrFullArchAndAttrCpu() {}
+// CHECK-LABEL: define dso_local void @testAttrCpuOnly
+// CHECK-SAME: () #8 {
+__attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
+
+//.
+// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei" }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" "tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei" }
+// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei" }
+// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore" }
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei" }
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei" }
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
@@ -0,0 +1,10 @@
+// REQUIRES: riscv-registered-target
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m -target-feature +a \
+// RUN:  -emit-llvm %s 2>&1 | FileCheck %s
+
+// CHECK: error: duplicate 'arch=' in the 'target' attribute string;
+__attribute__((target("arch=rv64gc;arch=rv64gc_zbb"))) void testMultiArchSelectLast() {}
+// CHECK: error: duplicate 'cpu=' in the 'target' attribute string;
+__attribute__((target("cpu=sifive-u74;cpu=sifive-u54"))) void testMultiCpuSelectLast() {}
+// CHECK: error: duplicate 'tune=' in the 'target' attribute string;
+__attribute__((target("tune=sifive-u74;tune=sifive-u54"))) void testMultiTuneSelectLast() {}
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -3450,6 +3450,11 @@
 return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
<< Unknown << Tune << ParsedAttrs.Tune << Target;
 
+  if (Context.getTargetInfo().getTriple().isRISCV() &&
+  ParsedAttrs.Duplicate != "")
+return Diag(LiteralLoc,

[PATCH] D151730: [RISCV] Support target attribute for function

2023-10-31 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 557943.
BeMg added a comment.
Herald added a reviewer: aaron.ballman.

Align with spec

1. duplicate target attribute will cause compilation fail


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,45 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m -target-feature +a \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @testDefault
+// CHECK-SAME: () #0 {
+void testDefault() {}
+// CHECK-LABEL: define dso_local void @testMultiAttrStr
+// CHECK-SAME: () #1 {
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void
+testMultiAttrStr() {}
+// CHECK-LABEL: define dso_local void @testSingleExtension
+// CHECK-SAME: () #2 {
+__attribute__((target("arch=+zbb"))) void testSingleExtension() {}
+// CHECK-LABEL: define dso_local void @testMultiExtension
+// CHECK-SAME: () #3 {
+__attribute__((target("arch=+zbb,+v,+zicond"))) void testMultiExtension() {}
+// CHECK-LABEL: define dso_local void @testFullArch
+// CHECK-SAME: () #4 {
+__attribute__((target("arch=rv64gc_zbb"))) void testFullArch() {}
+// CHECK-LABEL: define dso_local void @testFullArchButSmallThanCmdArch
+// CHECK-SAME: () #5 {
+__attribute__((target("arch=rv64im"))) void testFullArchButSmallThanCmdArch() {}
+// CHECK-LABEL: define dso_local void @testAttrArchAndAttrCpu
+// CHECK-SAME: () #6 {
+__attribute__((target("cpu=sifive-u54;arch=+zbb"))) void
+testAttrArchAndAttrCpu() {}
+// CHECK-LABEL: define dso_local void @testAttrFullArchAndAttrCpu
+// CHECK-SAME: () #7 {
+__attribute__((target("cpu=sifive-u54;arch=rv64im"))) void
+testAttrFullArchAndAttrCpu() {}
+// CHECK-LABEL: define dso_local void @testAttrCpuOnly
+// CHECK-SAME: () #8 {
+__attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
+
+//.
+// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+zifencei" }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" "tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+zbb,+zifencei" }
+// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+zbb,+zicsr,+zifencei" }
+// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m" }
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+zbb,+zifencei" }
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+zicsr,+zifencei" }
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
@@ -0,0 +1,10 @@
+// REQUIRES: riscv-registered-target
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m -target-feature +a \
+// RUN:  -emit-llvm %s 2>&1 | FileCheck %s
+
+// CHECK: error: duplicate 'arch=' in the 'target' attribute string;
+__attribute__((target("arch=rv64gc;arch=rv64gc_zbb"))) void testMultiArchSelectLast() {}
+// CHECK: error: duplicate 'cpu=' in the 'target' attribute string;
+__attribute__((target("cpu=sifive-u74;cpu=sifive-u54"))) void testMultiCpuSelectLast() {}
+// CHECK: error: duplicate 'tune=' in the 'target' attribute string;
+__attribute__((target("tune=sifive-u74;tune=sifive-u54"))) void testMultiTuneSelectLast() {}
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -3450,6 +3450,11 @@
 return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
<< Unknown << Tune << ParsedAttrs.Tune << Target;
 
+  if (Context.getTargetInfo().getTriple().isRISCV() &&
+  ParsedAttrs.Duplicate != "")
+return Diag(LiteralLoc, diag::err_duplicate_target_attribute)
+   << Duplicate << None << ParsedAttrs.Duplicate << Target;
+
   if (ParsedAttrs.Duplicate != "")
 return Diag(LiteralLoc,

[PATCH] D151730: [RISCV] Support target attribute for function

2023-11-02 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:434
+if (MarchFromCPU != "") {
+  Ret.Features.clear();
+  handleFullArchString(MarchFromCPU, Ret.Features);

craig.topper wrote:
> Why does this clear Ret.Features, but full-arch-string doesn't?
I think full-arch-string also clear the Ret.Features in line 398 right after 
`if (Feature.startswith("arch="))`.


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[PATCH] D151730: [RISCV] Support target attribute for function

2023-11-02 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 557995.
BeMg added a comment.

1. remain else if by removing continue
2. Keep NonISAExtFeature after override
3. Update testcase with -target-feature +save-restore
4. Improve resolveTargetOverride function


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,46 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m \
+// RUN:  -target-feature +a -target-feature +save-restore \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @testDefault
+// CHECK-SAME: () #0 {
+void testDefault() {}
+// CHECK-LABEL: define dso_local void @testMultiAttrStr
+// CHECK-SAME: () #1 {
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void
+testMultiAttrStr() {}
+// CHECK-LABEL: define dso_local void @testSingleExtension
+// CHECK-SAME: () #2 {
+__attribute__((target("arch=+zbb"))) void testSingleExtension() {}
+// CHECK-LABEL: define dso_local void @testMultiExtension
+// CHECK-SAME: () #3 {
+__attribute__((target("arch=+zbb,+v,+zicond"))) void testMultiExtension() {}
+// CHECK-LABEL: define dso_local void @testFullArch
+// CHECK-SAME: () #4 {
+__attribute__((target("arch=rv64gc_zbb"))) void testFullArch() {}
+// CHECK-LABEL: define dso_local void @testFullArchButSmallThanCmdArch
+// CHECK-SAME: () #5 {
+__attribute__((target("arch=rv64im"))) void testFullArchButSmallThanCmdArch() {}
+// CHECK-LABEL: define dso_local void @testAttrArchAndAttrCpu
+// CHECK-SAME: () #6 {
+__attribute__((target("cpu=sifive-u54;arch=+zbb"))) void
+testAttrArchAndAttrCpu() {}
+// CHECK-LABEL: define dso_local void @testAttrFullArchAndAttrCpu
+// CHECK-SAME: () #7 {
+__attribute__((target("cpu=sifive-u54;arch=rv64im"))) void
+testAttrFullArchAndAttrCpu() {}
+// CHECK-LABEL: define dso_local void @testAttrCpuOnly
+// CHECK-SAME: () #8 {
+__attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
+
+//.
+// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei" }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" "tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei" }
+// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei" }
+// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore" }
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei" }
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei" }
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
@@ -0,0 +1,10 @@
+// REQUIRES: riscv-registered-target
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m -target-feature +a \
+// RUN:  -emit-llvm %s 2>&1 | FileCheck %s
+
+// CHECK: error: duplicate 'arch=' in the 'target' attribute string;
+__attribute__((target("arch=rv64gc;arch=rv64gc_zbb"))) void testMultiArchSelectLast() {}
+// CHECK: error: duplicate 'cpu=' in the 'target' attribute string;
+__attribute__((target("cpu=sifive-u74;cpu=sifive-u54"))) void testMultiCpuSelectLast() {}
+// CHECK: error: duplicate 'tune=' in the 'target' attribute string;
+__attribute__((target("tune=sifive-u74;tune=sifive-u54"))) void testMultiTuneSelectLast() {}
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -3450,6 +3450,11 @@
 return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
<< Unknown << Tune << ParsedAttrs.Tune << Target;
 
+  if (Context.getTargetInfo().getTriple().isRISCV() &&
+  Par

[PATCH] D151730: [RISCV] Support target attribute for function

2023-11-03 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:370
+ std::vector &Features) {
+  Features.push_back("__RISCV_TargetAttrNeedOverride");
+  auto RII = llvm::RISCVISAInfo::parseArchString(

craig.topper wrote:
> Why do we need "__RISCV_TargetAttrNeedOverride"?
My idea is using `__RISCV_TargetAttrNeedOverride` to distinguish the 
module-level feature and target attribute feature.

The module-level feature will merge with target attribute feature in 
https://github.com/llvm/llvm-project/blob/main/clang/lib/AST/ASTContext.cpp#L13481.
 And be used/refine inside RISCVTargetInfo::initFeatureMap.

After merge, It could find the target attribute feature start point by 
analyzing FeatureVec, but I prefer use the `__RISCV_TargetAttrNeedOverride` to 
do this job.




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[PATCH] D136570: [RISCV] Add Svnapot extension

2022-10-23 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, jdoerfert, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136570

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll

Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvnapot = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -388,6 +388,13 @@
 AssemblerPredicate<(all_of FeatureStdExtZicbop),
 "'Zicbop' (Cache-Block Prefetch Instructions)">;
 
+def FeatureStdExtSvnapot
+: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
+   "'Svnapot' (NAPOT Translation Contiguity)">;
+def HasStdExtSvnapot : Predicate<"Subtarget->hasStdExtSvnapot()">,
+ AssemblerPredicate<(all_of FeatureStdExtSvnapot),
+ "'Svnapot' (NAPOT Translation Contiguity)">;
+
 def FeatureStdExtZtso
 : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -101,6 +101,8 @@
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},

[PATCH] D136571: [RISCV] add svinval extension

2022-10-23 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, jdoerfert, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136571

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/priv-valid.s

Index: llvm/test/MC/RISCV/priv-valid.s
===
--- llvm/test/MC/RISCV/priv-valid.s
+++ llvm/test/MC/RISCV/priv-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: uret
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvinval = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvinval() const { return HasStdExtSvinval; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmu

[PATCH] D136570: [RISCV] Add Svnapot extension

2022-10-23 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 470039.
BeMg added a comment.

Update


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136570/new/

https://reviews.llvm.org/D136570

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll

Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvnapot = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -388,6 +388,13 @@
 AssemblerPredicate<(all_of FeatureStdExtZicbop),
 "'Zicbop' (Cache-Block Prefetch Instructions)">;
 
+def FeatureStdExtSvnapot
+: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
+   "'Svnapot' (NAPOT Translation Contiguity)">;
+def HasStdExtSvnapot : Predicate<"Subtarget->hasStdExtSvnapot()">,
+ AssemblerPredicate<(all_of FeatureStdExtSvnapot),
+ "'Svnapot' (NAPOT Translation Contiguity)">;
+
 def FeatureStdExtZtso
 : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -101,6 +101,8 @@
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},
 {"zicbop", RISCVExtensionVersion{1, 0}},
+
+{"svnapot", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -39,6 +39,7 @@
 /

[PATCH] D136570: [RISCV] Add Svnapot extension

2022-10-23 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 470040.
BeMg added a comment.

Remove Predicate and AssemblerPredicate


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136570/new/

https://reviews.llvm.org/D136570

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll

Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvnapot = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -388,6 +388,10 @@
 AssemblerPredicate<(all_of FeatureStdExtZicbop),
 "'Zicbop' (Cache-Block Prefetch Instructions)">;
 
+def FeatureStdExtSvnapot
+: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
+   "'Svnapot' (NAPOT Translation Contiguity)">;
+
 def FeatureStdExtZtso
 : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -101,6 +101,8 @@
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},
 {"zicbop", RISCVExtensionVersion{1, 0}},
+
+{"svnapot", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -39,6 +39,7 @@
 // CHECK-NOT: __riscv_zk
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
+// CHECK-NOT: __riscv_svnapot
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -

[PATCH] D136571: [RISCV] add svinval extension

2022-10-23 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 470041.
BeMg added a comment.

Use Requires<[HasStdSvinval]> instead of using let Predicates


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/priv-valid.s

Index: llvm/test/MC/RISCV/priv-valid.s
===
--- llvm/test/MC/RISCV/priv-valid.s
+++ llvm/test/MC/RISCV/priv-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: uret
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvinval = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvinval() const { return HasStdExtSvinval; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -796,24 +796,24 @@
   let rs2 = 0b00101;
 }
 
-def SFENCE_W_INVAL :

[PATCH] D136571: [RISCV] add svinval extension

2022-10-23 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 470046.
BeMg added a comment.

Reorder the def then use the same let Predicates


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/priv-valid.s

Index: llvm/test/MC/RISCV/priv-valid.s
===
--- llvm/test/MC/RISCV/priv-valid.s
+++ llvm/test/MC/RISCV/priv-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: uret
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvinval = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvinval() const { return HasStdExtSvinval; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -796,6 +796,7 @@
   let rs2 = 0b00101;
 }
 
+let Predicates = [HasStdExtSvinval]

[PATCH] D136570: [RISCV] Add Svnapot extension

2022-10-24 Thread Piyou Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf8b8426861a7: [RISCV] Add Svnapot extension (authored by 
BeMg).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136570/new/

https://reviews.llvm.org/D136570

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll

Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvnapot = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -388,6 +388,10 @@
 AssemblerPredicate<(all_of FeatureStdExtZicbop),
 "'Zicbop' (Cache-Block Prefetch Instructions)">;
 
+def FeatureStdExtSvnapot
+: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
+   "'Svnapot' (NAPOT Translation Contiguity)">;
+
 def FeatureStdExtZtso
 : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -101,6 +101,8 @@
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},
 {"zicbop", RISCVExtensionVersion{1, 0}},
+
+{"svnapot", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -39,6 +39,7 @@
 // CHECK-NOT: __riscv_zk
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
+// CHECK-NOT: __riscv_svnapot
 
 // RUN: %clang -targe

[PATCH] D136571: [RISCV] add svinval extension

2022-10-25 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 470428.
BeMg added a comment.

Update RISCVUsage.html


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/priv-valid.s

Index: llvm/test/MC/RISCV/priv-valid.s
===
--- llvm/test/MC/RISCV/priv-valid.s
+++ llvm/test/MC/RISCV/priv-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: uret
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvinval = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvinval() const { return HasStdExtSvinval; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -796,6 +796,7 @@
   let rs2 = 0b00101;
 }
 
+let Predicates = [HasStdExtSvinval]

[PATCH] D136571: [RISCV] add svinval extension

2022-10-25 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 470559.
BeMg added a comment.

Update RISCVUsage.rst


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/priv-valid.s

Index: llvm/test/MC/RISCV/priv-valid.s
===
--- llvm/test/MC/RISCV/priv-valid.s
+++ llvm/test/MC/RISCV/priv-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: uret
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -111,6 +113,7 @@
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@
   bool HasStdExtZicbom = false;
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
+  bool HasStdExtSvinval = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtSvinval() const { return HasStdExtSvinval; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -796,6 +796,7 @@
   let rs2 = 0b00101;
 }
 
+let Predicates = [HasStdExtSvinval]

[PATCH] D136571: [RISCV] add svinval extension

2022-10-25 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 470722.
BeMg marked 2 inline comments as done.
BeMg added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/priv-valid.s

Index: llvm/test/MC/RISCV/priv-valid.s
===
--- llvm/test/MC/RISCV/priv-valid.s
+++ llvm/test/MC/RISCV/priv-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: uret
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -74,6 +75,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -114,6 +116,7 @@
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -153,6 +156,7 @@
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -86,6 +86,7 @@
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
   bool HasStdExtSvnapot = false;
+  bool HasStdExtSvinval = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -184,6 +185,7 @@
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
   bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
+  bool hasStdExtSvinval() const { return HasStdExtSvinval; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -796,6 +796,7 @@
   let rs2 = 0b00101;
 }
 
+l

[PATCH] D136571: [RISCV] add svinval extension

2022-10-26 Thread Piyou Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7d7940fd7761: [RISCV] add svinval extension (authored by 
BeMg).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/priv-valid.s

Index: llvm/test/MC/RISCV/priv-valid.s
===
--- llvm/test/MC/RISCV/priv-valid.s
+++ llvm/test/MC/RISCV/priv-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: uret
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -74,6 +75,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -114,6 +116,7 @@
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -153,6 +156,7 @@
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -86,6 +86,7 @@
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
   bool HasStdExtSvnapot = false;
+  bool HasStdExtSvinval = false;
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
@@ -184,6 +185,7 @@
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
   bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
+  bool hasStdExtSvinval() const { return HasStdExtSvinval; }
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -

[PATCH] D140361: [WIP][RISCV] Merge Masked and unMasked manual codegen

2022-12-19 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140361

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -171,6 +171,10 @@
 
   if (RVVI->hasManualCodegen()) {
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+if (RVVI->isMasked())
+  OS << "IsMasked = true;\n";
+else
+  OS << "IsMasked = false;\n";
 OS << RVVI->getManualCodegen();
 OS << "break;\n";
 return;
@@ -517,7 +521,6 @@
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
-StringRef MaskedManualCodegen = R->getValueAsString("MaskedManualCodegen");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
 std::vector RequiredFeatures =
@@ -594,7 +597,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
+SupportOverloading, HasBuiltinAlias, ManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
 Policy::PolicyNone, IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
@@ -610,7 +613,7 @@
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-  MaskedManualCodegen, PolicyTypes.value(), IntrinsicTypes,
+  ManualCodegen, PolicyTypes.value(), IntrinsicTypes,
   RequiredFeatures, NF, P, IsPrototypeDefaultTU));
 }
   } // End for Log2LMULList
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19461,6 +19461,7 @@
   constexpr unsigned TAIL_AGNOSTIC = 1;
   constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
   int DefaultPolicy = TAIL_UNDISTURBED;
+  bool IsMasked = false;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector IntrinsicTypes;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -217,7 +217,6 @@
 
   // Manual code in clang codegen riscv_vector_builtin_cg.inc
   code ManualCodegen = [{}];
-  code MaskedManualCodegen = [{}];
 
   // When emit the automatic clang codegen, it describes what types we have to use
   // to obtain the specific LLVM intrinsic. -1 means the return type, otherwise,
@@ -627,31 +626,18 @@
   UnMaskedPolicyScheme = HasPassthruOperand,
   ManualCodegen = [{
   {
-if (DefaultPolicy == TAIL_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-IntrinsicTypes = {ResultType, Ops[3]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-Value *NewVL = Ops[2];
-Ops.erase(Ops.begin() + 2);
-llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
-llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
-// Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
-return V;
-  }
-  }],
-  MaskedManualCodegen = [{
-  {
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-Intrinsic

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

2022-12-20 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 484180.
BeMg added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139995/new/

https://reviews.llvm.org/D139995

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -164,8 +164,8 @@
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
   // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (RVVI->getDefaultPolicy() != Policy::TU &&
-  RVVI->getDefaultPolicy() != Policy::TUMU && !RVVI->hasPassthruOperand() &&
+  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
+  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
 
@@ -193,11 +193,11 @@
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
   " DefaultPolicy));\n";
   if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -207,7 +207,7 @@
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
 "DefaultPolicy));\n";
 else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy() == Policy::TA)
+ RVVI->getDefaultPolicy().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -527,7 +527,11 @@
 unsigned NF = R->getValueAsInt("NF");
 
 // If unmasked builtin supports policy, they should be TU or TA.
-SmallVector SupportedUnMaskedPolicies = {Policy::TU, Policy::TA};
+llvm::SmallVector SupportedUnMaskedPolicies;
+SupportedUnMaskedPolicies.emplace_back(Policy(
+Policy::PolicyType::Undisturbed, Policy::PolicyType::Omit)); // TU
+SupportedUnMaskedPolicies.emplace_back(
+Policy(Policy::PolicyType::Agnostic, Policy::PolicyType::Omit)); // TA
 SmallVector SupportedMaskedPolicies =
 RVVIntrinsic::getSupportedMaskedPolicies(HasTailPolicy, HasMaskPolicy);
 
@@ -544,10 +548,10 @@
 auto Prototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme);
+UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme);
+IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -569,7 +573,7 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
@@ -596,7 +600,7 @@
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
 SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
 *MaskTypes, IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -914,30 +914,22 @@
   SmallVector NewPrototype(Prototype.begin(),
 Prototype.end());
   // Update DefaultPolicy if need (TA or TAMA) for compute builtin types.
-  switch (DefaultPolicy) {
-  case Policy::MA:
-DefaultPolicy = Policy::TAMA;
-

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

2022-12-20 Thread Piyou Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0d4c6506100b: [RISCV] Refactor RVV Policy by structure 
(authored by BeMg).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139995/new/

https://reviews.llvm.org/D139995

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -164,8 +164,8 @@
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
   // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (RVVI->getDefaultPolicy() != Policy::TU &&
-  RVVI->getDefaultPolicy() != Policy::TUMU && !RVVI->hasPassthruOperand() &&
+  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
+  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
 
@@ -193,11 +193,11 @@
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
   " DefaultPolicy));\n";
   if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -207,7 +207,7 @@
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
 "DefaultPolicy));\n";
 else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy() == Policy::TA)
+ RVVI->getDefaultPolicy().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -527,7 +527,11 @@
 unsigned NF = R->getValueAsInt("NF");
 
 // If unmasked builtin supports policy, they should be TU or TA.
-SmallVector SupportedUnMaskedPolicies = {Policy::TU, Policy::TA};
+llvm::SmallVector SupportedUnMaskedPolicies;
+SupportedUnMaskedPolicies.emplace_back(Policy(
+Policy::PolicyType::Undisturbed, Policy::PolicyType::Omit)); // TU
+SupportedUnMaskedPolicies.emplace_back(
+Policy(Policy::PolicyType::Agnostic, Policy::PolicyType::Omit)); // TA
 SmallVector SupportedMaskedPolicies =
 RVVIntrinsic::getSupportedMaskedPolicies(HasTailPolicy, HasMaskPolicy);
 
@@ -544,10 +548,10 @@
 auto Prototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme);
+UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme);
+IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -569,7 +573,7 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
@@ -596,7 +600,7 @@
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
 SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
 *MaskTypes, IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -914,30 +914,22 @@
   SmallVector NewPrototype(Prototype.begin(),
 Prototype.end());
   // Upda

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

2022-12-20 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 484251.
BeMg added a comment.

Update format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140361/new/

https://reviews.llvm.org/D140361

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -171,6 +171,10 @@
 
   if (RVVI->hasManualCodegen()) {
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+if (RVVI->isMasked())
+  OS << "IsMasked = true;\n";
+else
+  OS << "IsMasked = false;\n";
 OS << RVVI->getManualCodegen();
 OS << "break;\n";
 return;
@@ -517,7 +521,6 @@
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
-StringRef MaskedManualCodegen = R->getValueAsString("MaskedManualCodegen");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
 std::vector RequiredFeatures =
@@ -594,7 +597,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
+SupportOverloading, HasBuiltinAlias, ManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
 Policy::PolicyNone, IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
@@ -610,7 +613,7 @@
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-  MaskedManualCodegen, PolicyTypes.value(), IntrinsicTypes,
+  ManualCodegen, PolicyTypes.value(), IntrinsicTypes,
   RequiredFeatures, NF, P, IsPrototypeDefaultTU));
 }
   } // End for Log2LMULList
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19461,6 +19461,7 @@
   constexpr unsigned TAIL_AGNOSTIC = 1;
   constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
   int DefaultPolicy = TAIL_UNDISTURBED;
+  bool IsMasked = false;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector IntrinsicTypes;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -217,7 +217,6 @@
 
   // Manual code in clang codegen riscv_vector_builtin_cg.inc
   code ManualCodegen = [{}];
-  code MaskedManualCodegen = [{}];
 
   // When emit the automatic clang codegen, it describes what types we have to use
   // to obtain the specific LLVM intrinsic. -1 means the return type, otherwise,
@@ -627,31 +626,18 @@
   UnMaskedPolicyScheme = HasPassthruOperand,
   ManualCodegen = [{
   {
-if (DefaultPolicy == TAIL_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-IntrinsicTypes = {ResultType, Ops[3]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-Value *NewVL = Ops[2];
-Ops.erase(Ops.begin() + 2);
-llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
-llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
-// Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
-return V;
-  }
-  }],
-  MaskedManualCodegen = [{
-  {
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
+if(IsMasked) {
+  // Move mask to right before vl.
+  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
+  if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
+  Ops.push_back(ConstantInt::get(Ops.back()->getTyp

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

2022-12-20 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 484436.
BeMg added a comment.

Update format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140361/new/

https://reviews.llvm.org/D140361

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -171,6 +171,10 @@
 
   if (RVVI->hasManualCodegen()) {
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+if (RVVI->isMasked())
+  OS << "IsMasked = true;\n";
+else
+  OS << "IsMasked = false;\n";
 OS << RVVI->getManualCodegen();
 OS << "break;\n";
 return;
@@ -517,7 +521,6 @@
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
-StringRef MaskedManualCodegen = R->getValueAsString("MaskedManualCodegen");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
 std::vector RequiredFeatures =
@@ -594,7 +597,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
+SupportOverloading, HasBuiltinAlias, ManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
 Policy::PolicyNone, IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
@@ -610,7 +613,7 @@
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-  MaskedManualCodegen, PolicyTypes.value(), IntrinsicTypes,
+  ManualCodegen, PolicyTypes.value(), IntrinsicTypes,
   RequiredFeatures, NF, P, IsPrototypeDefaultTU));
 }
   } // End for Log2LMULList
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19461,6 +19461,7 @@
   constexpr unsigned TAIL_AGNOSTIC = 1;
   constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
   int DefaultPolicy = TAIL_UNDISTURBED;
+  bool IsMasked = false;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector IntrinsicTypes;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -217,7 +217,6 @@
 
   // Manual code in clang codegen riscv_vector_builtin_cg.inc
   code ManualCodegen = [{}];
-  code MaskedManualCodegen = [{}];
 
   // When emit the automatic clang codegen, it describes what types we have to use
   // to obtain the specific LLVM intrinsic. -1 means the return type, otherwise,
@@ -627,31 +626,18 @@
   UnMaskedPolicyScheme = HasPassthruOperand,
   ManualCodegen = [{
   {
-if (DefaultPolicy == TAIL_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-IntrinsicTypes = {ResultType, Ops[3]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-Value *NewVL = Ops[2];
-Ops.erase(Ops.begin() + 2);
-llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
-llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
-// Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
-return V;
-  }
-  }],
-  MaskedManualCodegen = [{
-  {
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
+if (IsMasked) {
+  // Move mask to right before vl.
+  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
+  if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
+  Ops.push_back(ConstantInt::get(Ops.back()->getTy

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

2022-12-20 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 484437.
BeMg added a comment.

Update format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140361/new/

https://reviews.llvm.org/D140361

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -171,6 +171,10 @@
 
   if (RVVI->hasManualCodegen()) {
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+if (RVVI->isMasked())
+  OS << "IsMasked = true;\n";
+else
+  OS << "IsMasked = false;\n";
 OS << RVVI->getManualCodegen();
 OS << "break;\n";
 return;
@@ -517,7 +521,6 @@
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
-StringRef MaskedManualCodegen = R->getValueAsString("MaskedManualCodegen");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
 std::vector RequiredFeatures =
@@ -594,7 +597,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
+SupportOverloading, HasBuiltinAlias, ManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
 Policy::PolicyNone, IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
@@ -610,7 +613,7 @@
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-  MaskedManualCodegen, PolicyTypes.value(), IntrinsicTypes,
+  ManualCodegen, PolicyTypes.value(), IntrinsicTypes,
   RequiredFeatures, NF, P, IsPrototypeDefaultTU));
 }
   } // End for Log2LMULList
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19461,6 +19461,7 @@
   constexpr unsigned TAIL_AGNOSTIC = 1;
   constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
   int DefaultPolicy = TAIL_UNDISTURBED;
+  bool IsMasked = false;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector IntrinsicTypes;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -217,7 +217,6 @@
 
   // Manual code in clang codegen riscv_vector_builtin_cg.inc
   code ManualCodegen = [{}];
-  code MaskedManualCodegen = [{}];
 
   // When emit the automatic clang codegen, it describes what types we have to use
   // to obtain the specific LLVM intrinsic. -1 means the return type, otherwise,
@@ -627,31 +626,18 @@
   UnMaskedPolicyScheme = HasPassthruOperand,
   ManualCodegen = [{
   {
-if (DefaultPolicy == TAIL_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-IntrinsicTypes = {ResultType, Ops[3]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-Value *NewVL = Ops[2];
-Ops.erase(Ops.begin() + 2);
-llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
-llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
-// Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
-return V;
-  }
-  }],
-  MaskedManualCodegen = [{
-  {
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
+if (IsMasked) {
+  // Move mask to right before vl.
+  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
+  if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
+  Ops.push_back(ConstantInt::get(Ops.back()->getTy

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

2022-12-20 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 484459.
BeMg added a comment.

Update format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140361/new/

https://reviews.llvm.org/D140361

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -171,6 +171,10 @@
 
   if (RVVI->hasManualCodegen()) {
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+if (RVVI->isMasked())
+  OS << "IsMasked = true;\n";
+else
+  OS << "IsMasked = false;\n";
 OS << RVVI->getManualCodegen();
 OS << "break;\n";
 return;
@@ -517,7 +521,6 @@
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
-StringRef MaskedManualCodegen = R->getValueAsString("MaskedManualCodegen");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
 std::vector RequiredFeatures =
@@ -594,7 +597,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
+SupportOverloading, HasBuiltinAlias, ManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
 Policy::PolicyNone, IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
@@ -610,7 +613,7 @@
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-  MaskedManualCodegen, PolicyTypes.value(), IntrinsicTypes,
+  ManualCodegen, PolicyTypes.value(), IntrinsicTypes,
   RequiredFeatures, NF, P, IsPrototypeDefaultTU));
 }
   } // End for Log2LMULList
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19461,6 +19461,7 @@
   constexpr unsigned TAIL_AGNOSTIC = 1;
   constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
   int DefaultPolicy = TAIL_UNDISTURBED;
+  bool IsMasked = false;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector IntrinsicTypes;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -217,7 +217,6 @@
 
   // Manual code in clang codegen riscv_vector_builtin_cg.inc
   code ManualCodegen = [{}];
-  code MaskedManualCodegen = [{}];
 
   // When emit the automatic clang codegen, it describes what types we have to use
   // to obtain the specific LLVM intrinsic. -1 means the return type, otherwise,
@@ -627,31 +626,18 @@
   UnMaskedPolicyScheme = HasPassthruOperand,
   ManualCodegen = [{
   {
-if (DefaultPolicy == TAIL_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-IntrinsicTypes = {ResultType, Ops[3]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-Value *NewVL = Ops[2];
-Ops.erase(Ops.begin() + 2);
-llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
-llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
-// Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
-return V;
-  }
-  }],
-  MaskedManualCodegen = [{
-  {
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
+if (IsMasked) {
+  // Move mask to right before vl.
+  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
+  if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
+  Ops.push_back(ConstantInt::get(Ops.back()->getTy

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

2022-12-21 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 484498.
BeMg added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140361/new/

https://reviews.llvm.org/D140361

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -171,6 +171,10 @@
 
   if (RVVI->hasManualCodegen()) {
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+if (RVVI->isMasked())
+  OS << "IsMasked = true;\n";
+else
+  OS << "IsMasked = false;\n";
 OS << RVVI->getManualCodegen();
 OS << "break;\n";
 return;
@@ -517,7 +521,6 @@
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
-StringRef MaskedManualCodegen = R->getValueAsString("MaskedManualCodegen");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
 std::vector RequiredFeatures =
@@ -598,7 +601,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
+SupportOverloading, HasBuiltinAlias, ManualCodegen,
 *MaskTypes, IntrinsicTypes, RequiredFeatures, NF,
 Policy(), IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
@@ -614,7 +617,7 @@
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-  MaskedManualCodegen, *PolicyTypes, IntrinsicTypes,
+  ManualCodegen, *PolicyTypes, IntrinsicTypes,
   RequiredFeatures, NF, P, IsPrototypeDefaultTU));
 }
   } // End for Log2LMULList
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19438,6 +19438,7 @@
   constexpr unsigned TAIL_AGNOSTIC = 1;
   constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
   int DefaultPolicy = TAIL_UNDISTURBED;
+  bool IsMasked = false;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector IntrinsicTypes;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -217,7 +217,6 @@
 
   // Manual code in clang codegen riscv_vector_builtin_cg.inc
   code ManualCodegen = [{}];
-  code MaskedManualCodegen = [{}];
 
   // When emit the automatic clang codegen, it describes what types we have to use
   // to obtain the specific LLVM intrinsic. -1 means the return type, otherwise,
@@ -627,31 +626,18 @@
   UnMaskedPolicyScheme = HasPassthruOperand,
   ManualCodegen = [{
   {
-if (DefaultPolicy == TAIL_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-IntrinsicTypes = {ResultType, Ops[3]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-Value *NewVL = Ops[2];
-Ops.erase(Ops.begin() + 2);
-llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
-llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
-// Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
-return V;
-  }
-  }],
-  MaskedManualCodegen = [{
-  {
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
+if (IsMasked) {
+  // Move mask to right before vl.
+  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
+  if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
+  Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
+  Intr

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

2022-12-21 Thread Piyou Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5370255ff18a: [RISCV] Merge Masked and unMasked RVV manual 
codegen (authored by BeMg).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140361/new/

https://reviews.llvm.org/D140361

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -171,6 +171,10 @@
 
   if (RVVI->hasManualCodegen()) {
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+if (RVVI->isMasked())
+  OS << "IsMasked = true;\n";
+else
+  OS << "IsMasked = false;\n";
 OS << RVVI->getManualCodegen();
 OS << "break;\n";
 return;
@@ -517,7 +521,6 @@
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
-StringRef MaskedManualCodegen = R->getValueAsString("MaskedManualCodegen");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
 std::vector RequiredFeatures =
@@ -598,7 +601,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
+SupportOverloading, HasBuiltinAlias, ManualCodegen,
 *MaskTypes, IntrinsicTypes, RequiredFeatures, NF,
 Policy(), IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
@@ -614,7 +617,7 @@
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-  MaskedManualCodegen, *PolicyTypes, IntrinsicTypes,
+  ManualCodegen, *PolicyTypes, IntrinsicTypes,
   RequiredFeatures, NF, P, IsPrototypeDefaultTU));
 }
   } // End for Log2LMULList
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19442,6 +19442,7 @@
   constexpr unsigned TAIL_AGNOSTIC = 1;
   constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
   int DefaultPolicy = TAIL_UNDISTURBED;
+  bool IsMasked = false;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector IntrinsicTypes;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -217,7 +217,6 @@
 
   // Manual code in clang codegen riscv_vector_builtin_cg.inc
   code ManualCodegen = [{}];
-  code MaskedManualCodegen = [{}];
 
   // When emit the automatic clang codegen, it describes what types we have to use
   // to obtain the specific LLVM intrinsic. -1 means the return type, otherwise,
@@ -627,31 +626,18 @@
   UnMaskedPolicyScheme = HasPassthruOperand,
   ManualCodegen = [{
   {
-if (DefaultPolicy == TAIL_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-IntrinsicTypes = {ResultType, Ops[3]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-Value *NewVL = Ops[2];
-Ops.erase(Ops.begin() + 2);
-llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
-llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
-// Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
-return V;
-  }
-  }],
-  MaskedManualCodegen = [{
-  {
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
-  Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
+if (IsMasked) {
+  // Move mask to right before vl.
+  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
+  if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+

[PATCH] D151730: [RISCV] Support target attribute for function

2023-10-05 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added a comment.

ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

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[PATCH] D155674: [RISCV] Update zihintntl to 1p0

2023-07-18 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
jdoerfert, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, eopXD, MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155674

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntl-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN: | FileChec

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: llvm/docs/RISCVUsage.rst:214
+``zihintntl``
   LLVM implements the `0.2 draft specification 
`__.
 

zihintntl could add into `table:: Ratified Extensions by Status`, and be 
removed this from the Experimental Extensions section.


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[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: clang/test/Preprocessor/riscv-target-features.c:151
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
 // CHECK-ZIHINTNTL-EXT: __riscv_zihintntl 2000{{$}}
 

The CHECK-ZIHINTNTL-EXT also need update.


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[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: llvm/unittests/Support/RISCVISAInfoTest.cpp:376
   EXPECT_EQ(Exts.count("zihintntl"), 1U);
-  auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izihintntl0p2", 
true);
+  auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izihintntl1p0", 
true);
   ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded());

These unit tests are used to test the experimental extension name parsing, it 
is not suitable to use zihintntl here because zihintntl is no longer 
experimental.

I update it by https://reviews.llvm.org/D155673. After rebasing, I think the 
test fail in RISCVISAInfoTest.cpp can be resolved.




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[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added a comment.

LGTM


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[PATCH] D155674: [RISCV] Update zihintntl to 1p0

2023-07-20 Thread Piyou Chen via Phabricator via cfe-commits

BeMg abandoned this revision.
BeMg added a comment.

duplicate with https://reviews.llvm.org/D151547


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[PATCH] D155935: [RISCV] Enable multiversion function

2023-07-21 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155935

Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/RISCV/riscv-fmv.c

Index: clang/test/CodeGen/RISCV/riscv-fmv.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-fmv.c
@@ -0,0 +1,98 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+__attribute__((target("arch=+v"))) void test1(void) {}
+__attribute__((target("arch=+v,+zbb"))) void test1(void) {}
+__attribute__((target("arch=+v,+zbb,+zihintntl0p2"))) void test1(void) {}
+__attribute__((target("arch=rv64gc"))) void test1(void) {}
+__attribute__((target("default"))) void test1(void) {}
+
+__attribute__((target("default"))) void test2(void) {}
+
+void test3() { test1(); test2(); }
+
+// CHECK-IR: @0 = private unnamed_addr constant [2 x i8] c"v\00", align 1
+// CHECK-IR: @1 = private unnamed_addr constant [6 x i8] c"v;zbb\00", align 1
+// CHECK-IR: @2 = private unnamed_addr constant [29 x i8] c"v;zbb;experimental-zihintntl\00", align 1
+// CHECK-IR: @3 = private unnamed_addr constant [25 x i8] c"m;a;f;d;c;zicsr;zifencei\00", align 1
+
+// CHECK-IR: @test1.ifunc = weak_odr ifunc void (), ptr @test1.resolver
+// CHECK-IR: @test2.ifunc = weak_odr ifunc void (), ptr @test2.resolver
+
+// CHECK-IR-LABEL: define dso_local void @test1.v
+// CHECK-IR-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.v_zbb
+// CHECK-IR-SAME: () #[[ATTR1:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.v_zbb_experimental-zihintntl
+// CHECK-IR-SAME: () #[[ATTR2:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.m_a_f_d_c_zicsr_zifencei
+// CHECK-IR-SAME: () #[[ATTR3:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1
+// CHECK-IR-SAME: () #[[ATTR4:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test2
+// CHECK-IR-SAME: () #[[ATTR4]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test3
+// CHECK-IR-SAME: () #[[ATTR4]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:call void @test1.ifunc()
+// CHECK-IR-NEXT:call void @test2.ifunc()
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define weak_odr ptr @test1.resolver() comdat {
+// CHECK-IR-NEXT:  resolver_entry:
+// CHECK-IR-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB0:[0-9]+]])
+// CHECK-IR-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK-IR:   resolver_return:
+// CHECK-IR-NEXT:ret ptr @test1.v
+// CHECK-IR:   resolver_else:
+// CHECK-IR-NEXT:[[TMP1:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB1:[0-9]+]])
+// CHECK-IR-NEXT:br i1 [[TMP1]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
+// CHECK-IR:   resolver_return1:
+// CHECK-IR-NEXT:ret ptr @test1.v_zbb
+// CHECK-IR:   resolver_else2:
+// CHECK-IR-NEXT:[[TMP2:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB2:[0-9]+]])
+// CHECK-IR-NEXT:br i1 [[TMP2]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
+// CHECK-IR:   resolver_return3:
+// CHECK-IR-NEXT:ret ptr @test1.v_zbb_experimental-zihintntl
+// CHECK-IR:   resolver_else4:
+// CHECK-IR-NEXT:[[TMP3:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB3:[0-9]+]])
+// CHECK-IR-NEXT:br i1 [[TMP3]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
+// CHECK-IR:   resolver_return5:
+// CHECK-IR-NEXT:ret ptr @test1.m_a_f_d_c_zicsr_zifencei
+// CHECK-IR:   resolver_else6:
+// CHECK-IR-NEXT:ret ptr @test1
+//
+//
+// CHECK-IR-LABEL: define weak_odr ptr @test2.resolver() comdat {
+// CHECK-IR-NEXT:  resolver_entry:
+// CHECK-IR-NEXT:ret ptr @t

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

2023-07-25 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
BeMg requested review of this revision.
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Herald added a project: clang.

Repository:
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Files:
  clang/lib/Headers/riscv_ntlh.h
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c


Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -100,6 +100,24 @@
   *scvs1 = __riscv_ntl_load(scvs2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   *scvc1 = __riscv_ntl_load(scvc2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  uc = __riscv_ntl_load(&sc);   // CHECK: load i8{{.*}}align 1, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  sc = __riscv_ntl_load(&uc);   // CHECK: load i8{{.*}}align 1, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  us = __riscv_ntl_load(&ss);   // CHECK: load i16{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  ss = __riscv_ntl_load(&us);   // CHECK: load i16{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  ui = __riscv_ntl_load(&si);   // CHECK: load i32{{.*}}align 4, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  si = __riscv_ntl_load(&ui);   // CHECK: load i32{{.*}}align 4, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  ull = __riscv_ntl_load(&sll); // CHECK: load i64{{.*}}align 8, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  sll = __riscv_ntl_load(&ull); // CHECK: load i64{{.*}}align 8, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  h1 = __riscv_ntl_load(&h2);   // CHECK: load half{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  f1 = __riscv_ntl_load(&f2);   // CHECK: load float{{.*}}align 4, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  d1 = __riscv_ntl_load(&d2);   // CHECK: load double{{.*}}align 8, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  v4si1 = __riscv_ntl_load(&v4si2);   // CHECK: load <4 x i32>{{.*}}align 16, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  v8ss1 = __riscv_ntl_load(&v8ss2);   // CHECK: load <8 x i16>{{.*}}align 16, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  v16sc1 = __riscv_ntl_load(&v16sc2);   // CHECK: load <16 x i8>{{.*}}align 
16, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvi1 = __riscv_ntl_load(scvi2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvs1 = __riscv_ntl_load(scvs2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvc1 = __riscv_ntl_load(scvc2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+
   __riscv_ntl_store(&uc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: 
store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&sc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: 
store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&us, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: 
store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
@@ -172,6 +190,23 @@
   __riscv_ntl_store(scvs2, *scvs1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   __riscv_ntl_store(scvc2, *scvc1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  __riscv_ntl_store(&uc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&us, 1);// CHECK: store i16{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ss, 1);// CHECK: store i16{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ui, 1);// CHECK: store i32{{.*}}align 4, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&si, 1);// CHECK: store i32{{.*}}align 4, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ull, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sll, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&h1, 1.0);  // CHECK: store half{{.*}}align 2, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&f1, 1.

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

2023-07-27 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 544645.
BeMg added a comment.

Add prefix __riscv_ for all marco


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156221/new/

https://reviews.llvm.org/D156221

Files:
  clang/lib/Headers/riscv_ntlh.h
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c


Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -100,6 +100,24 @@
   *scvs1 = __riscv_ntl_load(scvs2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   *scvc1 = __riscv_ntl_load(scvc2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  uc = __riscv_ntl_load(&sc);   // CHECK: load i8{{.*}}align 1, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  sc = __riscv_ntl_load(&uc);   // CHECK: load i8{{.*}}align 1, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  us = __riscv_ntl_load(&ss);   // CHECK: load i16{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  ss = __riscv_ntl_load(&us);   // CHECK: load i16{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  ui = __riscv_ntl_load(&si);   // CHECK: load i32{{.*}}align 4, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  si = __riscv_ntl_load(&ui);   // CHECK: load i32{{.*}}align 4, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  ull = __riscv_ntl_load(&sll); // CHECK: load i64{{.*}}align 8, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  sll = __riscv_ntl_load(&ull); // CHECK: load i64{{.*}}align 8, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  h1 = __riscv_ntl_load(&h2);   // CHECK: load half{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  f1 = __riscv_ntl_load(&f2);   // CHECK: load float{{.*}}align 4, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  d1 = __riscv_ntl_load(&d2);   // CHECK: load double{{.*}}align 8, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  v4si1 = __riscv_ntl_load(&v4si2);   // CHECK: load <4 x i32>{{.*}}align 16, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  v8ss1 = __riscv_ntl_load(&v8ss2);   // CHECK: load <8 x i16>{{.*}}align 16, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  v16sc1 = __riscv_ntl_load(&v16sc2);   // CHECK: load <16 x i8>{{.*}}align 
16, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvi1 = __riscv_ntl_load(scvi2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvs1 = __riscv_ntl_load(scvs2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvc1 = __riscv_ntl_load(scvc2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+
   __riscv_ntl_store(&uc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: 
store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&sc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: 
store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&us, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: 
store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
@@ -172,6 +190,23 @@
   __riscv_ntl_store(scvs2, *scvs1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   __riscv_ntl_store(scvc2, *scvc1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  __riscv_ntl_store(&uc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&us, 1);// CHECK: store i16{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ss, 1);// CHECK: store i16{{.*}}align 2, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ui, 1);// CHECK: store i32{{.*}}align 4, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&si, 1);// CHECK: store i32{{.*}}align 4, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ull, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sll, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal 
!4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&h1, 1.0);  // CHECK: store half{{.*}}align 2, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&f1, 1.0);  // CHECK: store float{{.*}}align 4, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&d1, 1.0);  // CHECK: store double{{.*}}align 8, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&v4si1, v4si2);  // CHECK: store <4 x i32>{{.*}}align 16, 
!nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl

[PATCH] D152423: [RISCV] Add function that check extension name with version

2023-08-14 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 549892.
BeMg added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

rebase and update testcase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152423/new/

https://reviews.llvm.org/D152423

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+// CHECK-IR: void @test1() #0
+__attribute__((target("arch=-a,+v,+zbb,+zicond1p0"))) void test1() {}
+
+// CHECK-IR: void @test2() #1
+__attribute__((target("arch=rv64gc_zbb"))) void test2 () {}
+
+// CHECK-IR: void @test3() #2
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void test3 () {}
+
+// CHECK-IR: attributes #0 {{.*}}+experimental-zicond{{.*}}+v,+zbb{{.*}}+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a{{.*}}
+// CHECK-IR: attributes #1 {{.*}}+c{{.*}}+zbb{{.*}}
+// CHECK-IR: attributes #2 {{.*}} "target-cpu"="rocket-rv64" {{.*}}+v{{.*}} "tune-cpu"="generic-rv64" {{.*}}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -114,6 +114,9 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  bool supportsTargetAttributeTune() const override { return true; }
+  bool validateCpuSupports(StringRef FeatureStr) const override;
+  ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -250,12 +250,17 @@
 
   // RISCVISAInfo makes implications for ISA features
   std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  std::vector UpdatedFeatures;
+
   // Add non-ISA features like `relax` and `save-restore` back
   for (const std::string &Feature : FeaturesVec)
 if (!llvm::is_contained(ImpliedFeatures, Feature))
-  ImpliedFeatures.push_back(Feature);
+  UpdatedFeatures.push_back(Feature);
+
+  UpdatedFeatures.insert(UpdatedFeatures.end(), ImpliedFeatures.begin(),
+ ImpliedFeatures.end());
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeatures);
 }
 
 std::optional>
@@ -346,3 +351,77 @@
   bool Is64Bit = getTriple().isArch64Bit();
   llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
 }
+
+// Parse RISC-V Target attributes, which are a comma separated list of:
+//  "arch=" - parsed to features as per -march=..
+//  "cpu=" - parsed to features as per -mcpu=.., with CPU set to 
+//  "tune=" - TuneCPU set to 
+ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
+  ParsedTargetAttr Ret;
+  if (Features == "default")
+return Ret;
+  SmallVector AttrFeatures;
+  Features.split(AttrFeatures, ";");
+  bool FoundArch = false;
+
+  for (auto &Feature : AttrFeatures) {
+Feature = Feature.trim();
+StringRef AttrString = Feature.split("=").second.trim();
+
+if (Feature.startswith("arch=")) {
+  if (FoundArch)
+Ret.Duplicate = "arch=";
+  FoundArch = true;
+
+  if (AttrString.startswith("+") || AttrString.startswith("-")) {
+// EXTENSION like arch=+v,+zbb,-c
+SmallVector Exts;
+AttrString.split(Exts, ",");
+for (auto Ext : Exts) {
+  if (Ext.empty())
+continue;
+
+  StringRef ExtName = Ext.substr(1);
+  std::string TargetFeature =
+  llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
+  if (!TargetFeature.empty())
+Ret.Features.push_back(Ext.front() + TargetFeature);
+  else
+Ret.Features.push_back(Ext.str());
+}
+  } else {
+// full-arch-string like arch=rv64gcv
+auto RII = llvm::RISCVISAInfo::parseArchString(
+AttrString, /* EnableExperimentalExtension */ true);
+if (!RII) {
+  consumeError(RII.takeError());
+} else {
+  std::vector FeatStrings = (*RII)->toFeatureVe

[PATCH] D151730: [RISCV] Support target attribute for function

2023-08-15 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 550237.
BeMg added a comment.

rebase and update testcase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+// CHECK-IR: void @test1() #0
+__attribute__((target("arch=-a,+v,+zbb,+zicond1p0"))) void test1() {}
+
+// CHECK-IR: void @test2() #1
+__attribute__((target("arch=rv64gc_zbb"))) void test2 () {}
+
+// CHECK-IR: void @test3() #2
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void test3 () {}
+
+// CHECK-IR: attributes #0 {{.*}}+experimental-zicond{{.*}}+v,+zbb{{.*}}+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a{{.*}}
+// CHECK-IR: attributes #1 {{.*}}+c{{.*}}+zbb{{.*}}
+// CHECK-IR: attributes #2 {{.*}} "target-cpu"="rocket-rv64" {{.*}}+v{{.*}} "tune-cpu"="generic-rv64" {{.*}}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -114,6 +114,9 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  bool supportsTargetAttributeTune() const override { return true; }
+  bool validateCpuSupports(StringRef FeatureStr) const override;
+  ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -250,12 +250,17 @@
 
   // RISCVISAInfo makes implications for ISA features
   std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  std::vector UpdatedFeatures;
+
   // Add non-ISA features like `relax` and `save-restore` back
   for (const std::string &Feature : FeaturesVec)
 if (!llvm::is_contained(ImpliedFeatures, Feature))
-  ImpliedFeatures.push_back(Feature);
+  UpdatedFeatures.push_back(Feature);
+
+  UpdatedFeatures.insert(UpdatedFeatures.end(), ImpliedFeatures.begin(),
+ ImpliedFeatures.end());
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeatures);
 }
 
 std::optional>
@@ -346,3 +351,77 @@
   bool Is64Bit = getTriple().isArch64Bit();
   llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
 }
+
+// Parse RISC-V Target attributes, which are a comma separated list of:
+//  "arch=" - parsed to features as per -march=..
+//  "cpu=" - parsed to features as per -mcpu=.., with CPU set to 
+//  "tune=" - TuneCPU set to 
+ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
+  ParsedTargetAttr Ret;
+  if (Features == "default")
+return Ret;
+  SmallVector AttrFeatures;
+  Features.split(AttrFeatures, ";");
+  bool FoundArch = false;
+
+  for (auto &Feature : AttrFeatures) {
+Feature = Feature.trim();
+StringRef AttrString = Feature.split("=").second.trim();
+
+if (Feature.startswith("arch=")) {
+  if (FoundArch)
+Ret.Duplicate = "arch=";
+  FoundArch = true;
+
+  if (AttrString.startswith("+") || AttrString.startswith("-")) {
+// EXTENSION like arch=+v,+zbb,-c
+SmallVector Exts;
+AttrString.split(Exts, ",");
+for (auto Ext : Exts) {
+  if (Ext.empty())
+continue;
+
+  StringRef ExtName = Ext.substr(1);
+  std::string TargetFeature =
+  llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
+  if (!TargetFeature.empty())
+Ret.Features.push_back(Ext.front() + TargetFeature);
+  else
+Ret.Features.push_back(Ext.str());
+}
+  } else {
+// full-arch-string like arch=rv64gcv
+auto RII = llvm::RISCVISAInfo::parseArchString(
+AttrString, /* EnableExperimentalExtension */ true);
+if (!RII) {
+  consumeError(RII.takeError());
+} else {
+  std::vector FeatStrings = (*RII)->toFeatureVector();
+  for (auto FeatString : FeatStrings)
+Ret

[PATCH] D152423: [RISCV] Add function that check extension name with version

2023-08-15 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 550238.
BeMg added a comment.

revert last patch because it's wrong one


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152423/new/

https://reviews.llvm.org/D152423

Files:
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -604,3 +604,25 @@
   EXPECT_EQ(ExtsRV64IDZce.count("zcmp"), 1U);
   EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
 }
+
+TEST(isSupportedExtensionWithVersion, AcceptsSingleExtensionWithVersion) {
+  EXPECT_TRUE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb1p0"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zfoo1p0"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zfoo"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion(""));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("c2p0zbb1p0"));
+}
+
+TEST(getTargetFeatureForExtension, RetrieveTargetFeatureFromOneExt) {
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zbb"), "zbb");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zicond1p0"),
+"experimental-zicond");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zicond"),
+"experimental-zicond");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zihintntl1234p4321"),
+"");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zfoo"), "");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension(""), "");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zbbzihintntl"), "");
+}
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -1249,3 +1249,40 @@
   }
   llvm_unreachable("Invalid XLEN");
 }
+
+bool RISCVISAInfo::isSupportedExtensionWithVersion(StringRef Ext) {
+  if (Ext.empty())
+return false;
+
+  auto Pos = findLastNonVersionCharacter(Ext) + 1;
+  StringRef Name = Ext.substr(0, Pos);
+  StringRef Vers = Ext.substr(Pos);
+  if (Vers.empty())
+return false;
+
+  unsigned Major, Minor, ConsumeLength;
+  if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+   true, true)) {
+consumeError(std::move(E));
+return false;
+  }
+
+  return true;
+}
+
+std::string RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
+  if (Ext.empty())
+return std::string();
+
+  auto Pos = findLastNonVersionCharacter(Ext) + 1;
+  StringRef Name = Ext.substr(0, Pos);
+
+  if (Pos != Ext.size() && !isSupportedExtensionWithVersion(Ext))
+return std::string();
+
+  if (!isSupportedExtension(Name))
+return std::string();
+
+  return isExperimentalExtension(Name) ? "experimental-" + Name.str()
+   : Name.str();
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -85,10 +85,12 @@
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
+  static bool isSupportedExtensionWithVersion(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext, unsigned MajorVersion,
unsigned MinorVersion);
   static llvm::Expected>
   postProcessAndChecking(std::unique_ptr &&ISAInfo);
+  static std::string getTargetFeatureForExtension(StringRef Ext);
 
 private:
   RISCVISAInfo(unsigned XLen)


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -604,3 +604,25 @@
   EXPECT_EQ(ExtsRV64IDZce.count("zcmp"), 1U);
   EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
 }
+
+TEST(isSupportedExtensionWithVersion, AcceptsSingleExtensionWithVersion) {
+  EXPECT_TRUE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb1p0"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zfoo1p0"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zfoo"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion(""));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("c2p0zbb1p0"));
+}
+
+TEST(getTargetFeatureForExtension, RetrieveTargetFeatureFromOneExt) {
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zbb"), "zbb");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zicond1p0"),
+

[PATCH] D152423: [RISCV] Add function that check extension name with version

2023-08-20 Thread Piyou Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4b60e1e821b4: [RISCV] Add function that check extension name 
with version (authored by BeMg).
Herald added a subscriber: sunshaoce.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152423/new/

https://reviews.llvm.org/D152423

Files:
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -604,3 +604,25 @@
   EXPECT_EQ(ExtsRV64IDZce.count("zcmp"), 1U);
   EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
 }
+
+TEST(isSupportedExtensionWithVersion, AcceptsSingleExtensionWithVersion) {
+  EXPECT_TRUE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb1p0"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zfoo1p0"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zfoo"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion(""));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("c2p0zbb1p0"));
+}
+
+TEST(getTargetFeatureForExtension, RetrieveTargetFeatureFromOneExt) {
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zbb"), "zbb");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zicond1p0"),
+"experimental-zicond");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zicond"),
+"experimental-zicond");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zihintntl1234p4321"),
+"");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zfoo"), "");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension(""), "");
+  EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zbbzihintntl"), "");
+}
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -1253,3 +1253,40 @@
   }
   llvm_unreachable("Invalid XLEN");
 }
+
+bool RISCVISAInfo::isSupportedExtensionWithVersion(StringRef Ext) {
+  if (Ext.empty())
+return false;
+
+  auto Pos = findLastNonVersionCharacter(Ext) + 1;
+  StringRef Name = Ext.substr(0, Pos);
+  StringRef Vers = Ext.substr(Pos);
+  if (Vers.empty())
+return false;
+
+  unsigned Major, Minor, ConsumeLength;
+  if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+   true, true)) {
+consumeError(std::move(E));
+return false;
+  }
+
+  return true;
+}
+
+std::string RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
+  if (Ext.empty())
+return std::string();
+
+  auto Pos = findLastNonVersionCharacter(Ext) + 1;
+  StringRef Name = Ext.substr(0, Pos);
+
+  if (Pos != Ext.size() && !isSupportedExtensionWithVersion(Ext))
+return std::string();
+
+  if (!isSupportedExtension(Name))
+return std::string();
+
+  return isExperimentalExtension(Name) ? "experimental-" + Name.str()
+   : Name.str();
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -85,10 +85,12 @@
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
+  static bool isSupportedExtensionWithVersion(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext, unsigned MajorVersion,
unsigned MinorVersion);
   static llvm::Expected>
   postProcessAndChecking(std::unique_ptr &&ISAInfo);
+  static std::string getTargetFeatureForExtension(StringRef Ext);
 
 private:
   RISCVISAInfo(unsigned XLen)


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -604,3 +604,25 @@
   EXPECT_EQ(ExtsRV64IDZce.count("zcmp"), 1U);
   EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
 }
+
+TEST(isSupportedExtensionWithVersion, AcceptsSingleExtensionWithVersion) {
+  EXPECT_TRUE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb1p0"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zfoo1p0"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zfoo"));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion(""));
+  EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("c2p0zbb1p0"));
+}
+
+TEST(getTargetFeatureForExtension, RetrieveTarget

[PATCH] D151730: [RISCV] Support target attribute for function

2023-08-21 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 552200.
BeMg added a comment.
Herald added a subscriber: sunshaoce.

Remove some condition because RFC doesn't support it. (Must include prefix 
arch|cpu|tune)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+// CHECK-IR: void @test1() #0
+__attribute__((target("arch=-a,+v,+zbb,+zicond1p0"))) void test1() {}
+
+// CHECK-IR: void @test2() #1
+__attribute__((target("arch=rv64gc_zbb"))) void test2 () {}
+
+// CHECK-IR: void @test3() #2
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void test3 () {}
+
+// CHECK-IR: attributes #0 {{.*}}+experimental-zicond{{.*}}+v,+zbb{{.*}}+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a{{.*}}
+// CHECK-IR: attributes #1 {{.*}}+c{{.*}}+zbb{{.*}}
+// CHECK-IR: attributes #2 {{.*}} "target-cpu"="rocket-rv64" {{.*}}+v{{.*}} "tune-cpu"="generic-rv64" {{.*}}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -114,6 +114,9 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  bool supportsTargetAttributeTune() const override { return true; }
+  bool validateCpuSupports(StringRef FeatureStr) const override;
+  ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -250,12 +250,17 @@
 
   // RISCVISAInfo makes implications for ISA features
   std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  std::vector UpdatedFeatures;
+
   // Add non-ISA features like `relax` and `save-restore` back
   for (const std::string &Feature : FeaturesVec)
 if (!llvm::is_contained(ImpliedFeatures, Feature))
-  ImpliedFeatures.push_back(Feature);
+  UpdatedFeatures.push_back(Feature);
+
+  UpdatedFeatures.insert(UpdatedFeatures.end(), ImpliedFeatures.begin(),
+ ImpliedFeatures.end());
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeatures);
 }
 
 std::optional>
@@ -346,3 +351,74 @@
   bool Is64Bit = getTriple().isArch64Bit();
   llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
 }
+
+// Parse RISC-V Target attributes, which are a comma separated list of:
+//  "arch=" - parsed to features as per -march=..
+//  "cpu=" - parsed to features as per -mcpu=.., with CPU set to 
+//  "tune=" - TuneCPU set to 
+ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
+  ParsedTargetAttr Ret;
+  if (Features == "default")
+return Ret;
+  SmallVector AttrFeatures;
+  Features.split(AttrFeatures, ";");
+  bool FoundArch = false;
+
+  for (auto &Feature : AttrFeatures) {
+Feature = Feature.trim();
+StringRef AttrString = Feature.split("=").second.trim();
+
+if (Feature.startswith("arch=")) {
+  if (FoundArch)
+Ret.Duplicate = "arch=";
+  FoundArch = true;
+
+  if (AttrString.startswith("+") || AttrString.startswith("-")) {
+// EXTENSION like arch=+v,+zbb,-c
+SmallVector Exts;
+AttrString.split(Exts, ",");
+for (auto Ext : Exts) {
+  if (Ext.empty())
+continue;
+
+  StringRef ExtName = Ext.substr(1);
+  std::string TargetFeature =
+  llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
+  if (!TargetFeature.empty())
+Ret.Features.push_back(Ext.front() + TargetFeature);
+  else
+Ret.Features.push_back(Ext.str());
+}
+  } else {
+// full-arch-string like arch=rv64gcv
+auto RII = llvm::RISCVISAInfo::parseArchString(
+AttrString, /* EnableExperimentalExtension */ true);
+if (!RII) {
+  consumeError(RII.takeError());
+} else {
+  std::vector Fe

[PATCH] D151730: [RISCV] Support target attribute for function

2023-08-22 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 552265.
BeMg added a comment.

Also remove the `-` operator from target attribute


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+// CHECK-IR: void @test1() #0
+__attribute__((target("arch=+v,+zbb,+zicond1p0"))) void test1() {}
+
+// CHECK-IR: void @test2() #1
+__attribute__((target("arch=rv64gc_zbb"))) void test2 () {}
+
+// CHECK-IR: void @test3() #2
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void test3 () {}
+
+// CHECK-IR: attributes #0 {{.*}}+experimental-zicond{{.*}}+v,+zbb{{.*}}+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b{{.*}}
+// CHECK-IR: attributes #1 {{.*}}+c{{.*}}+zbb{{.*}}
+// CHECK-IR: attributes #2 {{.*}} "target-cpu"="rocket-rv64" {{.*}}+v{{.*}} "tune-cpu"="generic-rv64" {{.*}}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -114,6 +114,9 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  bool supportsTargetAttributeTune() const override { return true; }
+  bool validateCpuSupports(StringRef FeatureStr) const override;
+  ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -250,12 +250,17 @@
 
   // RISCVISAInfo makes implications for ISA features
   std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  std::vector UpdatedFeatures;
+
   // Add non-ISA features like `relax` and `save-restore` back
   for (const std::string &Feature : FeaturesVec)
 if (!llvm::is_contained(ImpliedFeatures, Feature))
-  ImpliedFeatures.push_back(Feature);
+  UpdatedFeatures.push_back(Feature);
+
+  UpdatedFeatures.insert(UpdatedFeatures.end(), ImpliedFeatures.begin(),
+ ImpliedFeatures.end());
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeatures);
 }
 
 std::optional>
@@ -346,3 +351,74 @@
   bool Is64Bit = getTriple().isArch64Bit();
   llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
 }
+
+// Parse RISC-V Target attributes, which are a comma separated list of:
+//  "arch=" - parsed to features as per -march=..
+//  "cpu=" - parsed to features as per -mcpu=.., with CPU set to 
+//  "tune=" - TuneCPU set to 
+ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
+  ParsedTargetAttr Ret;
+  if (Features == "default")
+return Ret;
+  SmallVector AttrFeatures;
+  Features.split(AttrFeatures, ";");
+  bool FoundArch = false;
+
+  for (auto &Feature : AttrFeatures) {
+Feature = Feature.trim();
+StringRef AttrString = Feature.split("=").second.trim();
+
+if (Feature.startswith("arch=")) {
+  if (FoundArch)
+Ret.Duplicate = "arch=";
+  FoundArch = true;
+
+  if (AttrString.startswith("+")) {
+// EXTENSION like arch=+v,+zbb
+SmallVector Exts;
+AttrString.split(Exts, ",");
+for (auto Ext : Exts) {
+  if (Ext.empty())
+continue;
+
+  StringRef ExtName = Ext.substr(1);
+  std::string TargetFeature =
+  llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
+  if (!TargetFeature.empty())
+Ret.Features.push_back(Ext.front() + TargetFeature);
+  else
+Ret.Features.push_back(Ext.str());
+}
+  } else {
+// full-arch-string like arch=rv64gcv
+auto RII = llvm::RISCVISAInfo::parseArchString(
+AttrString, /* EnableExperimentalExtension */ true);
+if (!RII) {
+  consumeError(RII.takeError());
+} else {
+  std::vector FeatStrings = (*RII)->toFeatureVector();
+  for (auto FeatString : FeatStrings)
+Ret.Features.push_

[PATCH] D158624: [RISCV] Implement multiVersionSortPriority

2023-08-23 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: jobnoorman, luke, sunshaoce, VincentWu, vkmr, 
frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158624

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h


Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -114,6 +114,7 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  unsigned multiVersionSortPriority(StringRef Name) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -346,3 +346,6 @@
   bool Is64Bit = getTriple().isArch64Bit();
   llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
 }
+unsigned RISCVTargetInfo::multiVersionSortPriority(StringRef Name) const {
+  return llvm::RISCVISAInfo::getExtensionSerial(Name);
+}


Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -114,6 +114,7 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  unsigned multiVersionSortPriority(StringRef Name) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -346,3 +346,6 @@
   bool Is64Bit = getTriple().isArch64Bit();
   llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
 }
+unsigned RISCVTargetInfo::multiVersionSortPriority(StringRef Name) const {
+  return llvm::RISCVISAInfo::getExtensionSerial(Name);
+}
___
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[PATCH] D155935: [RISCV] Enable multiversion function

2023-08-23 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 552721.
BeMg added a comment.
Herald added a subscriber: sunshaoce.

Rebase and update testcase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155935/new/

https://reviews.llvm.org/D155935

Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/RISCV/riscv-fmv.c

Index: clang/test/CodeGen/RISCV/riscv-fmv.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-fmv.c
@@ -0,0 +1,106 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+__attribute__((target("arch=+v"))) void test1(void) {}
+__attribute__((target("arch=+v,+zbb"))) void test1(void) {}
+__attribute__((target("arch=+v,+zbb,+zicond1p0"))) void test1(void) {}
+__attribute__((target("arch=rv64gc"))) void test1(void) {}
+__attribute__((target("default"))) void test1(void) {}
+
+__attribute__((target("default"))) void test2(void) {}
+
+void test3() { test1(); test2(); }
+
+// CHECK-IR: $test1.resolver = comdat any
+// CHECK-IR: $test2.resolver = comdat any
+
+// CHECK-IR: @0 = private unnamed_addr constant [2 x i8] c"v\00", align 1
+// CHECK-IR: @1 = private unnamed_addr constant [6 x i8] c"v;zbb\00", align 1
+// CHECK-IR: @2 = private unnamed_addr constant [26 x i8] c"v;zbb;experimental-zicond\00", align 1
+// CHECK-IR: @3 = private unnamed_addr constant [25 x i8] c"m;a;f;d;c;zicsr;zifencei\00", align 1
+
+
+// CHECK-IR-LABEL: define dso_local void @test1.v
+// CHECK-IR-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.zbb_v
+// CHECK-IR-SAME: () #[[ATTR1:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.experimental-zicond_zbb_v
+// CHECK-IR-SAME: () #[[ATTR2:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.zifencei_zicsr_m_f_d_c_a
+// CHECK-IR-SAME: () #[[ATTR3:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1
+// CHECK-IR-SAME: () #[[ATTR4:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test2
+// CHECK-IR-SAME: () #[[ATTR4]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test3
+// CHECK-IR-SAME: () #[[ATTR4]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:call void @test1.resolver()
+// CHECK-IR-NEXT:call void @test2.resolver()
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define weak_odr void @test1.resolver() comdat {
+// CHECK-IR-NEXT:  resolver_entry:
+// CHECK-IR-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB0:[0-9]+]])
+// CHECK-IR-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK-IR:   resolver_return:
+// CHECK-IR-NEXT:musttail call void @test1.v()
+// CHECK-IR-NEXT:ret void
+// CHECK-IR:   resolver_else:
+// CHECK-IR-NEXT:[[TMP1:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB1:[0-9]+]])
+// CHECK-IR-NEXT:br i1 [[TMP1]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
+// CHECK-IR:   resolver_return1:
+// CHECK-IR-NEXT:musttail call void @test1.zbb_v()
+// CHECK-IR-NEXT:ret void
+// CHECK-IR:   resolver_else2:
+// CHECK-IR-NEXT:[[TMP2:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB2:[0-9]+]])
+// CHECK-IR-NEXT:br i1 [[TMP2]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
+// CHECK-IR:   resolver_return3:
+// CHECK-IR-NEXT:musttail call void @test1.experimental-zicond_zbb_v()
+// CHECK-IR-NEXT:ret void
+// CHECK-IR:   resolver_else4:
+// CHECK-IR-NEXT:[[TMP3:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB3:[0-9]+]])
+// CHECK-IR-NEXT:br i1 [[TMP3]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
+// CHECK-IR:   resolver_return5:
+// CHECK-IR-NEXT:musttail call void @test1.zifencei_zicsr_m_f_d_c_a()
+// CHECK-IR-NEXT:ret void
+// CHECK-IR:   resolver_else6:
+// CHECK-IR-NEXT:musttail call void @test1()
+// CHECK-IR-NEXT:ret void
+//
+//
+// CHECK-IR-LABEL: define weak_odr void @test2.resolver() comdat {
+// CHECK-IR-NEXT:  resolver_entry:
+// CHECK-IR-NEXT:musttail call void @test2()
+// CHECK-

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

2023-08-01 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 546324.
BeMg added a comment.

Use semacheck and CGBuiltin to support overload version functionY


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156221/new/

https://reviews.llvm.org/D156221

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/riscv_ntlh.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c

Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -100,6 +100,24 @@
   *scvs1 = __riscv_ntl_load(scvs2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   *scvc1 = __riscv_ntl_load(scvc2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  uc = __riscv_ntl_load(&sc);   // CHECK: load i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  sc = __riscv_ntl_load(&uc);   // CHECK: load i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  us = __riscv_ntl_load(&ss);   // CHECK: load i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  ss = __riscv_ntl_load(&us);   // CHECK: load i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  ui = __riscv_ntl_load(&si);   // CHECK: load i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  si = __riscv_ntl_load(&ui);   // CHECK: load i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  ull = __riscv_ntl_load(&sll); // CHECK: load i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  sll = __riscv_ntl_load(&ull); // CHECK: load i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  h1 = __riscv_ntl_load(&h2);   // CHECK: load half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  f1 = __riscv_ntl_load(&f2);   // CHECK: load float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  d1 = __riscv_ntl_load(&d2);   // CHECK: load double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  v4si1 = __riscv_ntl_load(&v4si2);   // CHECK: load <4 x i32>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  v8ss1 = __riscv_ntl_load(&v8ss2);   // CHECK: load <8 x i16>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  v16sc1 = __riscv_ntl_load(&v16sc2);   // CHECK: load <16 x i8>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvi1 = __riscv_ntl_load(scvi2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvs1 = __riscv_ntl_load(scvs2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvc1 = __riscv_ntl_load(scvc2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+
   __riscv_ntl_store(&uc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&sc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&us, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
@@ -172,6 +190,23 @@
   __riscv_ntl_store(scvs2, *scvs1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   __riscv_ntl_store(scvc2, *scvc1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  __riscv_ntl_store(&uc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&us, 1);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ss, 1);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ui, 1);// CHECK: store i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&si, 1);// CHECK: store i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ull, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sll, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&h1, 1.0);  // CHECK: store half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&f1, 1.0);  // CHECK: store float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&d1, 1.0);  // CHECK: store double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&v4si1, v4si2);  // CHECK: store <4 x i32>{{.*}}

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

2023-08-03 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 546753.
BeMg added a comment.

Add new line


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156221/new/

https://reviews.llvm.org/D156221

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/riscv_ntlh.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c

Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -100,6 +100,24 @@
   *scvs1 = __riscv_ntl_load(scvs2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   *scvc1 = __riscv_ntl_load(scvc2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  uc = __riscv_ntl_load(&sc);   // CHECK: load i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  sc = __riscv_ntl_load(&uc);   // CHECK: load i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  us = __riscv_ntl_load(&ss);   // CHECK: load i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  ss = __riscv_ntl_load(&us);   // CHECK: load i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  ui = __riscv_ntl_load(&si);   // CHECK: load i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  si = __riscv_ntl_load(&ui);   // CHECK: load i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  ull = __riscv_ntl_load(&sll); // CHECK: load i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  sll = __riscv_ntl_load(&ull); // CHECK: load i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  h1 = __riscv_ntl_load(&h2);   // CHECK: load half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  f1 = __riscv_ntl_load(&f2);   // CHECK: load float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  d1 = __riscv_ntl_load(&d2);   // CHECK: load double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  v4si1 = __riscv_ntl_load(&v4si2);   // CHECK: load <4 x i32>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  v8ss1 = __riscv_ntl_load(&v8ss2);   // CHECK: load <8 x i16>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  v16sc1 = __riscv_ntl_load(&v16sc2);   // CHECK: load <16 x i8>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvi1 = __riscv_ntl_load(scvi2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvs1 = __riscv_ntl_load(scvs2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvc1 = __riscv_ntl_load(scvc2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+
   __riscv_ntl_store(&uc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&sc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&us, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
@@ -172,6 +190,23 @@
   __riscv_ntl_store(scvs2, *scvs1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   __riscv_ntl_store(scvc2, *scvc1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  __riscv_ntl_store(&uc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&us, 1);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ss, 1);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ui, 1);// CHECK: store i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&si, 1);// CHECK: store i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ull, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sll, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&h1, 1.0);  // CHECK: store half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&f1, 1.0);  // CHECK: store float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&d1, 1.0);  // CHECK: store double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&v4si1, v4si2);  // CHECK: store <4 x i32>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

2023-08-04 Thread Piyou Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2df05cd01c17: [RISCV] Support overloaded version ntlh 
intrinsic function (authored by BeMg).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156221/new/

https://reviews.llvm.org/D156221

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/riscv_ntlh.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c

Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -100,6 +100,24 @@
   *scvs1 = __riscv_ntl_load(scvs2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   *scvc1 = __riscv_ntl_load(scvc2, __RISCV_NTLH_ALL);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  uc = __riscv_ntl_load(&sc);   // CHECK: load i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  sc = __riscv_ntl_load(&uc);   // CHECK: load i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  us = __riscv_ntl_load(&ss);   // CHECK: load i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  ss = __riscv_ntl_load(&us);   // CHECK: load i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  ui = __riscv_ntl_load(&si);   // CHECK: load i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  si = __riscv_ntl_load(&ui);   // CHECK: load i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  ull = __riscv_ntl_load(&sll); // CHECK: load i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  sll = __riscv_ntl_load(&ull); // CHECK: load i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  h1 = __riscv_ntl_load(&h2);   // CHECK: load half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  f1 = __riscv_ntl_load(&f2);   // CHECK: load float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  d1 = __riscv_ntl_load(&d2);   // CHECK: load double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  v4si1 = __riscv_ntl_load(&v4si2);   // CHECK: load <4 x i32>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  v8ss1 = __riscv_ntl_load(&v8ss2);   // CHECK: load <8 x i16>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  v16sc1 = __riscv_ntl_load(&v16sc2);   // CHECK: load <16 x i8>{{.*}}align 16, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvi1 = __riscv_ntl_load(scvi2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvs1 = __riscv_ntl_load(scvs2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  *scvc1 = __riscv_ntl_load(scvc2);   // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+
   __riscv_ntl_store(&uc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&sc, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
   __riscv_ntl_store(&us, 1, __RISCV_NTLH_INNERMOST_PRIVATE);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
@@ -172,6 +190,23 @@
   __riscv_ntl_store(scvs2, *scvs1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
   __riscv_ntl_store(scvc2, *scvc1, __RISCV_NTLH_ALL);  // CHECK: store {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
 
+  __riscv_ntl_store(&uc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sc, 1);// CHECK: store i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&us, 1);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ss, 1);// CHECK: store i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ui, 1);// CHECK: store i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&si, 1);// CHECK: store i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&ull, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&sll, 1);   // CHECK: store i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&h1, 1.0);  // CHECK: store half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&f1, 1.0);  // CHECK: store float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !8
+  __riscv_ntl_store(&d1, 1.0);  // CHECK: store double{{.*}}align 8, !nont

[PATCH] D151730: [RISCV] Support target attribute for function

2023-09-12 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 556544.
BeMg added a comment.

Update to lastest spec

1. When it exist the duplicate target attribute, select the lastest one.
2. arch's features will override cpu's features. TargetFeature will override 
commandline feature.
3. enhence the testcase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,55 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m -target-feature +a \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @testDefault
+// CHECK-SAME: () #0 {
+void testDefault() {}
+// CHECK-LABEL: define dso_local void @testMultiAttrStr
+// CHECK-SAME: () #1 {
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void
+testMultiAttrStr() {}
+// CHECK-LABEL: define dso_local void @testSingleExtension
+// CHECK-SAME: () #2 {
+__attribute__((target("arch=+zbb"))) void testSingleExtension() {}
+// CHECK-LABEL: define dso_local void @testMultiExtension
+// CHECK-SAME: () #3 {
+__attribute__((target("arch=+zbb,+v,+zicond"))) void testMultiExtension() {}
+// CHECK-LABEL: define dso_local void @testFullArch
+// CHECK-SAME: () #4 {
+__attribute__((target("arch=rv64gc_zbb"))) void testFullArch() {}
+// CHECK-LABEL: define dso_local void @testFullArchButSmallThanCmdArch
+// CHECK-SAME: () #5 {
+__attribute__((target("arch=rv64im"))) void testFullArchButSmallThanCmdArch() {}
+// CHECK-LABEL: define dso_local void @testAttrArchAndAttrCpu
+// CHECK-SAME: () #6 {
+__attribute__((target("cpu=sifive-u54;arch=+zbb"))) void
+testAttrArchAndAttrCpu() {}
+// CHECK-LABEL: define dso_local void @testAttrFullArchAndAttrCpu
+// CHECK-SAME: () #7 {
+__attribute__((target("cpu=sifive-u54;arch=rv64im"))) void
+testAttrFullArchAndAttrCpu() {}
+// CHECK-LABEL: define dso_local void @testAttrCpuOnly
+// CHECK-SAME: () #8 {
+__attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
+// CHECK-LABEL: define dso_local void @testMultiArchSelectLast
+// CHECK-SAME: () #4 {
+__attribute__((target("arch=rv64gc;arch=rv64gc_zbb"))) void testMultiArchSelectLast() {}
+// CHECK-LABEL: define dso_local void @testMultiCpuSelectLast
+// CHECK-SAME: () #8 {
+__attribute__((target("cpu=sifive-u74;cpu=sifive-u54"))) void testMultiCpuSelectLast() {}
+// CHECK-LABEL: define dso_local void @testMultiTuneSelectLast
+// CHECK-SAME: () #9 {
+__attribute__((target("tune=sifive-u74;tune=sifive-u54"))) void testMultiTuneSelectLast() {}
+
+//.
+// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+zifencei" }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" "tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+zbb,+zifencei" }
+// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+zbb,+zicsr,+zifencei" }
+// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m" }
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+zbb,+zifencei" }
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+zicsr,+zifencei" }
+// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+zifencei" "tune-cpu"="sifive-u54" }
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -114,6 +114,8 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  bool supportsTargetAttributeTune() const override { return true; }
+  ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -224,6 +224,21 @@
 clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
 }
 
+sta

[PATCH] D151730: [RISCV] Support target attribute for function

2023-07-12 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 539428.
BeMg added a comment.

1. simplify riscv-func-attr-target.ll
2. handle corner case in parseTargetAttr


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,46 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() "target-features"="+a,+d,+f,+m,+c,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() "target-features"="+a,+d,+f,+m,+c,+zifencei" {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test3() "target-features"="+a,+d,+f,+m,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test4() "target-features"="+a,+d,+f,+m,+experimental-zihintntl,+zifencei" {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test5() "target-features"="+a,+d,+f,+m,+zifencei" {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -36,6 +36,7 @@
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
 
@@ -46,6 +47,10 @@
 STATISTIC(RISCVNumInstrsCompressed,
   "Number of RISC-V Compressed instructions emitted");
 
+namespace llvm {
+extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
+} // namespace llvm
+
 namespace {
 class RISCVAsmPrinter : public AsmPrinter {
   const RISCVSubtarget *STI;
@@ -83,6 +88,8 @@
   void emitEndOfAsmFile(Module &M) override;
 
   void emitFunctionEntryLabel() override;
+  void emitDirectiveOptionArch();
+  bool isSameAttribute();
 
 private:
   void emitAttributes();
@@ -238,11 +245,43 @@
   return false;
 }
 
+void RISCVAsmPrinter::emitDirectiveOptionArch() {
+  RISCVTargetStreamer &RTS =
+  static_cast(*OutStreamer->getTargetStreamer());
+  SmallVector NeedEmitStdOptionArgs;
+  const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
+  for (const auto &Feature : RISCVFeatureKV) {
+if (!llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
+  continue;
+if (STI->hasFeature(Feature.Value) && !MCSTI.hasFeature(Feature.Value))
+  NeedEmitStdOptionArgs.emplace_back(RISCVOptionArchArgType::Plus,
+ Feature.Key);
+if (!STI->hasFeature(Feature.Value) && MCSTI.hasFeature(Feature.Value))
+  NeedEmitStdOptionArgs.emplace_back(RISCVOptionArchArgType::Minus,
+ Feature.Key);
+  }
+  RTS.emitDirectiveOptionArch(NeedEmitStdOptionArgs);
+}
+
+bool RISCVAsmPrinter::isSameAttribute() {
+  const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
+  return MCSTI.getFeatureBits() == STI->getFeatureBits();
+}
+
 bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   STI = &MF.getSubtarget();
+  RISCVTargetStreamer &RTS =
+  static_cast(*OutStreamer->getTargetStreamer());
+  if (!isSameAttribute()) {
+RTS.emitDirectiveOptionPush();
+emitDirectiveOptionArch();
+  }
 
   SetupMachineFunction(MF);
   emitFunctionBody();
+
+  if (!isSameAttribute())
+RTS.emitDirectiveOptionPop();
   return false;
 }
 
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,152 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei

[PATCH] D151730: [RISCV] Support target attribute for function

2023-07-12 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 539856.
BeMg added a comment.

separate the change to RISCVAsmPrinter.cpp into another patch


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,46 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() "target-features"="+a,+d,+f,+m,+c,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() "target-features"="+a,+d,+f,+m,+c,+zifencei" {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test3() "target-features"="+a,+d,+f,+m,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test4() "target-features"="+a,+d,+f,+m,+experimental-zihintntl,+zifencei" {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test5() "target-features"="+a,+d,+f,+m,+zifencei" {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,152 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d %s\
+// RUN:  -S -o - | FileCheck %s --check-prefix=CHECK-ASM
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .option arch, -a, +v, +zbb, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+// CHECK-ASM-LABEL: test1
+// CHECK-ASM: .option pop
+// CHECK-IR: void @test1() #0
+__attribute__((target("arch=-a,+v,+zbb"))) void test1() {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +c
+// CHECK-ASM-LABEL: test2
+// CHECK-ASM: .option pop
+// CHECK-IR: void @test2() #1
+__attribute__((target("arch=rv64gc"))) void test2 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +c
+// CHECK-ASM-LABEL: test3
+// CHECK-ASM: .option pop
+// CHECK-IR: void @test3() #1
+__attribute__((target("arch=+c"))) void test3 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+// CHECK-ASM-LABEL: test4
+// CHECK-ASM: .option pop
+// CHECK-IR: void @test4() #2
+__attribute__((target("arch=+v"))) void test4 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   -a, +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+// CHECK-ASM-LABEL: test5
+// CHECK-ASM: .option pop
+// CHECK-IR: void @test5() #3
+__attribute__((target("arch=-a,+v"))) void test5() {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +zbb
+// CHECK-ASM-LABEL: test6
+// CHECK-ASM: .option pop
+// CHECK-IR: void @test6() #4
+__attribute__((target("arch=rv64g_zbb"))) void test6() {}
+
+// CHECK-ASM-LABEL: test7
+// CHECK-ASM-NOT: .option pop
+// CHECK-IR: void @test7() #5
+__attribute__((target("cpu=rocket-rv64"))) void test7 () {}
+
+// CHECK-ASM-LABEL: test8
+// CHECK-ASM-NOT: .option pop
+// CHECK-IR: void @test8() #6
+__attribute__((target("tune=rocket-rv64"))) void test8 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +c
+// CHECK-ASM-LABEL: test9
+// CHECK-ASM: .option pop
+// CHECK-IR: void @test9() #7
+__attribute__((target("cpu=rocket-rv64;arch=+c"))) void test9 () {}
+
+// CHECK

[PATCH] D151730: [RISCV] Support target attribute for function

2023-07-13 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 539901.
BeMg added a comment.

Update testcase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,46 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .option arch, +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() "target-features"="+a,+d,+f,+m,+c,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" {
+; CHECK-LABEL: test1
+; CHECK: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() "target-features"="+a,+d,+f,+m,+c,+zifencei" {
+; CHECK-LABEL: test2
+; CHECK: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .option arch, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test3() "target-features"="+a,+d,+f,+m,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" {
+; CHECK-LABEL: test3
+; CHECK: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .option arch, +experimental-zihintntl, +zifencei
+define void @test4() "target-features"="+a,+d,+f,+m,+experimental-zihintntl,+zifencei" {
+; CHECK-LABEL: test4
+; CHECK: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .option arch, +zifencei
+define void @test5() "target-features"="+a,+d,+f,+m,+zifencei" {
+; CHECK-LABEL: test5
+; CHECK: .option pop
+entry:
+  ret void
+}
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+// CHECK-IR: void @test1() #0
+__attribute__((target("arch=-a,+v,+zbb,+zihintntl0p2"))) void test1() {}
+
+// CHECK-IR: void @test2() #1
+__attribute__((target("arch=rv64gc_zbb"))) void test2 () {}
+
+// CHECK-IR: void @test3() #2
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void test3 () {}
+
+// CHECK-IR: attributes #0 {{.*}}+experimental-zihintntl{{.*}}+v,+zbb{{.*}}+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a{{.*}}
+// CHECK-IR: attributes #1 {{.*}}+c{{.*}}+zbb{{.*}}
+// CHECK-IR: attributes #2 {{.*}} "target-cpu"="rocket-rv64" {{.*}}+v{{.*}} "tune-cpu"="generic-rv64" {{.*}}
\ No newline at end of file
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -109,6 +109,9 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  bool supportsTargetAttributeTune() const override { return true; }
+  bool validateCpuSupports(StringRef FeatureStr) const override;
+  ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -250,12 +250,17 @@
 
   // RISCVISAInfo makes implications for ISA features
   std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  std::vector UpdatedFeatures;
+
   // Add non-ISA features like `relax` and `save-restore` back
   for (const std::string &Feature : FeaturesVec)
 if (!llvm::is_contained(ImpliedFeatures, Feature))
-  ImpliedFeatures.push_back(Feature);
+  UpdatedFeatures.push_back(Feature);
+
+  UpdatedFeatures.insert(UpdatedFeatures.end(), ImpliedFeatures.begin(),
+ ImpliedFeatures.end());
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeatures);
 }
 
 std::optional>
@@ -346,3 +351,77 @@
   bool Is64Bit = getTriple().isArch64Bit();
   llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
 }
+
+//

[PATCH] D151730: [RISCV] Support target attribute for function

2023-07-13 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 539907.
BeMg added a comment.

Move riscv-func-attr-target.ll into D155155 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a   \
+// RUN:  -target-feature +f -target-feature +d   \
+// RUN:  -emit-llvm %s -o - | FileCheck %s   \
+// RUN:  --check-prefix=CHECK-IR
+
+// CHECK-IR: void @test1() #0
+__attribute__((target("arch=-a,+v,+zbb,+zihintntl0p2"))) void test1() {}
+
+// CHECK-IR: void @test2() #1
+__attribute__((target("arch=rv64gc_zbb"))) void test2 () {}
+
+// CHECK-IR: void @test3() #2
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void test3 () {}
+
+// CHECK-IR: attributes #0 {{.*}}+experimental-zihintntl{{.*}}+v,+zbb{{.*}}+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a{{.*}}
+// CHECK-IR: attributes #1 {{.*}}+c{{.*}}+zbb{{.*}}
+// CHECK-IR: attributes #2 {{.*}} "target-cpu"="rocket-rv64" {{.*}}+v{{.*}} "tune-cpu"="generic-rv64" {{.*}}
\ No newline at end of file
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -109,6 +109,9 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
+  bool supportsTargetAttributeTune() const override { return true; }
+  bool validateCpuSupports(StringRef FeatureStr) const override;
+  ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -250,12 +250,17 @@
 
   // RISCVISAInfo makes implications for ISA features
   std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  std::vector UpdatedFeatures;
+
   // Add non-ISA features like `relax` and `save-restore` back
   for (const std::string &Feature : FeaturesVec)
 if (!llvm::is_contained(ImpliedFeatures, Feature))
-  ImpliedFeatures.push_back(Feature);
+  UpdatedFeatures.push_back(Feature);
+
+  UpdatedFeatures.insert(UpdatedFeatures.end(), ImpliedFeatures.begin(),
+ ImpliedFeatures.end());
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeatures);
 }
 
 std::optional>
@@ -346,3 +351,77 @@
   bool Is64Bit = getTriple().isArch64Bit();
   llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
 }
+
+// Parse RISC-V Target attributes, which are a comma separated list of:
+//  "arch=" - parsed to features as per -march=..
+//  "cpu=" - parsed to features as per -mcpu=.., with CPU set to 
+//  "tune=" - TuneCPU set to 
+ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
+  ParsedTargetAttr Ret;
+  if (Features == "default")
+return Ret;
+  SmallVector AttrFeatures;
+  Features.split(AttrFeatures, ";");
+  bool FoundArch = false;
+
+  for (auto &Feature : AttrFeatures) {
+Feature = Feature.trim();
+StringRef AttrString = Feature.split("=").second.trim();
+
+if (Feature.startswith("arch=")) {
+  if (FoundArch)
+Ret.Duplicate = "arch=";
+  FoundArch = true;
+
+  if (AttrString.startswith("+") || AttrString.startswith("-")) {
+// EXTENSION like arch=+v,+zbb,-c
+SmallVector Exts;
+AttrString.split(Exts, ",");
+for (auto Ext : Exts) {
+  if (Ext.empty())
+continue;
+
+  StringRef ExtName = Ext.substr(1);
+  std::string TargetFeature =
+  llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
+  if (!TargetFeature.empty())
+Ret.Features.push_back(Ext.front() + TargetFeature);
+  else
+Ret.Features.push_back(Ext.str());
+}
+  } else {
+// full-arch-string like arch=rv64gcv
+auto RII = llvm::RISCVISAInfo::parseArchString(
+AttrString, /* EnableExperimentalExtension */ true);
+if (!RII) {
+  consumeError(RII.takeError());
+} else {
+  std::vector FeatStrings = (*RI

[PATCH] D159174: [clang] Use stable_sort in AppendTargetMangling

2023-08-30 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added a subscriber: mgrang.
Herald added a project: All.
BeMg requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

For the target features in the same priority, make sure it is not a random 
mangling name.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159174

Files:
  clang/lib/CodeGen/CodeGenModule.cpp


Index: clang/lib/CodeGen/CodeGenModule.cpp
===
--- clang/lib/CodeGen/CodeGenModule.cpp
+++ clang/lib/CodeGen/CodeGenModule.cpp
@@ -1627,7 +1627,7 @@
   Out << '.';
   const TargetInfo &Target = CGM.getTarget();
   ParsedTargetAttr Info = Target.parseTargetAttr(Attr->getFeaturesStr());
-  llvm::sort(Info.Features, [&Target](StringRef LHS, StringRef RHS) {
+  llvm::stable_sort(Info.Features, [&Target](StringRef LHS, StringRef RHS) {
 // Multiversioning doesn't allow "no-${feature}", so we can
 // only have "+" prefixes here.
 assert(LHS.startswith("+") && RHS.startswith("+") &&


Index: clang/lib/CodeGen/CodeGenModule.cpp
===
--- clang/lib/CodeGen/CodeGenModule.cpp
+++ clang/lib/CodeGen/CodeGenModule.cpp
@@ -1627,7 +1627,7 @@
   Out << '.';
   const TargetInfo &Target = CGM.getTarget();
   ParsedTargetAttr Info = Target.parseTargetAttr(Attr->getFeaturesStr());
-  llvm::sort(Info.Features, [&Target](StringRef LHS, StringRef RHS) {
+  llvm::stable_sort(Info.Features, [&Target](StringRef LHS, StringRef RHS) {
 // Multiversioning doesn't allow "no-${feature}", so we can
 // only have "+" prefixes here.
 assert(LHS.startswith("+") && RHS.startswith("+") &&
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[PATCH] D159174: [Clang] Use stable_sort in AppendTargetMangling

2023-09-01 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added a comment.

Thanks for the review.

I'm working on RISC-V FMV support, and we found the large set of extension 
features is hard to maintain the priority that doesn't collision at all.

Lack the appropriate priority, it will generate the random mangling name. The 
predictable mangling name is convenient for testing.

This goal could also be achieved by giving the serial number for each feature, 
but I think the stable sort approach is simpler.


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[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

2023-03-29 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 509244.
BeMg edited the summary of this revision.
BeMg added a comment.
Herald added a subscriber: jobnoorman.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_ntlh.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td

Index: llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td
@@ -11,12 +11,24 @@
 ///
 //===--===//
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 4 in {
-  def PseudoNTLALL :  Pseudo<(outs), (ins), [], "ntl.all">, 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 4, isCodeGenOnly = 1 in {
+  def PseudoNTLP1   :  Pseudo<(outs), (ins), [], "ntl.p1">, 
+ PseudoInstExpansion<(ADD X0, X0, X2)>;
+  def PseudoNTLPALL :  Pseudo<(outs), (ins), [], "ntl.pall">, 
+ PseudoInstExpansion<(ADD X0, X0, X3)>;
+  def PseudoNTLS1   :  Pseudo<(outs), (ins), [], "ntl.s1">, 
+ PseudoInstExpansion<(ADD X0, X0, X4)>;
+  def PseudoNTLALL  :  Pseudo<(outs), (ins), [], "ntl.all">, 
  PseudoInstExpansion<(ADD X0, X0, X5)>;
 }
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 2 in {
-  def PseudoCNTLALL :  Pseudo<(outs), (ins), [], "c.ntl.all">,
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 2, isCodeGenOnly = 1 in {
+  def PseudoCNTLP1   :  Pseudo<(outs), (ins), [], "c.ntl.p1">,
+  PseudoInstExpansion<(C_ADD_HINT X0, X0, X2)>;
+  def PseudoCNTLPALL :  Pseudo<(outs), (ins), [], "c.ntl.pall">,
+  PseudoInstExpansion<(C_ADD_HINT X0, X0, X3)>;
+  def PseudoCNTLS1   :  Pseudo<(outs), (ins), [], "c.ntl.s1">,
+  PseudoInstExpansion<(C_ADD_HINT X0, X0, X4)>;
+  def PseudoCNTLALL  :  Pseudo<(outs), (ins), [], "c.ntl.all">,
   PseudoInstExpansion<(C_ADD_HINT X0, X0, X5)>;
 }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.h
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -25,6 +25,11 @@
 
 class RISCVSubtarget;
 
+static const MachineMemOperand::Flags MONontemporalBit0 =
+MachineMemOperand::MOTargetFlag1;
+static const MachineMemOperand::Flags MONontemporalBit1 =
+MachineMemOperand::MOTargetFlag2;
+
 namespace RISCVCC {
 
 enum CondCode {
@@ -238,6 +243,9 @@
 return hasAllNBitUsers(MI, MRI, 32);
   }
 
+  ArrayRef>
+  getSerializableMachineMemOperandTargetFlags() const override;
+
 protected:
   const RISCVSubtarget &STI;
 };
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2848,6 +2848,14 @@
   return true;
 }
 
+ArrayRef>
+RISCVInstrInfo::getSerializableMachineMemOperandTargetFlags() const {
+  static const std::pair TargetFlags[] =
+  {{MONontemporalBit0, "riscv-non-temporal-domain-bit-0"},
+   {MONontemporalBit1, "riscv-non-temporal-domain-bit-1"}};
+  return makeArrayRef(TargetFlags);
+}
+
 // Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
 bool RISCV::isSEXT_W(const MachineInstr &MI) {
   return MI.getOpcode() == RISCV::ADDIW && MI.getOperand(1).isReg() &&
Index: llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp
===
--- llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp
@@ -67,11 +67,27 @@
 continue;
   MachineMemOperand *MMO = *(MBBI.memoperands_begin());
   if (MMO->isNonTemporal()) {
+uint64_t NontemporalMode = 0;
+if (MMO->getFlags() & MONontemporalBit0)
+  NontemporalMode += 0b1;
+if (MMO->getFlags() & MONontemporalBit1)
+  NontemporalMode += 0b10;
+
+static const uint16_t NTLOpc[] = {
+RISCV::PseudoNTLP1, RISCV::PseudoNTLPALL, RISCV::PseudoNTLS1,
+RISCV::PseudoNTLALL};
+static const uint16_t CNTLOpc[] = {
+RISCV::PseudoCNTLP1,

[PATCH] D151730: [RISCV] Support target attribute for function

2023-06-25 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 534428.
BeMg added a comment.

1. Attrstring -> AttrString
2. using StringRef instead of string
3. Append unsupported target feature Let follow-up procedure raise diagnostic 
code


Repository:
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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,81 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() #0 {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() #1 {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test3() #1 {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test4() #2 {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test5() #3 {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test7() #4 {
+; CHECK-LABEL: test7
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test9() #6 {
+; CHECK-LABEL: test9
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test10() #7 {
+; CHECK-LABEL: test10
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #1 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zicsr,+zifencei,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihi

[PATCH] D151730: [RISCV] Support target attribute for function

2023-06-27 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 535191.
BeMg marked 8 inline comments as done.
BeMg added a comment.

Add const


Repository:
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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,81 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() #0 {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() #1 {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test3() #1 {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test4() #2 {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test5() #3 {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test7() #4 {
+; CHECK-LABEL: test7
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test9() #6 {
+; CHECK-LABEL: test9
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test10() #7 {
+; CHECK-LABEL: test10
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #1 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zicsr,+zifencei,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d

[PATCH] D151730: [RISCV] Support target attribute for function

2023-06-28 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:385
+  StringRef ExtName = Ext.substr(1);
+  if (llvm::RISCVISAInfo::isSupportedExtensionWithVersion(ExtName) ||
+  llvm::RISCVISAInfo::isSupportedExtension(ExtName))

craig.topper wrote:
> craig.topper wrote:
> > I wonder if we could encapsulate this `if` and the 3 calls into 
> > RISCVISAInfo into a single function in RISCVISAInfo?
> > 
> > Basically we want to know if an extension that may or may not have a 
> > version, is a valid extension and if so what is the target feature name for 
> > it. We could have one function that does all that and returns the target 
> > feature name or an empty string.
> I think I explained my idea poorly. I was wondering about having a function 
> that allowed us to write
> 
> ```
> std::string TargetFeature = 
> llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
> if (!TargetFeature.empty())
>   Ret.Features.push_back(Ext.front() + TargetFeature);
> else
>   Ret.Features.push_back(Ext.str());
> ```
Thank you for further explanation. I think getTargetFeatureFromOneExt can do 
this job.

```
std::string TargetFeature = 
llvm::RISCVISAInfo::getTargetFeatureFromOneExt(ExtName);
if (!TargetFeature.empty())
Ret.Features.push_back(Ext.front() + TargetFeature);
else
Ret.Features.push_back(Ext.str());
```




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[PATCH] D151730: [RISCV] Support target attribute for function

2023-06-29 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 535653.
BeMg added a comment.

Use getTargetFeatureForExtension instead of isSupportExtension


Repository:
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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,81 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() #0 {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() #1 {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test3() #1 {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test4() #2 {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test5() #3 {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test7() #4 {
+; CHECK-LABEL: test7
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test9() #6 {
+; CHECK-LABEL: test9
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test10() #7 {
+; CHECK-LABEL: test10
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #1 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zicsr,+zifencei,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-

[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

2023-04-11 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added a comment.

  test_nontemporal_load_v16i8
  test_nontemporal_load_v8i16

These two test cases in nontemporal.ll are affected by 
`areTwoSDNodeTargetMMOFlagsMergeable`.
Does we need extra testcases for `areTwoSDNodeTargetMMOFlagsMergeable`?


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[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

2023-04-17 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c:19
+typedef signed short v8ss __attribute__((vector_size(16)));
+typedef signed char v16sc __attribute__((vector_size(16)));
+v4si v4si1, v4si2;

craig.topper wrote:
> What about the rvv builtin types for scalable vectors?
Should we support rvv builtin types for __riscv_ntl_load/store although we 
already have plan to support RVV builtin type in nontemporal by extra RVV 
intrinsic functions?

It need some extra code to support these function with scalable vector type. 


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[PATCH] D151730: [RISCV] Support target attribute for function

2023-05-30 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
hiraditya, arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151730

Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -34,6 +34,7 @@
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
 
@@ -44,6 +45,10 @@
 STATISTIC(RISCVNumInstrsCompressed,
   "Number of RISC-V Compressed instructions emitted");
 
+namespace llvm {
+extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
+} // namespace llvm
+
 namespace {
 class RISCVAsmPrinter : public AsmPrinter {
   const RISCVSubtarget *STI;
@@ -82,6 +87,8 @@
   void emitEndOfAsmFile(Module &M) override;
 
   void emitFunctionEntryLabel() override;
+  void emitDirectiveOptionArch();
+  bool isSameAttribute();
 
 private:
   void emitAttributes();
@@ -232,11 +239,44 @@
   return false;
 }
 
+void RISCVAsmPrinter::emitDirectiveOptionArch() {
+  RISCVTargetStreamer &RTS =
+  static_cast(*OutStreamer->getTargetStreamer());
+  std::vector NeedEmitStdOption;
+  const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
+  for (auto Feature : RISCVFeatureKV) {
+if (STI->hasFeature(Feature.Value) && !MCSTI.hasFeature(Feature.Value) &&
+llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
+  NeedEmitStdOption.push_back(Feature.Key);
+  }
+
+  bool PrefixEmitted = false;
+  unsigned NeedEmitStdOptionSize = NeedEmitStdOption.size();
+  for (unsigned i = 0; i < NeedEmitStdOptionSize; i++) {
+RTS.emitDirectiveOptionArchPlus(NeedEmitStdOption[i], PrefixEmitted,
+i < NeedEmitStdOptionSize - 1);
+  }
+}
+
+bool RISCVAsmPrinter::isSameAttribute() {
+  const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
+  return MCSTI.getFeatureBits() == STI->getFeatureBits();
+}
+
 bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   STI = &MF.getSubtarget();
+  RISCVTargetStreamer &RTS =
+  static_cast(*OutStreamer->getTargetStreamer());
+  if (!isSameAttribute()) {
+RTS.emitDirectiveOptionPush();
+emitDirectiveOptionArch();
+  }
 
   SetupMachineFunction(MF);
   emitFunctionBody();
+
+  if (!isSameAttribute())
+RTS.emitDirectiveOptionPop();
   return false;
 }
 
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,35 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang -target riscv64 -march=rv64g -S %s -o - | FileCheck %s
+
+// clang-format off
+// CHECK: .option push
+// CHECK-NEXT: .optionarch,   +c, +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+// CHECK-LABEL: test1
+// CHECK: .option pop
+__attribute__((target("arch=rv64g+c+v"))) void test1 () {}
+
+// CHECK: .option push
+// CHECK-NEXT: .optionarch,   +c
+// CHECK-LABEL: test2
+// CHECK: .option pop
+__attribute__((target("arch=rv64gc"))) void test2 () {}
+
+// CHECK: .option push
+// CHECK-NEXT: .optionarch,   +c
+// CHECK-LABEL: test3
+// CHECK: .option pop
+__attribute__((target("arch=+c"))) void test3 () {}
+
+// CHECK: .option push
+// CHECK-NEXT: .optionarch,   +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+// CHECK-LABEL: test4
+// CHECK: .option pop
+__attribute__((target("arch=+v"))) void test4 () {}
+
+// CHECK: .option push
+// CHECK-NEXT: .optionarch,   +experimental-zihintntl
+// CHECK-LABEL: test5
+// CHECK: .option pop
+__attribute__((target("arch=+experimental-zihintntl"))) void test5 () {}
+
+// clang-format on
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -109,6 +109,8 @@
   void fillValidCPUList(SmallVectorImpl &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void f

[PATCH] D151730: [WIP][RISCV] Support target attribute for function

2023-05-31 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 526988.
BeMg added a comment.

update


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -34,6 +34,7 @@
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
 
@@ -44,6 +45,10 @@
 STATISTIC(RISCVNumInstrsCompressed,
   "Number of RISC-V Compressed instructions emitted");
 
+namespace llvm {
+extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
+} // namespace llvm
+
 namespace {
 class RISCVAsmPrinter : public AsmPrinter {
   const RISCVSubtarget *STI;
@@ -82,6 +87,8 @@
   void emitEndOfAsmFile(Module &M) override;
 
   void emitFunctionEntryLabel() override;
+  void emitDirectiveOptionArch();
+  bool isSameAttribute();
 
 private:
   void emitAttributes();
@@ -232,11 +239,44 @@
   return false;
 }
 
+void RISCVAsmPrinter::emitDirectiveOptionArch() {
+  RISCVTargetStreamer &RTS =
+  static_cast(*OutStreamer->getTargetStreamer());
+  std::vector NeedEmitStdOption;
+  const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
+  for (auto Feature : RISCVFeatureKV) {
+if (STI->hasFeature(Feature.Value) && !MCSTI.hasFeature(Feature.Value) &&
+llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
+  NeedEmitStdOption.push_back(Feature.Key);
+  }
+
+  bool PrefixEmitted = false;
+  unsigned NeedEmitStdOptionSize = NeedEmitStdOption.size();
+  for (unsigned i = 0; i < NeedEmitStdOptionSize; i++) {
+RTS.emitDirectiveOptionArchPlus(NeedEmitStdOption[i], PrefixEmitted,
+i < NeedEmitStdOptionSize - 1);
+  }
+}
+
+bool RISCVAsmPrinter::isSameAttribute() {
+  const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
+  return MCSTI.getFeatureBits() == STI->getFeatureBits();
+}
+
 bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   STI = &MF.getSubtarget();
+  RISCVTargetStreamer &RTS =
+  static_cast(*OutStreamer->getTargetStreamer());
+  if (!isSameAttribute()) {
+RTS.emitDirectiveOptionPush();
+emitDirectiveOptionArch();
+  }
 
   SetupMachineFunction(MF);
   emitFunctionBody();
+
+  if (!isSameAttribute())
+RTS.emitDirectiveOptionPop();
   return false;
 }
 
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,114 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang -target riscv64 -march=rv64g -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM
+// RUN: %clang -target riscv64 -march=rv64g -emit-llvm -S %s -o - | FileCheck %s --check-prefix=CHECK-IR
+
+// clang-format off
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +c, +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+// CHECK-ASM-LABEL: test1
+// CHECK-ASM: .option pop
+__attribute__((target("arch=rv64g,+c,+v"))) void test1 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +c
+// CHECK-ASM-LABEL: test2
+// CHECK-ASM: .option pop
+__attribute__((target("arch=rv64gc"))) void test2 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +c
+// CHECK-ASM-LABEL: test3
+// CHECK-ASM: .option pop
+__attribute__((target("arch=+c"))) void test3 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+// CHECK-ASM-LABEL: test4
+// CHECK-ASM: .option pop
+__attribute__((target("arch=+v"))) void test4 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +experimental-zihintntl
+// CHECK-ASM-LABEL: test5
+// CHECK-ASM: .option pop
+__attribute__((target("arch=+experimental-zihintntl"))) void test5 () {}
+
+// CHECK-ASM-LABEL: test7
+// CHECK-ASM-NOT: .option pop
+// CHECK-IR: void @test7() #4 
+__attribute__((target("cpu=rocket-rv64"))) void test7 () {}
+
+// CHECK-ASM-LABEL: test8
+// CHECK-ASM-NOT: .option pop
+// CHECK-IR: void @test8() #5
+__attribute__((target("tune=rocket-rv64"))) void test8 () {}
+
+// CHECK-ASM: .option push
+// CHECK-ASM-NEXT: .optionarch,   +c
+// CHECK-ASM-LABEL: test9
+// CHECK-ASM: .option pop
+// CHECK-IR: void @test9() #6
+__attribute__((target("cpu=rocket-rv64,arch=+c"))) void test9 () {}
+
+// CHECK-AS

[PATCH] D151730: [RISCV] Support target attribute for function

2023-06-01 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 527748.
BeMg added a comment.

1. Update RTS's function name
2. Add backend testcase


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,81 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() #0 {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() #1 {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test3() #1 {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test4() #2 {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test5() #3 {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test7() #4 {
+; CHECK-LABEL: test7
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test9() #6 {
+; CHECK-LABEL: test9
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test10() #7 {
+; CHECK-LABEL: test10
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #1 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zicsr,+zifencei,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-z

[PATCH] D149126: [RISCV][NFC] skip non-RISCV target test riscv32-zihintntl.c

2023-04-24 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149126

Files:
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c


Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature 
+experimental-zihintntl -emit-llvm %s -o - \
 // RUN: | FileCheck %s
 


Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature +experimental-zihintntl -emit-llvm %s -o - \
 // RUN: | FileCheck %s
 
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[PATCH] D149126: [RISCV][NFC] skip non-RISCV target test riscv32-zihintntl.c

2023-04-24 Thread Piyou Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdc72e8fe6758: [RISCV][NFC] skip non-RISCV target test 
riscv32-zihintntl.c (authored by BeMg).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149126/new/

https://reviews.llvm.org/D149126

Files:
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c


Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature 
+experimental-zihintntl -emit-llvm %s -o - \
 // RUN: | FileCheck %s
 


Index: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
===
--- clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature +experimental-zihintntl -emit-llvm %s -o - \
 // RUN: | FileCheck %s
 
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[PATCH] D151730: [RISCV] Support target attribute for function

2023-06-05 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 528390.
BeMg added a comment.

1. Update testcase
2. Support -
3. Verfy extension version


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,81 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() #0 {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() #1 {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test3() #1 {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test4() #2 {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test5() #3 {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test7() #4 {
+; CHECK-LABEL: test7
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test9() #6 {
+; CHECK-LABEL: test9
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test10() #7 {
+; CHECK-LABEL: test10
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #1 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zicsr,+zifencei,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-z

[PATCH] D151730: [RISCV] Support target attribute for function

2023-06-07 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 529510.
BeMg added a comment.

Use isSupportedExtensionWithVersion to implement parseTargetAttr


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,81 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() #0 {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() #1 {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test3() #1 {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test4() #2 {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test5() #3 {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test7() #4 {
+; CHECK-LABEL: test7
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test9() #6 {
+; CHECK-LABEL: test9
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test10() #7 {
+; CHECK-LABEL: test10
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #1 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zicsr,+zifencei,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-

[PATCH] D151730: [RISCV] Support target attribute for function

2023-06-09 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 529906.
BeMg added a comment.

1. Update testcase
2. Remove supportsMultiVersioning for RISCV


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-func-attr-target.c
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll

Index: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll
@@ -0,0 +1,81 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a,+d,+f,+m -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() #0 {
+; CHECK-LABEL: test1
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test2() #1 {
+; CHECK-LABEL: test2
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test3() #1 {
+; CHECK-LABEL: test3
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test4() #2 {
+; CHECK-LABEL: test4
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +experimental-zihintntl, +zifencei
+define void @test5() #3 {
+; CHECK-LABEL: test5
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +zifencei
+define void @test7() #4 {
+; CHECK-LABEL: test7
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +zifencei
+define void @test9() #6 {
+; CHECK-LABEL: test9
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+; CHECK: .option push
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test10() #7 {
+; CHECK-LABEL: test10
+; CHECL: .option pop
+entry:
+  ret void
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #1 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zicsr,+zifencei,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

2022-12-13 Thread Piyou Chen via Phabricator via cfe-commits

BeMg created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
BeMg requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139995

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -164,8 +164,7 @@
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
   // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (RVVI->getDefaultPolicy() != Policy::TU &&
-  RVVI->getDefaultPolicy() != Policy::TUMU && !RVVI->hasPassthruOperand() &&
+  if (RVVI->getDefaultPolicyBits() != 0 && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
 
@@ -193,11 +192,11 @@
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
   " DefaultPolicy));\n";
   if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -207,7 +206,7 @@
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
 "DefaultPolicy));\n";
 else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy() == Policy::TA)
+ RVVI->getDefaultPolicy().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -527,7 +526,11 @@
 unsigned NF = R->getValueAsInt("NF");
 
 // If unmasked builtin supports policy, they should be TU or TA.
-SmallVector SupportedUnMaskedPolicies = {Policy::TU, Policy::TA};
+llvm::SmallVector SupportedUnMaskedPolicies;
+SupportedUnMaskedPolicies.push_back(
+Policy(true, false, false, false)); // TU
+SupportedUnMaskedPolicies.push_back(
+Policy(false, true, false, false)); // TA
 SmallVector SupportedMaskedPolicies =
 RVVIntrinsic::getSupportedMaskedPolicies(HasTailPolicy, HasMaskPolicy);
 
@@ -544,10 +547,10 @@
 auto Prototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme);
+UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme);
+IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -569,7 +572,7 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
@@ -596,7 +599,7 @@
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
 SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -914,30 +914,22 @@
   SmallVec

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

2022-12-14 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 483068.
BeMg added a comment.

1. Update policy constructor
2. use emplace_back
3. Fix miss WithoutIntrinsicMU in policy equal check


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139995/new/

https://reviews.llvm.org/D139995

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -164,8 +164,7 @@
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
   // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (RVVI->getDefaultPolicy() != Policy::TU &&
-  RVVI->getDefaultPolicy() != Policy::TUMU && !RVVI->hasPassthruOperand() &&
+  if (RVVI->getDefaultPolicyBits() != 0 && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
 
@@ -193,11 +192,11 @@
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
   " DefaultPolicy));\n";
   if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -207,7 +206,7 @@
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
 "DefaultPolicy));\n";
 else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy() == Policy::TA)
+ RVVI->getDefaultPolicy().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -527,7 +526,11 @@
 unsigned NF = R->getValueAsInt("NF");
 
 // If unmasked builtin supports policy, they should be TU or TA.
-SmallVector SupportedUnMaskedPolicies = {Policy::TU, Policy::TA};
+llvm::SmallVector SupportedUnMaskedPolicies;
+SupportedUnMaskedPolicies.emplace_back(
+Policy(true, false, false, false)); // TU
+SupportedUnMaskedPolicies.emplace_back(
+Policy(false, true, false, false)); // TA
 SmallVector SupportedMaskedPolicies =
 RVVIntrinsic::getSupportedMaskedPolicies(HasTailPolicy, HasMaskPolicy);
 
@@ -544,10 +547,10 @@
 auto Prototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme);
+UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme);
+IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -569,7 +572,7 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
@@ -596,7 +599,7 @@
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
 SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -914,30 +914,22 @@
   SmallVector NewPrototype(Prototype.begin(),
 Prototype.end());
   // Update DefaultPolicy if need (TA or TAMA) for compute builtin types.
-  switch (DefaultPolicy) {
-  case Policy::MA:
-DefaultPolicy = Policy::TAMA;
-break;
-  cas

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

2022-12-14 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:140
+// Just for maintain the old order for quick test.
+return std::tie(this->MU, this->MA, this->TA, this->TU) <
+   std::tie(Other.MU, Other.MA, Other.TA, Other.TU);

craig.topper wrote:
> Does this need to include PolicyNone and IntrinsicWithoutMU?
In updateNamesAndPolicy, Policy will be reduce as follow

PolicyNone -> TUMU or TA or TU according to function argument
TUM -> TUMA
TAM -> TAMA
MU -> TAMU
MA -> TAMA 

For comparing the order of Policy, (PolicyNone TUM TAM MU MA) doesn't matter. 


Repository:
  rG LLVM Github Monorepo

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[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

2022-12-14 Thread Piyou Chen via Phabricator via cfe-commits

BeMg added inline comments.



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:105
+  : TU(_TU), TA(_TA), MU(_MU), MA(_MA) {}
+  Policy(bool _TU, bool _TA, bool _MU, bool _MA, bool _IntrinsicWithoutMU)
+  : TU(_TU), TA(_TA), MU(_MU), MA(_MA),

craig.topper wrote:
> You can unify the two constructors by adding `= false` after 
> `_IntrinsicWithoutMU`
Done



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:133
+return this->PolicyNone == Other.PolicyNone && this->TU == Other.TU &&
+   this->TA == Other.TA && this->MU == Other.MU && this->MA == 
Other.MA;
+  }

craig.topper wrote:
> This is missing `IntrinsicWithoutMU`
Done.



Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:211
+llvm::SmallVector SupportedUnMaskedPolicies;
+SupportedUnMaskedPolicies.push_back(
+Policy(true, false, false, false)); // TU

craig.topper wrote:
> Use emplace_back
Done



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:530
+llvm::SmallVector SupportedUnMaskedPolicies;
+SupportedUnMaskedPolicies.push_back(
+Policy(true, false, false, false)); // TU

craig.topper wrote:
> emplace_back
Done


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[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

2022-12-15 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 483414.
BeMg added a comment.

1. Remove this->
2. Remove Policy() in struct declarationx


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139995/new/

https://reviews.llvm.org/D139995

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -164,8 +164,7 @@
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
   // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (RVVI->getDefaultPolicy() != Policy::TU &&
-  RVVI->getDefaultPolicy() != Policy::TUMU && !RVVI->hasPassthruOperand() &&
+  if (RVVI->getDefaultPolicyBits() != 0 && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
 
@@ -193,11 +192,11 @@
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
   " DefaultPolicy));\n";
   if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -207,7 +206,7 @@
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
 "DefaultPolicy));\n";
 else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy() == Policy::TA)
+ RVVI->getDefaultPolicy().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -527,7 +526,11 @@
 unsigned NF = R->getValueAsInt("NF");
 
 // If unmasked builtin supports policy, they should be TU or TA.
-SmallVector SupportedUnMaskedPolicies = {Policy::TU, Policy::TA};
+llvm::SmallVector SupportedUnMaskedPolicies;
+SupportedUnMaskedPolicies.emplace_back(
+Policy(true, false, false, false)); // TU
+SupportedUnMaskedPolicies.emplace_back(
+Policy(false, true, false, false)); // TA
 SmallVector SupportedMaskedPolicies =
 RVVIntrinsic::getSupportedMaskedPolicies(HasTailPolicy, HasMaskPolicy);
 
@@ -544,10 +547,10 @@
 auto Prototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme);
+UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme);
+IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -569,7 +572,7 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
@@ -596,7 +599,7 @@
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
 SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -914,30 +914,22 @@
   SmallVector NewPrototype(Prototype.begin(),
 Prototype.end());
   // Update DefaultPolicy if need (TA or TAMA) for compute builtin types.
-  switch (DefaultPolicy) {
-  case Policy::MA:
-DefaultPolicy = Policy::TAMA;
-break;
-  case Policy::TAM:
-DefaultPolicy = Policy:

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

2022-12-16 Thread Piyou Chen via Phabricator via cfe-commits

BeMg updated this revision to Diff 483707.
BeMg added a comment.

1. Use Undisturbed, Agnostic and Omit to represent Tail and Mask
2. Replace getDefaultPolicyBits != 0 with !RVVI->isTUPolicy() && 
!RVVI->isTUMUPolicy()
3. Use llvm_unreachable


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139995/new/

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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -164,8 +164,8 @@
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
   // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (RVVI->getDefaultPolicy() != Policy::TU &&
-  RVVI->getDefaultPolicy() != Policy::TUMU && !RVVI->hasPassthruOperand() &&
+  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
+  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
 OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
 
@@ -193,11 +193,11 @@
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
   " DefaultPolicy));\n";
   if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy() == Policy::TAMA)
+  RVVI->getDefaultPolicy().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -207,7 +207,7 @@
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
 "DefaultPolicy));\n";
 else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy() == Policy::TA)
+ RVVI->getDefaultPolicy().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -527,7 +527,11 @@
 unsigned NF = R->getValueAsInt("NF");
 
 // If unmasked builtin supports policy, they should be TU or TA.
-SmallVector SupportedUnMaskedPolicies = {Policy::TU, Policy::TA};
+llvm::SmallVector SupportedUnMaskedPolicies;
+SupportedUnMaskedPolicies.emplace_back(Policy(
+Policy::PolicyType::Undisturbed, Policy::PolicyType::Omit)); // TU
+SupportedUnMaskedPolicies.emplace_back(
+Policy(Policy::PolicyType::Agnostic, Policy::PolicyType::Omit)); // TA
 SmallVector SupportedMaskedPolicies =
 RVVIntrinsic::getSupportedMaskedPolicies(HasTailPolicy, HasMaskPolicy);
 
@@ -544,10 +548,10 @@
 auto Prototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme);
+UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme);
+IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -569,7 +573,7 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
@@ -596,7 +600,7 @@
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
 SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
 MaskTypes.value(), IntrinsicTypes, RequiredFeatures, NF,
-Policy::PolicyNone, IsPrototypeDefaultTU));
+Policy(), IsPrototypeDefaultTU));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -914,30 +914,22 @@
   SmallVector NewPrototype(Prototype.begin(),
 Pr

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