BeMg updated this revision to Diff 539907.
BeMg added a comment.
Move riscv-func-attr-target.ll into D155155 <https://reviews.llvm.org/D155155>
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151730/new/
https://reviews.llvm.org/D151730
Files:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/test/CodeGen/RISCV/riscv-func-attr-target.c
Index: clang/test/CodeGen/RISCV/riscv-func-attr-target.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN: -target-feature +m -target-feature +a \
+// RUN: -target-feature +f -target-feature +d \
+// RUN: -emit-llvm %s -o - | FileCheck %s \
+// RUN: --check-prefix=CHECK-IR
+
+// CHECK-IR: void @test1() #0
+__attribute__((target("arch=-a,+v,+zbb,+zihintntl0p2"))) void test1() {}
+
+// CHECK-IR: void @test2() #1
+__attribute__((target("arch=rv64gc_zbb"))) void test2 () {}
+
+// CHECK-IR: void @test3() #2
+__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void test3 () {}
+
+// CHECK-IR: attributes #0 {{.*}}+experimental-zihintntl{{.*}}+v,+zbb{{.*}}+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a{{.*}}
+// CHECK-IR: attributes #1 {{.*}}+c{{.*}}+zbb{{.*}}
+// CHECK-IR: attributes #2 {{.*}} "target-cpu"="rocket-rv64" {{.*}}+v{{.*}} "tune-cpu"="generic-rv64" {{.*}}
\ No newline at end of file
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -109,6 +109,9 @@
void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
bool isValidTuneCPUName(StringRef Name) const override;
void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
+ bool supportsTargetAttributeTune() const override { return true; }
+ bool validateCpuSupports(StringRef FeatureStr) const override;
+ ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
};
class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
public:
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -250,12 +250,17 @@
// RISCVISAInfo makes implications for ISA features
std::vector<std::string> ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector<std::string> UpdatedFeatures;
+
// Add non-ISA features like `relax` and `save-restore` back
for (const std::string &Feature : FeaturesVec)
if (!llvm::is_contained(ImpliedFeatures, Feature))
- ImpliedFeatures.push_back(Feature);
+ UpdatedFeatures.push_back(Feature);
+
+ UpdatedFeatures.insert(UpdatedFeatures.end(), ImpliedFeatures.begin(),
+ ImpliedFeatures.end());
- return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
+ return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeatures);
}
std::optional<std::pair<unsigned, unsigned>>
@@ -346,3 +351,77 @@
bool Is64Bit = getTriple().isArch64Bit();
llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
}
+
+// Parse RISC-V Target attributes, which are a comma separated list of:
+// "arch=<arch>" - parsed to features as per -march=..
+// "cpu=<cpu>" - parsed to features as per -mcpu=.., with CPU set to <cpu>
+// "tune=<cpu>" - TuneCPU set to <cpu>
+ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
+ ParsedTargetAttr Ret;
+ if (Features == "default")
+ return Ret;
+ SmallVector<StringRef, 1> AttrFeatures;
+ Features.split(AttrFeatures, ";");
+ bool FoundArch = false;
+
+ for (auto &Feature : AttrFeatures) {
+ Feature = Feature.trim();
+ StringRef AttrString = Feature.split("=").second.trim();
+
+ if (Feature.startswith("arch=")) {
+ if (FoundArch)
+ Ret.Duplicate = "arch=";
+ FoundArch = true;
+
+ if (AttrString.startswith("+") || AttrString.startswith("-")) {
+ // EXTENSION like arch=+v,+zbb,-c
+ SmallVector<StringRef, 1> Exts;
+ AttrString.split(Exts, ",");
+ for (auto Ext : Exts) {
+ if (Ext.empty())
+ continue;
+
+ StringRef ExtName = Ext.substr(1);
+ std::string TargetFeature =
+ llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
+ if (!TargetFeature.empty())
+ Ret.Features.push_back(Ext.front() + TargetFeature);
+ else
+ Ret.Features.push_back(Ext.str());
+ }
+ } else {
+ // full-arch-string like arch=rv64gcv
+ auto RII = llvm::RISCVISAInfo::parseArchString(
+ AttrString, /* EnableExperimentalExtension */ true);
+ if (!RII) {
+ consumeError(RII.takeError());
+ } else {
+ std::vector<std::string> FeatStrings = (*RII)->toFeatureVector();
+ for (auto FeatString : FeatStrings)
+ Ret.Features.push_back(FeatString);
+ }
+ }
+ continue;
+ } else if (Feature.startswith("cpu=")) {
+ if (!Ret.CPU.empty())
+ Ret.Duplicate = "cpu=";
+ else
+ Ret.CPU = AttrString;
+ continue;
+ } else if (Feature.startswith("tune=")) {
+ if (!Ret.Tune.empty())
+ Ret.Duplicate = "tune=";
+ else
+ Ret.Tune = AttrString;
+ continue;
+ } else if (Feature.startswith("no-"))
+ Ret.Features.push_back("-" + Feature.split("-").second.str());
+ else
+ Ret.Features.push_back("+" + Feature.str());
+ }
+ return Ret;
+}
+
+bool RISCVTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
+ return ISAInfo->isSupportedExtensionFeature(FeatureStr);
+}
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