from:"Oliver Stannard via Phabricator via cfe\-commits"

[PATCH] D50175: [AArch64][NFC] better matching of AArch64 target in aarch64-cpus.c tests

2018-08-08 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added inline comments.



Comment at: test/Driver/aarch64-cpus.c:10
+// GENERIC: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-cpu" "generic"
+// GENERIC-LE: "-cc1"{{.*}} "-triple" "aarch64--"{{.*}} "-target-cpu" "generic"
 

Why do these need new check prefixes? All of the RUN lines above are selecting 
little-endian, so I'd expect GENERIC and GENERIC-LE to be the same.


https://reviews.llvm.org/D50175



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D50175: [AArch64][NFC] better matching of AArch64 target in aarch64-cpus.c tests

2018-08-09 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added inline comments.



Comment at: test/Driver/aarch64-cpus.c:10
+// GENERIC: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-cpu" "generic"
+// GENERIC-LE: "-cc1"{{.*}} "-triple" "aarch64--"{{.*}} "-target-cpu" "generic"
 

SjoerdMeijer wrote:
> olista01 wrote:
> > Why do these need new check prefixes? All of the RUN lines above are 
> > selecting little-endian, so I'd expect GENERIC and GENERIC-LE to be the 
> > same.
> Ok, good point. The output is slightly different. For the little-endian runs 
> above the output is:
> 
>   "-triple" "aarch64"
> 
> and with "-target aarch64_be -mlittle-endian" the output is:
> 
>   "-triple" "aarch64--"
> 
> As we don't want to be too generic and match "aarch64{{.*}}", I will 
> therefore change the GENERIC checks to match "aarch64{{[--]*}}", and indeed 
> remove GENERIC-LE.
I think that works, but it's a strange way to write the regex. You have "-" 
twice inside a character set, which is the same as only having it once, so 
"[--]*" matches zero or more occurrences of "-". I'd suggest using something 
like "(--)?" which matches either "--" or nothing.


https://reviews.llvm.org/D50175



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D50175: [AArch64][NFC] better matching of AArch64 target in aarch64-cpus.c tests

2018-08-09 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


https://reviews.llvm.org/D50175



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49793: [AArch64] - return address signing

2018-08-17 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


https://reviews.llvm.org/D49793



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D38452: Mark test as a long-test

2017-10-11 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM.


https://reviews.llvm.org/D38452



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51418: [AArch64] Enable return address signing for static ctors

2018-09-13 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC342126: [AArch64] Enable return address signing for static 
ctors (authored by olista01, committed by ).
Herald added a subscriber: cfe-commits.

Repository:
  rC Clang

https://reviews.llvm.org/D51418

Files:
  lib/CodeGen/CGDeclCXX.cpp
  test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp


Index: test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
===
--- test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
+++ test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
@@ -0,0 +1,21 @@
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - 
-msign-return-address=none  %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NONE
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - 
-msign-return-address=non-leaf %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - 
-msign-return-address=all %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL
+
+struct Foo {
+  Foo() {}
+  ~Foo() {}
+};
+
+Foo f;
+
+// CHECK: @llvm.global_ctors {{.*}}i32 65535, void ()* @[[CTOR_FN:.*]], i8* 
null
+
+// CHECK: @[[CTOR_FN]]() #[[ATTR:[0-9]*]]
+
+// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} 
"sign-return-address"={{.*}} }}
+// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} 
"sign-return-address"="non-leaf" {{.*}}}
+// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" 
{{.*}} }
Index: lib/CodeGen/CGDeclCXX.cpp
===
--- lib/CodeGen/CGDeclCXX.cpp
+++ lib/CodeGen/CGDeclCXX.cpp
@@ -359,6 +359,12 @@
   !isInSanitizerBlacklist(SanitizerKind::ShadowCallStack, Fn, Loc))
 Fn->addFnAttr(llvm::Attribute::ShadowCallStack);
 
+  auto RASignKind = getCodeGenOpts().getSignReturnAddress();
+  if (RASignKind != CodeGenOptions::SignReturnAddressScope::None)
+Fn->addFnAttr("sign-return-address",
+  RASignKind == CodeGenOptions::SignReturnAddressScope::All
+  ? "all"
+  : "non-leaf");
   return Fn;
 }
 


Index: test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
===
--- test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
+++ test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
@@ -0,0 +1,21 @@
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NONE
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL
+
+struct Foo {
+  Foo() {}
+  ~Foo() {}
+};
+
+Foo f;
+
+// CHECK: @llvm.global_ctors {{.*}}i32 65535, void ()* @[[CTOR_FN:.*]], i8* null
+
+// CHECK: @[[CTOR_FN]]() #[[ATTR:[0-9]*]]
+
+// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
+// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
+// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
Index: lib/CodeGen/CGDeclCXX.cpp
===
--- lib/CodeGen/CGDeclCXX.cpp
+++ lib/CodeGen/CGDeclCXX.cpp
@@ -359,6 +359,12 @@
   !isInSanitizerBlacklist(SanitizerKind::ShadowCallStack, Fn, Loc))
 Fn->addFnAttr(llvm::Attribute::ShadowCallStack);
 
+  auto RASignKind = getCodeGenOpts().getSignReturnAddress();
+  if (RASignKind != CodeGenOptions::SignReturnAddressScope::None)
+Fn->addFnAttr("sign-return-address",
+  RASignKind == CodeGenOptions::SignReturnAddressScope::All
+  ? "all"
+  : "non-leaf");
   return Fn;
 }
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

2018-09-13 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

This looks like it has the same problem as https://reviews.llvm.org/D51418 
(doesn't get applied to C++ static constructor functions).


Repository:
  rC Clang

https://reviews.llvm.org/D51429



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51432: [AArch64] Unwinding support for return address signing

2018-09-13 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added inline comments.



Comment at: src/DwarfInstructions.hpp:210
+register unsigned long long x16 __asm("x16") = cfa;
+asm("autia1716": "+r"(x17): "r"(x16));
+returnAddress = x17;

I don't think this will work for cross-unwinding builds: for them, 
_LIBUNWIND_TARGET_AARCH64 is defined even when the compilation target is not 
AArch64, so this instruction won't exist.

Fully supporting cross-unwinding looks non-trivial: we'd need to either provide 
some way to ask the client to authenticate a pointer on the target, or strip 
the high bits of the pointer (which requires knowing the virtual address size 
of the target). For now, I think it's OK to not support cross-unwinding.



Comment at: src/Registers.hpp:1835
+  if (((regNum >= 0) && (regNum < 32)) || regNum == UNW_ARM64_RA_SIGN_STATE)
 return _registers.__x[regNum];
+

When regNum == UNW_ARM64_RA_SIGN_STATE, the index into __x is out of range. 
We'll need to add new storage to hold this value, I'd suggest replacing the 
current padding value in the GPRs struct, as that will avoid changing the 
layout expected by the context save/restore functions.



Comment at: src/Registers.hpp:1845
 _registers.__sp = value;
-  else if ((regNum >= 0) && (regNum < 32))
+  else if ((regNum >= 0) && (regNum < 32) || regNum == UNW_ARM64_RA_SIGN_STATE)
 _registers.__x[regNum] = value;

Ditto.


Repository:
  rUNW libunwind

https://reviews.llvm.org/D51432



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

2018-10-09 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added inline comments.



Comment at: lib/Frontend/CompilerInvocation.cpp:1133
+  if (Arg *A = Args.getLastArg(OPT_msign_return_address_EQ)) {
+const auto SignScopeKey = StringRef(A->getValue()).split('+');
+StringRef SignScope = SignScopeKey.first;

The driver code is emitting a separate -msign-return-address-key= option, but 
this is expecting the key to still be part of -msign-return-address=, so we can 
never end up selecting the B key. Out of the two approaches, I prefer having 
multiple simpler options in CC1, so that we don't have to repeat all of the 
parsing that happens in the driver.

Also, you're emitting the -mbranch-target-enforce option in the driver, but not 
handling it here. We should either reject it in the driver for now, or add the 
CC1 part of that in this patch.


https://reviews.llvm.org/D51429



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

2018-10-17 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added inline comments.



Comment at: lib/CodeGen/CGDeclCXX.cpp:364
   if (RASignKind != CodeGenOptions::SignReturnAddressScope::None)
+  {
 Fn->addFnAttr("sign-return-address",

LLVM style has the opening brace on the same line as the if. There's a 
git-clang-format script in the clang repo which can fix up style issues like 
this for a whole patch, changing touching lines you haven't changes.



Comment at: lib/CodeGen/CGDeclCXX.cpp:374
+  : "b_key");
+  }
+

I think we need to handle branch-target-enforcement here too.



Comment at: lib/CodeGen/TargetInfo.cpp:4982
+if (Kind != CodeGenOptions::SignReturnAddressScope::None)
+{
+  Fn->addFnAttr("sign-return-address",

Style nit: brace on same line as if.



Comment at: lib/Driver/ToolChains/Clang.cpp:1433
 
+static std::tuple
+ParseAArch64BranchProtection(const Driver &D, const ArgList &Args, const Arg 
*A) {

Please add a comment about what the parts of the return value are.



Comment at: lib/Driver/ToolChains/Clang.cpp:1440
+  StringRef Value = A->getValue();
+  // This maps onto -mbranch-protection=+
+

I'm not sure what this is trying to say. Is it referring to the "standard" case 
below?



Comment at: lib/Driver/ToolChains/Clang.cpp:1448
+  } else if (!Value.equals("none")) {
+SmallVector BranchProtection;
+StringRef(A->getValue()).split(BranchProtection, '+');

I'd make this 4, because that's the longest sensible argument 
("pac-ret+leaf+b-key+bti").



Comment at: lib/Driver/ToolChains/Clang.cpp:1460
+Scope = "non-leaf";
+while (++Protection != BranchProtection.end()) {
+  if (Protection->equals("leaf"))

Add a comment about the fact that "leaf" and "b-key" must follow "pac-ret", to 
explain why we don't just parse this in one loop.



Comment at: lib/Driver/ToolChains/Clang.cpp:1543
+if (A->getOption().matches(options::OPT_msign_return_address_EQ))
+{
+  Scope = A->getValue();

Nit: brace on same line as if.



Comment at: test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp:7
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL  
--check-prefix=CHECK-A-KEY
 
 struct Foo {

This should also test branch target enforcement (it's also missing from the 
code).


https://reviews.llvm.org/D51429



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

2018-10-25 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


https://reviews.llvm.org/D51429



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54148: [NFC][Clang][Aarch64] Add missing test file

2018-11-07 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rC Clang

https://reviews.llvm.org/D54148



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57765: [ARM] Add Cortex-M35P Support

2019-03-14 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57765/new/

https://reviews.llvm.org/D57765



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D59631: [AArch64] Support selecting TPIDR_EL[1-3] as the thread base

2019-03-21 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a reviewer: olista01.
olista01 added a comment.

Is there an existing compiler which this option is trying to be compatible 
with? GCC for AArch64 doesn't currently have an option for this, so we don't 
have to worry about compatibility with that. If possible, I'd prefer for the 
option to be "-mtp=", to match the option accepted by clang and GCC for AArch32.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59631/new/

https://reviews.llvm.org/D59631



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D59631: [AArch64] Support selecting TPIDR_EL[1-3] as the thread base

2019-03-29 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

I can't see any other uses of the option groups, or any way to put an option 
into two groups, so this LGTM.

I'll commit it for you as before.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59631/new/

https://reviews.llvm.org/D59631



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D59631: [AArch64] Support selecting TPIDR_EL[1-3] as the thread base

2019-03-29 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC357250: [AArch64] Support selecting TPIDR_EL[1-3] as the 
thread base (authored by olista01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D59631?vs=191800&id=192814#toc

Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59631/new/

https://reviews.llvm.org/D59631

Files:
  include/clang/Driver/Options.td
  lib/Driver/ToolChains/Arch/AArch64.cpp
  test/Driver/clang-translation.c


Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -2016,8 +2016,8 @@
   HelpText<"Disallow generation of data access to code sections (ARM only)">;
 def mno_execute_only : Flag<["-"], "mno-execute-only">, 
Group,
   HelpText<"Allow generation of data access to code sections (ARM only)">;
-def mtp_mode_EQ : Joined<["-"], "mtp=">, Group, 
Values<"soft, cp15">,
-  HelpText<"Read thread pointer from coprocessor register (ARM only)">;
+def mtp_mode_EQ : Joined<["-"], "mtp=">, Group, 
Values<"soft,cp15,el0,el1,el2,el3">,
+  HelpText<"Thread pointer access method (AArch32/AArch64 only)">;
 def mpure_code : Flag<["-"], "mpure-code">, Alias; // Alias for 
GCC compatibility
 def mno_pure_code : Flag<["-"], "mno-pure-code">, Alias;
 def mtvos_version_min_EQ : Joined<["-"], "mtvos-version-min=">, Group;
Index: test/Driver/clang-translation.c
===
--- test/Driver/clang-translation.c
+++ test/Driver/clang-translation.c
@@ -120,6 +120,36 @@
 // RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER_NON %s
 // ARMv7_THREAD_POINTER_NON-NOT: "-target-feature" "+read-tp-hard"
 
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_NON %s
+// ARMv8_THREAD_POINTER_NON-NOT: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_NON-NOT: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_NON-NOT: "-target-feature" "+tpidr-el3"
+
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a -mtp=el0 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL0 %s
+// ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el3"
+
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a -mtp=el1 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL1 %s
+// ARMv8_THREAD_POINTER_EL1: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_EL1-NOT: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_EL1-NOT: "-target-feature" "+tpidr-el3"
+
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a -mtp=el2 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL2 %s
+// ARMv8_THREAD_POINTER_EL2-NOT: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_EL2: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_EL2-NOT: "-target-feature" "+tpidr-el3"
+
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a -mtp=el3 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL3 %s
+// ARMv8_THREAD_POINTER_EL3-NOT: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_EL3-NOT: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_EL3: "-target-feature" "+tpidr-el3"
+
 // RUN: %clang -target powerpc64-unknown-linux-gnu \
 // RUN: -### -S %s -mcpu=G5 2>&1 | FileCheck -check-prefix=PPCG5 %s
 // PPCG5: clang
Index: lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- lib/Driver/ToolChains/Arch/AArch64.cpp
+++ lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -194,6 +194,18 @@
 Features.push_back("-neon");
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) {
+StringRef Mtp = A->getValue();
+if (Mtp == "el3")
+  Features.push_back("+tpidr-el3");
+else if (Mtp == "el2")
+  Features.push_back("+tpidr-el2");
+else if (Mtp == "el1")
+  Features.push_back("+tpidr-el1");
+else if (Mtp != "el0")
+  D.Diag(diag::err_drv_invalid_mtp) << A->getAsString(Args);
+  }
+
   // En/disable crc
   if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) {
 if (A->getOption().matches(options::OPT_mcrc))


Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -2016,8 +2016,8 @@
   HelpText<"Disallow generation of data access to code sections (ARM only)">;
 def mno_execute_only : Flag<["-"], "mno-execute-only">, Group,
   HelpText<"Allow generation of data access to code sections (ARM only)">;
-def mtp_mode_EQ : Joined<["-"], "mtp=">, Group, Values<"soft, cp15">,
-  HelpText<"Read thread pointer from coprocessor register (ARM only)">;
+def mtp_mode_EQ : J

[PATCH] D51432: [AArch64] Unwinding support for return address signing

2018-09-20 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


https://reviews.llvm.org/D51432



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D52491: [ARM/AArch64][v8.5A] Add Armv8.5-A target

2018-09-25 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 created this revision.
Herald added a reviewer: javed.absar.
Herald added subscribers: cfe-commits, chrib, kristof.beyls.

This patch allows targetting Armv8.5-A from Clang. Most of the
implementation is in TargetParser, so this is mostly just adding tests.

Patch by Pablo Barrio!


Repository:
  rC Clang

https://reviews.llvm.org/D52491

Files:
  lib/Basic/Targets/ARM.cpp
  test/Driver/aarch64-cpus.c
  test/Driver/arm-cortex-cpus.c
  test/Preprocessor/arm-target-features.c


Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -737,3 +737,18 @@
 // CHECK-V82A: #define __ARM_ARCH_PROFILE 'A'
 // CHECK-V82A: #define __ARM_FEATURE_QRDMX 1
 // CHECK-V82A: #define __ARM_FP 0xe
+
+// RUN: %clang -target armv8.3a-none-none-eabi -x c -E -dM %s -o - | FileCheck 
-match-full-lines --check-prefix=CHECK-V83A %s
+// CHECK-V83A: #define __ARM_ARCH 8
+// CHECK-V83A: #define __ARM_ARCH_8_3A__ 1
+// CHECK-V83A: #define __ARM_ARCH_PROFILE 'A'
+
+// RUN: %clang -target armv8.4a-none-none-eabi -x c -E -dM %s -o - | FileCheck 
-match-full-lines --check-prefix=CHECK-V84A %s
+// CHECK-V84A: #define __ARM_ARCH 8
+// CHECK-V84A: #define __ARM_ARCH_8_4A__ 1
+// CHECK-V84A: #define __ARM_ARCH_PROFILE 'A'
+
+// RUN: %clang -target armv8.5a-none-none-eabi -x c -E -dM %s -o - | FileCheck 
-match-full-lines --check-prefix=CHECK-V85A %s
+// CHECK-V85A: #define __ARM_ARCH 8
+// CHECK-V85A: #define __ARM_ARCH_8_5A__ 1
+// CHECK-V85A: #define __ARM_ARCH_PROFILE 'A'
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -318,6 +318,26 @@
 // RUN: %clang -target arm -march=armebv8.4-a -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V84A %s
 // CHECK-BE-V84A: "-cc1"{{.*}} "-triple" "armebv8.4{{.*}}" "-target-cpu" 
"generic"
 
+// RUN: %clang -target armv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5-a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5a -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V85A %s
+// RUN: %clang -target armv8.5a -mlittle-endian -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5a -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv8.5-a -mlittle-endian 
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V85A %s
+// CHECK-V85A: "-cc1"{{.*}} "-triple" "armv8.5{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armebv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target armv8.5a -mbig-endian -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target armeb -march=armebv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target armeb -march=armebv8.5-a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target arm -march=armebv8.5a -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target arm -march=armebv8.5-a -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V85A %s
+// CHECK-BE-V85A: "-cc1"{{.*}} "-triple" "armebv8.5{{.*}}" "-target-cpu" 
"generic"
+
+// RUN: %clang -target armv8a-linux-eabi -march=armv8.5-a+fp16 -### -c %s 2>&1 
| FileCheck --check-prefix CHECK-V85A-FP16 %s
+// CHECK-V85A-FP16: "-cc1"{{.*}} "-triple" "armv8.5{{.*}}" "-target-cpu" 
"generic" {{.*}}"-target-feature" "+fullfp16"
+
 // Once we have CPUs with optional v8.2-A FP16, we will need a way to turn it
 // on and off. Cortex-A53 is a placeholder for now.
 // RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1 
| FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s
Index: test/Driver/aarch64-cpus.c
===
--- test/Driver/aarch64-cpus.c
+++ test/Driver/aarch64-cpus.c
@@ -542,6 +542,25 @@
 // RUN: %clang -target aarch64 -march=armv8.4-a+nofp16+fp16fml -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV84A-NO-FP16-FP16FML %s
 // GENERICV84A-NO-FP16-FP16FML: "-target-feature" "+fp16fml" "-target-feature" 
"+fullfp16"
 
+// RUN: %clang -target aarch64 -march=armv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -march=armv8.5-a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.5a -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.5-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV85A

[PATCH] D52493: [AArch64][v8.5A] Test clang option for the Memory Tagging Extension

2018-09-25 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 created this revision.
Herald added a reviewer: javed.absar.
Herald added subscribers: cfe-commits, kristof.beyls.

The implementation of this is in TargetParser, so we only need to add a
test for it in clang.

Patch by Pablo Barrio!


Repository:
  rC Clang

https://reviews.llvm.org/D52493

Files:
  test/Driver/aarch64-mte.c


Index: test/Driver/aarch64-mte.c
===
--- /dev/null
+++ test/Driver/aarch64-mte.c
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+memtag %s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+memtag %s 
2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+nomemtag %s 
2>&1 | FileCheck %s --check-prefix=NOMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+nomemtag %s 
2>&1 | FileCheck %s --check-prefix=NOMTE
+// NOMTE: "-target-feature" "-mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// ABSENTMTE-NOT: "-target-feature" "+mte"
+// ABSENTMTE-NOT: "-target-feature" "-mte"


Index: test/Driver/aarch64-mte.c
===
--- /dev/null
+++ test/Driver/aarch64-mte.c
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+memtag %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+memtag %s 2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+// NOMTE: "-target-feature" "-mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | FileCheck %s --check-prefix=ABSENTMTE
+// ABSENTMTE-NOT: "-target-feature" "+mte"
+// ABSENTMTE-NOT: "-target-feature" "-mte"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D52492: [AArch64][v8.5A] Test optional Armv8.5-A random number extension

2018-09-25 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 created this revision.
Herald added a reviewer: javed.absar.
Herald added subscribers: cfe-commits, chrib, kristof.beyls.

The implementation of this is in TargetParser, so we only need to add a
test for it in clang.

Patch by Pablo Barrio!


Repository:
  rC Clang

https://reviews.llvm.org/D52492

Files:
  test/Driver/aarch64-rand.c


Index: test/Driver/aarch64-rand.c
===
--- /dev/null
+++ test/Driver/aarch64-rand.c
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+rng %s 2>&1 
| FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+rng %s 2>&1 
| FileCheck %s
+// CHECK: "-target-feature" "+rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+norng %s 
2>&1 | FileCheck %s --check-prefix=NORAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+norng %s 
2>&1 | FileCheck %s --check-prefix=NORAND
+// NORAND: "-target-feature" "-rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// ABSENTRAND-NOT: "-target-feature" "+rand"
+// ABSENTRAND-NOT: "-target-feature" "-rand"


Index: test/Driver/aarch64-rand.c
===
--- /dev/null
+++ test/Driver/aarch64-rand.c
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+rng %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+rng %s 2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+norng %s 2>&1 | FileCheck %s --check-prefix=NORAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+norng %s 2>&1 | FileCheck %s --check-prefix=NORAND
+// NORAND: "-target-feature" "-rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | FileCheck %s --check-prefix=ABSENTRAND
+// ABSENTRAND-NOT: "-target-feature" "+rand"
+// ABSENTRAND-NOT: "-target-feature" "-rand"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D52491: [ARM/AArch64][v8.5A] Add Armv8.5-A target

2018-09-26 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC343111: [ARM/AArch64][v8.5A] Add Armv8.5-A target (authored 
by olista01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D52491?vs=166908&id=167130#toc

Repository:
  rC Clang

https://reviews.llvm.org/D52491

Files:
  lib/Basic/Targets/ARM.cpp
  test/Driver/aarch64-cpus.c
  test/Driver/arm-cortex-cpus.c
  test/Preprocessor/arm-target-features.c

Index: test/Driver/aarch64-cpus.c
===
--- test/Driver/aarch64-cpus.c
+++ test/Driver/aarch64-cpus.c
@@ -542,6 +542,25 @@
 // RUN: %clang -target aarch64 -march=armv8.4-a+nofp16+fp16fml -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV84A-NO-FP16-FP16FML %s
 // GENERICV84A-NO-FP16-FP16FML: "-target-feature" "+fp16fml" "-target-feature" "+fullfp16"
 
+// RUN: %clang -target aarch64 -march=armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -march=armv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// GENERICV85A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.5a"
+
+// RUN: %clang -target aarch64_be -march=armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64_be -march=armv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -march=armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -march=armv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -march=armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -march=armv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
+// GENERICV85A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.5a"
+
+// RUN: %clang -target aarch64 -march=armv8.5-a+fp16 -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-FP16 %s
+// GENERICV85A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.5a" "-target-feature" "+fullfp16"
+
 // fullfp16 is off by default for v8a, feature must not be mentioned
 // RUN: %clang -target aarch64 -march=armv8a  -### -c %s 2>&1 | FileCheck -check-prefix=V82ANOFP16 -check-prefix=GENERIC %s
 // RUN: %clang -target aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=V82ANOFP16 -check-prefix=GENERIC %s
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -318,6 +318,23 @@
 // RUN: %clang -target arm -march=armebv8.4-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V84A %s
 // CHECK-BE-V84A: "-cc1"{{.*}} "-triple" "armebv8.4{{.*}}" "-target-cpu" "generic"
 
+// RUN: %clang -target armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V85A %s
+// RUN: %clang -target armv8.5a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv8.5-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V85A %s
+// CHECK-V85A: "-cc1"{{.*}} "-triple" "armv8.5{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armebv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target armv8.5a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target armeb -march=armebv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target armeb -march=armebv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target arm -march=armebv8.5a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V85A %s
+// RUN: %clang -target arm -march=armebv8.5-a

[PATCH] D52492: [AArch64][v8.5A] Test optional Armv8.5-A random number extension

2018-09-27 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC343220: [AArch64][v8.5A] Test optional Armv8.5-A random 
number extension (authored by olista01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D52492?vs=166909&id=167322#toc

Repository:
  rC Clang

https://reviews.llvm.org/D52492

Files:
  test/Driver/aarch64-rand.c


Index: test/Driver/aarch64-rand.c
===
--- test/Driver/aarch64-rand.c
+++ test/Driver/aarch64-rand.c
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+rng %s 2>&1 
| FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+rng %s 2>&1 
| FileCheck %s
+// CHECK: "-target-feature" "+rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+norng %s 
2>&1 | FileCheck %s --check-prefix=NORAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+norng %s 
2>&1 | FileCheck %s --check-prefix=NORAND
+// NORAND: "-target-feature" "-rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// ABSENTRAND-NOT: "-target-feature" "+rand"
+// ABSENTRAND-NOT: "-target-feature" "-rand"


Index: test/Driver/aarch64-rand.c
===
--- test/Driver/aarch64-rand.c
+++ test/Driver/aarch64-rand.c
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+rng %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+rng %s 2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+norng %s 2>&1 | FileCheck %s --check-prefix=NORAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+norng %s 2>&1 | FileCheck %s --check-prefix=NORAND
+// NORAND: "-target-feature" "-rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | FileCheck %s --check-prefix=ABSENTRAND
+// ABSENTRAND-NOT: "-target-feature" "+rand"
+// ABSENTRAND-NOT: "-target-feature" "-rand"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D52493: [AArch64][v8.5A] Test clang option for the Memory Tagging Extension

2018-10-02 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC343566: [AArch64][v8.5A] Test clang option for the Memory 
Tagging Extension (authored by olista01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D52493?vs=166910&id=167900#toc

Repository:
  rC Clang

https://reviews.llvm.org/D52493

Files:
  test/Driver/aarch64-mte.c


Index: test/Driver/aarch64-mte.c
===
--- test/Driver/aarch64-mte.c
+++ test/Driver/aarch64-mte.c
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+memtag %s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+memtag %s 
2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+nomemtag %s 
2>&1 | FileCheck %s --check-prefix=NOMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+nomemtag %s 
2>&1 | FileCheck %s --check-prefix=NOMTE
+// NOMTE: "-target-feature" "-mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// ABSENTMTE-NOT: "-target-feature" "+mte"
+// ABSENTMTE-NOT: "-target-feature" "-mte"


Index: test/Driver/aarch64-mte.c
===
--- test/Driver/aarch64-mte.c
+++ test/Driver/aarch64-mte.c
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+memtag %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+memtag %s 2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+// NOMTE: "-target-feature" "-mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | FileCheck %s --check-prefix=ABSENTMTE
+// ABSENTMTE-NOT: "-target-feature" "+mte"
+// ABSENTMTE-NOT: "-target-feature" "-mte"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57764: [AArch64] Add Cortex-A76 and Cortex-A76AE Support

2019-02-06 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM, but please remember to upload with more context.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57764/new/

https://reviews.llvm.org/D57764



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57765: [ARM] Add Cortex-M35P Support

2019-02-06 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 requested changes to this revision.
olista01 added inline comments.
This revision now requires changes to proceed.



Comment at: test/Driver/arm-cortex-cpus.c:826
 // RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8MMAIN %s
+// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8MMAIN %s
 // CHECK-CPUV8MMAIN:  "-cc1"{{.*}} "-triple" "thumbv8m.main-

I think this should also check that the correct CPU is passed to cc1, because 
you've defined a ProcessorModel in the backend.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57765/new/

https://reviews.llvm.org/D57765



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D23610: [ARM] Add pre-defined macros for ROPI and RWPI

2019-02-18 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

These macros have been in the published ACLE for a while now: 
https://developer.arm.com/products/software-development-tools/compilers/arm-compiler-5/docs/101028/latest/5-feature-test-macros#position-independent-code


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D23610/new/

https://reviews.llvm.org/D23610



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D23610: [ARM] Add pre-defined macros for ROPI and RWPI

2019-02-18 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

Yes, the back-end work was all done years ago, I just also forgot about these 
while waiting for the ACLE to be published.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D23610/new/

https://reviews.llvm.org/D23610



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D23610: [ARM] Add pre-defined macros for ROPI and RWPI

2019-02-18 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL354265: [ARM] Add pre-defined macros for ROPI and RWPI 
(authored by olista01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D23610?vs=91990&id=187220#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D23610/new/

https://reviews.llvm.org/D23610

Files:
  cfe/trunk/include/clang/Basic/LangOptions.def
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/Basic/Targets/ARM.cpp
  cfe/trunk/lib/Driver/ToolChains/Clang.cpp
  cfe/trunk/lib/Frontend/CompilerInvocation.cpp
  cfe/trunk/test/Preprocessor/arm-pic-predefines.c


Index: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp
@@ -3810,6 +3810,13 @@
   CmdArgs.push_back("-pic-is-pie");
   }
 
+  if (RelocationModel == llvm::Reloc::ROPI ||
+  RelocationModel == llvm::Reloc::ROPI_RWPI)
+CmdArgs.push_back("-fropi");
+  if (RelocationModel == llvm::Reloc::RWPI ||
+  RelocationModel == llvm::Reloc::ROPI_RWPI)
+CmdArgs.push_back("-frwpi");
+
   if (Arg *A = Args.getLastArg(options::OPT_meabi)) {
 CmdArgs.push_back("-meabi");
 CmdArgs.push_back(A->getValue());
Index: cfe/trunk/lib/Basic/Targets/ARM.cpp
===
--- cfe/trunk/lib/Basic/Targets/ARM.cpp
+++ cfe/trunk/lib/Basic/Targets/ARM.cpp
@@ -652,6 +652,12 @@
   if (SoftFloat)
 Builder.defineMacro("__SOFTFP__");
 
+  // ACLE position independent code macros.
+  if (Opts.ROPI)
+Builder.defineMacro("__ARM_ROPI", "1");
+  if (Opts.RWPI)
+Builder.defineMacro("__ARM_RWPI", "1");
+
   if (ArchKind == llvm::ARM::ArchKind::XSCALE)
 Builder.defineMacro("__XSCALE__");
 
Index: cfe/trunk/lib/Frontend/CompilerInvocation.cpp
===
--- cfe/trunk/lib/Frontend/CompilerInvocation.cpp
+++ cfe/trunk/lib/Frontend/CompilerInvocation.cpp
@@ -2662,6 +2662,8 @@
   Opts.MaxTypeAlign = getLastArgIntValue(Args, OPT_fmax_type_align_EQ, 0, 
Diags);
   Opts.AlignDouble = Args.hasArg(OPT_malign_double);
   Opts.PICLevel = getLastArgIntValue(Args, OPT_pic_level, 0, Diags);
+  Opts.ROPI = Args.hasArg(OPT_fropi);
+  Opts.RWPI = Args.hasArg(OPT_frwpi);
   Opts.PIE = Args.hasArg(OPT_pic_is_pie);
   Opts.Static = Args.hasArg(OPT_static_define);
   Opts.DumpRecordLayoutsSimple = Args.hasArg(OPT_fdump_record_layouts_simple);
Index: cfe/trunk/include/clang/Basic/LangOptions.def
===
--- cfe/trunk/include/clang/Basic/LangOptions.def
+++ cfe/trunk/include/clang/Basic/LangOptions.def
@@ -170,6 +170,8 @@
 VALUE_LANGOPT(AlignDouble, 1, 0, "Controls if doubles should be 
aligned to 8 bytes (x86 only)")
 COMPATIBLE_VALUE_LANGOPT(PICLevel, 2, 0, "__PIC__ level")
 COMPATIBLE_VALUE_LANGOPT(PIE , 1, 0, "is pie")
+LANGOPT(ROPI , 1, 0, "Read-only position independence")
+LANGOPT(RWPI , 1, 0, "Read-write position 
independence")
 COMPATIBLE_LANGOPT(GNUInline , 1, 0, "GNU inline semantics")
 COMPATIBLE_LANGOPT(NoInlineDefine, 1, 0, "__NO_INLINE__ predefined macro")
 COMPATIBLE_LANGOPT(Deprecated, 1, 0, "__DEPRECATED predefined macro")
Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ -1606,9 +1606,9 @@
   HelpText<"Use the PLT to make function calls">;
 def fno_plt : Flag<["-"], "fno-plt">, Group, Flags<[CC1Option]>,
   HelpText<"Do not use the PLT to make function calls">;
-def fropi : Flag<["-"], "fropi">, Group;
+def fropi : Flag<["-"], "fropi">, Group, Flags<[CC1Option]>;
 def fno_ropi : Flag<["-"], "fno-ropi">, Group;
-def frwpi : Flag<["-"], "frwpi">, Group;
+def frwpi : Flag<["-"], "frwpi">, Group, Flags<[CC1Option]>;
 def fno_rwpi : Flag<["-"], "fno-rwpi">, Group;
 def fplugin_EQ : Joined<["-"], "fplugin=">, Group, 
Flags<[DriverOption]>, MetaVarName<"">,
   HelpText<"Load the named plugin (dynamic shared object)">;
Index: cfe/trunk/test/Preprocessor/arm-pic-predefines.c
===
--- cfe/trunk/test/Preprocessor/arm-pic-predefines.c
+++ cfe/trunk/test/Preprocessor/arm-pic-predefines.c
@@ -0,0 +1,14 @@
+// REQUIRES: arm-registered-target
+
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o -   | 
FileCheck %s --check-prefix=NO-ROPI --check-prefix=NO-RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -fropi| 
FileCheck %s --check-prefix=ROPI--check-prefix=NO-RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -frwpi| 
FileCheck %s --check-prefix=NO-ROPI --check-

[PATCH] D46108: [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro

2018-04-26 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 created this revision.
olista01 added reviewers: rengolin, SjoerdMeijer, flyingforyou.
Herald added a reviewer: javed.absar.
Herald added subscribers: llvm-commits, chrib, kristof.beyls.

This adds a pre-defined macro to test if the compiler has support for the 
v8.2-A dot rpoduct intrinsics in AArch32 mode.

  

The AAcrh64 equivalent has already been added by 
https://reviews.llvm.org/rL330229.

  

The ACLE spec which describes this macro hasn't been published yet, but this is 
based on the final internal draft, and GCC has already implemented this.


Repository:
  rL LLVM

https://reviews.llvm.org/D46108

Files:
  lib/Basic/Targets/ARM.cpp
  lib/Basic/Targets/ARM.h
  test/Preprocessor/arm-target-features.c


Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -6,6 +6,7 @@
 // CHECK-V8A: #define __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK-V8A: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
 // CHECK-V8A-NOT: #define __ARM_FP 0x
+// CHECK-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target armv8a-none-linux-gnueabi -x c -E -dM %s -o - | 
FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
 // RUN: %clang -target armv8a-none-linux-gnueabihf -x c -E -dM %s -o - | 
FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
@@ -18,6 +19,7 @@
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP 0xe
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_ARGS 1
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_FORMAT_IEEE 1
+// CHECK-V8A-ALLOW-FP-INSTR-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+fp16 -x c -E -dM 
%s -o - | FileCheck -match-full-lines 
--check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
 // CHECK-FULLFP16-VECTOR-SCALAR: #define __ARM_FEATURE_FP16_SCALAR_ARITHMETIC 1
@@ -30,6 +32,9 @@
 // CHECK-FULLFP16-SCALAR-NOT:   #define __ARM_FEATURE_FP16_VECTOR_ARITHMETIC 1
 // CHECK-FULLFP16-SCALAR:   #define __ARM_FP 0xe
 // CHECK-FULLFP16-SCALAR:   #define __ARM_FP16_FORMAT_IEEE 1
+//
+// RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+dotprod -x c -E 
-dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-DOTPROD %s
+// CHECK-DOTPROD: #define __ARM_FEATURE_DOTPROD 1
 
 // RUN: %clang -target armv8r-none-linux-gnu -x c -E -dM %s -o - | FileCheck 
-match-full-lines --check-prefix=CHECK-V8R %s
 // CHECK-V8R: #define __ARMEL__ 1
Index: lib/Basic/Targets/ARM.h
===
--- lib/Basic/Targets/ARM.h
+++ lib/Basic/Targets/ARM.h
@@ -69,6 +69,7 @@
   unsigned Crypto : 1;
   unsigned DSP : 1;
   unsigned Unaligned : 1;
+  unsigned DotProd : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)
Index: lib/Basic/Targets/ARM.cpp
===
--- lib/Basic/Targets/ARM.cpp
+++ lib/Basic/Targets/ARM.cpp
@@ -390,6 +390,7 @@
   Unaligned = 1;
   SoftFloat = SoftFloatABI = false;
   HWDiv = 0;
+  DotProd = 0;
 
   // This does not diagnose illegal cases like having both
   // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
@@ -432,6 +433,8 @@
   HW_FP |= HW_FP_HP;
 } else if (Feature == "+fullfp16") {
   HasLegalHalfType = true;
+} else if (Feature == "+dotprod") {
+  DotProd = true;
 }
   }
   HW_FP &= ~HW_FP_remove;
@@ -731,6 +734,8 @@
   if (HasLegalHalfType)
 Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
 
+  if (DotProd)
+Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
 
   switch (ArchKind) {
   default:


Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -6,6 +6,7 @@
 // CHECK-V8A: #define __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK-V8A: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
 // CHECK-V8A-NOT: #define __ARM_FP 0x
+// CHECK-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target armv8a-none-linux-gnueabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
 // RUN: %clang -target armv8a-none-linux-gnueabihf -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
@@ -18,6 +19,7 @@
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP 0xe
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_ARGS 1
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_FORMAT_IEEE 1
+// CHECK-V8A-ALLOW-FP-INSTR-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+fp16 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
 // CHECK-FULLFP16-VECTOR-SCALAR: #define __ARM_FEATURE_FP16_SCALAR_ARITHMETIC 1
@@ -30,6 +32,9 @@
 // CHECK-FULLFP16-SCALAR-NOT:   #define __ARM_FEATURE_F

[PATCH] D46109: [ARM, AArch64] Add intrinsics for dot product instructions

2018-04-26 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 created this revision.
olista01 added reviewers: rengolin, SjoerdMeijer, flyingforyou.
Herald added a reviewer: javed.absar.
Herald added subscribers: llvm-commits, chrib, kristof.beyls.

The ACLE spec which describes these intrinsics hasn't been published yet, but 
this is based on the final draft which will be published soon, and these have 
already been implemented by GCC.


Repository:
  rL LLVM

https://reviews.llvm.org/D46109

Files:
  include/clang/Basic/arm_neon.td
  include/clang/Basic/arm_neon_incl.td
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/aarch64-neon-dot-product.c
  test/CodeGen/arm-neon-dot-product.c
  utils/TableGen/NeonEmitter.cpp

Index: utils/TableGen/NeonEmitter.cpp
===
--- utils/TableGen/NeonEmitter.cpp
+++ utils/TableGen/NeonEmitter.cpp
@@ -995,6 +995,19 @@
 if (!AppliedQuad)
   Bitwidth *= 2;
 break;
+  case '7':
+if (AppliedQuad)
+  Bitwidth /= 2;
+ElementBitwidth = 8;
+break;
+  case '8':
+ElementBitwidth = 8;
+break;
+  case '9':
+if (!AppliedQuad)
+  Bitwidth *= 2;
+ElementBitwidth = 8;
+break;
   default:
 llvm_unreachable("Unhandled character!");
   }
Index: test/CodeGen/arm-neon-dot-product.c
===
--- /dev/null
+++ test/CodeGen/arm-neon-dot-product.c
@@ -0,0 +1,76 @@
+// RUN: %clang_cc1 -triple armv8-linux-gnueabihf -target-cpu cortex-a57 -target-feature +dotprod \
+// RUN: -disable-O0-optnone  -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s
+
+// REQUIRES: arm-registered-target
+
+// Test ARM v8.2-A dot product intrinsics
+
+#include 
+
+uint32x2_t test_vdot_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
+// CHECK-LABEL: define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: ret <2 x i32> [[RESULT]]
+  return vdot_u32(a, b, c);
+}
+
+uint32x4_t test_vdotq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
+// CHECK-LABEL: define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
+// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
+// CHECK: ret <4 x i32> [[RESULT]]
+  return vdotq_u32(a, b, c);
+}
+
+int32x2_t test_vdot_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
+// CHECK-LABEL: define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: ret <2 x i32> [[RESULT]]
+  return vdot_s32(a, b, c);
+}
+
+int32x4_t test_vdotq_s32(int32x4_t a, int8x16_t b, int8x16_t c) {
+// CHECK-LABEL: define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
+// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
+// CHECK: ret <4 x i32> [[RESULT]]
+  return vdotq_s32(a, b, c);
+}
+
+uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
+// CHECK-LABEL: define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
+// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <2 x i32> 
+// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
+// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> [[CAST2]])
+// CHECK: ret <2 x i32> [[RESULT]]
+  return vdot_lane_u32(a, b, c, 1);
+}
+
+uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) {
+// CHECK-LABEL: define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
+// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
+// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <4 x i32> 
+// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
+// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> [[CAST2]])
+// CHECK: ret <4 x i32> [[RESULT]]
+  return vdotq_lane_u32(a, b, c, 1);
+}
+
+int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
+// CHECK-LABEL: define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
+// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <2 x i32> 
+// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
+// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> [[CAST2]])
+// CHECK: ret <2 x i32> [[RESULT]]
+  return vdot_lane_s32(a, b, c, 1);
+}
+
+int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) {
+// CHECK-LABEL: define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8>

[PATCH] D46108: [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro

2018-04-27 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC331038: [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro 
(authored by olista01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D46108?vs=144080&id=144339#toc

Repository:
  rC Clang

https://reviews.llvm.org/D46108

Files:
  lib/Basic/Targets/ARM.cpp
  lib/Basic/Targets/ARM.h
  test/Preprocessor/arm-target-features.c


Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -6,6 +6,7 @@
 // CHECK-V8A: #define __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK-V8A: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
 // CHECK-V8A-NOT: #define __ARM_FP 0x
+// CHECK-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target armv8a-none-linux-gnueabi -x c -E -dM %s -o - | 
FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
 // RUN: %clang -target armv8a-none-linux-gnueabihf -x c -E -dM %s -o - | 
FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
@@ -18,6 +19,7 @@
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP 0xe
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_ARGS 1
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_FORMAT_IEEE 1
+// CHECK-V8A-ALLOW-FP-INSTR-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+fp16 -x c -E -dM 
%s -o - | FileCheck -match-full-lines 
--check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
 // CHECK-FULLFP16-VECTOR-SCALAR: #define __ARM_FEATURE_FP16_SCALAR_ARITHMETIC 1
@@ -30,6 +32,9 @@
 // CHECK-FULLFP16-SCALAR-NOT:   #define __ARM_FEATURE_FP16_VECTOR_ARITHMETIC 1
 // CHECK-FULLFP16-SCALAR:   #define __ARM_FP 0xe
 // CHECK-FULLFP16-SCALAR:   #define __ARM_FP16_FORMAT_IEEE 1
+//
+// RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+dotprod -x c -E 
-dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-DOTPROD %s
+// CHECK-DOTPROD: #define __ARM_FEATURE_DOTPROD 1
 
 // RUN: %clang -target armv8r-none-linux-gnu -x c -E -dM %s -o - | FileCheck 
-match-full-lines --check-prefix=CHECK-V8R %s
 // CHECK-V8R: #define __ARMEL__ 1
Index: lib/Basic/Targets/ARM.cpp
===
--- lib/Basic/Targets/ARM.cpp
+++ lib/Basic/Targets/ARM.cpp
@@ -390,6 +390,7 @@
   Unaligned = 1;
   SoftFloat = SoftFloatABI = false;
   HWDiv = 0;
+  DotProd = 0;
 
   // This does not diagnose illegal cases like having both
   // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
@@ -432,6 +433,8 @@
   HW_FP |= HW_FP_HP;
 } else if (Feature == "+fullfp16") {
   HasLegalHalfType = true;
+} else if (Feature == "+dotprod") {
+  DotProd = true;
 }
   }
   HW_FP &= ~HW_FP_remove;
@@ -731,6 +734,9 @@
   if (HasLegalHalfType)
 Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
 
+  // Armv8.2-A dot product intrinsics
+  if (DotProd)
+Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
 
   switch (ArchKind) {
   default:
Index: lib/Basic/Targets/ARM.h
===
--- lib/Basic/Targets/ARM.h
+++ lib/Basic/Targets/ARM.h
@@ -69,6 +69,7 @@
   unsigned Crypto : 1;
   unsigned DSP : 1;
   unsigned Unaligned : 1;
+  unsigned DotProd : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)


Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -6,6 +6,7 @@
 // CHECK-V8A: #define __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK-V8A: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
 // CHECK-V8A-NOT: #define __ARM_FP 0x
+// CHECK-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target armv8a-none-linux-gnueabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
 // RUN: %clang -target armv8a-none-linux-gnueabihf -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
@@ -18,6 +19,7 @@
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP 0xe
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_ARGS 1
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_FORMAT_IEEE 1
+// CHECK-V8A-ALLOW-FP-INSTR-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+fp16 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
 // CHECK-FULLFP16-VECTOR-SCALAR: #define __ARM_FEATURE_FP16_SCALAR_ARITHMETIC 1
@@ -30,6 +32,9 @@
 // CHECK-FULLFP16-SCALAR-NOT:   #define __ARM_FEATURE_FP16_VECTOR_ARITHMETIC 1
 // CHECK-FULLFP16-SCALAR:   #define __ARM_FP 0xe
 // CHECK-FULLFP16-SCALAR:   #define __ARM_FP16_FORMAT_IEEE 1
+//
+// RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+dotprod -x c -E -dM %s -o - | FileCheck -match-full

[PATCH] D46109: [ARM, AArch64] Add intrinsics for dot product instructions

2018-04-27 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 marked an inline comment as done.
olista01 added inline comments.



Comment at: test/CodeGen/arm-neon-dot-product.c:1
+// RUN: %clang_cc1 -triple armv8-linux-gnueabihf -target-cpu cortex-a57 
-target-feature +dotprod \
+// RUN: -disable-O0-optnone  -emit-llvm -o - %s | opt -S -instcombine | 
FileCheck %s

efriedma wrote:
> flyingforyou wrote:
> > efriedma wrote:
> > > flyingforyou wrote:
> > > > I think proper target is cortex-a55 or cortex-a75.
> > > > Do we need  check routines for wrong target-cpu?
> > > This is working as intended, I think: target-feature overrides target-cpu.
> > dotprod is ARMv8.2's addition feature not ARMv8. Cortex-a57 only supports 
> > ARMv8 which couldn't have dotprod feature. Am I missing something?
> Oh, sorry, misunderstood the question; yes, this might not be the most clear 
> "CHECK" line.
I've changed this to cortex-a75 for clarity.


Repository:
  rL LLVM

https://reviews.llvm.org/D46109



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D46109: [ARM, AArch64] Add intrinsics for dot product instructions

2018-04-27 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC331039: [ARM,AArch64] Add intrinsics for dot product 
instructions (authored by olista01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D46109?vs=144081&id=144341#toc

Repository:
  rC Clang

https://reviews.llvm.org/D46109

Files:
  include/clang/Basic/arm_neon.td
  include/clang/Basic/arm_neon_incl.td
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/aarch64-neon-dot-product.c
  test/CodeGen/arm-neon-dot-product.c
  utils/TableGen/NeonEmitter.cpp

Index: test/CodeGen/arm-neon-dot-product.c
===
--- test/CodeGen/arm-neon-dot-product.c
+++ test/CodeGen/arm-neon-dot-product.c
@@ -0,0 +1,76 @@
+// RUN: %clang_cc1 -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod \
+// RUN: -disable-O0-optnone  -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s
+
+// REQUIRES: arm-registered-target
+
+// Test ARM v8.2-A dot product intrinsics
+
+#include 
+
+uint32x2_t test_vdot_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
+// CHECK-LABEL: define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: ret <2 x i32> [[RESULT]]
+  return vdot_u32(a, b, c);
+}
+
+uint32x4_t test_vdotq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
+// CHECK-LABEL: define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
+// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
+// CHECK: ret <4 x i32> [[RESULT]]
+  return vdotq_u32(a, b, c);
+}
+
+int32x2_t test_vdot_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
+// CHECK-LABEL: define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: ret <2 x i32> [[RESULT]]
+  return vdot_s32(a, b, c);
+}
+
+int32x4_t test_vdotq_s32(int32x4_t a, int8x16_t b, int8x16_t c) {
+// CHECK-LABEL: define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
+// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
+// CHECK: ret <4 x i32> [[RESULT]]
+  return vdotq_s32(a, b, c);
+}
+
+uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
+// CHECK-LABEL: define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
+// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <2 x i32> 
+// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
+// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> [[CAST2]])
+// CHECK: ret <2 x i32> [[RESULT]]
+  return vdot_lane_u32(a, b, c, 1);
+}
+
+uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) {
+// CHECK-LABEL: define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
+// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
+// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <4 x i32> 
+// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
+// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> [[CAST2]])
+// CHECK: ret <4 x i32> [[RESULT]]
+  return vdotq_lane_u32(a, b, c, 1);
+}
+
+int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
+// CHECK-LABEL: define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
+// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
+// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <2 x i32> 
+// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
+// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> [[CAST2]])
+// CHECK: ret <2 x i32> [[RESULT]]
+  return vdot_lane_s32(a, b, c, 1);
+}
+
+int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) {
+// CHECK-LABEL: define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
+// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
+// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <4 x i32> 
+// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
+// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> [[CAST2]])
+// CHECK: ret <4 x i32> [[RESULT]]
+  return vdotq_lane_s32(a, b, c, 1);
+}
Index: test/CodeGen/aarch64-neon-dot-product.c
===
--- test/CodeGen/aarch64-neon-dot-product.c
+++ test/CodeGen/aarch64-neon-dot-product.c
@@ -0,0 +

[PATCH] D36666: [ObjC] Use consistent comment style in inline asm

2017-08-14 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 created this revision.
Herald added a subscriber: javed.absar.

The comment markers accepted by the assembler vary between different targets, 
but '//' is always accepted, so we should use that for consistency.


Repository:
  rL LLVM

https://reviews.llvm.org/D3

Files:
  lib/CodeGen/TargetInfo.cpp
  test/CodeGenObjC/arc-arm.m


Index: test/CodeGenObjC/arc-arm.m
===
--- test/CodeGenObjC/arc-arm.m
+++ test/CodeGenObjC/arc-arm.m
@@ -13,7 +13,7 @@
 void test1(void) {
   extern id test1_helper(void);
   // CHECK:  [[T0:%.*]] = call [[CC]]i8* @test1_helper()
-  // CHECK-NEXT: call void asm sideeffect "mov
+  // CHECK-NEXT: call void asm sideeffect "mov\09{{fp, fp|r7, r7}}\09\09// 
marker for objc_retainAutoreleaseReturnValue"
   // CHECK-NEXT: [[T1:%.*]] = call [[CC]]i8* 
@objc_retainAutoreleasedReturnValue(i8* [[T0]])
   // CHECK-NEXT: store i8* [[T1]],
   // CHECK-NEXT: call [[CC]]void @objc_storeStrong(
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -1085,7 +1085,7 @@
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
 return "movl\t%ebp, %ebp"
-   "\t\t## marker for objc_retainAutoreleaseReturnValue";
+   "\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 };
 
@@ -4880,7 +4880,7 @@
   : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tfp, fp\t\t# marker for objc_retainAutoreleaseReturnValue";
+return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
@@ -5486,7 +5486,7 @@
   }
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
+return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,


Index: test/CodeGenObjC/arc-arm.m
===
--- test/CodeGenObjC/arc-arm.m
+++ test/CodeGenObjC/arc-arm.m
@@ -13,7 +13,7 @@
 void test1(void) {
   extern id test1_helper(void);
   // CHECK:  [[T0:%.*]] = call [[CC]]i8* @test1_helper()
-  // CHECK-NEXT: call void asm sideeffect "mov
+  // CHECK-NEXT: call void asm sideeffect "mov\09{{fp, fp|r7, r7}}\09\09// marker for objc_retainAutoreleaseReturnValue"
   // CHECK-NEXT: [[T1:%.*]] = call [[CC]]i8* @objc_retainAutoreleasedReturnValue(i8* [[T0]])
   // CHECK-NEXT: store i8* [[T1]],
   // CHECK-NEXT: call [[CC]]void @objc_storeStrong(
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -1085,7 +1085,7 @@
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
 return "movl\t%ebp, %ebp"
-   "\t\t## marker for objc_retainAutoreleaseReturnValue";
+   "\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 };
 
@@ -4880,7 +4880,7 @@
   : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tfp, fp\t\t# marker for objc_retainAutoreleaseReturnValue";
+return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
@@ -5486,7 +5486,7 @@
   }
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
+return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D36666: [ObjC] Use consistent comment style in inline asm

2017-08-21 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added reviewers: rnk, niravd, SjoerdMeijer.
olista01 added a comment.

Ping.


Repository:
  rL LLVM

https://reviews.llvm.org/D3



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D36666: [ObjC] Use consistent comment style in inline asm

2017-08-21 Thread Oliver Stannard via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL311325: [ObjC] Use consistent comment style in inline asm 
(authored by olista01).

Changed prior to commit:
  https://reviews.llvm.org/D3?vs=110927&id=111942#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D3

Files:
  cfe/trunk/lib/CodeGen/TargetInfo.cpp
  cfe/trunk/test/CodeGenObjC/arc-arm.m


Index: cfe/trunk/test/CodeGenObjC/arc-arm.m
===
--- cfe/trunk/test/CodeGenObjC/arc-arm.m
+++ cfe/trunk/test/CodeGenObjC/arc-arm.m
@@ -13,7 +13,7 @@
 void test1(void) {
   extern id test1_helper(void);
   // CHECK:  [[T0:%.*]] = call [[CC]]i8* @test1_helper()
-  // CHECK-NEXT: call void asm sideeffect "mov
+  // CHECK-NEXT: call void asm sideeffect "mov\09{{fp, fp|r7, r7}}\09\09// 
marker for objc_retainAutoreleaseReturnValue"
   // CHECK-NEXT: [[T1:%.*]] = call [[CC]]i8* 
@objc_retainAutoreleasedReturnValue(i8* [[T0]])
   // CHECK-NEXT: store i8* [[T1]],
   // CHECK-NEXT: call [[CC]]void @objc_storeStrong(
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -1085,7 +1085,7 @@
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
 return "movl\t%ebp, %ebp"
-   "\t\t## marker for objc_retainAutoreleaseReturnValue";
+   "\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 };
 
@@ -4880,7 +4880,7 @@
   : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tfp, fp\t\t# marker for objc_retainAutoreleaseReturnValue";
+return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
@@ -5486,7 +5486,7 @@
   }
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
+return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,


Index: cfe/trunk/test/CodeGenObjC/arc-arm.m
===
--- cfe/trunk/test/CodeGenObjC/arc-arm.m
+++ cfe/trunk/test/CodeGenObjC/arc-arm.m
@@ -13,7 +13,7 @@
 void test1(void) {
   extern id test1_helper(void);
   // CHECK:  [[T0:%.*]] = call [[CC]]i8* @test1_helper()
-  // CHECK-NEXT: call void asm sideeffect "mov
+  // CHECK-NEXT: call void asm sideeffect "mov\09{{fp, fp|r7, r7}}\09\09// marker for objc_retainAutoreleaseReturnValue"
   // CHECK-NEXT: [[T1:%.*]] = call [[CC]]i8* @objc_retainAutoreleasedReturnValue(i8* [[T0]])
   // CHECK-NEXT: store i8* [[T1]],
   // CHECK-NEXT: call [[CC]]void @objc_storeStrong(
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -1085,7 +1085,7 @@
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
 return "movl\t%ebp, %ebp"
-   "\t\t## marker for objc_retainAutoreleaseReturnValue";
+   "\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 };
 
@@ -4880,7 +4880,7 @@
   : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tfp, fp\t\t# marker for objc_retainAutoreleaseReturnValue";
+return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
@@ -5486,7 +5486,7 @@
   }
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
+return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138143: [FPEnv] Enable strict fp for AArch64 in clang

2022-11-21 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138143/new/

https://reviews.llvm.org/D138143

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D146802: [Documentation] improved documentation of diagnostic messages by explaining thier syntax and test of clang by telling which subobject is uninitialized

2023-03-24 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

There is existing documentation of the diagnostics system here, which you could 
extend if something is still unclear or incomplete:

- clang/docs/InternalsManual.rst
- https://clang.llvm.org/docs/InternalsManual.html#the-diagnostics-subsystem


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146802/new/

https://reviews.llvm.org/D146802

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs and fields

2023-04-04 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146242/new/

https://reviews.llvm.org/D146242

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D23610: [ARM] Add pre-defined macros for ROPI, RWPI and FPIC

2017-03-16 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

My patch to the ACLE has now been accepted, so it will be in the next release. 
This is the wording:

  __ARM_ROPI is defined to 1 if the translation unit is being compiled in 
read-only position independent mode. In this mode, all read-only data and 
functions are at a link-time constant offset from the program counter.
  
  __ARM_RWPI is defined to 1 if the translation unit is being compiled in 
read-write position independent mode. In this mode, all writable data is at a 
link-time constant offset from the static base register defined in [AAPCS].
  
  The ROPI and RWPI position independence modes are compatible with each other, 
so the __ARM_ROPI and __ARM_RWPI macros may be defined at the same time.

We're not adding the FPIC macro to the ACLE, because that isn't ARM-specific.


Repository:
  rL LLVM

https://reviews.llvm.org/D23610



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D23610: [ARM] Add pre-defined macros for ROPI and RWPI

2017-03-16 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 updated this revision to Diff 91990.
olista01 retitled this revision from "[ARM] Add pre-defined macros for ROPI, 
RWPI and FPIC" to "[ARM] Add pre-defined macros for ROPI and RWPI".
olista01 edited the summary of this revision.

Repository:
  rL LLVM

https://reviews.llvm.org/D23610

Files:
  include/clang/Basic/LangOptions.def
  include/clang/Driver/Options.td
  lib/Basic/Targets.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/Preprocessor/arm-pic-predefines.c


Index: test/Preprocessor/arm-pic-predefines.c
===
--- /dev/null
+++ test/Preprocessor/arm-pic-predefines.c
@@ -0,0 +1,14 @@
+// REQUIRES: arm-registered-target
+
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o -   | 
FileCheck %s --check-prefix=NO-ROPI --check-prefix=NO-RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -fropi| 
FileCheck %s --check-prefix=ROPI--check-prefix=NO-RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -frwpi| 
FileCheck %s --check-prefix=NO-ROPI --check-prefix=RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -fropi -frwpi | 
FileCheck %s --check-prefix=ROPI--check-prefix=RWPI
+
+// Pre-defined macros for position-independence modes
+
+// NO-ROPI-NOT: #define __APCS_ROPI
+// ROPI: #define __ARM_ROPI
+
+// NO-RWPI-NOT: #define __APCS_RWPI
+// RWPI: #define __ARM_RWPI
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -2071,6 +2071,8 @@
   Opts.MaxTypeAlign = getLastArgIntValue(Args, OPT_fmax_type_align_EQ, 0, 
Diags);
   Opts.AlignDouble = Args.hasArg(OPT_malign_double);
   Opts.PICLevel = getLastArgIntValue(Args, OPT_pic_level, 0, Diags);
+  Opts.ROPI = Args.hasArg(OPT_fropi);
+  Opts.RWPI = Args.hasArg(OPT_frwpi);
   Opts.PIE = Args.hasArg(OPT_pic_is_pie);
   Opts.Static = Args.hasArg(OPT_static_define);
   Opts.DumpRecordLayoutsSimple = Args.hasArg(OPT_fdump_record_layouts_simple);
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -2193,6 +2193,13 @@
   CmdArgs.push_back("-pic-is-pie");
   }
 
+  if (RelocationModel == llvm::Reloc::ROPI ||
+  RelocationModel == llvm::Reloc::ROPI_RWPI)
+CmdArgs.push_back("-fropi");
+  if (RelocationModel == llvm::Reloc::RWPI ||
+  RelocationModel == llvm::Reloc::ROPI_RWPI)
+CmdArgs.push_back("-frwpi");
+
   if (Arg *A = Args.getLastArg(options::OPT_meabi)) {
 CmdArgs.push_back("-meabi");
 CmdArgs.push_back(A->getValue());
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -5577,6 +5577,12 @@
 
 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
   Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
+
+// ACLE position independent code macros.
+if (Opts.ROPI)
+  Builder.defineMacro("__ARM_ROPI", "1");
+if (Opts.RWPI)
+  Builder.defineMacro("__ARM_RWPI", "1");
   }
 
   ArrayRef getTargetBuiltins() const override {
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -1275,9 +1275,9 @@
 def fno_pic : Flag<["-"], "fno-pic">, Group;
 def fpie : Flag<["-"], "fpie">, Group;
 def fno_pie : Flag<["-"], "fno-pie">, Group;
-def fropi : Flag<["-"], "fropi">, Group;
+def fropi : Flag<["-"], "fropi">, Group, Flags<[CC1Option]>;
 def fno_ropi : Flag<["-"], "fno-ropi">, Group;
-def frwpi : Flag<["-"], "frwpi">, Group;
+def frwpi : Flag<["-"], "frwpi">, Group, Flags<[CC1Option]>;
 def fno_rwpi : Flag<["-"], "fno-rwpi">, Group;
 def fplugin_EQ : Joined<["-"], "fplugin=">, Group, 
Flags<[DriverOption]>, MetaVarName<"">,
   HelpText<"Load the named plugin (dynamic shared object)">;
Index: include/clang/Basic/LangOptions.def
===
--- include/clang/Basic/LangOptions.def
+++ include/clang/Basic/LangOptions.def
@@ -163,6 +163,8 @@
 VALUE_LANGOPT(AlignDouble, 1, 0, "Controls if doubles should be 
aligned to 8 bytes (x86 only)")
 COMPATIBLE_VALUE_LANGOPT(PICLevel, 2, 0, "__PIC__ level")
 COMPATIBLE_VALUE_LANGOPT(PIE , 1, 0, "is pie")
+LANGOPT(ROPI , 1, 0, "Read-only position independence")
+LANGOPT(RWPI , 1, 0, "Read-write position 
independence")
 COMPATIBLE_LANGOPT(GNUInline , 1, 0, "GNU inline semantics")
 COMPATIBLE_LANGOPT(NoInlineDefine, 1, 0, "__NO_INLINE__ predefined macro")
 COMPATIBLE_LANGOPT(Deprecated, 1, 0, "__DEPRECATED predefined macro")


Index: test/Preprocessor/arm-pic-predefines.c
=

[PATCH] D31501: [RFC] Integrate clang -cc1as diagnostics into DiagnosticsEngine

2017-03-31 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

What advantages does this have over the current way of printing diagnostics? If 
this is just to get -w and -Werror working, would it not be easier to pass 
those through to the assembler, than to send all diagnostics back through 
clang? We already have some flags in MCTargetOptions that should be able to to 
the same things -w and -Werror do.

On the other hand, if this would enable other features, like -W options to 
promote/suppress categories of assembler warnings, than this might allow us to 
avoid duplicating a lot of clang's diagnostic system in the LLVM SourceMgr. Do 
you have any ideas for how this could be done?


https://reviews.llvm.org/D31501



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D31501: [RFC] Integrate clang -cc1as diagnostics into DiagnosticsEngine

2017-04-03 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

That all sounds sensible from an assembler perspective, especially the ability 
to gradually move diagnostics into categories rather than having one big change 
that touches every assembler diag. However, I've not done much work in clang, 
so it would be good to get someone more familiar with the clang 
diagnostics/driver side of things to have a look at this too.


https://reviews.llvm.org/D31501



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D31765: Skip Unicode character expansion in assembly files

2017-04-07 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

The change itself looks fine, but I have a few comments on the test.

Tests of clang shouldn't actually run the assembler, as I think this one will 
fail if clang is built without the ARM backend. A better way to write the test 
would be to just run the preprocessor, and check that the occurrences of \u 
make it through unmodified.

You should also be able to use clang's -verify option to check the diagnostics, 
so that you don't need a dummy warning to avoid empty FileCheck input. Grep for 
expected-no-diagnostics in the existing tests for examples of this.


https://reviews.llvm.org/D31765



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D31765: Skip Unicode character expansion in assembly files

2017-04-07 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM


https://reviews.llvm.org/D31765



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D23610: [ARM] Add pre-defined macros for ROPI and RWPI

2017-04-18 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

Ping.


Repository:
  rL LLVM

https://reviews.llvm.org/D23610



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D23610: [ARM] Add pre-defined macros for ROPI, RWPI and FPIC

2016-12-14 Thread Oliver Stannard via Phabricator via cfe-commits

olista01 added a comment.

I've proposed a patch to the ACLE to add these macros, but it's stalled in 
review. I've just given it a ping, I'll try to get an answer soon.


Repository:
  rL LLVM

https://reviews.llvm.org/D23610



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

47 matches

Mail list logo