[clang-tools-extra] [RISCV][GISel] Select G_SELECT (PR #67614)
https://github.com/nitinjohnraj updated
https://github.com/llvm/llvm-project/pull/67614
>From 72ba591ed3cc3ab1b6321eaa215ef47a67803dac Mon Sep 17 00:00:00 2001
From: Nitin John Raj
Date: Wed, 27 Sep 2023 15:13:26 -0700
Subject: [PATCH] [RISCV][GISel] Select G_SELECT
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 29 ++
.../instruction-select/select-rv32.mir| 55 +++
.../instruction-select/select-rv64.mir| 55 +++
3 files changed, 139 insertions(+)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 2e690a3624edcb3..de95308a5adc339 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -44,11 +44,17 @@ class RISCVInstructionSelector : public InstructionSelector
{
const TargetRegisterClass *
getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
+ // tblgen-erated 'select' implementation, used as the initial selector for
+ // the patterns that don't require complex C++.
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+
+ // Custom selection methods
bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
+ bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB,
+MachineRegisterInfo &MRI) const;
bool earlySelectShift(unsigned Opc, MachineInstr &I, MachineIRBuilder &MIB,
const MachineRegisterInfo &MRI);
@@ -240,6 +246,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
case TargetOpcode::G_SEXT_INREG:
return selectSExtInreg(MI, MIB);
+ case TargetOpcode::G_SELECT:
+return selectSelect(MI, MIB, MRI);
default:
return false;
}
@@ -389,6 +397,27 @@ bool
RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI,
return true;
}
+bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
+MachineIRBuilder &MIB,
+MachineRegisterInfo &MRI) const {
+ // TODO: Currently we check that the conditional code passed to G_SELECT is
+ // not equal to zero; however, in the future, we might want to try and check
+ // if the conditional code comes from a G_ICMP. If it does, we can directly
+ // use G_ICMP to get the first three input operands of the
+ // Select_GPR_Using_CC_GPR. This might be done here, or in the appropriate
+ // combiner.
+ assert(MI.getOpcode() == TargetOpcode::G_SELECT);
+ MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)
+ .addDef(MI.getOperand(0).getReg())
+ .addReg(MI.getOperand(1).getReg())
+ .addReg(RISCV::X0)
+ .addImm(RISCVCC::COND_NE)
+ .addReg(MI.getOperand(2).getReg())
+ .addReg(MI.getOperand(3).getReg());
+ MI.eraseFromParent();
+ return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI);
+}
+
namespace llvm {
InstructionSelector *
createRISCVInstructionSelector(const RISCVTargetMachine &TM,
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
new file mode 100644
index 000..828835dac8f80ca
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select --simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+---
+name:select_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body:|
+ bb.0:
+liveins: $x10, $x11, $x12
+
+; CHECK-LABEL: name: select_s32
+; CHECK: liveins: $x10, $x11, $x12
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
+; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr =
Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]]
+; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
+; CHECK-NEXT: PseudoRET implicit $x10
+%0:gprb(s32) = COPY $x10
+%1:gprb(s32) = COPY $x11
+%2:gprb(s32) = COPY $x12
+%3:gprb(s32) = G_SELECT %0, %1, %2
+$x10 = COPY %3(s32)
+PseudoRET implicit $x10
+
+...
+---
+name:
[clang] [RISCV][GISel] Select G_SELECT (PR #67614)
https://github.com/nitinjohnraj updated
https://github.com/llvm/llvm-project/pull/67614
>From 72ba591ed3cc3ab1b6321eaa215ef47a67803dac Mon Sep 17 00:00:00 2001
From: Nitin John Raj
Date: Wed, 27 Sep 2023 15:13:26 -0700
Subject: [PATCH] [RISCV][GISel] Select G_SELECT
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 29 ++
.../instruction-select/select-rv32.mir| 55 +++
.../instruction-select/select-rv64.mir| 55 +++
3 files changed, 139 insertions(+)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 2e690a3624edcb3..de95308a5adc339 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -44,11 +44,17 @@ class RISCVInstructionSelector : public InstructionSelector
{
const TargetRegisterClass *
getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
+ // tblgen-erated 'select' implementation, used as the initial selector for
+ // the patterns that don't require complex C++.
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+
+ // Custom selection methods
bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
+ bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB,
+MachineRegisterInfo &MRI) const;
bool earlySelectShift(unsigned Opc, MachineInstr &I, MachineIRBuilder &MIB,
const MachineRegisterInfo &MRI);
@@ -240,6 +246,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
case TargetOpcode::G_SEXT_INREG:
return selectSExtInreg(MI, MIB);
+ case TargetOpcode::G_SELECT:
+return selectSelect(MI, MIB, MRI);
default:
return false;
}
@@ -389,6 +397,27 @@ bool
RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI,
return true;
}
+bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
+MachineIRBuilder &MIB,
+MachineRegisterInfo &MRI) const {
+ // TODO: Currently we check that the conditional code passed to G_SELECT is
+ // not equal to zero; however, in the future, we might want to try and check
+ // if the conditional code comes from a G_ICMP. If it does, we can directly
+ // use G_ICMP to get the first three input operands of the
+ // Select_GPR_Using_CC_GPR. This might be done here, or in the appropriate
+ // combiner.
+ assert(MI.getOpcode() == TargetOpcode::G_SELECT);
+ MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)
+ .addDef(MI.getOperand(0).getReg())
+ .addReg(MI.getOperand(1).getReg())
+ .addReg(RISCV::X0)
+ .addImm(RISCVCC::COND_NE)
+ .addReg(MI.getOperand(2).getReg())
+ .addReg(MI.getOperand(3).getReg());
+ MI.eraseFromParent();
+ return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI);
+}
+
namespace llvm {
InstructionSelector *
createRISCVInstructionSelector(const RISCVTargetMachine &TM,
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
new file mode 100644
index 000..828835dac8f80ca
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select --simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+---
+name:select_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body:|
+ bb.0:
+liveins: $x10, $x11, $x12
+
+; CHECK-LABEL: name: select_s32
+; CHECK: liveins: $x10, $x11, $x12
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
+; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr =
Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]]
+; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
+; CHECK-NEXT: PseudoRET implicit $x10
+%0:gprb(s32) = COPY $x10
+%1:gprb(s32) = COPY $x11
+%2:gprb(s32) = COPY $x12
+%3:gprb(s32) = G_SELECT %0, %1, %2
+$x10 = COPY %3(s32)
+PseudoRET implicit $x10
+
+...
+---
+name:
[clang] [RISCV][GISel] Select G_SELECT (PR #67614)
https://github.com/nitinjohnraj closed https://github.com/llvm/llvm-project/pull/67614 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [RISCV][GISel] Select G_SELECT (PR #67614)
https://github.com/nitinjohnraj closed https://github.com/llvm/llvm-project/pull/67614 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [RISCV][GlobalISel] Select G_FRAME_INDEX (PR #68254)
https://github.com/nitinjohnraj updated
https://github.com/llvm/llvm-project/pull/68254
>From 7a21ee374f2762d0b3b8a68b25be6ac1a71f3cfd Mon Sep 17 00:00:00 2001
From: Nitin John Raj
Date: Tue, 3 Oct 2023 09:40:22 -0700
Subject: [PATCH 1/4] [RISCV][GlobalISel] Select G_FRAME_INDEX
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 12 +++
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 1 +
.../instruction-select/frame-index-rv32.mir | 32 +++
.../instruction-select/frame-index-rv64.mir | 32 +++
4 files changed, 77 insertions(+)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..4c9a15c3afa33c5 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -239,6 +239,18 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
case TargetOpcode::G_SEXT_INREG:
return selectSExtInreg(MI, MIB);
+ case TargetOpcode::G_FRAME_INDEX: {
+// FIXME: We want to replace this with tablegen code that matches for
+// FrameAddrRegImm
+Register DstReg = MI.getOperand(0).getReg();
+
+if (!MRI.getType(DstReg).isPointer())
+ return false;
+
+MI.setDesc(TII.get(RISCV::ADDI));
+MI.addOperand(MachineOperand::CreateImm(0));
+return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+ }
default:
return false;
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 63686bd4bdbc3ae..59aebc7960bc3dc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -127,6 +127,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr
&MI) const {
case TargetOpcode::G_STORE:
break;
case TargetOpcode::G_CONSTANT:
+ case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE:
case TargetOpcode::G_BRCOND:
OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
new file mode 100644
index 000..20747bd1876180c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+%x = alloca i32, align 4
+ret ptr %x
+ }
+
+...
+---
+name:frame_index
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.1.entry:
+; CHECK-LABEL: name: frame_index
+; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+; CHECK-NEXT: $x10 = COPY [[ADDI]]
+; CHECK-NEXT: PseudoRET implicit $x10
+%0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+$x10 = COPY %0(p0)
+PseudoRET implicit $x10
+
+...
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
new file mode 100644
index 000..dc265bda0a68894
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+%x = alloca i32, align 4
+ret ptr %x
+ }
+
+...
+---
+name:frame_index
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.1.entry:
+; CHECK-LABEL: name: frame_index
+; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+; CHECK-NEXT: $x10 = COPY [[ADDI]]
+; CHECK-NEXT: PseudoRET implicit $x10
+%0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+$x10 = COPY %0(p0)
+PseudoRET implicit $x10
+
+...
>From 5d058ee7d1694a416
[clang-tools-extra] [RISCV][GlobalISel] Select G_PTR_ADD (PR #67605)
https://github.com/nitinjohnraj updated
https://github.com/llvm/llvm-project/pull/67605
>From eef2a293d346c05d7fceaa241c0f8489c37e6dea Mon Sep 17 00:00:00 2001
From: Nitin John Raj
Date: Thu, 21 Sep 2023 10:41:50 -0700
Subject: [PATCH 1/3] [RISCV][GlobalISel] Select G_PTR_ADD
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 48 +-
.../instruction-select/ptradd-rv32.mir| 50 +++
.../instruction-select/ptradd-rv64.mir| 50 +++
3 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..cead3a4a6c7fb06 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -45,6 +45,16 @@ class RISCVInstructionSelector : public InstructionSelector {
getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+
+ // A lowering phase that runs before any selection attempts.
+ // Returns true if the instruction was modified.
+ bool preISelLower(MachineInstr &MI, MachineIRBuilder &MIB,
+MachineRegisterInfo &MRI);
+
+ bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI);
+
+ // Custom selection methods
bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
@@ -130,12 +140,14 @@ bool RISCVInstructionSelector::earlySelectShift(
}
bool RISCVInstructionSelector::select(MachineInstr &MI) {
- unsigned Opc = MI.getOpcode();
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
MachineIRBuilder MIB(MI);
+ preISelLower(MI, MIB, MRI);
+ const unsigned Opc = MI.getOpcode();
+
if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
if (Opc == TargetOpcode::PHI || Opc == TargetOpcode::G_PHI) {
const Register DefReg = MI.getOperand(0).getReg();
@@ -225,6 +237,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
switch (Opc) {
case TargetOpcode::G_ANYEXT:
+ case TargetOpcode::G_PTRTOINT:
case TargetOpcode::G_TRUNC:
return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT:
@@ -244,6 +257,39 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
}
+bool RISCVInstructionSelector::replacePtrWithInt(MachineOperand &Op,
+ MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI) {
+ assert(Op.isReg() && "Operand is not a register!");
+ Register PtrReg = Op.getReg();
+ assert(MRI.getType(PtrReg).isPointer() && "Operand is not a pointer!");
+
+ const LLT XLenLLT = LLT::scalar(STI.getXLen());
+ auto PtrToInt = MIB.buildPtrToInt(XLenLLT, PtrReg);
+ MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRRegBankID));
+ MRI.setType(PtrReg, XLenLLT);
+ Op.setReg(PtrToInt.getReg(0));
+ return select(*PtrToInt);
+}
+
+bool RISCVInstructionSelector::preISelLower(MachineInstr &MI,
+MachineIRBuilder &MIB,
+MachineRegisterInfo &MRI) {
+ switch (MI.getOpcode()) {
+ case TargetOpcode::G_PTR_ADD: {
+Register DstReg = MI.getOperand(0).getReg();
+const LLT XLenLLT = LLT::scalar(STI.getXLen());
+
+replacePtrWithInt(MI.getOperand(1), MIB, MRI);
+MI.setDesc(TII.get(TargetOpcode::G_ADD));
+MRI.setType(DstReg, XLenLLT);
+return true;
+ }
+ default:
+return false;
+ }
+}
+
void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
const MachineInstr &MI,
int OpIdx) const {
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
new file mode 100644
index 000..bc0395685b40e9e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+---
+name:add_i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+liveins: $x10, $x11
+
+; CHECK-LABEL: name: add_i32
+; CHECK: liveins: $x10, $x11
+
[clang] [RISCV][GlobalISel] Select G_PTR_ADD (PR #67605)
https://github.com/nitinjohnraj updated
https://github.com/llvm/llvm-project/pull/67605
>From eef2a293d346c05d7fceaa241c0f8489c37e6dea Mon Sep 17 00:00:00 2001
From: Nitin John Raj
Date: Thu, 21 Sep 2023 10:41:50 -0700
Subject: [PATCH 1/3] [RISCV][GlobalISel] Select G_PTR_ADD
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 48 +-
.../instruction-select/ptradd-rv32.mir| 50 +++
.../instruction-select/ptradd-rv64.mir| 50 +++
3 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..cead3a4a6c7fb06 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -45,6 +45,16 @@ class RISCVInstructionSelector : public InstructionSelector {
getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+
+ // A lowering phase that runs before any selection attempts.
+ // Returns true if the instruction was modified.
+ bool preISelLower(MachineInstr &MI, MachineIRBuilder &MIB,
+MachineRegisterInfo &MRI);
+
+ bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI);
+
+ // Custom selection methods
bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
@@ -130,12 +140,14 @@ bool RISCVInstructionSelector::earlySelectShift(
}
bool RISCVInstructionSelector::select(MachineInstr &MI) {
- unsigned Opc = MI.getOpcode();
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
MachineIRBuilder MIB(MI);
+ preISelLower(MI, MIB, MRI);
+ const unsigned Opc = MI.getOpcode();
+
if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
if (Opc == TargetOpcode::PHI || Opc == TargetOpcode::G_PHI) {
const Register DefReg = MI.getOperand(0).getReg();
@@ -225,6 +237,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
switch (Opc) {
case TargetOpcode::G_ANYEXT:
+ case TargetOpcode::G_PTRTOINT:
case TargetOpcode::G_TRUNC:
return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT:
@@ -244,6 +257,39 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
}
+bool RISCVInstructionSelector::replacePtrWithInt(MachineOperand &Op,
+ MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI) {
+ assert(Op.isReg() && "Operand is not a register!");
+ Register PtrReg = Op.getReg();
+ assert(MRI.getType(PtrReg).isPointer() && "Operand is not a pointer!");
+
+ const LLT XLenLLT = LLT::scalar(STI.getXLen());
+ auto PtrToInt = MIB.buildPtrToInt(XLenLLT, PtrReg);
+ MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRRegBankID));
+ MRI.setType(PtrReg, XLenLLT);
+ Op.setReg(PtrToInt.getReg(0));
+ return select(*PtrToInt);
+}
+
+bool RISCVInstructionSelector::preISelLower(MachineInstr &MI,
+MachineIRBuilder &MIB,
+MachineRegisterInfo &MRI) {
+ switch (MI.getOpcode()) {
+ case TargetOpcode::G_PTR_ADD: {
+Register DstReg = MI.getOperand(0).getReg();
+const LLT XLenLLT = LLT::scalar(STI.getXLen());
+
+replacePtrWithInt(MI.getOperand(1), MIB, MRI);
+MI.setDesc(TII.get(TargetOpcode::G_ADD));
+MRI.setType(DstReg, XLenLLT);
+return true;
+ }
+ default:
+return false;
+ }
+}
+
void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
const MachineInstr &MI,
int OpIdx) const {
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
new file mode 100644
index 000..bc0395685b40e9e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+---
+name:add_i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+liveins: $x10, $x11
+
+; CHECK-LABEL: name: add_i32
+; CHECK: liveins: $x10, $x11
+
[clang-tools-extra] [RISCV][GlobalISel] Select G_PTR_ADD (PR #67605)
https://github.com/nitinjohnraj closed https://github.com/llvm/llvm-project/pull/67605 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][GlobalISel] Select G_PTR_ADD (PR #67605)
https://github.com/nitinjohnraj closed https://github.com/llvm/llvm-project/pull/67605 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [RISCV][GlobalISel] Select G_FRAME_INDEX (PR #68254)
https://github.com/nitinjohnraj updated
https://github.com/llvm/llvm-project/pull/68254
>From 7a21ee374f2762d0b3b8a68b25be6ac1a71f3cfd Mon Sep 17 00:00:00 2001
From: Nitin John Raj
Date: Tue, 3 Oct 2023 09:40:22 -0700
Subject: [PATCH 1/5] [RISCV][GlobalISel] Select G_FRAME_INDEX
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 12 +++
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 1 +
.../instruction-select/frame-index-rv32.mir | 32 +++
.../instruction-select/frame-index-rv64.mir | 32 +++
4 files changed, 77 insertions(+)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..4c9a15c3afa33c5 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -239,6 +239,18 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
case TargetOpcode::G_SEXT_INREG:
return selectSExtInreg(MI, MIB);
+ case TargetOpcode::G_FRAME_INDEX: {
+// FIXME: We want to replace this with tablegen code that matches for
+// FrameAddrRegImm
+Register DstReg = MI.getOperand(0).getReg();
+
+if (!MRI.getType(DstReg).isPointer())
+ return false;
+
+MI.setDesc(TII.get(RISCV::ADDI));
+MI.addOperand(MachineOperand::CreateImm(0));
+return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+ }
default:
return false;
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 63686bd4bdbc3ae..59aebc7960bc3dc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -127,6 +127,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr
&MI) const {
case TargetOpcode::G_STORE:
break;
case TargetOpcode::G_CONSTANT:
+ case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE:
case TargetOpcode::G_BRCOND:
OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
new file mode 100644
index 000..20747bd1876180c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+%x = alloca i32, align 4
+ret ptr %x
+ }
+
+...
+---
+name:frame_index
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.1.entry:
+; CHECK-LABEL: name: frame_index
+; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+; CHECK-NEXT: $x10 = COPY [[ADDI]]
+; CHECK-NEXT: PseudoRET implicit $x10
+%0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+$x10 = COPY %0(p0)
+PseudoRET implicit $x10
+
+...
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
new file mode 100644
index 000..dc265bda0a68894
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+%x = alloca i32, align 4
+ret ptr %x
+ }
+
+...
+---
+name:frame_index
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.1.entry:
+; CHECK-LABEL: name: frame_index
+; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+; CHECK-NEXT: $x10 = COPY [[ADDI]]
+; CHECK-NEXT: PseudoRET implicit $x10
+%0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+$x10 = COPY %0(p0)
+PseudoRET implicit $x10
+
+...
>From 5d058ee7d1694a416
[libunwind] [RISCV][GlobalISel] Select G_FRAME_INDEX (PR #68254)
https://github.com/nitinjohnraj closed https://github.com/llvm/llvm-project/pull/68254 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
