https://github.com/nitinjohnraj updated
https://github.com/llvm/llvm-project/pull/68254
>From 7a21ee374f2762d0b3b8a68b25be6ac1a71f3cfd Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin....@sifive.com>
Date: Tue, 3 Oct 2023 09:40:22 -0700
Subject: [PATCH 1/5] [RISCV][GlobalISel] Select G_FRAME_INDEX
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 12 +++++++
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 1 +
.../instruction-select/frame-index-rv32.mir | 32 +++++++++++++++++++
.../instruction-select/frame-index-rv64.mir | 32 +++++++++++++++++++
4 files changed, 77 insertions(+)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..4c9a15c3afa33c5 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -239,6 +239,18 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
case TargetOpcode::G_SEXT_INREG:
return selectSExtInreg(MI, MIB);
+ case TargetOpcode::G_FRAME_INDEX: {
+ // FIXME: We want to replace this with tablegen code that matches for
+ // FrameAddrRegImm
+ Register DstReg = MI.getOperand(0).getReg();
+
+ if (!MRI.getType(DstReg).isPointer())
+ return false;
+
+ MI.setDesc(TII.get(RISCV::ADDI));
+ MI.addOperand(MachineOperand::CreateImm(0));
+ return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+ }
default:
return false;
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 63686bd4bdbc3ae..59aebc7960bc3dc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -127,6 +127,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr
&MI) const {
case TargetOpcode::G_STORE:
break;
case TargetOpcode::G_CONSTANT:
+ case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE:
case TargetOpcode::G_BRCOND:
OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
new file mode 100644
index 000000000000000..20747bd1876180c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+ %x = alloca i32, align 4
+ ret ptr %x
+ }
+
+...
+---
+name: frame_index
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: frame_index
+ ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+ ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+ $x10 = COPY %0(p0)
+ PseudoRET implicit $x10
+
+...
diff --git
a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
new file mode 100644
index 000000000000000..dc265bda0a68894
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+ %x = alloca i32, align 4
+ ret ptr %x
+ }
+
+...
+---
+name: frame_index
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: frame_index
+ ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+ ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+ $x10 = COPY %0(p0)
+ PseudoRET implicit $x10
+
+...
>From 5d058ee7d1694a41663e992ae174bb01ee9901db Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin....@sifive.com>
Date: Wed, 4 Oct 2023 13:20:10 -0700
Subject: [PATCH 2/5] Made comment clearer
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4c9a15c3afa33c5..58143c174259857 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -240,8 +240,9 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
case TargetOpcode::G_SEXT_INREG:
return selectSExtInreg(MI, MIB);
case TargetOpcode::G_FRAME_INDEX: {
- // FIXME: We want to replace this with tablegen code that matches for
- // FrameAddrRegImm
+ // TODO: We may want to replace this code with the SelectionDAG patterns,
+ // which fail to get imported because it uses FrameAddrRegImm, which is a
+ // ComplexPattern
Register DstReg = MI.getOperand(0).getReg();
if (!MRI.getType(DstReg).isPointer())
>From 6bae77c5e211022337d987fbc6eb03c2b187b63f Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin....@sifive.com>
Date: Fri, 6 Oct 2023 13:11:21 -0700
Subject: [PATCH 3/5] Remove unnecessary pointer check
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 4 ----
1 file changed, 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 58143c174259857..a8b0550e642795f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -244,10 +244,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
// which fail to get imported because it uses FrameAddrRegImm, which is a
// ComplexPattern
Register DstReg = MI.getOperand(0).getReg();
-
- if (!MRI.getType(DstReg).isPointer())
- return false;
-
MI.setDesc(TII.get(RISCV::ADDI));
MI.addOperand(MachineOperand::CreateImm(0));
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
>From 26976ebe2b844c3f424b5b23d288cbb04c66ec70 Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin....@sifive.com>
Date: Fri, 6 Oct 2023 13:21:57 -0700
Subject: [PATCH 4/5] Remove unused DstReg
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index a8b0550e642795f..c01501f56715813 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -243,7 +243,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
// TODO: We may want to replace this code with the SelectionDAG patterns,
// which fail to get imported because it uses FrameAddrRegImm, which is a
// ComplexPattern
- Register DstReg = MI.getOperand(0).getReg();
MI.setDesc(TII.get(RISCV::ADDI));
MI.addOperand(MachineOperand::CreateImm(0));
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
>From 2de47e3c351e48f3b4328088ed33bddbde6790d3 Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin....@sifive.com>
Date: Tue, 10 Oct 2023 11:53:00 -0700
Subject: [PATCH 5/5] Add test for frame index register bank selection
---
.../GlobalISel/regbankselect/frame-index.mir | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
new file mode 100644
index 000000000000000..f701ef616962552
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+ %x = alloca i32, align 4
+ ret ptr %x
+ }
+
+...
+---
+name: frame_index
+legalized: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: frame_index
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %stack.0.x
+ ; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = G_FRAME_INDEX %stack.0.x
+ $x10 = COPY %0(p0)
+ PseudoRET implicit $x10
+
+...
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