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[PATCH] D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts

2020-05-20 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

Ping.


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[PATCH] D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts

2020-05-26 Thread Lucas Prates via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG98cad555e291: [Clang][AArch64] Capturing proper pointer 
alignment for Neon vld1 intrinsicts (authored by pratlucas).

Changed prior to commit:
  https://reviews.llvm.org/D79721?vs=263188&id=266138#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79721/new/

https://reviews.llvm.org/D79721

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-intrinsics.c

Index: clang/test/CodeGen/aarch64-neon-intrinsics.c
===
--- clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -8956,7 +8956,7 @@
 
 // CHECK-LABEL: @test_vld1q_u8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 uint8x16_t test_vld1q_u8(uint8_t const *a) {
   return vld1q_u8(a);
@@ -8965,7 +8965,7 @@
 // CHECK-LABEL: @test_vld1q_u16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 uint16x8_t test_vld1q_u16(uint16_t const *a) {
   return vld1q_u16(a);
@@ -8974,7 +8974,7 @@
 // CHECK-LABEL: @test_vld1q_u32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 uint32x4_t test_vld1q_u32(uint32_t const *a) {
   return vld1q_u32(a);
@@ -8983,7 +8983,7 @@
 // CHECK-LABEL: @test_vld1q_u64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 uint64x2_t test_vld1q_u64(uint64_t const *a) {
   return vld1q_u64(a);
@@ -8991,7 +8991,7 @@
 
 // CHECK-LABEL: @test_vld1q_s8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 int8x16_t test_vld1q_s8(int8_t const *a) {
   return vld1q_s8(a);
@@ -9000,7 +9000,7 @@
 // CHECK-LABEL: @test_vld1q_s16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 int16x8_t test_vld1q_s16(int16_t const *a) {
   return vld1q_s16(a);
@@ -9009,7 +9009,7 @@
 // CHECK-LABEL: @test_vld1q_s32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 int32x4_t test_vld1q_s32(int32_t const *a) {
   return vld1q_s32(a);
@@ -9018,7 +9018,7 @@
 // CHECK-LABEL: @test_vld1q_s64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 int64x2_t test_vld1q_s64(int64_t const *a) {
   return vld1q_s64(a);
@@ -9027,7 +9027,7 @@
 // CHECK-LABEL: @test_vld1q_f16(
 // CHECK:   [[TMP0:%.*]] = bitcast half* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
-// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]], align 2
 // CHECK:   ret <8 x half> [[TMP2]]
 float16x8_t test_vld1q_f16(float16_t const *a) {
   return vld1q_f16(a);
@@ -9036,7 +9036,7 @@
 // CHECK-LABEL: @test_vld1q_f32(
 // CHECK:   [[TMP0:%.*]] = bitcast float* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x float>*
-// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
 // CHECK:   ret <4 x float> [[TMP2]]
 float32x4_t test_vld1q_f32(float32_t const *a) {
   return vld1q_f32(a);
@@ -9045,7 +9045,7 @@
 // CHECK-LABEL: @test_vld1q_f64(
 // CHECK:   [[TMP0:%.*]] = bitcast double* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x double>*
-// CHECK:   [[TMP2:%.*]] = load

[PATCH] D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts

2020-05-27 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 266504.
pratlucas added a comment.

Hi @efriedma and @plotf,

Thank you the reduced test and for reverting the original patch.
I've updated it to avoid the issue while still capturing the proper argument 
alignment.
Do you mind taking a look before a reland it?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79721/new/

https://reviews.llvm.org/D79721

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-intrinsics.c

Index: clang/test/CodeGen/aarch64-neon-intrinsics.c
===
--- clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -8956,7 +8956,7 @@
 
 // CHECK-LABEL: @test_vld1q_u8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 uint8x16_t test_vld1q_u8(uint8_t const *a) {
   return vld1q_u8(a);
@@ -8965,7 +8965,7 @@
 // CHECK-LABEL: @test_vld1q_u16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 uint16x8_t test_vld1q_u16(uint16_t const *a) {
   return vld1q_u16(a);
@@ -8974,7 +8974,7 @@
 // CHECK-LABEL: @test_vld1q_u32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 uint32x4_t test_vld1q_u32(uint32_t const *a) {
   return vld1q_u32(a);
@@ -8983,7 +8983,7 @@
 // CHECK-LABEL: @test_vld1q_u64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 uint64x2_t test_vld1q_u64(uint64_t const *a) {
   return vld1q_u64(a);
@@ -8991,7 +8991,7 @@
 
 // CHECK-LABEL: @test_vld1q_s8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 int8x16_t test_vld1q_s8(int8_t const *a) {
   return vld1q_s8(a);
@@ -9000,7 +9000,7 @@
 // CHECK-LABEL: @test_vld1q_s16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 int16x8_t test_vld1q_s16(int16_t const *a) {
   return vld1q_s16(a);
@@ -9009,7 +9009,7 @@
 // CHECK-LABEL: @test_vld1q_s32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 int32x4_t test_vld1q_s32(int32_t const *a) {
   return vld1q_s32(a);
@@ -9018,7 +9018,7 @@
 // CHECK-LABEL: @test_vld1q_s64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 int64x2_t test_vld1q_s64(int64_t const *a) {
   return vld1q_s64(a);
@@ -9027,7 +9027,7 @@
 // CHECK-LABEL: @test_vld1q_f16(
 // CHECK:   [[TMP0:%.*]] = bitcast half* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
-// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]], align 2
 // CHECK:   ret <8 x half> [[TMP2]]
 float16x8_t test_vld1q_f16(float16_t const *a) {
   return vld1q_f16(a);
@@ -9036,7 +9036,7 @@
 // CHECK-LABEL: @test_vld1q_f32(
 // CHECK:   [[TMP0:%.*]] = bitcast float* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x float>*
-// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
 // CHECK:   ret <4 x float> [[TMP2]]
 float32x4_t test_vld1q_f32(float32_t const *a) {
   return vld1q_f32(a);
@@ -9045,7 +9045,7 @@
 // CHECK-LABEL: @test_vld1q_f64(
 // CHECK:   [[TMP0:%.*]] = bitcast double* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x double>*
-// CHECK:   [[TMP2:%.*]]

[PATCH] D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts

2020-06-02 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 267905.
pratlucas added a comment.

Addressing review comments and extending tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79721/new/

https://reviews.llvm.org/D79721

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-intrinsics.c

Index: clang/test/CodeGen/aarch64-neon-intrinsics.c
===
--- clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -8956,7 +8956,7 @@
 
 // CHECK-LABEL: @test_vld1q_u8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 uint8x16_t test_vld1q_u8(uint8_t const *a) {
   return vld1q_u8(a);
@@ -8965,7 +8965,7 @@
 // CHECK-LABEL: @test_vld1q_u16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 uint16x8_t test_vld1q_u16(uint16_t const *a) {
   return vld1q_u16(a);
@@ -8974,7 +8974,7 @@
 // CHECK-LABEL: @test_vld1q_u32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 uint32x4_t test_vld1q_u32(uint32_t const *a) {
   return vld1q_u32(a);
@@ -8983,7 +8983,7 @@
 // CHECK-LABEL: @test_vld1q_u64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 uint64x2_t test_vld1q_u64(uint64_t const *a) {
   return vld1q_u64(a);
@@ -8991,7 +8991,7 @@
 
 // CHECK-LABEL: @test_vld1q_s8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 int8x16_t test_vld1q_s8(int8_t const *a) {
   return vld1q_s8(a);
@@ -9000,7 +9000,7 @@
 // CHECK-LABEL: @test_vld1q_s16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 int16x8_t test_vld1q_s16(int16_t const *a) {
   return vld1q_s16(a);
@@ -9009,7 +9009,7 @@
 // CHECK-LABEL: @test_vld1q_s32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 int32x4_t test_vld1q_s32(int32_t const *a) {
   return vld1q_s32(a);
@@ -9018,7 +9018,7 @@
 // CHECK-LABEL: @test_vld1q_s64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 int64x2_t test_vld1q_s64(int64_t const *a) {
   return vld1q_s64(a);
@@ -9027,7 +9027,7 @@
 // CHECK-LABEL: @test_vld1q_f16(
 // CHECK:   [[TMP0:%.*]] = bitcast half* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
-// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]], align 2
 // CHECK:   ret <8 x half> [[TMP2]]
 float16x8_t test_vld1q_f16(float16_t const *a) {
   return vld1q_f16(a);
@@ -9036,7 +9036,7 @@
 // CHECK-LABEL: @test_vld1q_f32(
 // CHECK:   [[TMP0:%.*]] = bitcast float* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x float>*
-// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
 // CHECK:   ret <4 x float> [[TMP2]]
 float32x4_t test_vld1q_f32(float32_t const *a) {
   return vld1q_f32(a);
@@ -9045,7 +9045,7 @@
 // CHECK-LABEL: @test_vld1q_f64(
 // CHECK:   [[TMP0:%.*]] = bitcast double* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x double>*
-// CHECK:   [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 8
 // CHECK:   ret <2 x double> [[TMP2]]
 float64x2_t te

[PATCH] D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts

2020-06-02 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked 5 inline comments as done.
pratlucas added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:10334
 Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(VTy));
-auto Alignment = CharUnits::fromQuantity(
-BuiltinID == NEON::BI__builtin_neon_vld1_v ? 8 : 16);
-return Builder.CreateAlignedLoad(VTy, Ops[0], Alignment);
+return Builder.CreateAlignedLoad(VTy, Ops[0], PtrOp0.getAlignment());
   }

efriedma wrote:
> Might as well just `return Builder.CreateLoad(VTy, PtrOp0);`
The bitcast of the pointer for the proper vector type is required prior to the 
load, so `Builder.CreateLoad` may not be the best fit here.


Repository:
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2020-06-02 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:10366
+auto Alignment = CGM.getNaturalPointeeTypeAlignment(
+E->getArg(0)->IgnoreParenCasts()->getType());
 Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(VTy));

LukeGeeson wrote:
> simon_tatham wrote:
> > What effect is this change of strategy having on the alignment computation, 
> > for the already-supported instances of this builtin?
> > 
> > It //looks// to me as if `__builtin_neon_vld1_v` with (say) a `uint8_t *` 
> > pointer argument will now compute `Alignment=1` (the natural alignment of 
> > the pointee type), whereas it would previously have computed `Alignment=8` 
> > (the size of the whole vector being loaded or stored).
> > 
> > Is that intentional? Or accidental? Or have I completely misunderstood 
> > what's going on?
> > 
> > (Whichever of the three, some discussion in the commit message would be a 
> > good idea, explaining why this change does or does not make a difference, 
> > as appropriate.)
> Clang was incorrectly assuming that all the pointers from which loads were 
> being generated for vld1 intrinsics were aligned according to according to 
> the intrinsics result type. This causes alignment faults on the code 
> generated by the backend.
> This fixes the issue so that alignment is based on the type of the pointer 
> provided to as input to the intrinsic.
>  
> @pratlucas has done some work on this in parallel 
> https://reviews.llvm.org/D79721 which has been approved and may overrule this 
> particular line of code. 
> 
> I shall add a note to the commit message, and tentatively mark this as fixed, 
> given it's liable to adopt the work of Lucas.
> 
Hi @LukeGeeson ,
Just as a heads up, some changes to this implementations were requested on 
D79721.
The usage of `CGM.getNaturalPointeeTypeAlignment` and `IgnoreParenCasts()` was 
causing problems on certain argument types, so the alignment is now captured 
from the expression itself when it is emitted.


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[PATCH] D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts

2020-06-03 Thread Lucas Prates via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG8beaba13b8a6: [Clang][AArch64] Capturing proper pointer 
alignment for Neon vld1 intrinsicts (authored by pratlucas).

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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-intrinsics.c

Index: clang/test/CodeGen/aarch64-neon-intrinsics.c
===
--- clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -8956,7 +8956,7 @@
 
 // CHECK-LABEL: @test_vld1q_u8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 uint8x16_t test_vld1q_u8(uint8_t const *a) {
   return vld1q_u8(a);
@@ -8965,7 +8965,7 @@
 // CHECK-LABEL: @test_vld1q_u16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 uint16x8_t test_vld1q_u16(uint16_t const *a) {
   return vld1q_u16(a);
@@ -8974,7 +8974,7 @@
 // CHECK-LABEL: @test_vld1q_u32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 uint32x4_t test_vld1q_u32(uint32_t const *a) {
   return vld1q_u32(a);
@@ -8983,7 +8983,7 @@
 // CHECK-LABEL: @test_vld1q_u64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 uint64x2_t test_vld1q_u64(uint64_t const *a) {
   return vld1q_u64(a);
@@ -8991,7 +8991,7 @@
 
 // CHECK-LABEL: @test_vld1q_s8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 int8x16_t test_vld1q_s8(int8_t const *a) {
   return vld1q_s8(a);
@@ -9000,7 +9000,7 @@
 // CHECK-LABEL: @test_vld1q_s16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 int16x8_t test_vld1q_s16(int16_t const *a) {
   return vld1q_s16(a);
@@ -9009,7 +9009,7 @@
 // CHECK-LABEL: @test_vld1q_s32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 int32x4_t test_vld1q_s32(int32_t const *a) {
   return vld1q_s32(a);
@@ -9018,7 +9018,7 @@
 // CHECK-LABEL: @test_vld1q_s64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 int64x2_t test_vld1q_s64(int64_t const *a) {
   return vld1q_s64(a);
@@ -9027,7 +9027,7 @@
 // CHECK-LABEL: @test_vld1q_f16(
 // CHECK:   [[TMP0:%.*]] = bitcast half* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
-// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]], align 2
 // CHECK:   ret <8 x half> [[TMP2]]
 float16x8_t test_vld1q_f16(float16_t const *a) {
   return vld1q_f16(a);
@@ -9036,7 +9036,7 @@
 // CHECK-LABEL: @test_vld1q_f32(
 // CHECK:   [[TMP0:%.*]] = bitcast float* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x float>*
-// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
 // CHECK:   ret <4 x float> [[TMP2]]
 float32x4_t test_vld1q_f32(float32_t const *a) {
   return vld1q_f32(a);
@@ -9045,7 +9045,7 @@
 // CHECK-LABEL: @test_vld1q_f64(
 // CHECK:   [[TMP0:%.*]] = bitcast double* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x double>*
-// CHECK:   [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x double>,

[PATCH] D75903: [AArch64][CodeGen] Fixing stack alignment of HFA arguments on AArch64 PCS

2020-04-06 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

From the AAPCS64's Parameter Passing Rules section 
(https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#642parameter-passing-rules),
 I believe the proposed handling is correct. The HFA related rules described in 
this section are:

  Stage B – Pre-padding and extension of arguments
  [...]
  B.2   If the argument type is an HFA or an HVA, then the argument is used 
unmodified.
  [...]

  Stage C – Assignment of arguments to registers and stack
  [...]
  C.2   If the argument is an HFA or an HVA and there are sufficient 
unallocated SIMD and Floating-point registers (NSRN + number of members <= 8), 
then the argument is allocated to SIMD and Floating-point Registers (with one 
register per member of the HFA or HVA). The NSRN is incremented by the number 
of registers used. The argument has now been allocated.
  C.3   If the argument is an HFA or an HVA then the NSRN is set to 8 and the 
size of the argument is rounded up to the nearest multiple of 8 bytes.
  C.4   If the argument is an HFA, an HVA, a Quad-precision Floating-point or 
Short Vector Type then the NSAA is rounded up to the larger of 8 or the Natural 
Alignment of the argument’s type.
  [...]

As per rule `C.4`, the argument should be allocated on the stack address 
rounded to the larger of 8 and its Natural Alignment, which is 32 according to 
what is specified by the Composite Types rules in sectoin 5.6 of that same 
document 
(https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#composite-types):

  5.6   Composite Types
  [...]
  - The natural alignment of a composite type is the maximum of each of the 
member alignments of the 'top-level' members of the composite type i.e. before 
any alignment adjustment of the entire composite is applied

In regards to the compatibility with other compilers, I'm not sure that 
following what seems to be an uncompliant behavior would be the best way to 
proceed. @rnk and @ostannard, what would be your take on this?


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[PATCH] D75169: [ARM] Enforcing calling convention for half-precision FP arguments and returns for big-endian AArch32

2020-04-08 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

Ping.


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[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-08 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: llvm-commits, cfe-commits, danielkiss, hiraditya, 
kristof.beyls.
Herald added projects: clang, LLVM.
pratlucas added reviewers: chill, rjmccall, ostannard.
pratlucas added a parent revision: D75169: [ARM] Enforcing calling convention 
for half-precision FP arguments and returns for big-endian AArch32.

As half-precision floating point arguments and returns were previously
coerced to either float or int32 by clang's codegen, the CMSE handling
of those was also performed in clang's side by zeroing the unused MSBs
of the coercer values.

This patch moves this handling to the backend's calling convention
lowering, making sure the high bits of the registers used by
half-precision arguments and returns are zeroed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81428

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/cmse-clear-fp16.c
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -809,3 +809,379 @@
   ret void
 }
 
+define arm_aapcs_vfpcc half @h1(half (half)* nocapture %hptr) #10 {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-81M-LABEL: h1:
+; CHECK-81M:   @ %bb.0:
+; CHECK-81M-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-81M-NEXT:push {r7, lr}
+; CHECK-81M-NEXT:sub sp, #4
+; CHECK-81M-NEXT:vldr s0, .LCPI11_0
+; CHECK-81M-NEXT:blx r0
+; CHECK-81M-NEXT:vmov r0, s0
+; CHECK-81M-NEXT:uxth r0, r0
+; CHECK-81M-NEXT:vmov s0, r0
+; CHECK-81M-NEXT:add sp, #4
+; CHECK-81M-NEXT:pop.w {r7, lr}
+; CHECK-81M-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-81M-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-81M-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-81M-NEXT:bxns lr
+; CHECK-81M-NEXT:.p2align 2
+; CHECK-81M-NEXT:  @ %bb.1:
+; CHECK-81M-NEXT:  .LCPI11_0:
+; CHECK-81M-NEXT:.long 0x4900 @ float 2.61874657E-41
+  %call = call arm_aapcs_vfpcc half %hptr(half 10.0) #11
+  ret half %call
+}
+
+attributes #10 = { "cmse_nonsecure_entry" nounwind }
+attributes #11 = { nounwind }
+
+define arm_aapcs_vfpcc half @h2(half (half)* nocapture %hptr) #12 {
+; CHECK-8M-LABEL: h2:
+; CHECK-8M:   @ %bb.0: @ %entry
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI12_0
+; CHECK-8M-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-NEXT:bic r0, r0, #1
+; CHECK-8M-NEXT:sub sp, #136
+; CHECK-8M-NEXT:vmov r12, s0
+; CHECK-8M-NEXT:vlstm sp
+; CHECK-8M-NEXT:vmov s0, r12
+; CHECK-8M-NEXT:ldr r1, [sp, #64]
+; CHECK-8M-NEXT:bic r1, r1, #159
+; CHECK-8M-NEXT:bic r1, r1, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r1
+; CHECK-8M-NEXT:mov r1, r0
+; CHECK-8M-NEXT:mov r2, r0
+; CHECK-8M-NEXT:mov r3, r0
+; CHECK-8M-NEXT:mov r4, r0
+; CHECK-8M-NEXT:mov r5, r0
+; CHECK-8M-NEXT:mov r6, r0
+; CHECK-8M-NEXT:mov r7, r0
+; CHECK-8M-NEXT:mov r8, r0
+; CHECK-8M-NEXT:mov r9, r0
+; CHECK-8M-NEXT:mov r10, r0
+; CHECK-8M-NEXT:mov r11, r0
+; CHECK-8M-NEXT:msr apsr_nzcvqg, r0
+; CHECK-8M-NEXT:blxns r0
+; CHECK-8M-NEXT:vmov r12, s0
+; CHECK-8M-NEXT:vlldm sp
+; CHECK-8M-NEXT:vmov s0, r12
+; CHECK-8M-NEXT:add sp, #136
+; CHECK-8M-NEXT:pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-NEXT:pop {r7, pc}
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:  .LCPI12_0:
+; CHECK-8M-NEX

[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-09 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 269452.
pratlucas added a comment.

Moving the clean-up of the Clang-side handling to a separate patch.


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Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -809,3 +809,379 @@
   ret void
 }
 
+define arm_aapcs_vfpcc half @h1(half (half)* nocapture %hptr) #10 {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-81M-LABEL: h1:
+; CHECK-81M:   @ %bb.0:
+; CHECK-81M-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-81M-NEXT:push {r7, lr}
+; CHECK-81M-NEXT:sub sp, #4
+; CHECK-81M-NEXT:vldr s0, .LCPI11_0
+; CHECK-81M-NEXT:blx r0
+; CHECK-81M-NEXT:vmov r0, s0
+; CHECK-81M-NEXT:uxth r0, r0
+; CHECK-81M-NEXT:vmov s0, r0
+; CHECK-81M-NEXT:add sp, #4
+; CHECK-81M-NEXT:pop.w {r7, lr}
+; CHECK-81M-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-81M-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-81M-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-81M-NEXT:bxns lr
+; CHECK-81M-NEXT:.p2align 2
+; CHECK-81M-NEXT:  @ %bb.1:
+; CHECK-81M-NEXT:  .LCPI11_0:
+; CHECK-81M-NEXT:.long 0x4900 @ float 2.61874657E-41
+  %call = call arm_aapcs_vfpcc half %hptr(half 10.0) #11
+  ret half %call
+}
+
+attributes #10 = { "cmse_nonsecure_entry" nounwind }
+attributes #11 = { nounwind }
+
+define arm_aapcs_vfpcc half @h2(half (half)* nocapture %hptr) #12 {
+; CHECK-8M-LABEL: h2:
+; CHECK-8M:   @ %bb.0: @ %entry
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI12_0
+; CHECK-8M-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-NEXT:bic r0, r0, #1
+; CHECK-8M-NEXT:sub sp, #136
+; CHECK-8M-NEXT:vmov r12, s0
+; CHECK-8M-NEXT:vlstm sp
+; CHECK-8M-NEXT:vmov s0, r12
+; CHECK-8M-NEXT:ldr r1, [sp, #64]
+; CHECK-8M-NEXT:bic r1, r1, #159
+; CHECK-8M-NEXT:bic r1, r1, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r1
+; CHECK-8M-NEXT:mov r1, r0
+; CHECK-8M-NEXT:mov r2, r0
+; CHECK-8M-NEXT:mov r3, r0
+; CHECK-8M-NEXT:mov r4, r0
+; CHECK-8M-NEXT:mov r5, r0
+; CHECK-8M-NEXT:mov r6, r0
+; CHECK-8M-NEXT:mov r7, r0
+; CHECK-8M-NEXT:mov r8, r0
+; CHECK-8M-NEXT:mov r9, r0
+; CHECK-8M-NEXT:mov r10, r0
+; CHECK-8M-NEXT:mov r11, r0
+; CHECK-8M-NEXT:msr apsr_nzcvqg, r0
+; CHECK-8M-NEXT:blxns r0
+; CHECK-8M-NEXT:vmov r12, s0
+; CHECK-8M-NEXT:vlldm sp
+; CHECK-8M-NEXT:vmov s0, r12
+; CHECK-8M-NEXT:add sp, #136
+; CHECK-8M-NEXT:pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-NEXT:pop {r7, pc}
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:  .LCPI12_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-81M-LABEL: h2:
+; CHECK-81M:   @ %bb.0: @ %entry
+; CHECK-81M-NEXT:push {r7, lr}
+; CHECK-81M-NEXT:vldr s0, .LCPI12_0
+; CHECK-81M-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-81M-NEXT:bic r0, r0, #1
+; CHECK-81M-NEXT:vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+; CHECK-81M-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
+; CHECK-81M-NEXT:vstr fpcxts, [sp, #-8]!
+; CHECK-81M-NEXT:clrm {r1, r2, r3, r4, r5, r6

[PATCH] D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen

2020-06-09 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: cfe-commits, danielkiss, dmgreen, kristof.beyls.
Herald added a project: clang.
pratlucas added a parent revision: D81428: [ARM] Moving CMSE handling of half 
arguments and return to the backend.
pratlucas added reviewers: rjmccall, chill, ostannard, dnsampaio.

On the process of moving the argument lowering handling for
half-precision floating point arguments and returns to the backend, this
patch removes the code that was responsible for handling the coercion of
those arguments in Clang's Codegen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81451

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm-fp16-arguments.c
  clang/test/CodeGen/arm-mve-intrinsics/compare.c
  clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
  clang/test/CodeGen/arm-mve-intrinsics/dup.c
  clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
  clang/test/CodeGen/arm-mve-intrinsics/ternary.c
  clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
  clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
  clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
  clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
  clang/test/CodeGen/cmse-clear-fp16.c

Index: clang/test/CodeGen/cmse-clear-fp16.c
===
--- clang/test/CodeGen/cmse-clear-fp16.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// RUN: %clang_cc1 -triple thumbv8m.main -O0 -mcmse  -S -emit-llvm \
-// RUN:-fallow-half-arguments-and-returns %s -o - | \
-// RUN:FileCheck %s --check-prefixes=CHECK,CHECK-NOPT-SOFT
-// RUN: %clang_cc1 -triple thumbv8m.main -O2 -mcmse  -S -emit-llvm \
-// RUN:-fallow-half-arguments-and-returns %s -o - | \
-// RUN:FileCheck %s --check-prefixes=CHECK,CHECK-OPT-SOFT
-// RUN: %clang_cc1 -triple thumbv8m.main -O0 -mcmse  -S -emit-llvm \
-// RUN:-fallow-half-arguments-and-returns -mfloat-abi hard %s -o - | \
-// RUN:FileCheck %s --check-prefixes=CHECK,CHECK-NOPT-HARD
-// RUN: %clang_cc1 -triple thumbv8m.main -O2 -mcmse  -S -emit-llvm \
-// RUN:-fallow-half-arguments-and-returns -mfloat-abi hard %s -o - | \
-// RUN:FileCheck %s --check-prefixes=CHECK,CHECK-OPT-HARD
-
-__fp16 g0();
-__attribute__((cmse_nonsecure_entry)) __fp16 f0() {
-  return g0();
-}
-// CHECK:   define {{.*}}@f0()
-
-// CHECK-NOPT-SOFT: %[[V0:.*]] = load i32
-// CHECK-NOPT-SOFT: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-NOPT-SOFT: ret i32 %[[V1]]
-
-// CHECK-OPT-SOFT: %[[V0:.*]] = tail call {{.*}} @g0
-// CHECK-OPT-SOFT: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-OPT-SOFT: ret i32 %[[V1]]
-
-// CHECK-NOPT-HARD: %[[V0:.*]] = bitcast float {{.*}} to i32
-// CHECK-NOPT-HARD: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-NOPT-HARD: %[[V2:.*]] = bitcast i32 %[[V1]] to float
-// CHECK-NOPT-HARD: ret float %[[V2]]
-
-// CHECK-OPT-HARD: %[[V0:.*]] = bitcast float {{.*}} to i32
-// CHECK-OPT-HARD: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-OPT-HARD: %[[V2:.*]] = bitcast i32 %[[V1]] to float
-// CHECK-OPT-HARD: ret float %[[V2]]
-
-void __attribute__((cmse_nonsecure_call)) (*g1)(__fp16);
-__fp16 x;
-void f1() {
-  g1(x);
-}
-// CHECK: define {{.*}}@f1()
-
-// CHECK-NOPT-SOFT: %[[V0:.*]] = load i32
-// CHECK-NOPT-SOFT: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-NOPT-SOFT: call {{.*}} void {{.*}}(i32 %[[V1]])
-
-// CHECK-OPT-SOFT: %[[V1:.*]] = zext i16 {{.*}} to i32
-// CHECK-OPT-SOFT: call {{.*}} void {{.*}}(i32 %[[V1]])
-
-// CHECK-NOPT-HARD: %[[V0:.*]] = bitcast float {{.*}} to i32
-// CHECK-NOPT-HARD: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-NOPT-HARD: %[[V2:.*]] = bitcast i32 %[[V1]] to float
-// CHECK-NOPT-HARD: call {{.*}}(float %[[V2]])
-
-// CHECK-OPT-HARD: %[[V0:.*]] = zext i16 {{.*}} to i32
-// CHECK-OPT-HARD: %[[V1:.*]] = bitcast i32 %[[V0]] to float
-// CHECK-OPT-HARD: call {{.*}}(float %[[V1]])
Index: clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
===
--- clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
+++ clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
@@ -114,13 +114,10 @@
 
 // CHECK-LABEL: @test_vsubq_n_f16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast float [[B_COERCE:%.*]] to i32
-// CHECK-NEXT:[[TMP_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0]] to i16
-// CHECK-NEXT:[[TMP1:%.*]] = bitcast i16 [[TMP_0_EXTRACT_TRUNC]] to half
-// CHECK-NEXT:[[DOTSPLATINSERT:%.*]] = insertelement <8 x half> undef, half [[TMP1]], i32 0
+// CHECK-NEXT:[[DOTSPLATINSERT:%.*]] = insertelement <8 x half> undef, half [[B:%.*]], i32 0
 // CHECK-NEXT:[[DOTSPLAT:%.*]] = shufflevector <8 x half> [[DOTSPLATINSERT]], <8 x half> undef, <8 x i32> zeroinitializer
-// CHECK-NEXT:[[TMP2:%.*]] = fsub <8 x half> [[A:%.*]], [[DOTSPLAT]]
-// CHECK-NEXT:ret <8 x half> [[TMP2]]
+// CHECK-NEXT:[[TMP0:%.*]] = fsub <8 x half> [[A:%.*]], [[DOTSPLAT]]

[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-06-09 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 269450.
pratlucas added a comment.

Splitting the patch into two parts: one for introducing the half-precision
handling into AArch32's backend and one for removing the existing coercion
of those arguments from Clang.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/ARM/ARMCallingConv.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/ARM/fp16-args.ll
  llvm/test/CodeGen/ARM/fp16-bitcast.ll
  llvm/test/CodeGen/ARM/fp16-promote.ll
  llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-vdup.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

Index: llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
===
--- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
+++ llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
@@ -78,7 +78,6 @@
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 ; CHECK-NEXT:.p2align 1
 ; CHECK-NEXT:  @ %bb.1:
@@ -103,7 +102,6 @@
 ; CHECK-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -125,7 +123,6 @@
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-FP-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v16f16:
@@ -169,7 +166,6 @@
 ; CHECK-NOFP-NEXT:vminnm.f16 s8, s8, s10
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s4
 ; CHECK-NOFP-NEXT:vminnm.f16 s0, s8, s0
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
@@ -309,20 +305,20 @@
 define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {
 ; CHECK-FP-LABEL: fmin_v4f16_nofast:
 ; CHECK-FP:   @ %bb.0: @ %entry
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v4f16_nofast:
 ; CHECK-NOFP:   @ %bb.0: @ %entry
-; CHECK-NOFP-NEXT:vmov r1, s1
+; CHECK-NOFP-NEXT:vmov r0, s1
 ; CHECK-NOFP-NEXT:vmovx.f16 s10, s0
-; CHECK-NOFP-NEXT:vdup.32 q1, r1
+; CHECK-NOFP-NEXT:vdup.32 q1, r0
 ; CHECK-NOFP-NEXT:vmovx.f16 s8, s4
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s10
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
@@ -333,7 +329,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
@@ -346,13 +341,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v8f16_nofast:
@@ -384,7 +379,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -398,13 +392,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT

[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-06-09 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 269466.
pratlucas added a comment.

Formatting patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/ARM/ARMCallingConv.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/ARM/fp16-args.ll
  llvm/test/CodeGen/ARM/fp16-bitcast.ll
  llvm/test/CodeGen/ARM/fp16-promote.ll
  llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-vdup.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

Index: llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
===
--- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
+++ llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
@@ -78,7 +78,6 @@
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 ; CHECK-NEXT:.p2align 1
 ; CHECK-NEXT:  @ %bb.1:
@@ -103,7 +102,6 @@
 ; CHECK-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -125,7 +123,6 @@
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-FP-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v16f16:
@@ -169,7 +166,6 @@
 ; CHECK-NOFP-NEXT:vminnm.f16 s8, s8, s10
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s4
 ; CHECK-NOFP-NEXT:vminnm.f16 s0, s8, s0
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
@@ -309,20 +305,20 @@
 define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {
 ; CHECK-FP-LABEL: fmin_v4f16_nofast:
 ; CHECK-FP:   @ %bb.0: @ %entry
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v4f16_nofast:
 ; CHECK-NOFP:   @ %bb.0: @ %entry
-; CHECK-NOFP-NEXT:vmov r1, s1
+; CHECK-NOFP-NEXT:vmov r0, s1
 ; CHECK-NOFP-NEXT:vmovx.f16 s10, s0
-; CHECK-NOFP-NEXT:vdup.32 q1, r1
+; CHECK-NOFP-NEXT:vdup.32 q1, r0
 ; CHECK-NOFP-NEXT:vmovx.f16 s8, s4
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s10
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
@@ -333,7 +329,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
@@ -346,13 +341,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v8f16_nofast:
@@ -384,7 +379,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -398,13 +392,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.1

[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-06-10 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 269915.
pratlucas marked 2 inline comments as done.
pratlucas added a comment.

Clean-ups + fixing failure in CodeGen/ARM/half.ll test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/ARM/ARMCallingConv.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/ARM/fp16-args.ll
  llvm/test/CodeGen/ARM/fp16-bitcast.ll
  llvm/test/CodeGen/ARM/fp16-promote.ll
  llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-vdup.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

Index: llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
===
--- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
+++ llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
@@ -78,7 +78,6 @@
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 ; CHECK-NEXT:.p2align 1
 ; CHECK-NEXT:  @ %bb.1:
@@ -103,7 +102,6 @@
 ; CHECK-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -125,7 +123,6 @@
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-FP-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v16f16:
@@ -169,7 +166,6 @@
 ; CHECK-NOFP-NEXT:vminnm.f16 s8, s8, s10
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s4
 ; CHECK-NOFP-NEXT:vminnm.f16 s0, s8, s0
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
@@ -309,20 +305,20 @@
 define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {
 ; CHECK-FP-LABEL: fmin_v4f16_nofast:
 ; CHECK-FP:   @ %bb.0: @ %entry
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v4f16_nofast:
 ; CHECK-NOFP:   @ %bb.0: @ %entry
-; CHECK-NOFP-NEXT:vmov r1, s1
+; CHECK-NOFP-NEXT:vmov r0, s1
 ; CHECK-NOFP-NEXT:vmovx.f16 s10, s0
-; CHECK-NOFP-NEXT:vdup.32 q1, r1
+; CHECK-NOFP-NEXT:vdup.32 q1, r0
 ; CHECK-NOFP-NEXT:vmovx.f16 s8, s4
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s10
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
@@ -333,7 +329,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
@@ -346,13 +341,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v8f16_nofast:
@@ -384,7 +379,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -398,13 +392,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.

[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-06-10 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked an inline comment as done.
pratlucas added inline comments.



Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:524
+  CallConv))
+return;
   EVT ValueVT = Val.getValueType();

efriedma wrote:
> I'm not sure I understand why the standard getCopyFromParts/getCopyToParts 
> codepath doesn't work. Is the issue that it uses FP_ROUND/FP_EXTEND to 
> promote from f16 to f32?
Yes, the issue is the usage of FP_ROUND/FP_EXTEND indeed. Those cause the 
argument to be converted from f16 into f32 - with a `vcvtb.f16.f32` for 
instance - instead of simply being placed the value in the LSBs as required by 
the AAPCS.



Comment at: llvm/lib/Target/ARM/ARMCallingConv.cpp:296
+
+static bool CC_ARM_AAPCS_Custom_f16(unsigned ValNo, MVT ValVT, MVT LocVT,
+CCValAssign::LocInfo LocInfo,

efriedma wrote:
> It isn't obvious to me why you need this; can you not use 
> CCBitConvertToType/CCAssignToReg?
For hard floats, using CCAssingToReg would indeed work well in the majority of 
the scenarios, but would get in the way of the CMSE handling from D81428. Using 
the f16 loc type causes the clearing of the top 16 bits to be optimized out in 
the DAG.
Also, the AAPCS expects the argument sized to be extended to 4 bytes, so using 
the f32 loc type attends to that rule.

For soft floats, on the other hand, simply convering it to i32 causes the code 
on ARMISel lowering to be quite cumbersome. The loc info becomes either 
`CCValAssign::BCvt` (f16 -> f32 - >i32) or `CCValAssign::AExt` ( f16 -> i16 -> 
i32), so checking for when we need to handle things differently for f16 becomes 
less clear.
Using this flow we have the `isCustom` flag assigned and can have a more 
explicit handling of this.




Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169



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[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-06-11 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 270143.
pratlucas added a comment.

Fixing failure on CodeGen/ARM/GlobalISel/arm-unsupported.ll and making 
clang-format happy.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/ARM/ARMCallLowering.cpp
  llvm/lib/Target/ARM/ARMCallingConv.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
  llvm/test/CodeGen/ARM/fp16-args.ll
  llvm/test/CodeGen/ARM/fp16-bitcast.ll
  llvm/test/CodeGen/ARM/fp16-promote.ll
  llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-vdup.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

Index: llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
===
--- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
+++ llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
@@ -78,7 +78,6 @@
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 ; CHECK-NEXT:.p2align 1
 ; CHECK-NEXT:  @ %bb.1:
@@ -103,7 +102,6 @@
 ; CHECK-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -125,7 +123,6 @@
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-FP-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v16f16:
@@ -169,7 +166,6 @@
 ; CHECK-NOFP-NEXT:vminnm.f16 s8, s8, s10
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s4
 ; CHECK-NOFP-NEXT:vminnm.f16 s0, s8, s0
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
@@ -309,20 +305,20 @@
 define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {
 ; CHECK-FP-LABEL: fmin_v4f16_nofast:
 ; CHECK-FP:   @ %bb.0: @ %entry
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v4f16_nofast:
 ; CHECK-NOFP:   @ %bb.0: @ %entry
-; CHECK-NOFP-NEXT:vmov r1, s1
+; CHECK-NOFP-NEXT:vmov r0, s1
 ; CHECK-NOFP-NEXT:vmovx.f16 s10, s0
-; CHECK-NOFP-NEXT:vdup.32 q1, r1
+; CHECK-NOFP-NEXT:vdup.32 q1, r0
 ; CHECK-NOFP-NEXT:vmovx.f16 s8, s4
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s10
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
@@ -333,7 +329,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
@@ -346,13 +341,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v8f16_nofast:
@@ -384,7 +379,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -398,13 +392,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s

[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-11 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 270149.
pratlucas added a comment.

Rebasing and simplifying function attributes on test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -4,13 +4,13 @@
 ; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
 ; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
 
 define float @f1(float (float)* nocapture %fptr) #0 {
 ; CHECK-8M-LABEL: f1:
@@ -809,3 +809,443 @@
   ret void
 }
 
+define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-NO-MVE-LABEL: h1:
+; CHECK-NO-MVE:   @ %bb.0:
+; CHECK-NO-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-NO-MVE-NEXT:push {r7, lr}
+; CHECK-NO-MVE-NEXT:sub sp, #4
+; CHECK-NO-MVE-NEXT:vldr s0, .LCPI11_0
+; CHECK-NO-MVE-NEXT:blx r0
+; CHECK-NO-MVE-NEXT:vmov r0, s0
+; CHECK-NO-MVE-NEXT:uxth r0, r0
+; CHECK-NO-MVE-NEXT:vmov s0, r0
+; CHECK-NO-MVE-NEXT:add sp, #4
+; CHECK-NO-MVE-NEXT:pop.w {r7, lr}
+; CHECK-NO-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-NO-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-NO-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-NO-MVE-NEXT:bxns lr
+; CHECK-NO-MVE-NEXT:.p2align 2
+; CHECK-NO-MVE-NEXT:  @ %bb.1:
+; CHECK-NO-MVE-NEXT:  .LCPI11_0:
+; CHECK-NO-MVE-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-MVE-LABEL: h1:
+; CHECK-MVE:   @ %bb.0:
+; CHECK-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-MVE-NEXT:push {r7, lr}
+; CHECK-MVE-NEXT:sub sp, #4
+; CHECK-MVE-NEXT:vmov.f16 s0, #1.00e+01
+; CHECK-MVE-NEXT:vmov.f16 r1, s0
+; CHECK-MVE-NEXT:vmov s0, r1
+; CHECK-MVE-NEXT:blx r0
+; CHECK-MVE-NEXT:vmov.f16 r0, s0
+; CHECK-MVE-NEXT:vmov s0, r0
+; CHECK-MVE-NEXT:add sp, #4
+; CHECK-MVE-NEXT:pop.w {r7, lr}
+; CHECK-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-MVE-NEXT:bxns lr
+  %call = call half %hptr(half 10.0) nounwind
+  ret half %call
+}
+
+define half @h2(half (half)* nocapture %hptr

[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-11 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 270160.
pratlucas added a comment.

Addressing review comment.


Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -4,13 +4,13 @@
 ; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
 ; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
 
 define float @f1(float (float)* nocapture %fptr) #0 {
 ; CHECK-8M-LABEL: f1:
@@ -809,3 +809,443 @@
   ret void
 }
 
+define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-NO-MVE-LABEL: h1:
+; CHECK-NO-MVE:   @ %bb.0:
+; CHECK-NO-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-NO-MVE-NEXT:push {r7, lr}
+; CHECK-NO-MVE-NEXT:sub sp, #4
+; CHECK-NO-MVE-NEXT:vldr s0, .LCPI11_0
+; CHECK-NO-MVE-NEXT:blx r0
+; CHECK-NO-MVE-NEXT:vmov r0, s0
+; CHECK-NO-MVE-NEXT:uxth r0, r0
+; CHECK-NO-MVE-NEXT:vmov s0, r0
+; CHECK-NO-MVE-NEXT:add sp, #4
+; CHECK-NO-MVE-NEXT:pop.w {r7, lr}
+; CHECK-NO-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-NO-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-NO-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-NO-MVE-NEXT:bxns lr
+; CHECK-NO-MVE-NEXT:.p2align 2
+; CHECK-NO-MVE-NEXT:  @ %bb.1:
+; CHECK-NO-MVE-NEXT:  .LCPI11_0:
+; CHECK-NO-MVE-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-MVE-LABEL: h1:
+; CHECK-MVE:   @ %bb.0:
+; CHECK-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-MVE-NEXT:push {r7, lr}
+; CHECK-MVE-NEXT:sub sp, #4
+; CHECK-MVE-NEXT:vmov.f16 s0, #1.00e+01
+; CHECK-MVE-NEXT:vmov.f16 r1, s0
+; CHECK-MVE-NEXT:vmov s0, r1
+; CHECK-MVE-NEXT:blx r0
+; CHECK-MVE-NEXT:vmov.f16 r0, s0
+; CHECK-MVE-NEXT:vmov s0, r0
+; CHECK-MVE-NEXT:add sp, #4
+; CHECK-MVE-NEXT:pop.w {r7, lr}
+; CHECK-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-MVE-NEXT:bxns lr
+  %call = call half %hptr(half 10.0) nounwind
+  ret half %call
+}
+
+define half @h2(half (half)* nocapture %hptr) nounwind {
+; CHECK-8M-LA

[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-11 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked 4 inline comments as done.
pratlucas added inline comments.



Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:2267
 
+// Mask f16 arguments if this is a CMSE nonsecure call
+auto ArgVT = Outs[realArgIdx].ArgVT;

ostannard wrote:
> Could this be done more efficiently by changing the ANY_EXTEND above to a 
> ZERO_EXTEND when this is a CMSE call?
Now that the `fp16` type convertion on D75169 was updated to use 
`VMOVhr`/`VMOVrh`, I've updated this patch to only use and `AND` masking when 
the argument are extended by `getCopyToParts`/`getCopyFromParts` prior to the 
calling convention lowering.


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[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-06-12 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

Hi @efriedma,

From @SjoerdMeijer's comment and the links he pointed to, it seems to me that 
making `f16` types legal for all ARM subtargets would be a major undertaking 
and far from trivial to implement. It's also not clear to me how significant 
would be the returns of this effort.
My feeling is that we could proceed with the current approach and discuss the 
possbility of making `f16` legal in a separate follow up effort, as mentioned 
by @dnsampaio.

What's your view on this?


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[PATCH] D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen

2020-06-15 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

Hi @stuij,

The changes to the backend only handle the half (f16) type itself, not vectors 
that have it as their base type.

From what I've checked on the AAPCS, the rules for handling those types are a 
bit different and they would require their own handling in the backend's 
calling convention lowering.
I haven't looked into the backend's handling of those types in detail, but I 
believe a similar approach to the one taken for f16 would be possible for the 
vector types as well.


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[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-18 Thread Lucas Prates via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG92ad6d57c218: [ARM] Moving CMSE handling of half arguments 
and return to the backend (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -4,13 +4,13 @@
 ; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
 ; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
 
 define float @f1(float (float)* nocapture %fptr) #0 {
 ; CHECK-8M-LABEL: f1:
@@ -809,3 +809,443 @@
   ret void
 }
 
+define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-NO-MVE-LABEL: h1:
+; CHECK-NO-MVE:   @ %bb.0:
+; CHECK-NO-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-NO-MVE-NEXT:push {r7, lr}
+; CHECK-NO-MVE-NEXT:sub sp, #4
+; CHECK-NO-MVE-NEXT:vldr s0, .LCPI11_0
+; CHECK-NO-MVE-NEXT:blx r0
+; CHECK-NO-MVE-NEXT:vmov r0, s0
+; CHECK-NO-MVE-NEXT:uxth r0, r0
+; CHECK-NO-MVE-NEXT:vmov s0, r0
+; CHECK-NO-MVE-NEXT:add sp, #4
+; CHECK-NO-MVE-NEXT:pop.w {r7, lr}
+; CHECK-NO-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-NO-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-NO-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-NO-MVE-NEXT:bxns lr
+; CHECK-NO-MVE-NEXT:.p2align 2
+; CHECK-NO-MVE-NEXT:  @ %bb.1:
+; CHECK-NO-MVE-NEXT:  .LCPI11_0:
+; CHECK-NO-MVE-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-MVE-LABEL: h1:
+; CHECK-MVE:   @ %bb.0:
+; CHECK-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-MVE-NEXT:push {r7, lr}
+; CHECK-MVE-NEXT:sub sp, #4
+; CHECK-MVE-NEXT:vmov.f16 s0, #1.00e+01
+; CHECK-MVE-NEXT:vmov.f16 r1, s0
+; CHECK-MVE-NEXT:vmov s0, r1
+; CHECK-MVE-NEXT:blx r0
+; CHECK-MVE-NEXT:vmov.f16 r0, s0
+; CHECK-MVE-NEXT:vmov s0, r0
+; CHECK-MVE-NEXT:add sp, #4
+; CHECK-MVE-NEXT:pop.w {r7, lr}
+; CHECK-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-MVE-NEXT:bxns lr
+  %call = call half %hptr(half 10.0) noun

[PATCH] D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen

2020-06-18 Thread Lucas Prates via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGada4c9dc4a63: [ARM][Clang] Removing lowering of 
half-precision FP arguments and returns from… (authored by pratlucas).

Changed prior to commit:
  https://reviews.llvm.org/D81451?vs=269453&id=271677#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm-fp16-arguments.c
  clang/test/CodeGen/arm-mve-intrinsics/compare.c
  clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
  clang/test/CodeGen/arm-mve-intrinsics/dup.c
  clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
  clang/test/CodeGen/arm-mve-intrinsics/ternary.c
  clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
  clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
  clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
  clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
  clang/test/CodeGen/cmse-clear-fp16.c

Index: clang/test/CodeGen/cmse-clear-fp16.c
===
--- clang/test/CodeGen/cmse-clear-fp16.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// RUN: %clang_cc1 -triple thumbv8m.main -O0 -mcmse  -S -emit-llvm \
-// RUN:-fallow-half-arguments-and-returns %s -o - | \
-// RUN:FileCheck %s --check-prefixes=CHECK,CHECK-NOPT-SOFT
-// RUN: %clang_cc1 -triple thumbv8m.main -O2 -mcmse  -S -emit-llvm \
-// RUN:-fallow-half-arguments-and-returns %s -o - | \
-// RUN:FileCheck %s --check-prefixes=CHECK,CHECK-OPT-SOFT
-// RUN: %clang_cc1 -triple thumbv8m.main -O0 -mcmse  -S -emit-llvm \
-// RUN:-fallow-half-arguments-and-returns -mfloat-abi hard %s -o - | \
-// RUN:FileCheck %s --check-prefixes=CHECK,CHECK-NOPT-HARD
-// RUN: %clang_cc1 -triple thumbv8m.main -O2 -mcmse  -S -emit-llvm \
-// RUN:-fallow-half-arguments-and-returns -mfloat-abi hard %s -o - | \
-// RUN:FileCheck %s --check-prefixes=CHECK,CHECK-OPT-HARD
-
-__fp16 g0();
-__attribute__((cmse_nonsecure_entry)) __fp16 f0() {
-  return g0();
-}
-// CHECK:   define {{.*}}@f0()
-
-// CHECK-NOPT-SOFT: %[[V0:.*]] = load i32
-// CHECK-NOPT-SOFT: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-NOPT-SOFT: ret i32 %[[V1]]
-
-// CHECK-OPT-SOFT: %[[V0:.*]] = tail call {{.*}} @g0
-// CHECK-OPT-SOFT: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-OPT-SOFT: ret i32 %[[V1]]
-
-// CHECK-NOPT-HARD: %[[V0:.*]] = bitcast float {{.*}} to i32
-// CHECK-NOPT-HARD: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-NOPT-HARD: %[[V2:.*]] = bitcast i32 %[[V1]] to float
-// CHECK-NOPT-HARD: ret float %[[V2]]
-
-// CHECK-OPT-HARD: %[[V0:.*]] = bitcast float {{.*}} to i32
-// CHECK-OPT-HARD: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-OPT-HARD: %[[V2:.*]] = bitcast i32 %[[V1]] to float
-// CHECK-OPT-HARD: ret float %[[V2]]
-
-void __attribute__((cmse_nonsecure_call)) (*g1)(__fp16);
-__fp16 x;
-void f1() {
-  g1(x);
-}
-// CHECK: define {{.*}}@f1()
-
-// CHECK-NOPT-SOFT: %[[V0:.*]] = load i32
-// CHECK-NOPT-SOFT: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-NOPT-SOFT: call {{.*}} void {{.*}}(i32 %[[V1]])
-
-// CHECK-OPT-SOFT: %[[V1:.*]] = zext i16 {{.*}} to i32
-// CHECK-OPT-SOFT: call {{.*}} void {{.*}}(i32 %[[V1]])
-
-// CHECK-NOPT-HARD: %[[V0:.*]] = bitcast float {{.*}} to i32
-// CHECK-NOPT-HARD: %[[V1:.*]] = and i32 %[[V0]], 65535
-// CHECK-NOPT-HARD: %[[V2:.*]] = bitcast i32 %[[V1]] to float
-// CHECK-NOPT-HARD: call {{.*}}(float %[[V2]])
-
-// CHECK-OPT-HARD: %[[V0:.*]] = zext i16 {{.*}} to i32
-// CHECK-OPT-HARD: %[[V1:.*]] = bitcast i32 %[[V0]] to float
-// CHECK-OPT-HARD: call {{.*}}(float %[[V1]])
Index: clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
===
--- clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
+++ clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
@@ -114,13 +114,10 @@
 
 // CHECK-LABEL: @test_vsubq_n_f16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast float [[B_COERCE:%.*]] to i32
-// CHECK-NEXT:[[TMP_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0]] to i16
-// CHECK-NEXT:[[TMP1:%.*]] = bitcast i16 [[TMP_0_EXTRACT_TRUNC]] to half
-// CHECK-NEXT:[[DOTSPLATINSERT:%.*]] = insertelement <8 x half> undef, half [[TMP1]], i32 0
+// CHECK-NEXT:[[DOTSPLATINSERT:%.*]] = insertelement <8 x half> undef, half [[B:%.*]], i32 0
 // CHECK-NEXT:[[DOTSPLAT:%.*]] = shufflevector <8 x half> [[DOTSPLATINSERT]], <8 x half> undef, <8 x i32> zeroinitializer
-// CHECK-NEXT:[[TMP2:%.*]] = fsub <8 x half> [[A:%.*]], [[DOTSPLAT]]
-// CHECK-NEXT:ret <8 x half> [[TMP2]]
+// CHECK-NEXT:[[TMP0:%.*]] = fsub <8 x half> [[A:%.*]], [[DOTSPLAT]]
+// CHECK-NEXT:ret <8 x half> [[TMP0]]
 //
 float16x8_t test_vsubq_n_f16(float16x8_t a, float16_t b)
 {
@@ -187,15 +184,12 @@
 
 // CHECK-LABEL: @test_vsubq_x_n_f16(
 // CHECK-NEXT:  entry:
-// CHE

[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-06-18 Thread Lucas Prates via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa255931c4055: [ARM] Supporting lowering of half-precision FP 
arguments and returns in… (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/ARM/ARMCallLowering.cpp
  llvm/lib/Target/ARM/ARMCallingConv.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
  llvm/test/CodeGen/ARM/fp16-args.ll
  llvm/test/CodeGen/ARM/fp16-bitcast.ll
  llvm/test/CodeGen/ARM/fp16-promote.ll
  llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-vdup.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

Index: llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
===
--- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
+++ llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
@@ -78,7 +78,6 @@
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:vminnm.f16 s0, s0, s2
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 ; CHECK-NEXT:.p2align 1
 ; CHECK-NEXT:  @ %bb.1:
@@ -103,7 +102,6 @@
 ; CHECK-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-NEXT:vstr.16 s0, [r0]
 ; CHECK-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -125,7 +123,6 @@
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s6
 ; CHECK-FP-NEXT:vminnm.f16 s4, s4, s3
 ; CHECK-FP-NEXT:vminnm.f16 s0, s4, s0
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v16f16:
@@ -169,7 +166,6 @@
 ; CHECK-NOFP-NEXT:vminnm.f16 s8, s8, s10
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s4
 ; CHECK-NOFP-NEXT:vminnm.f16 s0, s8, s0
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
@@ -309,20 +305,20 @@
 define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {
 ; CHECK-FP-LABEL: fmin_v4f16_nofast:
 ; CHECK-FP:   @ %bb.0: @ %entry
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v4f16_nofast:
 ; CHECK-NOFP:   @ %bb.0: @ %entry
-; CHECK-NOFP-NEXT:vmov r1, s1
+; CHECK-NOFP-NEXT:vmov r0, s1
 ; CHECK-NOFP-NEXT:vmovx.f16 s10, s0
-; CHECK-NOFP-NEXT:vdup.32 q1, r1
+; CHECK-NOFP-NEXT:vdup.32 q1, r0
 ; CHECK-NOFP-NEXT:vmovx.f16 s8, s4
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s10
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
@@ -333,7 +329,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
@@ -346,13 +341,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov r1, s1
-; CHECK-FP-NEXT:vdup.32 q1, r1
+; CHECK-FP-NEXT:vmov r0, s1
+; CHECK-FP-NEXT:vdup.32 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vmov.u16 r1, q0[1]
-; CHECK-FP-NEXT:vdup.16 q1, r1
+; CHECK-FP-NEXT:vmov.u16 r0, q0[1]
+; CHECK-FP-NEXT:vdup.16 q1, r0
 ; CHECK-FP-NEXT:vminnm.f16 q0, q0, q1
-; CHECK-FP-NEXT:vstr.16 s0, [r0]
+; CHECK-FP-NEXT:@ kill: def $s0 killed $s0 killed $q0
 ; CHECK-FP-NEXT:bx lr
 ;
 ; CHECK-NOFP-LABEL: fmin_v8f16_nofast:
@@ -384,7 +379,6 @@
 ; CHECK-NOFP-NEXT:vcmp.f16 s8, s0
 ; CHECK-NOFP-NEXT:vmrs APSR_nzcv, fpscr
 ; CHECK-NOFP-NEXT:vselgt.f16 s0, s0, s8
-; CHECK-NOFP-NEXT:vstr.16 s0, [r0]
 ; CHECK-NOFP-NEXT:bx lr
 entry:
   %z = call half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
@@ -398,13 +392,13 @@
 ; CHECK-FP-NEXT:vmov.f64 d2, d1
 ; CHECK-FP-NEXT:vmov.f32 s5, s3
 ; CHECK-FP-NEXT:vminnm.f16 q0, q

[PATCH] D75169: [ARM] Enforcing calling convention for half-precision FP arguments and returns for big-endian AArch32

2020-04-20 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.
Herald added a subscriber: danielkiss.

Ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169



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[PATCH] D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section

2020-04-21 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Section names used in clang section pragmas were not validated against
previously defined sections, causing section type conflicts to be
ignored by Sema.

This patch enables Clang to capture these section type conflicts by
using the existing Sema's UnifySection method to validate section names
from clang section pragmas.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78572

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/SemaAttr.cpp
  clang/test/Sema/pragma-clang-section.c


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -fsyntax-only -verify %s -triple arm-none-eabi
-#pragma clang section bss="mybss.1" data="mydata.1" rodata="myrodata.1" 
text="mytext.1"
+#pragma clang section bss="mybss.1" data="mydata.1" rodata="myrodata.1" 
text="mytext.1" // expected-note {{#pragma entered here}} expected-note 
{{#pragma entered here}}
 #pragma clang section bss="" data="" rodata="" text=""
 #pragma clang section
 
@@ -16,4 +16,10 @@
 #pragma clang section text "text.2"   // expected-error {{expected '=' 
following '#pragma clang section text'}}
 #pragma clang section relro "relro.2"   // expected-error {{expected '=' 
following '#pragma clang section relro'}}
 #pragma clang section bss="" data="" rodata="" text="" more //expected-error 
{{expected one of [bss|data|rodata|text|relro] section kind in '#pragma clang 
section'}}
+
+#pragma clang section bss="mybss.3" data="mybss.3" // expected-error {{this 
causes a section type conflict with a prior #pragma section}} expected-note 
{{#pragma entered here}} expected-note {{#pragma entered here}}
+#pragma clang section rodata="mydata.1" // expected-error {{this causes a 
section type conflict with a prior #pragma section}}
+#pragma clang section bss="myrodata.1" // expected-error {{this causes a 
section type conflict with a prior #pragma section}}
+#pragma clang section text="mybss.3" // expected-error {{this causes a section 
type conflict with a prior #pragma section}}
+
 int a;
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -256,12 +256,15 @@
 void Sema::ActOnPragmaClangSection(SourceLocation PragmaLoc, 
PragmaClangSectionAction Action,
PragmaClangSectionKind SecKind, StringRef 
SecName) {
   PragmaClangSection *CSec;
+  int SectionFlags = ASTContext::PSF_Read;
   switch (SecKind) {
 case PragmaClangSectionKind::PCSK_BSS:
   CSec = &PragmaClangBSSSection;
+  SectionFlags |= ASTContext::PSF_Write | ASTContext::PSF_ZeroInit;
   break;
 case PragmaClangSectionKind::PCSK_Data:
   CSec = &PragmaClangDataSection;
+  SectionFlags |= ASTContext::PSF_Write;
   break;
 case PragmaClangSectionKind::PCSK_Rodata:
   CSec = &PragmaClangRodataSection;
@@ -271,6 +274,7 @@
   break;
 case PragmaClangSectionKind::PCSK_Text:
   CSec = &PragmaClangTextSection;
+  SectionFlags |= ASTContext::PSF_Execute;
   break;
 default:
   llvm_unreachable("invalid clang section kind");
@@ -281,6 +285,9 @@
 return;
   }
 
+  if (UnifySection(SecName, SectionFlags, PragmaLoc))
+return;
+
   CSec->Valid = true;
   CSec->SectionName = std::string(SecName);
   CSec->PragmaLocation = PragmaLoc;
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1845,6 +1845,7 @@
   return;
 }
 
+SourceLocation PragmaLocation = Tok.getLocation();
 PP.Lex(Tok); // eat ['bss'|'data'|'rodata'|'text']
 if (Tok.isNot(tok::equal)) {
   PP.Diag(Tok.getLocation(), 
diag::err_pragma_clang_section_expected_equal) << SecKind;
@@ -1855,7 +1856,7 @@
 if (!PP.LexStringLiteral(Tok, SecName, "pragma clang section", false))
   return;
 
-Actions.ActOnPragmaClangSection(Tok.getLocation(),
+Actions.ActOnPragmaClangSection(PragmaLocation,
   (SecName.size()? Sema::PragmaClangSectionAction::PCSA_Set :
Sema::PragmaClangSectionAction::PCSA_Clear),
SecKind, SecName);
Index: clang/include/clang/AST/ASTContext.h
===
--- clang/include/clang/AST/ASTContext.h
+++ clang/include/clang/AST/ASTContext.h
@@ -2946,6 +2946,7 @@
 PSF_Write = 0x2,
 PSF_Execute = 0x4,
 PSF_Implicit = 0x8,
+PSF_ZeroInit = 0x10,
 PSF_Invalid = 0x8000U,
   };
 


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-cl

[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-04-21 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Conflicting types for the same section name defined in clang section
pragmas and GNU-style section attributes were not properly captured by
Clang's Sema. The lack of diagnostics was caused by the fact the section
specification coming from attributes was handled by Sema as implicit,
even though explicitly defined by the user.

This patch enables the diagnostics for section type conflicts between
those specifications by making sure sections defined in section
attributes are correctly handled as explicit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78573

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Sema/SemaAttr.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/test/Sema/pragma-clang-section.c

Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -22,4 +22,9 @@
 #pragma clang section bss="myrodata.1" // expected-error {{this causes a section type conflict with a prior #pragma section}}
 #pragma clang section text="mybss.3" // expected-error {{this causes a section type conflict with a prior #pragma section}}
 
+#pragma clang section rodata="myrodata.4" // expected-note {{#pragma entered here}}
+int x __attribute__((section("myrodata.4"))); // expected-error {{'x' causes a section type conflict with a prior #pragma section}}
+const int y __attribute__((section("myrodata.5"))) = 10; // expected-note {{declared here}}
+#pragma clang section data="myrodata.5" // expected-error {{this causes a section type conflict with 'y'}}
+
 int a;
Index: clang/lib/Sema/SemaDecl.cpp
===
--- clang/lib/Sema/SemaDecl.cpp
+++ clang/lib/Sema/SemaDecl.cpp
@@ -12736,7 +12736,7 @@
   if (GlobalStorage && var->isThisDeclarationADefinition() &&
   !inTemplateInstantiation()) {
 PragmaStack *Stack = nullptr;
-int SectionFlags = ASTContext::PSF_Implicit | ASTContext::PSF_Read;
+int SectionFlags = ASTContext::PSF_Read;
 if (var->getType().isConstQualified())
   Stack = &ConstSegStack;
 else if (!var->getInit()) {
@@ -12746,14 +12746,19 @@
   Stack = &DataSegStack;
   SectionFlags |= ASTContext::PSF_Write;
 }
-if (Stack->CurrentValue && !var->hasAttr())
+if (const SectionAttr *SA = var->getAttr()) {
+  if (SA->getSyntax() == AttributeCommonInfo::AS_Declspec)
+SectionFlags |= ASTContext::PSF_Implicit;
+  UnifySection(SA->getName(), SectionFlags, var);
+} else if (Stack->CurrentValue) {
+  SectionFlags |= ASTContext::PSF_Implicit;
+  auto SectionName = Stack->CurrentValue->getString();
   var->addAttr(SectionAttr::CreateImplicit(
-  Context, Stack->CurrentValue->getString(),
-  Stack->CurrentPragmaLocation, AttributeCommonInfo::AS_Pragma,
-  SectionAttr::Declspec_allocate));
-if (const SectionAttr *SA = var->getAttr())
-  if (UnifySection(SA->getName(), SectionFlags, var))
+  Context, SectionName, Stack->CurrentPragmaLocation,
+  AttributeCommonInfo::AS_Pragma, SectionAttr::Declspec_allocate));
+  if (UnifySection(SectionName, SectionFlags, var))
 var->dropAttr();
+}
 
 // Apply the init_seg attribute if this has an initializer.  If the
 // initializer turns out to not be dynamic, we'll end up ignoring this
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -471,42 +471,50 @@
 bool Sema::UnifySection(StringRef SectionName,
 int SectionFlags,
 DeclaratorDecl *Decl) {
-  auto Section = Context.SectionInfos.find(SectionName);
-  if (Section == Context.SectionInfos.end()) {
+  SourceLocation PragmaLocation;
+  if (auto A = Decl->getAttr())
+if (A->isImplicit())
+  PragmaLocation = A->getLocation();
+  auto SectionIt = Context.SectionInfos.find(SectionName);
+  if (SectionIt == Context.SectionInfos.end()) {
 Context.SectionInfos[SectionName] =
-ASTContext::SectionInfo(Decl, SourceLocation(), SectionFlags);
+ASTContext::SectionInfo(Decl, PragmaLocation, SectionFlags);
 return false;
   }
   // A pre-declared section takes precedence w/o diagnostic.
-  if (Section->second.SectionFlags == SectionFlags ||
-  !(Section->second.SectionFlags & ASTContext::PSF_Implicit))
+  const auto &Section = SectionIt->second;
+  if (Section.SectionFlags == SectionFlags ||
+  ((SectionFlags & ASTContext::PSF_Implicit) &&
+   !(Section.SectionFlags & ASTContext::PSF_Implicit)))
 return false;
-  auto OtherDecl = Section->second.Decl;
   Diag(Decl->getLocation(), diag::err_section_conflict)
-  << Decl << OtherDecl;
-  Diag(OtherDecl->getLocation(), diag::note_decla

[PATCH] D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section

2020-04-21 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 259039.
pratlucas added a comment.

Fixing missing clang-format messages.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78572/new/

https://reviews.llvm.org/D78572

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/SemaAttr.cpp
  clang/test/Sema/pragma-clang-section.c


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -fsyntax-only -verify %s -triple arm-none-eabi
-#pragma clang section bss="mybss.1" data="mydata.1" rodata="myrodata.1" 
text="mytext.1"
+#pragma clang section bss = "mybss.1" data = "mydata.1" rodata = "myrodata.1" 
text = "mytext.1" // expected-note {{#pragma entered here}} expected-note 
{{#pragma entered here}}
 #pragma clang section bss="" data="" rodata="" text=""
 #pragma clang section
 
@@ -16,4 +16,10 @@
 #pragma clang section text "text.2"   // expected-error {{expected '=' 
following '#pragma clang section text'}}
 #pragma clang section relro "relro.2"   // expected-error {{expected '=' 
following '#pragma clang section relro'}}
 #pragma clang section bss="" data="" rodata="" text="" more //expected-error 
{{expected one of [bss|data|rodata|text|relro] section kind in '#pragma clang 
section'}}
+
+#pragma clang section bss = "mybss.3" data = "mybss.3" // expected-error 
{{this causes a section type conflict with a prior #pragma section}} 
expected-note {{#pragma entered here}} expected-note {{#pragma entered here}}
+#pragma clang section rodata = "mydata.1"  // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+#pragma clang section bss = "myrodata.1"   // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+#pragma clang section text = "mybss.3" // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+
 int a;
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -256,12 +256,15 @@
 void Sema::ActOnPragmaClangSection(SourceLocation PragmaLoc, 
PragmaClangSectionAction Action,
PragmaClangSectionKind SecKind, StringRef 
SecName) {
   PragmaClangSection *CSec;
+  int SectionFlags = ASTContext::PSF_Read;
   switch (SecKind) {
 case PragmaClangSectionKind::PCSK_BSS:
   CSec = &PragmaClangBSSSection;
+  SectionFlags |= ASTContext::PSF_Write | ASTContext::PSF_ZeroInit;
   break;
 case PragmaClangSectionKind::PCSK_Data:
   CSec = &PragmaClangDataSection;
+  SectionFlags |= ASTContext::PSF_Write;
   break;
 case PragmaClangSectionKind::PCSK_Rodata:
   CSec = &PragmaClangRodataSection;
@@ -271,6 +274,7 @@
   break;
 case PragmaClangSectionKind::PCSK_Text:
   CSec = &PragmaClangTextSection;
+  SectionFlags |= ASTContext::PSF_Execute;
   break;
 default:
   llvm_unreachable("invalid clang section kind");
@@ -281,6 +285,9 @@
 return;
   }
 
+  if (UnifySection(SecName, SectionFlags, PragmaLoc))
+return;
+
   CSec->Valid = true;
   CSec->SectionName = std::string(SecName);
   CSec->PragmaLocation = PragmaLoc;
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1845,6 +1845,7 @@
   return;
 }
 
+SourceLocation PragmaLocation = Tok.getLocation();
 PP.Lex(Tok); // eat ['bss'|'data'|'rodata'|'text']
 if (Tok.isNot(tok::equal)) {
   PP.Diag(Tok.getLocation(), 
diag::err_pragma_clang_section_expected_equal) << SecKind;
@@ -1855,10 +1856,11 @@
 if (!PP.LexStringLiteral(Tok, SecName, "pragma clang section", false))
   return;
 
-Actions.ActOnPragmaClangSection(Tok.getLocation(),
-  (SecName.size()? Sema::PragmaClangSectionAction::PCSA_Set :
-   Sema::PragmaClangSectionAction::PCSA_Clear),
-   SecKind, SecName);
+Actions.ActOnPragmaClangSection(
+PragmaLocation,
+(SecName.size() ? Sema::PragmaClangSectionAction::PCSA_Set
+: Sema::PragmaClangSectionAction::PCSA_Clear),
+SecKind, SecName);
   }
 }
 
Index: clang/include/clang/AST/ASTContext.h
===
--- clang/include/clang/AST/ASTContext.h
+++ clang/include/clang/AST/ASTContext.h
@@ -2946,6 +2946,7 @@
 PSF_Write = 0x2,
 PSF_Execute = 0x4,
 PSF_Implicit = 0x8,
+PSF_ZeroInit = 0x10,
 PSF_Invalid = 0x8000U,
   };
 


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma

[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-04-21 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 259040.
pratlucas added a comment.

Fixing "mising clang-format" messages.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78573/new/

https://reviews.llvm.org/D78573

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Sema/SemaAttr.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/test/Sema/pragma-clang-section.c

Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -22,4 +22,9 @@
 #pragma clang section bss = "myrodata.1"   // expected-error {{this causes a section type conflict with a prior #pragma section}}
 #pragma clang section text = "mybss.3" // expected-error {{this causes a section type conflict with a prior #pragma section}}
 
+#pragma clang section rodata = "myrodata.4"  // expected-note {{#pragma entered here}}
+int x __attribute__((section("myrodata.4")));// expected-error {{'x' causes a section type conflict with a prior #pragma section}}
+const int y __attribute__((section("myrodata.5"))) = 10; // expected-note {{declared here}}
+#pragma clang section data = "myrodata.5"// expected-error {{this causes a section type conflict with 'y'}}
+
 int a;
Index: clang/lib/Sema/SemaDecl.cpp
===
--- clang/lib/Sema/SemaDecl.cpp
+++ clang/lib/Sema/SemaDecl.cpp
@@ -12736,7 +12736,7 @@
   if (GlobalStorage && var->isThisDeclarationADefinition() &&
   !inTemplateInstantiation()) {
 PragmaStack *Stack = nullptr;
-int SectionFlags = ASTContext::PSF_Implicit | ASTContext::PSF_Read;
+int SectionFlags = ASTContext::PSF_Read;
 if (var->getType().isConstQualified())
   Stack = &ConstSegStack;
 else if (!var->getInit()) {
@@ -12746,14 +12746,19 @@
   Stack = &DataSegStack;
   SectionFlags |= ASTContext::PSF_Write;
 }
-if (Stack->CurrentValue && !var->hasAttr())
+if (const SectionAttr *SA = var->getAttr()) {
+  if (SA->getSyntax() == AttributeCommonInfo::AS_Declspec)
+SectionFlags |= ASTContext::PSF_Implicit;
+  UnifySection(SA->getName(), SectionFlags, var);
+} else if (Stack->CurrentValue) {
+  SectionFlags |= ASTContext::PSF_Implicit;
+  auto SectionName = Stack->CurrentValue->getString();
   var->addAttr(SectionAttr::CreateImplicit(
-  Context, Stack->CurrentValue->getString(),
-  Stack->CurrentPragmaLocation, AttributeCommonInfo::AS_Pragma,
-  SectionAttr::Declspec_allocate));
-if (const SectionAttr *SA = var->getAttr())
-  if (UnifySection(SA->getName(), SectionFlags, var))
+  Context, SectionName, Stack->CurrentPragmaLocation,
+  AttributeCommonInfo::AS_Pragma, SectionAttr::Declspec_allocate));
+  if (UnifySection(SectionName, SectionFlags, var))
 var->dropAttr();
+}
 
 // Apply the init_seg attribute if this has an initializer.  If the
 // initializer turns out to not be dynamic, we'll end up ignoring this
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -471,42 +471,49 @@
 bool Sema::UnifySection(StringRef SectionName,
 int SectionFlags,
 DeclaratorDecl *Decl) {
-  auto Section = Context.SectionInfos.find(SectionName);
-  if (Section == Context.SectionInfos.end()) {
+  SourceLocation PragmaLocation;
+  if (auto A = Decl->getAttr())
+if (A->isImplicit())
+  PragmaLocation = A->getLocation();
+  auto SectionIt = Context.SectionInfos.find(SectionName);
+  if (SectionIt == Context.SectionInfos.end()) {
 Context.SectionInfos[SectionName] =
-ASTContext::SectionInfo(Decl, SourceLocation(), SectionFlags);
+ASTContext::SectionInfo(Decl, PragmaLocation, SectionFlags);
 return false;
   }
   // A pre-declared section takes precedence w/o diagnostic.
-  if (Section->second.SectionFlags == SectionFlags ||
-  !(Section->second.SectionFlags & ASTContext::PSF_Implicit))
+  const auto &Section = SectionIt->second;
+  if (Section.SectionFlags == SectionFlags ||
+  ((SectionFlags & ASTContext::PSF_Implicit) &&
+   !(Section.SectionFlags & ASTContext::PSF_Implicit)))
 return false;
-  auto OtherDecl = Section->second.Decl;
-  Diag(Decl->getLocation(), diag::err_section_conflict)
-  << Decl << OtherDecl;
-  Diag(OtherDecl->getLocation(), diag::note_declared_at)
-  << OtherDecl->getName();
-  if (auto A = Decl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
-  if (auto A = OtherDecl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
+  Diag(Decl->getLocation(), diag::err_section_conflict) << Decl <

[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-04-21 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 259048.
pratlucas added a comment.

Removing unnecessary function.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78573/new/

https://reviews.llvm.org/D78573

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Sema/SemaAttr.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/test/Sema/pragma-clang-section.c

Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -22,4 +22,9 @@
 #pragma clang section bss = "myrodata.1"   // expected-error {{this causes a section type conflict with a prior #pragma section}}
 #pragma clang section text = "mybss.3" // expected-error {{this causes a section type conflict with a prior #pragma section}}
 
+#pragma clang section rodata = "myrodata.4"  // expected-note {{#pragma entered here}}
+int x __attribute__((section("myrodata.4")));// expected-error {{'x' causes a section type conflict with a prior #pragma section}}
+const int y __attribute__((section("myrodata.5"))) = 10; // expected-note {{declared here}}
+#pragma clang section data = "myrodata.5"// expected-error {{this causes a section type conflict with 'y'}}
+
 int a;
Index: clang/lib/Sema/SemaDecl.cpp
===
--- clang/lib/Sema/SemaDecl.cpp
+++ clang/lib/Sema/SemaDecl.cpp
@@ -12736,7 +12736,7 @@
   if (GlobalStorage && var->isThisDeclarationADefinition() &&
   !inTemplateInstantiation()) {
 PragmaStack *Stack = nullptr;
-int SectionFlags = ASTContext::PSF_Implicit | ASTContext::PSF_Read;
+int SectionFlags = ASTContext::PSF_Read;
 if (var->getType().isConstQualified())
   Stack = &ConstSegStack;
 else if (!var->getInit()) {
@@ -12746,14 +12746,19 @@
   Stack = &DataSegStack;
   SectionFlags |= ASTContext::PSF_Write;
 }
-if (Stack->CurrentValue && !var->hasAttr())
+if (const SectionAttr *SA = var->getAttr()) {
+  if (SA->getSyntax() == AttributeCommonInfo::AS_Declspec)
+SectionFlags |= ASTContext::PSF_Implicit;
+  UnifySection(SA->getName(), SectionFlags, var);
+} else if (Stack->CurrentValue) {
+  SectionFlags |= ASTContext::PSF_Implicit;
+  auto SectionName = Stack->CurrentValue->getString();
   var->addAttr(SectionAttr::CreateImplicit(
-  Context, Stack->CurrentValue->getString(),
-  Stack->CurrentPragmaLocation, AttributeCommonInfo::AS_Pragma,
-  SectionAttr::Declspec_allocate));
-if (const SectionAttr *SA = var->getAttr())
-  if (UnifySection(SA->getName(), SectionFlags, var))
+  Context, SectionName, Stack->CurrentPragmaLocation,
+  AttributeCommonInfo::AS_Pragma, SectionAttr::Declspec_allocate));
+  if (UnifySection(SectionName, SectionFlags, var))
 var->dropAttr();
+}
 
 // Apply the init_seg attribute if this has an initializer.  If the
 // initializer turns out to not be dynamic, we'll end up ignoring this
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -471,42 +471,49 @@
 bool Sema::UnifySection(StringRef SectionName,
 int SectionFlags,
 DeclaratorDecl *Decl) {
-  auto Section = Context.SectionInfos.find(SectionName);
-  if (Section == Context.SectionInfos.end()) {
+  SourceLocation PragmaLocation;
+  if (auto A = Decl->getAttr())
+if (A->isImplicit())
+  PragmaLocation = A->getLocation();
+  auto SectionIt = Context.SectionInfos.find(SectionName);
+  if (SectionIt == Context.SectionInfos.end()) {
 Context.SectionInfos[SectionName] =
-ASTContext::SectionInfo(Decl, SourceLocation(), SectionFlags);
+ASTContext::SectionInfo(Decl, PragmaLocation, SectionFlags);
 return false;
   }
   // A pre-declared section takes precedence w/o diagnostic.
-  if (Section->second.SectionFlags == SectionFlags ||
-  !(Section->second.SectionFlags & ASTContext::PSF_Implicit))
+  const auto &Section = SectionIt->second;
+  if (Section.SectionFlags == SectionFlags ||
+  ((SectionFlags & ASTContext::PSF_Implicit) &&
+   !(Section.SectionFlags & ASTContext::PSF_Implicit)))
 return false;
-  auto OtherDecl = Section->second.Decl;
-  Diag(Decl->getLocation(), diag::err_section_conflict)
-  << Decl << OtherDecl;
-  Diag(OtherDecl->getLocation(), diag::note_declared_at)
-  << OtherDecl->getName();
-  if (auto A = Decl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
-  if (auto A = OtherDecl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
+  Diag(Decl->getLocation(), diag::err_section_conflict) << Decl << Sectio

[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-04-23 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 259594.
pratlucas added a comment.

Rebasing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78573/new/

https://reviews.llvm.org/D78573

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Sema/SemaAttr.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/test/Sema/pragma-clang-section.c

Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -22,4 +22,9 @@
 #pragma clang section bss = "myrodata.1"   // expected-error {{this causes a section type conflict with a prior #pragma section}}
 #pragma clang section text = "mybss.3" // expected-error {{this causes a section type conflict with a prior #pragma section}}
 
+#pragma clang section rodata = "myrodata.4"  // expected-note {{#pragma entered here}}
+int x __attribute__((section("myrodata.4")));// expected-error {{'x' causes a section type conflict with a prior #pragma section}}
+const int y __attribute__((section("myrodata.5"))) = 10; // expected-note {{declared here}}
+#pragma clang section data = "myrodata.5"// expected-error {{this causes a section type conflict with 'y'}}
+
 int a;
Index: clang/lib/Sema/SemaDecl.cpp
===
--- clang/lib/Sema/SemaDecl.cpp
+++ clang/lib/Sema/SemaDecl.cpp
@@ -12746,7 +12746,7 @@
   if (GlobalStorage && var->isThisDeclarationADefinition() &&
   !inTemplateInstantiation()) {
 PragmaStack *Stack = nullptr;
-int SectionFlags = ASTContext::PSF_Implicit | ASTContext::PSF_Read;
+int SectionFlags = ASTContext::PSF_Read;
 if (var->getType().isConstQualified())
   Stack = &ConstSegStack;
 else if (!var->getInit()) {
@@ -12756,14 +12756,19 @@
   Stack = &DataSegStack;
   SectionFlags |= ASTContext::PSF_Write;
 }
-if (Stack->CurrentValue && !var->hasAttr())
+if (const SectionAttr *SA = var->getAttr()) {
+  if (SA->getSyntax() == AttributeCommonInfo::AS_Declspec)
+SectionFlags |= ASTContext::PSF_Implicit;
+  UnifySection(SA->getName(), SectionFlags, var);
+} else if (Stack->CurrentValue) {
+  SectionFlags |= ASTContext::PSF_Implicit;
+  auto SectionName = Stack->CurrentValue->getString();
   var->addAttr(SectionAttr::CreateImplicit(
-  Context, Stack->CurrentValue->getString(),
-  Stack->CurrentPragmaLocation, AttributeCommonInfo::AS_Pragma,
-  SectionAttr::Declspec_allocate));
-if (const SectionAttr *SA = var->getAttr())
-  if (UnifySection(SA->getName(), SectionFlags, var))
+  Context, SectionName, Stack->CurrentPragmaLocation,
+  AttributeCommonInfo::AS_Pragma, SectionAttr::Declspec_allocate));
+  if (UnifySection(SectionName, SectionFlags, var))
 var->dropAttr();
+}
 
 // Apply the init_seg attribute if this has an initializer.  If the
 // initializer turns out to not be dynamic, we'll end up ignoring this
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -471,42 +471,49 @@
 bool Sema::UnifySection(StringRef SectionName,
 int SectionFlags,
 DeclaratorDecl *Decl) {
-  auto Section = Context.SectionInfos.find(SectionName);
-  if (Section == Context.SectionInfos.end()) {
+  SourceLocation PragmaLocation;
+  if (auto A = Decl->getAttr())
+if (A->isImplicit())
+  PragmaLocation = A->getLocation();
+  auto SectionIt = Context.SectionInfos.find(SectionName);
+  if (SectionIt == Context.SectionInfos.end()) {
 Context.SectionInfos[SectionName] =
-ASTContext::SectionInfo(Decl, SourceLocation(), SectionFlags);
+ASTContext::SectionInfo(Decl, PragmaLocation, SectionFlags);
 return false;
   }
   // A pre-declared section takes precedence w/o diagnostic.
-  if (Section->second.SectionFlags == SectionFlags ||
-  !(Section->second.SectionFlags & ASTContext::PSF_Implicit))
+  const auto &Section = SectionIt->second;
+  if (Section.SectionFlags == SectionFlags ||
+  ((SectionFlags & ASTContext::PSF_Implicit) &&
+   !(Section.SectionFlags & ASTContext::PSF_Implicit)))
 return false;
-  auto OtherDecl = Section->second.Decl;
-  Diag(Decl->getLocation(), diag::err_section_conflict)
-  << Decl << OtherDecl;
-  Diag(OtherDecl->getLocation(), diag::note_declared_at)
-  << OtherDecl->getName();
-  if (auto A = Decl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
-  if (auto A = OtherDecl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
+  Diag(Decl->getLocation(), diag::err_section_conflict) << Decl << Section;
+  if (Section.Dec

[PATCH] D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section

2020-04-23 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 259593.
pratlucas added a comment.

Rebasing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78572/new/

https://reviews.llvm.org/D78572

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/SemaAttr.cpp
  clang/test/Sema/pragma-clang-section.c


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -fsyntax-only -verify %s -triple arm-none-eabi
-#pragma clang section bss="mybss.1" data="mydata.1" rodata="myrodata.1" 
text="mytext.1"
+#pragma clang section bss = "mybss.1" data = "mydata.1" rodata = "myrodata.1" 
text = "mytext.1" // expected-note {{#pragma entered here}} expected-note 
{{#pragma entered here}}
 #pragma clang section bss="" data="" rodata="" text=""
 #pragma clang section
 
@@ -16,4 +16,10 @@
 #pragma clang section text "text.2"   // expected-error {{expected '=' 
following '#pragma clang section text'}}
 #pragma clang section relro "relro.2"   // expected-error {{expected '=' 
following '#pragma clang section relro'}}
 #pragma clang section bss="" data="" rodata="" text="" more //expected-error 
{{expected one of [bss|data|rodata|text|relro] section kind in '#pragma clang 
section'}}
+
+#pragma clang section bss = "mybss.3" data = "mybss.3" // expected-error 
{{this causes a section type conflict with a prior #pragma section}} 
expected-note {{#pragma entered here}} expected-note {{#pragma entered here}}
+#pragma clang section rodata = "mydata.1"  // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+#pragma clang section bss = "myrodata.1"   // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+#pragma clang section text = "mybss.3" // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+
 int a;
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -256,12 +256,15 @@
 void Sema::ActOnPragmaClangSection(SourceLocation PragmaLoc, 
PragmaClangSectionAction Action,
PragmaClangSectionKind SecKind, StringRef 
SecName) {
   PragmaClangSection *CSec;
+  int SectionFlags = ASTContext::PSF_Read;
   switch (SecKind) {
 case PragmaClangSectionKind::PCSK_BSS:
   CSec = &PragmaClangBSSSection;
+  SectionFlags |= ASTContext::PSF_Write | ASTContext::PSF_ZeroInit;
   break;
 case PragmaClangSectionKind::PCSK_Data:
   CSec = &PragmaClangDataSection;
+  SectionFlags |= ASTContext::PSF_Write;
   break;
 case PragmaClangSectionKind::PCSK_Rodata:
   CSec = &PragmaClangRodataSection;
@@ -271,6 +274,7 @@
   break;
 case PragmaClangSectionKind::PCSK_Text:
   CSec = &PragmaClangTextSection;
+  SectionFlags |= ASTContext::PSF_Execute;
   break;
 default:
   llvm_unreachable("invalid clang section kind");
@@ -281,6 +285,9 @@
 return;
   }
 
+  if (UnifySection(SecName, SectionFlags, PragmaLoc))
+return;
+
   CSec->Valid = true;
   CSec->SectionName = std::string(SecName);
   CSec->PragmaLocation = PragmaLoc;
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1845,6 +1845,7 @@
   return;
 }
 
+SourceLocation PragmaLocation = Tok.getLocation();
 PP.Lex(Tok); // eat ['bss'|'data'|'rodata'|'text']
 if (Tok.isNot(tok::equal)) {
   PP.Diag(Tok.getLocation(), 
diag::err_pragma_clang_section_expected_equal) << SecKind;
@@ -1855,10 +1856,11 @@
 if (!PP.LexStringLiteral(Tok, SecName, "pragma clang section", false))
   return;
 
-Actions.ActOnPragmaClangSection(Tok.getLocation(),
-  (SecName.size()? Sema::PragmaClangSectionAction::PCSA_Set :
-   Sema::PragmaClangSectionAction::PCSA_Clear),
-   SecKind, SecName);
+Actions.ActOnPragmaClangSection(
+PragmaLocation,
+(SecName.size() ? Sema::PragmaClangSectionAction::PCSA_Set
+: Sema::PragmaClangSectionAction::PCSA_Clear),
+SecKind, SecName);
   }
 }
 
Index: clang/include/clang/AST/ASTContext.h
===
--- clang/include/clang/AST/ASTContext.h
+++ clang/include/clang/AST/ASTContext.h
@@ -2976,6 +2976,7 @@
 PSF_Write = 0x2,
 PSF_Execute = 0x4,
 PSF_Implicit = 0x8,
+PSF_ZeroInit = 0x10,
 PSF_Invalid = 0x8000U,
   };
 


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/t

[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-04-28 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked 4 inline comments as done.
pratlucas added inline comments.



Comment at: clang/include/clang/AST/ASTContext.h:3008
+/// Insertion operator for diagnostics.
+inline const DiagnosticBuilder &
+operator<<(const DiagnosticBuilder &DB,

rnk wrote:
> It seems like there is no need for this to be defined inline, since it is 
> presumably cold code.
The `inline`'s purpose here is just to allow the definition in the header file, 
avoiding multiple definition errors.



Comment at: clang/test/Sema/pragma-clang-section.c:28
+const int y __attribute__((section("myrodata.5"))) = 10; // expected-note 
{{declared here}}
+#pragma clang section data = "myrodata.5"// expected-error 
{{this causes a section type conflict with 'y'}}
+

rnk wrote:
> Please add a case like:
>   const int y __attribute__((section("myrodata.6"))) = 11;
> There should be no diagnostics in this case, and I expect myrodata.6 to 
> override the pragma, since it is more specific to the declaration.
I've added this case to the test.
The overriding behaviour is already checked by 
`clang/test/CodeGen/clang-sections-attribute.c`.


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[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-04-28 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 260630.
pratlucas added a comment.

Updateing test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78573/new/

https://reviews.llvm.org/D78573

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Sema/SemaAttr.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/test/Sema/pragma-clang-section.c

Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -22,4 +22,10 @@
 #pragma clang section bss = "myrodata.1"   // expected-error {{this causes a section type conflict with a prior #pragma section}}
 #pragma clang section text = "mybss.3" // expected-error {{this causes a section type conflict with a prior #pragma section}}
 
+#pragma clang section rodata = "myrodata.4"  // expected-note {{#pragma entered here}}
+int x __attribute__((section("myrodata.4")));// expected-error {{'x' causes a section type conflict with a prior #pragma section}}
+const int y __attribute__((section("myrodata.5"))) = 10; // expected-note {{declared here}}
+#pragma clang section data = "myrodata.5"// expected-error {{this causes a section type conflict with 'y'}}
+const int z __attribute__((section("myrodata.6"))) = 11;
+
 int a;
Index: clang/lib/Sema/SemaDecl.cpp
===
--- clang/lib/Sema/SemaDecl.cpp
+++ clang/lib/Sema/SemaDecl.cpp
@@ -12754,7 +12754,7 @@
   if (GlobalStorage && var->isThisDeclarationADefinition() &&
   !inTemplateInstantiation()) {
 PragmaStack *Stack = nullptr;
-int SectionFlags = ASTContext::PSF_Implicit | ASTContext::PSF_Read;
+int SectionFlags = ASTContext::PSF_Read;
 if (var->getType().isConstQualified())
   Stack = &ConstSegStack;
 else if (!var->getInit()) {
@@ -12764,14 +12764,19 @@
   Stack = &DataSegStack;
   SectionFlags |= ASTContext::PSF_Write;
 }
-if (Stack->CurrentValue && !var->hasAttr())
+if (const SectionAttr *SA = var->getAttr()) {
+  if (SA->getSyntax() == AttributeCommonInfo::AS_Declspec)
+SectionFlags |= ASTContext::PSF_Implicit;
+  UnifySection(SA->getName(), SectionFlags, var);
+} else if (Stack->CurrentValue) {
+  SectionFlags |= ASTContext::PSF_Implicit;
+  auto SectionName = Stack->CurrentValue->getString();
   var->addAttr(SectionAttr::CreateImplicit(
-  Context, Stack->CurrentValue->getString(),
-  Stack->CurrentPragmaLocation, AttributeCommonInfo::AS_Pragma,
-  SectionAttr::Declspec_allocate));
-if (const SectionAttr *SA = var->getAttr())
-  if (UnifySection(SA->getName(), SectionFlags, var))
+  Context, SectionName, Stack->CurrentPragmaLocation,
+  AttributeCommonInfo::AS_Pragma, SectionAttr::Declspec_allocate));
+  if (UnifySection(SectionName, SectionFlags, var))
 var->dropAttr();
+}
 
 // Apply the init_seg attribute if this has an initializer.  If the
 // initializer turns out to not be dynamic, we'll end up ignoring this
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -471,42 +471,49 @@
 bool Sema::UnifySection(StringRef SectionName,
 int SectionFlags,
 DeclaratorDecl *Decl) {
-  auto Section = Context.SectionInfos.find(SectionName);
-  if (Section == Context.SectionInfos.end()) {
+  SourceLocation PragmaLocation;
+  if (auto A = Decl->getAttr())
+if (A->isImplicit())
+  PragmaLocation = A->getLocation();
+  auto SectionIt = Context.SectionInfos.find(SectionName);
+  if (SectionIt == Context.SectionInfos.end()) {
 Context.SectionInfos[SectionName] =
-ASTContext::SectionInfo(Decl, SourceLocation(), SectionFlags);
+ASTContext::SectionInfo(Decl, PragmaLocation, SectionFlags);
 return false;
   }
   // A pre-declared section takes precedence w/o diagnostic.
-  if (Section->second.SectionFlags == SectionFlags ||
-  !(Section->second.SectionFlags & ASTContext::PSF_Implicit))
+  const auto &Section = SectionIt->second;
+  if (Section.SectionFlags == SectionFlags ||
+  ((SectionFlags & ASTContext::PSF_Implicit) &&
+   !(Section.SectionFlags & ASTContext::PSF_Implicit)))
 return false;
-  auto OtherDecl = Section->second.Decl;
-  Diag(Decl->getLocation(), diag::err_section_conflict)
-  << Decl << OtherDecl;
-  Diag(OtherDecl->getLocation(), diag::note_declared_at)
-  << OtherDecl->getName();
-  if (auto A = Decl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
-  if (auto A = OtherDecl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
+  Diag(Decl->getLocation(), d

[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-05-05 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

Ping.


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[PATCH] D75169: [ARM] Enforcing calling convention for half-precision FP arguments and returns for big-endian AArch32

2020-05-05 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

Ping.


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[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-05-07 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 262594.
pratlucas added a comment.

Addressing review comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78573/new/

https://reviews.llvm.org/D78573

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaAttr.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/test/Sema/pragma-clang-section.c

Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -22,4 +22,10 @@
 #pragma clang section bss = "myrodata.1"   // expected-error {{this causes a section type conflict with a prior #pragma section}}
 #pragma clang section text = "mybss.3" // expected-error {{this causes a section type conflict with a prior #pragma section}}
 
+#pragma clang section rodata = "myrodata.4"  // expected-note {{#pragma entered here}}
+int x __attribute__((section("myrodata.4")));// expected-error {{'x' causes a section type conflict with a prior #pragma section}}
+const int y __attribute__((section("myrodata.5"))) = 10; // expected-note {{declared here}}
+#pragma clang section data = "myrodata.5"// expected-error {{this causes a section type conflict with 'y'}}
+const int z __attribute__((section("myrodata.6"))) = 11;
+
 int a;
Index: clang/lib/Sema/SemaDecl.cpp
===
--- clang/lib/Sema/SemaDecl.cpp
+++ clang/lib/Sema/SemaDecl.cpp
@@ -12754,7 +12754,7 @@
   if (GlobalStorage && var->isThisDeclarationADefinition() &&
   !inTemplateInstantiation()) {
 PragmaStack *Stack = nullptr;
-int SectionFlags = ASTContext::PSF_Implicit | ASTContext::PSF_Read;
+int SectionFlags = ASTContext::PSF_Read;
 if (var->getType().isConstQualified())
   Stack = &ConstSegStack;
 else if (!var->getInit()) {
@@ -12764,14 +12764,19 @@
   Stack = &DataSegStack;
   SectionFlags |= ASTContext::PSF_Write;
 }
-if (Stack->CurrentValue && !var->hasAttr())
+if (const SectionAttr *SA = var->getAttr()) {
+  if (SA->getSyntax() == AttributeCommonInfo::AS_Declspec)
+SectionFlags |= ASTContext::PSF_Implicit;
+  UnifySection(SA->getName(), SectionFlags, var);
+} else if (Stack->CurrentValue) {
+  SectionFlags |= ASTContext::PSF_Implicit;
+  auto SectionName = Stack->CurrentValue->getString();
   var->addAttr(SectionAttr::CreateImplicit(
-  Context, Stack->CurrentValue->getString(),
-  Stack->CurrentPragmaLocation, AttributeCommonInfo::AS_Pragma,
-  SectionAttr::Declspec_allocate));
-if (const SectionAttr *SA = var->getAttr())
-  if (UnifySection(SA->getName(), SectionFlags, var))
+  Context, SectionName, Stack->CurrentPragmaLocation,
+  AttributeCommonInfo::AS_Pragma, SectionAttr::Declspec_allocate));
+  if (UnifySection(SectionName, SectionFlags, var))
 var->dropAttr();
+}
 
 // Apply the init_seg attribute if this has an initializer.  If the
 // initializer turns out to not be dynamic, we'll end up ignoring this
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -530,42 +530,49 @@
 bool Sema::UnifySection(StringRef SectionName,
 int SectionFlags,
 DeclaratorDecl *Decl) {
-  auto Section = Context.SectionInfos.find(SectionName);
-  if (Section == Context.SectionInfos.end()) {
+  SourceLocation PragmaLocation;
+  if (auto A = Decl->getAttr())
+if (A->isImplicit())
+  PragmaLocation = A->getLocation();
+  auto SectionIt = Context.SectionInfos.find(SectionName);
+  if (SectionIt == Context.SectionInfos.end()) {
 Context.SectionInfos[SectionName] =
-ASTContext::SectionInfo(Decl, SourceLocation(), SectionFlags);
+ASTContext::SectionInfo(Decl, PragmaLocation, SectionFlags);
 return false;
   }
   // A pre-declared section takes precedence w/o diagnostic.
-  if (Section->second.SectionFlags == SectionFlags ||
-  !(Section->second.SectionFlags & ASTContext::PSF_Implicit))
+  const auto &Section = SectionIt->second;
+  if (Section.SectionFlags == SectionFlags ||
+  ((SectionFlags & ASTContext::PSF_Implicit) &&
+   !(Section.SectionFlags & ASTContext::PSF_Implicit)))
 return false;
-  auto OtherDecl = Section->second.Decl;
-  Diag(Decl->getLocation(), diag::err_section_conflict)
-  << Decl << OtherDecl;
-  Diag(OtherDecl->getLocation(), diag::note_declared_at)
-  << OtherDecl->getName();
-  if (auto A = Decl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
-  if (auto A = OtherDecl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_ent

[PATCH] D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section

2020-05-07 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 262592.
pratlucas added a comment.

Addressing review comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78572/new/

https://reviews.llvm.org/D78572

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/SemaAttr.cpp
  clang/test/Sema/pragma-clang-section.c


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -fsyntax-only -verify %s -triple arm-none-eabi
-#pragma clang section bss="mybss.1" data="mydata.1" rodata="myrodata.1" 
text="mytext.1"
+#pragma clang section bss = "mybss.1" data = "mydata.1" rodata = "myrodata.1" 
text = "mytext.1" // expected-note 2 {{#pragma entered here}}
 #pragma clang section bss="" data="" rodata="" text=""
 #pragma clang section
 
@@ -16,4 +16,10 @@
 #pragma clang section text "text.2"   // expected-error {{expected '=' 
following '#pragma clang section text'}}
 #pragma clang section relro "relro.2"   // expected-error {{expected '=' 
following '#pragma clang section relro'}}
 #pragma clang section bss="" data="" rodata="" text="" more //expected-error 
{{expected one of [bss|data|rodata|text|relro] section kind in '#pragma clang 
section'}}
+
+#pragma clang section bss = "mybss.3" data = "mybss.3" // expected-error 
{{this causes a section type conflict with a prior #pragma section}} 
expected-note {{#pragma entered here}} expected-note {{#pragma entered here}}
+#pragma clang section rodata = "mydata.1"  // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+#pragma clang section bss = "myrodata.1"   // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+#pragma clang section text = "mybss.3" // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+
 int a;
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -256,12 +256,15 @@
 void Sema::ActOnPragmaClangSection(SourceLocation PragmaLoc, 
PragmaClangSectionAction Action,
PragmaClangSectionKind SecKind, StringRef 
SecName) {
   PragmaClangSection *CSec;
+  int SectionFlags = ASTContext::PSF_Read;
   switch (SecKind) {
 case PragmaClangSectionKind::PCSK_BSS:
   CSec = &PragmaClangBSSSection;
+  SectionFlags |= ASTContext::PSF_Write | ASTContext::PSF_ZeroInit;
   break;
 case PragmaClangSectionKind::PCSK_Data:
   CSec = &PragmaClangDataSection;
+  SectionFlags |= ASTContext::PSF_Write;
   break;
 case PragmaClangSectionKind::PCSK_Rodata:
   CSec = &PragmaClangRodataSection;
@@ -271,6 +274,7 @@
   break;
 case PragmaClangSectionKind::PCSK_Text:
   CSec = &PragmaClangTextSection;
+  SectionFlags |= ASTContext::PSF_Execute;
   break;
 default:
   llvm_unreachable("invalid clang section kind");
@@ -281,6 +285,9 @@
 return;
   }
 
+  if (UnifySection(SecName, SectionFlags, PragmaLoc))
+return;
+
   CSec->Valid = true;
   CSec->SectionName = std::string(SecName);
   CSec->PragmaLocation = PragmaLoc;
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1873,6 +1873,7 @@
   return;
 }
 
+SourceLocation PragmaLocation = Tok.getLocation();
 PP.Lex(Tok); // eat ['bss'|'data'|'rodata'|'text']
 if (Tok.isNot(tok::equal)) {
   PP.Diag(Tok.getLocation(), 
diag::err_pragma_clang_section_expected_equal) << SecKind;
@@ -1883,10 +1884,11 @@
 if (!PP.LexStringLiteral(Tok, SecName, "pragma clang section", false))
   return;
 
-Actions.ActOnPragmaClangSection(Tok.getLocation(),
-  (SecName.size()? Sema::PragmaClangSectionAction::PCSA_Set :
-   Sema::PragmaClangSectionAction::PCSA_Clear),
-   SecKind, SecName);
+Actions.ActOnPragmaClangSection(
+PragmaLocation,
+(SecName.size() ? Sema::PragmaClangSectionAction::PCSA_Set
+: Sema::PragmaClangSectionAction::PCSA_Clear),
+SecKind, SecName);
   }
 }
 
Index: clang/include/clang/AST/ASTContext.h
===
--- clang/include/clang/AST/ASTContext.h
+++ clang/include/clang/AST/ASTContext.h
@@ -2978,6 +2978,7 @@
 PSF_Write = 0x2,
 PSF_Execute = 0x4,
 PSF_Implicit = 0x8,
+PSF_ZeroInit = 0x10,
 PSF_Invalid = 0x8000U,
   };
 


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang

[PATCH] D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section

2020-05-07 Thread Lucas Prates via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG0dac639f285a: [Clang][Sema] Capturing section type conflicts 
on #pragma clang section (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78572/new/

https://reviews.llvm.org/D78572

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/SemaAttr.cpp
  clang/test/Sema/pragma-clang-section.c


Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -fsyntax-only -verify %s -triple arm-none-eabi
-#pragma clang section bss="mybss.1" data="mydata.1" rodata="myrodata.1" 
text="mytext.1"
+#pragma clang section bss = "mybss.1" data = "mydata.1" rodata = "myrodata.1" 
text = "mytext.1" // expected-note 2 {{#pragma entered here}}
 #pragma clang section bss="" data="" rodata="" text=""
 #pragma clang section
 
@@ -16,4 +16,10 @@
 #pragma clang section text "text.2"   // expected-error {{expected '=' 
following '#pragma clang section text'}}
 #pragma clang section relro "relro.2"   // expected-error {{expected '=' 
following '#pragma clang section relro'}}
 #pragma clang section bss="" data="" rodata="" text="" more //expected-error 
{{expected one of [bss|data|rodata|text|relro] section kind in '#pragma clang 
section'}}
+
+#pragma clang section bss = "mybss.3" data = "mybss.3" // expected-error 
{{this causes a section type conflict with a prior #pragma section}} 
expected-note {{#pragma entered here}} expected-note {{#pragma entered here}}
+#pragma clang section rodata = "mydata.1"  // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+#pragma clang section bss = "myrodata.1"   // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+#pragma clang section text = "mybss.3" // expected-error 
{{this causes a section type conflict with a prior #pragma section}}
+
 int a;
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -256,12 +256,15 @@
 void Sema::ActOnPragmaClangSection(SourceLocation PragmaLoc, 
PragmaClangSectionAction Action,
PragmaClangSectionKind SecKind, StringRef 
SecName) {
   PragmaClangSection *CSec;
+  int SectionFlags = ASTContext::PSF_Read;
   switch (SecKind) {
 case PragmaClangSectionKind::PCSK_BSS:
   CSec = &PragmaClangBSSSection;
+  SectionFlags |= ASTContext::PSF_Write | ASTContext::PSF_ZeroInit;
   break;
 case PragmaClangSectionKind::PCSK_Data:
   CSec = &PragmaClangDataSection;
+  SectionFlags |= ASTContext::PSF_Write;
   break;
 case PragmaClangSectionKind::PCSK_Rodata:
   CSec = &PragmaClangRodataSection;
@@ -271,6 +274,7 @@
   break;
 case PragmaClangSectionKind::PCSK_Text:
   CSec = &PragmaClangTextSection;
+  SectionFlags |= ASTContext::PSF_Execute;
   break;
 default:
   llvm_unreachable("invalid clang section kind");
@@ -281,6 +285,9 @@
 return;
   }
 
+  if (UnifySection(SecName, SectionFlags, PragmaLoc))
+return;
+
   CSec->Valid = true;
   CSec->SectionName = std::string(SecName);
   CSec->PragmaLocation = PragmaLoc;
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1873,6 +1873,7 @@
   return;
 }
 
+SourceLocation PragmaLocation = Tok.getLocation();
 PP.Lex(Tok); // eat ['bss'|'data'|'rodata'|'text']
 if (Tok.isNot(tok::equal)) {
   PP.Diag(Tok.getLocation(), 
diag::err_pragma_clang_section_expected_equal) << SecKind;
@@ -1883,10 +1884,11 @@
 if (!PP.LexStringLiteral(Tok, SecName, "pragma clang section", false))
   return;
 
-Actions.ActOnPragmaClangSection(Tok.getLocation(),
-  (SecName.size()? Sema::PragmaClangSectionAction::PCSA_Set :
-   Sema::PragmaClangSectionAction::PCSA_Clear),
-   SecKind, SecName);
+Actions.ActOnPragmaClangSection(
+PragmaLocation,
+(SecName.size() ? Sema::PragmaClangSectionAction::PCSA_Set
+: Sema::PragmaClangSectionAction::PCSA_Clear),
+SecKind, SecName);
   }
 }
 
Index: clang/include/clang/AST/ASTContext.h
===
--- clang/include/clang/AST/ASTContext.h
+++ clang/include/clang/AST/ASTContext.h
@@ -2978,6 +2978,7 @@
 PSF_Write = 0x2,
 PSF_Execute = 0x4,
 PSF_Implicit = 0x8,
+PSF_ZeroInit = 0x10,
 PSF_Invalid = 0x8000U,
   };
 


Index: clang/test/Sema/pragma-clang-section.c
==

[PATCH] D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes

2020-05-07 Thread Lucas Prates via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG9d39df03a984: [Clang][Sema] Capturing section type conflicts 
between #pragma clang section… (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78573/new/

https://reviews.llvm.org/D78573

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaAttr.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/test/Sema/pragma-clang-section.c

Index: clang/test/Sema/pragma-clang-section.c
===
--- clang/test/Sema/pragma-clang-section.c
+++ clang/test/Sema/pragma-clang-section.c
@@ -22,4 +22,10 @@
 #pragma clang section bss = "myrodata.1"   // expected-error {{this causes a section type conflict with a prior #pragma section}}
 #pragma clang section text = "mybss.3" // expected-error {{this causes a section type conflict with a prior #pragma section}}
 
+#pragma clang section rodata = "myrodata.4"  // expected-note {{#pragma entered here}}
+int x __attribute__((section("myrodata.4")));// expected-error {{'x' causes a section type conflict with a prior #pragma section}}
+const int y __attribute__((section("myrodata.5"))) = 10; // expected-note {{declared here}}
+#pragma clang section data = "myrodata.5"// expected-error {{this causes a section type conflict with 'y'}}
+const int z __attribute__((section("myrodata.6"))) = 11;
+
 int a;
Index: clang/lib/Sema/SemaDecl.cpp
===
--- clang/lib/Sema/SemaDecl.cpp
+++ clang/lib/Sema/SemaDecl.cpp
@@ -12754,7 +12754,7 @@
   if (GlobalStorage && var->isThisDeclarationADefinition() &&
   !inTemplateInstantiation()) {
 PragmaStack *Stack = nullptr;
-int SectionFlags = ASTContext::PSF_Implicit | ASTContext::PSF_Read;
+int SectionFlags = ASTContext::PSF_Read;
 if (var->getType().isConstQualified())
   Stack = &ConstSegStack;
 else if (!var->getInit()) {
@@ -12764,14 +12764,19 @@
   Stack = &DataSegStack;
   SectionFlags |= ASTContext::PSF_Write;
 }
-if (Stack->CurrentValue && !var->hasAttr())
+if (const SectionAttr *SA = var->getAttr()) {
+  if (SA->getSyntax() == AttributeCommonInfo::AS_Declspec)
+SectionFlags |= ASTContext::PSF_Implicit;
+  UnifySection(SA->getName(), SectionFlags, var);
+} else if (Stack->CurrentValue) {
+  SectionFlags |= ASTContext::PSF_Implicit;
+  auto SectionName = Stack->CurrentValue->getString();
   var->addAttr(SectionAttr::CreateImplicit(
-  Context, Stack->CurrentValue->getString(),
-  Stack->CurrentPragmaLocation, AttributeCommonInfo::AS_Pragma,
-  SectionAttr::Declspec_allocate));
-if (const SectionAttr *SA = var->getAttr())
-  if (UnifySection(SA->getName(), SectionFlags, var))
+  Context, SectionName, Stack->CurrentPragmaLocation,
+  AttributeCommonInfo::AS_Pragma, SectionAttr::Declspec_allocate));
+  if (UnifySection(SectionName, SectionFlags, var))
 var->dropAttr();
+}
 
 // Apply the init_seg attribute if this has an initializer.  If the
 // initializer turns out to not be dynamic, we'll end up ignoring this
Index: clang/lib/Sema/SemaAttr.cpp
===
--- clang/lib/Sema/SemaAttr.cpp
+++ clang/lib/Sema/SemaAttr.cpp
@@ -530,42 +530,49 @@
 bool Sema::UnifySection(StringRef SectionName,
 int SectionFlags,
 DeclaratorDecl *Decl) {
-  auto Section = Context.SectionInfos.find(SectionName);
-  if (Section == Context.SectionInfos.end()) {
+  SourceLocation PragmaLocation;
+  if (auto A = Decl->getAttr())
+if (A->isImplicit())
+  PragmaLocation = A->getLocation();
+  auto SectionIt = Context.SectionInfos.find(SectionName);
+  if (SectionIt == Context.SectionInfos.end()) {
 Context.SectionInfos[SectionName] =
-ASTContext::SectionInfo(Decl, SourceLocation(), SectionFlags);
+ASTContext::SectionInfo(Decl, PragmaLocation, SectionFlags);
 return false;
   }
   // A pre-declared section takes precedence w/o diagnostic.
-  if (Section->second.SectionFlags == SectionFlags ||
-  !(Section->second.SectionFlags & ASTContext::PSF_Implicit))
+  const auto &Section = SectionIt->second;
+  if (Section.SectionFlags == SectionFlags ||
+  ((SectionFlags & ASTContext::PSF_Implicit) &&
+   !(Section.SectionFlags & ASTContext::PSF_Implicit)))
 return false;
-  auto OtherDecl = Section->second.Decl;
-  Diag(Decl->getLocation(), diag::err_section_conflict)
-  << Decl << OtherDecl;
-  Diag(OtherDecl->getLocation(), diag::note_declared_at)
-  << OtherDecl->getName();
-  if (auto A = Decl->getAttr())
-if (A->isImplicit())
-  Diag(A->getLocation(), diag::note_pragma_entered_here);
-  if (a

[PATCH] D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts

2020-05-11 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: cfe-commits, danielkiss, kristof.beyls.
Herald added a project: clang.
pratlucas added reviewers: t.p.northover, ostannard, pcc.

During CodeGen for AArch64 Neon intrinsics, Clang was incorrectly
assuming all the pointers from which loads were being generated for vld1
intrinsics were aligned according to the intrinsics result type, causing
alignment faults on the code generated by the backend.

This patch updates vld1 intrinsics' CodeGen to properly capture the
correct load alignment based on the type of the pointer provided as
input for the intrinsic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79721

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-intrinsics.c

Index: clang/test/CodeGen/aarch64-neon-intrinsics.c
===
--- clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -8956,7 +8956,7 @@
 
 // CHECK-LABEL: @test_vld1q_u8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 uint8x16_t test_vld1q_u8(uint8_t const *a) {
   return vld1q_u8(a);
@@ -8965,7 +8965,7 @@
 // CHECK-LABEL: @test_vld1q_u16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 uint16x8_t test_vld1q_u16(uint16_t const *a) {
   return vld1q_u16(a);
@@ -8974,7 +8974,7 @@
 // CHECK-LABEL: @test_vld1q_u32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 uint32x4_t test_vld1q_u32(uint32_t const *a) {
   return vld1q_u32(a);
@@ -8983,7 +8983,7 @@
 // CHECK-LABEL: @test_vld1q_u64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 uint64x2_t test_vld1q_u64(uint64_t const *a) {
   return vld1q_u64(a);
@@ -8991,7 +8991,7 @@
 
 // CHECK-LABEL: @test_vld1q_s8(
 // CHECK:   [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK:   [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
 // CHECK:   ret <16 x i8> [[TMP1]]
 int8x16_t test_vld1q_s8(int8_t const *a) {
   return vld1q_s8(a);
@@ -9000,7 +9000,7 @@
 // CHECK-LABEL: @test_vld1q_s16(
 // CHECK:   [[TMP0:%.*]] = bitcast i16* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
 // CHECK:   ret <8 x i16> [[TMP2]]
 int16x8_t test_vld1q_s16(int16_t const *a) {
   return vld1q_s16(a);
@@ -9009,7 +9009,7 @@
 // CHECK-LABEL: @test_vld1q_s32(
 // CHECK:   [[TMP0:%.*]] = bitcast i32* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
 // CHECK:   ret <4 x i32> [[TMP2]]
 int32x4_t test_vld1q_s32(int32_t const *a) {
   return vld1q_s32(a);
@@ -9018,7 +9018,7 @@
 // CHECK-LABEL: @test_vld1q_s64(
 // CHECK:   [[TMP0:%.*]] = bitcast i64* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
-// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
 // CHECK:   ret <2 x i64> [[TMP2]]
 int64x2_t test_vld1q_s64(int64_t const *a) {
   return vld1q_s64(a);
@@ -9027,7 +9027,7 @@
 // CHECK-LABEL: @test_vld1q_f16(
 // CHECK:   [[TMP0:%.*]] = bitcast half* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
-// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]], align 2
 // CHECK:   ret <8 x half> [[TMP2]]
 float16x8_t test_vld1q_f16(float16_t const *a) {
   return vld1q_f16(a);
@@ -9036,7 +9036,7 @@
 // CHECK-LABEL: @test_vld1q_f32(
 // CHECK:   [[TMP0:%.*]] = bitcast float* %a to i8*
 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x float>*
-// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]]
+// CHECK:   [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
 // CHECK:   ret <4 x float> [[TMP2]]
 float32x4_t test_vld1q_f

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-27 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 440189.
pratlucas added a comment.

Updating method to use `MAchineBasickBlock::iterator&`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,274 @@
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all --verify-machineinstrs | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {pc}
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7, pc}
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AAPCS-NEXT:.save {lr}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:mov lr, r11
+; FP-AAPCS-NEXT:.save {r11}
+; FP-AA

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-27 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG70a5c525349b: [ARM][Thumb] Command-line option to ensure 
AAPCS compliant Frame Records (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,274 @@
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all --verify-machineinstrs | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {pc}
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7, pc}
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AA

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-06 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
pratlucas requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Currently the a AAPCS compliant frame record is not always created for
functions when it should. Although a consistent frame record might not
be required in some cases, there are still scenarios where applications
may want to make use of the call hierarchy made available trough it.

In order to enable the use of AAPCS compliant frame records whilst keep
backwards compatibility, this patch introduces a new command-line option
(`-mframe-chain=[none|aapcs|aapcs+leaf]`) for Aarch32 and Thumb backends.
The option allows users to explicitly select when to use it, and is also
useful to ensure the extra overhead introduced by the frame records is
only introduced when necessary, in particular for Thumb targets.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,301 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:add r11, sp, #0
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {lr}
+; LEAF-FP-AAPCS-NEXT:mov r11, lr
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.save {lr}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov lr, r11
+; LEAF-NOFP-AAPCS-NEXT:.save {r11}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-NOFP-AAPCS-NEXT:add r11, sp, #0
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:pop {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov r11, lr
+; LEAF-NOFP-AAPCS-NEXT:pop {r1}
+; LEAF-NOFP-AAPCS-NEXT:bx r1
+  %2 = alloca i32, align 4
+  store i32

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-06 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 427632.
pratlucas added a comment.

Addressing linting messages.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,301 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:add r11, sp, #0
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {lr}
+; LEAF-FP-AAPCS-NEXT:mov r11, lr
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.save {lr}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov lr, r11
+; LEAF-NOFP-AAPCS-NEXT:.save {r11}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-NOFP-AAPCS-NEXT:add r11, sp, #0
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:pop {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov r11, lr
+; LEAF-NOFP-AAPCS-NEXT:pop {r1}
+; LEAF-NOFP-AAPCS-NEXT:bx r1
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:bx r1
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AAPCS-NEXT:.save {lr}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:mov lr, r11
+; FP-AAPCS-NEXT:.save {r11}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:.set

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-13 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 429237.
pratlucas added a comment.

Adding frame access test coverage, adding check for FrameSetup flag and 
adjusting calculation of FP value.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,305 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:add r11, sp, #0
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {lr}
+; LEAF-FP-AAPCS-NEXT:mov r11, lr
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.save {lr}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov lr, r11
+; LEAF-NOFP-AAPCS-NEXT:.save {r11}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-NOFP-AAPCS-NEXT:add r11, sp, #0
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:pop {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov r11, lr
+; LEAF-NOFP-AAPCS-NEXT:pop {r1}
+; LEAF-NOFP-AAPCS-NEXT:bx r1
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-13 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked an inline comment as done.
pratlucas added inline comments.



Comment at: llvm/lib/Target/ARM/Thumb1FrameLowering.cpp:242
+  // Find last push instruction for GPRCS2 - spilling of high registers
+  // (r8-r11) could consist of multiple tPUSH and tMOVr instructions.
+  while (true) {

efriedma wrote:
> It seems sort of fragile to assume the entry block doesn't contain any tPUSH 
> instructions; we can use them in places other than the prologue.  Can we use 
> the FrameSetup flag?
This approach is fragile indeed, I guess the fact that high reg spills are less 
usual has helpep it go unnoticed for so long.
I've added the checks for the FrameSetup flag to make sure it doesn't run over 
into unrelated instructions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

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[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-18 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 430324.
pratlucas marked an inline comment as done.
pratlucas added a comment.

Fix incorrect use of r11 on load/store instructions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,305 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:add r11, sp, #0
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {lr}
+; LEAF-FP-AAPCS-NEXT:mov r11, lr
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.save {lr}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov lr, r11
+; LEAF-NOFP-AAPCS-NEXT:.save {r11}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-NOFP-AAPCS-NEXT:add r11, sp, #0
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:pop {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov r11, lr
+; LEAF-NOFP-AAPCS-NEXT:pop {r1}
+; LEAF-NOFP-AAPCS-NEXT:bx r1
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+;

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-20 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked 4 inline comments as done.
pratlucas added inline comments.



Comment at: llvm/lib/Target/ARM/ARMFrameLowering.cpp:1844
+for (const auto &MI : MBB)
+  if (MI.getOpcode() == ARM::tSTRspi || MI.getOpcode() == ARM::tSTRi)
+for (const auto &Op : MI.operands())

efriedma wrote:
> How do you end up with tSTRi with a frameindex operand?  SelectionDAG won't 
> generate that, I think.
Indeed I didn't hit any case where tSTRi was emitted during my tests, but I 
included it here to be on the safe side given the contents of the comment on 
line 2050. I'm happy to remove it if it's indeed not necessary.



Comment at: llvm/lib/Target/ARM/ARMFrameLowering.cpp:2110
+  if ((requiresAAPCSFrameRecord(MF) ||
+   MF.getTarget().Options.DisableFramePointerElim(MF)) &&
+  !LRSpilled) {

efriedma wrote:
> Should requiresAAPCSFrameRecord() be orthogonal to DisableFramePointerElim()? 
>  I mean, we have a complete set of flags controlling frame pointer 
> elimination; the only part that's "new" here is that the frame pointer is 
> stored in r11, instead of r7.
For cases where a function's codegen requires the use of a frame pointer, we 
want an AAPCS compliant frame record to be generated even when the frame 
pointer elimination is enabled. For that reason we need the two options to be 
orthogonal on some level.
I've updated this check to be more strict and only consider 
`requiresAAPCSFrameRecord()` when the function has a frame pointer.



Comment at: llvm/test/CodeGen/Thumb/frame-access.ll:73
+; CHECK-AAPCS: mov r0, r11
+; CHECK-AAPCS: str r1, [r0, #8]
+; CHECK-AAPCS: mov r0, r11

efriedma wrote:
> Can we use sp-relative accesses here?  If we're not doing dynamic 
> allocations, it should be a fixed offset.
The current criteria for the Arm and Thumb backends is that fixed  frame 
indices are always accessed through FP whenever it is available (See [[ 
https://github.com/llvm/llvm-project/blob/aed49eac87b8aa77298252ea781bae4725ae8046/llvm/lib/Target/ARM/ARMFrameLowering.cpp#L1083
 | ARMFrameLowering.cpp ]]).
I guess that could be changed, but I feel it would fall outside the scope of 
this patch.


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[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-20 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 430991.
pratlucas marked 2 inline comments as done.
pratlucas added a comment.

Addressing review comments.


Repository:
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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,304 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.save {lr}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:mov lr, r11
+; LEAF-NOFP-AAPCS-NEXT:.save {r11}
+; LEAF-NOFP-AAPCS-NEXT:push {lr}
+; LEAF-NOFP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-NOFP-AAPCS-NEXT:mov r11, sp
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:pop {r1}
+; LEAF-NOFP-AAPCS-NEXT:mov r11, r1
+; LEAF-NOFP-AAPCS-NEXT:pop {r1}
+; LEAF-NOFP-AAPCS-NEXT:bx r1
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-24 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 431634.
pratlucas marked 2 inline comments as done.
pratlucas added a comment.

Avoiding unecessary uses of FP and addressing review comments.


Repository:
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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,288 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:bx r1
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AAPCS-NEXT:.save {lr}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:mov lr, r11
+; FP-AAPCS-NEXT:.save {r11}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:.setfp r11, sp
+; FP-AAPCS-NEXT:mov r11, sp
+; FP-AAPCS-NEXT:

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-05-24 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked 2 inline comments as done.
pratlucas added inline comments.



Comment at: llvm/lib/Target/ARM/Thumb1FrameLowering.cpp:1167
+   STI.hasV5TOps());
+  // Only unused return registers can be used as copy regs at this point
+  popRegsFromStack(MBB, MI, TII, FrameRecord, UnusedReturnRegs, IsVarArg,

efriedma wrote:
> Are we actually guaranteed to have any unused return registers at this point? 
>  The calling convention uses r0-r3 to return values.
Although unlikely in thumb1, we could run out of return registers here indeed 
(the calling convention only uses `r2` and `r3` to return 128-bit containerized 
vectors).
I've updated the code to make use of a scratch register if that ever happens. 
This required D126285, a minor NFC change so it could work correctly.



Comment at: llvm/test/CodeGen/Thumb/frame-access.ll:73
+; CHECK-AAPCS: mov r0, r11
+; CHECK-AAPCS: str r1, [r0, #8]
+; CHECK-AAPCS: mov r0, r11

efriedma wrote:
> pratlucas wrote:
> > efriedma wrote:
> > > Can we use sp-relative accesses here?  If we're not doing dynamic 
> > > allocations, it should be a fixed offset.
> > The current criteria for the Arm and Thumb backends is that fixed  frame 
> > indices are always accessed through FP whenever it is available (See [[ 
> > https://github.com/llvm/llvm-project/blob/aed49eac87b8aa77298252ea781bae4725ae8046/llvm/lib/Target/ARM/ARMFrameLowering.cpp#L1083
> >  | ARMFrameLowering.cpp ]]).
> > I guess that could be changed, but I feel it would fall outside the scope 
> > of this patch.
> This patch does make it much more likely that fp-relative accesses are going 
> to be out of range, but sure, I guess we can treat it as a separate issue.
That's a good point. I've pondered over this for a bit and realized that this 
is not the intended behaviour - we want FP and the frame record to be compliant 
with AAPCS in the scenarios where they're supposed to be generated and not to 
make its use more likely.
I've updated the code to match this. The expected behaviour when using the new 
option should be:

  - `r11` is set as the frame pointer - It should be reserved and not used as a 
general purpose register
  - For a function, an AAPCS compliant frame record should be created and `r11` 
should point to its location on the stack if:
- Frame pointer elimination is disabled for the function (leaf vs non-leaf)
- Codegen requires the use of FP






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[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-08-25 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

Hi @hans , I'll have a look at it!


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[PATCH] D91776: [ARM][AAarch64] Initial command-line support for v8.7-A

2020-12-14 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 311624.
pratlucas added a comment.

Rebasing.


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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/aarch64-ls64.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1100,6 +1100,8 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv8.6-a", "generic", "v8.6a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv8.7-a", "generic", "v8.7a",
+  ARMBuildAttrs::CPUArch::v8_A));
 }
 
 bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -5354,6 +5354,7 @@
 case AArch64::ArchKind::ARMV8_4A:
 case AArch64::ArchKind::ARMV8_5A:
 case AArch64::ArchKind::ARMV8_6A:
+case AArch64::ArchKind::ARMV8_7A:
 case AArch64::ArchKind::ARMV8R:
   RequestedExtensions.push_back("sm4");
   RequestedExtensions.push_back("sha3");
@@ -5375,6 +5376,7 @@
 case AArch64::ArchKind::ARMV8_4A:
 case AArch64::ArchKind::ARMV8_5A:
 case AArch64::ArchKind::ARMV8_6A:
+case AArch64::ArchKind::ARMV8_7A:
   RequestedExtensions.push_back("nosm4");
   RequestedExtensions.push_back("nosha3");
   RequestedExtensions.push_back("nosha2");
Index: llvm/lib/Support/ARMTargetParser.cpp
===
--- llvm/lib/Support/ARMTargetParser.cpp
+++ llvm/lib/Support/ARMTargetParser.cpp
@@ -154,6 +154,7 @@
   .Case("v8.4a", "v8.4-a")
   .Case("v8.5a", "v8.5-a")
   .Case("v8.6a", "v8.6-a")
+  .Case("v8.7a", "v8.7-a")
   .Case("v8r", "v8-r")
   .Case("v8m.base", "v8-m.base")
   .Case("v8m.main", "v8-m.main")
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -118,6 +118,8 @@
 Features.push_back("+v8.5a");
   if (AK == AArch64::ArchKind::ARMV8_6A)
 Features.push_back("+v8.6a");
+  if (AK == AArch64::ArchKind::ARMV8_7A)
+Features.push_back("+v8.7a");
   if(AK == AArch64::ArchKind::ARMV8R)
 Features.push_back("+v8r");
 
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -62,6 +62,7 @@
   AEK_I8MM =1 << 30,
   AEK_F32MM =   1ULL << 31,
   AEK_F64MM =   1ULL << 32,
+  AEK_LS64 =1ULL << 33,
 };
 
 enum class ArchKind {
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -51,6 +51,13 @@
   AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
   AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
   AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM))
+AARCH64_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a",
+ ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
+ (AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
+  AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
 // For v8-R, we do not enable crypto and align with GCC that enables a more
 // minimal set of optional architecture extensions.
 AARCH64_ARCH("armv8-r", ARMV8R, "8-R", "v8r",
@@ -99,6 +106,7 @@
 AARCH64_ARCH_EXT_NAME("f32mm",AArch64::AEK_F32MM,   "+f32mm", "-f32mm")
 AARCH64_ARCH_EXT_NAME("f64mm",AArch64::AEK_F64MM,   "+f64mm", "-f64mm")
 AARCH64_ARCH_EXT_NAME("tme",  AArch64::AEK_TME, "+tme",   "-tme")
+AARCH64_ARCH_EXT_NAME("ls64", AA

[PATCH] D93231: [ARM] Adding v8.7-A command-line support for the ARM target

2020-12-14 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: dexonsmith, danielkiss, hiraditya, kristof.beyls.
pratlucas requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This extends the command-line support for the 'armv8.7-a' architecture
name to the ARM target.

Based on a patch written by Momchil Velikov.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93231

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMPredicates.td
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -26,9 +26,9 @@
 "armv7e-m","armv7em",  "armv8-a", "armv8","armv8a",
 "armv8l",  "armv8.1-a","armv8.1a","armv8.2-a","armv8.2a",
 "armv8.3-a",   "armv8.3a", "armv8.4-a",   "armv8.4a", "armv8.5-a",
-"armv8.5a", "armv8.6-a",   "armv8.6a", "armv8-r", "armv8r",
-"armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt",
-"iwmmxt2",  "xscale",  "armv8.1-m.main",
+"armv8.5a","armv8.6-a","armv8.6a","armv8.7-a","armv8.7a",
+"armv8-r", "armv8r",   "armv8-m.base","armv8m.base",  "armv8-m.main",
+"armv8m.main", "iwmmxt",   "iwmmxt2", "xscale",   "armv8.1-m.main",
 };
 
 bool testARMCPU(StringRef CPUName, StringRef ExpectedArch,
@@ -443,6 +443,9 @@
   EXPECT_TRUE(
   testARMArch("armv8.6-a", "generic", "v8.6a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(
+  testARMArch("armv8.7-a", "generic", "v8.7a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv8-r", "cortex-r52", "v8r",
   ARMBuildAttrs::CPUArch::v8_R));
@@ -710,7 +713,8 @@
   "v7",   "v7a","v7ve",  "v7hl",   "v7l",   "v7-r",   "v7r",   "v7-m",
   "v7m",  "v7k","v7s",   "v7e-m",  "v7em",  "v8-a",   "v8","v8a",
   "v8l",  "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.4-a",
-  "v8.4a", "v8.5-a","v8.5a", "v8.6-a", "v8.6a", "v8-r",   "v8m.base", "v8m.main", "v8.1m.main"
+  "v8.4a", "v8.5-a","v8.5a", "v8.6-a", "v8.6a", "v8.7-a", "v8.7a", "v8-r",
+  "v8m.base", "v8m.main", "v8.1m.main"
   };
 
   for (unsigned i = 0; i < array_lengthof(Arch); i++) {
@@ -776,6 +780,7 @@
 case ARM::ArchKind::ARMV8_4A:
 case ARM::ArchKind::ARMV8_5A:
 case ARM::ArchKind::ARMV8_6A:
+case ARM::ArchKind::ARMV8_7A:
   EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
   break;
 default:
Index: llvm/lib/Target/ARM/ARMPredicates.td
===
--- llvm/lib/Target/ARM/ARMPredicates.td
+++ llvm/lib/Target/ARM/ARMPredicates.td
@@ -77,6 +77,8 @@
  AssemblerPredicate<(all_of HasV8_5aOps), "armv8.5a">;
 def HasV8_6a : Predicate<"Subtarget->hasV8_6aOps()">,
  AssemblerPredicate<(all_of HasV8_6aOps), "armv8.6a">;
+def HasV8_7a : Predicate<"Subtarget->hasV8_7aOps()">,
+ AssemblerPredicate<(all_of HasV8_7aOps), "armv8.7a">;
 def NoVFP: Predicate<"!Subtarget->hasVFP2Base()">;
 def HasVFP2  : Predicate<"Subtarget->hasVFP2Base()">,
  AssemblerPredicate<(all_of FeatureVFP2_SP), "VFP2">;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -535,6 +535,10 @@
[HasV8_5aOps, FeatureBF16,
 FeatureMatMulInt8]>;
 
+def HasV8_7aOps   : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true",
+   "Support ARM v8.7a instructions",
+   [HasV8_6aOps]>;
+
 def HasV8_1MMainlineOps : SubtargetFeature<
"v8.1m.main", "HasV8_1MMainlineOps", "true",
"Support ARM v8-1M Mainline instructions",
@@ -831,6 +835,19 @@
FeatureCRC,
FeatureRAS,
FeatureDotProd]>;
+def ARMv87a   : Architecture<"armv8.7-a", "ARMv86a",  [HasV8_7aOps,
+   FeatureAClass,
+   FeatureDB,
+

[PATCH] D93232: [AArch64] Adding ACLE intrinsics for the LS64 extension

2020-12-14 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: danielkiss, jfb, hiraditya, kristof.beyls.
pratlucas requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This introduces the ARMv8.7-A LS64 extension's intrinsics for 64 bytes
atomic loads and stores: `__arm_ld64b`, `__arm_st64b`, `__arm_st64bv`,
and `__arm_st64bv0`. These are selected into the LS64 instructions
LD64B, ST64B, ST64BV and ST64BV0, respectively.

Based on patches written by Simon Tatham.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93232

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/ls64-intrinsics.ll

Index: llvm/test/CodeGen/AArch64/ls64-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/ls64-intrinsics.ll
@@ -0,0 +1,92 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64_be -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s
+
+define void @test_ld64b({ i64, i64, i64, i64, i64, i64, i64, i64 }* %out, i8* %addr) {
+; CHECK-LABEL: test_ld64b:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:ld64b x2, [x1]
+; CHECK-NEXT:stp x8, x9, [x0, #48]
+; CHECK-NEXT:stp x6, x7, [x0, #32]
+; CHECK-NEXT:stp x4, x5, [x0, #16]
+; CHECK-NEXT:stp x2, x3, [x0]
+; CHECK-NEXT:ret
+entry:
+  %val = tail call { i64, i64, i64, i64, i64, i64, i64, i64 } @llvm.aarch64.ld64b(i8* %addr)
+  store { i64, i64, i64, i64, i64, i64, i64, i64 } %val, { i64, i64, i64, i64, i64, i64, i64, i64 }* %out, align 8
+  ret void
+}
+
+define void @test_st64b({ i64, i64, i64, i64, i64, i64, i64, i64 }* %in, i8* %addr) {
+; CHECK-LABEL: test_st64b:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:ldp x8, x9, [x0, #48]
+; CHECK-NEXT:ldp x6, x7, [x0, #32]
+; CHECK-NEXT:ldp x4, x5, [x0, #16]
+; CHECK-NEXT:ldp x2, x3, [x0]
+; CHECK-NEXT:st64b x2, [x1]
+; CHECK-NEXT:ret
+entry:
+  %val = load { i64, i64, i64, i64, i64, i64, i64, i64 }, { i64, i64, i64, i64, i64, i64, i64, i64 }* %in, align 8
+  %v0 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 0
+  %v1 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 1
+  %v2 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 2
+  %v3 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 3
+  %v4 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 4
+  %v5 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 5
+  %v6 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 6
+  %v7 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 7
+  tail call void @llvm.aarch64.st64b(i8* %addr, i64 %v0, i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7)
+  ret void
+}
+
+define i64 @test_st64bv({ i64, i64, i64, i64, i64, i64, i64, i64 }* %in, i8* %addr) {
+; CHECK-LABEL: test_st64bv:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:ldp x8, x9, [x0, #48]
+; CHECK-NEXT:ldp x6, x7, [x0, #32]
+; CHECK-NEXT:ldp x4, x5, [x0, #16]
+; CHECK-NEXT:ldp x2, x3, [x0]
+; CHECK-NEXT:st64bv x0, x2, [x1]
+; CHECK-NEXT:ret
+entry:
+  %val = load { i64, i64, i64, i64, i64, i64, i64, i64 }, { i64, i64, i64, i64, i64, i64, i64, i64 }* %in, align 8
+  %v0 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 0
+  %v1 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 1
+  %v2 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 2
+  %v3 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 3
+  %v4 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 4
+  %v5 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 5
+  %v6 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 6
+  %v7 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 7
+  %status = tail call i64 @llvm.aarch64.st64bv(i8* %addr, i64 %v0, i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7)
+  ret i64 %status
+}
+
+define i64 @test_st64bv0({ i64, i64, i64, i64, i64, i64, i64, i64 }* %in, i8* %addr) {
+; CHECK-LABEL: test_st64bv0:
+; CHECK:   // %bb.0: // %entry
+; CHECK-NEXT:ldp x8, x9, [x0, #48]
+; CHECK-NEXT:ldp x6, x7, [x0, #32]
+; CHECK-NEXT:ldp x4, x5, [x0, #16]
+; CHECK-NEXT:ldp x2, x3, [x0]
+; CHECK-NEXT:st64bv0 x0, x2, [x1]
+; CHECK-NEXT:ret
+entry:
+  %val = load { i64, i64, i64, i64, i64, i64, i64, i64 }, { i64, i64, i64, i64, i64

[PATCH] D91776: [ARM][AAarch64] Initial command-line support for v8.7-A

2020-12-17 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc4d851b07903: [ARM][AAarch64] Initial command-line support 
for v8.7-A (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91776/new/

https://reviews.llvm.org/D91776

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/aarch64-ls64.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1103,6 +1103,8 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv8.6-a", "generic", "v8.6a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv8.7-a", "generic", "v8.7a",
+  ARMBuildAttrs::CPUArch::v8_A));
 }
 
 bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -5354,6 +5354,7 @@
 case AArch64::ArchKind::ARMV8_4A:
 case AArch64::ArchKind::ARMV8_5A:
 case AArch64::ArchKind::ARMV8_6A:
+case AArch64::ArchKind::ARMV8_7A:
 case AArch64::ArchKind::ARMV8R:
   RequestedExtensions.push_back("sm4");
   RequestedExtensions.push_back("sha3");
@@ -5375,6 +5376,7 @@
 case AArch64::ArchKind::ARMV8_4A:
 case AArch64::ArchKind::ARMV8_5A:
 case AArch64::ArchKind::ARMV8_6A:
+case AArch64::ArchKind::ARMV8_7A:
   RequestedExtensions.push_back("nosm4");
   RequestedExtensions.push_back("nosha3");
   RequestedExtensions.push_back("nosha2");
Index: llvm/lib/Support/ARMTargetParser.cpp
===
--- llvm/lib/Support/ARMTargetParser.cpp
+++ llvm/lib/Support/ARMTargetParser.cpp
@@ -154,6 +154,7 @@
   .Case("v8.4a", "v8.4-a")
   .Case("v8.5a", "v8.5-a")
   .Case("v8.6a", "v8.6-a")
+  .Case("v8.7a", "v8.7-a")
   .Case("v8r", "v8-r")
   .Case("v8m.base", "v8-m.base")
   .Case("v8m.main", "v8-m.main")
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -118,6 +118,8 @@
 Features.push_back("+v8.5a");
   if (AK == AArch64::ArchKind::ARMV8_6A)
 Features.push_back("+v8.6a");
+  if (AK == AArch64::ArchKind::ARMV8_7A)
+Features.push_back("+v8.7a");
   if(AK == AArch64::ArchKind::ARMV8R)
 Features.push_back("+v8r");
 
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -62,6 +62,7 @@
   AEK_I8MM =1 << 30,
   AEK_F32MM =   1ULL << 31,
   AEK_F64MM =   1ULL << 32,
+  AEK_LS64 =1ULL << 33,
 };
 
 enum class ArchKind {
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -51,6 +51,13 @@
   AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
   AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
   AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM))
+AARCH64_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a",
+ ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
+ (AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
+  AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
 // For v8-R, we do not enable crypto and align with GCC that enables a more
 // minimal set of optional architecture extensions.
 AARCH64_ARCH("armv8-r", ARMV8R, "8-R", "v8r",
@@ -99,6 +106,7 @@
 AARCH64_ARCH_EXT_NAME("f32mm",AArch64::AEK_F32MM,   "+f32mm", "-f32mm")
 AARCH64_ARCH_EXT_NAME("f64mm",AArch64::AEK

[PATCH] D93231: [ARM] Adding v8.7-A command-line support for the ARM target

2020-12-17 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc5046ebdf6e4: [ARM] Adding v8.7-A command-line support for 
the ARM target (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93231/new/

https://reviews.llvm.org/D93231

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMPredicates.td
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -26,9 +26,9 @@
 "armv7e-m","armv7em",  "armv8-a", "armv8","armv8a",
 "armv8l",  "armv8.1-a","armv8.1a","armv8.2-a","armv8.2a",
 "armv8.3-a",   "armv8.3a", "armv8.4-a",   "armv8.4a", "armv8.5-a",
-"armv8.5a", "armv8.6-a",   "armv8.6a", "armv8-r", "armv8r",
-"armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt",
-"iwmmxt2",  "xscale",  "armv8.1-m.main",
+"armv8.5a","armv8.6-a","armv8.6a","armv8.7-a","armv8.7a",
+"armv8-r", "armv8r",   "armv8-m.base","armv8m.base",  "armv8-m.main",
+"armv8m.main", "iwmmxt",   "iwmmxt2", "xscale",   "armv8.1-m.main",
 };
 
 bool testARMCPU(StringRef CPUName, StringRef ExpectedArch,
@@ -443,6 +443,9 @@
   EXPECT_TRUE(
   testARMArch("armv8.6-a", "generic", "v8.6a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(
+  testARMArch("armv8.7-a", "generic", "v8.7a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv8-r", "cortex-r52", "v8r",
   ARMBuildAttrs::CPUArch::v8_R));
@@ -710,7 +713,8 @@
   "v7",   "v7a","v7ve",  "v7hl",   "v7l",   "v7-r",   "v7r",   "v7-m",
   "v7m",  "v7k","v7s",   "v7e-m",  "v7em",  "v8-a",   "v8","v8a",
   "v8l",  "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.4-a",
-  "v8.4a", "v8.5-a","v8.5a", "v8.6-a", "v8.6a", "v8-r",   "v8m.base", "v8m.main", "v8.1m.main"
+  "v8.4a", "v8.5-a","v8.5a", "v8.6-a", "v8.6a", "v8.7-a", "v8.7a", "v8-r",
+  "v8m.base", "v8m.main", "v8.1m.main"
   };
 
   for (unsigned i = 0; i < array_lengthof(Arch); i++) {
@@ -776,6 +780,7 @@
 case ARM::ArchKind::ARMV8_4A:
 case ARM::ArchKind::ARMV8_5A:
 case ARM::ArchKind::ARMV8_6A:
+case ARM::ArchKind::ARMV8_7A:
   EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
   break;
 default:
Index: llvm/lib/Target/ARM/ARMPredicates.td
===
--- llvm/lib/Target/ARM/ARMPredicates.td
+++ llvm/lib/Target/ARM/ARMPredicates.td
@@ -77,6 +77,8 @@
  AssemblerPredicate<(all_of HasV8_5aOps), "armv8.5a">;
 def HasV8_6a : Predicate<"Subtarget->hasV8_6aOps()">,
  AssemblerPredicate<(all_of HasV8_6aOps), "armv8.6a">;
+def HasV8_7a : Predicate<"Subtarget->hasV8_7aOps()">,
+ AssemblerPredicate<(all_of HasV8_7aOps), "armv8.7a">;
 def NoVFP: Predicate<"!Subtarget->hasVFP2Base()">;
 def HasVFP2  : Predicate<"Subtarget->hasVFP2Base()">,
  AssemblerPredicate<(all_of FeatureVFP2_SP), "VFP2">;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -535,6 +535,10 @@
[HasV8_5aOps, FeatureBF16,
 FeatureMatMulInt8]>;
 
+def HasV8_7aOps   : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true",
+   "Support ARM v8.7a instructions",
+   [HasV8_6aOps]>;
+
 def HasV8_1MMainlineOps : SubtargetFeature<
"v8.1m.main", "HasV8_1MMainlineOps", "true",
"Support ARM v8-1M Mainline instructions",
@@ -831,6 +835,19 @@
FeatureCRC,
FeatureRAS,
FeatureDotProd]>;
+def ARMv87a   : Architecture<"armv8.7-a", "ARMv86a",  [HasV8_7aOps,
+   FeatureAClass,
+   FeatureDB,
+   FeatureFPARMv8,
+

[PATCH] D90765: [ARM][AArch64] Adding Neoverse V1 CPU support

2020-11-04 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: llvm-commits, cfe-commits, danielkiss, hiraditya, 
kristof.beyls.
Herald added projects: clang, LLVM.
pratlucas requested review of this revision.

Add support for the Neoverse V1 CPU to the ARM and AArch64 backends.

This is based on patches from Mark Murray and Victor Campos.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90765

Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  llvm/include/llvm/MC/SubtargetFeature.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -274,6 +274,12 @@
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
  ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
  "8.2-A"));
+  EXPECT_TRUE(testARMCPU("neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+ ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+ ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+ ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+ ARM::AEK_DOTPROD,
+ "8.4-A"));
   EXPECT_TRUE(testARMCPU("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -322,7 +328,7 @@
  "7-S"));
 }
 
-static constexpr unsigned NumARMCPUArchs = 89;
+static constexpr unsigned NumARMCPUArchs = 90;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -881,6 +887,14 @@
   AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
   AArch64::AEK_RCPC | AArch64::AEK_SSBS,
   "8.2-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
+  AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_CRYPTO,
+  "8.4-A"));
   EXPECT_TRUE(testAArch64CPU(
  "cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_RDM  | AArch64::AEK_SSBS|
@@ -1034,7 +1048,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 43;
+static constexpr unsigned NumAArch64CPUArchs = 44;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -20,6 +20,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-x1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-v1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m4 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m5 2>&1 | FileCheck %s
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -76,7 +76,8 @@
 Krait,
 Kryo,
 NeoverseN1,
-Swift
+Swift,
+NeoverseV1,
   };
   enum ARMProcClassEnum {
 None,
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -321,6 +321,8 @@
 PreISelOperandLatencyAdjustment = 1;
 PartialUpdateClearance = 12;
 break;
+  case NeoverseV1:
+break;
   }
 }
 
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -601,6 +601,9 @@
 def ProcX1  : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
 
+def ProcNeoverseV1 : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
+

[PATCH] D90765: [ARM][AArch64] Adding Neoverse V1 CPU support

2020-11-05 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 303091.
pratlucas added a comment.

Addressing comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90765/new/

https://reviews.llvm.org/D90765

Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  llvm/include/llvm/MC/SubtargetFeature.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -274,6 +274,12 @@
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
  ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
  "8.2-A"));
+  EXPECT_TRUE(testARMCPU("neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+ ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+ ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+ ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+ ARM::AEK_DOTPROD,
+ "8.4-A"));
   EXPECT_TRUE(testARMCPU("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -322,7 +328,7 @@
  "7-S"));
 }
 
-static constexpr unsigned NumARMCPUArchs = 89;
+static constexpr unsigned NumARMCPUArchs = 90;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -881,6 +887,14 @@
   AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
   AArch64::AEK_RCPC | AArch64::AEK_SSBS,
   "8.2-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
+  AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_CRYPTO,
+  "8.4-A"));
   EXPECT_TRUE(testAArch64CPU(
  "cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_RDM  | AArch64::AEK_SSBS|
@@ -1034,7 +1048,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 43;
+static constexpr unsigned NumAArch64CPUArchs = 44;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -20,6 +20,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-x1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-v1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m4 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m5 2>&1 | FileCheck %s
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -76,6 +76,7 @@
 Krait,
 Kryo,
 NeoverseN1,
+NeoverseV1,
 Swift
   };
   enum ARMProcClassEnum {
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -314,6 +314,7 @@
 PreISelOperandLatencyAdjustment = 1;
 break;
   case NeoverseN1:
+  case NeoverseV1:
 break;
   case Swift:
 MaxInterleaveFactor = 2;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -601,6 +601,9 @@
 def ProcX1  : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
 
+def ProcV1  : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
+   "NeoverseV1", "Neoverse-V1 ARM processors", []>;
+
 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
"Qualcomm Kr

[PATCH] D90765: [ARM][AArch64] Adding Neoverse V1 CPU support

2020-11-06 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 303486.
pratlucas added a comment.

Updating default extensions in target parser to match tablegen features.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90765/new/

https://reviews.llvm.org/D90765

Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  llvm/include/llvm/MC/SubtargetFeature.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -8,7 +8,9 @@
 
 #include "llvm/Support/TargetParser.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/AArch64TargetParser.h"
 #include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/ARMTargetParser.h"
 #include "gtest/gtest.h"
 #include 
 
@@ -280,6 +282,12 @@
 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
 ARM::AEK_RAS | ARM::AEK_DOTPROD,
 "8.2-A"));
+  EXPECT_TRUE(testARMCPU("neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+ ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+ ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+ ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+ ARM::AEK_FP16 | ARM::AEK_BF16 | ARM::AEK_DOTPROD,
+ "8.4-A"));
   EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",
  ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
  ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -322,7 +330,7 @@
  "7-S"));
 }
 
-static constexpr unsigned NumARMCPUArchs = 89;
+static constexpr unsigned NumARMCPUArchs = 90;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -881,6 +889,14 @@
   AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
   AArch64::AEK_RCPC | AArch64::AEK_SSBS,
   "8.2-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
+  AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_CRYPTO | AArch64::AEK_FP16 | AArch64::AEK_BF16,
+  "8.4-A"));
   EXPECT_TRUE(testAArch64CPU(
  "cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_RDM  | AArch64::AEK_SSBS|
@@ -1034,7 +1050,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 43;
+static constexpr unsigned NumAArch64CPUArchs = 44;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -20,6 +20,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-x1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-v1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m4 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m5 2>&1 | FileCheck %s
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -76,6 +76,7 @@
 Krait,
 Kryo,
 NeoverseN1,
+NeoverseV1,
 Swift
   };
   enum ARMProcClassEnum {
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -314,6 +314,7 @@
 PreISelOperandLatencyAdjustment = 1;
 break;
   case NeoverseN1:
+  case NeoverseV1:
 break;
   case Swift:
 MaxInterleaveFactor = 2;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -601,6 +601,9 @@
 def ProcX1  : SubtargetFeature<

[PATCH] D90765: [ARM][AArch64] Adding Neoverse V1 CPU support

2020-11-09 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 303803.
pratlucas added a comment.

Removing extra includes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90765/new/

https://reviews.llvm.org/D90765

Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  llvm/include/llvm/MC/SubtargetFeature.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -280,6 +280,12 @@
 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
 ARM::AEK_RAS | ARM::AEK_DOTPROD,
 "8.2-A"));
+  EXPECT_TRUE(testARMCPU("neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+ ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+ ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+ ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+ ARM::AEK_FP16 | ARM::AEK_BF16 | ARM::AEK_DOTPROD,
+ "8.4-A"));
   EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",
  ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
  ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -322,7 +328,7 @@
  "7-S"));
 }
 
-static constexpr unsigned NumARMCPUArchs = 89;
+static constexpr unsigned NumARMCPUArchs = 90;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -881,6 +887,14 @@
   AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
   AArch64::AEK_RCPC | AArch64::AEK_SSBS,
   "8.2-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
+  AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_CRYPTO | AArch64::AEK_FP16 | AArch64::AEK_BF16,
+  "8.4-A"));
   EXPECT_TRUE(testAArch64CPU(
  "cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_RDM  | AArch64::AEK_SSBS|
@@ -1034,7 +1048,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 43;
+static constexpr unsigned NumAArch64CPUArchs = 44;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -20,6 +20,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-x1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-v1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m4 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m5 2>&1 | FileCheck %s
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -76,6 +76,7 @@
 Krait,
 Kryo,
 NeoverseN1,
+NeoverseV1,
 Swift
   };
   enum ARMProcClassEnum {
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -314,6 +314,7 @@
 PreISelOperandLatencyAdjustment = 1;
 break;
   case NeoverseN1:
+  case NeoverseV1:
 break;
   case Swift:
 MaxInterleaveFactor = 2;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -601,6 +601,9 @@
 def ProcX1  : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
 
+def ProcV1  : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
+   "NeoverseV1", "Neoverse-V1 ARM processors", []>;
+
 def ProcKrait   : SubtargetFeature<"krait", "

[PATCH] D90765: [ARM][AArch64] Adding Neoverse V1 CPU support

2020-11-09 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc2c2cc136013: [ARM][AArch64] Adding Neoverse V1 CPU support 
(authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90765/new/

https://reviews.llvm.org/D90765

Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  llvm/include/llvm/MC/SubtargetFeature.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -280,6 +280,12 @@
 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
 ARM::AEK_RAS | ARM::AEK_DOTPROD,
 "8.2-A"));
+  EXPECT_TRUE(testARMCPU("neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+ ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+ ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+ ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+ ARM::AEK_FP16 | ARM::AEK_BF16 | ARM::AEK_DOTPROD,
+ "8.4-A"));
   EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",
  ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
  ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -322,7 +328,7 @@
  "7-S"));
 }
 
-static constexpr unsigned NumARMCPUArchs = 89;
+static constexpr unsigned NumARMCPUArchs = 90;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -881,6 +887,14 @@
   AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
   AArch64::AEK_RCPC | AArch64::AEK_SSBS,
   "8.2-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
+  AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_CRYPTO | AArch64::AEK_FP16 | AArch64::AEK_BF16,
+  "8.4-A"));
   EXPECT_TRUE(testAArch64CPU(
  "cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_RDM  | AArch64::AEK_SSBS|
@@ -1034,7 +1048,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 43;
+static constexpr unsigned NumAArch64CPUArchs = 44;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -20,6 +20,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-x1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-v1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m4 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m5 2>&1 | FileCheck %s
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -76,6 +76,7 @@
 Krait,
 Kryo,
 NeoverseN1,
+NeoverseV1,
 Swift
   };
   enum ARMProcClassEnum {
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -314,6 +314,7 @@
 PreISelOperandLatencyAdjustment = 1;
 break;
   case NeoverseN1:
+  case NeoverseV1:
 break;
   case Swift:
 MaxInterleaveFactor = 2;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -601,6 +601,9 @@
 def ProcX1  : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
 
+def ProcV1  : SubtargetFeature<"neoverse-v1", "ARMProcFamily",

[PATCH] D91776: [ARM][AAarch64] Initial command-line support for v8.7-A

2020-11-19 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: llvm-commits, cfe-commits, danielkiss, hiraditya, 
kristof.beyls.
Herald added projects: clang, LLVM.
pratlucas requested review of this revision.

This introduces command-line support for the 'armv8.7-a' architecture name
(and an alias without the '-', as usual), and for the 'ls64' extension name.

Based on patches written by Simon Tatham.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91776

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/aarch64-ls64.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -5384,6 +5384,7 @@
 case AArch64::ArchKind::ARMV8_4A:
 case AArch64::ArchKind::ARMV8_5A:
 case AArch64::ArchKind::ARMV8_6A:
+case AArch64::ArchKind::ARMV8_7A:
 case AArch64::ArchKind::ARMV8R:
   RequestedExtensions.push_back("sm4");
   RequestedExtensions.push_back("sha3");
@@ -5405,6 +5406,7 @@
 case AArch64::ArchKind::ARMV8_4A:
 case AArch64::ArchKind::ARMV8_5A:
 case AArch64::ArchKind::ARMV8_6A:
+case AArch64::ArchKind::ARMV8_7A:
   RequestedExtensions.push_back("nosm4");
   RequestedExtensions.push_back("nosha3");
   RequestedExtensions.push_back("nosha2");
Index: llvm/lib/Support/ARMTargetParser.cpp
===
--- llvm/lib/Support/ARMTargetParser.cpp
+++ llvm/lib/Support/ARMTargetParser.cpp
@@ -154,6 +154,7 @@
   .Case("v8.4a", "v8.4-a")
   .Case("v8.5a", "v8.5-a")
   .Case("v8.6a", "v8.6-a")
+  .Case("v8.7a", "v8.7-a")
   .Case("v8r", "v8-r")
   .Case("v8m.base", "v8-m.base")
   .Case("v8m.main", "v8-m.main")
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -118,6 +118,8 @@
 Features.push_back("+v8.5a");
   if (AK == AArch64::ArchKind::ARMV8_6A)
 Features.push_back("+v8.6a");
+  if (AK == AArch64::ArchKind::ARMV8_7A)
+Features.push_back("+v8.7a");
   if(AK == AArch64::ArchKind::ARMV8R)
 Features.push_back("+v8r");
 
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -62,6 +62,7 @@
   AEK_I8MM =1 << 30,
   AEK_F32MM =   1ULL << 31,
   AEK_F64MM =   1ULL << 32,
+  AEK_LS64 =1ULL << 33,
 };
 
 enum class ArchKind {
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -51,6 +51,13 @@
   AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
   AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
   AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM))
+AARCH64_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a",
+ ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
+ (AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
+  AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
 AARCH64_ARCH("armv8-r", ARMV8R, "8-R", "v8r",
  ARMBuildAttrs::CPUArch::v8_R, FK_CRYPTO_NEON_FP_ARMV8,
  (AArch64::AEK_CRC | AArch64::AEK_RDM  | AArch64::AEK_SSBS|
@@ -99,6 +106,7 @@
 AARCH64_ARCH_EXT_NAME("f32mm",AArch64::AEK_F32MM,   "+f32mm", "-f32mm")
 AARCH64_ARCH_EXT_NAME("f64mm",AArch64::AEK_F64MM,   "+f64mm", "-f64mm")
 AARCH64_ARCH_EXT_NAME("tme",  AArch64::AEK_TME, "+tme",   "-tme")
+AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64,"+ls64",  "-ls64")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME
Index: clang/test/Driver/aarch64-ls64.c
===
--- /dev/null
+++ clang/test/Driver/aarch64-ls64.c
@@ -0,0 +1,12 @@
+// Test that target feature ls64 is implemented and available correctly
+// RUN: %clang -### -target aarch64-none-none-eabi -

[PATCH] D93101: [Clang][Codegen] Truncate initializers of union bitfield members

2021-01-27 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas accepted this revision.
pratlucas added a comment.
This revision is now accepted and ready to land.

The truncate conditions look a lot better and the test coverage seems 
reasonable now.
LGTM.


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[PATCH] D110241: [docs] List support for Armv9-A, Armv9.1-A and Armv9.2-A in LLVM and Clang

2021-09-22 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas accepted this revision.
pratlucas added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D110065: [AArch64] Add support for the 'R' architecture profile.

2021-09-23 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added inline comments.



Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3299
 static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
   if (FBS[AArch64::HasV8_1aOps])
 Str += "ARMv8.1a";

As features can now depend on `HasV8_0aOps`, does it make sense to cover it 
here?



Comment at: 
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp:1567-1571
+Reg = AArch64SysReg::lookupSysRegByName("TTBR0_EL2");
+if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) {
+  O << Reg->Name;
+  return;
+}

Nit: Maybe extract this block to a function as it's used a few times.


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[PATCH] D135680: [clang][ARM] follow GCC behavior for defining SOFTFP

2022-10-18 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas accepted this revision.
pratlucas added a comment.
This revision is now accepted and ready to land.

Thanks! LGTM.


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[PATCH] D135680: [clang][ARM] follow GCC behavior for defining SOFTFP

2022-10-13 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added inline comments.



Comment at: clang/test/Preprocessor/init-arm.c:404
+//   is specified
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi 
-target-feature +soft-float -target-feature +soft-float-abi < /dev/null | 
FileCheck -match-full-lines -check-prefix ARMEABISOFTFP_NOFP %s
 //

I believe this RUN line won't covered the new condition added to 
`clang/lib/Basic/Targets/ARM.cpp` above, as it sets `+soft-float`.
Can you add an extra test without that option enabled?


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[PATCH] D140999: [NFC][TargetParser] Deprecate llvm/Support/AArch64TargetParser.h

2023-01-05 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas accepted this revision.
pratlucas added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D141403: [AArch64] Add command line support for v9.4-A's Instrumentation Extension

2023-01-10 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added a subscriber: kristof.beyls.
Herald added a project: All.
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Herald added subscribers: llvm-commits, cfe-commits.

This introduces command line support (`+ite`) for the v9.4-A's
Instrumentation Extension (FEAT_ITE).

Patch by Son Tuan Vu.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141403

Files:
  clang/test/Driver/aarch64-ite.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.def
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/unittests/TargetParser/TargetParserTest.cpp


Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1610,6 +1610,7 @@
   AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
   AArch64::AEK_RCPC3,   AArch64::AEK_THE,   AArch64::AEK_D128,
   AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
+  AArch64::AEK_ITE,
   };
 
   std::vector Features;
@@ -1681,6 +1682,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -146,6 +146,7 @@
   AEK_LSE128 =  1ULL << 52, // FEAT_LSE128
   AEK_SPECRES2 =1ULL << 53, // FEAT_SPECRES2
   AEK_RASv2 =   1ULL << 54, // FEAT_RASv2
+  AEK_ITE = 1ULL << 55, // FEAT_ITE
 };
 // clang-format on
 
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.def
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.def
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.def
@@ -217,6 +217,7 @@
 AARCH64_ARCH_EXT_NAME("d128", AArch64::AEK_D128, "+d128", "-d128", MAX, "", 0)
 AARCH64_ARCH_EXT_NAME("lse128", AArch64::AEK_LSE128, "+lse128", "-lse128", MAX,
   "", 0)
+AARCH64_ARCH_EXT_NAME("ite", AArch64::AEK_ITE, "+ite", "-ite", MAX, "", 0)
 AARCH64_ARCH_EXT_NAME("sha1", AArch64::AEK_NONE, {}, {}, SHA1,
   "+fp-armv8,+neon", 120)
 AARCH64_ARCH_EXT_NAME("pmull", AArch64::AEK_NONE, {}, {}, PMULL,
Index: clang/test/Driver/aarch64-ite.c
===
--- /dev/null
+++ clang/test/Driver/aarch64-ite.c
@@ -0,0 +1,17 @@
+// Test that target feature ite is implemented and available correctly
+
+// FEAT_ITE is optional (off by default) for v8.9a/9.4a and older, and can be 
enabled using +ite
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a   %s 
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+ite   %s 
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+noite %s 
2>&1 | FileCheck %s --check-prefix=DISABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a   %s 
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+ite   %s 
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+noite %s 
2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// FEAT_ITE is invalid before v8
+// RUN: %clang -### -target arm-none-none-eabi -march=armv7-a+ite %s 2>&1 
| FileCheck %s --check-prefix=INVALID
+
+// INVALID: error: unsupported argument 'armv7-a+ite' to option '-march='
+// ENABLED: "-target-feature" "+ite"
+// NOT_ENABLED-NOT: "-target-feature" "+ite"
+// DISABLED: "-target-feature" "-ite"


Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1610,6 +1610,7 @@
   AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
   AArch64::AEK_RCPC3,   AArch64::AEK_THE,   AArch64::AEK_D128,
   AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
+  AArch64::AEK_ITE,
   };
 
   std::vector Features;
@@ -1681,6 +1682,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
 
   // Assuming

[PATCH] D141404: [AArch64][Clang] Adjust default features for v8.9-A/v9.4-A in clang driver

2023-01-10 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added a subscriber: kristof.beyls.
Herald added a project: All.
pratlucas requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Update the clang driver to include the following features as default for
the v8.9-A/v9.4-A architecture versions:

- FEAT_SPECRES2
- FEAT_CSSC
- FEAT_RASv2

Patch by Sam Elliott.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141404

Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cssc.c


Index: clang/test/Driver/aarch64-cssc.c
===
--- clang/test/Driver/aarch64-cssc.c
+++ clang/test/Driver/aarch64-cssc.c
@@ -1,12 +1,13 @@
 // Test that target feature cssc is implemented and available correctly
+// FEAT_CSSC is a required part of v8.9a/v9.4a and optional from v8.7a/v9.3a 
onwards.
 // RUN: %clang -### -target aarch64-none-none-eabi %s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a%s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.7-a+cssc   %s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a%s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+cssc   %s 
2>&1 | FileCheck %s
 // RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nocssc %s 
2>&1 | FileCheck %s --check-prefix=NO_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a%s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.2-a+cssc   %s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a%s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+cssc   %s 
2>&1 | FileCheck %s
 // RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nocssc %s 
2>&1 | FileCheck %s --check-prefix=NO_CSSC
 
 // CHECK: "-target-feature" "+cssc"
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -498,6 +498,11 @@
 Features.insert(std::next(Features.begin() + ArchFeatPos),
 {"+hbc", "+mops"});
 
+  // Default features for Armv8.9-a/Armv9.4-a or later.
+  if (V8Version >= 9 || V9Version >= 4)
+Features.insert(std::next(Features.begin() + ArchFeatPos),
+{"+specres2", "+cssc", "+rasv2"});
+
   if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
options::OPT_munaligned_access)) {
 if (A->getOption().matches(options::OPT_mno_unaligned_access))


Index: clang/test/Driver/aarch64-cssc.c
===
--- clang/test/Driver/aarch64-cssc.c
+++ clang/test/Driver/aarch64-cssc.c
@@ -1,12 +1,13 @@
 // Test that target feature cssc is implemented and available correctly
+// FEAT_CSSC is a required part of v8.9a/v9.4a and optional from v8.7a/v9.3a onwards.
 // RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a%s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.7-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a%s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+cssc   %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a%s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.2-a+cssc

[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

2022-11-15 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added inline comments.



Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:70-76
+AARCH64_ARCH("armv8.9-a", ARMV8_9A, "8.9-A", "v8.9a",
+ ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
+ (AArch64::AEK_CRC | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
+  AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))

The new entries need to be updated, as D137924 has recently landed removing a 
couple of unused fields from `AARCH64_ARCH`.


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[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

2022-11-15 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added inline comments.



Comment at: llvm/include/llvm/Support/ARMTargetParser.def:127
+  ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+  ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
 ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a",

stuij wrote:
> tmatheson wrote:
> > No ARM::AEK_SHA2 | ARM::AEK_AES? Or does 8.8 need updated?
> Yes, I think 8.8 needs update, and some other arches as well.
> 
> In the A profile armarm, section A2.3, it is stated that from 8.2 SME(2) and 
> EAS aren't by default included in the cryptographic extension as the 
> Cryptographic Extension in an implementation is subject to export license 
> controls. Inclusion of the extension can be either/or or none, so we should 
> default to none.
> 
> I think this should be handled by  separate patch.
The v8.9-a entry on AArch64TargetParser.def includes both `AEK_SHA2` and 
`AEK_AES`. Can you also update it to make sure they are consistent?


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[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

2022-11-15 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added inline comments.



Comment at: llvm/unittests/Support/TargetParserTest.cpp:532
+  testARMArch("armv9.4-a", "generic", "v9.4a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(

Should this be testing for `ARMBuildAttrs::CPUArch::v9_A` instead?


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[PATCH] D142539: [NFC][AArch64] Use optional returns in target parser instead of 'invalid' objects

2023-01-25 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
pratlucas requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

This updates the parsing methods in AArch64's Target Parser to make use
of optional returns instead of "invalid" enum values, making the API's
behaviour clearer.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142539

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/TargetParser/AArch64TargetParser.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -17,6 +17,7 @@
 #include "llvm/TargetParser/Triple.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
+#include 
 #include 
 
 using namespace llvm;
@@ -961,11 +962,12 @@
 TEST_P(AArch64CPUTestFixture, testAArch64CPU) {
   ARMCPUTestParams params = GetParam();
 
-  const AArch64::ArchInfo &AI = AArch64::parseCpu(params.CPUName).Arch;
-  EXPECT_EQ(params.ExpectedArch, AI.Name);
+  const std::optional Cpu = AArch64::parseCpu(params.CPUName);
+  EXPECT_TRUE(Cpu);
+  EXPECT_EQ(params.ExpectedArch, Cpu->Arch.Name);
 
   uint64_t default_extensions =
-  AArch64::getDefaultExtensions(params.CPUName, AI);
+  AArch64::getDefaultExtensions(params.CPUName, Cpu->Arch);
   EXPECT_PRED_FORMAT2(
   AssertSameExtensionFlags(params.CPUName),
   params.ExpectedFlags, default_extensions);
@@ -974,10 +976,6 @@
 INSTANTIATE_TEST_SUITE_P(
 AArch64CPUTests, AArch64CPUTestFixture,
 ::testing::Values(
-ARMCPUTestParams("invalid", "invalid", "invalid", AArch64::AEK_NONE,
- ""),
-ARMCPUTestParams("generic", "invalid", "none", AArch64::AEK_NONE, ""),
-
 ARMCPUTestParams("cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1410,14 +1408,14 @@
   // valid, and match the expected 'magic' count.
   EXPECT_EQ(List.size(), NumAArch64CPUArchs);
   for(StringRef CPU : List) {
-EXPECT_NE(AArch64::parseCpu(CPU).Arch, AArch64::INVALID);
+EXPECT_TRUE(AArch64::parseCpu(CPU));
   }
 }
 
 bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
  unsigned ArchAttr) {
-  const AArch64::ArchInfo &AI = AArch64::parseArch(Arch);
-  return AI != AArch64::INVALID;
+  const std::optional AI = AArch64::parseArch(Arch);
+  return AI.has_value();
 }
 
 TEST(TargetParserTest, testAArch64Arch) {
@@ -1453,81 +1451,92 @@
   ARMBuildAttrs::CPUArch::v8_A));
 }
 
-bool testAArch64Extension(StringRef CPUName, const AArch64::ArchInfo &AI,
-  StringRef ArchExt) {
-  return AArch64::getDefaultExtensions(CPUName, AI) &
- AArch64::parseArchExt(ArchExt);
+bool testAArch64Extension(StringRef CPUName, StringRef ArchExt) {
+  std::optional Extension =
+  AArch64::parseArchExtension(ArchExt);
+  if (!Extension)
+return false;
+  std::optional CpuInfo = AArch64::parseCpu(CPUName);
+  return (CpuInfo->Arch.DefaultExts | CpuInfo->DefaultExtensions) & Extension->ID;
+}
+
+bool testAArch64Extension(const AArch64::ArchInfo &AI, StringRef ArchExt) {
+  std::optional Extension =
+  AArch64::parseArchExtension(ArchExt);
+  if (!Extension)
+return false;
+  return AI.DefaultExts & Extension->ID;
 }
 
 TEST(TargetParserTest, testAArch64Extension) {
-  EXPECT_FALSE(testAArch64Extension("cortex-a34", AArch64::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a35", AArch64::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a53", AArch64::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55", AArch64::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55", AArch64::INVALID, "fp16"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a55", AArch64::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55", AArch64::INVALID, "dotprod"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a57", AArch64::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a72", AArch64::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a73", AArch64::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75", AArch64::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75", AArch64::INVALID, "fp16"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a75", AArch64::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75", AArch64::INVALID, "dotprod"));
-  EXPECT_TRUE(

[PATCH] D142540: [NFC][AArch64] Get default features directly from ArchInfo and CpuInfo objects

2023-01-25 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
pratlucas requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

This updates the AArch64's Target Parser and its uses to capture
information about default features directly from ArchInfo and CpuInfo
objects, instead of relying on an API function to access them
indirectly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142540

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/TargetParser/AArch64TargetParser.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -966,11 +966,9 @@
   EXPECT_TRUE(Cpu);
   EXPECT_EQ(params.ExpectedArch, Cpu->Arch.Name);
 
-  uint64_t default_extensions =
-  AArch64::getDefaultExtensions(params.CPUName, Cpu->Arch);
   EXPECT_PRED_FORMAT2(
   AssertSameExtensionFlags(params.CPUName),
-  params.ExpectedFlags, default_extensions);
+  params.ExpectedFlags, Cpu->getDefaultExtensions());
 }
 
 INSTANTIATE_TEST_SUITE_P(
@@ -1457,7 +1455,7 @@
   if (!Extension)
 return false;
   std::optional CpuInfo = AArch64::parseCpu(CPUName);
-  return (CpuInfo->Arch.DefaultExts | CpuInfo->DefaultExtensions) & Extension->ID;
+  return CpuInfo->getDefaultExtensions() & Extension->ID;
 }
 
 bool testAArch64Extension(const AArch64::ArchInfo &AI, StringRef ArchExt) {
Index: llvm/lib/TargetParser/AArch64TargetParser.cpp
===
--- llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -25,19 +25,6 @@
   return 0;
 }
 
-uint64_t AArch64::getDefaultExtensions(StringRef CPU,
-   const AArch64::ArchInfo &AI) {
-  if (CPU == "generic")
-return AI.DefaultExts;
-
-  // Note: this now takes cpu aliases into account
-  std::optional Cpu = parseCpu(CPU);
-  if (!Cpu)
-return AI.DefaultExts;
-
-  return Cpu->Arch.DefaultExts | Cpu->DefaultExtensions;
-}
-
 void AArch64::getFeatureOption(StringRef Name, std::string &Feature) {
   for (const auto &E : llvm::AArch64::Extensions) {
 if (Name == E.Name) {
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6891,8 +6891,7 @@
   // Get the architecture and extension features.
   std::vector AArch64Features;
   AArch64Features.push_back(ArchInfo->ArchFeature);
-  AArch64::getExtensionFeatures(
-  AArch64::getDefaultExtensions("generic", *ArchInfo), AArch64Features);
+  AArch64::getExtensionFeatures(ArchInfo->DefaultExts, AArch64Features);
 
   MCSubtargetInfo &STI = copySTI();
   std::vector ArchFeatures(AArch64Features.begin(), AArch64Features.end());
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -334,6 +334,10 @@
   const ArchInfo &Arch;
   uint64_t DefaultExtensions; // Default extensions for this CPU. These will be
   // ORd with the architecture defaults.
+
+  uint64_t getDefaultExtensions() const {
+return DefaultExtensions | Arch.DefaultExts;
+  }
 };
 
 inline constexpr CpuInfo CpuInfos[] = {
@@ -501,7 +505,6 @@
 StringRef resolveCPUAlias(StringRef CPU);
 
 // Information by Name
-uint64_t getDefaultExtensions(StringRef CPU, const ArchInfo &AI);
 void getFeatureOption(StringRef Name, std::string &Feature);
 std::optional getArchForCpu(StringRef CPU);
 
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -140,7 +140,7 @@
 
 Features.push_back(ArchInfo->ArchFeature);
 
-uint64_t Extension = llvm::AArch64::getDefaultExtensions(CPU, *ArchInfo);
+uint64_t Extension = CpuInfo->getDefaultExtensions();
 if (!llvm::AArch64::getExtensionFeatures(Extension, Features))
   return false;
   }
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -692,10 +692,8 @@
   Features[OtherArch->getSubArch()] = Enabled;
 
   // Set any features implied by the arch

[PATCH] D142541: [NFC][AArch64] Get extension strings directly from ArchInfo in target parser

2023-01-25 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
pratlucas requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142541

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/TargetParser/AArch64TargetParser.cpp


Index: llvm/lib/TargetParser/AArch64TargetParser.cpp
===
--- llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -25,16 +25,6 @@
   return 0;
 }
 
-void AArch64::getFeatureOption(StringRef Name, std::string &Feature) {
-  for (const auto &E : llvm::AArch64::Extensions) {
-if (Name == E.Name) {
-  Feature = E.Feature;
-  return;
-}
-  }
-  Feature = Name.str();
-}
-
 std::optional AArch64::getArchForCpu(StringRef CPU) {
   if (CPU == "generic")
 return ARMV8A;
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -505,7 +505,6 @@
 StringRef resolveCPUAlias(StringRef CPU);
 
 // Information by Name
-void getFeatureOption(StringRef Name, std::string &Feature);
 std::optional getArchForCpu(StringRef CPU);
 
 // Parser
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -973,12 +973,16 @@
   }
 }
   for (const auto &Feature : FeaturesVec)
-if (Feature[0] == '+') {
-  std::string F;
-  llvm::AArch64::getFeatureOption(Feature, F);
-  UpdatedFeaturesVec.push_back(F);
-} else if (Feature[0] != '?')
-  UpdatedFeaturesVec.push_back(Feature);
+if (Feature[0] != '?') {
+  std::string UpdatedFeature = Feature;
+  if (Feature[0] == '+') {
+std::optional Extension =
+  llvm::AArch64::parseArchExtension(Feature.substr(1));
+if (Extension)
+  UpdatedFeature = Extension->Feature.str();
+  }
+  UpdatedFeaturesVec.push_back(UpdatedFeature);
+}
 
   return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
 }


Index: llvm/lib/TargetParser/AArch64TargetParser.cpp
===
--- llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -25,16 +25,6 @@
   return 0;
 }
 
-void AArch64::getFeatureOption(StringRef Name, std::string &Feature) {
-  for (const auto &E : llvm::AArch64::Extensions) {
-if (Name == E.Name) {
-  Feature = E.Feature;
-  return;
-}
-  }
-  Feature = Name.str();
-}
-
 std::optional AArch64::getArchForCpu(StringRef CPU) {
   if (CPU == "generic")
 return ARMV8A;
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -505,7 +505,6 @@
 StringRef resolveCPUAlias(StringRef CPU);
 
 // Information by Name
-void getFeatureOption(StringRef Name, std::string &Feature);
 std::optional getArchForCpu(StringRef CPU);
 
 // Parser
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -973,12 +973,16 @@
   }
 }
   for (const auto &Feature : FeaturesVec)
-if (Feature[0] == '+') {
-  std::string F;
-  llvm::AArch64::getFeatureOption(Feature, F);
-  UpdatedFeaturesVec.push_back(F);
-} else if (Feature[0] != '?')
-  UpdatedFeaturesVec.push_back(Feature);
+if (Feature[0] != '?') {
+  std::string UpdatedFeature = Feature;
+  if (Feature[0] == '+') {
+std::optional Extension =
+  llvm::AArch64::parseArchExtension(Feature.substr(1));
+if (Extension)
+  UpdatedFeature = Extension->Feature.str();
+  }
+  UpdatedFeaturesVec.push_back(UpdatedFeature);
+}
 
   return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
 }
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[PATCH] D142539: [NFC][AArch64] Use optional returns in target parser instead of 'invalid' objects

2023-01-26 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked an inline comment as done.
pratlucas added inline comments.



Comment at: llvm/unittests/TargetParser/TargetParserTest.cpp:1456
+  std::optional Extension =
+  AArch64::parseArchExtension(ArchExt);
+  if (!Extension)

tmatheson wrote:
> I think we still need to test getDefaultExtensions, unless we're deleting it.
D142540 deletes it in favor of using the information in `CpuInfo` and 
`ArchInfo`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142539/new/

https://reviews.llvm.org/D142539

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[PATCH] D142540: [NFC][AArch64] Get default features directly from ArchInfo and CpuInfo objects

2023-01-26 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 492491.
pratlucas added a comment.

Renaming `getDefaultExtensions()` to `getImpliedExtensions()`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142540/new/

https://reviews.llvm.org/D142540

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/TargetParser/AArch64TargetParser.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -966,11 +966,9 @@
   EXPECT_TRUE(Cpu);
   EXPECT_EQ(params.ExpectedArch, Cpu->Arch.Name);
 
-  uint64_t default_extensions =
-  AArch64::getDefaultExtensions(params.CPUName, Cpu->Arch);
   EXPECT_PRED_FORMAT2(
   AssertSameExtensionFlags(params.CPUName),
-  params.ExpectedFlags, default_extensions);
+  params.ExpectedFlags, Cpu->getImpliedExtensions());
 }
 
 INSTANTIATE_TEST_SUITE_P(
@@ -1457,7 +1455,7 @@
   if (!Extension)
 return false;
   std::optional CpuInfo = AArch64::parseCpu(CPUName);
-  return (CpuInfo->Arch.DefaultExts | CpuInfo->DefaultExtensions) & Extension->ID;
+  return CpuInfo->getImpliedExtensions() & Extension->ID;
 }
 
 bool testAArch64Extension(const AArch64::ArchInfo &AI, StringRef ArchExt) {
Index: llvm/lib/TargetParser/AArch64TargetParser.cpp
===
--- llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -25,19 +25,6 @@
   return 0;
 }
 
-uint64_t AArch64::getDefaultExtensions(StringRef CPU,
-   const AArch64::ArchInfo &AI) {
-  if (CPU == "generic")
-return AI.DefaultExts;
-
-  // Note: this now takes cpu aliases into account
-  std::optional Cpu = parseCpu(CPU);
-  if (!Cpu)
-return AI.DefaultExts;
-
-  return Cpu->Arch.DefaultExts | Cpu->DefaultExtensions;
-}
-
 void AArch64::getFeatureOption(StringRef Name, std::string &Feature) {
   for (const auto &E : llvm::AArch64::Extensions) {
 if (Name == E.Name) {
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6891,8 +6891,7 @@
   // Get the architecture and extension features.
   std::vector AArch64Features;
   AArch64Features.push_back(ArchInfo->ArchFeature);
-  AArch64::getExtensionFeatures(
-  AArch64::getDefaultExtensions("generic", *ArchInfo), AArch64Features);
+  AArch64::getExtensionFeatures(ArchInfo->DefaultExts, AArch64Features);
 
   MCSubtargetInfo &STI = copySTI();
   std::vector ArchFeatures(AArch64Features.begin(), AArch64Features.end());
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -334,6 +334,10 @@
   const ArchInfo &Arch;
   uint64_t DefaultExtensions; // Default extensions for this CPU. These will be
   // ORd with the architecture defaults.
+
+  uint64_t getImpliedExtensions() const {
+return DefaultExtensions | Arch.DefaultExts;
+  }
 };
 
 inline constexpr CpuInfo CpuInfos[] = {
@@ -501,7 +505,6 @@
 StringRef resolveCPUAlias(StringRef CPU);
 
 // Information by Name
-uint64_t getDefaultExtensions(StringRef CPU, const ArchInfo &AI);
 void getFeatureOption(StringRef Name, std::string &Feature);
 std::optional getArchForCpu(StringRef CPU);
 
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -140,7 +140,7 @@
 
 Features.push_back(ArchInfo->ArchFeature);
 
-uint64_t Extension = llvm::AArch64::getDefaultExtensions(CPU, *ArchInfo);
+uint64_t Extension = CpuInfo->getImpliedExtensions();
 if (!llvm::AArch64::getExtensionFeatures(Extension, Features))
   return false;
   }
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -692,10 +692,8 @@
   Features[OtherArch->getSubArch()] = Enabled;
 
   // Set any features implied by the architecture
-  uint64_t Extensions =
-  llvm::AArch64::getDefaultExtensions("generic", *ArchInfo);
   std::vector CPUFeats;
-  if (llvm::AArch64::getExtensionFeatures(Extensions, CPUFeats)) {
+  if (llvm::AArch64::getExtensionFeatures(ArchInfo->DefaultExts, CP

[PATCH] D142539: [NFC][AArch64] Use optional returns in target parser instead of 'invalid' objects

2023-01-27 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
pratlucas marked an inline comment as done.
Closed by commit rG9ea00fc74c3c: [NFC][AArch64] Use optional returns in target 
parser instead of 'invalid'… (authored by pratlucas).

Changed prior to commit:
  https://reviews.llvm.org/D142539?vs=492095&id=492704#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142539/new/

https://reviews.llvm.org/D142539

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/TargetParser/AArch64TargetParser.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -17,6 +17,7 @@
 #include "llvm/TargetParser/Triple.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
+#include 
 #include 
 
 using namespace llvm;
@@ -961,11 +962,12 @@
 TEST_P(AArch64CPUTestFixture, testAArch64CPU) {
   ARMCPUTestParams params = GetParam();
 
-  const AArch64::ArchInfo &AI = AArch64::parseCpu(params.CPUName).Arch;
-  EXPECT_EQ(params.ExpectedArch, AI.Name);
+  const std::optional Cpu = AArch64::parseCpu(params.CPUName);
+  EXPECT_TRUE(Cpu);
+  EXPECT_EQ(params.ExpectedArch, Cpu->Arch.Name);
 
   uint64_t default_extensions =
-  AArch64::getDefaultExtensions(params.CPUName, AI);
+  AArch64::getDefaultExtensions(params.CPUName, Cpu->Arch);
   EXPECT_PRED_FORMAT2(
   AssertSameExtensionFlags(params.CPUName),
   params.ExpectedFlags, default_extensions);
@@ -974,10 +976,6 @@
 INSTANTIATE_TEST_SUITE_P(
 AArch64CPUTests, AArch64CPUTestFixture,
 ::testing::Values(
-ARMCPUTestParams("invalid", "invalid", "invalid", AArch64::AEK_NONE,
- ""),
-ARMCPUTestParams("generic", "invalid", "none", AArch64::AEK_NONE, ""),
-
 ARMCPUTestParams("cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1425,14 +1423,14 @@
   // valid, and match the expected 'magic' count.
   EXPECT_EQ(List.size(), NumAArch64CPUArchs);
   for(StringRef CPU : List) {
-EXPECT_NE(AArch64::parseCpu(CPU).Arch, AArch64::INVALID);
+EXPECT_TRUE(AArch64::parseCpu(CPU));
   }
 }
 
 bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
  unsigned ArchAttr) {
-  const AArch64::ArchInfo &AI = AArch64::parseArch(Arch);
-  return AI != AArch64::INVALID;
+  const std::optional AI = AArch64::parseArch(Arch);
+  return AI.has_value();
 }
 
 TEST(TargetParserTest, testAArch64Arch) {
@@ -1468,81 +1466,92 @@
   ARMBuildAttrs::CPUArch::v8_A));
 }
 
-bool testAArch64Extension(StringRef CPUName, const AArch64::ArchInfo &AI,
-  StringRef ArchExt) {
-  return AArch64::getDefaultExtensions(CPUName, AI) &
- AArch64::parseArchExt(ArchExt);
+bool testAArch64Extension(StringRef CPUName, StringRef ArchExt) {
+  std::optional Extension =
+  AArch64::parseArchExtension(ArchExt);
+  if (!Extension)
+return false;
+  std::optional CpuInfo = AArch64::parseCpu(CPUName);
+  return (CpuInfo->Arch.DefaultExts | CpuInfo->DefaultExtensions) & Extension->ID;
+}
+
+bool testAArch64Extension(const AArch64::ArchInfo &AI, StringRef ArchExt) {
+  std::optional Extension =
+  AArch64::parseArchExtension(ArchExt);
+  if (!Extension)
+return false;
+  return AI.DefaultExts & Extension->ID;
 }
 
 TEST(TargetParserTest, testAArch64Extension) {
-  EXPECT_FALSE(testAArch64Extension("cortex-a34", AArch64::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a35", AArch64::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a53", AArch64::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55", AArch64::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55", AArch64::INVALID, "fp16"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a55", AArch64::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55", AArch64::INVALID, "dotprod"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a57", AArch64::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a72", AArch64::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a73", AArch64::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75", AArch64::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75", AArch64::INVALID, "fp16"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a75", AArch64::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75", AArch64

[PATCH] D142540: [NFC][AArch64] Get default features directly from ArchInfo and CpuInfo objects

2023-01-27 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0753cf2caca7: [NFC][AArch64] Get default features directly 
from ArchInfo and CpuInfo objects (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142540/new/

https://reviews.llvm.org/D142540

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/TargetParser/AArch64TargetParser.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -966,11 +966,9 @@
   EXPECT_TRUE(Cpu);
   EXPECT_EQ(params.ExpectedArch, Cpu->Arch.Name);
 
-  uint64_t default_extensions =
-  AArch64::getDefaultExtensions(params.CPUName, Cpu->Arch);
   EXPECT_PRED_FORMAT2(
   AssertSameExtensionFlags(params.CPUName),
-  params.ExpectedFlags, default_extensions);
+  params.ExpectedFlags, Cpu->getImpliedExtensions());
 }
 
 INSTANTIATE_TEST_SUITE_P(
@@ -1472,7 +1470,7 @@
   if (!Extension)
 return false;
   std::optional CpuInfo = AArch64::parseCpu(CPUName);
-  return (CpuInfo->Arch.DefaultExts | CpuInfo->DefaultExtensions) & Extension->ID;
+  return CpuInfo->getImpliedExtensions() & Extension->ID;
 }
 
 bool testAArch64Extension(const AArch64::ArchInfo &AI, StringRef ArchExt) {
Index: llvm/lib/TargetParser/AArch64TargetParser.cpp
===
--- llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -25,19 +25,6 @@
   return 0;
 }
 
-uint64_t AArch64::getDefaultExtensions(StringRef CPU,
-   const AArch64::ArchInfo &AI) {
-  if (CPU == "generic")
-return AI.DefaultExts;
-
-  // Note: this now takes cpu aliases into account
-  std::optional Cpu = parseCpu(CPU);
-  if (!Cpu)
-return AI.DefaultExts;
-
-  return Cpu->Arch.DefaultExts | Cpu->DefaultExtensions;
-}
-
 void AArch64::getFeatureOption(StringRef Name, std::string &Feature) {
   for (const auto &E : llvm::AArch64::Extensions) {
 if (Name == E.Name) {
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6891,8 +6891,7 @@
   // Get the architecture and extension features.
   std::vector AArch64Features;
   AArch64Features.push_back(ArchInfo->ArchFeature);
-  AArch64::getExtensionFeatures(
-  AArch64::getDefaultExtensions("generic", *ArchInfo), AArch64Features);
+  AArch64::getExtensionFeatures(ArchInfo->DefaultExts, AArch64Features);
 
   MCSubtargetInfo &STI = copySTI();
   std::vector ArchFeatures(AArch64Features.begin(), AArch64Features.end());
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -334,6 +334,10 @@
   const ArchInfo &Arch;
   uint64_t DefaultExtensions; // Default extensions for this CPU. These will be
   // ORd with the architecture defaults.
+
+  uint64_t getImpliedExtensions() const {
+return DefaultExtensions | Arch.DefaultExts;
+  }
 };
 
 inline constexpr CpuInfo CpuInfos[] = {
@@ -509,7 +513,6 @@
 StringRef resolveCPUAlias(StringRef CPU);
 
 // Information by Name
-uint64_t getDefaultExtensions(StringRef CPU, const ArchInfo &AI);
 void getFeatureOption(StringRef Name, std::string &Feature);
 std::optional getArchForCpu(StringRef CPU);
 
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -140,7 +140,7 @@
 
 Features.push_back(ArchInfo->ArchFeature);
 
-uint64_t Extension = llvm::AArch64::getDefaultExtensions(CPU, *ArchInfo);
+uint64_t Extension = CpuInfo->getImpliedExtensions();
 if (!llvm::AArch64::getExtensionFeatures(Extension, Features))
   return false;
   }
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -692,10 +692,8 @@
   Features[OtherArch->getSubArch()] = Enabled;
 
   // Set any features implied by the architecture
-  uint64_t Extensions =
-  llvm::AArch64::getDefaultExtensions("generic", *ArchInfo);
   std::vector CPUFeats;
-  if (l

[PATCH] D142541: [NFC][AArch64] Get extension strings directly from ArchInfo in target parser

2023-01-27 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG852bb68ddb2b: [NFC][AArch64] Get extension strings directly 
from ArchInfo in target parser (authored by pratlucas).

Repository:
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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/TargetParser/AArch64TargetParser.cpp


Index: llvm/lib/TargetParser/AArch64TargetParser.cpp
===
--- llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -25,16 +25,6 @@
   return 0;
 }
 
-void AArch64::getFeatureOption(StringRef Name, std::string &Feature) {
-  for (const auto &E : llvm::AArch64::Extensions) {
-if (Name == E.Name) {
-  Feature = E.Feature;
-  return;
-}
-  }
-  Feature = Name.str();
-}
-
 std::optional AArch64::getArchForCpu(StringRef CPU) {
   if (CPU == "generic")
 return ARMV8A;
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -513,7 +513,6 @@
 StringRef resolveCPUAlias(StringRef CPU);
 
 // Information by Name
-void getFeatureOption(StringRef Name, std::string &Feature);
 std::optional getArchForCpu(StringRef CPU);
 
 // Parser
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -973,12 +973,16 @@
   }
 }
   for (const auto &Feature : FeaturesVec)
-if (Feature[0] == '+') {
-  std::string F;
-  llvm::AArch64::getFeatureOption(Feature, F);
-  UpdatedFeaturesVec.push_back(F);
-} else if (Feature[0] != '?')
-  UpdatedFeaturesVec.push_back(Feature);
+if (Feature[0] != '?') {
+  std::string UpdatedFeature = Feature;
+  if (Feature[0] == '+') {
+std::optional Extension =
+  llvm::AArch64::parseArchExtension(Feature.substr(1));
+if (Extension)
+  UpdatedFeature = Extension->Feature.str();
+  }
+  UpdatedFeaturesVec.push_back(UpdatedFeature);
+}
 
   return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
 }


Index: llvm/lib/TargetParser/AArch64TargetParser.cpp
===
--- llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -25,16 +25,6 @@
   return 0;
 }
 
-void AArch64::getFeatureOption(StringRef Name, std::string &Feature) {
-  for (const auto &E : llvm::AArch64::Extensions) {
-if (Name == E.Name) {
-  Feature = E.Feature;
-  return;
-}
-  }
-  Feature = Name.str();
-}
-
 std::optional AArch64::getArchForCpu(StringRef CPU) {
   if (CPU == "generic")
 return ARMV8A;
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -513,7 +513,6 @@
 StringRef resolveCPUAlias(StringRef CPU);
 
 // Information by Name
-void getFeatureOption(StringRef Name, std::string &Feature);
 std::optional getArchForCpu(StringRef CPU);
 
 // Parser
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -973,12 +973,16 @@
   }
 }
   for (const auto &Feature : FeaturesVec)
-if (Feature[0] == '+') {
-  std::string F;
-  llvm::AArch64::getFeatureOption(Feature, F);
-  UpdatedFeaturesVec.push_back(F);
-} else if (Feature[0] != '?')
-  UpdatedFeaturesVec.push_back(Feature);
+if (Feature[0] != '?') {
+  std::string UpdatedFeature = Feature;
+  if (Feature[0] == '+') {
+std::optional Extension =
+  llvm::AArch64::parseArchExtension(Feature.substr(1));
+if (Extension)
+  UpdatedFeature = Extension->Feature.str();
+  }
+  UpdatedFeaturesVec.push_back(UpdatedFeature);
+}
 
   return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
 }
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[PATCH] D138792: [AArch64] Improve TargetParser API

2023-01-13 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas accepted this revision.
pratlucas added a comment.

LGTM with a tiny nit. Feel free to fix it when landing the changes.




Comment at: llvm/include/llvm/TargetParser/AArch64TargetParser.h:164-166
+  CPUFeatures CPUFeature;  // ?
+  StringRef DependentFeatures; // ?
+  unsigned FmvPriority;// ?

Minor nit: can you replace the `// ?` comments with a single TODO to 
document those better? It'd look a bit less confusing for others reading this 
in the future.


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[PATCH] D141403: [AArch64] Add command line support for v9.4-A's Instrumentation Extension

2023-01-23 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 491384.
pratlucas added a comment.

Rebasing, including minor changes due to recent target parser refactoring.


Repository:
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Files:
  clang/test/Driver/aarch64-ite.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/unittests/TargetParser/TargetParserTest.cpp


Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1553,6 +1553,7 @@
   AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
   AArch64::AEK_RCPC3,   AArch64::AEK_THE,   AArch64::AEK_D128,
   AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
+  AArch64::AEK_ITE,
   };
 
   std::vector Features;
@@ -1624,6 +1625,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -147,6 +147,7 @@
   AEK_LSE128 =  1ULL << 52, // FEAT_LSE128
   AEK_SPECRES2 =1ULL << 53, // FEAT_SPECRES2
   AEK_RASv2 =   1ULL << 54, // FEAT_RASv2
+  AEK_ITE = 1ULL << 55, // FEAT_ITE
 };
 // clang-format on
 
@@ -196,6 +197,7 @@
 {"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250},
 {"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_MAX, "", 0},
 {"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270},
+{"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_MAX, "", 0},
 {"jscvt", AArch64::AEK_NONE, {}, {}, FEAT_JSCVT, 
"+fp-armv8,+neon,+jsconv", 210},
 {"ls64_accdata", AArch64::AEK_NONE, {}, {}, FEAT_LS64_ACCDATA, "+ls64", 
540},
 {"ls64_v", AArch64::AEK_NONE, {}, {}, FEAT_LS64_V, "", 530},
Index: clang/test/Driver/aarch64-ite.c
===
--- /dev/null
+++ clang/test/Driver/aarch64-ite.c
@@ -0,0 +1,17 @@
+// Test that target feature ite is implemented and available correctly
+
+// FEAT_ITE is optional (off by default) for v8.9a/9.4a and older, and can be 
enabled using +ite
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a   %s 
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+ite   %s 
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+noite %s 
2>&1 | FileCheck %s --check-prefix=DISABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a   %s 
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+ite   %s 
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+noite %s 
2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// FEAT_ITE is invalid before v8
+// RUN: %clang -### -target arm-none-none-eabi -march=armv7-a+ite %s 2>&1 
| FileCheck %s --check-prefix=INVALID
+
+// INVALID: error: unsupported argument 'armv7-a+ite' to option '-march='
+// ENABLED: "-target-feature" "+ite"
+// NOT_ENABLED-NOT: "-target-feature" "+ite"
+// DISABLED: "-target-feature" "-ite"


Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1553,6 +1553,7 @@
   AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
   AArch64::AEK_RCPC3,   AArch64::AEK_THE,   AArch64::AEK_D128,
   AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
+  AArch64::AEK_ITE,
   };
 
   std::vector Features;
@@ -1624,6 +1625,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetPa

[PATCH] D141404: [AArch64][Clang] Adjust default features for v8.9-A/v9.4-A in clang driver

2023-01-23 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 491385.
pratlucas added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Updated to use the same approach as D141518 .


Repository:
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Files:
  clang/test/Driver/aarch64-cssc.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h


Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -315,12 +315,12 @@
 inline constexpr ArchInfo ARMV8_6A  = { VersionTuple{8, 6}, AProfile, 
"armv8.6-a", "+v8.6a", (BaseNoCrypto | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | 
AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)};
 inline constexpr ArchInfo ARMV8_7A  = { VersionTuple{8, 7}, AProfile, 
"armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)};
 inline constexpr ArchInfo ARMV8_8A  = { VersionTuple{8, 8}, AProfile, 
"armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts | AArch64::AEK_MOPS | 
AArch64::AEK_HBC)};
-inline constexpr ArchInfo ARMV8_9A  = { VersionTuple{8, 9}, AProfile, 
"armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts)};
+inline constexpr ArchInfo ARMV8_9A  = { VersionTuple{8, 9}, AProfile, 
"armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts | AArch64::AEK_SPECRES2 | 
AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
 inline constexpr ArchInfo ARMV9A= { VersionTuple{9, 0}, AProfile, 
"armv9-a", "+v9a", (BaseNoCrypto | AArch64::AEK_FP16 | AArch64::AEK_SVE | 
AArch64::AEK_SVE2)};
 inline constexpr ArchInfo ARMV9_1A  = { VersionTuple{9, 1}, AProfile, 
"armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts | AArch64::AEK_BF16 | 
AArch64::AEK_I8MM)};
 inline constexpr ArchInfo ARMV9_2A  = { VersionTuple{9, 2}, AProfile, 
"armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts)};
 inline constexpr ArchInfo ARMV9_3A  = { VersionTuple{9, 3}, AProfile, 
"armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts | AArch64::AEK_MOPS | 
AArch64::AEK_HBC)};
-inline constexpr ArchInfo ARMV9_4A  = { VersionTuple{9, 4}, AProfile, 
"armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts)};
+inline constexpr ArchInfo ARMV9_4A  = { VersionTuple{9, 4}, AProfile, 
"armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts | AArch64::AEK_SPECRES2 | 
AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
 // For v8-R, we do not enable crypto and align with GCC that enables a more 
minimal set of optional architecture extensions.
 inline constexpr ArchInfo ARMV8R= { VersionTuple{8, 0}, RProfile, 
"armv8-r", "+v8r", ((BaseNoCrypto ^ AArch64::AEK_LSE) | AArch64::AEK_SSBS | 
AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_SB), };
 // clang-format on
Index: clang/test/Driver/aarch64-cssc.c
===
--- clang/test/Driver/aarch64-cssc.c
+++ clang/test/Driver/aarch64-cssc.c
@@ -1,15 +1,17 @@
 // Test that target feature cssc is implemented and available correctly
-// RUN: %clang -### -target aarch64-none-none-eabi %s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a%s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nocssc %s 
2>&1 | FileCheck %s --check-prefix=NO_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a%s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nocssc %s 
2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// FEAT_CSSC is a required part of v8.9a/v9.4a and optional from v8.7a/v9.3a 
onwards.
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi   
  %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv8.7-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv8.9-a%s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv8.9-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv8.9-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv9.2-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none

[PATCH] D141404: [AArch64][Clang] Adjust default features for v8.9-A/v9.4-A in clang driver

2023-01-23 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked an inline comment as done.
pratlucas added inline comments.



Comment at: clang/test/Driver/aarch64-cssc.c:11
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv9.4-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
 

tmatheson wrote:
> Missing -###?
That's a consequence of the approach from D141518. The target features now go 
into IR attributes instead.


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[PATCH] D141403: [AArch64] Add command line support for v9.4-A's Instrumentation Extension

2023-01-23 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8246aceb90c2: [AArch64] Add command line support for 
v9.4-A's Instrumentation Extension (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/aarch64-ite.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/unittests/TargetParser/TargetParserTest.cpp


Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1553,6 +1553,7 @@
   AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
   AArch64::AEK_RCPC3,   AArch64::AEK_THE,   AArch64::AEK_D128,
   AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
+  AArch64::AEK_ITE,
   };
 
   std::vector Features;
@@ -1624,6 +1625,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -147,6 +147,7 @@
   AEK_LSE128 =  1ULL << 52, // FEAT_LSE128
   AEK_SPECRES2 =1ULL << 53, // FEAT_SPECRES2
   AEK_RASv2 =   1ULL << 54, // FEAT_RASv2
+  AEK_ITE = 1ULL << 55, // FEAT_ITE
 };
 // clang-format on
 
@@ -196,6 +197,7 @@
 {"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250},
 {"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_MAX, "", 0},
 {"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270},
+{"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_MAX, "", 0},
 {"jscvt", AArch64::AEK_NONE, {}, {}, FEAT_JSCVT, 
"+fp-armv8,+neon,+jsconv", 210},
 {"ls64_accdata", AArch64::AEK_NONE, {}, {}, FEAT_LS64_ACCDATA, "+ls64", 
540},
 {"ls64_v", AArch64::AEK_NONE, {}, {}, FEAT_LS64_V, "", 530},
Index: clang/test/Driver/aarch64-ite.c
===
--- /dev/null
+++ clang/test/Driver/aarch64-ite.c
@@ -0,0 +1,17 @@
+// Test that target feature ite is implemented and available correctly
+
+// FEAT_ITE is optional (off by default) for v8.9a/9.4a and older, and can be 
enabled using +ite
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a   %s 
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+ite   %s 
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+noite %s 
2>&1 | FileCheck %s --check-prefix=DISABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a   %s 
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+ite   %s 
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+noite %s 
2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// FEAT_ITE is invalid before v8
+// RUN: %clang -### -target arm-none-none-eabi -march=armv7-a+ite %s 2>&1 
| FileCheck %s --check-prefix=INVALID
+
+// INVALID: error: unsupported argument 'armv7-a+ite' to option '-march='
+// ENABLED: "-target-feature" "+ite"
+// NOT_ENABLED-NOT: "-target-feature" "+ite"
+// DISABLED: "-target-feature" "-ite"


Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1553,6 +1553,7 @@
   AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
   AArch64::AEK_RCPC3,   AArch64::AEK_THE,   AArch64::AEK_D128,
   AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
+  AArch64::AEK_ITE,
   };
 
   std::vector Features;
@@ -1624,6 +1625,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h

[PATCH] D141404: [AArch64][Clang] Adjust default features for v8.9-A/v9.4-A in clang driver

2023-01-23 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
pratlucas marked an inline comment as done.
Closed by commit rG5f6813beed85: [AArch64][Clang] Adjust default features for 
v8.9-A/v9.4-A in clang driver (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141404/new/

https://reviews.llvm.org/D141404

Files:
  clang/test/Driver/aarch64-cssc.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h


Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -315,12 +315,12 @@
 inline constexpr ArchInfo ARMV8_6A  = { VersionTuple{8, 6}, AProfile, 
"armv8.6-a", "+v8.6a", (BaseNoCrypto | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | 
AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)};
 inline constexpr ArchInfo ARMV8_7A  = { VersionTuple{8, 7}, AProfile, 
"armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)};
 inline constexpr ArchInfo ARMV8_8A  = { VersionTuple{8, 8}, AProfile, 
"armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts | AArch64::AEK_MOPS | 
AArch64::AEK_HBC)};
-inline constexpr ArchInfo ARMV8_9A  = { VersionTuple{8, 9}, AProfile, 
"armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts)};
+inline constexpr ArchInfo ARMV8_9A  = { VersionTuple{8, 9}, AProfile, 
"armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts | AArch64::AEK_SPECRES2 | 
AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
 inline constexpr ArchInfo ARMV9A= { VersionTuple{9, 0}, AProfile, 
"armv9-a", "+v9a", (BaseNoCrypto | AArch64::AEK_FP16 | AArch64::AEK_SVE | 
AArch64::AEK_SVE2)};
 inline constexpr ArchInfo ARMV9_1A  = { VersionTuple{9, 1}, AProfile, 
"armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts | AArch64::AEK_BF16 | 
AArch64::AEK_I8MM)};
 inline constexpr ArchInfo ARMV9_2A  = { VersionTuple{9, 2}, AProfile, 
"armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts)};
 inline constexpr ArchInfo ARMV9_3A  = { VersionTuple{9, 3}, AProfile, 
"armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts | AArch64::AEK_MOPS | 
AArch64::AEK_HBC)};
-inline constexpr ArchInfo ARMV9_4A  = { VersionTuple{9, 4}, AProfile, 
"armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts)};
+inline constexpr ArchInfo ARMV9_4A  = { VersionTuple{9, 4}, AProfile, 
"armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts | AArch64::AEK_SPECRES2 | 
AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
 // For v8-R, we do not enable crypto and align with GCC that enables a more 
minimal set of optional architecture extensions.
 inline constexpr ArchInfo ARMV8R= { VersionTuple{8, 0}, RProfile, 
"armv8-r", "+v8r", ((BaseNoCrypto ^ AArch64::AEK_LSE) | AArch64::AEK_SSBS | 
AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_SB), };
 // clang-format on
Index: clang/test/Driver/aarch64-cssc.c
===
--- clang/test/Driver/aarch64-cssc.c
+++ clang/test/Driver/aarch64-cssc.c
@@ -1,15 +1,17 @@
 // Test that target feature cssc is implemented and available correctly
-// RUN: %clang -### -target aarch64-none-none-eabi %s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a%s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nocssc %s 
2>&1 | FileCheck %s --check-prefix=NO_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a%s 
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nocssc %s 
2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// FEAT_CSSC is a required part of v8.9a/v9.4a and optional from v8.7a/v9.3a 
onwards.
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi   
  %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv8.7-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv8.9-a%s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv8.9-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv8.9-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv9.2-a+cssc

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-13 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6119053dab67: [ARM][Thumb] Command-line option to ensure 
AAPCS compliant Frame Records (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,288 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:bx r1
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AAPCS-NEXT:.save {lr}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:mov lr, r11
+; FP-AAPCS-NEXT:.save {r11}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAP

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-13 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 436396.
pratlucas added a comment.

Fixing assertion failure caused by incorrect use of tSTRr.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,288 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:bx r1
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AAPCS-NEXT:.save {lr}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:mov lr, r11
+; FP-AAPCS-NEXT:.save {r11}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:.setfp r11, sp
+; FP-AAPCS-NEXT:mov r11, sp
+; FP-AAPCS-NEXT:.pad #8
+; FP-AAPCS-NEXT:sub sp, #8
+; FP

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-14 Thread Lucas Prates via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7625e01d6616: [ARM][Thumb] Command-line option to ensure 
AAPCS compliant Frame Records (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,288 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:bx r1
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AAPCS-NEXT:.save {lr}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:mov lr, r11
+; FP-AAPCS-NEXT:.save {r11}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAP

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-14 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

The newly added `frame-chain.ll` test uncovered an issue with an invalid use of 
the tMOVr instruction, which is only available from V6 onwards. The failure was 
captured by a buildbot with expensive checks enabled.
The issue is unrelated to the codegen changes from this patch, and still 
happens when compiling the same IR code if the changes are reverted.
Given the above, I've updated the test to use thumbv6m while the issue is not 
resolved: rGcbcce82ef6b5 
.


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[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-14 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas added a comment.

@RKSimon I was writting my comment above just before I saw your message, lucky 
they went in in the correct order :)
I'm tracking down the source of the invalid `tMOVr` and I'll raise a ticket 
with the details.


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[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-23 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 439356.
pratlucas added a comment.

Fixing use-after-poison issue detected by ASAN buildbot.

When popping LR on thumb it's value is popped into PC and used as a return.
The original return instruction gets erased, invalidating the MachineInstr
iterator. This change makes sure we don't try to access the iterator in these
conditions.


Repository:
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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,274 @@
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all --verify-machineinstrs | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumbv6m-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf --verify-machineinstrs | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {pc}
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NE

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-07 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 434846.
pratlucas marked 2 inline comments as done.
pratlucas added a comment.

Addressing comments.


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,288 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:bx r1
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AAPCS-NEXT:.save {lr}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:mov lr, r11
+; FP-AAPCS-NEXT:.save {r11}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:.setfp r11, sp
+; FP-AAPCS-NEXT:mov r11, sp
+; FP-AAPCS-NEXT:.pad #8
+; FP-AAPCS-NEXT:sub sp, #8

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-07 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked 2 inline comments as done.
pratlucas added inline comments.



Comment at: llvm/lib/Target/ARM/ARMFrameLowering.cpp:732
+  // AAPCS requires use of R11, and PACBTI gets in the way of regular pushes,
+  // so FP ends up on area two.
   if (HasFP) {

efriedma wrote:
> I guess this is related to this patch because it involves the interaction of 
> PACBTI with -mframe_chain ?  (Without this patch, PACBTI doesn't exist on any 
> targets where the frame pointer is in r11.)  I'm fine leaving it to a 
> followup, though.
Sounds good. I'm going to address that on a followup patch.


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[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-08 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas updated this revision to Diff 435157.
pratlucas added a comment.

Avoid scavenging extra register when accessing const pool.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMCallingConv.td
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/ARM/frame-chain.ll
  llvm/test/CodeGen/Thumb/frame-access.ll
  llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
  llvm/test/CodeGen/Thumb/frame-chain.ll

Index: llvm/test/CodeGen/Thumb/frame-chain.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Thumb/frame-chain.ll
@@ -0,0 +1,288 @@
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all | FileCheck %s --check-prefixes=FP,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-FP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf | FileCheck %s --check-prefixes=FP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=FP-AAPCS,LEAF-NOFP-AAPCS
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none | FileCheck %s --check-prefixes=NOFP,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP
+; RUN: llc -mtriple thumb-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-frame-chain-leaf | FileCheck %s --check-prefixes=NOFP-AAPCS,LEAF-NOFP-AAPCS
+
+define dso_local noundef i32 @leaf(i32 noundef %0) {
+; LEAF-FP-LABEL: leaf:
+; LEAF-FP:   @ %bb.0:
+; LEAF-FP-NEXT:.pad #4
+; LEAF-FP-NEXT:sub sp, #4
+; LEAF-FP-NEXT:str r0, [sp]
+; LEAF-FP-NEXT:adds r0, r0, #4
+; LEAF-FP-NEXT:add sp, #4
+; LEAF-FP-NEXT:bx lr
+;
+; LEAF-FP-AAPCS-LABEL: leaf:
+; LEAF-FP-AAPCS:   @ %bb.0:
+; LEAF-FP-AAPCS-NEXT:.save {lr}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:mov lr, r11
+; LEAF-FP-AAPCS-NEXT:.save {r11}
+; LEAF-FP-AAPCS-NEXT:push {lr}
+; LEAF-FP-AAPCS-NEXT:.setfp r11, sp
+; LEAF-FP-AAPCS-NEXT:mov r11, sp
+; LEAF-FP-AAPCS-NEXT:.pad #4
+; LEAF-FP-AAPCS-NEXT:sub sp, #4
+; LEAF-FP-AAPCS-NEXT:str r0, [sp]
+; LEAF-FP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-FP-AAPCS-NEXT:add sp, #4
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:mov r11, r1
+; LEAF-FP-AAPCS-NEXT:pop {r1}
+; LEAF-FP-AAPCS-NEXT:bx r1
+;
+; LEAF-NOFP-LABEL: leaf:
+; LEAF-NOFP:   @ %bb.0:
+; LEAF-NOFP-NEXT:.pad #4
+; LEAF-NOFP-NEXT:sub sp, #4
+; LEAF-NOFP-NEXT:str r0, [sp]
+; LEAF-NOFP-NEXT:adds r0, r0, #4
+; LEAF-NOFP-NEXT:add sp, #4
+; LEAF-NOFP-NEXT:bx lr
+;
+; LEAF-NOFP-AAPCS-LABEL: leaf:
+; LEAF-NOFP-AAPCS:   @ %bb.0:
+; LEAF-NOFP-AAPCS-NEXT:.pad #4
+; LEAF-NOFP-AAPCS-NEXT:sub sp, #4
+; LEAF-NOFP-AAPCS-NEXT:str r0, [sp]
+; LEAF-NOFP-AAPCS-NEXT:adds r0, r0, #4
+; LEAF-NOFP-AAPCS-NEXT:add sp, #4
+; LEAF-NOFP-AAPCS-NEXT:bx lr
+  %2 = alloca i32, align 4
+  store i32 %0, i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
+  %4 = add nsw i32 %3, 4
+  ret i32 %4
+}
+
+define dso_local noundef i32 @non_leaf(i32 noundef %0) {
+; FP-LABEL: non_leaf:
+; FP:   @ %bb.0:
+; FP-NEXT:.save {r7, lr}
+; FP-NEXT:push {r7, lr}
+; FP-NEXT:.setfp r7, sp
+; FP-NEXT:add r7, sp, #0
+; FP-NEXT:.pad #8
+; FP-NEXT:sub sp, #8
+; FP-NEXT:str r0, [sp, #4]
+; FP-NEXT:bl leaf
+; FP-NEXT:adds r0, r0, #1
+; FP-NEXT:add sp, #8
+; FP-NEXT:pop {r7}
+; FP-NEXT:pop {r1}
+; FP-NEXT:bx r1
+;
+; FP-AAPCS-LABEL: non_leaf:
+; FP-AAPCS:   @ %bb.0:
+; FP-AAPCS-NEXT:.save {lr}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:mov lr, r11
+; FP-AAPCS-NEXT:.save {r11}
+; FP-AAPCS-NEXT:push {lr}
+; FP-AAPCS-NEXT:.setfp r11, sp
+; FP-AAPCS-NEXT:mov r11, sp
+; FP-AAPCS-NEXT:.pad #8
+; FP-AAPCS-NEXT:sub sp, #8
+; FP

[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

2022-06-08 Thread Lucas Prates via Phabricator via cfe-commits

pratlucas marked an inline comment as done.
pratlucas added inline comments.



Comment at: llvm/test/CodeGen/Thumb/frame-access.ll:335
+; CHECK-FP-AAPCS: mov r1, r11
+; CHECK-FP-AAPCS: ldr r0, [r0, r1]
+; CHECK: bl i

efriedma wrote:
> This sequence requires, in general, scavenging two registers.  I'm not sure 
> we can do that in general?  I think we normally only have one emergency spill 
> slot.
> 
> Maybe we can save a register using add instead of mov; something like `ldr 
> r0, .LCPI0_0; add r0, r11; ldr r0, [r0]`.
That's true. Loads aren't affected as they reuse the destination register, but 
stores would indeed require the scaveging of two registers.
I've updaded the code to use the `add` approach instead.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125094/new/

https://reviews.llvm.org/D125094

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