from:"LevyHsu via Phabricator via cfe\-commits"

[PATCH] D101143: [RISCV] [1/2] Add IR intrinsic for Zbe extension

2021-04-23 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, kito-cheng, asb, jrtc27, Jim.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, sabuasal, 
simoncook, johnrusso, rbar, hiraditya.
LevyHsu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.

RV32/64:

  bcomress
  bdecompress

RV64 ONLY:

  bcomressw
  bdecompressw


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101143

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBE
+
+declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+
+define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: bcompress32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bcompressw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBE-LABEL: bcompress32:
+; RV64IBE:   # %bb.0:
+; RV64IBE-NEXT:bcompressw a0, a0, a1
+; RV64IBE-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+
+define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: bdecompress32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bdecompressw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBE-LABEL: bdecompress32:
+; RV64IBE:   # %bb.0:
+; RV64IBE-NEXT:bdecompressw a0, a0, a1
+; RV64IBE-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
+
+define i64 @bcompress64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bcompress64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bcompress a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBE-LABEL: bcompress64:
+; RV64IBE:   # %bb.0:
+; RV64IBE-NEXT:bcompress a0, a0, a1
+; RV64IBE-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
+
+define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bdecompress64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bdecompress a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBE-LABEL: bdecompress64:
+; RV64IBE:   # %bb.0:
+; RV64IBE-NEXT:bdecompress a0, a0, a1
+; RV64IBE-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBE
+
+declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+
+define i32 @bcompress32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: bcompress32:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:bcompress a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBE-LABEL: bcompress32:
+; RV32IBE:   # %bb.0:
+; RV32IBE-NEXT:bcompress a0, a0, a1
+; RV32IBE-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+
+define i32 @bdecompress32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: bdecompress32:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:bdecompress a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBE-LABEL: bdecompress32:
+; RV32IBE:   # %bb.0:
+; RV32IBE-NEXT:bdecompress a0, a0, a1
+; RV32IBE-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td

[PATCH] D101144: [RISCV] [2/2] Add IR intrinsic for Zbe extension

2021-04-23 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, jrtc27, Jim, asb, kito-cheng.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, usaxena95, s.egerton, benna, psnobl, kadircet, jocewei, PkmX, 
arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, mgorny.
LevyHsu requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang-tools-extra.

RV32/64:

  bcomress
  bdecompress

RV64 ONLY:

  bcomressw
  bdecompressw


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101144

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbe_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c

Index: clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbe %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbe %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,26 @@
+/*===-- rvintrin.h -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbe)
+#include "riscv_zbe_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
\ No newline at end of file
Index: clang/lib/Headers/riscv_zbe_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbe_intrin.h
@@ -0,0 +1,51 @@
+/*=== riscv_zbe_intrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __RISCV_ZBE_INTRIN_H
+#define __RISCV_ZBE_INTRIN_H
+
+#include 
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbe
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv_bcompress_32(int32_t rs1,
+  int32_t rs2) {
+  return __builtin_riscv_bcompress_32(rs1, rs2);
+}
+
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv_bdecompress_32(int32_t rs1,
+int32_t rs2) {
+  return __builtin_riscv_bdecompress_32(rs1, rs2);
+}
+
+// RV64 ONLY
+#if __riscv_xlen == 64
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv_bcompress_64(int64_t rs1,
+  int64_t rs2) {
+  return __builtin_riscv_bcompress_64(rs1, rs2);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv_bdecompress_64(int64_t rs1,
+int64_t rs2) {
+  return __builtin_riscv_bdecompress_64(rs1, rs2);
+}
+#endif // if __riscv_xlen == 64
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBE_INTRIN_H
\ No newline at end of file
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbe_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"includ

[PATCH] D101143: [RISCV] [1/2] Add IR intrinsic for Zbe extension

2021-04-24 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 340322.
LevyHsu marked an inline comment as done.
LevyHsu added a comment.

1. llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  - Format fix: Aligned SDT*** for:

  riscv_bcompress
riscv_bcompressw
riscv_bdecompress
riscv_bdecompressw


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101143/new/

https://reviews.llvm.org/D101143

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBE
+
+declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+
+define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: bcompress32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bcompressw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBE-LABEL: bcompress32:
+; RV64IBE:   # %bb.0:
+; RV64IBE-NEXT:bcompressw a0, a0, a1
+; RV64IBE-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+
+define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: bdecompress32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bdecompressw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBE-LABEL: bdecompress32:
+; RV64IBE:   # %bb.0:
+; RV64IBE-NEXT:bdecompressw a0, a0, a1
+; RV64IBE-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
+
+define i64 @bcompress64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bcompress64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bcompress a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBE-LABEL: bcompress64:
+; RV64IBE:   # %bb.0:
+; RV64IBE-NEXT:bcompress a0, a0, a1
+; RV64IBE-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
+
+define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bdecompress64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bdecompress a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBE-LABEL: bdecompress64:
+; RV64IBE:   # %bb.0:
+; RV64IBE-NEXT:bdecompress a0, a0, a1
+; RV64IBE-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBE
+
+declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+
+define i32 @bcompress32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: bcompress32:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:bcompress a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBE-LABEL: bcompress32:
+; RV32IBE:   # %bb.0:
+; RV32IBE-NEXT:bcompress a0, a0, a1
+; RV32IBE-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+
+define i32 @bdecompress32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: bdecompress32:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:bdecompress a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBE-LABEL: bdecompress32:
+; RV32IBE:   # %bb.0:
+; RV32IBE-NEXT:bdecompress a0, a0, a1
+; RV32IBE-NEXT:ret
+  %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -33,6 +33,10 @@
 def riscv_shflw  : SDNode<"RISCVISD::SHFLW",  SDT_RISCVIntBinOpW>;
 def riscv_unshfl : SDNode<"

[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

2021-04-25 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, kito-cheng, jrtc27, asb, Jim.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, sabuasal, 
simoncook, johnrusso, rbar, hiraditya.
LevyHsu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.

RV64 ONLY:

  bmator
  bmatxor
  bmatflip


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101248

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBM
+
+declare i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+
+define i64 @bmator64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmator64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmator a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmator64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmator a0, a0, a1
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+
+define i64 @bmatxor64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmatxor64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmatxor a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmatxor64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmatxor a0, a0, a1
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatflip.i64(i64 %a)
+
+define i64 @bmatflip64(i64 %a) nounwind {
+; RV64IB-LABEL: bmatflip64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmatflip a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmatflip64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmatflip a0, a0
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmatflip.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -934,6 +934,12 @@
 def : PatGprGpr;
 } // Predicates = [HasStdExtZbc]
 
+let Predicates = [HasStdExtZbm, IsRV64] in {
+def : PatGprGpr;
+def : PatGprGpr;
+def : PatGpr;
+} // Predicates = [HasStdExtZbm, IsRV64]
+
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr;
 def : PatGpr;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -89,6 +89,11 @@
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
+  // Zbm
+  def int_riscv_bmator   : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatxor  : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatflip : BitManipGPRIntrinsics;
+
   // Zbp
   def int_riscv_grev  : BitManipGPRGPRIntrinsics;
   def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
@@ -0,0 +1,45 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbm -emit-llvm %s -o - \
+// RUN: | FileCheck %s  -check-prefix=RV64ZBM
+
+// RV64ZBM-LABEL: @clmul(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:[[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP2:%.*]] = call i64 @llvm.riscv.bmator.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBM-NEXT:ret i64 [[TMP2]]
+//
+long clmul(long a, long b) {
+  return __builtin_riscv_bmator(a, b);
+}
+
+// RV64ZBM-LABEL: @clmulh(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEX

[PATCH] D101249: [RISCV] [2/2] Add IR intrinsic for Zbm extension

2021-04-25 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, jrtc27, asb, kito-cheng, Jim.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, usaxena95, s.egerton, benna, psnobl, kadircet, jocewei, PkmX, 
arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, mgorny.
LevyHsu requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang-tools-extra.

RV64 ONLY:

  bmator
  bmatxor
  bmatflip


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101249

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbm_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c

Index: clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbm %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbm %s
+
+#include 
\ No newline at end of file
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,26 @@
+/*===-- rvintrin.h -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbm)
+#include "riscv_zbm_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
\ No newline at end of file
Index: clang/lib/Headers/riscv_zbm_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbm_intrin.h
@@ -0,0 +1,44 @@
+/*=== riscv_zbm_intrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __RISCV_ZBM_INTRIN_H
+#define __RISCV_ZBM_INTRIN_H
+
+#include 
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbe RV64 ONLY
+#if __riscv_xlen == 64
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv_bmator(int64_t rs1,
+int64_t rs2) {
+  return __builtin_riscv_bmator(rs1, rs2);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv__bmatxor(int64_t rs1,
+  int64_t rs2) {
+  return __builtin_riscv_bmatxor(rs1, rs2);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv__bmatflip(int64_t rs1) {
+  return __builtin_riscv_bmatflip(rs1);
+}
+#endif // if __riscv_xlen == 64
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBM_INTRIN_H
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbm_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""},
+  {"include/riscv_zbm_intrin.h", ""},
   {"include/shaintrin.h", ""},
   {"include/smmintrin.h", ""},
   {"include/stdalign.h", ""},
Index: clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
===
--- clang-tools-extra/clang-include-fixer/find-all-sy

[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

2021-04-26 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 340705.
LevyHsu added a comment.

1. clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
  - All test cases renamed


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101248/new/

https://reviews.llvm.org/D101248

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBM
+
+declare i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+
+define i64 @bmator64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmator64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmator a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmator64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmator a0, a0, a1
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+
+define i64 @bmatxor64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmatxor64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmatxor a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmatxor64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmatxor a0, a0, a1
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatflip.i64(i64 %a)
+
+define i64 @bmatflip64(i64 %a) nounwind {
+; RV64IB-LABEL: bmatflip64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmatflip a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmatflip64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmatflip a0, a0
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmatflip.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -934,6 +934,12 @@
 def : PatGprGpr;
 } // Predicates = [HasStdExtZbc]
 
+let Predicates = [HasStdExtZbm, IsRV64] in {
+def : PatGprGpr;
+def : PatGprGpr;
+def : PatGpr;
+} // Predicates = [HasStdExtZbm, IsRV64]
+
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr;
 def : PatGpr;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -89,6 +89,11 @@
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
+  // Zbm
+  def int_riscv_bmator   : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatxor  : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatflip : BitManipGPRIntrinsics;
+
   // Zbp
   def int_riscv_grev  : BitManipGPRGPRIntrinsics;
   def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
@@ -0,0 +1,45 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbm -emit-llvm %s -o - \
+// RUN: | FileCheck %s  -check-prefix=RV64ZBM
+
+// RV64ZBM-LABEL: @bmator(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:[[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP2:%.*]] = call i64 @llvm.riscv.bmator.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBM-NEXT:ret i64 [[TMP2]]
+//
+long bmator(long a, long b) {
+  return __builtin_riscv_bmator(a, b);
+}
+
+// RV64ZBM-LABEL: @bmatxor(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:[[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64Z

[PATCH] D99008: [RISCV] Add intrinsic for Zbr extension

2021-03-19 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, evandro, kito-cheng, khchen.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
LevyHsu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.

Implementation for RISC-V Zbr extension intrinsics.

RV32 / 64:

  crc32b
  crc32h
  crc32w
  crc32cb
  crc32ch
  crc32cw

RV64 Only:

  crc32d
  crc32cd


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99008

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c
  clang/test/Headers/rvintrin.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32Zbr.ll
  llvm/test/CodeGen/RISCV/rv64Zbr.ll

Index: llvm/test/CodeGen/RISCV/rv64Zbr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64Zbr.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBR
+
+declare i64 @llvm.riscv.crc32.b.i64(i64)
+
+define i64 @crc32b(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32b:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.b a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.h.i64(i64)
+
+define i64 @crc32h(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32h:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.h a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.w.i64(i64)
+
+define i64 @crc32w(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32w:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.w a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.b.i64(i64)
+
+define i64 @crc32cb(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cb:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.b a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.h.i64(i64)
+
+define i64 @crc32ch(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32ch:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.h a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.w.i64(i64)
+
+define i64 @crc32cw(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cw:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.w a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.d.i64(i64)
+
+define i64 @crc32d(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32d:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.d a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.d.i64(i64)
+
+define i64 @crc32cd(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cd:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.d a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32Zbr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32Zbr.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBR
+
+declare i32 @llvm.riscv.crc32.b.i32(i32)
+
+define i32 @crc32b(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32b:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.b a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.h.i32(i32)
+
+define i32 @crc32h(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32h:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.h a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.w.i32(i32)
+
+define i32 @crc32w(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32w:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.w a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.w.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare

[PATCH] D99008: [RISCV] Add intrinsic for Zbr extension

2021-03-19 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 332076.
Herald added subscribers: usaxena95, kadircet, arphaman, mgorny.
Herald added a project: clang-tools-extra.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99008/new/

https://reviews.llvm.org/D99008

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbr_intrin.h
  clang/lib/Headers/rvintrin.h

Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,30 @@
+/* === rvintrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+// Long is 32 bit on riscv32 and 64 bit on riscv64 according to calling convention.
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+_Static_assert(__riscv_xlen == sizeof(uint_xlen_t) * 8,
+   "uint_xlen_t is not __riscv_xlen bits long");
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbr)
+#include "riscv_zbr_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
\ No newline at end of file
Index: clang/lib/Headers/riscv_zbr_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbr_intrin.h
@@ -0,0 +1,68 @@
+/* === riscv_zbr_intrin.h --===
+*
+* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+* See https://llvm.org/LICENSE.txt for license information.
+* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+*
+*===---===
+*/
+
+#ifndef __RISCV_ZBR_INTRIN_H
+#define __RISCV_ZBR_INTRIN_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbr
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS
+_rv_crc32_b(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_b(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS
+_rv_crc32_h(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_h(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS
+_rv_crc32_w(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_w(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS
+_rv_crc32c_b(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_b(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS
+_rv_crc32c_h(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_h(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS
+_rv_crc32c_w(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_w(rs1);
+}
+
+// RV64 only intrinsics
+
+#if __riscv_xlen == 64
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS
+_rv_crc32_d(int_xlen_t rs1) {
+return __builtin_riscv_crc32_d(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS
+_rv_crc32c_d(int_xlen_t rs1) {
+return __builtin_riscv_crc32c_d(rs1);
+}
+
+#endif // if defined(__riscv64__)
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBR_INTRIN_H
\ No newline at end of file
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbr_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""},
+  {"include/riscv_zbr_intrin.h", ""},
   {"include/shaintrin.h", ""},
   {"include/smmintrin.h", ""},
   {"include/stdalign.h", ""},
Index: clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
===

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

2021-03-19 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, kito-cheng, evandro, khchen.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
LevyHsu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.

Implementation for RISC-V Zbr extension intrinsics.

head file is included in the second patch incase the name needs to be changed

RV32 / 64:

  crc32b
  crc32h
  crc32w
  crc32cb
  crc32ch
  crc32cw

RV64 Only:

  crc32d
  crc32cd


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99009

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c
  clang/test/Headers/rvintrin.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32Zbr.ll
  llvm/test/CodeGen/RISCV/rv64Zbr.ll

Index: llvm/test/CodeGen/RISCV/rv64Zbr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64Zbr.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBR
+
+declare i64 @llvm.riscv.crc32.b.i64(i64)
+
+define i64 @crc32b(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32b:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.b a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.h.i64(i64)
+
+define i64 @crc32h(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32h:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.h a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.w.i64(i64)
+
+define i64 @crc32w(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32w:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.w a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.b.i64(i64)
+
+define i64 @crc32cb(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cb:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.b a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.h.i64(i64)
+
+define i64 @crc32ch(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32ch:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.h a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.w.i64(i64)
+
+define i64 @crc32cw(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cw:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.w a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.d.i64(i64)
+
+define i64 @crc32d(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32d:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.d a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.d.i64(i64)
+
+define i64 @crc32cd(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cd:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.d a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32Zbr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32Zbr.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBR
+
+declare i32 @llvm.riscv.crc32.b.i32(i32)
+
+define i32 @crc32b(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32b:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.b a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.h.i32(i32)
+
+define i32 @crc32h(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32h:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.h a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.w.i32(i32)
+
+define i32 @crc32w(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32w:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.w a0, a0
+; RV32ZBR-NEXT:ret
+

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

2021-03-23 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 332562.
LevyHsu edited the summary of this revision.
LevyHsu added a comment.

1. Fix format issue
2. For

  SemaChecking.cpp 

now it should allow Diag to print all missing features.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99009/new/

https://reviews.llvm.org/D99009

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbr.ll
  llvm/test/CodeGen/RISCV/rv64zbr.ll

Index: llvm/test/CodeGen/RISCV/rv64zbr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbr.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBR
+
+declare i64 @llvm.riscv.crc32.b.i64(i64)
+
+define i64 @crc32b(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32b:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.b a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.h.i64(i64)
+
+define i64 @crc32h(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32h:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.h a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.w.i64(i64)
+
+define i64 @crc32w(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32w:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.w a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.b.i64(i64)
+
+define i64 @crc32cb(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cb:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.b a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.h.i64(i64)
+
+define i64 @crc32ch(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32ch:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.h a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.w.i64(i64)
+
+define i64 @crc32cw(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cw:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.w a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.d.i64(i64)
+
+define i64 @crc32d(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32d:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.d a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.d.i64(i64)
+
+define i64 @crc32cd(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cd:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.d a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbr.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBR
+
+declare i32 @llvm.riscv.crc32.b.i32(i32)
+
+define i32 @crc32b(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32b:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.b a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.h.i32(i32)
+
+define i32 @crc32h(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32h:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.h a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.w.i32(i32)
+
+define i32 @crc32w(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32w:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.w a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.w.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.b.i32(i32)
+
+define i32 @crc32cb(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32cb:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32c.b a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32c.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.h.i32(i32)
+
+define i32 @crc32ch(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32ch:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:

[PATCH] D99008: [RISCV] [2/2] Add intrinsic for Zbr extension

2021-03-23 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 332565.
LevyHsu edited the summary of this revision.
LevyHsu added a comment.

1. Format fix
2. rvintrin.c is moved to the second part of the pach


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99008/new/

https://reviews.llvm.org/D99008

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbr_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-v %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-v %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,28 @@
+/* === rvintrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+// Long is 32 bit on riscv32 and 64 bit on riscv64 according to calling 
+// convention.
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbr)
+#include "riscv_zbr_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbr_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbr_intrin.h
@@ -0,0 +1,60 @@
+/* === riscv_zbr_intrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RISCV_ZBR_INTRIN_H
+#define __RISCV_ZBR_INTRIN_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbr
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_b(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_b(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_h(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_h(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_w(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_w(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_b(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_b(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_h(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_h(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_w(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_w(rs1);
+}
+
+// RV64 only intrinsics
+
+#if __riscv_xlen == 64
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_d(int_xlen_t rs1) {
+return __builtin_riscv_crc32_d(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_d(int_xlen_t rs1) {
+return __builtin_riscv_crc32c_d(rs1);
+}
+
+#endif // if defined(__riscv64__)
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBR_INTRIN_H
\ No newline at end of file
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbr_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+

[PATCH] D99008: [RISCV] [2/2] Add intrinsic for Zbr extension

2021-03-24 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 333219.
LevyHsu added a comment.

in clang/test/Headers/rvintrin.c
RUN:   -target-feature +experimental-zbr %s


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99008/new/

https://reviews.llvm.org/D99008

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbr_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbr %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbr %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,28 @@
+/* === rvintrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+// Long is 32 bit on riscv32 and 64 bit on riscv64 according to calling 
+// convention.
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbr)
+#include "riscv_zbr_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbr_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbr_intrin.h
@@ -0,0 +1,60 @@
+/* === riscv_zbr_intrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RISCV_ZBR_INTRIN_H
+#define __RISCV_ZBR_INTRIN_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbr
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_b(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_b(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_h(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_h(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_w(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_w(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_b(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_b(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_h(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_h(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_w(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_w(rs1);
+}
+
+// RV64 only intrinsics
+
+#if __riscv_xlen == 64
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_d(int_xlen_t rs1) {
+return __builtin_riscv_crc32_d(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_d(int_xlen_t rs1) {
+return __builtin_riscv_crc32c_d(rs1);
+}
+
+#endif // if defined(__riscv64__)
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBR_INTRIN_H
\ No newline at end of file
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbr_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""}

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbr extension

2021-03-25 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, jrtc27, kito-cheng.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, usaxena95, s.egerton, Jim, benna, psnobl, kadircet, jocewei, 
PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, mgorny.
LevyHsu requested review of this revision.
Herald added a subscriber: cfe-commits.
Herald added a project: clang-tools-extra.

Implementation for RISC-V Zbb extension intrinsic.

Head files are included in the second patch in case the name needs to be 
changed.

RV32 / 64:
orc.b


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99319

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbb_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbb %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbb %s
+
+#include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3395,13 +3395,28 @@
  CallExpr *TheCall) {
   // CodeGenFunction can also detect this, but this gives a better error
   // message.
+  bool miss_feature_error = false;
+  SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  if (Features.find("experimental-v") != StringRef::npos &&
-  !TI.hasFeature("experimental-v"))
-return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v)
-   << TheCall->getSourceRange();
-
-  return false;
+  StringRef(Features).split(ReqFeatures, ',');
+  
+  // Check if each required feature is included in TargetInfo
+  for (size_t i = 0; i < ReqFeatures.size(); i++) {
+if (!TI.hasFeature(ReqFeatures[i])) {
+  
+  // Make message like "experimental-zbr" to "Zbr"
+  ReqFeatures[i].consume_front("experimental-");
+  std::string FeatureStr = ReqFeatures[i].str();
+  FeatureStr[0] = std::toupper(FeatureStr[0]);
+  
+  // Error message
+  miss_feature_error = true;
+  Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
+  << TheCall->getSourceRange() << StringRef(FeatureStr);
+}
+  }
+
+  return miss_feature_error;
 }
 
 bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,28 @@
+/* === rvintrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+// Long is 32 bit on riscv32 and 64 bit on riscv64 according to calling 
+// convention.
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbb)
+#include "riscv_zbb_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbb_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbb_intrin.h
@@ -0,0 +1,26 @@
+/* === riscv_zbb_intrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RISCV_ZBB_INTRIN_H
+#define __RISCV_ZBB_INTRIN_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbb
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) {
+  return __builtin_riscv_orc_b(rs1);
+}
+
+#if defined(__cplusplus)

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

2021-03-25 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, jrtc27, kito-cheng.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
LevyHsu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.

Implementation for RISC-V Zbb extension intrinsic.

Head files are included in the second patch in case the name needs to be 
changed.

RV32 / 64:
orc.b


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99320

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBB
+
+declare i64 @llvm.riscv.orc.b.i64(i64)
+
+define i64 @orcb(i64 %a) nounwind {
+; RV64IB-LABEL: orcb:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:orc.b a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBB-LABEL: orcb:
+; RV64IBB:   # %bb.0:
+; RV64IBB-NEXT:orc.b a0, a0
+; RV64IBB-NEXT:ret
+  %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb(i32 %a) nounwind {
+; RV32IB-LABEL: orcb:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:orc.b a0, a0
+; RV32IB-NEXT:ret
+;
+; RV32IBB-LABEL: orcb:
+; RV32IBB:   # %bb.0:
+; RV32IBB-NEXT:orc.b a0, a0
+; RV32IBB-NEXT:ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -874,3 +874,7 @@
(SRLIWPat GPR:$rs1, (i64 16,
   (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr;
+} // Predicates = [HasStdExtZbb]
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -825,6 +825,8 @@
 
 /// Generic pattern classes
 
+class PatGpr
+: Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
 class PatGprGpr
 : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 class PatGprSimm12
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -10,6 +10,20 @@
 //
 //===--===//
 
+//===--===//
+// RISC-V Bitmanip (Bit Manipulation) Extension
+// Zbb extension part
+
+let TargetPrefix = "riscv" in {
+  
+class BitMan_GPR_Intrinsics
+: Intrinsic<[llvm_any_ty], [llvm_any_ty],
+[IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+  
+def int_riscv_orc_b : BitMan_GPR_Intrinsics;
+
+} // TargetPrefix = "riscv"
+
 //===--===//
 // Atomics
 
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -0,0 +1,15 @@
+// NOTE: Assertions have been autogenerated by utils/updat

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

2021-03-29 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 333798.
LevyHsu added a comment.

1. Generated with git format-patch -o patches/ -2 HEAD -U99
2. clang/lib/Sema/SemaChecking.cpp
  - Rewrote CheckRISCVBuiltinFunctionCall
3. clang/lib/CodeGen/CGBuiltin.cpp
  - IntrinsicTypes = {ResultType};
4. llvm/include/llvm/IR/IntrinsicsRISCV.td
  - The second llvm_any_ty has been changed to LLVMMatchType<0>
5. clang/lib/Headers/riscv_zbb_intrin.h
  - Added corresponding 32/64 orcb
6. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  - ANY_EXTEND both op0 and op 0 then truncate back to i32 when orc32b under 
RV64
7. llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll 
llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll 
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c 
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  - Added corresponding testcases.




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99320/new/

https://reviews.llvm.org/D99320

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb32(i32 %a) nounwind {
+; RV64IB-LABEL: orcb32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:orc.b a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBB-LABEL: orcb32:
+; RV64IBB:   # %bb.0:
+; RV64IBB-NEXT:orc.b a0, a0
+; RV64IBB-NEXT:ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.orc.b.i64(i64)
+
+define i64 @orcb64(i64 %a) nounwind {
+; RV64IB-LABEL: orcb64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:orc.b a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBB-LABEL: orcb64:
+; RV64IBB:   # %bb.0:
+; RV64IBB-NEXT:orc.b a0, a0
+; RV64IBB-NEXT:ret
+  %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb(i32 %a) nounwind {
+; RV32IB-LABEL: orcb:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:orc.b a0, a0
+; RV32IB-NEXT:ret
+;
+; RV32IBB-LABEL: orcb:
+; RV32IBB:   # %bb.0:
+; RV32IBB-NEXT:orc.b a0, a0
+; RV32IBB-NEXT:ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -897,3 +897,7 @@
(srl (and GPR:$rs1, 0x), (i64 16,
   (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr;
+} // Predicates = [HasStdExtZbb]
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -831,6 +831,8 @@
 
 /// Generic pattern classes
 
+class PatGpr
+: Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
 class PatGprGpr
 : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 class PatGprSimm12
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -198,6 +198,9 @@
 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
   }
 
+  if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
+setOperationAction(ISD::INTRINSIC_WO_CHAI

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

2021-03-29 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 333801.
LevyHsu added a comment.

1. Generated with git format-patch -o patches/ -2 HEAD -U99
2. clang/lib/Headers/riscv_zbb_intrin.h
  - Added corresponding 32/64 orcb intrinsic
  - include error message when user include this file directly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99319/new/

https://reviews.llvm.org/D99319

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbb_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbb %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbb %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,28 @@
+/* === rvintrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+// Long is 32 bit on riscv32 and 64 bit on riscv64 according to calling 
+// convention.
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbb)
+#include "riscv_zbb_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbb_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbb_intrin.h
@@ -0,0 +1,40 @@
+/* === riscv_zbb_intrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H  
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __RISCV_ZBB_INTRIN_H
+#define __RISCV_ZBB_INTRIN_H
+
+#include 
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbb
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) {
+  return __builtin_riscv_orc_b(rs1);
+}
+
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv32_orc_b(int32_t rs1) {
+  return __builtin_riscv32_orc_b(rs1);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv64_orc_b(int64_t rs1) {
+  return __builtin_riscv64_orc_b(rs1);
+}
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBB_INTRIN_H
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbb_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""},
+  {"include/riscv_zbb_intrin.h", ""},
   {"include/shaintrin.h", ""},
   {"include/smmintrin.h", ""},
   {"include/stdalign.h", ""},
Index: clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

2021-03-30 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 334072.
LevyHsu added a comment.

1. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  - Fixed mishandling on op0
2. clang/include/clang/Basic/BuiltinsRISCV.def clang/lib/CodeGen/CGBuiltin.cpp
  - Reduce port to 2 versions for 32/64 only.
3. clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c 
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  - Remove extra tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99320/new/

https://reviews.llvm.org/D99320

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb32(i32 %a) nounwind {
+; RV64IB-LABEL: orcb32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:orc.b a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBB-LABEL: orcb32:
+; RV64IBB:   # %bb.0:
+; RV64IBB-NEXT:orc.b a0, a0
+; RV64IBB-NEXT:ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.orc.b.i64(i64)
+
+define i64 @orcb64(i64 %a) nounwind {
+; RV64IB-LABEL: orcb64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:orc.b a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBB-LABEL: orcb64:
+; RV64IBB:   # %bb.0:
+; RV64IBB-NEXT:orc.b a0, a0
+; RV64IBB-NEXT:ret
+  %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb(i32 %a) nounwind {
+; RV32IB-LABEL: orcb:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:orc.b a0, a0
+; RV32IB-NEXT:ret
+;
+; RV32IBB-LABEL: orcb:
+; RV32IBB:   # %bb.0:
+; RV32IBB-NEXT:orc.b a0, a0
+; RV32IBB-NEXT:ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -897,3 +897,7 @@
(srl (and GPR:$rs1, 0x), (i64 16,
   (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr;
+} // Predicates = [HasStdExtZbb]
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -831,6 +831,8 @@
 
 /// Generic pattern classes
 
+class PatGpr
+: Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
 class PatGprGpr
 : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 class PatGprSimm12
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -198,6 +198,9 @@
 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
   }
 
+  if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
+setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
+
   if (Subtarget.is64Bit()) {
 setOperationAction(ISD::ADD, MVT::i32, Custom);
 setOperationAction(ISD::SUB, MVT::i32, Custom);
@@ -4168,6 +4171,14 @@
 default:
   llvm_unreachable(
   "Don't know how to custom type legalize this intrinsic!");
+case Intrinsic::riscv_orc_b: {
+  SDValue Newop1 =
+  DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

2021-03-30 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 334073.
LevyHsu added a comment.

1. clang/lib/Headers/riscv_zbb_intrin.h
  - Remove extra ports. now orc_b handles xlen op,
  - _rv64_orc_b and _rv32_orc_b for RV64
  - _rv32_orc_b for RV32


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99319/new/

https://reviews.llvm.org/D99319

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbb_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbb %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbb %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,28 @@
+/* === rvintrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+// Long is 32 bit on riscv32 and 64 bit on riscv64 according to calling 
+// convention.
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbb)
+#include "riscv_zbb_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbb_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbb_intrin.h
@@ -0,0 +1,52 @@
+/* === riscv_zbb_intrin.h --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H  
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __RISCV_ZBB_INTRIN_H
+#define __RISCV_ZBB_INTRIN_H
+
+#include 
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbb
+
+// RV32/64 ORC_B_32
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv32_orc_b(int32_t rs1) {
+  return __builtin_riscv_orc_b_32(rs1);
+}
+
+// RV32 ORC_B
+#if __riscv_xlen == 32
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) {
+  return __builtin_riscv_orc_b_32(rs1);
+}
+#endif // if __riscv_xlen == 32
+
+// RV64 ORC_B and ORC_B_64
+#if __riscv_xlen == 64
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) {
+  return __builtin_riscv_orc_b_64(rs1);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv64_orc_b(int64_t rs1) {
+  return __builtin_riscv_orc_b_64(rs1);
+}
+#endif // if __riscv_xlen == 64
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBB_INTRIN_H
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbb_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""},
+  {"include/riscv_zbb_i

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

2021-03-30 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 334322.
LevyHsu added a comment.

1. clang/lib/Sema/SemaChecking.cpp
  - Fixed var name & loop
2. clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  - renamed function


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99320/new/

https://reviews.llvm.org/D99320

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb32(i32 %a) nounwind {
+; RV64IB-LABEL: orcb32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:orc.b a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBB-LABEL: orcb32:
+; RV64IBB:   # %bb.0:
+; RV64IBB-NEXT:orc.b a0, a0
+; RV64IBB-NEXT:ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.orc.b.i64(i64)
+
+define i64 @orcb64(i64 %a) nounwind {
+; RV64IB-LABEL: orcb64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:orc.b a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBB-LABEL: orcb64:
+; RV64IBB:   # %bb.0:
+; RV64IBB-NEXT:orc.b a0, a0
+; RV64IBB-NEXT:ret
+  %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb(i32 %a) nounwind {
+; RV32IB-LABEL: orcb:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:orc.b a0, a0
+; RV32IB-NEXT:ret
+;
+; RV32IBB-LABEL: orcb:
+; RV32IBB:   # %bb.0:
+; RV32IBB-NEXT:orc.b a0, a0
+; RV32IBB-NEXT:ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -897,3 +897,7 @@
(srl (and GPR:$rs1, 0x), (i64 16,
   (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr;
+} // Predicates = [HasStdExtZbb]
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -831,6 +831,8 @@
 
 /// Generic pattern classes
 
+class PatGpr
+: Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
 class PatGprGpr
 : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 class PatGprSimm12
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -198,6 +198,9 @@
 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
   }
 
+  if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
+setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
+
   if (Subtarget.is64Bit()) {
 setOperationAction(ISD::ADD, MVT::i32, Custom);
 setOperationAction(ISD::SUB, MVT::i32, Custom);
@@ -4168,6 +4171,14 @@
 default:
   llvm_unreachable(
   "Don't know how to custom type legalize this intrinsic!");
+case Intrinsic::riscv_orc_b: {
+  SDValue Newop1 =
+  DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+  SDValue Res = 
+  DAG.getNode(N->getOpcode(), DL, MVT::i64, N->getOperand(0), Newop1);
+  Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+  return;
+}

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

2021-03-30 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 334328.
LevyHsu added a comment.

1. clang/lib/Headers/riscv_zbb_intrin.h
  - Fixed llvm header and other style issues.
2. clang/lib/Headers/rvintrin.h
  - Fixed llvm header and other style issues.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99319/new/

https://reviews.llvm.org/D99319

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbb_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbb %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbb %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,26 @@
+/*=== rvintrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbb)
+#include "riscv_zbb_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbb_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbb_intrin.h
@@ -0,0 +1,52 @@
+/*=== riscv_zbb_intrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __RISCV_ZBB_INTRIN_H
+#define __RISCV_ZBB_INTRIN_H
+
+#include 
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbb
+
+// RV32/64 ORC_B_32
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv32_orc_b(int32_t rs1) {
+  return __builtin_riscv_orc_b_32(rs1);
+}
+
+// RV32 ORC_B
+#if __riscv_xlen == 32
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) {
+  return __builtin_riscv_orc_b_32(rs1);
+}
+#endif // if __riscv_xlen == 32
+
+// RV64 ORC_B and ORC_B_64
+#if __riscv_xlen == 64
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) {
+  return __builtin_riscv_orc_b_64(rs1);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv64_orc_b(int64_t rs1) {
+  return __builtin_riscv_orc_b_64(rs1);
+}
+#endif // if __riscv_xlen == 64
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBB_INTRIN_H
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbb_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""},
+  {"include/riscv_zbb_intrin.h", ""},
   {"include/shaintrin.h", ""},
   {"include/smmintrin.h", ""},
   {"include/stdalign.h", ""},
Index: clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
===
--- clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
+++ clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
@@ -57,6 +57,8 @@
   {"include/prfchwintrin.h$", ""},
   {"include/rdseedintrin.h$", ""},
   {"include/rtmintrin.h$", ""},
+  {"include/rvintrin.h$", ""},
+  {"include/riscv_zbb_intrin.h$", ""},
   {"inc

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

2021-03-30 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 334331.
LevyHsu marked 9 inline comments as done.
LevyHsu added a comment.

1. clang/lib/Sema/SemaChecking.cpp
  - Rewrite Sema::CheckRISCVBuiltinFunctionCall
  - Coding style fix
2. llvm/include/llvm/IR/IntrinsicsRISCV.td
  - BitMan_GPR_Intrinsics's op1 now matches type of op0
  - Put crc32_d directly below crc32_w.
  - Coding style fix
3. llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  - Coding style fix


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99009/new/

https://reviews.llvm.org/D99009

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbr.ll
  llvm/test/CodeGen/RISCV/rv64zbr.ll

Index: llvm/test/CodeGen/RISCV/rv64zbr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbr.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBR
+
+declare i64 @llvm.riscv.crc32.b.i64(i64)
+
+define i64 @crc32b(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32b:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.b a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.h.i64(i64)
+
+define i64 @crc32h(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32h:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.h a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.w.i64(i64)
+
+define i64 @crc32w(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32w:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.w a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.b.i64(i64)
+
+define i64 @crc32cb(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cb:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.b a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.h.i64(i64)
+
+define i64 @crc32ch(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32ch:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.h a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.w.i64(i64)
+
+define i64 @crc32cw(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cw:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.w a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.d.i64(i64)
+
+define i64 @crc32d(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32d:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32.d a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.d.i64(i64)
+
+define i64 @crc32cd(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cd:
+; RV64ZBR:   # %bb.0:
+; RV64ZBR-NEXT:crc32c.d a0, a0
+; RV64ZBR-NEXT:ret
+  %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbr.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBR
+
+declare i32 @llvm.riscv.crc32.b.i32(i32)
+
+define i32 @crc32b(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32b:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.b a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.h.i32(i32)
+
+define i32 @crc32h(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32h:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.h a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.w.i32(i32)
+
+define i32 @crc32w(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32w:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32.w a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp = call i32 @llvm.riscv.crc32.w.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.b.i32(i32)
+
+define i32 @crc32cb(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32cb:
+; RV32ZBR:   # %bb.0:
+; RV32ZBR-NEXT:crc32c.b a0, a0
+; RV32ZBR-NEXT:ret
+  %tmp

[PATCH] D99008: [RISCV] [2/2] Add intrinsic for Zbr extension

2021-03-30 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 334332.
LevyHsu added a comment.

1. clang/lib/Headers/riscv_zbr_intrin.h
  - Fix coding style issues
  - Added error messages to alert user not include this headfile directly.
2. clang/lib/Headers/rvintrin.h
  - Fix coding style issues.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99008/new/

https://reviews.llvm.org/D99008

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbr_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbr %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbr %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,26 @@
+/*===-- rvintrin.h -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbr)
+#include "riscv_zbr_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbr_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbr_intrin.h
@@ -0,0 +1,61 @@
+/*=== riscv_zbb_intrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __RISCV_ZBR_INTRIN_H
+#define __RISCV_ZBR_INTRIN_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbr
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_b(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_b(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_h(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_h(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_w(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_w(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_b(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_b(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_h(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_h(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_w(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_w(rs1);
+}
+
+// RV64 only intrinsics
+#if __riscv_xlen == 64
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32_d(int_xlen_t rs1) {
+  return __builtin_riscv_crc32_d(rs1);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_crc32c_d(int_xlen_t rs1) {
+  return __builtin_riscv_crc32c_d(rs1);
+}
+#endif // if defined(__riscv64__)
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBR_INTRIN_H
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbr_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""},
+  {"include/riscv_zbr_intrin.h", ""},
   {"include/shaintrin.h", ""},
   {"include/smmintrin.h", ""},
   {"include/stdalign.h", ""},
Index: clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
==

[PATCH] D99711: [RISCV] [2/2] Add intrinsic for Zbc extension

2021-04-01 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, kito-cheng, asb, jrtc27, Jim.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, sabuasal, 
simoncook, johnrusso, rbar, hiraditya.
LevyHsu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.

Head files are included in the second patch in case the name needs to be 
changed.

RV32 / 64:
clmul
clmulh
clmulr


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99711

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBC
+
+declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+
+define i64 @clmul64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:clmul a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBC-LABEL: clmul64:
+; RV64IBC:   # %bb.0:
+; RV64IBC-NEXT:clmul a0, a0, a1
+; RV64IBC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmul.h.i64(i64 %a, i64 %b)
+
+define i64 @clmul64h(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64h:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:clmulh a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBC-LABEL: clmul64h:
+; RV64IBC:   # %bb.0:
+; RV64IBC-NEXT:clmulh a0, a0, a1
+; RV64IBC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmul.h.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmul.r.i64(i64 %a, i64 %b)
+
+define i64 @clmul64r(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64r:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:clmulr a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBC-LABEL: clmul64r:
+; RV64IBC:   # %bb.0:
+; RV64IBC-NEXT:clmulr a0, a0, a1
+; RV64IBC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmul.r.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBC
+
+declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+
+define i32 @clmul32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:clmul a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBC-LABEL: clmul32:
+; RV32IBC:   # %bb.0:
+; RV32IBC-NEXT:clmul a0, a0, a1
+; RV32IBC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmul.h.i32(i32 %a, i32 %b)
+
+define i32 @clmul32h(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32h:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:clmulh a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBC-LABEL: clmul32h:
+; RV32IBC:   # %bb.0:
+; RV32IBC-NEXT:clmulh a0, a0, a1
+; RV32IBC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmul.h.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmul.r.i32(i32 %a, i32 %b)
+
+define i32 @clmul32r(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32r:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:clmulr a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBC-LABEL: clmul32r:
+; RV32IBC:   # %bb.0:
+; RV32IBC-NEXT:clmulr a0, a0, a1
+; RV32IBC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmul.r.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -893,3 +893,9 @@
(srl (and GPR:$rs1, 0x), (i64

[PATCH] D99712: [RISCV] [2/2] Add intrinsic for Zbc extension

2021-04-01 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, kito-cheng, asb, jrtc27, Jim.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, usaxena95, s.egerton, benna, psnobl, kadircet, jocewei, PkmX, 
arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, mgorny.
LevyHsu requested review of this revision.
Herald added a subscriber: cfe-commits.
Herald added a project: clang-tools-extra.

Head files are included in the second patch in case the name needs to be 
changed.

RV32 / 64:
clmul
clmulh
clmulr


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99712

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbc_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbc %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbc %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,26 @@
+/*=== rvintrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbc)
+#include "riscv_zbc_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbc_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbc_intrin.h
@@ -0,0 +1,38 @@
+/*=== riscv_zbc_intrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#error "Never use  directly;include  instead."
+#endif
+
+#ifndef __RISCV_ZBC_INTRIN_H
+#define __RISCV_ZBC_INTRIN_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbc
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_clmul(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_clmul(rs1, rs2);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_clmul_h(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_clmul_h(rs1, rs2);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_clmul_r(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_clmul_r(rs1, rs2);
+}
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBC_INTRIN_H
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbc_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""},
+  {"include/riscv_zbc_intrin.h", ""},
   {"include/shaintrin.h", ""},
   {"include/smmintrin.h", ""},
   {"include/stdalign.h", ""},
Index: clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
===
--- clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
+++ clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
@@ -57,6 +57,8 @@
   {"include/prfchwintrin.h$", ""},
   {"include/rdseedintrin.h$", ""},

[PATCH] D99711: [RISCV] [1/2] Add intrinsic for Zbc extension

2021-04-01 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 334882.
LevyHsu marked 2 inline comments as done.
LevyHsu added a comment.

1. clang/include/clang/Basic/BuiltinsRISCV.def clang/lib/CodeGen/CGBuiltin.cpp 
llvm/include/llvm/IR/IntrinsicsRISCV.td 
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c 
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
  - Renaming clmul_h clmul_r to clmulh clmulr

2. llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll 
llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
  - Renaming clmul.h clmul.r to clmulh clmulr


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99711/new/

https://reviews.llvm.org/D99711

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBC
+
+declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+
+define i64 @clmul64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:clmul a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBC-LABEL: clmul64:
+; RV64IBC:   # %bb.0:
+; RV64IBC-NEXT:clmul a0, a0, a1
+; RV64IBC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+
+define i64 @clmul64h(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64h:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:clmulh a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBC-LABEL: clmul64h:
+; RV64IBC:   # %bb.0:
+; RV64IBC-NEXT:clmulh a0, a0, a1
+; RV64IBC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
+
+define i64 @clmul64r(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64r:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:clmulr a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBC-LABEL: clmul64r:
+; RV64IBC:   # %bb.0:
+; RV64IBC-NEXT:clmulr a0, a0, a1
+; RV64IBC-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBC
+
+declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+
+define i32 @clmul32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:clmul a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBC-LABEL: clmul32:
+; RV32IBC:   # %bb.0:
+; RV32IBC-NEXT:clmul a0, a0, a1
+; RV32IBC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+
+define i32 @clmul32h(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32h:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:clmulh a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBC-LABEL: clmul32h:
+; RV32IBC:   # %bb.0:
+; RV32IBC-NEXT:clmulh a0, a0, a1
+; RV32IBC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
+
+define i32 @clmul32r(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32r:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:clmulr a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBC-LABEL: clmul32r:
+; RV32IBC:   # %bb.0:
+; RV32IBC-NEXT:clmulr a0, a0, a1
+; RV32IBC-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -893,3 +893,9 @@
(srl (and GPR:$rs1, 0x), (i64 16,
   (PACKUW GPR:$rs1, G

[PATCH] D99712: [RISCV] [2/2] Add intrinsic for Zbc extension

2021-04-01 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 334883.
LevyHsu added a comment.

1. clang/lib/Headers/riscv_zbc_intrin.h
  - Renaming clmul_h clmul_r to clmulh clmulr


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99712/new/

https://reviews.llvm.org/D99712

Files:
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbc_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/Headers/rvintrin.c

Index: clang/test/Headers/rvintrin.c
===
--- /dev/null
+++ clang/test/Headers/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbc %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbc %s
+
+#include 
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,26 @@
+/*=== rvintrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbc)
+#include "riscv_zbc_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbc_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbc_intrin.h
@@ -0,0 +1,38 @@
+/*=== riscv_zbc_intrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#error "Never use  directly;include  instead."
+#endif
+
+#ifndef __RISCV_ZBC_INTRIN_H
+#define __RISCV_ZBC_INTRIN_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbc
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_clmul(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_clmul(rs1, rs2);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_clmulh(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_clmulh(rs1, rs2);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_clmulr(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_clmulr(rs1, rs2);
+}
+
+#if defined(__cplusplus)
+}
+#endif // if defined(__cplusplus)
+
+#endif // __RISCV_ZBC_INTRIN_H
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -97,6 +97,8 @@
   ptwriteintrin.h
   rdseedintrin.h
   rtmintrin.h
+  rvintrin.h
+  riscv_zbc_intrin.h
   serializeintrin.h
   sgxintrin.h
   s390intrin.h
Index: clang-tools-extra/clangd/index/CanonicalIncludes.cpp
===
--- clang-tools-extra/clangd/index/CanonicalIncludes.cpp
+++ clang-tools-extra/clangd/index/CanonicalIncludes.cpp
@@ -152,6 +152,8 @@
   {"include/prfchwintrin.h", ""},
   {"include/rdseedintrin.h", ""},
   {"include/rtmintrin.h", ""},
+  {"include/rvintrin.h", ""},
+  {"include/riscv_zbc_intrin.h", ""},
   {"include/shaintrin.h", ""},
   {"include/smmintrin.h", ""},
   {"include/stdalign.h", ""},
Index: clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
===
--- clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
+++ clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
@@ -57,6 +57,8 @@
   {"include/prfchwintrin.h$", ""},
   {"include/rdseedintrin.h$", ""},
   {"include/rtmintrin.h$", ""},
+  {"include/rvintrin.h$", ""},
+  {"include/riscv_zbc_intrin.h$", ""},
   {"include/shaintrin.h$", ""},
   {"include/smmintrin.h$", ""},
   {"include/stdalign.h$", ""},
___
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[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

2021-04-20 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, jrtc27, kito-cheng, asb, Jim.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, sabuasal, 
simoncook, johnrusso, rbar, hiraditya.
LevyHsu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.

RV32/64:

  grev
  grevi
  gorc
  gorci
  shfl
  shfli
  unshfl
  unshfli

RV64 ONLY:

  grevw
  greviw
  gorcw
  gorciw
  shflw
  shfli (For non-existing shfliw)
  unshfli   (For non-existing unshfliw)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100830

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  llvm/test/MC/RISCV/rv32b-aliases-valid.s
  llvm/test/MC/RISCV/rv64b-aliases-valid.s

Index: llvm/test/MC/RISCV/rv64b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv64b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv64b-aliases-valid.s
@@ -338,3 +338,27 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 29
+# CHECK-S-OBJ: grevi t0, t1, 29
+grev x5, x6, 29
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 29
+# CHECK-S-OBJ: gorci t0, t1, 29
+gorc x5, x6, 29
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 29
+# CHECK-S-OBJ: shfli t0, t1, 29
+shfl x5, x6, 29
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 29
+# CHECK-S-OBJ: unshfli t0, t1, 29
+unshfl x5, x6, 29
+
+# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 29
+# CHECK-S-OBJ: greviw t0, t1, 29
+grevw x5, x6, 29
+
+# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 29
+# CHECK-S-OBJ: gorciw t0, t1, 29
+gorcw x5, x6, 29
Index: llvm/test/MC/RISCV/rv32b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv32b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv32b-aliases-valid.s
@@ -242,3 +242,19 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 29
+# CHECK-S-OBJ: grevi t0, t1, 29
+grev x5, x6, 29
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 29
+# CHECK-S-OBJ: gorci t0, t1, 29
+gorc x5, x6, 29
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 29
+# CHECK-S-OBJ: shfli t0, t1, 29
+shfl x5, x6, 29
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 29
+# CHECK-S-OBJ: unshfli t0, t1, 29
+unshfl x5, x6, 29
Index: llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
@@ -0,0 +1,325 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBP
+
+declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+
+define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: grev32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:grevw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grev32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:grevw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.grevi.i32(i32 %a)
+
+define signext i32 @grevi32(i32 signext %a) nounwind {
+; RV64IB-LABEL: grevi32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:greviw a0, a0, 29
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grevi32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:greviw a0, a0, 29
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 29)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+
+define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: gorc32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorcw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorc32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorcw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorci.i32(i32 %a)
+
+define signext i32 @gorci32(i32 signext %a) nounwind {
+; RV64IB-LABEL: gorci32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorciw a0, a0, 29
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorci32:
+; RV64IBP:   # %bb.0:
+;

[PATCH] D100831: [RISCV] [2/2] Add intrinsic for Zbp extension

2021-04-20 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, jrtc27, kito-cheng, asb, Jim.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, usaxena95, s.egerton, benna, psnobl, kadircet, jocewei, PkmX, 
arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, mgorny.
LevyHsu requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang-tools-extra.

RV32/64:

  grev
  grevi
  gorc
  gorci
  shfl
  shfli
  unshfl
  unshfli

RV64 ONLY:

  grevw
  greviw
  gorcw
  gorciw
  shflw
  shfli (For non-existing shfliw)
  unshfli   (For non-existing unshfliw)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100831

Files:
  .gitignore
  clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
  clang-tools-extra/clangd/index/CanonicalIncludes.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_zbp_intrin.h
  clang/lib/Headers/rvintrin.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c

Index: clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/rvintrin.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbp %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-zbp %s
+
+#include 
\ No newline at end of file
Index: clang/lib/Headers/rvintrin.h
===
--- /dev/null
+++ clang/lib/Headers/rvintrin.h
@@ -0,0 +1,26 @@
+/*===-- rvintrin.h -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#define __RVINTRIN_H
+
+#define int_xlen_t long
+#define uint_xlen_t unsigned int_xlen_t
+
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __artificial__, __nodebug__))
+
+#if defined(__riscv_zbp)
+#include "riscv_zbp_intrin.h"
+#endif
+
+#undef __DEFAULT_FN_ATTRS
+#undef uint_xlen_t
+#undef int_xlen_t
+#endif // __RVINTRIN_H
Index: clang/lib/Headers/riscv_zbp_intrin.h
===
--- /dev/null
+++ clang/lib/Headers/riscv_zbp_intrin.h
@@ -0,0 +1,79 @@
+/*=== riscv_zbp_intrin.h ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RVINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __RISCV_ZBP_INTRIN_H
+#define __RISCV_ZBP_INTRIN_H
+
+#include 
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Zbp
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv_grev_32(int32_t rs1, int32_t rs2) {
+  return __builtin_riscv_grev_32(rs1, rs2);
+}
+
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv_gorc_32(int32_t rs1, int32_t rs2) {
+  return __builtin_riscv_gorc_32(rs1, rs2);
+}
+
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv_shfl_32(int32_t rs1, int32_t rs2) {
+  return __builtin_riscv_shfl_32(rs1, rs2);
+}
+
+static __inline__ int32_t __DEFAULT_FN_ATTRS _rv_unshfl_32(int32_t rs1, int32_t rs2) {
+  return __builtin_riscv_unshfl_32(rs1, rs2);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_xperm_n(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_xperm_n(rs1, rs2);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_xperm_b(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_xperm_b(rs1, rs2);
+}
+
+static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_xperm_h(int_xlen_t rs1, int_xlen_t rs2) {
+  return __builtin_riscv_xperm_h(rs1, rs2);
+}
+
+// RV64 ONLY
+#if __riscv_xlen == 64
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv_grev_64(int64_t rs1, int64_t rs2) {
+  return __builtin_riscv_grev_64(rs1, rs2);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv_gorc_64(int64_t rs1, int64_t rs2) {
+  return __builtin_riscv_gorc_64(rs1, rs2);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv_shfl_64(int64_t rs1, int64_t rs2) {
+  return __builtin_riscv_shfl_64(rs1, rs2);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv_unshfl_64(int64_t rs1, int64_t rs2) {
+  return __builtin_riscv_unshfl_64(rs1, rs2);
+}
+
+static __inline__ int64_t __DEFAULT_FN_ATTRS _rv_xperm_w(int6

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

2021-04-20 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 339086.
LevyHsu added a comment.

Change Log:

1. llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  - Aligned SDNode def for shflw/unshfl/unshflw
  - Reordered def : PatGprImm;
  - Merged Pat def when Predicates = [HasStdExtZbp]

2. llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll 
llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll 
llvm/test/MC/RISCV/rv32b-aliases-valid.s 
llvm/test/MC/RISCV/rv64b-aliases-valid.s
  - Replaced all imm from 29 to 4


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100830/new/

https://reviews.llvm.org/D100830

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  llvm/test/MC/RISCV/rv32b-aliases-valid.s
  llvm/test/MC/RISCV/rv64b-aliases-valid.s

Index: llvm/test/MC/RISCV/rv64b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv64b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv64b-aliases-valid.s
@@ -338,3 +338,27 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: grevi t0, t1, 4
+grev x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
+# CHECK-S-OBJ: gorci t0, t1, 4
+gorc x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
+# CHECK-S-OBJ: shfli t0, t1, 4
+shfl x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
+# CHECK-S-OBJ: unshfli t0, t1, 4
+unshfl x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 4
+# CHECK-S-OBJ: greviw t0, t1, 4
+grevw x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 4
+# CHECK-S-OBJ: gorciw t0, t1, 4
+gorcw x5, x6, 4
Index: llvm/test/MC/RISCV/rv32b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv32b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv32b-aliases-valid.s
@@ -242,3 +242,19 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: grevi t0, t1, 4
+grev x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
+# CHECK-S-OBJ: gorci t0, t1, 4
+gorc x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
+# CHECK-S-OBJ: shfli t0, t1, 4
+shfl x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
+# CHECK-S-OBJ: unshfli t0, t1, 4
+unshfl x5, x6, 4
Index: llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
@@ -0,0 +1,325 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBP
+
+declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+
+define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: grev32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:grevw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grev32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:grevw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.grevi.i32(i32 %a)
+
+define signext i32 @grevi32(i32 signext %a) nounwind {
+; RV64IB-LABEL: grevi32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:greviw a0, a0, 4
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grevi32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:greviw a0, a0, 4
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+
+define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: gorc32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorcw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorc32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorcw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorci.i32(i32 %a)
+
+define signext i32 @gorci32(i32 signext %a) nounwind {
+; RV64IB-LABEL: gorci32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorciw a0, a0, 4
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorci32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorciw a0, a0, 4
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
+
+define signext i32 @shfl32(

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

2021-04-20 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 339105.
LevyHsu marked 6 inline comments as done.
LevyHsu added a comment.

1. clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c 
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c 
llvm/test/MC/RISCV/rv32b-aliases-valid.s 
llvm/test/MC/RISCV/rv64b-aliases-valid.s 
llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll 
llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  - Changed imm in testcase to 13 so it's 4bit 1101 and won't be lower to other 
instructions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100830/new/

https://reviews.llvm.org/D100830

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  llvm/test/MC/RISCV/rv32b-aliases-valid.s
  llvm/test/MC/RISCV/rv64b-aliases-valid.s

Index: llvm/test/MC/RISCV/rv64b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv64b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv64b-aliases-valid.s
@@ -338,3 +338,27 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
+# CHECK-S-OBJ: grevi t0, t1, 13
+grev x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
+# CHECK-S-OBJ: gorci t0, t1, 13
+gorc x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
+# CHECK-S-OBJ: shfli t0, t1, 13
+shfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
+# CHECK-S-OBJ: unshfli t0, t1, 13
+unshfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 13
+# CHECK-S-OBJ: greviw t0, t1, 13
+grevw x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13
+# CHECK-S-OBJ: gorciw t0, t1, 13
+gorcw x5, x6, 13
Index: llvm/test/MC/RISCV/rv32b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv32b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv32b-aliases-valid.s
@@ -242,3 +242,19 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
+# CHECK-S-OBJ: grevi t0, t1, 13
+grev x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
+# CHECK-S-OBJ: gorci t0, t1, 13
+gorc x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
+# CHECK-S-OBJ: shfli t0, t1, 13
+shfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
+# CHECK-S-OBJ: unshfli t0, t1, 13
+unshfl x5, x6, 13
Index: llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
@@ -0,0 +1,325 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBP
+
+declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+
+define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: grev32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:grevw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grev32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:grevw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.grevi.i32(i32 %a)
+
+define signext i32 @grevi32(i32 signext %a) nounwind {
+; RV64IB-LABEL: grevi32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:greviw a0, a0, 13
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grevi32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:greviw a0, a0, 13
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+
+define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: gorc32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorcw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorc32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorcw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorci.i32(i32 %a)
+
+define signext i32 @gorci32(i32 signext %a) nounwind {
+; RV64IB-LABEL: gorci32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorciw a0, a0, 13
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorci32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorciw a0, a0, 13
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.r

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

2021-04-21 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 339138.
LevyHsu added a comment.

1. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  - Fix format issue with clang-format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100830/new/

https://reviews.llvm.org/D100830

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  llvm/test/MC/RISCV/rv32b-aliases-valid.s
  llvm/test/MC/RISCV/rv64b-aliases-valid.s

Index: llvm/test/MC/RISCV/rv64b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv64b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv64b-aliases-valid.s
@@ -338,3 +338,27 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
+# CHECK-S-OBJ: grevi t0, t1, 13
+grev x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
+# CHECK-S-OBJ: gorci t0, t1, 13
+gorc x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
+# CHECK-S-OBJ: shfli t0, t1, 13
+shfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
+# CHECK-S-OBJ: unshfli t0, t1, 13
+unshfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 13
+# CHECK-S-OBJ: greviw t0, t1, 13
+grevw x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13
+# CHECK-S-OBJ: gorciw t0, t1, 13
+gorcw x5, x6, 13
Index: llvm/test/MC/RISCV/rv32b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv32b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv32b-aliases-valid.s
@@ -242,3 +242,19 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
+# CHECK-S-OBJ: grevi t0, t1, 13
+grev x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
+# CHECK-S-OBJ: gorci t0, t1, 13
+gorc x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
+# CHECK-S-OBJ: shfli t0, t1, 13
+shfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
+# CHECK-S-OBJ: unshfli t0, t1, 13
+unshfl x5, x6, 13
Index: llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
@@ -0,0 +1,325 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBP
+
+declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+
+define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: grev32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:grevw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grev32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:grevw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.grevi.i32(i32 %a)
+
+define signext i32 @grevi32(i32 signext %a) nounwind {
+; RV64IB-LABEL: grevi32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:greviw a0, a0, 13
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grevi32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:greviw a0, a0, 13
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+
+define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: gorc32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorcw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorc32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorcw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorci.i32(i32 %a)
+
+define signext i32 @gorci32(i32 signext %a) nounwind {
+; RV64IB-LABEL: gorci32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorciw a0, a0, 13
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorci32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorciw a0, a0, 13
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
+
+define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: shfl32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:shflw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: shfl32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:shflw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp =

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

2021-04-21 Thread LevyHsu via Phabricator via cfe-commits

LevyHsu updated this revision to Diff 339150.
LevyHsu added a comment.

Fix format in RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100830/new/

https://reviews.llvm.org/D100830

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  llvm/test/MC/RISCV/rv32b-aliases-valid.s
  llvm/test/MC/RISCV/rv64b-aliases-valid.s

Index: llvm/test/MC/RISCV/rv64b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv64b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv64b-aliases-valid.s
@@ -338,3 +338,27 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
+# CHECK-S-OBJ: grevi t0, t1, 13
+grev x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
+# CHECK-S-OBJ: gorci t0, t1, 13
+gorc x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
+# CHECK-S-OBJ: shfli t0, t1, 13
+shfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
+# CHECK-S-OBJ: unshfli t0, t1, 13
+unshfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 13
+# CHECK-S-OBJ: greviw t0, t1, 13
+grevw x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13
+# CHECK-S-OBJ: gorciw t0, t1, 13
+gorcw x5, x6, 13
Index: llvm/test/MC/RISCV/rv32b-aliases-valid.s
===
--- llvm/test/MC/RISCV/rv32b-aliases-valid.s
+++ llvm/test/MC/RISCV/rv32b-aliases-valid.s
@@ -242,3 +242,19 @@
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
+# CHECK-S-OBJ: grevi t0, t1, 13
+grev x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
+# CHECK-S-OBJ: gorci t0, t1, 13
+gorc x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
+# CHECK-S-OBJ: shfli t0, t1, 13
+shfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
+# CHECK-S-OBJ: unshfli t0, t1, 13
+unshfl x5, x6, 13
Index: llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
@@ -0,0 +1,325 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBP
+
+declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+
+define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: grev32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:grevw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grev32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:grevw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.grevi.i32(i32 %a)
+
+define signext i32 @grevi32(i32 signext %a) nounwind {
+; RV64IB-LABEL: grevi32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:greviw a0, a0, 13
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: grevi32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:greviw a0, a0, 13
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+
+define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: gorc32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorcw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorc32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorcw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorci.i32(i32 %a)
+
+define signext i32 @gorci32(i32 signext %a) nounwind {
+; RV64IB-LABEL: gorci32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:gorciw a0, a0, 13
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: gorci32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:gorciw a0, a0, 13
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
+
+define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: shfl32:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:shflw a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBP-LABEL: shfl32:
+; RV64IBP:   # %bb.0:
+; RV64IBP-NEXT:shflw a0, a0, a1
+; RV64IBP-NEXT:ret
+  %tmp = call i32 @llvm.riscv.shfl.

[PATCH] D101143: [RISCV] [1/2] Add IR intrinsic for Zbe extension

[PATCH] D101144: [RISCV] [2/2] Add IR intrinsic for Zbe extension

[PATCH] D101143: [RISCV] [1/2] Add IR intrinsic for Zbe extension

[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

[PATCH] D101249: [RISCV] [2/2] Add IR intrinsic for Zbm extension

[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

[PATCH] D99008: [RISCV] Add intrinsic for Zbr extension

[PATCH] D99008: [RISCV] Add intrinsic for Zbr extension

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

[PATCH] D99008: [RISCV] [2/2] Add intrinsic for Zbr extension

[PATCH] D99008: [RISCV] [2/2] Add intrinsic for Zbr extension

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbr extension

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

[PATCH] D99008: [RISCV] [2/2] Add intrinsic for Zbr extension

[PATCH] D99711: [RISCV] [2/2] Add intrinsic for Zbc extension

[PATCH] D99712: [RISCV] [2/2] Add intrinsic for Zbc extension

[PATCH] D99711: [RISCV] [1/2] Add intrinsic for Zbc extension

[PATCH] D99712: [RISCV] [2/2] Add intrinsic for Zbc extension

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

[PATCH] D100831: [RISCV] [2/2] Add intrinsic for Zbp extension

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

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