LevyHsu updated this revision to Diff 333798.
LevyHsu added a comment.
1. Generated with git format-patch -o patches/ -2 HEAD -U999999
2. clang/lib/Sema/SemaChecking.cpp
- Rewrote CheckRISCVBuiltinFunctionCall
3. clang/lib/CodeGen/CGBuiltin.cpp
- IntrinsicTypes = {ResultType};
4. llvm/include/llvm/IR/IntrinsicsRISCV.td
- The second llvm_any_ty has been changed to LLVMMatchType<0>
5. clang/lib/Headers/riscv_zbb_intrin.h
- Added corresponding 32/64 orcb
6. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
- ANY_EXTEND both op0 and op 0 then truncate back to i32 when orc32b under
RV64
7. llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
- Added corresponding testcases.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D99320/new/
https://reviews.llvm.org/D99320
Files:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb32(i32 %a) nounwind {
+; RV64IB-LABEL: orcb32:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: orc.b a0, a0
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: orcb32:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: orc.b a0, a0
+; RV64IBB-NEXT: ret
+ %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.orc.b.i64(i64)
+
+define i64 @orcb64(i64 %a) nounwind {
+; RV64IB-LABEL: orcb64:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: orc.b a0, a0
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: orcb64:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: orc.b a0, a0
+; RV64IBB-NEXT: ret
+ %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb(i32 %a) nounwind {
+; RV32IB-LABEL: orcb:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: orc.b a0, a0
+; RV32IB-NEXT: ret
+;
+; RV32IBB-LABEL: orcb:
+; RV32IBB: # %bb.0:
+; RV32IBB-NEXT: orc.b a0, a0
+; RV32IBB-NEXT: ret
+ %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -897,3 +897,7 @@
(srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
(PACKUW GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr<int_riscv_orc_b, ORCB>;
+} // Predicates = [HasStdExtZbb]
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -831,6 +831,8 @@
/// Generic pattern classes
+class PatGpr<SDPatternOperator OpNode, RVInst Inst>
+ : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
class PatGprGpr<SDPatternOperator OpNode, RVInst Inst>
: Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst>
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -198,6 +198,9 @@
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}
+ if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
+
if (Subtarget.is64Bit()) {
setOperationAction(ISD::ADD, MVT::i32, Custom);
setOperationAction(ISD::SUB, MVT::i32, Custom);
@@ -4168,6 +4171,15 @@
default:
llvm_unreachable(
"Don't know how to custom type legalize this intrinsic!");
+ case Intrinsic::riscv_orc_b: {
+ SDValue LHS =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
+ SDValue RHS =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+ SDValue Res = DAG.getNode(N->getOpcode(), DL, MVT::i64, LHS, RHS);
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+ return;
+ }
case Intrinsic::riscv_vmv_x_s: {
EVT VT = N->getValueType(0);
MVT XLenVT = Subtarget.getXLenVT();
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -10,6 +10,21 @@
//
//===----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// RISC-V Bitmanip (Bit Manipulation) Extension
+// Zbb extension part
+
+let TargetPrefix = "riscv" in {
+
+ class BitMan_GPR_Intrinsics
+ : Intrinsic<[llvm_any_ty],
+ [LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+
+ def int_riscv_orc_b : BitMan_GPR_Intrinsics;
+
+} // TargetPrefix = "riscv"
+
//===----------------------------------------------------------------------===//
// Atomics
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -0,0 +1,39 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbb -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZBB
+
+// RV64ZBB-LABEL: @orcb64(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]])
+// RV64ZBB-NEXT: ret i64 [[TMP1]]
+//
+long orcb64(long a) {
+ return __builtin_riscv_orc_b(a);
+}
+
+// RV64ZBB-LABEL: @orcb32(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
+// RV64ZBB-NEXT: ret i32 [[TMP1]]
+//
+int orcb32(int a) {
+ return __builtin_riscv32_orc_b(a);
+}
+
+// RV64ZBB-LABEL: @orcb64_2(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]])
+// RV64ZBB-NEXT: ret i64 [[TMP1]]
+//
+long orcb64_2(long a) {
+ return __builtin_riscv64_orc_b(a);
+}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBB
+
+
+// RV32ZBB-LABEL: @orcb(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
+// RV32ZBB-NEXT: ret i32 [[TMP1]]
+//
+int orcb(int a) {
+ return __builtin_riscv_orc_b(a);
+}
+
+// RV32ZBB-LABEL: @orcb32(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
+// RV32ZBB-NEXT: ret i32 [[TMP1]]
+//
+int orcb32(int a) {
+ return __builtin_riscv32_orc_b(a);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===================================================================
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3415,13 +3415,29 @@
CallExpr *TheCall) {
// CodeGenFunction can also detect this, but this gives a better error
// message.
+ bool Feature_Missing = false;
+ SmallVector<StringRef> ReqFeatures;
StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- if (Features.find("experimental-v") != StringRef::npos &&
- !TI.hasFeature("experimental-v"))
- return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v)
- << TheCall->getSourceRange();
+ Features.split(ReqFeatures, ',');
- return false;
+ // Check if each required feature is included
+ for (auto &I : ReqFeatures) {
+ if (TI.hasFeature(I))
+ continue;
+ else {
+ // Make message like "experimental-zbr" to "Zbr"
+ I.consume_front("experimental-");
+ std::string FeatureStr = I.str();
+ FeatureStr[0] = std::toupper(FeatureStr[0]);
+
+ // Error message
+ Feature_Missing = true;
+ Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
+ << TheCall->getSourceRange() << StringRef(FeatureStr);
+ }
+ }
+
+ return Feature_Missing;
}
bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -17882,6 +17882,18 @@
llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
switch (BuiltinID) {
#include "clang/Basic/riscv_vector_builtin_cg.inc"
+
+ // Zbb
+ case RISCV::BI__builtin_riscv_orc_b:
+ case RISCV::BI__builtin_riscv32_orc_b:
+ case RISCV::BI__builtin_riscv64_orc_b:
+ ID = Intrinsic::riscv_orc_b;
+ IntrinsicTypes = {ResultType};
+ break;
+ default: {
+ llvm_unreachable("unexpected builtin ID");
+ return nullptr;
+ } // default
}
assert(ID != Intrinsic::not_intrinsic);
Index: clang/include/clang/Basic/DiagnosticSemaKinds.td
===================================================================
--- clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11182,7 +11182,7 @@
"calling %0 is a violation of trusted computing base '%1'">,
InGroup<DiagGroup<"tcb-enforcement">>;
-// RISC-V V-extension
-def err_riscvv_builtin_requires_v : Error<
- "builtin requires 'V' extension support to be enabled">;
+// RISC-V builtin required extension warning
+def err_riscv_builtin_requires_extension : Error<
+ "builtin requires %0 extension support to be enabled">;
} // end of sema component.
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===================================================================
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,5 +17,10 @@
#include "clang/Basic/riscv_vector_builtins.inc"
+// Zbb extension
+TARGET_BUILTIN(__builtin_riscv_orc_b, "LiLi", "nc", "experimental-zbb")
+TARGET_BUILTIN(__builtin_riscv32_orc_b, "ZiZi", "nc", "experimental-zbb")
+TARGET_BUILTIN(__builtin_riscv64_orc_b, "WiWi", "nc", "experimental-zbb")
+
#undef BUILTIN
#undef TARGET_BUILTIN
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