[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-02 Thread Kamran Yousafzai via cfe-commits 


@@ -251,6 +253,15 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to alignment/bitwidth if that is possible
+else if (getContext().getTypeSize(QTy) > Alignment &&
+ getContext().getTypeSize(QTy) > BitWidth) {
+  bool isSigned =
+  FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+  unsigned bits =

KamranYousafzai wrote:

Capitalized in the latest push.

https://github.com/llvm/llvm-project/pull/110690
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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-02 Thread Kamran Yousafzai via cfe-commits 


@@ -251,6 +253,15 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to alignment/bitwidth if that is possible
+else if (getContext().getTypeSize(QTy) > Alignment &&
+ getContext().getTypeSize(QTy) > BitWidth) {
+  bool isSigned =

KamranYousafzai wrote:

Capitalized in the latest push

https://github.com/llvm/llvm-project/pull/110690
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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-02 Thread Kamran Yousafzai via cfe-commits 


@@ -251,6 +253,15 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to alignment/bitwidth if that is possible
+else if (getContext().getTypeSize(QTy) > Alignment &&

KamranYousafzai wrote:

You are right, the latest push reflects the change suggested. It now just 
checks against size of a byte to ensure the size at the very minimum is 8 bits.

https://github.com/llvm/llvm-project/pull/110690
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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-02 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai edited 
https://github.com/llvm/llvm-project/pull/110690
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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-02 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai updated 
https://github.com/llvm/llvm-project/pull/110690

>From f1da56e337a4a2f0414fd600897addb0fa61b843 Mon Sep 17 00:00:00 2001
From: "muhammad.kamran4" 
Date: Tue, 1 Oct 2024 17:21:21 +0200
Subject: [PATCH] fixed fp calling convention for fpcc eligible structs for
 risc-v

---
 clang/lib/CodeGen/Targets/RISCV.cpp  |  7 +
 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c | 28 
 clang/test/CodeGen/RISCV/riscv64-abi.c   |  4 +--
 3 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c

diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp 
b/clang/lib/CodeGen/Targets/RISCV.cpp
index fd72fe673b9b14..ba512f51e52b81 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -251,6 +251,13 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to alignment/bitwidth if that is possible
+else if (getContext().getTypeSize(QTy) > BitWidth) {
+  bool IsSigned =
+  FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+  unsigned Bits = std::max(8U, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+  QTy = getContext().getIntTypeForBitwidth(Bits, IsSigned);
+}
 if (BitWidth == 0) {
   ZeroWidthBitFieldCount++;
   continue;
diff --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c 
b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 00..a315b409da613a
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+   const float  f0;
+   unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
+// CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 0
+// CHECK-NEXT:store float [[TMP0]], ptr [[TMP2]], align 1
+// CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:store i8 [[TMP1]], ptr [[TMP3]], align 1
+// CHECK-NEXT:[[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:[[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
+// CHECK-NEXT:[[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// CHECK-NEXT:[[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT:ret i32 [[BF_CAST]]
+//
+unsigned  func(struct S  arg)
+{
+return arg.f1;
+}
diff --git a/clang/test/CodeGen/RISCV/riscv64-abi.c 
b/clang/test/CodeGen/RISCV/riscv64-abi.c
index 021565238904e4..64c831361cb8e0 100644
--- a/clang/test/CodeGen/RISCV/riscv64-abi.c
+++ b/clang/test/CodeGen/RISCV/riscv64-abi.c
@@ -1710,7 +1710,7 @@ struct float16_int64_s f_ret_float16_int64_s(void) {
 // LP64:  entry:
 //
 // LP64F-LP64D-LABEL: define dso_local void @f_float16_int64bf_s_arg
-// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
+// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //
 void f_float16_int64bf_s_arg(struct float16_int64bf_s a) {}
@@ -1719,7 +1719,7 @@ void f_float16_int64bf_s_arg(struct float16_int64bf_s a) 
{}
 // LP64-SAME: () #[[ATTR0]] {
 // LP64:  entry:
 //
-// LP64F-LP64D-LABEL: define dso_local <{ half, i64 }> @f_ret_float16_int64bf_s
+// LP64F-LP64D-LABEL: define dso_local <{ half, i32 }> @f_ret_float16_int64bf_s
 // LP64F-LP64D-SAME: () #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //

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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-02 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai updated 
https://github.com/llvm/llvm-project/pull/110690

>From 8ca2d40d834c500fd463c6fa0d475cd9f91407c2 Mon Sep 17 00:00:00 2001
From: "muhammad.kamran4" 
Date: Tue, 1 Oct 2024 17:21:21 +0200
Subject: [PATCH] fixed fp calling convention for fpcc eligible structs for
 risc-v

---
 clang/lib/CodeGen/Targets/RISCV.cpp  |  7 +
 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c | 28 
 2 files changed, 35 insertions(+)
 create mode 100644 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c

diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp 
b/clang/lib/CodeGen/Targets/RISCV.cpp
index fd72fe673b9b14..ba512f51e52b81 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -251,6 +251,13 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to alignment/bitwidth if that is possible
+else if (getContext().getTypeSize(QTy) > BitWidth) {
+  bool IsSigned =
+  FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+  unsigned Bits = std::max(8U, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+  QTy = getContext().getIntTypeForBitwidth(Bits, IsSigned);
+}
 if (BitWidth == 0) {
   ZeroWidthBitFieldCount++;
   continue;
diff --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c 
b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 00..a315b409da613a
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+   const float  f0;
+   unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
+// CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 0
+// CHECK-NEXT:store float [[TMP0]], ptr [[TMP2]], align 1
+// CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:store i8 [[TMP1]], ptr [[TMP3]], align 1
+// CHECK-NEXT:[[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:[[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
+// CHECK-NEXT:[[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// CHECK-NEXT:[[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT:ret i32 [[BF_CAST]]
+//
+unsigned  func(struct S  arg)
+{
+return arg.f1;
+}

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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-04 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai updated 
https://github.com/llvm/llvm-project/pull/110690

>From 2a41d57df06316007868e9c9ffb2e247f02ddeb6 Mon Sep 17 00:00:00 2001
From: "muhammad.kamran4" 
Date: Tue, 1 Oct 2024 17:21:21 +0200
Subject: [PATCH] fixed fp calling convention for fpcc eligible structs for
 risc-v

---
 clang/lib/CodeGen/Targets/RISCV.cpp  |  7 +
 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c | 28 
 clang/test/CodeGen/RISCV/riscv64-abi.c   |  4 +--
 3 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c

diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp 
b/clang/lib/CodeGen/Targets/RISCV.cpp
index fd72fe673b9b14..082efefe80dbf3 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -251,6 +251,13 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to bitwidth if possible
+else if (getContext().getTypeSize(QTy) > BitWidth) {
+  bool IsSigned =
+  FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+  unsigned Bits = std::max(8U, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+  QTy = getContext().getIntTypeForBitwidth(Bits, IsSigned);
+}
 if (BitWidth == 0) {
   ZeroWidthBitFieldCount++;
   continue;
diff --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c 
b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 00..a315b409da613a
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+   const float  f0;
+   unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
+// CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 0
+// CHECK-NEXT:store float [[TMP0]], ptr [[TMP2]], align 1
+// CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:store i8 [[TMP1]], ptr [[TMP3]], align 1
+// CHECK-NEXT:[[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:[[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
+// CHECK-NEXT:[[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// CHECK-NEXT:[[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT:ret i32 [[BF_CAST]]
+//
+unsigned  func(struct S  arg)
+{
+return arg.f1;
+}
diff --git a/clang/test/CodeGen/RISCV/riscv64-abi.c 
b/clang/test/CodeGen/RISCV/riscv64-abi.c
index 021565238904e4..64c831361cb8e0 100644
--- a/clang/test/CodeGen/RISCV/riscv64-abi.c
+++ b/clang/test/CodeGen/RISCV/riscv64-abi.c
@@ -1710,7 +1710,7 @@ struct float16_int64_s f_ret_float16_int64_s(void) {
 // LP64:  entry:
 //
 // LP64F-LP64D-LABEL: define dso_local void @f_float16_int64bf_s_arg
-// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
+// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //
 void f_float16_int64bf_s_arg(struct float16_int64bf_s a) {}
@@ -1719,7 +1719,7 @@ void f_float16_int64bf_s_arg(struct float16_int64bf_s a) 
{}
 // LP64-SAME: () #[[ATTR0]] {
 // LP64:  entry:
 //
-// LP64F-LP64D-LABEL: define dso_local <{ half, i64 }> @f_ret_float16_int64bf_s
+// LP64F-LP64D-LABEL: define dso_local <{ half, i32 }> @f_ret_float16_int64bf_s
 // LP64F-LP64D-SAME: () #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //

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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-01 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai edited 
https://github.com/llvm/llvm-project/pull/110690
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[clang] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-01 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai created 
https://github.com/llvm/llvm-project/pull/110690

The code generated for calls with FPCC eligible structs as arguments doesn't 
consider the alignment with a bitfield, which results in a store crossing the 
boundary of the memory allocated using alloca, e.g.
For the code:
```
struct __attribute__((packed, aligned(1))) S {
   const float  f0;
   unsigned f1 : 1;
};
unsigned  func(struct S  arg)
{
return arg.f1;
} 
```
The generated IR is:
```
 define dso_local signext i32 @func(
 float [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
  [[ENTRY:.*:]]
[[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
[[TMP2:%.*]] = getelementptr inbounds nuw { float, i32 }, ptr [[ARG]], i32 
0, i32 0
store float [[TMP0]], ptr [[TMP2]], align 1
[[TMP3:%.*]] = getelementptr inbounds nuw { float, i32 }, ptr [[ARG]], i32 
0, i32 1
store i32 [[TMP1]], ptr [[TMP3]], align 1
[[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[ARG]], i32 0, 
i32 1
[[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
[[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
[[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
ret i32 [[BF_CAST]]
```
Where, `store i32 [[TMP1]], ptr [[TMP3]], align 1` can be seen to crossing the 
boundary of the allocated memory. If, the IR is seen after optimizations, the 
IR left is:
```
 define dso_local noundef signext i32 @func(
 float [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
  [[ENTRY:.*:]]
ret i32 0
```
The patch trims the second member of the struct after taking into consideration 
the alignment and bitwidth to decide the appropriate integer type and the test 
shows the results of this patch.

Note that the bug is seen only when `f` extension is enabled.

>From b751fd8f9a8f193a61761639ced7a839075db50c Mon Sep 17 00:00:00 2001
From: "muhammad.kamran4" 
Date: Tue, 1 Oct 2024 17:21:21 +0200
Subject: [PATCH] fixed fp calling convention for fpcc eligible structs for
 risc-v

---
 clang/lib/CodeGen/Targets/RISCV.cpp  | 11 ++
 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c | 21 
 2 files changed, 32 insertions(+)
 create mode 100644 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c

diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp 
b/clang/lib/CodeGen/Targets/RISCV.cpp
index fd72fe673b9b14..142371ffe27e54 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -224,6 +224,8 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 if (isEmptyRecord(getContext(), Ty, true, true))
   return true;
 const RecordDecl *RD = RTy->getDecl();
+const Type *RT = RD->getTypeForDecl();
+unsigned Alignment = getContext().getTypeAlign(RT);
 // Unions aren't eligible unless they're empty (which is caught above).
 if (RD->isUnion())
   return false;
@@ -251,6 +253,15 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to alignment/bitwidth if that is possible
+else if (getContext().getTypeSize(QTy) > Alignment &&
+ getContext().getTypeSize(QTy) > BitWidth) {
+  bool isSigned =
+  FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+  unsigned bits =
+  std::max(Alignment, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+  QTy = getContext().getIntTypeForBitwidth(bits, isSigned);
+}
 if (BitWidth == 0) {
   ZeroWidthBitFieldCount++;
   continue;
diff --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c 
b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 00..5d813aa05e60c6
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,21 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm -O3 %s -o - \
+// RUN:   | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+   const float  f0;
+   unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext range(i32 0, 2) i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) local_unnamed_addr 
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[BF_CLEAR:%.*]] = and i8 [[TMP1]], 1
+// CHECK-NEXT:[[BF_CAST:%.*]] = zext nneg i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT:ret i32 [[BF_CAST]]
+//
+unsigned  func(struct S  arg)
+{
+return arg.f1;
+}

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[clang] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-01 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai edited 
https://github.com/llvm/llvm-project/pull/110690
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[clang] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-01 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai updated 
https://github.com/llvm/llvm-project/pull/110690

>From 69d04c6b48f1fad94d696a1cd2be66d7438f9c4c Mon Sep 17 00:00:00 2001
From: "muhammad.kamran4" 
Date: Tue, 1 Oct 2024 17:21:21 +0200
Subject: [PATCH] fixed fp calling convention for fpcc eligible structs for
 risc-v

---
 clang/lib/CodeGen/Targets/RISCV.cpp  | 11 
 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c | 28 
 2 files changed, 39 insertions(+)
 create mode 100644 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c

diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp 
b/clang/lib/CodeGen/Targets/RISCV.cpp
index fd72fe673b9b14..142371ffe27e54 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -224,6 +224,8 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 if (isEmptyRecord(getContext(), Ty, true, true))
   return true;
 const RecordDecl *RD = RTy->getDecl();
+const Type *RT = RD->getTypeForDecl();
+unsigned Alignment = getContext().getTypeAlign(RT);
 // Unions aren't eligible unless they're empty (which is caught above).
 if (RD->isUnion())
   return false;
@@ -251,6 +253,15 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to alignment/bitwidth if that is possible
+else if (getContext().getTypeSize(QTy) > Alignment &&
+ getContext().getTypeSize(QTy) > BitWidth) {
+  bool isSigned =
+  FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+  unsigned bits =
+  std::max(Alignment, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+  QTy = getContext().getIntTypeForBitwidth(bits, isSigned);
+}
 if (BitWidth == 0) {
   ZeroWidthBitFieldCount++;
   continue;
diff --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c 
b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 00..a315b409da613a
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+   const float  f0;
+   unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
+// CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 0
+// CHECK-NEXT:store float [[TMP0]], ptr [[TMP2]], align 1
+// CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:store i8 [[TMP1]], ptr [[TMP3]], align 1
+// CHECK-NEXT:[[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:[[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
+// CHECK-NEXT:[[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// CHECK-NEXT:[[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT:ret i32 [[BF_CAST]]
+//
+unsigned  func(struct S  arg)
+{
+return arg.f1;
+}

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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-03 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai updated 
https://github.com/llvm/llvm-project/pull/110690

>From 2a41d57df06316007868e9c9ffb2e247f02ddeb6 Mon Sep 17 00:00:00 2001
From: "muhammad.kamran4" 
Date: Tue, 1 Oct 2024 17:21:21 +0200
Subject: [PATCH] fixed fp calling convention for fpcc eligible structs for
 risc-v

---
 clang/lib/CodeGen/Targets/RISCV.cpp  |  7 +
 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c | 28 
 clang/test/CodeGen/RISCV/riscv64-abi.c   |  4 +--
 3 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c

diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp 
b/clang/lib/CodeGen/Targets/RISCV.cpp
index fd72fe673b9b14..082efefe80dbf3 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -251,6 +251,13 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to bitwidth if possible
+else if (getContext().getTypeSize(QTy) > BitWidth) {
+  bool IsSigned =
+  FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+  unsigned Bits = std::max(8U, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+  QTy = getContext().getIntTypeForBitwidth(Bits, IsSigned);
+}
 if (BitWidth == 0) {
   ZeroWidthBitFieldCount++;
   continue;
diff --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c 
b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 00..a315b409da613a
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+   const float  f0;
+   unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
+// CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 0
+// CHECK-NEXT:store float [[TMP0]], ptr [[TMP2]], align 1
+// CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:store i8 [[TMP1]], ptr [[TMP3]], align 1
+// CHECK-NEXT:[[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr 
[[ARG]], i32 0, i32 1
+// CHECK-NEXT:[[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
+// CHECK-NEXT:[[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// CHECK-NEXT:[[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT:ret i32 [[BF_CAST]]
+//
+unsigned  func(struct S  arg)
+{
+return arg.f1;
+}
diff --git a/clang/test/CodeGen/RISCV/riscv64-abi.c 
b/clang/test/CodeGen/RISCV/riscv64-abi.c
index 021565238904e4..64c831361cb8e0 100644
--- a/clang/test/CodeGen/RISCV/riscv64-abi.c
+++ b/clang/test/CodeGen/RISCV/riscv64-abi.c
@@ -1710,7 +1710,7 @@ struct float16_int64_s f_ret_float16_int64_s(void) {
 // LP64:  entry:
 //
 // LP64F-LP64D-LABEL: define dso_local void @f_float16_int64bf_s_arg
-// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
+// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //
 void f_float16_int64bf_s_arg(struct float16_int64bf_s a) {}
@@ -1719,7 +1719,7 @@ void f_float16_int64bf_s_arg(struct float16_int64bf_s a) 
{}
 // LP64-SAME: () #[[ATTR0]] {
 // LP64:  entry:
 //
-// LP64F-LP64D-LABEL: define dso_local <{ half, i64 }> @f_ret_float16_int64bf_s
+// LP64F-LP64D-LABEL: define dso_local <{ half, i32 }> @f_ret_float16_int64bf_s
 // LP64F-LP64D-SAME: () #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //

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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-03 Thread Kamran Yousafzai via cfe-commits 


@@ -251,6 +251,13 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType 
Ty, CharUnits CurOff,
 // bitwidth is XLen or less.
 if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
   QTy = getContext().getIntTypeForBitwidth(XLen, false);
+// Trim type to alignment/bitwidth if that is possible

KamranYousafzai wrote:

Updated

https://github.com/llvm/llvm-project/pull/110690
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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-03 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai edited 
https://github.com/llvm/llvm-project/pull/110690
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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-10-03 Thread Kamran Yousafzai via cfe-commits 

https://github.com/KamranYousafzai edited 
https://github.com/llvm/llvm-project/pull/110690
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[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

2024-11-07 Thread Kamran Yousafzai via cfe-commits 

KamranYousafzai wrote:

Hi @asb , could you please have a look and review the proposed changes?

https://github.com/llvm/llvm-project/pull/110690
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