https://github.com/KamranYousafzai updated
https://github.com/llvm/llvm-project/pull/110690
>From 8ca2d40d834c500fd463c6fa0d475cd9f91407c2 Mon Sep 17 00:00:00 2001
From: "muhammad.kamran4" <muhammad.kam...@esperantotech.com>
Date: Tue, 1 Oct 2024 17:21:21 +0200
Subject: [PATCH] fixed fp calling convention for fpcc eligible structs for
risc-v
---
clang/lib/CodeGen/Targets/RISCV.cpp | 7 +++++
clang/test/CodeGen/RISCV/riscv-fpcc-struct.c | 28 ++++++++++++++++++++
2 files changed, 35 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp
b/clang/lib/CodeGen/Targets/RISCV.cpp
index fd72fe673b9b14..ba512f51e52b81 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -251,6 +251,13 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType
Ty, CharUnits CurOff,
// bitwidth is XLen or less.
if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
QTy = getContext().getIntTypeForBitwidth(XLen, false);
+ // Trim type to alignment/bitwidth if that is possible
+ else if (getContext().getTypeSize(QTy) > BitWidth) {
+ bool IsSigned =
+ FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+ unsigned Bits = std::max(8U, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+ QTy = getContext().getIntTypeForBitwidth(Bits, IsSigned);
+ }
if (BitWidth == 0) {
ZeroWidthBitFieldCount++;
continue;
diff --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 00000000000000..a315b409da613a
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+ const float f0;
+ unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
+// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr
[[ARG]], i32 0, i32 0
+// CHECK-NEXT: store float [[TMP0]], ptr [[TMP2]], align 1
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr
[[ARG]], i32 0, i32 1
+// CHECK-NEXT: store i8 [[TMP1]], ptr [[TMP3]], align 1
+// CHECK-NEXT: [[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr
[[ARG]], i32 0, i32 1
+// CHECK-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
+// CHECK-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// CHECK-NEXT: [[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT: ret i32 [[BF_CAST]]
+//
+unsigned func(struct S arg)
+{
+ return arg.f1;
+}
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