from:"Jim Lin via cfe\-commits"

[clang] 7ee479a - [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

2020-05-17 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2020-05-18T13:13:22+08:00
New Revision: 7ee479a760e0a4402b4eb7fb6168768a44f66945

URL: 
https://github.com/llvm/llvm-project/commit/7ee479a760e0a4402b4eb7fb6168768a44f66945
DIFF: 
https://github.com/llvm/llvm-project/commit/7ee479a760e0a4402b4eb7fb6168768a44f66945.diff

LOG: [RISCV] Fix passing two floating-point values in complex separately by two 
GPRs on RV64

Summary:
This patch fixed the error of counting the remaining FPRs. Complex 
floating-point
values should be passed by two FPRs for the hard-float ABI. If no two FPRs are
available, it should be passed via a 64-bit GPR (fp+fp). `ArgFPRsLeft` is only
decreased one while the type is complex floating-point. It causes two 
floating-point
values in the complex are passed separately by two GPRs.

Reviewers: asb, luismarques, lenary

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, 
shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, 
the_o, rkruppe, PkmX, jocewei, psnobl, benna, s.egerton, pzheng, 
sameer.abuasal, apazos, evandro, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D79770

Added: 


Modified: 
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/riscv64-lp64-abi.c
clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c

Removed: 




diff  --git a/clang/lib/CodeGen/TargetInfo.cpp 
b/clang/lib/CodeGen/TargetInfo.cpp
index 44608ea461ec..a4ca0b07da9e 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -10238,7 +10238,8 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType 
Ty, bool IsFixed,
   uint64_t Size = getContext().getTypeSize(Ty);
 
   // Pass floating point values via FPRs if possible.
-  if (IsFixed && Ty->isFloatingType() && FLen >= Size && ArgFPRsLeft) {
+  if (IsFixed && Ty->isFloatingType() && !Ty->isComplexType() &&
+  FLen >= Size && ArgFPRsLeft) {
 ArgFPRsLeft--;
 return ABIArgInfo::getDirect();
   }

diff  --git a/clang/test/CodeGen/riscv64-lp64-abi.c 
b/clang/test/CodeGen/riscv64-lp64-abi.c
index 8347056c54d3..00d8c66af155 100644
--- a/clang/test/CodeGen/riscv64-lp64-abi.c
+++ b/clang/test/CodeGen/riscv64-lp64-abi.c
@@ -30,3 +30,24 @@ struct large f_scalar_stack_2(double a, __int128_t b, long 
double c, v32i8 d,
   uint8_t e, int8_t f, uint8_t g) {
   return (struct large){a, e, f, g};
 }
+
+// Complex floating-point values or structs containing a single complex
+// floating-point value should be passed in a GPR.
+
+// CHECK: define void @f_floatcomplex(i64 %a.coerce)
+void f_floatcomplex(float __complex__ a) {}
+
+// CHECK: define i64 @f_ret_floatcomplex()
+float __complex__ f_ret_floatcomplex() {
+  return 1.0;
+}
+
+struct floatcomplex_s { float __complex__ c; };
+
+// CHECK: define void @f_floatcomplex_s_arg(i64 %a.coerce)
+void f_floatcomplex_s_arg(struct floatcomplex_s a) {}
+
+// CHECK: define i64 @f_ret_floatcomplex_s()
+struct floatcomplex_s f_ret_floatcomplex_s() {
+  return (struct floatcomplex_s){1.0};
+}

diff  --git a/clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c 
b/clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
index 9a44928cac8d..7a25cef6cadc 100644
--- a/clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
+++ b/clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
@@ -165,6 +165,35 @@ struct floatcomplex_s f_ret_floatcomplex_s() {
   return (struct floatcomplex_s){1.0};
 }
 
+// Complex floating-point values or structs containing a single complex
+// floating-point value should be passed in GPRs if no two FPRs is available.
+
+// CHECK: define void @f_floatcomplex_insufficient_fprs1(float %a.coerce0, 
float %a.coerce1, float %b.coerce0, float %b.coerce1, float %c.coerce0, float 
%c.coerce1, float %d.coerce0, float %d.coerce1, i64 %e.coerce)
+void f_floatcomplex_insufficient_fprs1(float __complex__ a, float __complex__ 
b,
+   float __complex__ c, float __complex__ 
d,
+   float __complex__ e) {}
+
+
+// CHECK: define void @f_floatcomplex_s_arg_insufficient_fprs1(float %0, float 
%1, float %2, float %3, float %4, float %5, float %6, float %7, i64 %e.coerce)
+void f_floatcomplex_s_arg_insufficient_fprs1(struct floatcomplex_s a,
+ struct floatcomplex_s b,
+ struct floatcomplex_s c,
+ struct floatcomplex_s d,
+ struct floatcomplex_s e) {}
+
+// CHECK: define void @f_floatcomplex_insufficient_fprs2(float %a, float 
%b.coerce0, float %b.coerce1, float %c.coerce0, float %c.coerce1, float 
%d.coerce0, float %d.coerce1, i64 %e.coerce)
+void f_floatcomplex_insufficient_fprs2(float a,
+   float __complex__ b, float __complex__ 
c,
+   float __co

[clang] [RISCV] Remove redundant variable Log2LMUL from vset intrinsic. NFC (PR #76422)

2023-12-26 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/76422

None

>From 460d1b9ece1fb208047a8c35088bd5dcb12279b2 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 27 Dec 2023 11:19:21 +0800
Subject: [PATCH] [RISCV] Remove redundant variable Log2LMUL for vset
 intrinsic. NFC

---
 clang/include/clang/Basic/riscv_vector.td | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/clang/include/clang/Basic/riscv_vector.td 
b/clang/include/clang/Basic/riscv_vector.td
index f2dde7f540fb74..e7d78b03511fe9 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2441,11 +2441,9 @@ let HasMasked = false, HasVL = false, IRName = "" in {
 return Builder.CreateInsertVector(ResultType, Ops[0], Ops[2], Ops[1]);
   }
   }] in {
-let Log2LMUL = [0, 1, 2] in {
-  foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", 
"(LFixedLog2LMUL:3)"] in {
-def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # 
"vKzv", "csilxfd">;
-def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul 
#"UvKzUv", "csil">;
-  }
+foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", 
"(LFixedLog2LMUL:3)"] in {
+  def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # 
"vKzv", "csilxfd">;
+  def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul 
#"UvKzUv", "csil">;
 }
 foreach nf = NFList in {
   defvar T = "(Tuple:" # nf # ")";

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[clang] [RISCV] Remove redundant variable Log2LMUL from vset intrinsic. NFC (PR #76422)

2023-12-26 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/76422
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[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

2024-01-10 Thread Jim Lin via cfe-commits



@@ -386,6 +393,11 @@ bool 
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
   if (llvm::is_contained(Features, "+experimental"))
 HasExperimental = true;
 
+  if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
+Diags.Report(diag::err_invalid_feature_combination)
+<< "ILP32E cannot be used with the D ISA extension";
+return false;
+  }

tclin914 wrote:

Does it also need to check ilp32e isn't compatible with zcmp?

https://github.com/llvm/llvm-project/pull/76777
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[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

2024-03-29 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/87095

In M68kRegisterInfo.td, register SP is defined with name sp and alternate name 
a7.

Fixes: https://github.com/llvm/llvm-project/issues/78620

>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Sat, 30 Mar 2024 01:37:49 +0800
Subject: [PATCH] [M68k] Change gcc register name from a7 to sp

In M68kRegisterInfo.td, register SP is defined with name x7 and alternate name 
a7.

Fixes: https://github.com/llvm/llvm-project/issues/78620
---
 clang/lib/Basic/Targets/M68k.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/M68k.cpp b/clang/lib/Basic/Targets/M68k.cpp
index 1b7e0a7f32c9be..9e6b59f1e42a8d 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -127,7 +127,7 @@ bool M68kTargetInfo::hasFeature(StringRef Feature) const {
 
 const char *const M68kTargetInfo::GCCRegNames[] = {
 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
+"a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
 "pc"};
 
 ArrayRef M68kTargetInfo::getGCCRegNames() const {

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[clang] [M68k][clang] Enable frame pointer optimization by default (PR #87264)

2024-04-01 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/87264

Enable frame pointer optimization by default to match it with gcc.

Fixes: https://github.com/llvm/llvm-project/issues/75013

>From 4eeb31d4ad8503db9a1cc079eeb9aa4186136719 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Sat, 30 Mar 2024 02:54:31 +0800
Subject: [PATCH] [M68k][clang] Enable frame pointer optimization by default

Enable frame pointer optimization by default to match it with gcc.

Fixes: https://github.com/llvm/llvm-project/issues/75013
---
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 1 +
 clang/test/Driver/frame-pointer-elim.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ace4fb99581e38..ae49f1906053dc 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -114,6 +114,7 @@ static bool useFramePointerForTargetByDefault(const 
llvm::opt::ArgList &Args,
   case llvm::Triple::csky:
   case llvm::Triple::loongarch32:
   case llvm::Triple::loongarch64:
+  case llvm::Triple::m68k:
 return !clang::driver::tools::areOptimizationsEnabled(Args);
   default:
 break;
diff --git a/clang/test/Driver/frame-pointer-elim.c 
b/clang/test/Driver/frame-pointer-elim.c
index 847c5b7b0b01f3..e1b0a468ab8259 100644
--- a/clang/test/Driver/frame-pointer-elim.c
+++ b/clang/test/Driver/frame-pointer-elim.c
@@ -125,6 +125,12 @@
 // RUN: %clang -### -target sparc64 -S -O1 %s 2>&1 | \
 // RUN:   FileCheck --check-prefix=KEEP-NONE %s
 
+// M68k targets omit the frame pointer when optimizations are enabled.
+// RUN: %clang -### -target m68k -S %s 2>&1 | \
+// RUN:   FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### -target m68k -S -O1 %s 2>&1 | \
+// RUN:   FileCheck --check-prefix=KEEP-NONE %s
+
 // For AAarch32 (A32, T32) linux targets, default omit frame pointer when
 // optimizations are enabled.
 // RUN: %clang -### -target arm-linux-gnueabihf- -marm -S %s 2>&1 | \

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[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

2024-04-01 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/87095

>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Sat, 30 Mar 2024 01:37:49 +0800
Subject: [PATCH 1/2] [M68k] Change gcc register name from a7 to sp

In M68kRegisterInfo.td, register SP is defined with name x7 and alternate name 
a7.

Fixes: https://github.com/llvm/llvm-project/issues/78620
---
 clang/lib/Basic/Targets/M68k.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/M68k.cpp b/clang/lib/Basic/Targets/M68k.cpp
index 1b7e0a7f32c9be..9e6b59f1e42a8d 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -127,7 +127,7 @@ bool M68kTargetInfo::hasFeature(StringRef Feature) const {
 
 const char *const M68kTargetInfo::GCCRegNames[] = {
 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
+"a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
 "pc"};
 
 ArrayRef M68kTargetInfo::getGCCRegNames() const {

>From ded6535bd84ac612f20ab116ae6690a2b5a70c0b Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Tue, 2 Apr 2024 05:06:09 +0800
Subject: [PATCH 2/2] Implement getGCCRegAliases and add testcase

Testcase is copied from
clang/test/CodeGen/LoongArch/inline-asm-gcc-regs.c.
---
 clang/lib/Basic/Targets/M68k.cpp  |   9 +-
 clang/lib/Basic/Targets/M68k.h|   1 +
 clang/test/CodeGen/M68k/inline-asm-gcc-regs.c | 134 ++
 3 files changed, 142 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGen/M68k/inline-asm-gcc-regs.c

diff --git a/clang/lib/Basic/Targets/M68k.cpp b/clang/lib/Basic/Targets/M68k.cpp
index 9e6b59f1e42a8d..94f2630d953cdc 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -134,9 +134,14 @@ ArrayRef M68kTargetInfo::getGCCRegNames() 
const {
   return llvm::ArrayRef(GCCRegNames);
 }
 
+const TargetInfo::GCCRegAlias M68kTargetInfo::GCCRegAliases[] = {
+  {{"bp"}, "a5"},
+  {{"fp"}, "a6"},
+  {{"usp", "ssp", "isp", "a7"}, "sp"},
+};
+
 ArrayRef M68kTargetInfo::getGCCRegAliases() const {
-  // No aliases.
-  return std::nullopt;
+  return llvm::ArrayRef(GCCRegAliases);
 }
 
 bool M68kTargetInfo::validateAsmConstraint(
diff --git a/clang/lib/Basic/Targets/M68k.h b/clang/lib/Basic/Targets/M68k.h
index a9c262e62fbad0..7ffa901127e504 100644
--- a/clang/lib/Basic/Targets/M68k.h
+++ b/clang/lib/Basic/Targets/M68k.h
@@ -25,6 +25,7 @@ namespace targets {
 
 class LLVM_LIBRARY_VISIBILITY M68kTargetInfo : public TargetInfo {
   static const char *const GCCRegNames[];
+  static const TargetInfo::GCCRegAlias GCCRegAliases[];
 
   enum CPUKind {
 CK_Unknown,
diff --git a/clang/test/CodeGen/M68k/inline-asm-gcc-regs.c 
b/clang/test/CodeGen/M68k/inline-asm-gcc-regs.c
new file mode 100644
index 00..40d3543d8a6f90
--- /dev/null
+++ b/clang/test/CodeGen/M68k/inline-asm-gcc-regs.c
@@ -0,0 +1,134 @@
+// RUN: %clang_cc1 -triple m68k -emit-llvm -O2 %s -o - | FileCheck %s
+
+/// Check GCC register names and alias can be used in register variable 
definition.
+
+// CHECK-LABEL: @test_d0
+// CHECK: call void asm sideeffect "", "{d0}"(i32 undef)
+void test_d0() {
+register int a asm ("d0");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d1
+// CHECK: call void asm sideeffect "", "{d1}"(i32 undef)
+void test_d1() {
+register int a asm ("d1");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d2
+// CHECK: call void asm sideeffect "", "{d2}"(i32 undef)
+void test_d2() {
+register int a asm ("d2");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d3
+// CHECK: call void asm sideeffect "", "{d3}"(i32 undef)
+void test_d3() {
+register int a asm ("d3");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d4
+// CHECK: call void asm sideeffect "", "{d4}"(i32 undef)
+void test_d4() {
+register int a asm ("d4");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d5
+// CHECK: call void asm sideeffect "", "{d5}"(i32 undef)
+void test_d5() {
+register int a asm ("d5");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d6
+// CHECK: call void asm sideeffect "", "{d6}"(i32 undef)
+void test_d6() {
+register int a asm ("d6");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d7
+// CHECK: call void asm sideeffect "", "{d7}"(i32 undef)
+void test_d7() {
+register int a asm ("d7");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_a0
+// CHECK: call void asm sideeffect "", "{a0}"(i32 undef)
+void test_a0() {
+register int a asm ("a0");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_a1
+// CHECK: call void asm sideeffect "", "{a1}"(i32 undef)
+void test_a1() {
+register int a asm ("a1");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_a2
+// CHECK: call void asm sideeffect "", "{a2}"(i32 undef)
+void test_a2() {
+register int a asm ("a2");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_a3
+/

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

2024-04-01 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/87095

>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Sat, 30 Mar 2024 01:37:49 +0800
Subject: [PATCH 1/3] [M68k] Change gcc register name from a7 to sp

In M68kRegisterInfo.td, register SP is defined with name x7 and alternate name 
a7.

Fixes: https://github.com/llvm/llvm-project/issues/78620
---
 clang/lib/Basic/Targets/M68k.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/M68k.cpp b/clang/lib/Basic/Targets/M68k.cpp
index 1b7e0a7f32c9be..9e6b59f1e42a8d 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -127,7 +127,7 @@ bool M68kTargetInfo::hasFeature(StringRef Feature) const {
 
 const char *const M68kTargetInfo::GCCRegNames[] = {
 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
+"a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
 "pc"};
 
 ArrayRef M68kTargetInfo::getGCCRegNames() const {

>From ded6535bd84ac612f20ab116ae6690a2b5a70c0b Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Tue, 2 Apr 2024 05:06:09 +0800
Subject: [PATCH 2/3] Implement getGCCRegAliases and add testcase

Testcase is copied from
clang/test/CodeGen/LoongArch/inline-asm-gcc-regs.c.
---
 clang/lib/Basic/Targets/M68k.cpp  |   9 +-
 clang/lib/Basic/Targets/M68k.h|   1 +
 clang/test/CodeGen/M68k/inline-asm-gcc-regs.c | 134 ++
 3 files changed, 142 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGen/M68k/inline-asm-gcc-regs.c

diff --git a/clang/lib/Basic/Targets/M68k.cpp b/clang/lib/Basic/Targets/M68k.cpp
index 9e6b59f1e42a8d..94f2630d953cdc 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -134,9 +134,14 @@ ArrayRef M68kTargetInfo::getGCCRegNames() 
const {
   return llvm::ArrayRef(GCCRegNames);
 }
 
+const TargetInfo::GCCRegAlias M68kTargetInfo::GCCRegAliases[] = {
+  {{"bp"}, "a5"},
+  {{"fp"}, "a6"},
+  {{"usp", "ssp", "isp", "a7"}, "sp"},
+};
+
 ArrayRef M68kTargetInfo::getGCCRegAliases() const {
-  // No aliases.
-  return std::nullopt;
+  return llvm::ArrayRef(GCCRegAliases);
 }
 
 bool M68kTargetInfo::validateAsmConstraint(
diff --git a/clang/lib/Basic/Targets/M68k.h b/clang/lib/Basic/Targets/M68k.h
index a9c262e62fbad0..7ffa901127e504 100644
--- a/clang/lib/Basic/Targets/M68k.h
+++ b/clang/lib/Basic/Targets/M68k.h
@@ -25,6 +25,7 @@ namespace targets {
 
 class LLVM_LIBRARY_VISIBILITY M68kTargetInfo : public TargetInfo {
   static const char *const GCCRegNames[];
+  static const TargetInfo::GCCRegAlias GCCRegAliases[];
 
   enum CPUKind {
 CK_Unknown,
diff --git a/clang/test/CodeGen/M68k/inline-asm-gcc-regs.c 
b/clang/test/CodeGen/M68k/inline-asm-gcc-regs.c
new file mode 100644
index 00..40d3543d8a6f90
--- /dev/null
+++ b/clang/test/CodeGen/M68k/inline-asm-gcc-regs.c
@@ -0,0 +1,134 @@
+// RUN: %clang_cc1 -triple m68k -emit-llvm -O2 %s -o - | FileCheck %s
+
+/// Check GCC register names and alias can be used in register variable 
definition.
+
+// CHECK-LABEL: @test_d0
+// CHECK: call void asm sideeffect "", "{d0}"(i32 undef)
+void test_d0() {
+register int a asm ("d0");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d1
+// CHECK: call void asm sideeffect "", "{d1}"(i32 undef)
+void test_d1() {
+register int a asm ("d1");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d2
+// CHECK: call void asm sideeffect "", "{d2}"(i32 undef)
+void test_d2() {
+register int a asm ("d2");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d3
+// CHECK: call void asm sideeffect "", "{d3}"(i32 undef)
+void test_d3() {
+register int a asm ("d3");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d4
+// CHECK: call void asm sideeffect "", "{d4}"(i32 undef)
+void test_d4() {
+register int a asm ("d4");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d5
+// CHECK: call void asm sideeffect "", "{d5}"(i32 undef)
+void test_d5() {
+register int a asm ("d5");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d6
+// CHECK: call void asm sideeffect "", "{d6}"(i32 undef)
+void test_d6() {
+register int a asm ("d6");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_d7
+// CHECK: call void asm sideeffect "", "{d7}"(i32 undef)
+void test_d7() {
+register int a asm ("d7");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_a0
+// CHECK: call void asm sideeffect "", "{a0}"(i32 undef)
+void test_a0() {
+register int a asm ("a0");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_a1
+// CHECK: call void asm sideeffect "", "{a1}"(i32 undef)
+void test_a1() {
+register int a asm ("a1");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_a2
+// CHECK: call void asm sideeffect "", "{a2}"(i32 undef)
+void test_a2() {
+register int a asm ("a2");
+asm ("" :: "r" (a));
+}
+
+// CHECK-LABEL: @test_a3
+/

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

2024-04-01 Thread Jim Lin via cfe-commits


tclin914 wrote:

> Is it possible use `TargetInfo::getGCCRegAliases` to model the aliasing 
> between a7 and sp? Also, could you add a simple test?

Implement getGCCRegAliases and add testcase.

https://github.com/llvm/llvm-project/pull/87095
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[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

2024-04-02 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/87095
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

2024-01-30 Thread Jim Lin via cfe-commits


https://github.com/tclin914 approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/79618
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[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

2024-01-30 Thread Jim Lin via cfe-commits



@@ -797,6 +797,13 @@ def FeatureStdExtSvpbmt
 : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
"'Svpbmt' (Page-Based Memory Types)">;
 
+def FeatureStdExtZalasr

tclin914 wrote:

Could we put this definition after Zacas.

https://github.com/llvm/llvm-project/pull/79911
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[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

2024-01-30 Thread Jim Lin via cfe-commits



@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*- 
tablegen -*-===//

tclin914 wrote:

exceed 80 characters

https://github.com/llvm/llvm-project/pull/79911
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[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

2024-01-30 Thread Jim Lin via cfe-commits



@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*- 
tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the Zalasr (Load-Acquire
+// and Store-Release) extension
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class LAQ_r funct3, string opcodestr>
+: RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO,
+(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
+opcodestr, "$rd, $rs1"> {
+  let rs2 = 0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class SRL_r funct3, string opcodestr>
+: RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO,
+(outs ), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
+opcodestr, "$rs2, $rs1"> {
+  let rd = 0;
+}
+multiclass LAQ_r_aq_rl funct3, string opcodestr> {
+  def _AQ: LAQ_r<1, 0, funct3, opcodestr # ".aq">;
+  def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">;
+}
+
+multiclass SRL_r_aq_rl funct3, string opcodestr> {
+  def _RL: SRL_r<0, 1, funct3, opcodestr # ".rl">;
+  def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">;
+}
+
+//===--===//
+// Instructions
+//===--===//
+

tclin914 wrote:

Could we remain only one blank line for consistency with others.

https://github.com/llvm/llvm-project/pull/79911
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[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)

2024-02-04 Thread Jim Lin via cfe-commits


https://github.com/tclin914 approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/79615
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[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)

2024-01-29 Thread Jim Lin via cfe-commits



@@ -0,0 +1,479 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +zvfh -target-feature +experimental-zvfbfwma 
-disable-O0-optnone  \

tclin914 wrote:

Are `-target-feature +zfh` and `-target-feature +zvfh` necessary?

https://github.com/llvm/llvm-project/pull/79615
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

2024-01-29 Thread Jim Lin via cfe-commits



@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
   def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
   def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
 }
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-2, -1, 0, 1, 2],

tclin914 wrote:

Do we need a RequiredFeatures for this?

https://github.com/llvm/llvm-project/pull/79618
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

2024-01-29 Thread Jim Lin via cfe-commits



@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
   def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
   def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
 }
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-2, -1, 0, 1, 2],
+OverloadedName = "vfwcvtbf16_f" in
+defm : RVVConvBuiltinSet<"vfwcvtbf16_f_f_v", "y", [["Fw", "Fwv"]]>;

tclin914 wrote:

Could we just use `RVVConvBuiltin` here. 
Like `def vfwcvtbf16_f_f_v : RVVConvBuiltin<"Fw", "Fwv", "y", "vfwcvtbf16_f">;`

https://github.com/llvm/llvm-project/pull/79618
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

2024-01-29 Thread Jim Lin via cfe-commits



@@ -0,0 +1,218 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +zvfh -target-feature +experimental-zvfbfmin 
-disable-O0-optnone  \

tclin914 wrote:

Are -target-feature +zfh and -target-feature +zvfh necessary?

https://github.com/llvm/llvm-project/pull/79618
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

2024-01-29 Thread Jim Lin via cfe-commits



@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
   def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
   def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
 }
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-2, -1, 0, 1, 2],

tclin914 wrote:

Ok, It can't declare a bfloat16 vector without Zvfbfmin extension. Thanks for 
explanation.

https://github.com/llvm/llvm-project/pull/79618
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

2024-01-29 Thread Jim Lin via cfe-commits



@@ -282,6 +282,9 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
 }
   }
 
+  if (BaseType == BasicType::BFloat16 && !TI.hasFeature("zvfbfmin"))

tclin914 wrote:

bfloat vector is only valid when zvfbfmin is enabled. So it doesn't need to 
check again.

https://github.com/llvm/llvm-project/pull/79618
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[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)

2024-01-30 Thread Jim Lin via cfe-commits



@@ -21189,6 +21189,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   case RISCV::BI__builtin_riscv_clmulh_64:
   case RISCV::BI__builtin_riscv_clmulr_32:
   case RISCV::BI__builtin_riscv_clmulr_64:
+  case RISCV::BI__builtin_riscv_mopr_32:

tclin914 wrote:

I think put mop between zb* builtins is not a good ideal.

https://github.com/llvm/llvm-project/pull/79971
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[clang] [RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (PR #77866)

2024-01-11 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/77866

>From #75735, Zvfh implies Zvfhmin.

>From be8d27cf8a3cf511598437a401a2277b36752137 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 12 Jan 2024 09:58:49 +0800
Subject: [PATCH] [RISCV] Change required features for Zvfhmin intrinsics from
 ZvfhminOrZvfh to Zvfhmin

>From https://github.com/llvm/llvm-project/pull/75735, Zvfh implies Zvfhmin.
---
 clang/include/clang/Basic/riscv_vector.td | 44 +--
 .../clang/Support/RISCVVIntrinsicUtils.h  |  2 +-
 clang/lib/Sema/SemaRISCVVectorLookup.cpp  |  5 +--
 clang/utils/TableGen/RISCVVEmitter.cpp|  2 +-
 4 files changed, 26 insertions(+), 27 deletions(-)

diff --git a/clang/include/clang/Basic/riscv_vector.td 
b/clang/include/clang/Basic/riscv_vector.td
index e7d78b03511fe9..8bde081052505d 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -117,7 +117,7 @@ multiclass RVVIndexedLoad {
 defvar eew = eew_list[0];
 defvar eew_type = eew_list[1];
 let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
-RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
[]) in {
   def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
 if !not(IsFloat.val) then {
@@ -128,7 +128,7 @@ multiclass RVVIndexedLoad {
   defvar eew64 = "64";
   defvar eew64_type = "(Log2EEW:6)";
   let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
-  RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+  RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
  ["RV64"]) in {
   def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
 if !not(IsFloat.val) then {
@@ -222,7 +222,7 @@ multiclass RVVIndexedStore {
   defvar eew = eew_list[0];
   defvar eew_type = eew_list[1];
   let Name = op # eew  # "_v", IRName = op, MaskedIRName = op # 
"_mask",
-  RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+  RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
  []) in  {
 def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
 if !not(IsFloat.val) then {
@@ -233,7 +233,7 @@ multiclass RVVIndexedStore {
 defvar eew64 = "64";
 defvar eew64_type = "(Log2EEW:6)";
 let Name = op # eew64  # "_v", IRName = op, MaskedIRName = op # 
"_mask",
-RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
["RV64"]) in  {
   def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
   if !not(IsFloat.val) then {
@@ -681,7 +681,7 @@ let HasBuiltinAlias = false,
 def vlm: RVVVLEMaskBuiltin;
 defm vle8: RVVVLEBuiltin<["c"]>;
 defm vle16: RVVVLEBuiltin<["s"]>;
-let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in
   defm vle16_h: RVVVLEBuiltin<["x"]>;
 defm vle32: RVVVLEBuiltin<["i","f"]>;
 defm vle64: RVVVLEBuiltin<["l","d"]>;
@@ -689,7 +689,7 @@ defm vle64: RVVVLEBuiltin<["l","d"]>;
 def vsm : RVVVSEMaskBuiltin;
 defm vse8 : RVVVSEBuiltin<["c"]>;
 defm vse16: RVVVSEBuiltin<["s"]>;
-let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in
   defm vse16_h: RVVVSEBuiltin<["x"]>;
 defm vse32: RVVVSEBuiltin<["i","f"]>;
 defm vse64: RVVVSEBuiltin<["l","d"]>;
@@ -697,14 +697,14 @@ defm vse64: RVVVSEBuiltin<["l","d"]>;
 // 7.5. Vector Strided Instructions
 defm vlse8: RVVVLSEBuiltin<["c"]>;
 defm vlse16: RVVVLSEBuiltin<["s"]>;
-let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in
   defm vlse16_h: RVVVLSEBuiltin<["x"]>;
 defm vlse32: RVVVLSEBuiltin<["i","f"]>;
 defm vlse64: RVVVLSEBuiltin<["l","d"]>;
 
 defm vsse8 : RVVVSSEBuiltin<["c"]>;
 defm vsse16: RVVVSSEBuiltin<["s"]>;
-let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in
   defm vsse16_h: RVVVSSEBuiltin<["x"]>;
 defm vsse32: RVVVSSEBuiltin<["i","f"]>;
 defm vsse64: RVVVSSEBuiltin<["l","d"]>;
@@ -719,7 +719,7 @@ defm : RVVIndexedStore<"vsoxei">;
 // 7.7. Unit-stride Fault-Only-First Loads
 defm vle8ff: RVVVLEFFBuiltin<["c"]>;
 defm vle16ff: RVVVLEFFBuiltin<["s"]>;
-let Name = "vle16ff_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in
   defm vle16ff: RVVVLEFFBuiltin<["x"]>;
 defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
 defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
@@ -738,7

[clang] [RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (PR #77866)

2024-01-13 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/77866
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[clang-tools-extra] 8188c99 - [docs] Update path to clang-tools-extra

2020-01-02 Thread Jim Lin via cfe-commits


Author: Alexander Lanin
Date: 2020-01-02T19:30:29+08:00
New Revision: 8188c998ffa4d20253444b257402907d2aa74dc2

URL: 
https://github.com/llvm/llvm-project/commit/8188c998ffa4d20253444b257402907d2aa74dc2
DIFF: 
https://github.com/llvm/llvm-project/commit/8188c998ffa4d20253444b257402907d2aa74dc2.diff

LOG: [docs] Update path to clang-tools-extra

Summary:
> tools/clang/tools/extra
has become
>clang-tools-extra
which was not updated in all docs.

Reviewers: alexfh, aaron.ballman, ilya-biryukov, juliehockett

Reviewed By: aaron.ballman

Subscribers: Jim, cfe-commits

Tags: #clang-tools-extra, #clang

Differential Revision: https://reviews.llvm.org/D71982

Added: 


Modified: 
clang-tools-extra/docs/clang-include-fixer.rst
clang-tools-extra/docs/clang-tidy/Contributing.rst
clang-tools-extra/docs/pp-trace.rst

Removed: 




diff  --git a/clang-tools-extra/docs/clang-include-fixer.rst 
b/clang-tools-extra/docs/clang-include-fixer.rst
index b934095d8e74..7d1fd9ed70e7 100644
--- a/clang-tools-extra/docs/clang-include-fixer.rst
+++ b/clang-tools-extra/docs/clang-include-fixer.rst
@@ -49,7 +49,7 @@ database for LLVM, any project built by CMake should follow 
similar steps.
   $ ninja clang-include-fixer // build clang-include-fixer tool.
   $ ls compile_commands.json # Make sure compile_commands.json exists.
 compile_commands.json
-  $ 
path/to/llvm/source/tools/clang/tools/extra/clang-include-fixer/find-all-symbols/tool/run-find-all-symbols.py
+  $ 
path/to/llvm/source/clang-tools-extra/clang-include-fixer/find-all-symbols/tool/run-find-all-symbols.py
 ... wait as clang indexes the code base ...
   $ ln -s $PWD/find_all_symbols_db.yaml path/to/llvm/source/ # Link database 
into the source tree.
   $ ln -s $PWD/compile_commands.json path/to/llvm/source/ # Also link 
compilation database if it's not there already.
@@ -64,7 +64,7 @@ following key binding to your ``.vimrc``:
 
 .. code-block:: console
 
-  noremap cf :pyf 
path/to/llvm/source/tools/clang/tools/extra/clang-include-fixer/tool/clang-include-fixer.py
+  noremap cf :pyf 
path/to/llvm/source/clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.py
 
 This enables `clang-include-fixer` for NORMAL and VISUAL mode. Change
 `cf` to another binding if you need clang-include-fixer on a 
diff erent
@@ -118,7 +118,7 @@ in your ``.emacs``:
 
 .. code-block:: console
 
- (add-to-list 'load-path 
"path/to/llvm/source/tools/clang/tools/extra/clang-include-fixer/tool/"
+ (add-to-list 'load-path 
"path/to/llvm/source/clang-tools-extra/clang-include-fixer/tool/"
  (require 'clang-include-fixer)
 
 Within Emacs the tool can be invoked with the command

diff  --git a/clang-tools-extra/docs/clang-tidy/Contributing.rst 
b/clang-tools-extra/docs/clang-tidy/Contributing.rst
index 09ff1f65c2c2..3ed6dadb5e8b 100644
--- a/clang-tools-extra/docs/clang-tidy/Contributing.rst
+++ b/clang-tools-extra/docs/clang-tidy/Contributing.rst
@@ -63,7 +63,7 @@ the LLVM System`_, `Using Clang Tools`_ and `How To Setup 
Clang Tooling For
 LLVM`_ documents to check out and build LLVM, Clang and Clang Extra Tools with
 CMake.
 
-Once you are done, change to the ``llvm/tools/clang/tools/extra`` directory, 
and
+Once you are done, change to the ``llvm/clang-tools-extra`` directory, and
 let's start!
 
 .. _Getting Started with the LLVM System: 
https://llvm.org/docs/GettingStarted.html
@@ -75,7 +75,7 @@ The Directory Structure
 ---
 
 :program:`clang-tidy` source code resides in the
-``llvm/tools/clang/tools/extra`` directory and is structured as follows:
+``llvm/clang-tools-extra`` directory and is structured as follows:
 
 ::
 

diff  --git a/clang-tools-extra/docs/pp-trace.rst 
b/clang-tools-extra/docs/pp-trace.rst
index b0930070dcca..60e4de461253 100644
--- a/clang-tools-extra/docs/pp-trace.rst
+++ b/clang-tools-extra/docs/pp-trace.rst
@@ -104,16 +104,16 @@ With real data:::
 
   ---
   - Callback: FileChanged
-Loc: 
"c:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-include.cpp:1:1"
+Loc: 
"c:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-include.cpp:1:1"
 Reason: EnterFile
 FileType: C_User
 PrevFID: (invalid)
 (etc.)
   - Callback: FileChanged
-Loc: 
"D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-include.cpp:5:1"
+Loc: 
"D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-include.cpp:5:1"
 Reason: ExitFile
 FileType: C_User
-PrevFID: 
"D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/Input/Level1B.h"
+PrevFID: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/Input/Level1B.h"
   - Callback: EndOfMainFile
   ...
 
@@ -172,7 +172,7 @@ PrevFID  ((file)|(invalid)) 
  FileID
 Example:::
 
   - Callback: FileChanged
-Loc: 
"D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-include.cpp:1:1"
+Loc: 
"D:/Clang/llvm/clang-tools-extr

[clang] ab1bcda - [NFC] Use isX86() instead of getArch()

2020-01-07 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2020-01-07T17:35:44+08:00
New Revision: ab1bcda851d95aeec03ffc1218bf9cae261a9280

URL: 
https://github.com/llvm/llvm-project/commit/ab1bcda851d95aeec03ffc1218bf9cae261a9280
DIFF: 
https://github.com/llvm/llvm-project/commit/ab1bcda851d95aeec03ffc1218bf9cae261a9280.diff

LOG: [NFC] Use isX86() instead of getArch()

Summary: This is a clean up for https://reviews.llvm.org/D72247.

Reviewers: MaskRay, craig.topper, jhenderson

Reviewed By: MaskRay

Subscribers: hiraditya, rupprecht, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D72320

Added: 


Modified: 
clang/include/clang/Basic/TargetInfo.h
clang/lib/AST/Mangle.cpp
clang/lib/CodeGen/CGOpenMPRuntime.cpp
clang/lib/CodeGen/CodeGenFunction.cpp
clang/lib/Driver/ToolChains/Arch/X86.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Driver/ToolChains/Darwin.cpp
clang/lib/Sema/SemaExpr.cpp
llvm/lib/Analysis/TargetLibraryInfo.cpp
llvm/lib/MC/MCObjectFileInfo.cpp
llvm/tools/llvm-objdump/MachODump.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/TargetInfo.h 
b/clang/include/clang/Basic/TargetInfo.h
index a32b30f5b7e9..3a8e35524695 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1146,10 +1146,7 @@ class TargetInfo : public virtual 
TransferrableTargetInfo,
 
   /// Identify whether this target supports multiversioning of functions,
   /// which requires support for cpu_supports and cpu_is functionality.
-  bool supportsMultiVersioning() const {
-return getTriple().getArch() == llvm::Triple::x86 ||
-   getTriple().getArch() == llvm::Triple::x86_64;
-  }
+  bool supportsMultiVersioning() const { return getTriple().isX86(); }
 
   /// Identify whether this target supports IFuncs.
   bool supportsIFunc() const { return getTriple().isOSBinFormatELF(); }
@@ -1214,8 +1211,7 @@ class TargetInfo : public virtual TransferrableTargetInfo,
   /// Whether the target supports SEH __try.
   bool isSEHTrySupported() const {
 return getTriple().isOSWindows() &&
-   (getTriple().getArch() == llvm::Triple::x86 ||
-getTriple().getArch() == llvm::Triple::x86_64 ||
+   (getTriple().isX86() ||
 getTriple().getArch() == llvm::Triple::aarch64);
   }
 

diff  --git a/clang/lib/AST/Mangle.cpp b/clang/lib/AST/Mangle.cpp
index 32d466cb5718..e106b31f59f0 100644
--- a/clang/lib/AST/Mangle.cpp
+++ b/clang/lib/AST/Mangle.cpp
@@ -63,9 +63,7 @@ static CCMangling getCallingConvMangling(const ASTContext 
&Context,
  const NamedDecl *ND) {
   const TargetInfo &TI = Context.getTargetInfo();
   const llvm::Triple &Triple = TI.getTriple();
-  if (!Triple.isOSWindows() ||
-  !(Triple.getArch() == llvm::Triple::x86 ||
-Triple.getArch() == llvm::Triple::x86_64))
+  if (!Triple.isOSWindows() || !Triple.isX86())
 return CCM_Other;
 
   if (Context.getLangOpts().CPlusPlus && !isExternC(ND) &&

diff  --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp 
b/clang/lib/CodeGen/CGOpenMPRuntime.cpp
index b3b16befeea4..b71756f2449f 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp
@@ -10829,8 +10829,7 @@ void CGOpenMPRuntime::emitDeclareSimdFunction(const 
FunctionDecl *FD,
 ExprLoc = VLENExpr->getExprLoc();
   }
   OMPDeclareSimdDeclAttr::BranchStateTy State = Attr->getBranchState();
-  if (CGM.getTriple().getArch() == llvm::Triple::x86 ||
-  CGM.getTriple().getArch() == llvm::Triple::x86_64) {
+  if (CGM.getTriple().isX86()) {
 emitX86DeclareSimdFunction(FD, Fn, VLENVal, ParamAttrs, State);
   } else if (CGM.getTriple().getArch() == llvm::Triple::aarch64) {
 unsigned VLEN = VLENVal.getExtValue();

diff  --git a/clang/lib/CodeGen/CodeGenFunction.cpp 
b/clang/lib/CodeGen/CodeGenFunction.cpp
index 448b70de9714..a717f43e3efd 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2378,10 +2378,7 @@ static void 
CreateMultiVersionResolverReturn(CodeGenModule &CGM,
 
 void CodeGenFunction::EmitMultiVersionResolver(
 llvm::Function *Resolver, ArrayRef Options) {
-  assert((getContext().getTargetInfo().getTriple().getArch() ==
-  llvm::Triple::x86 ||
-  getContext().getTargetInfo().getTriple().getArch() ==
-  llvm::Triple::x86_64) &&
+  assert(getContext().getTargetInfo().getTriple().isX86() &&
  "Only implemented for x86 targets");
 
   bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();

diff  --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp 
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index d2b97bf6ad71..d1e0c8253b79 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -63,8 +63,7 @@ const char *x86::getX86Targe

[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

2023-09-25 Thread Jim Lin via cfe-commits



@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
 def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
  (sequence "X%u", 18, 23))>;
 
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {

tclin914 wrote:

Is GPRX1X5 better?

https://github.com/llvm/llvm-project/pull/66043
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[clang] af7231d - [RISCV] Make the order of tests in riscv-target-features.c eqaul to the extensions listed in the table in RISCVISAInfo.cpp. NFC.

2023-08-17 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-08-18T12:56:12+08:00
New Revision: af7231d1835b3dbfd938c7fdff8188ce49a3b58b

URL: 
https://github.com/llvm/llvm-project/commit/af7231d1835b3dbfd938c7fdff8188ce49a3b58b
DIFF: 
https://github.com/llvm/llvm-project/commit/af7231d1835b3dbfd938c7fdff8188ce49a3b58b.diff

LOG: [RISCV] Make the order of tests in riscv-target-features.c eqaul to the 
extensions listed in the table in RISCVISAInfo.cpp. NFC.

1. Let the order of tests equal to listed in the extension table in 
RISCVISAInfo.cpp.
2. Separate non-experimental and experimental extensions.
3. Add missing tests for RV32.
4. Add missing tests for some extension.
5. Let line break style be the same.

Added: 


Modified: 
clang/test/Preprocessor/riscv-target-features.c

Removed: 




diff  --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index c2722fb34a1a72..02b67dc7944ba8 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -3,54 +3,122 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
 // RUN: -o - | FileCheck %s
 
-// CHECK-NOT: __riscv_div {{.*$}}
-// CHECK-NOT: __riscv_m {{.*$}}
-// CHECK-NOT: __riscv_mul {{.*$}}
-// CHECK-NOT: __riscv_muldiv {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
-// CHECK-NOT: __riscv_f {{.*$}}
+// CHECK-NOT: __riscv_c {{.*$}}
+// CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
+// CHECK-NOT: __riscv_f {{.*$}}
 // CHECK-NOT: __riscv_flen {{.*$}}
 // CHECK-NOT: __riscv_fdiv {{.*$}}
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
-// CHECK-NOT: __riscv_c {{.*$}}
-// CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_zihintntl {{.*$}}
+// CHECK-NOT: __riscv_h {{.*$}}
+// CHECK-NOT: __riscv_div {{.*$}}
+// CHECK-NOT: __riscv_m {{.*$}}
+// CHECK-NOT: __riscv_mul {{.*$}}
+// CHECK-NOT: __riscv_muldiv {{.*$}}
+// CHECK-NOT: __riscv_svinval {{.*$}}
+// CHECK-NOT: __riscv_svnapot {{.*$}}
+// CHECK-NOT: __riscv_svpbmt {{.*$}}
+// CHECK-NOT: __riscv_v {{.*$}}
+// CHECK-NOT: __riscv_v_elen {{.*$}}
+// CHECK-NOT: __riscv_v_elen_fp {{.*$}}
+// CHECK-NOT: __riscv_v_intrinsic {{.*$}}
+// CHECK-NOT: __riscv_v_min_vlen {{.*$}}
+// CHECK-NOT: __riscv_vector {{.*$}}
+// CHECK-NOT: __riscv_xcvalu {{.*$}}
+// CHECK-NOT: __riscv_xcvbi {{.*$}}
+// CHECK-NOT: __riscv_xcvbitmanip {{.*$}}
+// CHECK-NOT: __riscv_xcvmac {{.*$}}
+// CHECK-NOT: __riscv_xcvsimd {{.*$}}
+// CHECK-NOT: __riscv_xsfcie {{.*$}}
+// CHECK-NOT: __riscv_xsfvcp {{.*$}}
+// CHECK-NOT: __riscv_xtheadba {{.*$}}
+// CHECK-NOT: __riscv_xtheadbb {{.*$}}
+// CHECK-NOT: __riscv_xtheadbs {{.*$}}
+// CHECK-NOT: __riscv_xtheadcmo {{.*$}}
+// CHECK-NOT: __riscv_xtheadcondmov {{.*$}}
+// CHECK-NOT: __riscv_xtheadfmemidx {{.*$}}
+// CHECK-NOT: __riscv_xtheadmac {{.*$}}
+// CHECK-NOT: __riscv_xtheadmemidx {{.*$}}
+// CHECK-NOT: __riscv_xtheadmempair {{.*$}}
+// CHECK-NOT: __riscv_xtheadsync {{.*$}}
+// CHECK-NOT: __riscv_xtheadvdot {{.*$}}
+// CHECK-NOT: __riscv_xventanacondops {{.*$}}
+// CHECK-NOT: __riscv_zawrs {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
 // CHECK-NOT: __riscv_zbc {{.*$}}
-// CHECK-NOT: __riscv_zbs {{.*$}}
-// CHECK-NOT: __riscv_zfh {{.*$}}
-// CHECK-NOT: __riscv_v {{.*$}}
-// CHECK-NOT: __riscv_vector {{.*$}}
-// CHECK-NOT: __riscv_v_intrinsic {{.*$}}
+// CHECK-NOT: __riscv_zbkb {{.*$}}
 // CHECK-NOT: __riscv_zbkc {{.*$}}
 // CHECK-NOT: __riscv_zbkx {{.*$}}
-// CHECK-NOT: __riscv_zbkb {{.*$}}
-// CHECK-NOT: __riscv_zkne {{.*$}}
-// CHECK-NOT: __riscv_zknd {{.*$}}
-// CHECK-NOT: __riscv_zknh {{.*$}}
-// CHECK-NOT: __riscv_zksh {{.*$}}
-// CHECK-NOT: __riscv_zksed {{.*$}}
-// CHECK-NOT: __riscv_zkr {{.*$}}
-// CHECK-NOT: __riscv_zkt {{.*$}}
-// CHECK-NOT: __riscv_zk {{.*$}}
-// CHECK-NOT: __riscv_zicbom {{.*$}}
-// CHECK-NOT: __riscv_zicboz {{.*$}}
-// CHECK-NOT: __riscv_svnapot {{.*$}}
-// CHECK-NOT: __riscv_svpbmt {{.*$}}
-// CHECK-NOT: __riscv_svinval {{.*$}}
-// CHECK-NOT: __riscv_xventanacondops {{.*$}}
+// CHECK-NOT: __riscv_zbs {{.*$}}
 // CHECK-NOT: __riscv_zca {{.*$}}
 // CHECK-NOT: __riscv_zcb {{.*$}}
 // CHECK-NOT: __riscv_zcd {{.*$}}
+// CHECK-NOT: __riscv_zce {{.*$}}
 // CHECK-NOT: __riscv_zcf {{.*$}}
 // CHECK-NOT: __riscv_zcmp {{.*$}}
 // CHECK-NOT: __riscv_zcmt {{.*$}}
-// CHECK-NOT: __riscv_h {{.*$}}
+// CHECK-NOT: __riscv_zdinx {{.*$}}
+// CHECK-NOT: __riscv_zfh {{.*$}}
+// CHECK-NOT: __riscv_zfhmin {{.*$}}
+// CHECK-NOT: __riscv_zfinx {{.*$}}
+// CHECK-NOT: __riscv_zhinx {{.*$}}
+// CHECK-NOT: __riscv_zhinxmin {{.*$}}
+// CHECK-NOT: __riscv_zicbom {{.*$}}
+// CHECK-NOT: __riscv_zicbop {{.*$}}
+// CHECK-NOT: __riscv_zicboz {{.*$}}
+// CHECK-NOT: __riscv_zicntr {{.*$}}
+// CHECK-NOT: __riscv_zicsr {{.*$}}
+// CHECK-NOT: __riscv_zifencei {{.*$}}
+// CHECK-NOT: __riscv_zihintntl {{.*$}}
+// CHECK-NOT: __riscv_zihint

[clang] 1c10667 - [AST] Simplify Type::isSizelessBuiltinType(). NFC.

2023-08-01 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-08-02T10:46:42+08:00
New Revision: 1c1066797c5bb56616dc485b596fd40d5f03ece2

URL: 
https://github.com/llvm/llvm-project/commit/1c1066797c5bb56616dc485b596fd40d5f03ece2
DIFF: 
https://github.com/llvm/llvm-project/commit/1c1066797c5bb56616dc485b596fd40d5f03ece2.diff

LOG: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

Reuse isSVESizelessBuiltinType() and isRVVSizelessBuiltinType().

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D156686

Added: 


Modified: 
clang/lib/AST/Type.cpp

Removed: 




diff  --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index cd1bcc4f17cdc6..8af6e296a20efb 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@ bool Type::isIncompleteType(NamedDecl **Def) const {
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"



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[clang] d7abafa - [RISCV] Remove -menable-experimental-extensions option for zc extension in riscv-target-features.c. NFC.

2023-08-06 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-08-07T14:03:33+08:00
New Revision: d7abafa6a03f3aa66b18b16cb040795201870845

URL: 
https://github.com/llvm/llvm-project/commit/d7abafa6a03f3aa66b18b16cb040795201870845
DIFF: 
https://github.com/llvm/llvm-project/commit/d7abafa6a03f3aa66b18b16cb040795201870845.diff

LOG: [RISCV] Remove -menable-experimental-extensions option for zc extension in 
riscv-target-features.c. NFC.

zca, zcb, zcd, zcf, zcmp and zcmt aren't experimental extensions.

Added: 


Modified: 
clang/test/Preprocessor/riscv-target-features.c

Removed: 




diff  --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 3a0ab9431e0769..2361ec70a5609c 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -496,40 +496,40 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s
 // CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 100{{$}}
 
-// RUN: %clang -target riscv32 -march=rv32izca1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
-// RUN: %clang -target riscv64 -march=rv64izca1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// RUN: %clang -target riscv32 -march=rv32izca1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izca1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
 // CHECK-ZCA-EXT: __riscv_zca 100{{$}}
 
-// RUN: %clang -target riscv32 -march=rv32izcb1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
-// RUN: %clang -target riscv64 -march=rv64izcb1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// RUN: %clang -target riscv32 -march=rv32izcb1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcb1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
 // CHECK-ZCB-EXT: __riscv_zca 100{{$}}
 // CHECK-ZCB-EXT: __riscv_zcb 100{{$}}
 
-// RUN: %clang -target riscv32 -march=rv32izcd1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
-// RUN: %clang -target riscv64 -march=rv64izcd1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
+// RUN: %clang -target riscv32 -march=rv32izcd1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcd1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
 // CHECK-ZCD-EXT: __riscv_zcd 100{{$}}
 
-// RUN: %clang -target riscv32 -march=rv32izcf1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
+// RUN: %clang -target riscv32 -march=rv32izcf1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
 // CHECK-ZCF-EXT: __riscv_zcf 100{{$}}
 
-// RUN: %clang -target riscv32 -march=rv32izcmp1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCMP-EXT %s
-// RUN: %clang -target riscv64 -march=rv64izcmp1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCMP-EXT %s
+// RUN: %clang -target riscv32 -march=rv32izcmp1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMP-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcmp1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMP-EXT %s
 // CHECK-ZCMP-EXT: __riscv_zca 100{{$}}
 // CHECK-ZCMP-EXT: __riscv_zcmp 100{{$}}
 
-// RUN: %clang -target riscv32 -march=rv32izcmt1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCMT-EXT %s
-// RUN: %clang -target riscv64 -march=rv64izcmt1p0 
-menable-experimental-extensions \
-// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCMT-EXT %s
+// RUN: %clang -target riscv32 -march=rv32izcmt1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMT-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcmt1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMT-EXT %s
 // CHECK-ZCMT-EXT: __riscv_zca 100{{$}}
 // CHECK-ZCMT-EXT: __riscv_zcmt 100{{$}}
 



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[clang] 767ca3a - [RISCV] Remove pre-defined macro test for b extension. NFC.

2023-08-07 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-08-08T13:01:34+08:00
New Revision: 767ca3a70d6d60bd52ff0829335942aa6dafcc28

URL: 
https://github.com/llvm/llvm-project/commit/767ca3a70d6d60bd52ff0829335942aa6dafcc28
DIFF: 
https://github.com/llvm/llvm-project/commit/767ca3a70d6d60bd52ff0829335942aa6dafcc28.diff

LOG: [RISCV] Remove pre-defined macro test for b extension. NFC.

B extension has been removed.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157353

Added: 


Modified: 
clang/test/Preprocessor/riscv-target-features.c

Removed: 




diff  --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 2361ec70a5609c..dcf62e76149ccd 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \



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[clang] 8fe0449 - [RISCV] Fix required features checking with empty string

2023-07-14 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-07-14T16:09:11+08:00
New Revision: 8fe0449ac99087c74f785ddbdd4fbba65b396b3b

URL: 
https://github.com/llvm/llvm-project/commit/8fe0449ac99087c74f785ddbdd4fbba65b396b3b
DIFF: 
https://github.com/llvm/llvm-project/commit/8fe0449ac99087c74f785ddbdd4fbba65b396b3b.diff

LOG: [RISCV] Fix required features checking with empty string

In our downstream, we define some intrinsics that don't require any
extra extension enabled. Such as

TARGET_BUILTIN(__builtin_riscv_xxx, "LiLi", "nc", "")

But `split` function's `KeepEmpty` argument is True. Got the error message

error: builtin requires at least one of the following extensions support to be 
enabled : ''

when we use our customized intrinsic.

Reviewed By: craig.topper, wangpc

Differential Revision: https://reviews.llvm.org/D154596

Added: 


Modified: 
clang/lib/Sema/SemaChecking.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 392062ea64a1fc..f9a50f6ef3be6f 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo 
&TI,
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {



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[clang] d099dbb - [git-clang-format] Fix typo in help message

2023-08-29 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-08-30T14:09:31+08:00
New Revision: d099dbb221a4c3474a15117b1658dedc5dcd6ebf

URL: 
https://github.com/llvm/llvm-project/commit/d099dbb221a4c3474a15117b1658dedc5dcd6ebf
DIFF: 
https://github.com/llvm/llvm-project/commit/d099dbb221a4c3474a15117b1658dedc5dcd6ebf.diff

LOG: [git-clang-format] Fix typo in help message

`git clang-format` -> `git-clang-format`

Added: 


Modified: 
clang/tools/clang-format/git-clang-format

Removed: 




diff  --git a/clang/tools/clang-format/git-clang-format 
b/clang/tools/clang-format/git-clang-format
index c0b99b82203234..3e49c49af2babc 100755
--- a/clang/tools/clang-format/git-clang-format
+++ b/clang/tools/clang-format/git-clang-format
@@ -13,11 +13,11 @@ clang-format git integration
 
 
 This file provides a clang-format integration for git. Put it somewhere in your
-path and ensure that it is executable. Then, "git clang-format" will invoke
+path and ensure that it is executable. Then, "git-clang-format" will invoke
 clang-format on the changes in current files or a specific commit.
 
 For further details, run:
-git clang-format -h
+git-clang-format -h
 
 Requires Python 2.7 or Python 3
 """
@@ -32,7 +32,7 @@ import re
 import subprocess
 import sys
 
-usage = ('git clang-format [OPTIONS] [] [|--staged] '
+usage = ('git-clang-format [OPTIONS] [] [|--staged] '
  '[--] [...]')
 
 desc = '''
@@ -42,13 +42,13 @@ only applied to the working directory, or in the 
stage/index.
 
 Examples:
   To format staged changes, i.e everything that's been `git add`ed:
-git clang-format
+git-clang-format
 
   To also format everything touched in the most recent commit:
-git clang-format HEAD~1
+git-clang-format HEAD~1
 
   If you're on a branch off main, to format everything touched on your branch:
-git clang-format main
+git-clang-format main
 
 If two commits are given (requires --
diff ), run clang-format on all lines in the
 second  that 
diff er from the first .



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[clang] c1dda0f - [AST] Remove unneeded `return false` from UseExcessPrecision. NFC.

2023-08-30 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-08-30T16:05:55+08:00
New Revision: c1dda0f7934d28eb8dfc92206c49b188a1a091de

URL: 
https://github.com/llvm/llvm-project/commit/c1dda0f7934d28eb8dfc92206c49b188a1a091de
DIFF: 
https://github.com/llvm/llvm-project/commit/c1dda0f7934d28eb8dfc92206c49b188a1a091de.diff

LOG: [AST] Remove unneeded `return false` from UseExcessPrecision. NFC.

Remove unneeded `return false` from UseExcessPrecision and move `break` inside.

Added: 


Modified: 
clang/lib/AST/Type.cpp

Removed: 




diff  --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index 8173e082048207..c08ebfb7f142b3 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -1526,16 +1526,16 @@ bool QualType::UseExcessPrecision(const ASTContext 
&Ctx) {
   Ctx.getLangOpts().getFloat16ExcessPrecision() !=
   Ctx.getLangOpts().ExcessPrecisionKind::FPP_None)
 return true;
-  return false;
-} break;
+  break;
+}
 case BuiltinType::Kind::BFloat16: {
   const TargetInfo &TI = Ctx.getTargetInfo();
   if (TI.hasBFloat16Type() && !TI.hasFullBFloat16Type() &&
   Ctx.getLangOpts().getBFloat16ExcessPrecision() !=
   Ctx.getLangOpts().ExcessPrecisionKind::FPP_None)
 return true;
-  return false;
-} break;
+  break;
+}
 default:
   return false;
 }



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[clang] ea789f8 - Remove unused option that gcc ignored

2020-02-18 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2020-02-19T08:36:07+08:00
New Revision: ea789f819f26a1b003a1bf07466fc9fa2fe558ec

URL: 
https://github.com/llvm/llvm-project/commit/ea789f819f26a1b003a1bf07466fc9fa2fe558ec
DIFF: 
https://github.com/llvm/llvm-project/commit/ea789f819f26a1b003a1bf07466fc9fa2fe558ec.diff

LOG: Remove unused option that gcc ignored

Reviewers: efriedma, MaskRay

Reviewed By: efriedma, MaskRay

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D72825

Added: 


Modified: 
clang/include/clang/Driver/Options.td
clang/test/Driver/clang_f_opts.c

Removed: 




diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 1a42925ca530..4104a4ae6ed0 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3325,9 +3325,6 @@ defm strength_reduce :
 defm tls_model : BooleanFFlag<"tls-model">, Group;
 defm tracer : BooleanFFlag<"tracer">, 
Group;
 defm tree_dce : BooleanFFlag<"tree-dce">, 
Group;
-defm tree_loop_im : BooleanFFlag<"tree_loop_im">,  
Group;
-defm tree_loop_ivcanon : BooleanFFlag<"tree_loop_ivcanon">,  
Group;
-defm tree_loop_linear : BooleanFFlag<"tree_loop_linear">,  
Group;
 defm tree_salias : BooleanFFlag<"tree-salias">, Group;
 defm tree_ter : BooleanFFlag<"tree-ter">, 
Group;
 defm tree_vectorizer_verbose : BooleanFFlag<"tree-vectorizer-verbose">, 
Group;

diff  --git a/clang/test/Driver/clang_f_opts.c 
b/clang/test/Driver/clang_f_opts.c
index 970b4e934e78..3d0d74ba5ab9 100644
--- a/clang/test/Driver/clang_f_opts.c
+++ b/clang/test/Driver/clang_f_opts.c
@@ -291,9 +291,6 @@
 // RUN: -frename-registers\
 // RUN: -fschedule-insns2 \
 // RUN: -fsingle-precision-constant   \
-// RUN: -ftree_loop_im\
-// RUN: -ftree_loop_ivcanon   \
-// RUN: -ftree_loop_linear\
 // RUN: -funsafe-loop-optimizations   \
 // RUN: -fuse-linker-plugin   \
 // RUN: -fvect-cost-model \
@@ -431,9 +428,6 @@
 // CHECK-WARNING-DAG: optimization flag '-frename-registers' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fschedule-insns2' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fsingle-precision-constant' is not 
supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_im' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_ivcanon' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_linear' is not supported
 // CHECK-WARNING-DAG: optimization flag '-funsafe-loop-optimizations' is not 
supported
 // CHECK-WARNING-DAG: optimization flag '-fuse-linker-plugin' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fvect-cost-model' is not supported



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[clang] 492d4a9 - [NFC] Update the testcase clang_f_opts.c for the removed options

2020-02-18 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2020-02-19T09:28:41+08:00
New Revision: 492d4a992d88516da471b60ecd9a37ea80dbf9a4

URL: 
https://github.com/llvm/llvm-project/commit/492d4a992d88516da471b60ecd9a37ea80dbf9a4
DIFF: 
https://github.com/llvm/llvm-project/commit/492d4a992d88516da471b60ecd9a37ea80dbf9a4.diff

LOG: [NFC] Update the testcase clang_f_opts.c for the removed options

Added: 


Modified: 
clang/test/Driver/clang_f_opts.c

Removed: 




diff  --git a/clang/test/Driver/clang_f_opts.c 
b/clang/test/Driver/clang_f_opts.c
index 3d0d74ba5ab9..6fb820a9938d 100644
--- a/clang/test/Driver/clang_f_opts.c
+++ b/clang/test/Driver/clang_f_opts.c
@@ -364,9 +364,6 @@
 // RUN: -frename-registers\
 // RUN: -fschedule-insns2 \
 // RUN: -fsingle-precision-constant   \
-// RUN: -ftree_loop_im\
-// RUN: -ftree_loop_ivcanon   \
-// RUN: -ftree_loop_linear\
 // RUN: -funsafe-loop-optimizations   \
 // RUN: -fuse-linker-plugin   \
 // RUN: -fvect-cost-model \



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[clang] d40afad - [git-clang-format] Fix typo in help message

2020-03-02 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2020-03-02T18:16:35+08:00
New Revision: d40afadec0acd5f093a5f46fa2362312aef54189

URL: 
https://github.com/llvm/llvm-project/commit/d40afadec0acd5f093a5f46fa2362312aef54189
DIFF: 
https://github.com/llvm/llvm-project/commit/d40afadec0acd5f093a5f46fa2362312aef54189.diff

LOG: [git-clang-format] Fix typo in help message

Added: 


Modified: 
clang/tools/clang-format/git-clang-format

Removed: 




diff  --git a/clang/tools/clang-format/git-clang-format 
b/clang/tools/clang-format/git-clang-format
index bf05d9143fa1..abbe3b7b97c6 100755
--- a/clang/tools/clang-format/git-clang-format
+++ b/clang/tools/clang-format/git-clang-format
@@ -45,7 +45,7 @@ second  that 
diff er from the first .
 The following git-config settings set the default of the corresponding option:
   clangFormat.binary
   clangFormat.commit
-  clangFormat.extension
+  clangFormat.extensions
   clangFormat.style
 '''
 



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[clang] cefac9d - Remove implicit conversion that promotes half to other larger precision types for fp classification builtins

2019-12-09 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2019-12-10T13:24:21+08:00
New Revision: cefac9dfaac9c806433ad88cca85bd2f3ba1edad

URL: 
https://github.com/llvm/llvm-project/commit/cefac9dfaac9c806433ad88cca85bd2f3ba1edad
DIFF: 
https://github.com/llvm/llvm-project/commit/cefac9dfaac9c806433ad88cca85bd2f3ba1edad.diff

LOG: Remove implicit conversion that promotes half to other larger precision 
types for fp classification builtins

Summary:
It shouldn't promote half to double or any larger precision types for fp 
classification builtins.
Because fp classification builtins would get incorrect result with promoted 
argument.
For example, __builtin_isnormal with a subnormal half value should return 
false, but it is not.
That the subnormal half value is promoted to a normal double value.

Reviewers: aaron.ballman

Reviewed By: aaron.ballman

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D71049

Added: 


Modified: 
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins.c

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 825e0faa3037..2be9ecec 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5808,10 +5808,11 @@ bool Sema::SemaBuiltinFPClassification(CallExpr 
*TheCall, unsigned NumArgs) {
<< OrigArg->getType() << OrigArg->getSourceRange();
 
   // If this is an implicit conversion from float -> float, double, or
-  // long double, remove it.
+  // long double, or half -> half, float, double, or long double, remove it.
   if (ImplicitCastExpr *Cast = dyn_cast(OrigArg)) {
 // Only remove standard FloatCasts, leaving other casts inplace
 if (Cast->getCastKind() == CK_FloatingCast) {
+  bool IgnoreCast = false;
   Expr *CastArg = Cast->getSubExpr();
   if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Float)) {
 assert(
@@ -5820,6 +5821,19 @@ bool Sema::SemaBuiltinFPClassification(CallExpr 
*TheCall, unsigned NumArgs) {
  Cast->getType()->isSpecificBuiltinType(BuiltinType::LongDouble)) 
&&
 "promotion from float to either float, double, or long double is "
 "the only expected cast here");
+IgnoreCast = true;
+  } else if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Half)) 
{
+assert(
+(Cast->getType()->isSpecificBuiltinType(BuiltinType::Double) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Float) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Half) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::LongDouble)) 
&&
+"promotion from half to either half, float, double, or long double 
"
+"is the only expected cast here");
+IgnoreCast = true;
+  }
+
+  if (IgnoreCast) {
 Cast->setSubExpr(nullptr);
 TheCall->setArg(NumArgs-1, CastArg);
   }

diff  --git a/clang/test/CodeGen/builtins.c b/clang/test/CodeGen/builtins.c
index 5b482543d2d0..591416d00cc7 100644
--- a/clang/test/CodeGen/builtins.c
+++ b/clang/test/CodeGen/builtins.c
@@ -193,8 +193,12 @@ void test_conditional_bzero() {
 }
 
 // CHECK-LABEL: define void @test_float_builtins
-void test_float_builtins(float F, double D, long double LD) {
+void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
   volatile int res;
+  res = __builtin_isinf(*H);
+  // CHECK:  call half @llvm.fabs.f16(half
+  // CHECK:  fcmp oeq half {{.*}}, 0xH7C00
+
   res = __builtin_isinf(F);
   // CHECK:  call float @llvm.fabs.f32(float
   // CHECK:  fcmp oeq float {{.*}}, 0x7FF0
@@ -207,6 +211,14 @@ void test_float_builtins(float F, double D, long double 
LD) {
   // CHECK:  call x86_fp80 @llvm.fabs.f80(x86_fp80
   // CHECK:  fcmp oeq x86_fp80 {{.*}}, 0xK7FFF8000
 
+  res = __builtin_isinf_sign(*H);
+  // CHECK:  %[[ABS:.*]] = call half @llvm.fabs.f16(half %[[ARG:.*]])
+  // CHECK:  %[[ISINF:.*]] = fcmp oeq half %[[ABS]], 0xH7C00
+  // CHECK:  %[[BITCAST:.*]] = bitcast half %[[ARG]] to i16
+  // CHECK:  %[[ISNEG:.*]] = icmp slt i16 %[[BITCAST]], 0
+  // CHECK:  %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
+  // CHECK:  select i1 %[[ISINF]], i32 %[[SIGN]], i32 0
+
   res = __builtin_isinf_sign(F);
   // CHECK:  %[[ABS:.*]] = call float @llvm.fabs.f32(float %[[ARG:.*]])
   // CHECK:  %[[ISINF:.*]] = fcmp oeq float %[[ABS]], 0x7FF0
@@ -231,6 +243,10 @@ void test_float_builtins(float F, double D, long double 
LD) {
   // CHECK:  %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
   // CHECK:  select i1 %[[ISINF]], i32 %[[SIGN]], i32 0
 
+  res = __builtin_isfinite(*H);
+  // CHECK: call half @llvm.fabs.f16(half
+  // CHECK: fcmp one half {{.*}}, 0xH7C00
+
   res = __builtin_isfinite(F);
   // CHECK: call float @llvm.fabs.f32(float
   // CHECK: fcmp one float {{.*}}, 0x7FF0
@

[clang] 9c39663 - Only Remove implicit conversion for the target that support fp16

2019-12-10 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2019-12-10T19:15:11+08:00
New Revision: 9c3966379813c198129c57aa3ebecd68d6af1ebd

URL: 
https://github.com/llvm/llvm-project/commit/9c3966379813c198129c57aa3ebecd68d6af1ebd
DIFF: 
https://github.com/llvm/llvm-project/commit/9c3966379813c198129c57aa3ebecd68d6af1ebd.diff

LOG: Only Remove implicit conversion for the target that support fp16

Remove implicit conversion that promotes half to double
for the target that support fp16. If the target doesn't
support fp16, fp16 will be converted to fp16 intrinsic.

Added: 


Modified: 
clang/lib/Sema/SemaChecking.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 2be9ecec..aff63aef2934 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5822,7 +5822,8 @@ bool Sema::SemaBuiltinFPClassification(CallExpr *TheCall, 
unsigned NumArgs) {
 "promotion from float to either float, double, or long double is "
 "the only expected cast here");
 IgnoreCast = true;
-  } else if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Half)) 
{
+  } else if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Half) 
&&
+ !Context.getTargetInfo().useFP16ConversionIntrinsics()) {
 assert(
 (Cast->getType()->isSpecificBuiltinType(BuiltinType::Double) ||
  Cast->getType()->isSpecificBuiltinType(BuiltinType::Float) ||



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[clang] 4daa8d1 - Correct inf typo

2019-12-12 Thread Jim Lin via cfe-commits


Author: Andrew Gaul
Date: 2019-12-13T11:02:40+08:00
New Revision: 4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a

URL: 
https://github.com/llvm/llvm-project/commit/4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a
DIFF: 
https://github.com/llvm/llvm-project/commit/4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a.diff

LOG: Correct inf typo

Reviewers: krasimir

Reviewed By: krasimir

Subscribers: Jim, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D57732

Added: 


Modified: 
clang/docs/ClangFormatStyleOptions.rst
clang/include/clang/Format/Format.h

Removed: 




diff  --git a/clang/docs/ClangFormatStyleOptions.rst 
b/clang/docs/ClangFormatStyleOptions.rst
index 2f7483435fd4..18cdc54a370f 100644
--- a/clang/docs/ClangFormatStyleOptions.rst
+++ b/clang/docs/ClangFormatStyleOptions.rst
@@ -958,7 +958,7 @@ the configuration (without a prefix: ``Auto``).
 
 .. code-block:: c++
 
-  int f()   vs.   inf f()
+  int f()   vs.   int f()
   {}  {
   }
 

diff  --git a/clang/include/clang/Format/Format.h 
b/clang/include/clang/Format/Format.h
index f17a10c7f5c8..add2937f3b43 100644
--- a/clang/include/clang/Format/Format.h
+++ b/clang/include/clang/Format/Format.h
@@ -981,7 +981,7 @@ struct FormatStyle {
 /// set, and the function could/should not be put on a single line (as per
 /// `AllowShortFunctionsOnASingleLine` and constructor formatting options).
 /// \code
-///   int f()   vs.   inf f()
+///   int f()   vs.   int f()
 ///   {}  {
 ///   }
 /// \endcode



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[clang] 466f884 - [NFC] Remove trailing space

2020-02-17 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2020-02-18T10:49:13+08:00
New Revision: 466f8843f526b03c8944a46af5ebb374133b5389

URL: 
https://github.com/llvm/llvm-project/commit/466f8843f526b03c8944a46af5ebb374133b5389
DIFF: 
https://github.com/llvm/llvm-project/commit/466f8843f526b03c8944a46af5ebb374133b5389.diff

LOG: [NFC] Remove trailing space

sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h,td}

Added: 


Modified: 
clang/lib/AST/DeclCXX.cpp
clang/lib/AST/JSONNodeDumper.cpp
clang/lib/AST/StmtProfile.cpp
clang/lib/Basic/FileManager.cpp
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CGObjCGNU.cpp
clang/lib/CodeGen/CGObjCRuntime.cpp
clang/lib/Index/IndexDecl.cpp
clang/lib/Parse/ParseExpr.cpp
clang/lib/Parse/ParseExprCXX.cpp
clang/lib/Parse/ParseTemplate.cpp
clang/lib/Sema/SemaExpr.cpp
clang/lib/Sema/SemaObjCProperty.cpp
clang/lib/Sema/SemaTemplate.cpp
clang/lib/Sema/SemaTemplateInstantiate.cpp
clang/lib/Sema/SemaTemplateVariadic.cpp
clang/lib/Serialization/ModuleManager.cpp
llvm/include/llvm-c/Core.h
llvm/lib/Analysis/AliasSetTracker.cpp
llvm/lib/Analysis/GuardUtils.cpp
llvm/lib/Analysis/Loads.cpp
llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
llvm/lib/Analysis/ScalarEvolution.cpp
llvm/lib/Analysis/TargetLibraryInfo.cpp
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Analysis/VectorUtils.cpp
llvm/lib/AsmParser/LLParser.cpp
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/lib/CodeGen/GCRootLowering.cpp
llvm/lib/CodeGen/StackMaps.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/CodeGen/ValueTypes.cpp
llvm/lib/IR/Constants.cpp
llvm/lib/IR/Core.cpp
llvm/lib/IR/DiagnosticInfo.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/MC/XCOFFObjectWriter.cpp
llvm/lib/Support/Host.cpp

Removed: 




diff  --git a/clang/lib/AST/DeclCXX.cpp b/clang/lib/AST/DeclCXX.cpp
index 931a1141b1b4..58e7e16d6817 100644
--- a/clang/lib/AST/DeclCXX.cpp
+++ b/clang/lib/AST/DeclCXX.cpp
@@ -663,7 +663,7 @@ bool 
CXXRecordDecl::lambdaIsDefaultConstructibleAndAssignable() const {
   // C++17 [expr.prim.lambda]p21:
   //   The closure type associated with a lambda-expression has no default
   //   constructor and a deleted copy assignment operator.
-  if (getLambdaCaptureDefault() != LCD_None || 
+  if (getLambdaCaptureDefault() != LCD_None ||
   getLambdaData().NumCaptures != 0)
 return false;
   return getASTContext().getLangOpts().CPlusPlus2a;
@@ -2152,7 +2152,7 @@ CXXMethodDecl 
*CXXMethodDecl::getDevirtualizedMethod(const Expr *Base,
 return DevirtualizedMethod;
 
   // Similarly, if the class itself or its destructor is marked 'final',
-  // the class can't be derived from and we can therefore devirtualize the 
+  // the class can't be derived from and we can therefore devirtualize the
   // member function call.
   if (BestDynamicDecl->isEffectivelyFinal())
 return DevirtualizedMethod;

diff  --git a/clang/lib/AST/JSONNodeDumper.cpp 
b/clang/lib/AST/JSONNodeDumper.cpp
index c30b07137edc..637b61e90a90 100644
--- a/clang/lib/AST/JSONNodeDumper.cpp
+++ b/clang/lib/AST/JSONNodeDumper.cpp
@@ -997,7 +997,7 @@ void JSONNodeDumper::VisitObjCPropertyDecl(const 
ObjCPropertyDecl *D) {
   case ObjCPropertyDecl::Required: JOS.attribute("control", "required"); break;
   case ObjCPropertyDecl::Optional: JOS.attribute("control", "optional"); break;
   }
-  
+
   ObjCPropertyDecl::PropertyAttributeKind Attrs = D->getPropertyAttributes();
   if (Attrs != ObjCPropertyDecl::OBJC_PR_noattr) {
 if (Attrs & ObjCPropertyDecl::OBJC_PR_getter)

diff  --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp
index 14ddc13ce561..76c5fe2e5402 100644
--- a/clang/lib/AST/StmtProfile.cpp
+++ b/clang/lib/AST/StmtProfile.cpp
@@ -1387,7 +1387,7 @@ void StmtProfiler::VisitRequiresExpr(const RequiresExpr 
*S) {
   ID.AddInteger(concepts::Requirement::RK_Nested);
   auto *NestedReq = cast(Req);
   ID.AddBoolean(NestedReq->isSubstitutionFailure());
-  if (!NestedReq->isSubstitutionFailure())  
+  if (!NestedReq->isSubstitutionFailure())
 Visit(NestedReq->getConstraintExpr());
 }
   }

diff  --git a/clang/lib/Basic/FileManager.cpp b/clang/lib/Basic/FileManager.cpp
index e4d019aedb7c..ac8af8fcaf4a 100644
--- a/clang/lib/Basic/FileManager.cpp
+++ b/clang/lib/Basic/FileManager.cpp
@@ -513,7 +513,7 @@ FileManager::getStatValue(StringRef Path, llvm::vfs::Status 
&Status,
   StatCache.get(), *FS);
 }
 
-std::error_code 
+std::error_code
 FileManager::getNoncachedStatValue(StringRef Path,
llvm::vfs::Status &Result) {
   SmallString<128> FilePath(Path);

diff  --git a/clang/lib/CodeGen/BackendUtil.cpp 
b/clang/lib/CodeGen/BackendUtil.cpp
index 48e26459e94f..6c71cf793c0f 100644
--- a/clang/lib/

[clang] 612b7e1 - [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi

2023-06-25 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-06-26T13:15:37+08:00
New Revision: 612b7e10a9afa797d41e134bc62a8ef87a014caf

URL: 
https://github.com/llvm/llvm-project/commit/612b7e10a9afa797d41e134bc62a8ef87a014caf
DIFF: 
https://github.com/llvm/llvm-project/commit/612b7e10a9afa797d41e134bc62a8ef87a014caf.diff

LOG: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to 
iUZi/iUWi

Input argument of clz and ctz should be unsigned type and return value
should be integer like `builtin_clz` and `builtin_ctz` defined in 
clang/include/clang/Basic/Builtins.def.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153235

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsRISCV.def
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsRISCV.def 
b/clang/include/clang/Basic/BuiltinsRISCV.def
index a1a32f0a3e4ef..7f84be42faf40 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,10 +18,10 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb")
-TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "iUZi", "nc", "zbb|xtheadbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "iUWi", "nc", "zbb|xtheadbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "iUWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c 
b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
index 329f9ec52a0ce..4129457fcd073 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@ int orc_b_32(int a) {
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -34,6 +34,6 @@ int clz_32(int a) {
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c 
b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
index 0133cb1ec202d..baf7de1e0b9f1 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,19 +34,22 @@ long orc_b_64(long a) {
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
 // RV64ZBB-LABEL: @clz_64(
 // RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
-// RV64ZBB-NEXT:ret i64 [[TMP1]]
+// RV64ZBB-NEXT:store i64 [[TMP1]], ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:[[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:ret i32 [[TMP2]]
 //
-long clz_64(long a) {
+int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,18 +61,21 @@ long clz_64(long a) {
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
-// RV64ZBB-NEXT:ret i64 [[TMP1]]
+// RV64ZBB-NEXT:store i64 [[TMP1]], ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:[[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:ret i32 [[TMP2]]
 //
-long ctz_64(long a) {
+int ctz_64(unsigned long a) {

[clang] 33d3d51 - [RISCV] Add missing test for ctz_32 on RV64

2023-05-21 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-05-22T10:28:27+08:00
New Revision: 33d3d51d77a7fb7ca6b919f9ba47999cd8531844

URL: 
https://github.com/llvm/llvm-project/commit/33d3d51d77a7fb7ca6b919f9ba47999cd8531844
DIFF: 
https://github.com/llvm/llvm-project/commit/33d3d51d77a7fb7ca6b919f9ba47999cd8531844.diff

LOG: [RISCV] Add missing test for ctz_32 on RV64

Apparently, both of clz and ctz should have tests for _32 version on RV64.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D150945

Added: 


Modified: 
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

Removed: 




diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c 
b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
index e136151e511b3..0133cb1ec202d 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@ long clz_64(long a) {
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8



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[clang] d4c5b45 - [NFC] Remove unneeded semicolon after function definition

2023-06-06 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-06-07T09:29:49+08:00
New Revision: d4c5b452934a31f9b3685cf58bd682104b686d1a

URL: 
https://github.com/llvm/llvm-project/commit/d4c5b452934a31f9b3685cf58bd682104b686d1a
DIFF: 
https://github.com/llvm/llvm-project/commit/d4c5b452934a31f9b3685cf58bd682104b686d1a.diff

LOG: [NFC] Remove unneeded semicolon after function definition

Added: 


Modified: 
clang/lib/Tooling/Transformer/Stencil.cpp
lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.h
llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
llvm/include/llvm/Object/GOFFObjectFile.h
llvm/lib/Target/CSKY/CSKYAsmPrinter.h
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVTargetStreamer.h
llvm/lib/Target/X86/MCTargetDesc/X86MCExpr.h
llvm/unittests/Transforms/Vectorize/VPlanTest.cpp

Removed: 




diff  --git a/clang/lib/Tooling/Transformer/Stencil.cpp 
b/clang/lib/Tooling/Transformer/Stencil.cpp
index 2198aefddc9f1..f2c1b6f8520a8 100644
--- a/clang/lib/Tooling/Transformer/Stencil.cpp
+++ b/clang/lib/Tooling/Transformer/Stencil.cpp
@@ -327,7 +327,7 @@ class SelectBoundStencil : public 
clang::transformer::StencilInterface {
 assert(containsNoNullStencils(CaseStencils) &&
"cases of selectBound may not be null");
   }
-  ~SelectBoundStencil() override{};
+  ~SelectBoundStencil() override {}
 
   llvm::Error eval(const MatchFinder::MatchResult &match,
std::string *result) const override {

diff  --git a/lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.h 
b/lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.h
index e1b8558e1cda0..da0b867fb1e9b 100644
--- a/lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.h
+++ b/lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.h
@@ -22,7 +22,7 @@ class ArchitectureAArch64 : public Architecture {
 
   llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
 
-  void OverrideStopInfo(Thread &thread) const override{};
+  void OverrideStopInfo(Thread &thread) const override {}
 
   const MemoryTagManager *GetMemoryTagManager() const override {
 return &m_memory_tag_manager;

diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h 
b/llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
index 035c5a08feefd..eff87c5617d99 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
@@ -93,10 +93,10 @@ class GISelKnownBits : public GISelChangeObserver {
   Align computeKnownAlignment(Register R, unsigned Depth = 0);
 
   // Observer API. No-op for non-caching implementation.
-  void erasingInstr(MachineInstr &MI) override{};
-  void createdInstr(MachineInstr &MI) override{};
-  void changingInstr(MachineInstr &MI) override{};
-  void changedInstr(MachineInstr &MI) override{};
+  void erasingInstr(MachineInstr &MI) override {}
+  void createdInstr(MachineInstr &MI) override {}
+  void changingInstr(MachineInstr &MI) override {}
+  void changedInstr(MachineInstr &MI) override {}
 
 protected:
   unsigned getMaxDepth() const { return MaxDepth; }

diff  --git a/llvm/include/llvm/Object/GOFFObjectFile.h 
b/llvm/include/llvm/Object/GOFFObjectFile.h
index 37b6b1ec659a0..c39a9dee98d14 100644
--- a/llvm/include/llvm/Object/GOFFObjectFile.h
+++ b/llvm/include/llvm/Object/GOFFObjectFile.h
@@ -82,7 +82,7 @@ class GOFFObjectFile : public ObjectFile {
   bool isSymbolIndirect(DataRefImpl Symb) const;
 
   // SectionRef.
-  void moveSectionNext(DataRefImpl &Sec) const override{};
+  void moveSectionNext(DataRefImpl &Sec) const override {}
   virtual Expected getSectionName(DataRefImpl Sec) const override {
 return StringRef();
   }
@@ -112,7 +112,7 @@ class GOFFObjectFile : public ObjectFile {
   const uint8_t *getSectionPrEsdRecord(uint32_t SectionIndex) const;
 
   // RelocationRef.
-  void moveRelocationNext(DataRefImpl &Rel) const override{};
+  void moveRelocationNext(DataRefImpl &Rel) const override {}
   uint64_t getRelocationOffset(DataRefImpl Rel) const override { return 0; }
   symbol_iterator getRelocationSymbol(DataRefImpl Rel) const override {
 DataRefImpl Temp;
@@ -120,7 +120,7 @@ class GOFFObjectFile : public ObjectFile {
   }
   uint64_t getRelocationType(DataRefImpl Rel) const override { return 0; }
   void getRelocationTypeName(DataRefImpl Rel,
- SmallVectorImpl &Result) const override{};
+ SmallVectorImpl &Result) const override {}
 };
 
 } // namespace object

diff  --git a/llvm/lib/Target/CSKY/CSKYAsmPrinter.h 
b/llvm/lib/Target/CSKY/CSKYAsmPrinter.h
index 5e87594e4fdf1..379189512405a 100644
--- a/llvm/lib/Target/CSKY/CSKYAsmPrinter.h
+++ b/llvm/lib/Target/CSKY/CSKYAsmPrinter.h
@@ -57,7 +57,7 @@ class LLVM_LIBRARY_VISIBILITY CSKYAsmPrinter : public 
AsmPrinter {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   // we emit cons

[clang] dc895d0 - [RISCV] Remove redundant line `NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py` from riscv64-zknd-zkne.c

2023-06-14 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2023-06-15T10:22:06+08:00
New Revision: dc895d023e63fd9276fe493eded776e101015c86

URL: 
https://github.com/llvm/llvm-project/commit/dc895d023e63fd9276fe493eded776e101015c86
DIFF: 
https://github.com/llvm/llvm-project/commit/dc895d023e63fd9276fe493eded776e101015c86.diff

LOG: [RISCV] Remove redundant line `NOTE: Assertions have been autogenerated by 
utils/update_cc_test_checks.py` from riscv64-zknd-zkne.c

Added: 


Modified: 
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c

Removed: 




diff  --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c 
b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
index 9b9ce9d33dd5e..1132c98ef595f 100644
--- a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
@@ -1,7 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKND-ZKNE
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKND-ZKNE
 



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[clang] [RISCV] Add testcase for -mcmodel= (PR #107816)

2024-09-09 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/107816

None

>From f6da0096e4dcf3f7b5c8da4e8e170e88b7ebb471 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Mon, 9 Sep 2024 12:59:30 +0800
Subject: [PATCH] [RISCV] Add testcase for -mcmodel=

---
 clang/test/Driver/riscv-mcmodel.c | 14 ++
 1 file changed, 14 insertions(+)
 create mode 100644 clang/test/Driver/riscv-mcmodel.c

diff --git a/clang/test/Driver/riscv-mcmodel.c 
b/clang/test/Driver/riscv-mcmodel.c
new file mode 100644
index 00..4f5fa95f59b666
--- /dev/null
+++ b/clang/test/Driver/riscv-mcmodel.c
@@ -0,0 +1,14 @@
+// RUN: %clang --target=riscv32 -### -c -mcmodel=small %s 2>&1 | FileCheck 
--check-prefix=SMALL %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=small %s 2>&1 | FileCheck 
--check-prefix=SMALL %s
+
+// RUN: %clang --target=riscv32 -### -c -mcmodel=medlow %s 2>&1 | FileCheck 
--check-prefix=SMALL %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=medlow %s 2>&1 | FileCheck 
--check-prefix=SMALL %s
+
+// RUN: %clang --target=riscv32 -### -c -mcmodel=medium %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=medium %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
+
+// RUN: %clang --target=riscv32 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
+
+// SMALL: "-mcmodel=small"
+// MEDIUM: "-mcmodel=medium"

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[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

2024-09-09 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/107817

None

>From f6da0096e4dcf3f7b5c8da4e8e170e88b7ebb471 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Mon, 9 Sep 2024 12:59:30 +0800
Subject: [PATCH 1/2] [RISCV] Add testcase for -mcmodel=

---
 clang/test/Driver/riscv-mcmodel.c | 14 ++
 1 file changed, 14 insertions(+)
 create mode 100644 clang/test/Driver/riscv-mcmodel.c

diff --git a/clang/test/Driver/riscv-mcmodel.c 
b/clang/test/Driver/riscv-mcmodel.c
new file mode 100644
index 00..4f5fa95f59b666
--- /dev/null
+++ b/clang/test/Driver/riscv-mcmodel.c
@@ -0,0 +1,14 @@
+// RUN: %clang --target=riscv32 -### -c -mcmodel=small %s 2>&1 | FileCheck 
--check-prefix=SMALL %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=small %s 2>&1 | FileCheck 
--check-prefix=SMALL %s
+
+// RUN: %clang --target=riscv32 -### -c -mcmodel=medlow %s 2>&1 | FileCheck 
--check-prefix=SMALL %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=medlow %s 2>&1 | FileCheck 
--check-prefix=SMALL %s
+
+// RUN: %clang --target=riscv32 -### -c -mcmodel=medium %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=medium %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
+
+// RUN: %clang --target=riscv32 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
+
+// SMALL: "-mcmodel=small"
+// MEDIUM: "-mcmodel=medium"

>From 7bc57f0b8db381fb6223056c6e18a7aeddf7788e Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Mon, 9 Sep 2024 13:09:23 +0800
Subject: [PATCH 2/2] [RISCV] Allow -mcmodel= to accept large for RV64

---
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 3 ++-
 clang/test/Driver/riscv-mcmodel.c  | 6 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 0601016c3b14b8..f0e1b59076c738 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -2906,7 +2906,8 @@ void tools::addMCModel(const Driver &D, const 
llvm::opt::ArgList &Args,
 CM = "small";
   else if (CM == "medany")
 CM = "medium";
-  Ok = CM == "small" || CM == "medium";
+  Ok = CM == "small" || CM == "medium" ||
+   (CM == "large" && Triple.isRISCV64());
 } else if (Triple.getArch() == llvm::Triple::x86_64) {
   Ok = llvm::is_contained({"small", "kernel", "medium", "large", "tiny"},
   CM);
diff --git a/clang/test/Driver/riscv-mcmodel.c 
b/clang/test/Driver/riscv-mcmodel.c
index 4f5fa95f59b666..2482672d625fe3 100644
--- a/clang/test/Driver/riscv-mcmodel.c
+++ b/clang/test/Driver/riscv-mcmodel.c
@@ -10,5 +10,11 @@
 // RUN: %clang --target=riscv32 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
 // RUN: %clang --target=riscv64 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
 
+// RUN: not %clang --target=riscv32 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=ERR-LARGE %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=LARGE %s
+
 // SMALL: "-mcmodel=small"
 // MEDIUM: "-mcmodel=medium"
+// LARGE: "-mcmodel=large"
+
+// ERR-LARGE:  error: unsupported argument 'large' to option '-mcmodel=' for 
target 'riscv32'

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[clang] [RISCV] Add testcase for -mcmodel= (PR #107816)

2024-09-09 Thread Jim Lin via cfe-commits


https://github.com/tclin914 edited 
https://github.com/llvm/llvm-project/pull/107816
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[clang] [RISCV] Add testcase for -mcmodel= (PR #107816)

2024-09-10 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/107816
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[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

2024-09-10 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/107817

>From e394e7ca9e769deb3f286f53a48a049340bd51bd Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Mon, 9 Sep 2024 13:09:23 +0800
Subject: [PATCH 1/3] [RISCV] Allow -mcmodel= to accept large for RV64

---
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 3 ++-
 clang/test/Driver/riscv-mcmodel.c  | 6 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 2ce6779f4b43e3..94e4fdd58e692a 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -2906,7 +2906,8 @@ void tools::addMCModel(const Driver &D, const 
llvm::opt::ArgList &Args,
 CM = "small";
   else if (CM == "medany")
 CM = "medium";
-  Ok = CM == "small" || CM == "medium";
+  Ok = CM == "small" || CM == "medium" ||
+   (CM == "large" && Triple.isRISCV64());
 } else if (Triple.getArch() == llvm::Triple::x86_64) {
   Ok = llvm::is_contained({"small", "kernel", "medium", "large", "tiny"},
   CM);
diff --git a/clang/test/Driver/riscv-mcmodel.c 
b/clang/test/Driver/riscv-mcmodel.c
index 4f5fa95f59b666..2482672d625fe3 100644
--- a/clang/test/Driver/riscv-mcmodel.c
+++ b/clang/test/Driver/riscv-mcmodel.c
@@ -10,5 +10,11 @@
 // RUN: %clang --target=riscv32 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
 // RUN: %clang --target=riscv64 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
 
+// RUN: not %clang --target=riscv32 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=ERR-LARGE %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=LARGE %s
+
 // SMALL: "-mcmodel=small"
 // MEDIUM: "-mcmodel=medium"
+// LARGE: "-mcmodel=large"
+
+// ERR-LARGE:  error: unsupported argument 'large' to option '-mcmodel=' for 
target 'riscv32'

>From 5361de735b5dc67e476163f73f2bd05f15f8d0c9 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Tue, 10 Sep 2024 10:35:48 +0800
Subject: [PATCH 2/3] Add checking that large code model is disallowed to be
 used with PIC code model.

---
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 4 
 clang/test/Driver/riscv-mcmodel.c  | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 94e4fdd58e692a..f58b816a9709dd 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -2902,6 +2902,10 @@ void tools::addMCModel(const Driver &D, const 
llvm::opt::ArgList &Args,
 } else if (Triple.isPPC64() || Triple.isOSAIX()) {
   Ok = CM == "small" || CM == "medium" || CM == "large";
 } else if (Triple.isRISCV()) {
+  // Large code model is disallowed to be used with PIC code model.
+  if (CM == "large" && RelocationModel != llvm::Reloc::Static)
+D.Diag(diag::err_drv_argument_not_allowed_with)
+<< A->getAsString(Args) << "-fpic";
   if (CM == "medlow")
 CM = "small";
   else if (CM == "medany")
diff --git a/clang/test/Driver/riscv-mcmodel.c 
b/clang/test/Driver/riscv-mcmodel.c
index 2482672d625fe3..c27d7c63a75a4f 100644
--- a/clang/test/Driver/riscv-mcmodel.c
+++ b/clang/test/Driver/riscv-mcmodel.c
@@ -13,8 +13,11 @@
 // RUN: not %clang --target=riscv32 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=ERR-LARGE %s
 // RUN: %clang --target=riscv64 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=LARGE %s
 
+// RUN: not %clang --target=riscv64 -### -c -mcmodel=large -fpic %s 2>&1 | 
FileCheck --check-prefix=LARGE %s
+
 // SMALL: "-mcmodel=small"
 // MEDIUM: "-mcmodel=medium"
 // LARGE: "-mcmodel=large"
 
 // ERR-LARGE:  error: unsupported argument 'large' to option '-mcmodel=' for 
target 'riscv32'
+// ERR-PIC-LARGE:  error: invalid argument '-mcmodel=large' not allowed with 
'-fpic'

>From cb5e9464f0b1d7a637b6ce6e8c3cff38be52ca3d Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 11 Sep 2024 09:29:43 +0800
Subject: [PATCH 3/3] Add -mcmodel=large to ReleaseNotes.rst

---
 clang/docs/ReleaseNotes.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 250821a9f9c45c..996dfcba0f35eb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -455,6 +455,8 @@ LoongArch Support
 RISC-V Support
 ^^
 
+- The option ``-mcmodel=large`` for the large code model is supported.
+
 CUDA/HIP Language Changes
 ^
 

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[clang] [RISCV] Emit predefined macro __riscv_cmodel_large for large code model (PR #108131)

2024-09-10 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/108131

None

>From e394e7ca9e769deb3f286f53a48a049340bd51bd Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Mon, 9 Sep 2024 13:09:23 +0800
Subject: [PATCH 1/4] [RISCV] Allow -mcmodel= to accept large for RV64

---
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 3 ++-
 clang/test/Driver/riscv-mcmodel.c  | 6 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 2ce6779f4b43e3..94e4fdd58e692a 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -2906,7 +2906,8 @@ void tools::addMCModel(const Driver &D, const 
llvm::opt::ArgList &Args,
 CM = "small";
   else if (CM == "medany")
 CM = "medium";
-  Ok = CM == "small" || CM == "medium";
+  Ok = CM == "small" || CM == "medium" ||
+   (CM == "large" && Triple.isRISCV64());
 } else if (Triple.getArch() == llvm::Triple::x86_64) {
   Ok = llvm::is_contained({"small", "kernel", "medium", "large", "tiny"},
   CM);
diff --git a/clang/test/Driver/riscv-mcmodel.c 
b/clang/test/Driver/riscv-mcmodel.c
index 4f5fa95f59b666..2482672d625fe3 100644
--- a/clang/test/Driver/riscv-mcmodel.c
+++ b/clang/test/Driver/riscv-mcmodel.c
@@ -10,5 +10,11 @@
 // RUN: %clang --target=riscv32 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
 // RUN: %clang --target=riscv64 -### -c -mcmodel=medany %s 2>&1 | FileCheck 
--check-prefix=MEDIUM %s
 
+// RUN: not %clang --target=riscv32 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=ERR-LARGE %s
+// RUN: %clang --target=riscv64 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=LARGE %s
+
 // SMALL: "-mcmodel=small"
 // MEDIUM: "-mcmodel=medium"
+// LARGE: "-mcmodel=large"
+
+// ERR-LARGE:  error: unsupported argument 'large' to option '-mcmodel=' for 
target 'riscv32'

>From 5361de735b5dc67e476163f73f2bd05f15f8d0c9 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Tue, 10 Sep 2024 10:35:48 +0800
Subject: [PATCH 2/4] Add checking that large code model is disallowed to be
 used with PIC code model.

---
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 4 
 clang/test/Driver/riscv-mcmodel.c  | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 94e4fdd58e692a..f58b816a9709dd 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -2902,6 +2902,10 @@ void tools::addMCModel(const Driver &D, const 
llvm::opt::ArgList &Args,
 } else if (Triple.isPPC64() || Triple.isOSAIX()) {
   Ok = CM == "small" || CM == "medium" || CM == "large";
 } else if (Triple.isRISCV()) {
+  // Large code model is disallowed to be used with PIC code model.
+  if (CM == "large" && RelocationModel != llvm::Reloc::Static)
+D.Diag(diag::err_drv_argument_not_allowed_with)
+<< A->getAsString(Args) << "-fpic";
   if (CM == "medlow")
 CM = "small";
   else if (CM == "medany")
diff --git a/clang/test/Driver/riscv-mcmodel.c 
b/clang/test/Driver/riscv-mcmodel.c
index 2482672d625fe3..c27d7c63a75a4f 100644
--- a/clang/test/Driver/riscv-mcmodel.c
+++ b/clang/test/Driver/riscv-mcmodel.c
@@ -13,8 +13,11 @@
 // RUN: not %clang --target=riscv32 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=ERR-LARGE %s
 // RUN: %clang --target=riscv64 -### -c -mcmodel=large %s 2>&1 | FileCheck 
--check-prefix=LARGE %s
 
+// RUN: not %clang --target=riscv64 -### -c -mcmodel=large -fpic %s 2>&1 | 
FileCheck --check-prefix=LARGE %s
+
 // SMALL: "-mcmodel=small"
 // MEDIUM: "-mcmodel=medium"
 // LARGE: "-mcmodel=large"
 
 // ERR-LARGE:  error: unsupported argument 'large' to option '-mcmodel=' for 
target 'riscv32'
+// ERR-PIC-LARGE:  error: invalid argument '-mcmodel=large' not allowed with 
'-fpic'

>From cb5e9464f0b1d7a637b6ce6e8c3cff38be52ca3d Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 11 Sep 2024 09:29:43 +0800
Subject: [PATCH 3/4] Add -mcmodel=large to ReleaseNotes.rst

---
 clang/docs/ReleaseNotes.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 250821a9f9c45c..996dfcba0f35eb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -455,6 +455,8 @@ LoongArch Support
 RISC-V Support
 ^^
 
+- The option ``-mcmodel=large`` for the large code model is supported.
+
 CUDA/HIP Language Changes
 ^
 

>From 9089641a3e25061dcf62461967bdbfb4d0d20f19 Mon Sep 17 00:00:00 2001
From: patrick 
Date: Fri, 26 Nov 2021 15:09:08 +0800
Subject: [PATCH 4/4] [RISCV] Emit predefined macro __riscv_cmodel_large for
 large code model.

---
 clang/lib/Basic/Targets/RISCV.cpp  | 2 ++
 clang/test/Preprocessor/riscv-cmodel.c | 9

[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

2024-09-10 Thread Jim Lin via cfe-commits


tclin914 wrote:

> What I am missing is:
> 
> * adjustments in `clang/lib/Basic/Targets/RISCV.cpp` to emit the macro 
> `__riscv_cmodel_large`
> * new tests in `clang/test/Preprocessor/riscv-cmodel.c`
> 
> Related PRs:
> 
> * [Add __riscv_cmodel_large define for large code model 
> riscv-non-isa/riscv-c-api-doc#86](https://github.com/riscv-non-isa/riscv-c-api-doc/pull/86)
> * [Add large code model 
> riscv-non-isa/riscv-toolchain-conventions#59](https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/59)

A follow-up PR #108131 for `__riscv_cmodel_large`

https://github.com/llvm/llvm-project/pull/107817
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[clang-tools-extra] f3314e3 - [clang-tidy] Pop Files only if FileChangeReason is ExitFile

2022-01-25 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2022-01-25T22:46:12+08:00
New Revision: f3314e3747873fdf026a28742a30f372503baf32

URL: 
https://github.com/llvm/llvm-project/commit/f3314e3747873fdf026a28742a30f372503baf32
DIFF: 
https://github.com/llvm/llvm-project/commit/f3314e3747873fdf026a28742a30f372503baf32.diff

LOG: [clang-tidy] Pop Files only if FileChangeReason is ExitFile

enum FileChangeReason has four possible type EnterFile, ExitFile,
SystemHeaderPragma and RenameFile,
It should pop the back element of Files only if FileChangeReason is ExitFile.

Added: 


Modified: 
clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp

Removed: 




diff  --git 
a/clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp 
b/clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp
index 681b8399154a7..a6e49439c8434 100644
--- a/clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp
+++ b/clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp
@@ -71,7 +71,7 @@ void DuplicateIncludeCallbacks::FileChanged(SourceLocation 
Loc,
 FileID PrevFID) {
   if (Reason == EnterFile)
 Files.emplace_back();
-  else
+  else if (Reason == ExitFile)
 Files.pop_back();
 }
 



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[clang] ad39b5b - [NFC] Remove duplicate include

2022-01-26 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2022-01-27T13:56:13+08:00
New Revision: ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e

URL: 
https://github.com/llvm/llvm-project/commit/ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e
DIFF: 
https://github.com/llvm/llvm-project/commit/ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e.diff

LOG: [NFC] Remove duplicate include

Added: 


Modified: 
clang/lib/Sema/SemaConcept.cpp
clang/unittests/AST/EvaluateAsRValueTest.cpp
clang/unittests/Tooling/Syntax/TokensTest.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaConcept.cpp b/clang/lib/Sema/SemaConcept.cpp
index 678f1e40e730b..ce99d4848ccaa 100644
--- a/clang/lib/Sema/SemaConcept.cpp
+++ b/clang/lib/Sema/SemaConcept.cpp
@@ -18,7 +18,6 @@
 #include "clang/Sema/Template.h"
 #include "clang/Sema/Overload.h"
 #include "clang/Sema/Initialization.h"
-#include "clang/Sema/SemaInternal.h"
 #include "clang/AST/ExprConcepts.h"
 #include "clang/AST/RecursiveASTVisitor.h"
 #include "clang/Basic/OperatorPrecedence.h"

diff  --git a/clang/unittests/AST/EvaluateAsRValueTest.cpp 
b/clang/unittests/AST/EvaluateAsRValueTest.cpp
index 0475330796d12..bf44136835f21 100644
--- a/clang/unittests/AST/EvaluateAsRValueTest.cpp
+++ b/clang/unittests/AST/EvaluateAsRValueTest.cpp
@@ -11,7 +11,6 @@
 //
 
//===--===//
 
-#include "clang/AST/ASTConsumer.h"
 #include "clang/AST/ASTConsumer.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/RecursiveASTVisitor.h"

diff  --git a/clang/unittests/Tooling/Syntax/TokensTest.cpp 
b/clang/unittests/Tooling/Syntax/TokensTest.cpp
index e7cb25782133e..22134d9d0cfb0 100644
--- a/clang/unittests/Tooling/Syntax/TokensTest.cpp
+++ b/clang/unittests/Tooling/Syntax/TokensTest.cpp
@@ -40,7 +40,6 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Testing/Support/Annotations.h"
 #include "llvm/Testing/Support/SupportHelpers.h"
-#include "gmock/gmock.h"
 #include 
 #include 
 #include 



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[clang] 9b70dda - [Builtins] Add missing the macro 'y' description in comments

2022-01-09 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2022-01-10T10:43:13+08:00
New Revision: 9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02

URL: 
https://github.com/llvm/llvm-project/commit/9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02
DIFF: 
https://github.com/llvm/llvm-project/commit/9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02.diff

LOG: [Builtins] Add missing the macro 'y' description in comments

New type str 'y' added from D76077. But missed its description in
comments.

Reviewed By: stuij

Differential Revision: https://reviews.llvm.org/D116509

Added: 


Modified: 
clang/include/clang/Basic/Builtins.def

Removed: 




diff  --git a/clang/include/clang/Basic/Builtins.def 
b/clang/include/clang/Basic/Builtins.def
index f73efdde3e2b1..bfaa7e9f5a9fa 100644
--- a/clang/include/clang/Basic/Builtins.def
+++ b/clang/include/clang/Basic/Builtins.def
@@ -26,6 +26,7 @@
 //  i -> int
 //  h -> half (__fp16, OpenCL)
 //  x -> half (_Float16)
+//  y -> half (__bf16)
 //  f -> float
 //  d -> double
 //  z -> size_t



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[clang] 6782417 - [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

2021-03-15 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2021-03-16T14:57:45+08:00
New Revision: 678241795c957b18bc473045e48abe3f2a61ff5c

URL: 
https://github.com/llvm/llvm-project/commit/678241795c957b18bc473045e48abe3f2a61ff5c
DIFF: 
https://github.com/llvm/llvm-project/commit/678241795c957b18bc473045e48abe3f2a61ff5c.diff

LOG: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

In BuiltinsRISCV.def, other extension 's intrinsics need to be defined by using 
macro BUILTIN.
So, it shouldn't undefine macro BUILTIN in the end of declaration for V 
intrinsics.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98682

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsRISCV.def
clang/utils/TableGen/RISCVVEmitter.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsRISCV.def 
b/clang/include/clang/Basic/BuiltinsRISCV.def
index e76c853787c9..c91b3d1b1f5c 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,3 +17,5 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+#undef BUILTIN
+#undef TARGET_BUILTIN

diff  --git a/clang/utils/TableGen/RISCVVEmitter.cpp 
b/clang/utils/TableGen/RISCVVEmitter.cpp
index ba96396c780d..f2b555a8b05c 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -881,7 +881,6 @@ void RVVEmitter::createBuiltins(raw_ostream &OS) {
 else
   OS << "\"\")\n";
   }
-  OS << "\n#undef BUILTIN\n";
   OS << "#undef RISCVV_BUILTIN\n";
 }
 



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[clang] 32ca5a0 - [RISCV] Refine pre-define macro tests

2021-03-30 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2021-03-31T14:06:20+08:00
New Revision: 32ca5a037ab9191d570bf9b5e0f13e28c3db27d9

URL: 
https://github.com/llvm/llvm-project/commit/32ca5a037ab9191d570bf9b5e0f13e28c3db27d9
DIFF: 
https://github.com/llvm/llvm-project/commit/32ca5a037ab9191d570bf9b5e0f13e28c3db27d9.diff

LOG: [RISCV] Refine pre-define macro tests

1. Undefined macro test for rv32i and rv64i.
  a. Reorder it with canonical order.
  b. Add missing  undefined macro check.
  c. Append defined value to `__riscv_a`, `__riscv_f` and `__riscv_c` to 
distinguish with
  `__riscv_arch_test`, `__riscv_cmodel_medlow` and 
`__riscv_float_abi_soft`. They have the same prefix.
2. Move abi macro test below f and d.
3. Unify coding style for newline.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D99631

Added: 


Modified: 
clang/test/Preprocessor/riscv-target-features.c

Removed: 




diff  --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 88826bbd60b8..da9b15b88a4c 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -4,14 +4,20 @@
 // RUN: -o - | FileCheck %s
 
 // CHECK-NOT: __riscv_div
+// CHECK-NOT: __riscv_m
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
-// CHECK-NOT: __riscv_compressed
-// CHECK-NOT: __riscv_bitmanip
+// CHECK-NOT: __riscv_a 200
+// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_f 200
+// CHECK-NOT: __riscv_d
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
-// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_c 200
+// CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_b
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_zba
 // CHECK-NOT: __riscv_zbb
 // CHECK-NOT: __riscv_zbc
@@ -24,6 +30,8 @@
 // CHECK-NOT: __riscv_zbs
 // CHECK-NOT: __riscv_zbt
 // CHECK-NOT: __riscv_zfh
+// CHECK-NOT: __riscv_v
+// CHECK-NOT: __riscv_vector
 // CHECK-NOT: __riscv_zvamo
 // CHECK-NOT: __riscv_zvlsseg
 
@@ -61,30 +69,6 @@
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
 
-// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// CHECK-C-EXT: __riscv_c 200
-// CHECK-C-EXT: __riscv_compressed 1
-
-// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// CHECK-B-EXT: __riscv_b 93000
-// CHECK-B-EXT: __riscv_bitmanip 1
-// CHECK-B-EXT: __riscv_zba 93000
-// CHECK-B-EXT: __riscv_zbb 93000
-// CHECK-B-EXT: __riscv_zbc 93000
-// CHECK-B-EXT: __riscv_zbe 93000
-// CHECK-B-EXT: __riscv_zbf 93000
-// CHECK-B-EXT: __riscv_zbm 93000
-// CHECK-B-EXT: __riscv_zbp 93000
-// CHECK-B-EXT: __riscv_zbr 93000
-// CHECK-B-EXT: __riscv_zbs 93000
-// CHECK-B-EXT: __riscv_zbt 93000
-
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x 
c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x 
c -E -dM %s \
@@ -109,104 +93,158 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 200
+// CHECK-C-EXT: __riscv_compressed 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
-// RUN:   -march=rv32iv0p10 -x c -E -dM %s \
-// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: -march=rv32ib0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
-// RUN:   -march=rv64iv0p10 -x c -E -dM %s \
-// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32izvamo0p10 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32izvamo0p10 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32izvlsseg0p10 -x

[clang] 8a2d375 - [NFC] [Clang]: fix spelling mistake in assert message

2021-04-11 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2021-04-12T14:10:52+08:00
New Revision: 8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53

URL: 
https://github.com/llvm/llvm-project/commit/8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53
DIFF: 
https://github.com/llvm/llvm-project/commit/8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53.diff

LOG: [NFC] [Clang]: fix spelling mistake in assert message

Reviewed By: Jim

Differential Revision: https://reviews.llvm.org/D71541

Added: 


Modified: 
clang/lib/AST/VTableBuilder.cpp

Removed: 




diff  --git a/clang/lib/AST/VTableBuilder.cpp b/clang/lib/AST/VTableBuilder.cpp
index f5865ce96b647..38d6fc28e0989 100644
--- a/clang/lib/AST/VTableBuilder.cpp
+++ b/clang/lib/AST/VTableBuilder.cpp
@@ -487,7 +487,7 @@ static bool HasSameVirtualSignature(const CXXMethodDecl 
*LHS,
 bool VCallOffsetMap::MethodsCanShareVCallOffset(const CXXMethodDecl *LHS,
 const CXXMethodDecl *RHS) {
   assert(VTableContextBase::hasVtableSlot(LHS) && "LHS must be virtual!");
-  assert(VTableContextBase::hasVtableSlot(RHS) && "LHS must be virtual!");
+  assert(VTableContextBase::hasVtableSlot(RHS) && "RHS must be virtual!");
 
   // A destructor can share a vcall offset with another destructor.
   if (isa(LHS))



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[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

2024-09-11 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/107817
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[clang] [RISCV] Emit predefined macro __riscv_cmodel_large for large code model (PR #108131)

2024-09-11 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/108131

>From 5874d7163114eda6e3c5b0fa50839af0eec4e48b Mon Sep 17 00:00:00 2001
From: patrick 
Date: Fri, 26 Nov 2021 15:09:08 +0800
Subject: [PATCH] [RISCV] Emit predefined macro __riscv_cmodel_large for large
 code model.

---
 clang/lib/Basic/Targets/RISCV.cpp  | 2 ++
 clang/test/Preprocessor/riscv-cmodel.c | 9 +
 2 files changed, 11 insertions(+)

diff --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index 6f9d050fc71a90..223ac66b5f219d 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -146,6 +146,8 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions 
&Opts,
 Builder.defineMacro("__riscv_cmodel_medlow");
   else if (CodeModel == "medium")
 Builder.defineMacro("__riscv_cmodel_medany");
+  else if (CodeModel == "large")
+Builder.defineMacro("__riscv_cmodel_large");
 
   StringRef ABIName = getABI();
   if (ABIName == "ilp32f" || ABIName == "lp64f")
diff --git a/clang/test/Preprocessor/riscv-cmodel.c 
b/clang/test/Preprocessor/riscv-cmodel.c
index 45b9a93de6f78a..bd9aa23f5d5e27 100644
--- a/clang/test/Preprocessor/riscv-cmodel.c
+++ b/clang/test/Preprocessor/riscv-cmodel.c
@@ -15,6 +15,7 @@
 
 // CHECK-MEDLOW: #define __riscv_cmodel_medlow 1
 // CHECK-MEDLOW-NOT: __riscv_cmodel_medany
+// CHECK-MEDLOW-NOT: __riscv_cmodel_large
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
 // RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
@@ -28,3 +29,11 @@
 
 // CHECK-MEDANY: #define __riscv_cmodel_medany 1
 // CHECK-MEDANY-NOT: __riscv_cmodel_medlow
+// CHECK-MEDANY-NOT: __riscv_cmodel_large
+
+// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=large -o - | FileCheck --check-prefix=CHECK-LARGE %s
+
+// CHECK-LARGE: #define __riscv_cmodel_large 1
+// CHECK-LARGE-NOT: __riscv_cmodel_medlow
+// CHECK-LARGE-NOT: __riscv_cmodel_medany

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[clang] [RISCV] Emit predefined macro __riscv_cmodel_large for large code model (PR #108131)

2024-09-12 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/108131
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[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-13 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/111653
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[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-10 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/111653

>From 80768f580d4ef6b9841b22ee5b287a87d9f25951 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 9 Oct 2024 11:37:46 +0800
Subject: [PATCH 1/2] [RISCV] Add support for inline asm constraint vd

It constrains vector registers excluding v0.

This patch also adds a testcase for constraints vr, vd and vm.
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   | 15 -
 .../CodeGen/RISCV/inline-asm-v-constraint.ll  | 66 +++
 2 files changed, 80 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 463887b8b55e61..0c8fd324edd1cf 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20340,7 +20340,7 @@ RISCVTargetLowering::getConstraintType(StringRef 
Constraint) const {
   return C_Other;
 }
   } else {
-if (Constraint == "vr" || Constraint == "vm")
+if (Constraint == "vr" || Constraint == "vd" || Constraint == "vm")
   return C_RegisterClass;
   }
   return TargetLowering::getConstraintType(Constraint);
@@ -20388,6 +20388,19 @@ 
RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
 return std::make_pair(0U, RC);
 }
+  } else if (Constraint == "vd") {
+for (const auto *RC :
+ {&RISCV::VRNoV0RegClass, &RISCV::VRM2NoV0RegClass,
+  &RISCV::VRM4NoV0RegClass, &RISCV::VRM8NoV0RegClass,
+  &RISCV::VRN2M1NoV0RegClass, &RISCV::VRN3M1NoV0RegClass,
+  &RISCV::VRN4M1NoV0RegClass, &RISCV::VRN5M1NoV0RegClass,
+  &RISCV::VRN6M1NoV0RegClass, &RISCV::VRN7M1NoV0RegClass,
+  &RISCV::VRN8M1NoV0RegClass, &RISCV::VRN2M2NoV0RegClass,
+  &RISCV::VRN3M2NoV0RegClass, &RISCV::VRN4M2NoV0RegClass,
+  &RISCV::VRN2M4NoV0RegClass}) {
+  if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
+return std::make_pair(0U, RC);
+}
   } else if (Constraint == "vm") {
 if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
   return std::make_pair(0U, &RISCV::VMV0RegClass);
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll 
b/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll
new file mode 100644
index 00..c04e4fea7b2c29
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll
@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+define  @constraint_vr( %0,  %1) nounwind {
+; RV32I-LABEL: constraint_vr:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:#APP
+; RV32I-NEXT:vadd.vv v8, v8, v9
+; RV32I-NEXT:#NO_APP
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: constraint_vr:
+; RV64I:   # %bb.0:
+; RV64I-NEXT:#APP
+; RV64I-NEXT:vadd.vv v8, v8, v9
+; RV64I-NEXT:#NO_APP
+; RV64I-NEXT:ret
+  %a = tail call  asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(
+ %0,  %1)
+  ret  %a
+}
+
+define  @constraint_vd( %0,  %1) nounwind {
+; RV32I-LABEL: constraint_vd:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:#APP
+; RV32I-NEXT:vadd.vv v8, v8, v9
+; RV32I-NEXT:#NO_APP
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: constraint_vd:
+; RV64I:   # %bb.0:
+; RV64I-NEXT:#APP
+; RV64I-NEXT:vadd.vv v8, v8, v9
+; RV64I-NEXT:#NO_APP
+; RV64I-NEXT:ret
+  %a = tail call  asm "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"(
+ %0,  %1)
+  ret  %a
+}
+
+define  @constraint_vm( %0,  %1) nounwind {
+; RV32I-LABEL: constraint_vm:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:vmv1r.v v9, v0
+; RV32I-NEXT:vmv1r.v v0, v8
+; RV32I-NEXT:#APP
+; RV32I-NEXT:vadd.vv v0, v9, v0
+; RV32I-NEXT:#NO_APP
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: constraint_vm:
+; RV64I:   # %bb.0:
+; RV64I-NEXT:vmv1r.v v9, v0
+; RV64I-NEXT:vmv1r.v v0, v8
+; RV64I-NEXT:#APP
+; RV64I-NEXT:vadd.vv v0, v9, v0
+; RV64I-NEXT:#NO_APP
+; RV64I-NEXT:ret
+  %a = tail call  asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vm"(
+ %0,  %1)
+  ret  %a
+}

>From 0212fb8ba0e3ea07a7216434f73efc77afe08953 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 11 Oct 2024 08:38:30 +0800
Subject: [PATCH 2/2] Add the change for vd in clang

---
 clang/lib/Basic/Targets/RISCV.cpp   | 2 +-
 clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c | 8 
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index 2a225820208c8c..870f0f38bc3057 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -102,7 +102,7 @@ bool RISCVTargetInfo::validate

[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

2024-10-17 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/112827

>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH 1/3] [RISCV] Check if v extension is enabled by the function
 features for the builtins not in Zve64*.

Fixes: https://github.com/llvm/llvm-project/issues/109694
---
 clang/lib/Sema/SemaRISCV.cpp | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3da4b515b1b114..3f1c2999286f3f 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -623,7 +623,12 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo 
&TI,
 ASTContext::BuiltinVectorTypeInfo Info = Context.getBuiltinVectorTypeInfo(
 TheCall->getType()->castAs());
 
-if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v"))
+const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+llvm::StringMap FunctionFeatureMap;
+Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
+
+if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
+&& !FunctionFeatureMap.lookup("v"))
   return Diag(TheCall->getBeginLoc(),
   diag::err_riscv_builtin_requires_extension)
  << /* IsExtension */ true << TheCall->getSourceRange() << "v";

>From ef6850dc40ad19fead0b8eecac8a0676d66df292 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 18 Oct 2024 11:43:55 +0800
Subject: [PATCH 2/3] clang-format

---
 clang/lib/Sema/SemaRISCV.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3f1c2999286f3f..d1ccc2774152b1 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -627,8 +627,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo 
&TI,
 llvm::StringMap FunctionFeatureMap;
 Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
 
-if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
-&& !FunctionFeatureMap.lookup("v"))
+if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v") &&
+!FunctionFeatureMap.lookup("v"))
   return Diag(TheCall->getBeginLoc(),
   diag::err_riscv_builtin_requires_extension)
  << /* IsExtension */ true << TheCall->getSourceRange() << "v";

>From 9958a5e8068113106974ca913bed7fb5ff90462e Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 18 Oct 2024 14:03:41 +0800
Subject: [PATCH 3/3] Add testcase

---
 clang/test/CodeGen/RISCV/riscv-func-attr-target.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c 
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index aeddbc4ebf6895..1a40cb72575926 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -65,6 +65,13 @@ void test_rvv_f64_type_w_zve64d() {
   vfloat64m1_t v;
 }
 
+__attribute__((target("arch=+v")))
+vint64m1_t test_rvv_vmulh_eew64_w_v(vint64m1_t a, vint64m1_t b) {
+// CHECK-LABEL: test_rvv_vmulh_eew64_w_v
+// CHECK-SAME: #13
+  return __riscv_vmulh_vv_i64m1(a, b, 2);
+}
+
 //.
 // CHECK: attributes #0 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa"
 }
 // CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" 
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 "tune-cpu"="generic-rv64" }
@@ -79,3 +86,4 @@ void test_rvv_f64_type_w_zve64d() {
 // CHECK: attributes #9 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
 // CHECK: attributes #11 = { 
{{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
 // CHECK: attributes #12 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #13 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 }

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[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

2024-10-17 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/112827

>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH 1/2] [RISCV] Check if v extension is enabled by the function
 features for the builtins not in Zve64*.

Fixes: https://github.com/llvm/llvm-project/issues/109694
---
 clang/lib/Sema/SemaRISCV.cpp | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3da4b515b1b114..3f1c2999286f3f 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -623,7 +623,12 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo 
&TI,
 ASTContext::BuiltinVectorTypeInfo Info = Context.getBuiltinVectorTypeInfo(
 TheCall->getType()->castAs());
 
-if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v"))
+const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+llvm::StringMap FunctionFeatureMap;
+Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
+
+if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
+&& !FunctionFeatureMap.lookup("v"))
   return Diag(TheCall->getBeginLoc(),
   diag::err_riscv_builtin_requires_extension)
  << /* IsExtension */ true << TheCall->getSourceRange() << "v";

>From ef6850dc40ad19fead0b8eecac8a0676d66df292 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 18 Oct 2024 11:43:55 +0800
Subject: [PATCH 2/2] clang-format

---
 clang/lib/Sema/SemaRISCV.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3f1c2999286f3f..d1ccc2774152b1 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -627,8 +627,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo 
&TI,
 llvm::StringMap FunctionFeatureMap;
 Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
 
-if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
-&& !FunctionFeatureMap.lookup("v"))
+if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v") &&
+!FunctionFeatureMap.lookup("v"))
   return Diag(TheCall->getBeginLoc(),
   diag::err_riscv_builtin_requires_extension)
  << /* IsExtension */ true << TheCall->getSourceRange() << "v";

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[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

2024-10-17 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/112827
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[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

2024-10-17 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/112827

>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH 1/2] [RISCV] Check if v extension is enabled by the function
 features for the builtins not in Zve64*.

Fixes: https://github.com/llvm/llvm-project/issues/109694
---
 clang/lib/Sema/SemaRISCV.cpp | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3da4b515b1b114..3f1c2999286f3f 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -623,7 +623,12 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo 
&TI,
 ASTContext::BuiltinVectorTypeInfo Info = Context.getBuiltinVectorTypeInfo(
 TheCall->getType()->castAs());
 
-if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v"))
+const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+llvm::StringMap FunctionFeatureMap;
+Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
+
+if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
+&& !FunctionFeatureMap.lookup("v"))
   return Diag(TheCall->getBeginLoc(),
   diag::err_riscv_builtin_requires_extension)
  << /* IsExtension */ true << TheCall->getSourceRange() << "v";

>From ef6850dc40ad19fead0b8eecac8a0676d66df292 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 18 Oct 2024 11:43:55 +0800
Subject: [PATCH 2/2] clang-format

---
 clang/lib/Sema/SemaRISCV.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3f1c2999286f3f..d1ccc2774152b1 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -627,8 +627,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo 
&TI,
 llvm::StringMap FunctionFeatureMap;
 Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
 
-if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
-&& !FunctionFeatureMap.lookup("v"))
+if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v") &&
+!FunctionFeatureMap.lookup("v"))
   return Diag(TheCall->getBeginLoc(),
   diag::err_riscv_builtin_requires_extension)
  << /* IsExtension */ true << TheCall->getSourceRange() << "v";

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[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

2024-10-17 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/112827

Fixes: https://github.com/llvm/llvm-project/issues/109694

>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH] [RISCV] Check if v extension is enabled by the function
 features for the builtins not in Zve64*.

Fixes: https://github.com/llvm/llvm-project/issues/109694
---
 clang/lib/Sema/SemaRISCV.cpp | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3da4b515b1b114..3f1c2999286f3f 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -623,7 +623,12 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo 
&TI,
 ASTContext::BuiltinVectorTypeInfo Info = Context.getBuiltinVectorTypeInfo(
 TheCall->getType()->castAs());
 
-if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v"))
+const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+llvm::StringMap FunctionFeatureMap;
+Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
+
+if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
+&& !FunctionFeatureMap.lookup("v"))
   return Diag(TheCall->getBeginLoc(),
   diag::err_riscv_builtin_requires_extension)
  << /* IsExtension */ true << TheCall->getSourceRange() << "v";

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[clang] [RISCV][Clang] Add RequiredFeatures to zvfh intrinsics (PR #115436)

2024-11-10 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/115436
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[clang] [RISCV][test] Fix incorrect check prefix in riscv32-toolchain.c and riscv64-toolchain.c. (PR #109390)

2024-09-22 Thread Jim Lin via cfe-commits


https://github.com/tclin914 edited 
https://github.com/llvm/llvm-project/pull/109390
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[clang] [RISCV][test] Fix incorrect check prefix in riscv32-toolchain.c and riscv64-toolchain.c. (PR #109390)

2024-09-22 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/109390
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[clang] [RISCV] Fix incorrect check prefix in riscv32-toolchain.c and riscv64-toolchain.c. NFC. (PR #109390)

2024-09-20 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/109390

None

>From 6de7650ee341546d5f67c4918bce4f6901452818 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Fri, 20 Sep 2024 16:39:05 +0800
Subject: [PATCH] [RISCV] Fix incorrect check prefix in riscv32-toolchain.c and
 riscv64-toolchain.c. NFC.

---
 clang/test/Driver/riscv32-toolchain.c | 2 +-
 clang/test/Driver/riscv64-toolchain.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/test/Driver/riscv32-toolchain.c 
b/clang/test/Driver/riscv32-toolchain.c
index 322a6ca2840fb9..50db13f8294c19 100644
--- a/clang/test/Driver/riscv32-toolchain.c
+++ b/clang/test/Driver/riscv32-toolchain.c
@@ -23,7 +23,7 @@
 
 // C-RV32-BAREMETAL-ILP32: 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin/riscv32-unknown-elf-ld"
 // C-RV32-BAREMETAL-ILP32: 
"--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
-// C-RV64-BAREMETAL-LP64-SAME: "-X"
+// C-RV32-BAREMETAL-ILP32: "-X"
 // C-RV32-BAREMETAL-ILP32: 
"{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib/crt0.o"
 // C-RV32-BAREMETAL-ILP32: 
"{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/crtbegin.o"
 // C-RV32-BAREMETAL-ILP32: 
"-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1"
diff --git a/clang/test/Driver/riscv64-toolchain.c 
b/clang/test/Driver/riscv64-toolchain.c
index b3216de3075400..06d5f50f3f4086 100644
--- a/clang/test/Driver/riscv64-toolchain.c
+++ b/clang/test/Driver/riscv64-toolchain.c
@@ -23,7 +23,7 @@
 
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../../../bin/riscv64-unknown-elf-ld"
 // C-RV64-BAREMETAL-LP64: 
"--sysroot={{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf"
-// C-RV64-BAREMETAL-LP64-SAME: "-X"
+// C-RV64-BAREMETAL-LP64: "-X"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf/lib/crt0.o"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/crtbegin.o"
 // C-RV64-BAREMETAL-LP64: 
"-L{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1"

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[clang] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vfrsqrt7. NFC (PR #115269)

2024-11-06 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/115269

None

>From d6a33142b94a6ad0ca747d330a4ac4b3f7a476af Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Thu, 7 Nov 2024 13:47:09 +0800
Subject: [PATCH] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin
 vfrsqrt7. NFC

---
 clang/include/clang/Basic/riscv_vector.td| 2 +-
 clang/include/clang/Basic/riscv_vector_common.td | 8 
 2 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/clang/include/clang/Basic/riscv_vector.td 
b/clang/include/clang/Basic/riscv_vector.td
index 1387494c4aeb00..74b9a7fc753a62 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1859,7 +1859,7 @@ let ManualCodegen = [{
 }
 
 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
-def vfrsqrt7 : RVVFloatingUnaryVVBuiltin;
+defm vfrsqrt7 : RVVOutBuiltinSet<"vfrsqrt7", "xfd", [["v", "v", "vv"]]>;
 
 // 13.11. Vector Floating-Point MIN/MAX Instructions
 defm vfmin : RVVFloatingBinBuiltinSet;
diff --git a/clang/include/clang/Basic/riscv_vector_common.td 
b/clang/include/clang/Basic/riscv_vector_common.td
index 33f6441217a5e1..b38ca7341361c4 100644
--- a/clang/include/clang/Basic/riscv_vector_common.td
+++ b/clang/include/clang/Basic/riscv_vector_common.td
@@ -576,14 +576,6 @@ let UnMaskedPolicyScheme = HasPassthruOperand,
   }
 }
 
-class RVVFloatingUnaryBuiltin
-: RVVOutBuiltin {
-  let Name = NAME # "_" # builtin_suffix;
-}
-
-class RVVFloatingUnaryVVBuiltin : RVVFloatingUnaryBuiltin<"v", "v", "vv">;
-
 class RVVConvBuiltin
 : RVVBuiltin {

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[clang] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vfrsqrt7. NFC (PR #115269)

2024-11-07 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/115269
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[clang] [lld] [llvm] [RISCV] Make A implies Zaamo and Zalrsc (PR #116907)

2024-11-19 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/116907

Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.

>From 91aea6122d192d72e078408366b46b3dab5a37a9 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 20 Nov 2024 10:31:58 +0800
Subject: [PATCH] [RISCV] Make A implies Zaamo and Zalrsc

Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.
---
 .../CodeGen/RISCV/riscv-func-attr-target.c| 20 +-
 lld/test/ELF/lto/riscv-attributes.ll  |  6 +--
 lld/test/ELF/riscv-attributes.s   | 16 
 llvm/lib/Target/RISCV/RISCVFeatures.td| 39 ++-
 llvm/test/CodeGen/RISCV/attributes.ll | 20 +-
 llvm/test/MC/RISCV/attribute-arch.s   | 14 +++
 llvm/test/MC/RISCV/attribute.s|  4 +-
 7 files changed, 60 insertions(+), 59 deletions(-)

diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c 
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index aeddbc4ebf6895..3e9c1d9229a66b 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -66,16 +66,16 @@ void test_rvv_f64_type_w_zve64d() {
 }
 
 //.
-// CHECK: attributes #0 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" 
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 "tune-cpu"="generic-rv64" }
-// CHECK: attributes #2 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
-// CHECK: attributes #3 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
 }
+// CHECK: attributes #0 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" 
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 "tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
+// CHECK: attributes #3 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
 }
 // Make sure we append negative features if we override the arch
-// CHECK: attributes #4 = { 
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
+// CHECK: attributes #4 = { 
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
 // CHECK: attributes #5 = { 
{{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
 // CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #9 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #11 = { 
{{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #12 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
+// CHECK: attributes #9 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #11 = { 
{{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #12 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restor

[clang] [RISCV][Clang] Add RequiredFeatures to zvfh intrinsics (PR #115436)

2024-11-08 Thread Jim Lin via cfe-commits


https://github.com/tclin914 edited 
https://github.com/llvm/llvm-project/pull/115436
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[clang] [lld] [llvm] [RISCV] Make A implies Zaamo and Zalrsc (PR #116907)

2024-11-21 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/116907

>From 08523139b789c836b22677f8e16b79910de601e4 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 20 Nov 2024 10:31:58 +0800
Subject: [PATCH 1/4] [RISCV] Make A implies Zaamo and Zalrsc

Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.
---
 .../CodeGen/RISCV/riscv-func-attr-target.c| 20 +-
 lld/test/ELF/lto/riscv-attributes.ll  |  6 +--
 lld/test/ELF/riscv-attributes.s   | 16 
 llvm/lib/Target/RISCV/RISCVFeatures.td| 39 ++-
 llvm/test/CodeGen/RISCV/attributes.ll | 20 +-
 llvm/test/MC/RISCV/attribute-arch.s   | 14 +++
 llvm/test/MC/RISCV/attribute.s|  4 +-
 7 files changed, 60 insertions(+), 59 deletions(-)

diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c 
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index aeddbc4ebf6895..3e9c1d9229a66b 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -66,16 +66,16 @@ void test_rvv_f64_type_w_zve64d() {
 }
 
 //.
-// CHECK: attributes #0 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" 
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 "tune-cpu"="generic-rv64" }
-// CHECK: attributes #2 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
-// CHECK: attributes #3 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
 }
+// CHECK: attributes #0 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" 
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 "tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
+// CHECK: attributes #3 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
 }
 // Make sure we append negative features if we override the arch
-// CHECK: attributes #4 = { 
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
+// CHECK: attributes #4 = { 
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
 // CHECK: attributes #5 = { 
{{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
 // CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #9 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #11 = { 
{{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #12 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
+// CHECK: attributes #9 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #11 = { 
{{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #12 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,

[clang] [lld] [llvm] [RISCV] Make A implies Zaamo and Zalrsc (PR #116907)

2024-11-20 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/116907

>From 08523139b789c836b22677f8e16b79910de601e4 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 20 Nov 2024 10:31:58 +0800
Subject: [PATCH 1/3] [RISCV] Make A implies Zaamo and Zalrsc

Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.
---
 .../CodeGen/RISCV/riscv-func-attr-target.c| 20 +-
 lld/test/ELF/lto/riscv-attributes.ll  |  6 +--
 lld/test/ELF/riscv-attributes.s   | 16 
 llvm/lib/Target/RISCV/RISCVFeatures.td| 39 ++-
 llvm/test/CodeGen/RISCV/attributes.ll | 20 +-
 llvm/test/MC/RISCV/attribute-arch.s   | 14 +++
 llvm/test/MC/RISCV/attribute.s|  4 +-
 7 files changed, 60 insertions(+), 59 deletions(-)

diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c 
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index aeddbc4ebf6895..3e9c1d9229a66b 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -66,16 +66,16 @@ void test_rvv_f64_type_w_zve64d() {
 }
 
 //.
-// CHECK: attributes #0 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" 
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 "tune-cpu"="generic-rv64" }
-// CHECK: attributes #2 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
-// CHECK: attributes #3 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
 }
+// CHECK: attributes #0 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" 
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 "tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
+// CHECK: attributes #3 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
 }
 // Make sure we append negative features if we override the arch
-// CHECK: attributes #4 = { 
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
+// CHECK: attributes #4 = { 
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
 // CHECK: attributes #5 = { 
{{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
 }
 // CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
-// CHECK: attributes #9 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #11 = { 
{{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
-// CHECK: attributes #12 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" 
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
 }
+// CHECK: attributes #9 = { 
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #11 = { 
{{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
 }
+// CHECK: attributes #12 = { 
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

2025-02-06 Thread Jim Lin via cfe-commits



@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo 
&TI,
   }
   }
 
+  auto checkVsetvl = [&](unsigned SEWOffset,
+unsigned LMULOffset) -> bool {
+const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+llvm::StringMap FunctionFeatureMap;
+Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
+llvm::APSInt SEWResult;
+llvm::APSInt LMULResult;
+if (SemaRef.BuiltinConstantArg(TheCall, SEWOffset, SEWResult) ||
+SemaRef.BuiltinConstantArg(TheCall, LMULOffset, LMULResult))
+  return true;
+int SEWValue = SEWResult.getSExtValue();
+int LMULValue = LMULResult.getSExtValue();
+if (((SEWValue == 0 && LMULValue == 5) ||  // e8mf8
+ (SEWValue == 1 && LMULValue == 6) ||  // e16mf4
+ (SEWValue == 2 && LMULValue == 7) ||  // e32mf2
+ (SEWValue == 3 && LMULValue == 0) ||  // e64m1
+ (SEWValue == 3 && LMULValue == 1) ||  // e64m2
+ (SEWValue == 3 && LMULValue == 2) ||  // e64m4
+ (SEWValue == 3 && LMULValue == 3)) && // e64m8
+(!TI.hasFeature("zve64x") && !FunctionFeatureMap.lookup("zve64x")))

tclin914 wrote:

Should we check for the feature `zvl64b`?

https://github.com/llvm/llvm-project/pull/126064
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[clang] [lld] [llvm] [RISCV] Make A implies Zaamo and Zalrsc (PR #116907)

2024-11-21 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/116907
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[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-09 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/135110

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler.

Relocation and fixup for the branch and gp-implied instructions will be added 
in a later patch.

>From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH] [RISCV] Add Andes XAndesperf (Andes Performance) extension.

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler.

Relocation and fixup for the branch and gp-implied instructions will be
added in a later patch.
---
 .../Driver/print-supported-extensions-riscv.c |   1 +
 llvm/docs/RISCVUsage.rst  |   3 +
 llvm/docs/ReleaseNotes.md |   1 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  56 ++-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  22 +-
 .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp |  23 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   9 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   |   1 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 358 ++
 llvm/test/CodeGen/RISCV/attributes.ll |   4 +
 llvm/test/CodeGen/RISCV/features-info.ll  |   1 +
 llvm/test/MC/RISCV/xandesperf-invalid.s   |  56 +++
 llvm/test/MC/RISCV/xandesperf-rv64-invalid.s  |  20 +
 llvm/test/MC/RISCV/xandesperf-rv64-valid.s|  34 ++
 llvm/test/MC/RISCV/xandesperf-valid.s | 105 +
 .../TargetParser/RISCVISAInfoTest.cpp |   1 +
 16 files changed, 673 insertions(+), 22 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
 create mode 100644 llvm/test/MC/RISCV/xandesperf-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-rv64-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-rv64-valid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index d06cedac5b1eb..f65bfcc2e44d6 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -154,6 +154,7 @@
 // CHECK-NEXT: svnapot  1.0   'Svnapot' (NAPOT Translation 
Contiguity)
 // CHECK-NEXT: svpbmt   1.0   'Svpbmt' (Page-Based Memory 
Types)
 // CHECK-NEXT: svvptc   1.0   'Svvptc' (Obviating 
Memory-Management Instructions after Marking PTEs Valid)
+// CHECK-NEXT: xandesperf   5.0   'XAndesPerf' (Andes 
Performance Extension)
 // CHECK-NEXT: xcvalu   1.0   'XCValu' (CORE-V ALU 
Operations)
 // CHECK-NEXT: xcvbi1.0   'XCVbi' (CORE-V Immediate 
Branching)
 // CHECK-NEXT: xcvbitmanip  1.0   'XCVbitmanip' (CORE-V Bit 
Manipulation)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index cda7e5fec8488..118f45abc1c31 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -503,6 +503,9 @@ The current vendor extensions supported are:
 ``experimental-XRivosVizip``
   LLVM implements `version 0.1 of the Rivos Vector Register Zips extension 
specification `__.
 
+``XAndesPerf``
+  LLVM implements `version 5.0.0 of the Andes Performance Extension 
specification 
`
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 526d6b4002bba..6c219a5af8398 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -159,6 +159,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for ``.option exact``, which disables automatic 
compression,
   and branch and linker relaxation. This can be disabled with ``.option 
noexact``,
   which is also the default.
+* Adds assembler support for the Andes `XAndesperf` (Andes Performance 
extension).
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index c57c123ab01dc..3dafc21b84c21 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -536,19 +536,24 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   }
 
   // True if operand is a symbol with no modifiers, or a constant with no
-  // modifiers and isShiftedInt(Op).
-  template  bool isBareSimmNLsb0() const {
-int64_t Imm;
-RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
+  // mo

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-17 Thread Jim Lin via cfe-commits


tclin914 wrote:

> Do you have plan send PR to 
> https://github.com/riscv-non-isa/riscv-toolchain-conventions?

PR:
[https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/84](https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/84)



https://github.com/llvm/llvm-project/pull/135110
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[clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)

2025-04-21 Thread Jim Lin via cfe-commits



@@ -1453,6 +1454,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s
 // CHECK-SMCSRIND-EXT: __riscv_smcsrind  100{{$}}
 
+// RUN: %clang --target=riscv32 \

tclin914 wrote:

Put the test for  `smcntrpmf` above for `smcsrind`

https://github.com/llvm/llvm-project/pull/136556
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[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

2025-04-22 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/136670

Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU 
architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions.  They 
are developed by Andes Technology https://www.andestech.com, a RISC-V IP 
provider. 

The overviews for N45/NX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/ 
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/

Scheduling model will be implemented in a later PR.

>From df3a0b2bd9cb31fc8e252e250d3107dd1ac2cc0b Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Tue, 22 Apr 2025 10:12:23 +0800
Subject: [PATCH] [RISCV] Add Andes N45/NX45 processor definition

Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU
architecture with rv[32|64]imafdc_zba_zbb_zbs march.

The overviews for N45/NX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/

Scheduling model will be implemented in a later PR.
---
 clang/test/Driver/riscv-cpus.c| 34 +++
 .../test/Misc/target-invalid-cpu-note/riscv.c | 12 ---
 llvm/docs/ReleaseNotes.md |  1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 30 
 4 files changed, 73 insertions(+), 4 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index c2314efd34aa6..19da8ede26a40 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -692,3 +692,37 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
 // MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck 
-check-prefix=MCPU-ANDES-N45 %s
+// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck 
-check-prefix=MTUNE-ANDES-N45 %s
+// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck 
-check-prefix=MCPU-ANDES-NX45 %s
+// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck 
-check-prefix=MTUNE-ANDES-NX45 %s
+// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c 
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 199916f70c14f..cd8a8bf95dd7a 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -5,7 +5,8 @@
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
 // RISCV32-NEXT: note: valid target CPU values are:
-// RISCV32-SAME: {{^}} generic-rv32
+// RISCV32-SAME: {{^}} andes-n45
+// RISCV32-SAME: {{^}}, generic-rv32
 // RISCV32-SAME: {{^}}, rocket-rv32
 // RISCV32-SAME: {{^}}, rp2350-hazard3
 // RISCV32-SAME: {{^}}, sifive-e20
@@ -24,7 +25,8 @@
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64-NEXT: note: valid target CPU values are:
-// RISCV64-SAME: {{^}} generic-rv64
+// RISCV64-SAME: {{^}} andes-nx45
+// RISCV64-SAME: {{^}}, generic-rv64
 // RISCV64-SAME: {{^}}, mips-p8700
 // RISCV64-SAME: {{^}}, rocket-rv64
 // RISCV64-SAME: {{^}}, sifive-p450
@@ -52,7 +54,8 @@
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV32-NEXT: note: valid t

[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

2025-04-22 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/136670
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[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-28 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/135110
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[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

2025-04-22 Thread Jim Lin via cfe-commits



@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
   FeatureStdExtZbkb,
   FeatureStdExtZcb,
   FeatureStdExtZcmp]>;
+
+def ANDES_N45 : RISCVProcessorModel<"andes-n45",
+NoSchedModel,
+[Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs]>;

tclin914 wrote:

Done.

https://github.com/llvm/llvm-project/pull/136670
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[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

2025-04-22 Thread Jim Lin via cfe-commits



@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
   FeatureStdExtZbkb,
   FeatureStdExtZcb,
   FeatureStdExtZcmp]>;
+
+def ANDES_N45 : RISCVProcessorModel<"andes-n45",
+NoSchedModel,
+[Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs]>;
+
+def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
+ NoSchedModel,
+ [Feature64Bit,
+  FeatureStdExtI,
+  FeatureStdExtZicsr,
+  FeatureStdExtZifencei,
+  FeatureStdExtM,
+  FeatureStdExtA,
+  FeatureStdExtF,
+  FeatureStdExtD,
+  FeatureStdExtC,
+  FeatureStdExtZba,
+  FeatureStdExtZbb,
+  FeatureStdExtZbs]>;

tclin914 wrote:

Done.

https://github.com/llvm/llvm-project/pull/136670
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[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

2025-04-22 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/136670

>From df3a0b2bd9cb31fc8e252e250d3107dd1ac2cc0b Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Tue, 22 Apr 2025 10:12:23 +0800
Subject: [PATCH 1/2] [RISCV] Add Andes N45/NX45 processor definition

Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU
architecture with rv[32|64]imafdc_zba_zbb_zbs march.

The overviews for N45/NX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/

Scheduling model will be implemented in a later PR.
---
 clang/test/Driver/riscv-cpus.c| 34 +++
 .../test/Misc/target-invalid-cpu-note/riscv.c | 12 ---
 llvm/docs/ReleaseNotes.md |  1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 30 
 4 files changed, 73 insertions(+), 4 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index c2314efd34aa6..19da8ede26a40 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -692,3 +692,37 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
 // MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck 
-check-prefix=MCPU-ANDES-N45 %s
+// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck 
-check-prefix=MTUNE-ANDES-N45 %s
+// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck 
-check-prefix=MCPU-ANDES-NX45 %s
+// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck 
-check-prefix=MTUNE-ANDES-NX45 %s
+// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c 
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 199916f70c14f..cd8a8bf95dd7a 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -5,7 +5,8 @@
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
 // RISCV32-NEXT: note: valid target CPU values are:
-// RISCV32-SAME: {{^}} generic-rv32
+// RISCV32-SAME: {{^}} andes-n45
+// RISCV32-SAME: {{^}}, generic-rv32
 // RISCV32-SAME: {{^}}, rocket-rv32
 // RISCV32-SAME: {{^}}, rp2350-hazard3
 // RISCV32-SAME: {{^}}, sifive-e20
@@ -24,7 +25,8 @@
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64-NEXT: note: valid target CPU values are:
-// RISCV64-SAME: {{^}} generic-rv64
+// RISCV64-SAME: {{^}} andes-nx45
+// RISCV64-SAME: {{^}}, generic-rv64
 // RISCV64-SAME: {{^}}, mips-p8700
 // RISCV64-SAME: {{^}}, rocket-rv64
 // RISCV64-SAME: {{^}}, sifive-p450
@@ -52,7 +54,8 @@
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV32-NEXT: note: valid target CPU values are:
-// TUNE-RISCV32-SAME: {{^}} generic-rv32
+// TUNE-RISCV32-SAME: {{^}} andes-n45
+// TUNE-RISCV32-SAME: {{^}}, generic-rv32
 // TUNE-RISCV32-SAME: {{^}}, rocket-rv32
 // TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
 // TUNE-RISCV32-SAME: {{^}}, sifive-e20
@@ -75,7 +78,8 @@
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
 //

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-10 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/135110

>From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 1/4] [RISCV] Add Andes XAndesperf (Andes Performance)
 extension.

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler.

Relocation and fixup for the branch and gp-implied instructions will be
added in a later patch.
---
 .../Driver/print-supported-extensions-riscv.c |   1 +
 llvm/docs/RISCVUsage.rst  |   3 +
 llvm/docs/ReleaseNotes.md |   1 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  56 ++-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  22 +-
 .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp |  23 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   9 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   |   1 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 358 ++
 llvm/test/CodeGen/RISCV/attributes.ll |   4 +
 llvm/test/CodeGen/RISCV/features-info.ll  |   1 +
 llvm/test/MC/RISCV/xandesperf-invalid.s   |  56 +++
 llvm/test/MC/RISCV/xandesperf-rv64-invalid.s  |  20 +
 llvm/test/MC/RISCV/xandesperf-rv64-valid.s|  34 ++
 llvm/test/MC/RISCV/xandesperf-valid.s | 105 +
 .../TargetParser/RISCVISAInfoTest.cpp |   1 +
 16 files changed, 673 insertions(+), 22 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
 create mode 100644 llvm/test/MC/RISCV/xandesperf-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-rv64-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-rv64-valid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index d06cedac5b1eb..f65bfcc2e44d6 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -154,6 +154,7 @@
 // CHECK-NEXT: svnapot  1.0   'Svnapot' (NAPOT Translation 
Contiguity)
 // CHECK-NEXT: svpbmt   1.0   'Svpbmt' (Page-Based Memory 
Types)
 // CHECK-NEXT: svvptc   1.0   'Svvptc' (Obviating 
Memory-Management Instructions after Marking PTEs Valid)
+// CHECK-NEXT: xandesperf   5.0   'XAndesPerf' (Andes 
Performance Extension)
 // CHECK-NEXT: xcvalu   1.0   'XCValu' (CORE-V ALU 
Operations)
 // CHECK-NEXT: xcvbi1.0   'XCVbi' (CORE-V Immediate 
Branching)
 // CHECK-NEXT: xcvbitmanip  1.0   'XCVbitmanip' (CORE-V Bit 
Manipulation)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index cda7e5fec8488..118f45abc1c31 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -503,6 +503,9 @@ The current vendor extensions supported are:
 ``experimental-XRivosVizip``
   LLVM implements `version 0.1 of the Rivos Vector Register Zips extension 
specification `__.
 
+``XAndesPerf``
+  LLVM implements `version 5.0.0 of the Andes Performance Extension 
specification 
`
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 526d6b4002bba..6c219a5af8398 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -159,6 +159,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for ``.option exact``, which disables automatic 
compression,
   and branch and linker relaxation. This can be disabled with ``.option 
noexact``,
   which is also the default.
+* Adds assembler support for the Andes `XAndesperf` (Andes Performance 
extension).
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index c57c123ab01dc..3dafc21b84c21 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -536,19 +536,24 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   }
 
   // True if operand is a symbol with no modifiers, or a constant with no
-  // modifiers and isShiftedInt(Op).
-  template  bool isBareSimmNLsb0() const {
-int64_t Imm;
-RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
+  // modifiers and isShiftedInt(Op).
+  template  bool isBareSimmNLsbK() const {
 if (!isImm())
   return false;
-bool IsConstantImm = evaluateConstantImm(getImm(), Imm);
-bool IsValid;
-if (!IsConstantImm)
-  IsVal

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-10 Thread Jim Lin via cfe-commits



@@ -0,0 +1,358 @@
+//===-- RISCVInstrInfoXAndes.td *- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by Andes Technology.
+//
+//===--===//
+
+//===--===//
+// Operand and SDNode transformation definitions.
+//===--===//
+
+// A 11-bit signed immediate where the least significant bit is zero.
+def simm11_lsb0 : Operand {
+  let ParserMatchClass = SImmAsmOperand<11, "Lsb0">;
+  let PrintMethod = "printBranchOperand";
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<11>";
+  let MCOperandPredicate = [{
+int64_t Imm;
+if (MCOp.evaluateAsConstantImm(Imm))
+  return isShiftedInt<10, 1>(Imm);
+return MCOp.isBareSymbolRef();
+  }];
+  let OperandType = "OPERAND_PCREL";
+}
+
+def simm18 : Operand {
+  let ParserMatchClass = SImmAsmOperand<18>;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeSImmOperand<18>";
+}
+
+def simm18_lsb0 : Operand {
+  let ParserMatchClass = SImmAsmOperand<18, "Lsb0">;
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<18>";
+}
+
+def simm19_lsb00 : Operand {
+  let ParserMatchClass = SImmAsmOperand<19, "Lsb00">;
+  let EncoderMethod = "getImmOpValueAsrN<2>";
+  let DecoderMethod = "decodeSImmOperandAndLslN<19, 2>";
+}
+
+def simm20_lsb000 : Operand {
+  let ParserMatchClass = SImmAsmOperand<20, "Lsb000">;
+  let EncoderMethod = "getImmOpValueAsrN<3>";
+  let DecoderMethod = "decodeSImmOperandAndLslN<20, 3>";
+}
+
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+class NDSRVInstBB
+: RVInst<(outs), (ins GPR:$rs1, uimmlog2xlen:$cimm, simm11_lsb0:$imm10),
+ opcodestr, "$rs1, $cimm, $imm10", [], InstFormatOther>,
+  Sched<[WriteJmp, ReadIALU]> {
+  bits<10> imm10;
+  bits<5> rs1;
+  bits<6> cimm;
+
+  let Inst{31} = imm10{9};
+  let Inst{30} = cs;
+  let Inst{29-25} = imm10{8-4};
+  let Inst{24-20} = cimm{4-0};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b111;
+  let Inst{11-8} = imm10{3-0};
+  let Inst{7} = cimm{5};
+  let Inst{6-0} = OPC_CUSTOM_2.Value;
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+  let isBranch = 1;
+  let isTerminator = 1;
+}
+
+class NDSRVInstBC funct3, string opcodestr>
+: RVInst<(outs), (ins GPR:$rs1, uimm7:$cimm, simm11_lsb0:$imm10),
+ opcodestr, "$rs1, $cimm, $imm10", [], InstFormatOther>,
+  Sched<[WriteJmp, ReadIALU]> {
+  bits<10> imm10;
+  bits<5> rs1;
+  bits<7> cimm;
+
+  let Inst{31} = imm10{9};
+  let Inst{30} = cimm{6};
+  let Inst{29-25} = imm10{8-4};
+  let Inst{24-20} = cimm{4-0};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-8} = imm10{3-0};
+  let Inst{7} = cimm{5};
+  let Inst{6-0} = OPC_CUSTOM_2.Value;
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+  let isBranch = 1;
+  let isTerminator = 1;
+}
+
+class NDSRVInstBFO funct3, string opcodestr>
+: RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimmlog2xlen:$msb, 
uimmlog2xlen:$lsb),
+ opcodestr, "$rd, $rs1, $msb, $lsb", [], InstFormatOther>,
+  Sched<[WriteIALU, ReadIALU]> {
+  bits<5> rd;
+  bits<5> rs1;
+  bits<6> msb;
+  bits<6> lsb;
+
+  let Inst{31-26} = msb;
+  let Inst{25-20} = lsb;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = OPC_CUSTOM_2.Value;
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class NDSRVInstRR funct7, string opcodestr>
+: RVInstR,
+  Sched<[WriteIALU, ReadIALU, ReadIALU]> {
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;

tclin914 wrote:

Remove it. Thanks.

https://github.com/llvm/llvm-project/pull/135110
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[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-10 Thread Jim Lin via cfe-commits



@@ -535,21 +540,29 @@ RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, 
unsigned OpNo,
   }
 }
 
-uint64_t
-RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
+template 
+unsigned
+RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
   SmallVectorImpl &Fixups,
   const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
 
   if (MO.isImm()) {
-uint64_t Res = MO.getImm();
-assert((Res & 1) == 0 && "LSB is non-zero");
-return Res >> 1;
+unsigned Res = MO.getImm();

tclin914 wrote:

It is my typo. Thanks.

https://github.com/llvm/llvm-project/pull/135110
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[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-10 Thread Jim Lin via cfe-commits



@@ -940,6 +947,14 @@ struct RISCVOperand final : public MCParsedAsmOperand {
 [](int64_t Imm) { return Imm != INT64_MIN && isInt<5>(Imm - 1); });
   }
 
+  bool isSImm18() const { return isBareSimmNLsbK<18, 0>(); }
+
+  bool isSImm18Lsb0() const { return isBareSimmNLsb0<18>(); }
+
+  bool isSImm19Lsb00() const { return isBareSimmNLsbK<19, 2>(); }
+
+  bool isSImm20Lsb000() const { return isBareSimmNLsbK<20, 3>(); }

tclin914 wrote:

Done. Thanks.

https://github.com/llvm/llvm-project/pull/135110
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[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-13 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/135110

>From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 1/7] [RISCV] Add Andes XAndesperf (Andes Performance)
 extension.

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler.

Relocation and fixup for the branch and gp-implied instructions will be
added in a later patch.
---
 .../Driver/print-supported-extensions-riscv.c |   1 +
 llvm/docs/RISCVUsage.rst  |   3 +
 llvm/docs/ReleaseNotes.md |   1 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  56 ++-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  22 +-
 .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp |  23 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   9 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   |   1 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 358 ++
 llvm/test/CodeGen/RISCV/attributes.ll |   4 +
 llvm/test/CodeGen/RISCV/features-info.ll  |   1 +
 llvm/test/MC/RISCV/xandesperf-invalid.s   |  56 +++
 llvm/test/MC/RISCV/xandesperf-rv64-invalid.s  |  20 +
 llvm/test/MC/RISCV/xandesperf-rv64-valid.s|  34 ++
 llvm/test/MC/RISCV/xandesperf-valid.s | 105 +
 .../TargetParser/RISCVISAInfoTest.cpp |   1 +
 16 files changed, 673 insertions(+), 22 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
 create mode 100644 llvm/test/MC/RISCV/xandesperf-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-rv64-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-rv64-valid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index d06cedac5b1eb..f65bfcc2e44d6 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -154,6 +154,7 @@
 // CHECK-NEXT: svnapot  1.0   'Svnapot' (NAPOT Translation 
Contiguity)
 // CHECK-NEXT: svpbmt   1.0   'Svpbmt' (Page-Based Memory 
Types)
 // CHECK-NEXT: svvptc   1.0   'Svvptc' (Obviating 
Memory-Management Instructions after Marking PTEs Valid)
+// CHECK-NEXT: xandesperf   5.0   'XAndesPerf' (Andes 
Performance Extension)
 // CHECK-NEXT: xcvalu   1.0   'XCValu' (CORE-V ALU 
Operations)
 // CHECK-NEXT: xcvbi1.0   'XCVbi' (CORE-V Immediate 
Branching)
 // CHECK-NEXT: xcvbitmanip  1.0   'XCVbitmanip' (CORE-V Bit 
Manipulation)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index cda7e5fec8488..118f45abc1c31 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -503,6 +503,9 @@ The current vendor extensions supported are:
 ``experimental-XRivosVizip``
   LLVM implements `version 0.1 of the Rivos Vector Register Zips extension 
specification `__.
 
+``XAndesPerf``
+  LLVM implements `version 5.0.0 of the Andes Performance Extension 
specification 
`
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 526d6b4002bba..6c219a5af8398 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -159,6 +159,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for ``.option exact``, which disables automatic 
compression,
   and branch and linker relaxation. This can be disabled with ``.option 
noexact``,
   which is also the default.
+* Adds assembler support for the Andes `XAndesperf` (Andes Performance 
extension).
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index c57c123ab01dc..3dafc21b84c21 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -536,19 +536,24 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   }
 
   // True if operand is a symbol with no modifiers, or a constant with no
-  // modifiers and isShiftedInt(Op).
-  template  bool isBareSimmNLsb0() const {
-int64_t Imm;
-RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
+  // modifiers and isShiftedInt(Op).
+  template  bool isBareSimmNLsbK() const {
 if (!isImm())
   return false;
-bool IsConstantImm = evaluateConstantImm(getImm(), Imm);
-bool IsValid;
-if (!IsConstantImm)
-  IsVal

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

2025-04-14 Thread Jim Lin via cfe-commits


https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/135110

>From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 1/8] [RISCV] Add Andes XAndesperf (Andes Performance)
 extension.

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler.

Relocation and fixup for the branch and gp-implied instructions will be
added in a later patch.
---
 .../Driver/print-supported-extensions-riscv.c |   1 +
 llvm/docs/RISCVUsage.rst  |   3 +
 llvm/docs/ReleaseNotes.md |   1 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  56 ++-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  22 +-
 .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp |  23 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   9 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   |   1 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 358 ++
 llvm/test/CodeGen/RISCV/attributes.ll |   4 +
 llvm/test/CodeGen/RISCV/features-info.ll  |   1 +
 llvm/test/MC/RISCV/xandesperf-invalid.s   |  56 +++
 llvm/test/MC/RISCV/xandesperf-rv64-invalid.s  |  20 +
 llvm/test/MC/RISCV/xandesperf-rv64-valid.s|  34 ++
 llvm/test/MC/RISCV/xandesperf-valid.s | 105 +
 .../TargetParser/RISCVISAInfoTest.cpp |   1 +
 16 files changed, 673 insertions(+), 22 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
 create mode 100644 llvm/test/MC/RISCV/xandesperf-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-rv64-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-rv64-valid.s
 create mode 100644 llvm/test/MC/RISCV/xandesperf-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index d06cedac5b1eb..f65bfcc2e44d6 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -154,6 +154,7 @@
 // CHECK-NEXT: svnapot  1.0   'Svnapot' (NAPOT Translation 
Contiguity)
 // CHECK-NEXT: svpbmt   1.0   'Svpbmt' (Page-Based Memory 
Types)
 // CHECK-NEXT: svvptc   1.0   'Svvptc' (Obviating 
Memory-Management Instructions after Marking PTEs Valid)
+// CHECK-NEXT: xandesperf   5.0   'XAndesPerf' (Andes 
Performance Extension)
 // CHECK-NEXT: xcvalu   1.0   'XCValu' (CORE-V ALU 
Operations)
 // CHECK-NEXT: xcvbi1.0   'XCVbi' (CORE-V Immediate 
Branching)
 // CHECK-NEXT: xcvbitmanip  1.0   'XCVbitmanip' (CORE-V Bit 
Manipulation)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index cda7e5fec8488..118f45abc1c31 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -503,6 +503,9 @@ The current vendor extensions supported are:
 ``experimental-XRivosVizip``
   LLVM implements `version 0.1 of the Rivos Vector Register Zips extension 
specification `__.
 
+``XAndesPerf``
+  LLVM implements `version 5.0.0 of the Andes Performance Extension 
specification 
`
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 526d6b4002bba..6c219a5af8398 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -159,6 +159,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for ``.option exact``, which disables automatic 
compression,
   and branch and linker relaxation. This can be disabled with ``.option 
noexact``,
   which is also the default.
+* Adds assembler support for the Andes `XAndesperf` (Andes Performance 
extension).
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index c57c123ab01dc..3dafc21b84c21 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -536,19 +536,24 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   }
 
   // True if operand is a symbol with no modifiers, or a constant with no
-  // modifiers and isShiftedInt(Op).
-  template  bool isBareSimmNLsb0() const {
-int64_t Imm;
-RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
+  // modifiers and isShiftedInt(Op).
+  template  bool isBareSimmNLsbK() const {
 if (!isImm())
   return false;
-bool IsConstantImm = evaluateConstantImm(getImm(), Imm);
-bool IsValid;
-if (!IsConstantImm)
-  IsVal

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

2025-04-15 Thread Jim Lin via cfe-commits



@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : 
RISCVProcessorModel<"xiangshan-nanhu",
 TuneZExtWFusion,
 TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+  NoSchedModel,

tclin914 wrote:

indentation alignment

https://github.com/llvm/llvm-project/pull/123193
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[clang] 56097bc - [RISCV][Clang] Fix typo: RISCXCVBuiltin -> RISCVXCVBuiltin. NFC.

2025-05-05 Thread Jim Lin via cfe-commits


Author: Jim Lin
Date: 2025-05-05T16:40:49+08:00
New Revision: 56097bce97b4f0a9717268e9ddc1bb72bc49390c

URL: 
https://github.com/llvm/llvm-project/commit/56097bce97b4f0a9717268e9ddc1bb72bc49390c
DIFF: 
https://github.com/llvm/llvm-project/commit/56097bce97b4f0a9717268e9ddc1bb72bc49390c.diff

LOG: [RISCV][Clang] Fix typo: RISCXCVBuiltin -> RISCVXCVBuiltin. NFC.

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsRISCVXCV.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsRISCVXCV.td 
b/clang/include/clang/Basic/BuiltinsRISCVXCV.td
index 06ce07ade5c12..d363fd514603c 100644
--- a/clang/include/clang/Basic/BuiltinsRISCVXCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCVXCV.td
@@ -11,7 +11,7 @@
 //
 
//===--===//
 
-class RISCXCVBuiltin : TargetBuiltin {
+class RISCVXCVBuiltin : TargetBuiltin {
   let Spellings = ["__builtin_riscv_cv_" # NAME];
   let Prototype = prototype;
   let Features = features;
@@ -21,21 +21,21 @@ let Attributes = [NoThrow, Const] in {
 
//===--===//
 // XCValu extension.
 
//===--===//
-def alu_slet  : RISCXCVBuiltin<"int(int, int)", "xcvalu">;
-def alu_sletu : RISCXCVBuiltin<"int(unsigned int, unsigned int)", "xcvalu">;
-def alu_exths : RISCXCVBuiltin<"int(int)", "xcvalu">;
-def alu_exthz : RISCXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">;
-def alu_extbs : RISCXCVBuiltin<"int(int)", "xcvalu">;
-def alu_extbz : RISCXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">;
+def alu_slet  : RISCVXCVBuiltin<"int(int, int)", "xcvalu">;
+def alu_sletu : RISCVXCVBuiltin<"int(unsigned int, unsigned int)", "xcvalu">;
+def alu_exths : RISCVXCVBuiltin<"int(int)", "xcvalu">;
+def alu_exthz : RISCVXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">;
+def alu_extbs : RISCVXCVBuiltin<"int(int)", "xcvalu">;
+def alu_extbz : RISCVXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">;
 
-def alu_clip   : RISCXCVBuiltin<"int(int, int)", "xcvalu">;
-def alu_clipu  : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int)", 
"xcvalu">;
-def alu_addN   : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
-def alu_adduN  : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, 
unsigned int)", "xcvalu">;
-def alu_addRN  : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
-def alu_adduRN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, 
unsigned int)", "xcvalu">;
-def alu_subN   : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
-def alu_subuN  : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, 
unsigned int)", "xcvalu">;
-def alu_subRN  : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
-def alu_subuRN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, 
unsigned int)", "xcvalu">;
+def alu_clip   : RISCVXCVBuiltin<"int(int, int)", "xcvalu">;
+def alu_clipu  : RISCVXCVBuiltin<"unsigned int(unsigned int, unsigned int)", 
"xcvalu">;
+def alu_addN   : RISCVXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
+def alu_adduN  : RISCVXCVBuiltin<"unsigned int(unsigned int, unsigned int, 
unsigned int)", "xcvalu">;
+def alu_addRN  : RISCVXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
+def alu_adduRN : RISCVXCVBuiltin<"unsigned int(unsigned int, unsigned int, 
unsigned int)", "xcvalu">;
+def alu_subN   : RISCVXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
+def alu_subuN  : RISCVXCVBuiltin<"unsigned int(unsigned int, unsigned int, 
unsigned int)", "xcvalu">;
+def alu_subRN  : RISCVXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
+def alu_subuRN : RISCVXCVBuiltin<"unsigned int(unsigned int, unsigned int, 
unsigned int)", "xcvalu">;
 } // Attributes = [NoThrow, Const]



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[clang] [llvm] [RISCV] Rename XCValu intrinsic name _slet(u) to _sle(u)) (PR #138498)

2025-05-05 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/138498

The instruction name and intrinsic name have been renamed to sle(u). The `t` 
was removed. Please refer to
https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md.

>From dc63633ee16568cf01bdc17c8c3abd7cf1714e0a Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Mon, 5 May 2025 17:16:25 +0800
Subject: [PATCH] [RISCV] Rename XCValu intrinsic name *_slet(u) to *_sle(u))

The instruction name and intrinsic name have been renamed to sle(u).
Please refer to
https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md.
---
 clang/include/clang/Basic/BuiltinsRISCVXCV.td |  4 ++--
 clang/lib/CodeGen/TargetBuiltins/RISCV.cpp|  4 ++--
 clang/lib/Headers/riscv_corev_alu.h   |  8 
 clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c | 12 ++--
 clang/test/CodeGen/RISCV/riscv-xcvalu.c   | 12 ++--
 llvm/test/CodeGen/RISCV/xcvalu.ll |  8 
 6 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/clang/include/clang/Basic/BuiltinsRISCVXCV.td 
b/clang/include/clang/Basic/BuiltinsRISCVXCV.td
index d363fd514603c..65eb52b198775 100644
--- a/clang/include/clang/Basic/BuiltinsRISCVXCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCVXCV.td
@@ -21,8 +21,8 @@ let Attributes = [NoThrow, Const] in {
 
//===--===//
 // XCValu extension.
 
//===--===//
-def alu_slet  : RISCVXCVBuiltin<"int(int, int)", "xcvalu">;
-def alu_sletu : RISCVXCVBuiltin<"int(unsigned int, unsigned int)", "xcvalu">;
+def alu_sle   : RISCVXCVBuiltin<"int(int, int)", "xcvalu">;
+def alu_sleu  : RISCVXCVBuiltin<"int(unsigned int, unsigned int)", "xcvalu">;
 def alu_exths : RISCVXCVBuiltin<"int(int)", "xcvalu">;
 def alu_exthz : RISCVXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">;
 def alu_extbs : RISCVXCVBuiltin<"int(int)", "xcvalu">;
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp 
b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 2434ae3c5d2ff..3335239b0b6c2 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -388,10 +388,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   case RISCV::BI__builtin_riscv_cv_alu_exthz:
 return Builder.CreateZExt(Builder.CreateTrunc(Ops[0], Int16Ty), Int32Ty,
   "exthz");
-  case RISCV::BI__builtin_riscv_cv_alu_slet:
+  case RISCV::BI__builtin_riscv_cv_alu_sle:
 return Builder.CreateZExt(Builder.CreateICmpSLE(Ops[0], Ops[1]), Int32Ty,
   "sle");
-  case RISCV::BI__builtin_riscv_cv_alu_sletu:
+  case RISCV::BI__builtin_riscv_cv_alu_sleu:
 return Builder.CreateZExt(Builder.CreateICmpULE(Ops[0], Ops[1]), Int32Ty,
   "sleu");
   case RISCV::BI__builtin_riscv_cv_alu_subN:
diff --git a/clang/lib/Headers/riscv_corev_alu.h 
b/clang/lib/Headers/riscv_corev_alu.h
index d2832ddf72efe..84f4d087e4863 100644
--- a/clang/lib/Headers/riscv_corev_alu.h
+++ b/clang/lib/Headers/riscv_corev_alu.h
@@ -24,13 +24,13 @@ static __inline__ long __DEFAULT_FN_ATTRS 
__riscv_cv_abs(long a) {
   return __builtin_abs(a);
 }
 
-static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_slet(long a, long b) {
-  return __builtin_riscv_cv_alu_slet(a, b);
+static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_sle(long a, long b) {
+  return __builtin_riscv_cv_alu_sle(a, b);
 }
 
 static __inline__ long __DEFAULT_FN_ATTRS
-__riscv_cv_alu_sletu(unsigned long a, unsigned long b) {
-  return __builtin_riscv_cv_alu_sletu(a, b);
+__riscv_cv_alu_sleu(unsigned long a, unsigned long b) {
+  return __builtin_riscv_cv_alu_sleu(a, b);
 }
 
 static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_min(long a, long b) {
diff --git a/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c 
b/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
index b4690a5f1c1ca..a0409e346d708 100644
--- a/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
+++ b/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
@@ -5,7 +5,7 @@
 #include 
 #include 
 
-// CHECK-LABEL: @test_alu_slet(
+// CHECK-LABEL: @test_alu_sle(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[A_ADDR_I:%.*]] = alloca i32, align 4
 // CHECK-NEXT:[[B_ADDR_I:%.*]] = alloca i32, align 4
@@ -23,11 +23,11 @@
 // CHECK-NEXT:[[SLE_I:%.*]] = zext i1 [[TMP4]] to i32
 // CHECK-NEXT:ret i32 [[SLE_I]]
 //
-int test_alu_slet(int32_t a, int32_t b) {
-  return __riscv_cv_alu_slet(a, b);
+int test_alu_sle(int32_t a, int32_t b) {
+  return __riscv_cv_alu_sle(a, b);
 }
 
-// CHECK-LABEL: @test_alu_sletu(
+// CHECK-LABEL: @test_alu_sleu(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[A_ADDR_I:%.*]] = alloca i32, align 4
 // CHECK-NEXT:[[B_ADDR_I:%.*]] = alloca i32, align 4
@@ -45,8 +45,8 @@ int test_alu_slet(int32_t a, int32_t b) {
 // CHECK-

[clang] [llvm] [RISCV] Rename XCValu intrinsic name _slet(u) to _sle(u)) (PR #138498)

2025-05-05 Thread Jim Lin via cfe-commits


https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/138498
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[clang] [llvm] [RISCV] Add Andes A45/AX45 processor definition (PR #136832)

2025-04-23 Thread Jim Lin via cfe-commits


https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/136832

Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline linux-capable 
CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are 
developed by Andes Technology https://www.andestech.com, a RISC-V IP provider.

The overviews for A45/AX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/ 
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/

Scheduling model will be implemented in a later PR.

>From ba745d8c918ad2cc3359c9e033b2c6b47d4810e5 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Wed, 23 Apr 2025 14:48:29 +0800
Subject: [PATCH] [RISCV] Add Andes A45/AX45 processor definition

Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline
linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA
extensions. They are developed by Andes Technology
https://www.andestech.com, a RISC-V IP provider.

The overviews for A45/AX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/

Scheduling model will be implemented in a later PR.
---
 clang/test/Driver/riscv-cpus.c| 34 +++
 .../test/Misc/target-invalid-cpu-note/riscv.c | 12 ---
 llvm/docs/ReleaseNotes.md |  1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 26 ++
 4 files changed, 69 insertions(+), 4 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 19da8ede26a40..bb3a9d38be673 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -726,3 +726,37 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck 
-check-prefix=MTUNE-ANDES-NX45 %s
 // MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a45 | FileCheck 
-check-prefix=MCPU-ANDES-A45 %s
+// MCPU-ANDES-A45: "-target-cpu" "andes-a45"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-A45-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a45 | FileCheck 
-check-prefix=MTUNE-ANDES-A45 %s
+// MTUNE-ANDES-A45: "-tune-cpu" "andes-a45"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax45 | FileCheck 
-check-prefix=MCPU-ANDES-AX45 %s
+// MCPU-ANDES-AX45: "-target-cpu" "andes-ax45"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-AX45-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax45 | FileCheck 
-check-prefix=MTUNE-ANDES-AX45 %s
+// MTUNE-ANDES-AX45: "-tune-cpu" "andes-ax45"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c 
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index cd8a8bf95dd7a..f0c4173e18022 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -5,7 +5,8 @@
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
 // RISCV32-NEXT: note: valid target CPU values are:
-// RISCV32-SAME: {{^}} andes-n45
+// RISCV32-SAME: {{^}} andes-a45
+// RISCV32-SAME: {{^}}, andes-n45
 // RISCV32-SAME: {{^}}, generic-rv32
 // RISCV32-SAME: {{^}}, rocket-rv32
 // RISCV32-SAME: {{^}}, rp2350-hazard3
@@ -25,7 +26,8 @@
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64-NEXT: note: valid target CPU values are:
-// RISCV64-SAME: {{^}} andes-nx45
+// RISCV64-SAME: {{^}} andes-ax45
+// RISCV64-SAME: {{^}}, andes-nx45
 // RISCV64-SAME: {{^}}, generic-rv64
 // RISCV64-SAME: {{^}}, mips-p8700
 // RISCV64-SAME: {{^}}, rocket-rv64
@@ -54,7 +56,8 @@
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-

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