[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In https://reviews.llvm.org/D45045#1189201, @vext01 wrote:

> Hi,
>
> I've been experimenting some more with this patch.
>
> It seems to me that if a label is optimised away, but you've requested it be 
> preserved, then you get a DWARF label with a zero offset. Is that the 
> expected behaviour? Should it be documented?
>
> E.g.:
>
>   < 6><0x00dc>  DW_TAG_label
>   DW_AT_name  
> __YK_BLK_2_19418_0
>   DW_AT_low_pc0x
>
>
> Thanks!


I expect that even the code is optimized out, the label will point to somewhere 
in the function. If the whole function is optimized out, the label should not 
exist any more. It should not have address zero.

Do you have any test snippet to reproduce the bug? Thanks.


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

Hi @vext01,

It should be fixed in https://reviews.llvm.org/D50495.
Please help me to confirm it in your environment. Thanks so much. :)


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In https://reviews.llvm.org/D45045#1092697, @hans wrote:

> This broke the Chromium build. I've uploaded a reproducer at 
> https://bugs.chromium.org/p/chromium/issues/detail?id=841170#c1
>
> I'm guessing maybe a Clang bootstrap with debug info might also reproduce the 
> problem, but I haven't tried that.
>
> Reverted in r331861.


https://reviews.llvm.org/D46738 should fix the bug.


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In https://reviews.llvm.org/D45045#1184313, @vext01 wrote:

> Looks like this was backed out (reverted) yesterday.
>
> I'm really interested in inserting DILabels from LLVM in my research project, 
> so I hope it can be recovered.


You could apply it locally. In most cases, it works fine.

Currently, I still work on some problems when you use label in goto expression 
and you do some calculation on it under optimization.
Following is the test case I try to resolve the problem.

  int tab[9];
  
  void execute(unsigned short *oip, unsigned short *ip)
  {
int x = 0;
int *xp = tab;
  base:
x++;
if (x == 4)
  {
*xp = 0;
return;
  }
*xp++ = ip - oip;
goto *(&&base + *ip++);
  }
  
  int main()
  {
unsigned short ip[10];
int i;
for (i = 0; i < 10; i++)
  ip[i] = 0;
execute(ip, ip);
  
return 0;
  }

If you do not use label in such complex way, I think you could apply it 
temporarily.


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[PATCH] D50226: [DebugInfo] Use DbgVariableIntrinsic as the base class of variables.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: aprantl, probinson, dblaikie.
Herald added subscribers: cfe-commits, JDevlieghere.

After refactoring DbgInfoIntrinsic class hierarchy, we use
DbgVariableIntrinsic as the base class of variable debug info.

In resolveTopLevelMetadata() in CGVTables.cpp, we only care about
dbg.value, so we try to cast the instructions to DbgVariableIntrinsic
before resolving variables.


Repository:
  rC Clang

https://reviews.llvm.org/D50226

Files:
  lib/CodeGen/CGVTables.cpp


Index: lib/CodeGen/CGVTables.cpp
===
--- lib/CodeGen/CGVTables.cpp
+++ lib/CodeGen/CGVTables.cpp
@@ -128,7 +128,7 @@
   // they are referencing.
   for (auto &BB : Fn->getBasicBlockList()) {
 for (auto &I : BB) {
-  if (auto *DII = dyn_cast(&I)) {
+  if (auto *DII = dyn_cast(&I)) {
 auto *DILocal = DII->getVariable();
 if (!DILocal->isResolved())
   DILocal->resolve();


Index: lib/CodeGen/CGVTables.cpp
===
--- lib/CodeGen/CGVTables.cpp
+++ lib/CodeGen/CGVTables.cpp
@@ -128,7 +128,7 @@
   // they are referencing.
   for (auto &BB : Fn->getBasicBlockList()) {
 for (auto &I : BB) {
-  if (auto *DII = dyn_cast(&I)) {
+  if (auto *DII = dyn_cast(&I)) {
 auto *DILocal = DII->getVariable();
 if (!DILocal->isResolved())
   DILocal->resolve();
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[PATCH] D50226: [DebugInfo] Use DbgVariableIntrinsic as the base class of variables.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL338985: [DebugInfo] Use DbgVariableIntrinsic as the base 
class of variables. (authored by HsiangKai, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D50226?vs=158924&id=159241#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D50226

Files:
  cfe/trunk/lib/CodeGen/CGVTables.cpp


Index: cfe/trunk/lib/CodeGen/CGVTables.cpp
===
--- cfe/trunk/lib/CodeGen/CGVTables.cpp
+++ cfe/trunk/lib/CodeGen/CGVTables.cpp
@@ -128,7 +128,7 @@
   // they are referencing.
   for (auto &BB : Fn->getBasicBlockList()) {
 for (auto &I : BB) {
-  if (auto *DII = dyn_cast(&I)) {
+  if (auto *DII = dyn_cast(&I)) {
 auto *DILocal = DII->getVariable();
 if (!DILocal->isResolved())
   DILocal->resolve();


Index: cfe/trunk/lib/CodeGen/CGVTables.cpp
===
--- cfe/trunk/lib/CodeGen/CGVTables.cpp
+++ cfe/trunk/lib/CodeGen/CGVTables.cpp
@@ -128,7 +128,7 @@
   // they are referencing.
   for (auto &BB : Fn->getBasicBlockList()) {
 for (auto &I : BB) {
-  if (auto *DII = dyn_cast(&I)) {
+  if (auto *DII = dyn_cast(&I)) {
 auto *DILocal = DII->getVariable();
 if (!DILocal->isResolved())
   DILocal->resolve();
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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In https://reviews.llvm.org/D45045#1247427, @vitalybuka wrote:

> Reverted in r343183
>  https://bugs.llvm.org/show_bug.cgi?id=39094
>  
> http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/29356/steps/build%20release%20tsan%20with%20clang/logs/stdio


I have fixed the bug in https://reviews.llvm.org/D52927 and it has landed in 
master branch. Could I recommit this patch?


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rC345009: [DebugInfo] Generate debug information for labels. 
(After fix PR39094) (authored by HsiangKai, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D45045?vs=145849&id=170580#toc

Repository:
  rC Clang

https://reviews.llvm.org/D45045

Files:
  lib/CodeGen/CGDebugInfo.cpp
  lib/CodeGen/CGDebugInfo.h
  lib/CodeGen/CGStmt.cpp
  test/CodeGen/debug-label-inline.c
  test/CodeGen/debug-label.c

Index: test/CodeGen/debug-label-inline.c
===
--- test/CodeGen/debug-label-inline.c
+++ test/CodeGen/debug-label-inline.c
@@ -0,0 +1,28 @@
+// This test will test the correctness of generating DILabel and
+// llvm.dbg.label when the label is in inlined functions.
+//
+// RUN: %clang_cc1 -O2 %s -o - -emit-llvm -debug-info-kind=limited | FileCheck %s
+inline int f1(int a, int b) {
+  int sum;
+
+top:
+  sum = a + b;
+  return sum;
+}
+
+extern int ga, gb;
+
+int f2(void) {
+  int result;
+
+  result = f1(ga, gb);
+  // CHECK: call void @llvm.dbg.label(metadata [[LABEL_METADATA:!.*]]), !dbg [[LABEL_LOCATION:!.*]]
+
+  return result;
+}
+
+// CHECK: distinct !DISubprogram(name: "f1", {{.*}}, retainedNodes: [[ELEMENTS:!.*]])
+// CHECK: [[ELEMENTS]] = !{{{.*}}, [[LABEL_METADATA]]}
+// CHECK: [[LABEL_METADATA]] = !DILabel({{.*}}, name: "top", {{.*}}, line: 8)
+// CHECK: [[INLINEDAT:!.*]] = distinct !DILocation(line: 18,
+// CHECK: [[LABEL_LOCATION]] = !DILocation(line: 8, {{.*}}, inlinedAt: [[INLINEDAT]])
Index: test/CodeGen/debug-label.c
===
--- test/CodeGen/debug-label.c
+++ test/CodeGen/debug-label.c
@@ -0,0 +1,16 @@
+// This test will test the correstness of generating DILabel and
+// llvm.dbg.label for labels.
+//
+// RUN: %clang_cc1 -emit-llvm %s -o - -emit-llvm -debug-info-kind=limited | FileCheck %s
+
+int f1(int a, int b) {
+  int sum;
+
+top:
+  // CHECK: call void @llvm.dbg.label(metadata [[LABEL_METADATA:!.*]]), !dbg [[LABEL_LOCATION:!.*]]
+  sum = a + b;
+  return sum;
+}
+
+// CHECK: [[LABEL_METADATA]] = !DILabel({{.*}}, name: "top", {{.*}}, line: 9)
+// CHECK: [[LABEL_LOCATION]] = !DILocation(line: 9,
Index: lib/CodeGen/CGStmt.cpp
===
--- lib/CodeGen/CGStmt.cpp
+++ lib/CodeGen/CGStmt.cpp
@@ -531,6 +531,16 @@
   }
 
   EmitBlock(Dest.getBlock());
+
+  // Emit debug info for labels.
+  if (CGDebugInfo *DI = getDebugInfo()) {
+if (CGM.getCodeGenOpts().getDebugInfo() >=
+codegenoptions::LimitedDebugInfo) {
+  DI->setLocation(D->getLocation());
+  DI->EmitLabel(D, Builder);
+}
+  }
+
   incrementProfileCounter(D->getStmt());
 }
 
Index: lib/CodeGen/CGDebugInfo.cpp
===
--- lib/CodeGen/CGDebugInfo.cpp
+++ lib/CodeGen/CGDebugInfo.cpp
@@ -3804,6 +3804,32 @@
   return EmitDeclare(VD, Storage, llvm::None, Builder);
 }
 
+void CGDebugInfo::EmitLabel(const LabelDecl *D, CGBuilderTy &Builder) {
+  assert(DebugKind >= codegenoptions::LimitedDebugInfo);
+  assert(!LexicalBlockStack.empty() && "Region stack mismatch, stack empty!");
+
+  if (D->hasAttr())
+return;
+
+  auto *Scope = cast(LexicalBlockStack.back());
+  llvm::DIFile *Unit = getOrCreateFile(D->getLocation());
+
+  // Get location information.
+  unsigned Line = getLineNumber(D->getLocation());
+  unsigned Column = getColumnNumber(D->getLocation());
+
+  StringRef Name = D->getName();
+
+  // Create the descriptor for the label.
+  auto *L =
+  DBuilder.createLabel(Scope, Name, Unit, Line, CGM.getLangOpts().Optimize);
+
+  // Insert an llvm.dbg.label into the current block.
+  DBuilder.insertLabel(L,
+   llvm::DebugLoc::get(Line, Column, Scope, CurInlinedAt),
+   Builder.GetInsertBlock());
+}
+
 llvm::DIType *CGDebugInfo::CreateSelfType(const QualType &QualTy,
   llvm::DIType *Ty) {
   llvm::DIType *CachedTy = getTypeOrNull(QualTy);
Index: lib/CodeGen/CGDebugInfo.h
===
--- lib/CodeGen/CGDebugInfo.h
+++ lib/CodeGen/CGDebugInfo.h
@@ -420,6 +420,9 @@
llvm::Value *AI,
CGBuilderTy &Builder);
 
+  /// Emit call to \c llvm.dbg.label for an label.
+  void EmitLabel(const LabelDecl *D, CGBuilderTy &Builder);
+
   /// Emit call to \c llvm.dbg.declare for an imported variable
   /// declaration in a block.
   void EmitDeclareOfBlockDeclRefVariable(
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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

D54199  and D54465 
 have been accepted and landed. I have tested 
the revision with LLVM test and Clang test. They are all passed. Chromium build 
is also successful in my local environment. I think it is ready to reland the 
revision.


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rL352025: Reland r345009 "[DebugInfo] Generate debug 
information for labels." (authored by HsiangKai, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D45045?vs=170580&id=183246#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D45045/new/

https://reviews.llvm.org/D45045

Files:
  cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
  cfe/trunk/lib/CodeGen/CGDebugInfo.h
  cfe/trunk/lib/CodeGen/CGStmt.cpp
  cfe/trunk/test/CodeGen/debug-label-inline.c
  cfe/trunk/test/CodeGen/debug-label.c

Index: cfe/trunk/test/CodeGen/debug-label.c
===
--- cfe/trunk/test/CodeGen/debug-label.c
+++ cfe/trunk/test/CodeGen/debug-label.c
@@ -0,0 +1,16 @@
+// This test will test the correstness of generating DILabel and
+// llvm.dbg.label for labels.
+//
+// RUN: %clang_cc1 -emit-llvm %s -o - -emit-llvm -debug-info-kind=limited | FileCheck %s
+
+int f1(int a, int b) {
+  int sum;
+
+top:
+  // CHECK: call void @llvm.dbg.label(metadata [[LABEL_METADATA:!.*]]), !dbg [[LABEL_LOCATION:!.*]]
+  sum = a + b;
+  return sum;
+}
+
+// CHECK: [[LABEL_METADATA]] = !DILabel({{.*}}, name: "top", {{.*}}, line: 9)
+// CHECK: [[LABEL_LOCATION]] = !DILocation(line: 9,
Index: cfe/trunk/test/CodeGen/debug-label-inline.c
===
--- cfe/trunk/test/CodeGen/debug-label-inline.c
+++ cfe/trunk/test/CodeGen/debug-label-inline.c
@@ -0,0 +1,28 @@
+// This test will test the correctness of generating DILabel and
+// llvm.dbg.label when the label is in inlined functions.
+//
+// RUN: %clang_cc1 -O2 %s -o - -emit-llvm -debug-info-kind=limited | FileCheck %s
+inline int f1(int a, int b) {
+  int sum;
+
+top:
+  sum = a + b;
+  return sum;
+}
+
+extern int ga, gb;
+
+int f2(void) {
+  int result;
+
+  result = f1(ga, gb);
+  // CHECK: call void @llvm.dbg.label(metadata [[LABEL_METADATA:!.*]]), !dbg [[LABEL_LOCATION:!.*]]
+
+  return result;
+}
+
+// CHECK: distinct !DISubprogram(name: "f1", {{.*}}, retainedNodes: [[ELEMENTS:!.*]])
+// CHECK: [[ELEMENTS]] = !{{{.*}}, [[LABEL_METADATA]]}
+// CHECK: [[LABEL_METADATA]] = !DILabel({{.*}}, name: "top", {{.*}}, line: 8)
+// CHECK: [[INLINEDAT:!.*]] = distinct !DILocation(line: 18,
+// CHECK: [[LABEL_LOCATION]] = !DILocation(line: 8, {{.*}}, inlinedAt: [[INLINEDAT]])
Index: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
===
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
@@ -3862,6 +3862,32 @@
   return EmitDeclare(VD, Storage, llvm::None, Builder);
 }
 
+void CGDebugInfo::EmitLabel(const LabelDecl *D, CGBuilderTy &Builder) {
+  assert(DebugKind >= codegenoptions::LimitedDebugInfo);
+  assert(!LexicalBlockStack.empty() && "Region stack mismatch, stack empty!");
+
+  if (D->hasAttr())
+return;
+
+  auto *Scope = cast(LexicalBlockStack.back());
+  llvm::DIFile *Unit = getOrCreateFile(D->getLocation());
+
+  // Get location information.
+  unsigned Line = getLineNumber(D->getLocation());
+  unsigned Column = getColumnNumber(D->getLocation());
+
+  StringRef Name = D->getName();
+
+  // Create the descriptor for the label.
+  auto *L =
+  DBuilder.createLabel(Scope, Name, Unit, Line, CGM.getLangOpts().Optimize);
+
+  // Insert an llvm.dbg.label into the current block.
+  DBuilder.insertLabel(L,
+   llvm::DebugLoc::get(Line, Column, Scope, CurInlinedAt),
+   Builder.GetInsertBlock());
+}
+
 llvm::DIType *CGDebugInfo::CreateSelfType(const QualType &QualTy,
   llvm::DIType *Ty) {
   llvm::DIType *CachedTy = getTypeOrNull(QualTy);
Index: cfe/trunk/lib/CodeGen/CGDebugInfo.h
===
--- cfe/trunk/lib/CodeGen/CGDebugInfo.h
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.h
@@ -425,6 +425,9 @@
llvm::Value *AI,
CGBuilderTy &Builder);
 
+  /// Emit call to \c llvm.dbg.label for an label.
+  void EmitLabel(const LabelDecl *D, CGBuilderTy &Builder);
+
   /// Emit call to \c llvm.dbg.declare for an imported variable
   /// declaration in a block.
   void EmitDeclareOfBlockDeclRefVariable(
Index: cfe/trunk/lib/CodeGen/CGStmt.cpp
===
--- cfe/trunk/lib/CodeGen/CGStmt.cpp
+++ cfe/trunk/lib/CodeGen/CGStmt.cpp
@@ -528,6 +528,16 @@
   }
 
   EmitBlock(Dest.getBlock());
+
+  // Emit debug info for labels.
+  if (CGDebugInfo *DI = getDebugInfo()) {
+if (CGM.getCodeGenOpts().getDebugInfo() >=
+codegenoptions::LimitedDebugInfo) {
+  DI->setLocation(D->getLocation());
+  DI->EmitLabel(D, Builder);
+}
+  }

[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In https://reviews.llvm.org/D45045#1299507, @tyb0807 wrote:

> Hello all,
>
> This commit has been reverted by https://reviews.llvm.org/rC345026. It was 
> reported that this broke the Chromium build (again). Have you had a look to 
> fix this, @HsiangKai?


I have fixed these bugs found in Chromium build in following two commits.

https://reviews.llvm.org/D54199
https://reviews.llvm.org/D54465

These two commits are under reviewing.
Thanks for your reminding.


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

Fix the bug in https://reviews.llvm.org/D52927.


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 142533.
HsiangKai added a comment.

Update test cases.


Repository:
  rC Clang

https://reviews.llvm.org/D45045

Files:
  lib/CodeGen/CGDebugInfo.cpp
  lib/CodeGen/CGDebugInfo.h
  lib/CodeGen/CGStmt.cpp
  test/CodeGen/debug-label-inline.c
  test/CodeGen/debug-label.c

Index: test/CodeGen/debug-label.c
===
--- /dev/null
+++ test/CodeGen/debug-label.c
@@ -0,0 +1,16 @@
+// This test will test the correstness of generating DILabel and
+// llvm.dbg.label for labels.
+//
+// RUN: %clang_cc1 -emit-llvm %s -o - -emit-llvm -debug-info-kind=limited | FileCheck %s
+
+int f1(int a, int b) {
+  int sum;
+
+top:
+  // CHECK: call void @llvm.dbg.label(metadata [[LABEL_METADATA:!.*]]), !dbg [[LABEL_LOCATION:!.*]]
+  sum = a + b;
+  return sum;
+}
+
+// CHECK: [[LABEL_METADATA]] = !DILabel({{.*}}, name: "top", {{.*}}, line: 9)
+// CHECK: [[LABEL_LOCATION]] = !DILocation(line: 9,
Index: test/CodeGen/debug-label-inline.c
===
--- /dev/null
+++ test/CodeGen/debug-label-inline.c
@@ -0,0 +1,28 @@
+// This test will test the correctness of generating DILabel and
+// llvm.dbg.label when the label is in inlined functions.
+//
+// RUN: %clang_cc1 -O2 %s -o - -emit-llvm -debug-info-kind=limited | FileCheck %s
+inline int f1(int a, int b) {
+  int sum;
+
+top:
+  sum = a + b;
+  return sum;
+}
+
+extern int ga, gb;
+
+int f2(void) {
+  int result;
+
+  result = f1(ga, gb);
+  // CHECK: call void @llvm.dbg.label(metadata [[LABEL_METADATA:!.*]]), !dbg [[LABEL_LOCATION:!.*]]
+
+  return result;
+}
+
+// CHECK: distinct !DISubprogram(name: "f1", {{.*}}, elements: [[ELEMENTS:!.*]])
+// CHECK: [[ELEMENTS]] = !{{{.*}}, [[LABEL_METADATA]]}
+// CHECK: [[LABEL_METADATA]] = !DILabel({{.*}}, name: "top", {{.*}}, line: 8)
+// CHECK: [[INLINEDAT:!.*]] = distinct !DILocation(line: 18,
+// CHECK: [[LABEL_LOCATION]] = !DILocation(line: 8, {{.*}}, inlinedAt: [[INLINEDAT]])
Index: lib/CodeGen/CGStmt.cpp
===
--- lib/CodeGen/CGStmt.cpp
+++ lib/CodeGen/CGStmt.cpp
@@ -531,6 +531,16 @@
   }
 
   EmitBlock(Dest.getBlock());
+
+  // Emit debug info for labels.
+  if (CGDebugInfo *DI = getDebugInfo()) {
+if (CGM.getCodeGenOpts().getDebugInfo() >=
+codegenoptions::LimitedDebugInfo) {
+  DI->setLocation(D->getLocation());
+  DI->EmitLabel(D, Builder);
+}
+  }
+
   incrementProfileCounter(D->getStmt());
 }
 
Index: lib/CodeGen/CGDebugInfo.h
===
--- lib/CodeGen/CGDebugInfo.h
+++ lib/CodeGen/CGDebugInfo.h
@@ -395,6 +395,9 @@
llvm::Value *AI,
CGBuilderTy &Builder);
 
+  /// Emit call to \c llvm.dbg.label for an label.
+  void EmitLabel(const LabelDecl *D, CGBuilderTy &Builder);
+
   /// Emit call to \c llvm.dbg.declare for an imported variable
   /// declaration in a block.
   void EmitDeclareOfBlockDeclRefVariable(const VarDecl *variable,
Index: lib/CodeGen/CGDebugInfo.cpp
===
--- lib/CodeGen/CGDebugInfo.cpp
+++ lib/CodeGen/CGDebugInfo.cpp
@@ -3640,6 +3640,33 @@
   return EmitDeclare(VD, Storage, llvm::None, Builder);
 }
 
+void CGDebugInfo::EmitLabel(const LabelDecl *D,
+CGBuilderTy &Builder) {
+  assert(DebugKind >= codegenoptions::LimitedDebugInfo);
+  assert(!LexicalBlockStack.empty() && "Region stack mismatch, stack empty!");
+
+  if (D->hasAttr())
+return;
+
+  auto *Scope = cast(LexicalBlockStack.back());
+  llvm::DIFile *Unit = getOrCreateFile(D->getLocation());
+
+  // Get location information.
+  unsigned Line = getLineNumber(D->getLocation());
+  unsigned Column = getColumnNumber(D->getLocation());
+
+  StringRef Name = D->getName();
+
+  // Create the descriptor for the label.
+  auto *L = DBuilder.createLabel(Scope, Name, Unit, Line,
+ CGM.getLangOpts().Optimize);
+
+  // Insert an llvm.dbg.label into the current block.
+  DBuilder.insertLabel(L,
+   llvm::DebugLoc::get(Line, Column, Scope, CurInlinedAt),
+   Builder.GetInsertBlock());
+}
+
 llvm::DIType *CGDebugInfo::CreateSelfType(const QualType &QualTy,
   llvm::DIType *Ty) {
   llvm::DIType *CachedTy = getTypeOrNull(QualTy);
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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked 2 inline comments as done.
HsiangKai added a comment.

Always add labels to DISubprogram even unreachable.


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 143243.
HsiangKai added a comment.

- Update test cases.
- Checked with clang-format.


Repository:
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Files:
  lib/CodeGen/CGDebugInfo.cpp
  lib/CodeGen/CGDebugInfo.h
  lib/CodeGen/CGStmt.cpp
  test/CodeGen/backend-unsupported-error.ll
  test/CodeGen/debug-label-inline.c
  test/CodeGen/debug-label.c

Index: test/CodeGen/debug-label.c
===
--- /dev/null
+++ test/CodeGen/debug-label.c
@@ -0,0 +1,16 @@
+// This test will test the correstness of generating DILabel and
+// llvm.dbg.label for labels.
+//
+// RUN: %clang_cc1 -emit-llvm %s -o - -emit-llvm -debug-info-kind=limited | FileCheck %s
+
+int f1(int a, int b) {
+  int sum;
+
+top:
+  // CHECK: call void @llvm.dbg.label(metadata [[LABEL_METADATA:!.*]]), !dbg [[LABEL_LOCATION:!.*]]
+  sum = a + b;
+  return sum;
+}
+
+// CHECK: [[LABEL_METADATA]] = !DILabel({{.*}}, name: "top", {{.*}}, line: 9)
+// CHECK: [[LABEL_LOCATION]] = !DILocation(line: 9,
Index: test/CodeGen/debug-label-inline.c
===
--- /dev/null
+++ test/CodeGen/debug-label-inline.c
@@ -0,0 +1,28 @@
+// This test will test the correctness of generating DILabel and
+// llvm.dbg.label when the label is in inlined functions.
+//
+// RUN: %clang_cc1 -O2 %s -o - -emit-llvm -debug-info-kind=limited | FileCheck %s
+inline int f1(int a, int b) {
+  int sum;
+
+top:
+  sum = a + b;
+  return sum;
+}
+
+extern int ga, gb;
+
+int f2(void) {
+  int result;
+
+  result = f1(ga, gb);
+  // CHECK: call void @llvm.dbg.label(metadata [[LABEL_METADATA:!.*]]), !dbg [[LABEL_LOCATION:!.*]]
+
+  return result;
+}
+
+// CHECK: distinct !DISubprogram(name: "f1", {{.*}}, retainedNodes: [[ELEMENTS:!.*]])
+// CHECK: [[ELEMENTS]] = !{{{.*}}, [[LABEL_METADATA]]}
+// CHECK: [[LABEL_METADATA]] = !DILabel({{.*}}, name: "top", {{.*}}, line: 8)
+// CHECK: [[INLINEDAT:!.*]] = distinct !DILocation(line: 18,
+// CHECK: [[LABEL_LOCATION]] = !DILocation(line: 8, {{.*}}, inlinedAt: [[INLINEDAT]])
Index: test/CodeGen/backend-unsupported-error.ll
===
--- test/CodeGen/backend-unsupported-error.ll
+++ test/CodeGen/backend-unsupported-error.ll
@@ -30,11 +30,11 @@
 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2)
 !1 = !DIFile(filename: "test.c", directory: "")
 !2 = !{}
-!4 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, unit: !0, variables: !2)
+!4 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, unit: !0, retainedNodes: !2)
 !5 = !DISubroutineType(types: !6)
 !6 = !{!7}
 !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
-!8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+!8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
 !10 = !{i32 2, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.9.0"}
Index: lib/CodeGen/CGStmt.cpp
===
--- lib/CodeGen/CGStmt.cpp
+++ lib/CodeGen/CGStmt.cpp
@@ -531,6 +531,16 @@
   }
 
   EmitBlock(Dest.getBlock());
+
+  // Emit debug info for labels.
+  if (CGDebugInfo *DI = getDebugInfo()) {
+if (CGM.getCodeGenOpts().getDebugInfo() >=
+codegenoptions::LimitedDebugInfo) {
+  DI->setLocation(D->getLocation());
+  DI->EmitLabel(D, Builder);
+}
+  }
+
   incrementProfileCounter(D->getStmt());
 }
 
Index: lib/CodeGen/CGDebugInfo.h
===
--- lib/CodeGen/CGDebugInfo.h
+++ lib/CodeGen/CGDebugInfo.h
@@ -395,6 +395,9 @@
llvm::Value *AI,
CGBuilderTy &Builder);
 
+  /// Emit call to \c llvm.dbg.label for an label.
+  void EmitLabel(const LabelDecl *D, CGBuilderTy &Builder);
+
   /// Emit call to \c llvm.dbg.declare for an imported variable
   /// declaration in a block.
   void EmitDeclareOfBlockDeclRefVariable(const VarDecl *variable,
Index: lib/CodeGen/CGDebugInfo.cpp
===
--- lib/CodeGen/CGDebugInfo.cpp
+++ lib/CodeGen/CGDebugInfo.cpp
@@ -3640,6 +3640,32 @@
   return EmitDeclare(VD, Storage, llvm::None, Builder);
 }
 
+void CGDebugInfo::EmitLabel(const LabelDecl *D, CGBu

[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked an inline comment as done.
HsiangKai added a comment.

@chenwj Do you have any comments for this patch?


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[PATCH] D45045: [DebugInfo] Generate debug information for labels.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In https://reviews.llvm.org/D45045#1114280, @HsiangKai wrote:

> In https://reviews.llvm.org/D45045#1092697, @hans wrote:
>
> > This broke the Chromium build. I've uploaded a reproducer at 
> > https://bugs.chromium.org/p/chromium/issues/detail?id=841170#c1
> >
> > I'm guessing maybe a Clang bootstrap with debug info might also reproduce 
> > the problem, but I haven't tried that.
> >
> > Reverted in r331861.
>
>
> https://reviews.llvm.org/D46738 should fix the bug.


https://reviews.llvm.org/rL336176 has fixed the bug. Could I revert the commit?
You could refer to PR37395.


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[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

Is this patch ready to land? Are there any comments or suggestions I missed?


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[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D69987#1853986 , @HsiangKai wrote:

> Update to version 0.8-draft-20191213.


Hi Roger,

I have updated it to 0.8-draft-20191213 in February. It is the same as version 
0.8. Sorry for that I did not update the commit message. Thanks for your kindly 
reminding.


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[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2283
+  unsigned Src2Reg = Inst.getOperand(1).getReg();
+  if (DestReg == Src2Reg)
+return Error(Loc, "The destination vector register group cannot 
overlap"

fpallares wrote:
> In this function we are validating the overlap constraints by checking 
> whether `DestReg` matches a vector operand. However, for widenings and 
> narrowings those checks should be extended to validate that the operand 
> doesn't belong to the same register group.
> 
> For instance:
> 
> `vwadd.vv v4, v4, v7`: The current code would give an error for this 
> instruction.
> `vwadd.vv v4, v5, v7`: There would be no error for this, even though `v5` 
> will always overlap with any widened group of `v4`.
> `vwadd.vv v4, v6, v7`: This should not emit any diagnostic because we can't 
> really tell at this point if there will be an overlap.
> 
> Perhaps we are already checking this somewhere else and I missed it?
> 
> (Note that this will probably change with fractional LMUL in 0.9)
> 
Good point!

Because there is no LMUL information in these instructions, we cannot detect 
the invalid cases precisely. I only detect destination and source occupy the 
same register. Maybe I could detect destination and (source + 1). The smallest 
LMUL is 1 in v0.8.

After this patch, I am going to prepare another one to upgrade the MC layer to 
v0.9. I will review this part.

Do you have any suggestions?


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 267239.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/ext.s
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/invalid.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/snippet.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/vsetvl.s

Index: llvm/test/MC/RISCV/rvv/vsetvl.s
===
--- llvm/test/MC/RISCV/rvv/vsetvl.s
+++ llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -8,12 +8,72 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+vsetvli a2, a0, e32,m1
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 
+
+vsetvli a2, a0, e32,m2
+# CHECK-INST: vsetvli a2, a0, e32,m2
+# CHECK-ENCODING: [0x57,0x76,0x95,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 00 
+
 vsetvli a2, a0, e32,m4
 # CHECK-INST: vsetvli a2, a0, e32,m4
 # CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 76 a5 00 
 
+vsetvli a2, a0, e32,m8
+# CHECK-INST: vsetvli a2, a0, e32,m8
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 00 
+
+vsetvli a2, a0, e32,mf2
+# CHECK-INST: vsetvli a2, a0, e32,mf2
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 02 
+
+vsetvli a2, a0, e32,mf4
+# CHECK-INST: vsetvli a2, a0, e32,mf4
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 02 
+
+vsetvli a2, a0, e32,mf8
+# CHECK-INST: vsetvli a2, a0, e32,mf8
+# CHECK-ENCODING: [0x57,0x76,0x95,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 02 
+
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 0c 
+
+vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 08 
+
+vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 04 
+
+vsetvli a2, a0, e32,m1,tu,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 
+
 vsetvl a2, a0, a1
 # CHECK-INST: vsetvl a2, a0, a1
 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
Index: llvm/test/MC/RISCV/rvv/store.s
===
--- llvm/test/MC/RISCV/rvv/store.s
+++ llvm/test/MC/RISCV/rvv/store.s
@@ -8,200 +8,296 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vsb.v v24, (a0), v0.t
-# CHECK-INST: vsb.v v24, (a0), v0.t
+vse8.v v24, (a0), v0.t
+# CHECK-INST: vse8.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 00 
 
-vsb.v v24, (a0)
-# CHECK-INST: vsb.v v24, (a0)
+vse8.v v24, (a0)
+# CHECK-INST: vse8.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 02 
 
-vsh.v v24, (a0), v0.t
-# CHECK-INST: vsh.v v24, (a0), v0.t
+vse16.v v24, (a0), v0.t
+# CHECK-INST: vse16.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 05 00 
 
-vsh.v v24, (a0)
-# CHECK-INST: vsh.v v24, (a0)
+vse16.v v24, (a0)
+# CHECK-INST: vse16.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x02]
 # CHECK

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 267447.

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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/ext.s
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/invalid.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/snippet.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/vsetvl.s

Index: llvm/test/MC/RISCV/rvv/vsetvl.s
===
--- llvm/test/MC/RISCV/rvv/vsetvl.s
+++ llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -8,12 +8,72 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+vsetvli a2, a0, e32,m1
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 
+
+vsetvli a2, a0, e32,m2
+# CHECK-INST: vsetvli a2, a0, e32,m2
+# CHECK-ENCODING: [0x57,0x76,0x95,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 00 
+
 vsetvli a2, a0, e32,m4
 # CHECK-INST: vsetvli a2, a0, e32,m4
 # CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 76 a5 00 
 
+vsetvli a2, a0, e32,m8
+# CHECK-INST: vsetvli a2, a0, e32,m8
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 00 
+
+vsetvli a2, a0, e32,mf2
+# CHECK-INST: vsetvli a2, a0, e32,mf2
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 02 
+
+vsetvli a2, a0, e32,mf4
+# CHECK-INST: vsetvli a2, a0, e32,mf4
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 02 
+
+vsetvli a2, a0, e32,mf8
+# CHECK-INST: vsetvli a2, a0, e32,mf8
+# CHECK-ENCODING: [0x57,0x76,0x95,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 02 
+
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 0c 
+
+vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 08 
+
+vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 04 
+
+vsetvli a2, a0, e32,m1,tu,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 
+
 vsetvl a2, a0, a1
 # CHECK-INST: vsetvl a2, a0, a1
 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
Index: llvm/test/MC/RISCV/rvv/store.s
===
--- llvm/test/MC/RISCV/rvv/store.s
+++ llvm/test/MC/RISCV/rvv/store.s
@@ -8,200 +8,296 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vsb.v v24, (a0), v0.t
-# CHECK-INST: vsb.v v24, (a0), v0.t
+vse8.v v24, (a0), v0.t
+# CHECK-INST: vse8.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 00 
 
-vsb.v v24, (a0)
-# CHECK-INST: vsb.v v24, (a0)
+vse8.v v24, (a0)
+# CHECK-INST: vse8.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 02 
 
-vsh.v v24, (a0), v0.t
-# CHECK-INST: vsh.v v24, (a0), v0.t
+vse16.v v24, (a0), v0.t
+# CHECK-INST: vse16.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 05 00 
 
-vsh.v v24, (a0)
-# CHECK-INST: vsh.v v24, (a0)
+vse16.v v24, (a0)
+# CHECK-INST: vse16.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:99
 // load vd, (rs1), vm
 class VUnitStrideLoad

fpallares wrote:
> I believe that with the changes introduced in the encoding of the loads and 
> stores we can do without the `mop` parameter in most of the classes here:
> 
> | class   | replace `mop` by   |
> |---|--|
> | `VUnitStrideLoad` | `MOPLDUnitStride` (i.e. `00`) |
> | `VStridedLoad` | `MOPLDStrided` (i.e. `10`) |
> | `VIndexedLoad` | `MOPLDIndexed` (i.e. `11`) |
> | `VUnitStrideStore` | `MOPSTUnitStride` (i.e. `00`) |
> | `VStridedStore` | `MOPLDStrided` (i.e. `10`) |
> 
> We still need to keep the parameter for the `VIndexedStore` class since it 
> can take `MOPSTIndexedOrder` (i.e. `11`) or `MOPSTIndexedUnord` (i.e. `01`).
> 
> Does this make sense to you?
It makes sense. Thanks.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D80802#2155432 , @simoncook wrote:

> Since this patch replaces 0.8 support with 0.9, it should include an update 
> to the version check in `clang/lib/Driver/ToolChains/Arch/RISCV.cpp` to match.


The modification is put in D81213 .


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D80802#2155802 , @fpallares wrote:

> Apologies we didn't identify this earlier but with the change of the mask 
> register layout (`MLEN=1`) the overlap constraints involving the mask 
> register were modified:
>
> //**RVV-0.8, Section 5.3. Vector Masking:**//
>
> > The destination vector register group for a masked vector instruction can 
> > only overlap the source mask register (v0) when LMUL=1. Otherwise, an 
> > illegal instruction exception is raised.
>
> //**RVV-0.9, Section 5.3. Vector Masking:**//
>
> > The destination vector register group for a masked vector instruction 
> > cannot overlap the source mask register (v0), unless the destination vector 
> > register is being written with a mask value (e.g., comparisons) or the 
> > scalar result of a reduction. Otherwise, an illegal instruction exception 
> > is raised.
>
> The change was introduced in this commit 
> .
>
> From my understanding, with this change an instruction such as the following 
> should be rejected in RVV-0.9:
>
>   vadd.vv v0, v1, v2, v0.t
>
>
> Also note that `vadc`/`vsbc` already have this behaviour.


Indeed, I did not take care of the mask register constraint for instructions. I 
will handle it in the next revision.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

Thanks for your review, @fpallares.


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[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

Ping.


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[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D69987#2074265 , @MaskRay wrote:

> Drive-by comment: the clang side change isn't tightly coupled with the LLVM 
> side changes. It should be a separate patch.


Create https://reviews.llvm.org/D81188 for clang side change.


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[PATCH] D81188: [RISCV] Support experimental v extensions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: MaskRay, rogfer01.
Herald added subscribers: cfe-commits, evandro, luismarques, apazos, 
sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, 
rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Herald added a project: clang.

This follows the design as discussed on the mailing lists in the
following RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html

Support for the vector 'v' extension v0.8.


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -360,3 +360,22 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP 
%s
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
+// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-V-NOVERS %s
+// RV32-EXPERIMENTAL-V-NOVERS: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s
+// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
+// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
+// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,6 +62,8 @@
   Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
+  if (Ext == "v")
+return RISCVExtensionVersion{"0", "8"};
   return None;
 }
 
@@ -399,6 +401,9 @@
 case 'b':
   Features.push_back("+experimental-b");
   break;
+case 'v':
+  Features.push_back("+experimental-v");
+  break;
 }
 
 // Consume full extension name and version, including any optional '_'


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -360,3 +360,22 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
+// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOVERS %s
+// RV32-EXPERIMENTAL-V-NOVERS: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s
+// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
+// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
+// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/Too

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56
+def NoConstraint : RISCVVConstraint<0>;
+def WidenV   : RISCVVConstraint<1>;
+def WidenW   : RISCVVConstraint<2>;

evandro wrote:
> Methinks that these constraints `WidenV`, `WidenW`, `WidenCvt`, should be 
> split up by their components.  IOW, into `Widen`, `Wide` (input), `Cvt`.  
> This way, it's easier to test for specific constraints.
Do you mean

WidenV = Widen;
WidenW = Widen | WideInput;
WidenCvt = Widen | Cvt;


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[PATCH] D81188: [RISCV] Support experimental v extensions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 268642.
HsiangKai added a comment.

Address @MaskRay's comments.


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Files:
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  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -360,3 +360,22 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP 
%s
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
+// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOVERS %s
+// RV32-EXPERIMENTAL-V-NOVERS: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s
+// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
+// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
+// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,6 +62,8 @@
   Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
+  if (Ext == "v")
+return RISCVExtensionVersion{"0", "8"};
   return None;
 }
 
@@ -399,6 +401,9 @@
 case 'b':
   Features.push_back("+experimental-b");
   break;
+case 'v':
+  Features.push_back("+experimental-v");
+  break;
 }
 
 // Consume full extension name and version, including any optional '_'


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -360,3 +360,22 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
+// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOVERS %s
+// RV32-EXPERIMENTAL-V-NOVERS: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s
+// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
+// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
+// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,6 +62,8 @@
   Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
+  if (Ext == "v")
+return RISCVExtensionVersion{"0", "8"};
   return None;
 }
 
@@ -399,6 +401,9 @@
 case 'b':
   Features.push_back("+experimental-b");
   break;
+case 'v':
+  Features.push_back("+experimental-v

[PATCH] D81213: [RISCV] Support experimental v extension v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: evandro, rogfer01, rkruppe.
Herald added subscribers: cfe-commits, luismarques, apazos, sameer.abuasal, 
pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Herald added a project: clang.
HsiangKai added a parent revision: D80802: [RISCV] Upgrade RVV MC to v0.9..

Change Clang options to support experimental v extension v0.9.


Repository:
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https://reviews.llvm.org/D81213

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -376,6 +376,6 @@
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for 
experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,7 +63,7 @@
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
-return RISCVExtensionVersion{"0", "8"};
+return RISCVExtensionVersion{"0", "9"};
   return None;
 }
 


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -376,6 +376,6 @@
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,7 +63,7 @@
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
-return RISCVExtensionVersion{"0", "8"};
+return RISCVExtensionVersion{"0", "9"};
   return None;
 }
 
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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2386
+CheckReg = Inst.getOperand(3).getReg();
 }
+if (DestReg == CheckReg)

fpallares wrote:
> fpallares wrote:
> > With the suggestion above, this could be further simplified to:
> > 
> > ```
> > ​if ((TargetFlags & RISCV::OneInput && Inst.getNumOperands() == 3) || 
> > Inst.getNumOperands() == 4)
> > ​  return Error(Loc, "The destination vector register group cannot 
> > overlap"
> > ​" the mask register.");
> > ```
> I see you have updated the patch and removed the `if` that checked whether we 
> were dealing with the masked versions of the instructions (by checking the 
> number of operands). IIUC that check is still necessary so we don't report an 
> error for unmasked instruction.
> 
> For example, from my understanding the following instruction is correct, but 
> we will be reporting an error.
> ```
> viota.m v0, v2
> ```
Good catch. Thank you.


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[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

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HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56
+def NoConstraint : RISCVVConstraint<0>;
+def WidenV   : RISCVVConstraint<1>;
+def WidenW   : RISCVVConstraint<2>;

evandro wrote:
> HsiangKai wrote:
> > evandro wrote:
> > > Methinks that these constraints `WidenV`, `WidenW`, `WidenCvt`, should be 
> > > split up by their components.  IOW, into `Widen`, `Wide` (input), `Cvt`.  
> > > This way, it's easier to test for specific constraints.
> > Do you mean
> > 
> > WidenV = Widen;
> > WidenW = Widen | WideInput;
> > WidenCvt = Widen | Cvt;
> Yes.
Got it. I will improve it based on v0.9 implementation.


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[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

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HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:9
+///
+/// This file describes the RISC-V instructions from the standard 'V',
+/// Vector instruction set extension.

asb wrote:
> Please add similar language as in RISCVInstrInfoB.td to indicate the version 
> being described and explain this version is experimental and hasn't been 
> ratified.
Got it. I will add more comments similar to RISCVInstrInfoB.td before landing 
the patch.


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[PATCH] D81188: [RISCV] Support experimental v extensions.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd698ff92a59c: [RISCV] Support experimental v extensions. 
(authored by HsiangKai).

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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -360,3 +360,22 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP 
%s
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
+// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOVERS %s
+// RV32-EXPERIMENTAL-V-NOVERS: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s
+// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
+// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
+// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,6 +62,8 @@
   Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
+  if (Ext == "v")
+return RISCVExtensionVersion{"0", "8"};
   return None;
 }
 
@@ -399,6 +401,9 @@
 case 'b':
   Features.push_back("+experimental-b");
   break;
+case 'v':
+  Features.push_back("+experimental-v");
+  break;
 }
 
 // Consume full extension name and version, including any optional '_'


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -360,3 +360,22 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
+// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOVERS %s
+// RV32-EXPERIMENTAL-V-NOVERS: error: invalid arch name 'rv32iv'
+// RV32-EXPERIMENTAL-V-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s
+// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
+// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
+// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,6 +62,8 @@
   Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
+  if (Ext == "v")
+return RISCVExtensionVersion{"0", "8"};
   return None;
 }
 
@@ -399,6 +401,9 @@
 case 'b':
   Features.push_back("+experimental-b");
 

[PATCH] D81213: [RISCV] Support experimental v extension v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG721d93fc5aa8: Support experimental v extension v0.9. 
(authored by HsiangKai).

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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -380,6 +380,6 @@
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for 
experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,7 +63,7 @@
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
-return RISCVExtensionVersion{"0", "8"};
+return RISCVExtensionVersion{"0", "9"};
   return None;
 }
 


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -380,6 +380,6 @@
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,7 +63,7 @@
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
-return RISCVExtensionVersion{"0", "8"};
+return RISCVExtensionVersion{"0", "9"};
   return None;
 }
 
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[PATCH] D106044: [RISCV] Update to vcpop.m, vlm.v and vsm.v according to v1.0-rc1.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D106044#2879361 , @rogfer01 wrote:

> I'm confused because the PDF at 
> https://github.com/riscv/riscv-v-spec/releases/tag/v1.0-rc1  doesn't seem to 
> describe  `vcpop.m`.
>
> I can see this has changed in the ToT 
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#changes-from-v1-0-rc1
>
> Perhaps this will be part of a future 1.0-rc2?

You are right. I will revert it. Thanks.


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[PATCH] D106049: [RISCV] Update to vfredusum.vs and vfwredusum.vs according to v1.0-rc1.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai abandoned this revision.
HsiangKai added a comment.

In D106049#2879422 , @frasercrmck 
wrote:

> Duplicate of D105690 ?

I didn't aware of it. Thanks.


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[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:926
+def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm",
+(VFREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm)>;
+

How about to set the `Emit` to 0 to lower the printing priority.

```
def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm",
(VFREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>;
```



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:940
+def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm",
+(VFWREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm)>;
+

Ditto.


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[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 359178.
HsiangKai added a comment.

Remove RV32 test cases.


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Files:
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/IdentifierTable.h
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/AST/ASTContext.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -411,7 +411,7 @@
   case ScalarTypeKind::Float:
 switch (ElementBitwidth) {
 case 16:
-  BuiltinStr += "h";
+  BuiltinStr += "x";
   break;
 case 32:
   BuiltinStr += "f";
@@ -507,7 +507,10 @@
 Str += "double";
   else if (ElementBitwidth == 32)
 Str += "float";
-  assert((ElementBitwidth == 32 || ElementBitwidth == 64) &&
+  else if (ElementBitwidth == 16)
+Str += "_Float16";
+  assert((ElementBitwidth == 16 || ElementBitwidth == 32 ||
+  ElementBitwidth == 64) &&
  "Unhandled floating type");
 } else
   Str += getTypeString("float");
@@ -565,7 +568,7 @@
 ElementBitwidth = 64;
 ScalarType = ScalarTypeKind::SignedInteger;
 break;
-  case 'h':
+  case 'x':
 ElementBitwidth = 16;
 ScalarType = ScalarTypeKind::Float;
 break;
@@ -931,7 +934,7 @@
   }
   OS << "#if defined(__riscv_zfh)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('h', Log2LMUL, "v");
+auto T = computeType('x', Log2LMUL, "v");
 if (T.hasValue())
   printType(T.getValue());
   }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
@@ -1,367 +1,487 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
-//
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf4_t test_vfadd_vv_f16mf4 (vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
+  return vfadd_vv_f16mf4(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv1f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf4_t test_vfadd_vf_f16mf4 (vfloat16mf4_t op1, _Float16 op2, size_t vl) {
+  return vfadd_vf_f16mf4(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf2_t test_vfadd_vv_f16mf2 (vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
+  return vfadd_vv_f16mf2(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv2f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf2_t test_vfadd_vf_f16mf2 (vfloat16mf2_t op1, _Float16 op2, size_t vl) {
+  return vfadd_vf_f16mf2(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16m1(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16m1_t test_vfadd_vv_f16m1 (vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+  return vfadd_vv_f16m1(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16m1(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv4f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16m1_t test_vfadd_vf_f16m1 (vfloat16m1_t op1, _Float16 op2, size_t vl) {
+  return vfadd_vf_f16m1(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV6

[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 359667.
HsiangKai added a comment.

Add else and llvm_unreachable() for unhandled floating types.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105001/new/

https://reviews.llvm.org/D105001

Files:
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/IdentifierTable.h
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/AST/ASTContext.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -411,7 +411,7 @@
   case ScalarTypeKind::Float:
 switch (ElementBitwidth) {
 case 16:
-  BuiltinStr += "h";
+  BuiltinStr += "x";
   break;
 case 32:
   BuiltinStr += "f";
@@ -507,8 +507,10 @@
 Str += "double";
   else if (ElementBitwidth == 32)
 Str += "float";
-  assert((ElementBitwidth == 32 || ElementBitwidth == 64) &&
- "Unhandled floating type");
+  else if (ElementBitwidth == 16)
+Str += "_Float16";
+  else
+llvm_unreachable("Unhandled floating type.");
 } else
   Str += getTypeString("float");
 break;
@@ -565,7 +567,7 @@
 ElementBitwidth = 64;
 ScalarType = ScalarTypeKind::SignedInteger;
 break;
-  case 'h':
+  case 'x':
 ElementBitwidth = 16;
 ScalarType = ScalarTypeKind::Float;
 break;
@@ -931,7 +933,7 @@
   }
   OS << "#if defined(__riscv_zfh)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('h', Log2LMUL, "v");
+auto T = computeType('x', Log2LMUL, "v");
 if (T.hasValue())
   printType(T.getValue());
   }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
@@ -1,367 +1,487 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
-//
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf4_t test_vfadd_vv_f16mf4 (vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
+  return vfadd_vv_f16mf4(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv1f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf4_t test_vfadd_vf_f16mf4 (vfloat16mf4_t op1, _Float16 op2, size_t vl) {
+  return vfadd_vf_f16mf4(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf2_t test_vfadd_vv_f16mf2 (vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
+  return vfadd_vv_f16mf2(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv2f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf2_t test_vfadd_vf_f16mf2 (vfloat16mf2_t op1, _Float16 op2, size_t vl) {
+  return vfadd_vf_f16mf2(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16m1(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16m1_t test_vfadd_vv_f16m1 (vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+  return vfadd_vv_f16m1(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16m1(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv4f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16m1_t test_vfadd_vf_f16m1 (vfloat16m1_t op1, _Float16 op2, size_t vl) {
+  return vfadd_vf_f16m1(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16m2(
+// CHECK-RV64-NEXT:  entry:
+/

[PATCH] D103796: [Clang][RISCV] Implement vlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 359703.
HsiangKai added a comment.

Correct the alignment of store.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103796/new/

https://reviews.llvm.org/D103796

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c

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[PATCH] D106255: [Clang][RISCV] Correct the alignment of stores generated by vlseg/vlsegff.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, frasercrmck, rogfer01.
Herald added subscribers: StephenFan, vkmr, dexonsmith, evandro, luismarques, 
apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106255

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c

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[PATCH] D106255: [Clang][RISCV] Correct the alignment of stores generated by vlseg/vlsegff.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 359718.
HsiangKai added a comment.

Update vlsegff test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106255/new/

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c

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[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG77bb82d06856: [Clang][RISCV] Support half-precision floating 
point for RVV intrinsics. (authored by HsiangKai).

Changed prior to commit:
  https://reviews.llvm.org/D105001?vs=359667&id=359798#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105001/new/

https://reviews.llvm.org/D105001

Files:
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/AST/ASTContext.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -415,7 +415,7 @@
   case ScalarTypeKind::Float:
 switch (ElementBitwidth) {
 case 16:
-  BuiltinStr += "h";
+  BuiltinStr += "x";
   break;
 case 32:
   BuiltinStr += "f";
@@ -516,8 +516,10 @@
 Str += "double";
   else if (ElementBitwidth == 32)
 Str += "float";
-  assert((ElementBitwidth == 32 || ElementBitwidth == 64) &&
- "Unhandled floating type");
+  else if (ElementBitwidth == 16)
+Str += "_Float16";
+  else
+llvm_unreachable("Unhandled floating type.");
 } else
   Str += getTypeString("float");
 break;
@@ -574,7 +576,7 @@
 ElementBitwidth = 64;
 ScalarType = ScalarTypeKind::SignedInteger;
 break;
-  case 'h':
+  case 'x':
 ElementBitwidth = 16;
 ScalarType = ScalarTypeKind::Float;
 break;
@@ -946,7 +948,7 @@
   }
   OS << "#if defined(__riscv_zfh)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('h', Log2LMUL, "v");
+auto T = computeType('x', Log2LMUL, "v");
 if (T.hasValue())
   printType(T.getValue());
   }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
@@ -1,367 +1,487 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
-//
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf4_t test_vfadd_vv_f16mf4 (vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
+  return vfadd_vv_f16mf4(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv1f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf4_t test_vfadd_vf_f16mf4 (vfloat16mf4_t op1, _Float16 op2, size_t vl) {
+  return vfadd_vf_f16mf4(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf2_t test_vfadd_vv_f16mf2 (vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
+  return vfadd_vv_f16mf2(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv2f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16mf2_t test_vfadd_vf_f16mf2 (vfloat16mf2_t op1, _Float16 op2, size_t vl) {
+  return vfadd_vf_f16mf2(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vv_f16m1(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16m1_t test_vfadd_vv_f16m1 (vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+  return vfadd_vv_f16m1(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfadd_vf_f16m1(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv4f16.f16.i64( [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+vfloat16m1_t test_vfadd_vf_f16m1 (vfl

[PATCH] D106255: [Clang][RISCV] Correct the alignment of stores generated by vlseg/vlsegff.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0d22dee2ca59: [Clang][RISCV] Correct the alignment of stores 
generated by vlseg/vlsegff. (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106255/new/

https://reviews.llvm.org/D106255

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c

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[PATCH] D106340: [Clang][RISCV] Add half-precision FP for vle16/vse16.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added a reviewer: craig.topper.
Herald added subscribers: StephenFan, vkmr, frasercrmck, dexonsmith, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

I missed to add half-precision FP types for vle16/vse16 in the previous
patches. Added them in this patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106340

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
@@ -1,11 +1,11 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
+// RUN:   -disable-O0-optnone  -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -16,7 +16,6 @@
   return vse8_v_i8mf8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -27,7 +26,6 @@
   return vse8_v_i8mf4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -38,7 +36,6 @@
   return vse8_v_i8mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -49,7 +46,6 @@
   return vse8_v_i8m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -60,7 +56,6 @@
   return vse8_v_i8m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -71,7 +66,6 @@
   return vse8_v_i8m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -82,7 +76,6 @@
   return vse8_v_i8m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -93,7 +86,6 @@
   return vse16_v_i16mf4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -104,7 +96,6 @@
   return vse16_v_i16mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -115,7 +106,6 @@
   return vse16_v_i16m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -126,7 +116,6 @@
   return vse16_v_i16m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -137,7 +126,6 @@
   return vse16_v_i16m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -148,7 +136,6 @@
   return vse16_v_i16m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to *
@@ -159,7 +146,6 @@
   return vse32_v_i32mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to *
@@ -170,7 +156,6 @@
   return vse32_v_i32m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to *
@@ 

[PATCH] D103809: [Clang][RISCV] Implement vloxseg and vluxseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 360013.
HsiangKai added a comment.

Correct alignment.


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[PATCH] D103796: [Clang][RISCV] Implement vlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 360024.
HsiangKai added a comment.

Remove RV32 test cases.


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  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c

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[PATCH] D103809: [Clang][RISCV] Implement vloxseg and vluxseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 360026.
HsiangKai added a comment.

Remove RV32 test cases.


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[PATCH] D103873: [Clang][RISCV] Implement vsoxseg and vsuxseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 360042.
HsiangKai added a comment.

Remove RV32 test cases.


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  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
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[PATCH] D106340: [Clang][RISCV] Add half-precision FP for vle16/vse16.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG89ce6449024d: [Clang][RISCV] Add half-precision FP for 
vle16/vse16. (authored by HsiangKai).

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  clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
@@ -1,11 +1,11 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
+// RUN:   -disable-O0-optnone  -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -16,7 +16,6 @@
   return vse8_v_i8mf8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -27,7 +26,6 @@
   return vse8_v_i8mf4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -38,7 +36,6 @@
   return vse8_v_i8mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -49,7 +46,6 @@
   return vse8_v_i8m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -60,7 +56,6 @@
   return vse8_v_i8m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -71,7 +66,6 @@
   return vse8_v_i8m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
@@ -82,7 +76,6 @@
   return vse8_v_i8m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -93,7 +86,6 @@
   return vse16_v_i16mf4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -104,7 +96,6 @@
   return vse16_v_i16mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -115,7 +106,6 @@
   return vse16_v_i16m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -126,7 +116,6 @@
   return vse16_v_i16m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -137,7 +126,6 @@
   return vse16_v_i16m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to *
@@ -148,7 +136,6 @@
   return vse16_v_i16m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to *
@@ -159,7 +146,6 @@
   return vse32_v_i32mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to *
@@ -170,7 +156,6 @@
   return vse32_v_i32m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to *
@@ -181,7 +166,6 @@
   return vse32_v_i32m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to *
@@ -192,7 +176,6 @@
   return vse32_v_i32m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_v

[PATCH] D103796: [Clang][RISCV] Implement vlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa9de8f7a5391: [Clang][RISCV] Implement vlsseg. (authored by 
HsiangKai).

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  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c

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[PATCH] D103809: [Clang][RISCV] Implement vloxseg and vluxseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1c55033ea16f: [Clang][RISCV] Implement vloxseg and vluxseg. 
(authored by HsiangKai).

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  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c

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[PATCH] D103873: [Clang][RISCV] Implement vsoxseg and vsuxseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG698f288fa16c: [Clang][RISCV] Implement vsoxseg and vsuxseg. 
(authored by HsiangKai).

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  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c

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[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10
 /// This file describes the RISC-V instructions from the standard 'V' Vector
 /// extension, version 0.10.
 /// This version is still experimental as the 'V' extension hasn't been

frasercrmck wrote:
> khchen wrote:
> > jacquesguan wrote:
> > > khchen wrote:
> > > > Do we need to update 0.10 to 1.0-rc?
> > > > If the answer is yes, I think maybe we also need to update the clang 
> > > > part (ex. arch parsing, predefine macro) in follow-up patches.
> > > > 
> > > > 
> > > Maybe update it after finishing all changes in 1.0-rc?
> > > Maybe update it after finishing all changes in 1.0-rc?
> > Yes.
> > 
> > The other questions like how do you encode `rc1` in `march` or predefined 
> > architecture extension macro.
> > or maybe we could just use 1.0 directly because v is still an experiential 
> > extension.
> > 
> > @luismarques  @frasercrmck @craig.topper @HsiangKai What do you think?
> Maybe we can discuss in the call today, but my initial thoughts would be to 
> just say 1.0 for the reasons you specified.
> 
> Perhaps there's already precedent in dealing with release-candidate specs for 
> the base ISA or other extensions?
I expect v1.0-rc1 will have no big change, especially for these renaming 
issues. I vote for 1.0 for the experimental extension.


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[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:680
   foreach type = TypeList in {
-foreach eew_list = EEWList in {
+foreach eew_list = Xlen32EEWList in {
   defvar eew = eew_list[0];

There is no need to define `Xlen32EEWList`. You could use `EEWList[0-2]` for 
the purpose.


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[PATCH] D106939: [RISCV] If the maskedoff is vundefined(), use ta, ma for vsetvli.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: frasercrmck, khchen, arcbbb, rogfer01, evandro, 
craig.topper.
Herald added subscribers: StephenFan, vkmr, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

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Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll


Index: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+
+declare  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+  ,
+  ,
+  ,
+  ,
+  i64);
+
+define  @intrinsic_vadd_maskedoff_undef( %0, 
 %1,  %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_maskedoff_undef:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:vadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+  %a = call  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ undef,
+ %0,
+ %1,
+ %2,
+i64 %3)
+
+  ret  %a
+}
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -376,17 +376,27 @@
   // over the tail values. Some pseudo instructions force a tail agnostic 
policy
   // despite having a tied def.
   bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags);
+  // hasDummyMaskOp(TSFlags) == ture means it is a non-masked instruction.
+  // FIXME: hasDummyMaskOp() is the closest attribute to distinguish masked
+  // and non-masked instructions. However, there are some exceptions for this
+  // attribute. PseudoVMV_V_[VXI] and PseudoVFMV_V_F have no need to append
+  // the dummy mask operand in MC lowering and they are non-masked 
instructions.
+  bool MaskAgnostic = RISCVII::hasDummyMaskOp(TSFlags) ? true : false;
   bool TailAgnostic = true;
   unsigned UseOpIdx;
-  if (!ForceTailAgnostic && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
-TailAgnostic = false;
-// If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
+  if (MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
+if (!ForceTailAgnostic)
+  TailAgnostic = false;
+// If the tied operand is an IMPLICIT_DEF we can keep MaskAgnostic and
+// TailAgnostic.
 const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
 MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
 if (UseMI) {
   UseMI = elideCopies(UseMI, MRI);
-  if (UseMI && UseMI->isImplicitDef())
+  if (UseMI && UseMI->isImplicitDef()) {
+MaskAgnostic = true;
 TailAgnostic = true;
+  }
 }
   }
 
@@ -399,7 +409,7 @@
   } else
 InstrInfo.setAVLReg(RISCV::NoRegister);
   InstrInfo.setVTYPE(VLMul, SEW, /*TailAgnostic*/ TailAgnostic,
- /*MaskAgnostic*/ false, MaskRegOp);
+ /*MaskAgnostic*/ MaskAgnostic, MaskRegOp);
 
   return InstrInfo;
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
@@ -0,0 +1,16 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg \
+// RUN:   | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  
@llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], 
i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m1_t test_vadd_vv_i8m1_m (vbool8_t mask, vint8m1_t op1, vint8m1_t op2, 
size_t vl) {
+  return vadd_vv_i8m1_m(mask, vundefined_i8m1(), op1, op2, vl);
+}


Index: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --risc

[PATCH] D106939: [RISCV] If the maskedoff is vundefined(), use ta, ma for vsetvli.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 362617.
HsiangKai added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll


Index: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+
+declare  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+  ,
+  ,
+  ,
+  ,
+  i64);
+
+define  @intrinsic_vadd_maskedoff_undef( %0, 
 %1,  %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_maskedoff_undef:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:vadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+  %a = call  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ undef,
+ %0,
+ %1,
+ %2,
+i64 %3)
+
+  ret  %a
+}
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -376,17 +376,24 @@
   // over the tail values. Some pseudo instructions force a tail agnostic 
policy
   // despite having a tied def.
   bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags);
+  bool MaskAgnostic = true;
   bool TailAgnostic = true;
   unsigned UseOpIdx;
-  if (!ForceTailAgnostic && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
-TailAgnostic = false;
-// If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
+  if (MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
+// hasDummyMaskOp(TSFlags) == true means it is a non-masked instruction.
+MaskAgnostic = RISCVII::hasDummyMaskOp(TSFlags);
+if (!ForceTailAgnostic)
+  TailAgnostic = false;
+// If the tied operand is an IMPLICIT_DEF we can keep MaskAgnostic and
+// TailAgnostic.
 const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
 MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
 if (UseMI) {
   UseMI = elideCopies(UseMI, MRI);
-  if (UseMI && UseMI->isImplicitDef())
+  if (UseMI && UseMI->isImplicitDef()) {
+MaskAgnostic = true;
 TailAgnostic = true;
+  }
 }
   }
 
@@ -399,7 +406,7 @@
   } else
 InstrInfo.setAVLReg(RISCV::NoRegister);
   InstrInfo.setVTYPE(VLMul, SEW, /*TailAgnostic*/ TailAgnostic,
- /*MaskAgnostic*/ false, MaskRegOp);
+ /*MaskAgnostic*/ MaskAgnostic, MaskRegOp);
 
   return InstrInfo;
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
@@ -0,0 +1,16 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg \
+// RUN:   | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  
@llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], 
i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m1_t test_vadd_vv_i8m1_m (vbool8_t mask, vint8m1_t op1, vint8m1_t op2, 
size_t vl) {
+  return vadd_vv_i8m1_m(mask, vundefined_i8m1(), op1, op2, vl);
+}


Index: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+
+declare  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+  ,
+  ,
+  ,
+  ,
+  i64);
+
+define  @intrinsic_vadd_maskedoff_undef( %0,  %1,  %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_maskedoff_undef:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:vadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+  %a = call  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ undef,
+ %0,
+ %1,
+ %2,
+i64 %3)
+
+  ret  %a
+}
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===
--- llvm/lib/Target/RI

[PATCH] D106939: [RISCV] If the maskedoff is vundefined(), use ta, ma for vsetvli.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 362920.
HsiangKai added a comment.

- Add more comments.
- Remove unnecessary `--riscv-no-aliases` in the test case.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D106939/new/

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Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll


Index: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+declare  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+  ,
+  ,
+  ,
+  ,
+  i64);
+
+define  @intrinsic_vadd_maskedoff_undef( %0, 
 %1,  %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_maskedoff_undef:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:vadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+  %a = call  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ undef,
+ %0,
+ %1,
+ %2,
+i64 %3)
+
+  ret  %a
+}
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -377,16 +377,25 @@
   // despite having a tied def.
   bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags);
   bool TailAgnostic = true;
+  // Default to mask agnostic unless the operation is masked and the 
destination
+  // is tied to a source. If the source is undef, keep it as mask agnostic.
+  bool MaskAgnostic = true;
   unsigned UseOpIdx;
-  if (!ForceTailAgnostic && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
-TailAgnostic = false;
-// If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
+  if (MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
+// hasDummyMaskOp(TSFlags) == true means it is a non-masked instruction.
+MaskAgnostic = RISCVII::hasDummyMaskOp(TSFlags);
+if (!ForceTailAgnostic)
+  TailAgnostic = false;
+// If the tied operand is an IMPLICIT_DEF we can keep MaskAgnostic and
+// TailAgnostic.
 const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
 MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
 if (UseMI) {
   UseMI = elideCopies(UseMI, MRI);
-  if (UseMI && UseMI->isImplicitDef())
+  if (UseMI && UseMI->isImplicitDef()) {
+MaskAgnostic = true;
 TailAgnostic = true;
+  }
 }
   }
 
@@ -398,8 +407,7 @@
   InstrInfo.setAVLReg(VLOp.getReg());
   } else
 InstrInfo.setAVLReg(RISCV::NoRegister);
-  InstrInfo.setVTYPE(VLMul, SEW, /*TailAgnostic*/ TailAgnostic,
- /*MaskAgnostic*/ false, MaskRegOp);
+  InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic, MaskRegOp);
 
   return InstrInfo;
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
@@ -0,0 +1,16 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg \
+// RUN:   | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  
@llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], 
i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint8m1_t test_vadd_vv_i8m1_m (vbool8_t mask, vint8m1_t op1, vint8m1_t op2, 
size_t vl) {
+  return vadd_vv_i8m1_m(mask, vundefined_i8m1(), op1, op2, vl);
+}


Index: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+declare  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+  ,
+  ,
+  ,
+  ,
+  i64);
+
+define  @intrinsic_vadd_maskedoff_undef( %0,  %1,  %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_maskedoff_undef:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:vadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+  %a = call  @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ undef,
+ %0,
+ %1,
+ %2,
+i64 %3)
+
+ 

[PATCH] D106939: [RISCV] If the maskedoff is vundefined(), use ta, ma for vsetvli.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D106939#2912807 , @frasercrmck 
wrote:

> LGTM but there are test failures. Is that just a whole load of `mu->ma` 
> changes that have been omitted for a smaller diff?

Updated test cases are put in https://reviews.llvm.org/D107022.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

kito-cheng wrote:
> khchen wrote:
> > evandro wrote:
> > > craig.topper wrote:
> > > > craig.topper wrote:
> > > > > jrtc27 wrote:
> > > > > > liaolucy wrote:
> > > > > > > RISC-V V has too many types, more than 200. All types use builtin 
> > > > > > > types? Is it possible to reduce the number of builtin types?
> > > > > > Indeed this is madness, what's wrong with just using 
> > > > > > `__attribute__((vector_size(n)))` on the right type? We should not 
> > > > > > be encouraging people to write code with architecture-specific 
> > > > > > types... but if we _really_ need these because RISC-V GCC decided 
> > > > > > this is how RISC-V V is going to look them can we not just shove 
> > > > > > them all in a header as typedef's for the architecture-independent 
> > > > > > attributed types and push that complexity out of the compiler 
> > > > > > itself?
> > > > > We are using  to specify types in IR. The size of 
> > > > > the fixed part is being used to control the LMUL parameter. There is 
> > > > > currently no way to spell a scalable vector type in C in a generic 
> > > > > way.
> > > > > 
> > > > > Alternatively I guess we could make LMUL a parameter to the intrinsic 
> > > > > and create the scalable IR types in the frontend based on it?
> > > > I do wonder why we bothered to have signed and unsigned types. The 
> > > > signedness of the operation should be carried in the intrinsic name.
> > > Some integer operations distinguish between signed and unsigned.  
> > > I do wonder why we bothered to have signed and unsigned types. The 
> > > signedness of the operation should be carried in the intrinsic name.
> > 
> > I think the only good thing for supporting both signed and unsigned type is 
> > that are more readable and compiler can does type checking for programmer. 
> > 
> > maybe the alternative way is changing intrinsic naming rule like 
> > 
> > ```
> > vint32m1_t a, b, c;
> > a = vadd_i32m1(b, c);
> > vuint32m1_t a, b, c;
> > a = vadd_u32m1(b, c);
> > vfloat32m1_t a, b, c;
> > a = vadd_f32m1(b, c);
> > ```
> One quick thought about this, if the concern is too much built-in types are 
> introduced in clang, maybe we could add a new attribute like 
> `__attribute__((vector_size(n)))`, maybe named 
> `__attribute__((riscv_scaleble_vector("[1|2|4|8|f2|f4|f8]")))`? and use that 
> to define vector types like `typedef int 
> __attribute__((riscv_scaleble_vector("2"))) vintm2_t`.
To have signed and unsigned types, we could do type checking for the builtins. 
For example, we have vmaxu_vv and vmax_vv. Users could pass signed vector types 
into unsigned version vmaxu_vv if we only have types without signed/unsigned. 
How could we tell users they pass values into the wrong builtins?


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[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:194
   HasV = true;
-else if (Feature == "+experimental-zfh")
+  HasRISCVVTypes = true;
+} else if (Feature == "+experimental-zfh")

khchen wrote:
> HasRISCVVTypes is an undefined variable?
I should move the snippet to D92715.


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[PATCH] D91315: [RISCV] Handle zfh in the arch string.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.scott, asb, kito-cheng, luismarques, Jim.
Herald added subscribers: cfe-commits, frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, lenary, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
niosHD, sabuasal, simoncook, johnrusso, rbar.
Herald added a project: clang.
HsiangKai requested review of this revision.
Herald added a subscriber: MaskRay.

Zfh in the arch string.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91315

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -78,3 +78,9 @@
 // CHECK-DOUBLE: __riscv_float_abi_double 1
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
+
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
+// CHECK-ZFH-EXT: __riscv_zfh 1
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -383,3 +383,12 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZFH-NOFLAG %s
+// RV32-EXPERIMENTAL-ZFH-NOFLAG: error: invalid arch name 'rv32izfh'
+// RV32-EXPERIMENTAL-ZFH-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
+// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -64,6 +64,8 @@
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
 return RISCVExtensionVersion{"0", "9"};
+  if (Ext == "zfh")
+return RISCVExtensionVersion{"0", "1"};
   return None;
 }
 
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,11 +31,12 @@
   bool HasD;
   bool HasC;
   bool HasB;
+  bool HasZfh;
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
-  : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false), HasB(false) {
+  : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false),
+HasC(false), HasB(false), HasZfh(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = &llvm::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -129,6 +129,9 @@
 
   if (HasB)
 Builder.defineMacro("__riscv_bitmanip");
+
+  if (HasZfh)
+Builder.defineMacro("__riscv_zfh");
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -144,6 +147,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-zfh", HasZfh)
   .Default(false);
 }
 
@@ -163,6 +167,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = true;
+else if (Feature == "+experimental-zfh")
+  HasZfh = true;
   }
 
   return true;


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -78,3 +78,9 @@
 // CHECK-DOUBLE: __riscv_float_abi_double 1
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
+

[PATCH] D91315: [RISCV] Handle zfh in the arch string.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG432d05174ed0: [RISCV] Handle zfh in the arch string. 
(authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91315/new/

https://reviews.llvm.org/D91315

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -78,3 +78,9 @@
 // CHECK-DOUBLE: __riscv_float_abi_double 1
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
+
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
+// CHECK-ZFH-EXT: __riscv_zfh 1
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -383,3 +383,12 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZFH-NOFLAG %s
+// RV32-EXPERIMENTAL-ZFH-NOFLAG: error: invalid arch name 'rv32izfh'
+// RV32-EXPERIMENTAL-ZFH-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
+// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -64,6 +64,8 @@
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
 return RISCVExtensionVersion{"0", "9"};
+  if (Ext == "zfh")
+return RISCVExtensionVersion{"0", "1"};
   return None;
 }
 
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,11 +31,12 @@
   bool HasD;
   bool HasC;
   bool HasB;
+  bool HasZfh;
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
-  : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false), HasB(false) {
+  : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false),
+HasC(false), HasB(false), HasZfh(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = &llvm::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -135,6 +135,9 @@
 
   if (HasB)
 Builder.defineMacro("__riscv_bitmanip");
+
+  if (HasZfh)
+Builder.defineMacro("__riscv_zfh");
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -150,6 +153,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-zfh", HasZfh)
   .Default(false);
 }
 
@@ -169,6 +173,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = true;
+else if (Feature == "+experimental-zfh")
+  HasZfh = true;
   }
 
   return true;


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -78,3 +78,9 @@
 // CHECK-DOUBLE: __riscv_float_abi_double 1
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
+// 

[PATCH] D92650: [RISCV] Define preprocessor definitions for 'V' extension.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, asb, luismarques, evandro.
Herald added subscribers: frasercrmck, NickHung, apazos, sameer.abuasal, 
pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92650

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -79,6 +79,14 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_vector 1
+//
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,12 +31,13 @@
   bool HasD;
   bool HasC;
   bool HasB;
+  bool HasV;
   bool HasZfh;
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false),
-HasC(false), HasB(false), HasZfh(false) {
+HasC(false), HasB(false), HasV(false), HasZfh(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = &llvm::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -136,6 +136,9 @@
   if (HasB)
 Builder.defineMacro("__riscv_bitmanip");
 
+  if (HasV)
+Builder.defineMacro("__riscv_vector");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh");
 }
@@ -153,6 +156,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-v", HasV)
   .Case("experimental-zfh", HasZfh)
   .Default(false);
 }
@@ -173,6 +177,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = true;
+else if (Feature == "+experimental-v")
+  HasV = true;
 else if (Feature == "+experimental-zfh")
   HasZfh = true;
   }


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -79,6 +79,14 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_vector 1
+//
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,12 +31,13 @@
   bool HasD;
   bool HasC;
   bool HasB;
+  bool HasV;
   bool HasZfh;
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false),
-HasC(false), HasB(false), HasZfh(false) {
+HasC(false), HasB(false), HasV(false), HasZfh(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = &llvm::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.c

[PATCH] D92650: [RISCV] Define preprocessor definitions for 'V' extension.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5e953a274b2a: [RISCV] Define preprocessor definitions for 
'V' extension. (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92650/new/

https://reviews.llvm.org/D92650

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -79,6 +79,14 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_vector 1
+//
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,12 +31,13 @@
   bool HasD;
   bool HasC;
   bool HasB;
+  bool HasV;
   bool HasZfh;
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false),
-HasC(false), HasB(false), HasZfh(false) {
+HasC(false), HasB(false), HasV(false), HasZfh(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = &llvm::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -136,6 +136,9 @@
   if (HasB)
 Builder.defineMacro("__riscv_bitmanip");
 
+  if (HasV)
+Builder.defineMacro("__riscv_vector");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh");
 }
@@ -153,6 +156,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-v", HasV)
   .Case("experimental-zfh", HasZfh)
   .Default(false);
 }
@@ -173,6 +177,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = true;
+else if (Feature == "+experimental-v")
+  HasV = true;
 else if (Feature == "+experimental-zfh")
   HasZfh = true;
   }


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -79,6 +79,14 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_vector 1
+//
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,12 +31,13 @@
   bool HasD;
   bool HasC;
   bool HasB;
+  bool HasV;
   bool HasZfh;
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false),
-HasC(false), HasB(false), HasZfh(false) {
+HasC(false), HasB(false), HasV(false), HasZfh(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = &llvm::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -136,6 +136,9 @@
   if (HasB)
 Builder.defineMacro("__riscv_bitmanip");
 
+  if (HasV)
+Bu

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:32
+// - ElBits is the size of one element in bits (SEW).
+//
+// - IsSigned is true for vectors of signed integer elements and

craig.topper wrote:
> NF argument isn't documented. And is always 1.
> NF argument isn't documented. And is always 1.

We could remove it in this patch. The field will be needed when we are going to 
upstream Zvlsseg implementation.



Comment at: clang/lib/AST/ASTContext.cpp:2178
+  Width = 0; \
+  Align = 128; \
+  break;

craig.topper wrote:
> Does this alignment need to be this high? The VMV0 register class in the 
> backend has an alignment of 64 for spills. Just wondering why they aren't 
> consistent.
> Does this alignment need to be this high? The VMV0 register class in the 
> backend has an alignment of 64 for spills. Just wondering why they aren't 
> consistent.

Indeed, it should be 64.



Comment at: clang/lib/CodeGen/CGDebugInfo.cpp:779
+
+  uint64_t Size = 0; // This is a scalable vector. See DwarfUnit.cpp:1414.
+  auto Align = getTypeAlignIfRequired(BT, CGM.getContext());

craig.topper wrote:
> Is there a function name in DwarfUnt.cpp that would be a better reference 
> here? Line numbers aren't stable.
> Is there a function name in DwarfUnt.cpp that would be a better reference 
> here? Line numbers aren't stable.

It should be `hasVectorBeenPadded()`. I have a downstream modification not 
upstreamed. We could remove the debug info for RVV types from this patch. I 
think it could be another patch for  debug info for scalable vector types.


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[PATCH] D102822: [Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, frasercrmck, rogfer01.
Herald added subscribers: StephenFan, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

If the memory object is scalable type, we do not know the exact size of
it at compile time. Set the size of lifetime marker to unknown if the
object is scalable one.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102822

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGDecl.cpp
  clang/lib/CodeGen/CGExprAgg.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/RISCV/riscv-v-lifetime.c

Index: clang/test/CodeGen/RISCV/riscv-v-lifetime.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-v-lifetime.c
@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm \
+// RUN:   -O1 -o - %s | FileCheck %s
+
+#include 
+
+extern void use(vint32m1_t *a);
+
+// CHECK-LABEL: @inlined(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A:%.*]] = alloca , align 4
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast * [[A]] to i8*
+// CHECK-NEXT:call void @llvm.lifetime.start.p0i8(i64 -1, i8* nonnull [[TMP0]]) #[[ATTR4:[0-9]+]]
+// CHECK-NEXT:call void @use(* nonnull [[A]]) #[[ATTR4]]
+// CHECK-NEXT:call void @llvm.lifetime.end.p0i8(i64 -1, i8* nonnull [[TMP0]]) #[[ATTR4]]
+// CHECK-NEXT:ret void
+//
+__attribute__((always_inline)) void inlined() {
+  vint32m1_t a;
+  use(&a);
+}
+
+// CHECK-LABEL: @lifetime_test(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_I:%.*]] = alloca , align 4
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast * [[A_I]] to i8*
+// CHECK-NEXT:call void @llvm.lifetime.start.p0i8(i64 -1, i8* nonnull [[TMP0]]) #[[ATTR4]]
+// CHECK-NEXT:call void @use(* nonnull [[A_I]]) #[[ATTR4]]
+// CHECK-NEXT:call void @llvm.lifetime.end.p0i8(i64 -1, i8* nonnull [[TMP0]]) #[[ATTR4]]
+// CHECK-NEXT:ret void
+//
+void lifetime_test() {
+  inlined();
+}
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -2872,7 +2872,7 @@
   void EmitSehTryScopeBegin();
   void EmitSehTryScopeEnd();
 
-  llvm::Value *EmitLifetimeStart(uint64_t Size, llvm::Value *Addr);
+  llvm::Value *EmitLifetimeStart(llvm::TypeSize Size, llvm::Value *Addr);
   void EmitLifetimeEnd(llvm::Value *Size, llvm::Value *Addr);
 
   llvm::Value *EmitCXXNewExpr(const CXXNewExpr *E);
Index: clang/lib/CodeGen/CGExprAgg.cpp
===
--- clang/lib/CodeGen/CGExprAgg.cpp
+++ clang/lib/CodeGen/CGExprAgg.cpp
@@ -276,7 +276,7 @@
 RetAddr = Dest.getAddress();
   } else {
 RetAddr = CGF.CreateMemTemp(RetTy, "tmp", &RetAllocaAddr);
-uint64_t Size =
+llvm::TypeSize Size =
 CGF.CGM.getDataLayout().getTypeAllocSize(CGF.ConvertTypeForMem(RetTy));
 LifetimeSizePtr = CGF.EmitLifetimeStart(Size, RetAllocaAddr.getPointer());
 if (LifetimeSizePtr) {
Index: clang/lib/CodeGen/CGDecl.cpp
===
--- clang/lib/CodeGen/CGDecl.cpp
+++ clang/lib/CodeGen/CGDecl.cpp
@@ -1317,11 +1317,15 @@
 /// Emit a lifetime.begin marker if some criteria are satisfied.
 /// \return a pointer to the temporary size Value if a marker was emitted, null
 /// otherwise
-llvm::Value *CodeGenFunction::EmitLifetimeStart(uint64_t Size,
+llvm::Value *CodeGenFunction::EmitLifetimeStart(llvm::TypeSize Size,
 llvm::Value *Addr) {
   if (!ShouldEmitLifetimeMarkers)
 return nullptr;
 
+  // Use -1 as the unknown size.
+  if (Size.isScalable())
+Size = llvm::TypeSize::Fixed(-1);
+
   assert(Addr->getType()->getPointerAddressSpace() ==
  CGM.getDataLayout().getAllocaAddrSpace() &&
  "Pointer should be in alloca address space");
@@ -1551,9 +1555,7 @@
   llvm::TypeSize size =
   CGM.getDataLayout().getTypeAllocSize(allocaTy);
   emission.SizeForLifetimeMarkers =
-  size.isScalable() ? EmitLifetimeStart(-1, AllocaAddr.getPointer())
-: EmitLifetimeStart(size.getFixedSize(),
-AllocaAddr.getPointer());
+  EmitLifetimeStart(size, AllocaAddr.getPointer());
 }
   } else {
 assert(!emission.useLifetimeMarkers());
Index: clang/lib/CodeGen/CGCall.cpp
===
--

[PATCH] D102822: [Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D102822#2770175 , @craig.topper 
wrote:

> Am I mistaken, or does this test already pass without these changes?

You are right. I didn't confirm it. I need to update the test case. Thanks.


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[PATCH] D102822: [Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 346656.
HsiangKai added a comment.

Update the test case.


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Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGDecl.cpp
  clang/lib/CodeGen/CGExprAgg.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp

Index: clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
@@ -0,0 +1,30 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-v \
+// RUN:   -emit-llvm -O1 -o - %s | FileCheck %s
+
+#include 
+
+template 
+void Foo(T &&);
+
+template 
+T Baz();
+
+// CHECK-LABEL: @_Z4Testv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[REF_TMP:%.*]] = alloca , align 8
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast * [[REF_TMP]] to i8*
+// CHECK-NEXT:call void @llvm.lifetime.start.p0i8(i64 -1, i8* nonnull [[TMP0]]) #[[ATTR3:[0-9]+]]
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z3BazIu15__rvv_int32m1_tET_v() #[[ATTR3]]
+// CHECK-NEXT:store  [[CALL]], * [[REF_TMP]], align 8, !tbaa [[TBAA4:![0-9]+]]
+// CHECK-NEXT:call void @_Z3FooIRKu15__rvv_int32m1_tEvOT_(* nonnull align 4 [[REF_TMP]]) #[[ATTR3]]
+// CHECK-NEXT:[[TMP1:%.*]] = load , * [[REF_TMP]], align 8, !tbaa [[TBAA4]]
+// CHECK-NEXT:call void @llvm.lifetime.end.p0i8(i64 -1, i8* nonnull [[TMP0]]) #[[ATTR3]]
+// CHECK-NEXT:ret  [[TMP1]]
+//
+vint32m1_t Test() {
+  const vint32m1_t &a = Baz();
+  Foo(a);
+  return a;
+}
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -2872,7 +2872,7 @@
   void EmitSehTryScopeBegin();
   void EmitSehTryScopeEnd();
 
-  llvm::Value *EmitLifetimeStart(uint64_t Size, llvm::Value *Addr);
+  llvm::Value *EmitLifetimeStart(llvm::TypeSize Size, llvm::Value *Addr);
   void EmitLifetimeEnd(llvm::Value *Size, llvm::Value *Addr);
 
   llvm::Value *EmitCXXNewExpr(const CXXNewExpr *E);
Index: clang/lib/CodeGen/CGExprAgg.cpp
===
--- clang/lib/CodeGen/CGExprAgg.cpp
+++ clang/lib/CodeGen/CGExprAgg.cpp
@@ -276,7 +276,7 @@
 RetAddr = Dest.getAddress();
   } else {
 RetAddr = CGF.CreateMemTemp(RetTy, "tmp", &RetAllocaAddr);
-uint64_t Size =
+llvm::TypeSize Size =
 CGF.CGM.getDataLayout().getTypeAllocSize(CGF.ConvertTypeForMem(RetTy));
 LifetimeSizePtr = CGF.EmitLifetimeStart(Size, RetAllocaAddr.getPointer());
 if (LifetimeSizePtr) {
Index: clang/lib/CodeGen/CGDecl.cpp
===
--- clang/lib/CodeGen/CGDecl.cpp
+++ clang/lib/CodeGen/CGDecl.cpp
@@ -1317,11 +1317,15 @@
 /// Emit a lifetime.begin marker if some criteria are satisfied.
 /// \return a pointer to the temporary size Value if a marker was emitted, null
 /// otherwise
-llvm::Value *CodeGenFunction::EmitLifetimeStart(uint64_t Size,
+llvm::Value *CodeGenFunction::EmitLifetimeStart(llvm::TypeSize Size,
 llvm::Value *Addr) {
   if (!ShouldEmitLifetimeMarkers)
 return nullptr;
 
+  // Use -1 as the unknown size.
+  if (Size.isScalable())
+Size = llvm::TypeSize::Fixed(-1);
+
   assert(Addr->getType()->getPointerAddressSpace() ==
  CGM.getDataLayout().getAllocaAddrSpace() &&
  "Pointer should be in alloca address space");
@@ -1551,9 +1555,7 @@
   llvm::TypeSize size =
   CGM.getDataLayout().getTypeAllocSize(allocaTy);
   emission.SizeForLifetimeMarkers =
-  size.isScalable() ? EmitLifetimeStart(-1, AllocaAddr.getPointer())
-: EmitLifetimeStart(size.getFixedSize(),
-AllocaAddr.getPointer());
+  EmitLifetimeStart(size, AllocaAddr.getPointer());
 }
   } else {
 assert(!emission.useLifetimeMarkers());
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -4679,7 +4679,7 @@
 } else {
   SRetPtr = CreateMemTemp(RetTy, "tmp", &SRetAlloca);
   if (HaveInsertPoint() && ReturnValue.isUnused()) {
-uint64_t size =
+llvm::TypeSize size =
 CGM.getDataLayout().getTypeAllocSize(ConvertTypeForMem(RetTy));
 UnusedReturnSizePtr = EmitLifetimeStart(size, SRetAlloca.getPointer());
   }
@@ -4840,7 +4840,7 @@
   IRCallArgs[FirstIRArg] = AI.getPointer();
 
   // Emit lifetime markers for the temporary alloca.
-  uint64_

[PATCH] D103527: [Clang][RISCV] Implement vlseg and vlsegff.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: frasercrmck, craig.topper, rogfer01.
Herald added subscribers: StephenFan, vkmr, dexonsmith, evandro, luismarques, 
apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Implement the new Zvlsseg intrinsic interface proposed in 
https://github.com/riscv/rvv-intrinsic-doc/issues/95


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  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/utils/TableGen/RISCVVEmitter.cpp

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[PATCH] D102822: [Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

Ping.


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D94583#2513070 , @jrtc27 wrote:

> There are a lot of "Resolve for v1.0" issues open against the spec still. Are 
> we sure we want to brand this as 1.0? It will end up as such in the ELF 
> attributes and thus be deemed compatible with future "real" 1.0 binaries.

We could keep the version number as v0.9 or do you think it is better to keep 
it as v1.020201218.


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[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

D95016  focuses on the Clang RVV builtin 
generator and it depends on this commit. I know it is clumsy to list the 
combinations for vadd plainly, but it is a simple way to demonstrate how to add 
RVV builtins in Clang. Could we accept this patch and D92715 
 first if there is no concern about these two 
patches?


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D94583#2514434 , @jrtc27 wrote:

> In D94583#2513915 , @HsiangKai wrote:
>
>> In D94583#2513070 , @jrtc27 wrote:
>>
>>> There are a lot of "Resolve for v1.0" issues open against the spec still. 
>>> Are we sure we want to brand this as 1.0? It will end up as such in the ELF 
>>> attributes and thus be deemed compatible with future "real" 1.0 binaries.
>>
>> We could keep the version number as v0.9 or do you think it is better to 
>> keep it as v1.020201218.
>
> You don't want it to be higher than 1.0 either as that would be newer than 
> the future actual 1.0.

Vector extension is under `-enable-experimental-extensions` in LLVM. Could we 
change the version number to v1.0 to align with current V specification? 
"Experimental v1.0" should be more consistent with "v1.0-draft" V 
specification. What do you think?


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 318929.
HsiangKai added a comment.
Herald added subscribers: jdoerfert, hiraditya.
Herald added a project: LLVM.

Rebase.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -40,7 +40,7 @@
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p9"
+# CHECK: attribute  5, "rv32i2p0_v1p0"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
+# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,7 +47,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -63,7 +63,7 @@
   if (STI.hasFeature(RISCV::FeatureStdExtB))
 Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v0p9";
+Arch += "_v1p0";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
 Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@
   if (STI.hasFeature(RISCV::FeatureExtZbt))
 Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-Arch += "_zvamo0p9";
+Arch += "_zvamo1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-Arch += "_zvlsseg0p9";
+Arch += "_zvlsseg1p0";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2126,7 +2126,7 @@
   if (getFeatureBits(RISCV::FeatureStdExtB))
 formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
   if (getFeatureBits(RISCV::FeatureStdExtV))
-formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
+formalArchStr = (Twine(formalArchStr) + "_v1p0").str();
   if (getFeatureBits(RISCV::FeatureExtZfh))
 formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
   if (getFeatureBits(RISCV::FeatureExtZba))
@@ -2152,9 +2152,9 @@
   if (getFeatureBits(RISCV::FeatureExtZbt))
 formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
   if (getFeatureBit

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:128
+  // after an underscore (_). It is instantiated like Prototype.
+  string MangledSuffix = managed_suffix;
+

mangled_suffix



Comment at: clang/include/clang/Basic/riscv_vector.td:147
+
+  // If HasMask, this flag states that this builtin has a merge operand. It is
+  // always the first operand.

"has a maskedoff operand"



Comment at: clang/include/clang/Basic/riscv_vector.td:149
+  // always the first operand.
+  bit HasMergeOperand = true;
+

Propose to use HasMaskedOffOperand.



Comment at: clang/include/clang/Basic/riscv_vector.td:161
+  // This builtin is valid for the given exponental LMULs.
+  list ELMUL = [0, 1, 2, 3, -1, -2, -3];
+

EMUL according to specification.



Comment at: clang/include/clang/Basic/riscv_vector.td:191
+multiclass GenRVVBuiltin {
+ if !or(!eq(gen_all, true), !eq(gen, true))  then {

mangled_suffix


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf19849a07b67: [RISCV] Update V extension to v1.0-draft 
08a0b464. (authored by HsiangKai).

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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -40,7 +40,7 @@
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p9"
+# CHECK: attribute  5, "rv32i2p0_v1p0"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
+# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,7 +47,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -63,7 +63,7 @@
   if (STI.hasFeature(RISCV::FeatureStdExtB))
 Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v0p9";
+Arch += "_v1p0";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
 Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@
   if (STI.hasFeature(RISCV::FeatureExtZbt))
 Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-Arch += "_zvamo0p9";
+Arch += "_zvamo1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-Arch += "_zvlsseg0p9";
+Arch += "_zvlsseg1p0";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2126,7 +2126,7 @@
   if (getFeatureBits(RISCV::FeatureStdExtB))
 formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
   if (getFeatureBits(RISCV::FeatureStdExtV))
-formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
+formalArchStr = (Twine(formalArchStr) + "_v1p0").str();
   if (getFeatureBits(RISCV::FeatureExtZfh))
 formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
   if (getFeatureBits(RISCV::FeatureExtZba))
@@ -2152,9 +2152,9 @@
   if (getFeatureBits(RISCV::FeatureExtZbt))
 formal

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 319144.
HsiangKai added a comment.

Address @craig.topper's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92715/new/

https://reviews.llvm.org/D92715

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
--- /d

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, jrtc27, rogfer01, frasercrmck, evandro.
Herald added subscribers: vkmr, NickHung, jdoerfert, luismarques, apazos, 
sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

v0.10 is tagged in V specification. Update the version to v0.10.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95680

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -40,7 +40,7 @@
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v1p0"
+# CHECK: attribute  5, "rv32i2p0_v0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 
-.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,7 +47,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
+; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -63,7 +63,7 @@
   if (STI.hasFeature(RISCV::FeatureStdExtB))
 Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v1p0";
+Arch += "_v0p10";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
 Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@
   if (STI.hasFeature(RISCV::FeatureExtZbt))
 Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-Arch += "_zvamo1p0";
+Arch += "_zvamo0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-Arch += "_zvlsseg1p0";
+Arch += "_zvlsseg0p10";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2126,7 +2126,7 @@
   if (getFeatureBits(RISCV::FeatureStdExtB))
 formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
   if (getFeatureBits(RISCV::FeatureStdExtV))
-formalArchStr = (Twine(formalArchStr) + "_v1p0").str();
+

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D95680#2530775 , @asb wrote:

> LGTM modulo one additional request: please update the comment at the top of 
> RISCVInstrInfoV.td to say "0.10" rather than "0.9".

Thanks for pointing it out. I will do it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95680/new/

https://reviews.llvm.org/D95680

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[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG282aca10aeb0: [RISCV] Update the version number to v0.10 for 
vector. (authored by HsiangKai).

Changed prior to commit:
  https://reviews.llvm.org/D95680?vs=320125&id=320226#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95680/new/

https://reviews.llvm.org/D95680

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -40,7 +40,7 @@
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v1p0"
+# CHECK: attribute  5, "rv32i2p0_v0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 
-.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,7 +47,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
+; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -7,7 +7,7 @@
 //===--===//
 ///
 /// This file describes the RISC-V instructions from the standard 'V' Vector
-/// extension, version 0.9.
+/// extension, version 0.10.
 /// This version is still experimental as the 'V' extension hasn't been
 /// ratified yet.
 ///
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -63,7 +63,7 @@
   if (STI.hasFeature(RISCV::FeatureStdExtB))
 Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v1p0";
+Arch += "_v0p10";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
 Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@
   if (STI.hasFeature(RISCV::FeatureExtZbt))
 Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-Arch += "_zvamo1p0";
+Arch += "_zvamo0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-Arch += "_zvlsseg1p0";
+Arch += "_zvlsseg0p10";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
==

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.
Herald added subscribers: StephenFan, vkmr.

In D92715#2520925 , @craig.topper 
wrote:

> I wonder if these types should be prefixed with "__clang_" like AArch64 tuple 
> types?

It seems only AArch64 tuple types have "__clang_" prefix.


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[PATCH] D109322: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2186
+}] in
+def policy : RVVHeader;

khchen wrote:
> It seems like we can rewrite `vsetvli/vsetvl` and ` vsetvlmax` instructions 
> by using the `RVVHeader` mechanism?
> We only need to have one mechanism to dump header code.
Should we create `vsetvli/vsetvlmax` builtins? If we should, we may not be able 
to use `RVVHeader` for these intrinsics.


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[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.
Herald added a subscriber: achieveartificialintelligence.

I will wait for https://reviews.llvm.org/D109322 be accepted. These two patches 
need to get in together.


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[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:162
   // For unit stride load with mask
   // Input: (maskedoff, pointer, mask, vl)
   class RISCVUSLoadMask

khchen wrote:
> maybe we could have another NFC patch to update those `argument info` 
> comments.
I will update these comments. Thanks.


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[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7d39a8a92122: [RISCV] (1/2) Add the tail policy argument to 
builtins/intrinsics. (authored by HsiangKai).

Changed prior to commit:
  https://reviews.llvm.org/D105092?vs=371499&id=374764#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105092/new/

https://reviews.llvm.org/D105092

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
  llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-rv6

[PATCH] D109322: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7afa61e71877: [RISCV] (2/2) Add the tail policy argument to 
builtins/intrinsics. (authored by HsiangKai).

Changed prior to commit:
  https://reviews.llvm.org/D109322?vs=374482&id=374765#toc

Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd-policy.c
 

[PATCH] D110684: [RISCV] Define _m intrinsics as builtins, instead of macros.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, rogfer01, frasercrmck.
Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr, 
dexonsmith, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

In the original design, we levarage _mt intrinsics to define macros for
_m intrinsics. Such as,

__builtin_rvv_vadd_vv_i8m1_mt((vbool8_t)(op0), (vint8m1_t)(op1), 
(vint8m1_t)(op2), (vint8m1_t)(op3), (size_t)(op4), (size_t)VE_TAIL_AGNOSTIC)

However, we could not define generic interface for mask intrinsics any
more due to clang_builtin_alias only accepts clang builtins as its
argument.

In the example,
__rvv_overloaded
 __attribute__((clang_builtin_alias(__builtin_rvv_vadd_vv_i8m1_mt)))

  vint8m1_t vadd(vbool8_t op0, vint8m1_t op1, vint8m1_t op2, vint8m1_t
  op3, size_t op4, size_t op5);

op5 is the tail policy argument. When users want to use vadd generic
interface for masked vector add, they need to specify tail policy in the
previous design. In this patch, we define _m intrinsics as clang
builtins to solve the problem.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110684

Files:
  clang/include/clang/Basic/IdentifierTable.h
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd-policy.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -158,6 +158,7 @@
   bool HasMaskedOffOperand;
   bool HasVL;
   bool HasPolicy;
+  bool IsPolicyIntrinsic;
   bool HasNoMaskedOverloaded;
   bool HasAutoDef; // There is automiatic definition in header
   std::string ManualCodegen;
@@ -173,7 +174,8 @@
   RVVIntrinsic(StringRef Name, StringRef Suffix, StringRef MangledName,
StringRef MangledSuffix, StringRef IRName, bool HasSideEffects,
bool IsMask, bool HasMaskedOffOperand, bool HasVL,
-   bool HasPolicy, bool HasNoMaskedOverloaded, bool HasAutoDef,
+   bool HasPolicy, bool IsPolicyIntrinsic,
+   bool HasNoMaskedOverloaded, bool HasAutoDef,
StringRef ManualCodegen, const RVVTypes &Types,
const std::vector &IntrinsicTypes,
StringRef RequiredExtension, unsigned NF);
@@ -185,6 +187,7 @@
   bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
   bool hasVL() const { return HasVL; }
   bool hasPolicy() const { return HasPolicy; }
+  bool isPolicyIntrinsic() const { return IsPolicyIntrinsic; }
   bool hasNoMaskedOverloaded() const { return HasNoMaskedOverloaded; }
   bool hasManualCodegen() const { return !ManualCodegen.empty(); }
   bool hasAutoDef() const { return HasAutoDef; }
@@ -201,9 +204,6 @@
   // init the RVVIntrinsic ID and IntrinsicTypes.
   void emitCodeGenSwitchBody(raw_ostream &o) const;
 
-  // Emit the define macors for mask intrinsics using _mt intrinsics.
-  void emitIntrinsicMaskMacro(raw_ostream &o) const;
-
   // Emit the macros for mapping C/C++ intrinsic function to builtin functions.
   void emitIntrinsicMacro(raw_ostream &o) const;
 
@@ -764,14 +764,16 @@
StringRef NewMangledName, StringRef MangledSuffix,
StringRef IRName, bool HasSideEffects, bool IsMask,
bool HasMaskedOffOperand, bool HasVL, bool HasPolicy,
-   bool HasNoMaskedOverloaded, bool HasAutoDef,
-   StringRef ManualCodegen, const RVVTypes &OutInTypes,
+   bool IsPolicyIntrinsic, bool HasNoMaskedOverloaded,
+   bool HasAutoDef, StringRef ManualCodegen,
+   const RVVTypes &OutInTypes,
const std::vector &NewIntrinsicTypes,
StringRef RequiredExtension, unsigned NF)
 : IRName(IRName), HasSideEffects(HasSideEffects), IsMask(IsMask),
   HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL),
-  HasPolicy(HasPolicy), HasNoMaskedOverloaded(HasNoMaskedOverloaded),
-  HasAutoDef(HasAutoDef), ManualCodegen(ManualCodegen.str()), NF(NF) {
+  HasPolicy(HasPolicy), IsPolicyIntrinsic(IsPolicyIntrinsic),
+  HasNoMaskedOverloaded(HasNoMaskedOverloaded), HasAutoDef(HasAutoDef),
+  ManualCodegen(ManualCodegen.str()), NF(NF) {
 
   // Init Name and MangledName
   Name = NewName.str();
@@ -785,7 +787,7 @@
 MangledName += "_" + MangledSuffix.str();
   if (IsMask) {
 Name += "_m";
-if (HasPolicy)
+if (IsPolicyIntrinsic)
   Name += "t";
   }
   // Init RISC-V

[PATCH] D110684: [RISCV] Define _m intrinsics as builtins, instead of macros.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 376890.
HsiangKai added a comment.

Update test cases.


Repository:
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Files:
  clang/include/clang/Basic/IdentifierTable.h
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamomax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamomin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoswap.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c
  clang/test/C

[PATCH] D106044: [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.
Herald added a subscriber: achieveartificialintelligence.

Ping.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D92715#2544233 , @craig.topper 
wrote:

> In D92715#2544178 , @HsiangKai wrote:
>
>> In D92715#2520925 , @craig.topper 
>> wrote:
>>
>>> I wonder if these types should be prefixed with "__clang_" like AArch64 
>>> tuple types?
>>
>> It seems only AArch64 tuple types have "__clang_" prefix.
>
> I think the other types don't have it because they are defined by an ARM 
> standard. See the description for https://reviews.llvm.org/D81721

It seems to use `__clang_` to differentiate tuple types and non-tuple types. 
The mangling rules are different between tuple types and non-tuple types in 
ARM. We have no mangling rules in our specification. I have a TODO item in this 
patch to clarify the mangling rules later.


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[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:11127
+def err_riscvv_builtin_not_useable : Error<
+   "builtin requires 'V' extension support to be enabled">;
 } // end of sema component.

Jim wrote:
> Add blank line.
> Is it "err_riscvv_builtin_not_enabled"?
I use the name that is defined in BSC version. It makes sense to me that it 
means "the risc-v V builtins are not useable."

@rogfer01, do you have any opinion on it?


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[Hsiangkai Wang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG766ee1096f0b: [Clang][RISCV] Define RISC-V V builtin types 
(authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92715/new/

https://reviews.llvm.org/D92715

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Ind

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, frasercrmck, rogfer01.
Herald added subscribers: StephenFan, vkmr, dexonsmith, evandro, luismarques, 
apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

The types in Zvlsseg occupy multiple vector registers. We use Record type in 
clang to represent Zvlsseg types. It will not increase the number of builtin 
types in clang. It just adds multiple implicit defined Record types for Zvlsseg.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97264

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/RISCVVTypes.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Sema/Sema.cpp
  clang/test/Sema/riscv-types.c

Index: clang/test/Sema/riscv-types.c
===
--- clang/test/Sema/riscv-types.c
+++ clang/test/Sema/riscv-types.c
@@ -133,4 +133,10 @@
 
   // CHECK: __rvv_int8mf2_t x43;
   __rvv_int8mf2_t x43;
+
+  // CHECK: __rvv_int8mf2x2_t x44;
+  __rvv_int8mf2x2_t x44;
+
+  // CHECK: __rvv_int8m2x2_t x45;
+  __rvv_int8m2x2_t x45;
 }
Index: clang/lib/Sema/Sema.cpp
===
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -389,6 +389,8 @@
   if (Context.getTargetInfo().hasRISCVVTypes()) {
 #define RVV_TYPE(Name, Id, SingletonId)\
   addImplicitTypedef(Name, Context.SingletonId);
+#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false) \
+  addImplicitTypedef(Name, Context.SingletonId);
 #include "clang/Basic/RISCVVTypes.def"
   }
 
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10669,6 +10669,10 @@
 }
   }
 
+  if (Ty->isRecordType() && !Ty->getAsRecordDecl()->field_empty() &&
+  Ty->getAsRecordDecl()->field_begin()->getType()->isSizelessType())
+return ABIArgInfo::getDirect(CGT.ConvertType(Ty));
+
   uint64_t NeededAlign = getContext().getTypeAlign(Ty);
   bool MustUseStack = false;
   // Determine the number of GPRs needed to pass the current argument
Index: clang/lib/AST/ASTContext.cpp
===
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -1439,6 +1439,8 @@
   if (Target.hasRISCVVTypes()) {
 #define RVV_TYPE(Name, Id, SingletonId)\
   InitBuiltinType(SingletonId, BuiltinType::Id);
+#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP)   \
+  InitRVVTupleType(SingletonId, Name, BuiltinType::ElemId, NF);
 #include "clang/Basic/RISCVVTypes.def"
   }
 
@@ -1478,6 +1480,36 @@
   }
 }
 
+void ASTContext::InitRVVTupleType(QualType &R, StringRef Name,
+  BuiltinType::Kind K, unsigned NF) {
+  auto TypeIter = llvm::find_if(Types, [&K](Type *Ty) {
+ if (Ty->isBuiltinType()) {
+   return cast(Ty)->getKind() == K;
+ }
+ return false;
+   });
+
+  if (TypeIter != Types.end()) {
+RecordDecl *RD = buildImplicitRecord(Name);
+RD->startDefinition();
+for (unsigned I = 0; I < NF; ++I) {
+  SmallVector FieldNameStorage;
+  FieldDecl *Field = FieldDecl::Create(*this, RD, SourceLocation(),
+   SourceLocation(),
+   &Idents.get(
+ (Twine("v") + Twine(I)).toStringRef(FieldNameStorage)),
+   QualType(*TypeIter, 0), nullptr, nullptr, false,
+   ICIS_NoInit);
+  Field->setAccess(AS_public);
+  RD->addDecl(Field);
+}
+RD->completeDefinition();
+
+TypedefDecl *TD = buildImplicitTypedef(getTagDeclType(RD), Name);
+R = getTypedefType(TD);
+  }
+}
+
 DiagnosticsEngine &ASTContext::getDiagnostics() const {
   return SourceMgr.getDiagnostics();
 }
@@ -3849,7 +3881,8 @@
 /// type of the specified element type and size. VectorType must be a built-in
 /// type.
 QualType ASTContext::getScalableVectorType(QualType EltTy,
-   unsigned NumElts) const {
+   unsigned NumElts,
+   unsigned Tuple) const {
   if (Target->hasAArch64SVETypes()) {
 uint64_t EltTySize = getTypeSize(EltTy);
 #define SVE_VECTOR_TYPE(Name, MangledName, Id, SingletonId, 

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 325957.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97264/new/

https://reviews.llvm.org/D97264

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/RISCVVTypes.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/Sema.cpp
  clang/test/Sema/riscv-types.c

Index: clang/test/Sema/riscv-types.c
===
--- clang/test/Sema/riscv-types.c
+++ clang/test/Sema/riscv-types.c
@@ -133,4 +133,10 @@
 
   // CHECK: __rvv_int8mf2_t x43;
   __rvv_int8mf2_t x43;
+
+  // CHECK: __rvv_int8mf2x2_t x44;
+  __rvv_int8mf2x2_t x44;
+
+  // CHECK: __rvv_int8m2x2_t x45;
+  __rvv_int8m2x2_t x45;
 }
Index: clang/lib/Sema/Sema.cpp
===
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -389,6 +389,8 @@
   if (Context.getTargetInfo().hasRISCVVTypes()) {
 #define RVV_TYPE(Name, Id, SingletonId)\
   addImplicitTypedef(Name, Context.SingletonId);
+#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NumEls, ElBits, NF, IsSigned, IsFP) \
+  addImplicitTypedef(Name, Context.SingletonId);
 #include "clang/Basic/RISCVVTypes.def"
   }
 
Index: clang/lib/AST/ASTContext.cpp
===
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -1439,6 +1439,8 @@
   if (Target.hasRISCVVTypes()) {
 #define RVV_TYPE(Name, Id, SingletonId)\
   InitBuiltinType(SingletonId, BuiltinType::Id);
+#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP)   \
+  InitRVVTupleType(SingletonId, Name, BuiltinType::ElemId, NF);
 #include "clang/Basic/RISCVVTypes.def"
   }
 
@@ -1478,6 +1480,36 @@
   }
 }
 
+void ASTContext::InitRVVTupleType(QualType &R, StringRef Name,
+  BuiltinType::Kind K, unsigned NF) {
+  auto TypeIter = llvm::find_if(Types, [&K](Type *Ty) {
+ if (Ty->isBuiltinType()) {
+   return cast(Ty)->getKind() == K;
+ }
+ return false;
+   });
+
+  if (TypeIter != Types.end()) {
+RecordDecl *RD = buildImplicitRecord(Name);
+RD->startDefinition();
+for (unsigned I = 0; I < NF; ++I) {
+  SmallVector FieldNameStorage;
+  FieldDecl *Field = FieldDecl::Create(*this, RD, SourceLocation(),
+   SourceLocation(),
+   &Idents.get(
+ (Twine("v") + Twine(I)).toStringRef(FieldNameStorage)),
+   QualType(*TypeIter, 0), nullptr, nullptr, false,
+   ICIS_NoInit);
+  Field->setAccess(AS_public);
+  RD->addDecl(Field);
+}
+RD->completeDefinition();
+
+TypedefDecl *TD = buildImplicitTypedef(getTagDeclType(RD), Name);
+R = getTypedefType(TD);
+  }
+}
+
 DiagnosticsEngine &ASTContext::getDiagnostics() const {
   return SourceMgr.getDiagnostics();
 }
@@ -2173,8 +2205,7 @@
 Align = Size;  \
 break;
 #include "clang/Basic/PPCTypes.def"
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, ElKind, ElBits, NF, IsSigned,   \
-IsFP)  \
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, ElKind, ElBits, IsSigned, IsFP) \
   case BuiltinType::Id:\
 Width = 0; \
 Align = ElBits;\
@@ -3829,15 +3860,14 @@
 return SVE_ELTTY(BFloat16Ty, 8, 3);
   case BuiltinType::SveBFloat16x4:
 return SVE_ELTTY(BFloat16Ty, 8, 4);
-#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF, \
-IsSigned)  \
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, IsSigned)   \
   case BuiltinType::Id:\
 return {getIntTypeForBitwidth(ElBits, IsSigned),   \
-llvm::ElementCount::getScalable(NumEls), NF};
-#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)   \
+llvm::ElementCount::getScalable(NumEls), 1};
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits)   \
   case BuiltinType::Id:\
 return {ElBits == 16 ? HalfTy : (ElBits == 32 ? FloatTy : DoubleTy),   \
-llvm::ElementCount::getScalable(NumEls), NF};
+llvm::ElementCount::getScalable(NumEls), 1};
 #define RVV

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked 3 inline comments as done.
HsiangKai added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:10672
 
+  if (Ty->isRecordType() && !Ty->getAsRecordDecl()->field_empty() &&
+  Ty->getAsRecordDecl()->field_begin()->getType()->isSizelessType())

craig.topper wrote:
> Are we able to test this yet?
No, I removed it.


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[PATCH] D97264: [RISCV] Define types for Zvlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/include/clang/AST/ASTContext.h:1024
+#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP) \
+  QualType SingletonId;
 #include "clang/Basic/RISCVVTypes.def"

craig.topper wrote:
> craig.topper wrote:
> > Why is this QualType and not CanQualType? I don't know what the difference 
> > is myself.
> Is there any downside to adding all these members to the ASTContext? I 
> suspect the builtin types have grown quite a bit since this was initially set 
> up. @rjmccall or @rsmith is this something we need to be concerned about?
CanQualType could not be used for typedef types.


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