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================ Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; ---------------- evandro wrote: > Methinks that these constraints `WidenV`, `WidenW`, `WidenCvt`, should be > split up by their components. IOW, into `Widen`, `Wide` (input), `Cvt`. > This way, it's easier to test for specific constraints. Do you mean WidenV = Widen; WidenW = Widen | WideInput; WidenCvt = Widen | Cvt; Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D69987 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
