[clang] [llvm] [HLSL] Adding Flatten and Branch if attributes (PR #116331)

2025-01-06 Thread Henry Jiang via cfe-commits 

mustartt wrote:

Hi @joaosaffran I believe this patch is causing an build error in 
`clang-ppc64le-rhel` build bot. 
https://lab.llvm.org/buildbot/#/builders/145/builds/4252

```
FAILED: 
tools/clang/lib/CodeGen/CMakeFiles/obj.clangCodeGen.dir/CodeGenFunction.cpp.o 
ccache /home/docker/llvm-external-buildbots/clang.17.0.6/bin/clang++ 
--gcc-toolchain=/gcc-toolchain/usr -DCLANG_EXPORTS -DGTEST_HAS_RTTI=0 -D_DEBUG 
-D_GLIBCXX_ASSERTIONS -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS 
-D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS 
-I/home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/tools/clang/lib/CodeGen
 
-I/home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/clang/lib/CodeGen
 
-I/home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/clang/include
 
-I/home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/tools/clang/include
 
-I/home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/include
 
-I/home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/llvm/include
 -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror 
-Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra 
-Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers 
-pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough 
-Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor 
-Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion 
-Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color 
-ffunction-sections -fdata-sections -fno-common -Woverloaded-virtual 
-Wno-nested-anon-types -O3 -DNDEBUG -std=c++17  -fno-exceptions -funwind-tables 
-fno-rtti -UNDEBUG -MD -MT 
tools/clang/lib/CodeGen/CMakeFiles/obj.clangCodeGen.dir/CodeGenFunction.cpp.o 
-MF 
tools/clang/lib/CodeGen/CMakeFiles/obj.clangCodeGen.dir/CodeGenFunction.cpp.o.d 
-o 
tools/clang/lib/CodeGen/CMakeFiles/obj.clangCodeGen.dir/CodeGenFunction.cpp.o 
-c 
/home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/clang/lib/CodeGen/CodeGenFunction.cpp
/home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/clang/lib/CodeGen/CodeGenFunction.cpp:2089:11:
 error: enumeration value 'SpellingNotCalculated' not handled in switch 
[-Werror,-Wswitch]
 2089 |   switch (HLSLControlFlowAttr) {
  |   ^~~
1 error generated.
```

https://github.com/llvm/llvm-project/pull/116331
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[clang] [llvm] [HLSL] Adding Flatten and Branch if attributes (PR #116331)

2025-01-06 Thread Henry Jiang via cfe-commits 

mustartt wrote:

Thanks! Not a problem, there were another earlier scyl related failure so the 
bots didn't pick this one up. 

https://github.com/llvm/llvm-project/pull/116331
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[clang] [flang] Revert "[flang] Add -f[no-]unroll-loops flag (#122906)" (PR #123779)

2025-01-21 Thread Henry Jiang via cfe-commits 

https://github.com/mustartt created 
https://github.com/llvm/llvm-project/pull/123779

This commit causes an regression in `ppc64-flang-aix` and 
`ppc64le-flang-rhel-clang`. It only exposes that unrolling has no effect on 
powerpc target and the issue is tracked here 
https://github.com/llvm/llvm-project/issues/123668

This reverts commit 0195ec452e16a0ff4b4f4ff2e2ea5a1dd5a20563.

>From 2c651ade2a8ae018588f6012b7015f7fab8af4e3 Mon Sep 17 00:00:00 2001
From: Henry Jiang 
Date: Tue, 21 Jan 2025 11:53:15 -0500
Subject: [PATCH] Revert "[flang] Add -f[no-]unroll-loops flag (#122906)"

This reverts commit 0195ec452e16a0ff4b4f4ff2e2ea5a1dd5a20563.
---
 clang/include/clang/Driver/Options.td |  4 +-
 clang/lib/Driver/ToolChains/Flang.cpp |  6 +--
 .../include/flang/Frontend/CodeGenOptions.def |  1 -
 flang/lib/Frontend/CompilerInvocation.cpp |  4 --
 flang/lib/Frontend/FrontendActions.cpp|  2 -
 flang/test/Driver/funroll-loops.f90   |  5 ---
 flang/test/HLFIR/unroll-loops.fir | 42 ---
 flang/test/Integration/unroll-loops.f90   | 37 
 8 files changed, 5 insertions(+), 96 deletions(-)
 delete mode 100644 flang/test/Driver/funroll-loops.f90
 delete mode 100644 flang/test/HLFIR/unroll-loops.fir
 delete mode 100644 flang/test/Integration/unroll-loops.f90

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 852051e772fc1c..4d1bd208754548 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4162,9 +4162,9 @@ def ftrap_function_EQ : Joined<["-"], "ftrap-function=">, 
Group,
   HelpText<"Issue call to specified function rather than a trap instruction">,
   MarshallingInfoString>;
 def funroll_loops : Flag<["-"], "funroll-loops">, Group,
-  HelpText<"Turn on loop unroller">, Visibility<[ClangOption, CC1Option, 
FlangOption, FC1Option]>;
+  HelpText<"Turn on loop unroller">, Visibility<[ClangOption, CC1Option]>;
 def fno_unroll_loops : Flag<["-"], "fno-unroll-loops">, Group,
-  HelpText<"Turn off loop unroller">, Visibility<[ClangOption, CC1Option, 
FlangOption, FC1Option]>;
+  HelpText<"Turn off loop unroller">, Visibility<[ClangOption, CC1Option]>;
 def ffinite_loops: Flag<["-"],  "ffinite-loops">, Group,
   HelpText<"Assume all non-trivial loops are finite.">, 
Visibility<[ClangOption, CC1Option]>;
 def fno_finite_loops: Flag<["-"], "fno-finite-loops">, Group,
diff --git a/clang/lib/Driver/ToolChains/Flang.cpp 
b/clang/lib/Driver/ToolChains/Flang.cpp
index 9c1fd28a3a8a26..8688a199018e84 100644
--- a/clang/lib/Driver/ToolChains/Flang.cpp
+++ b/clang/lib/Driver/ToolChains/Flang.cpp
@@ -156,9 +156,9 @@ void Flang::addCodegenOptions(const ArgList &Args,
options::OPT_fno_ppc_native_vec_elem_order,
options::OPT_fppc_native_vec_elem_order,
options::OPT_finit_global_zero,
-   options::OPT_fno_init_global_zero, 
options::OPT_ftime_report,
-   options::OPT_ftime_report_EQ, options::OPT_funroll_loops,
-   options::OPT_fno_unroll_loops});
+   options::OPT_fno_init_global_zero, 
+   options::OPT_ftime_report,
+   options::OPT_ftime_report_EQ});
 }
 
 void Flang::addPicOptions(const ArgList &Args, ArgStringList &CmdArgs) const {
diff --git a/flang/include/flang/Frontend/CodeGenOptions.def 
b/flang/include/flang/Frontend/CodeGenOptions.def
index deb8d1aede518b..9d03ec88a56b8a 100644
--- a/flang/include/flang/Frontend/CodeGenOptions.def
+++ b/flang/include/flang/Frontend/CodeGenOptions.def
@@ -32,7 +32,6 @@ CODEGENOPT(PrepareForThinLTO , 1, 0) ///< Set when -flto=thin 
is enabled on the
  ///< compile step.
 CODEGENOPT(StackArrays, 1, 0) ///< -fstack-arrays (enable the stack-arrays 
pass)
 CODEGENOPT(LoopVersioning, 1, 0) ///< Enable loop versioning.
-CODEGENOPT(UnrollLoops, 1, 0) ///< Enable loop unrolling
 CODEGENOPT(AliasAnalysis, 1, 0) ///< Enable alias analysis pass
 
 CODEGENOPT(Underscoring, 1, 1)
diff --git a/flang/lib/Frontend/CompilerInvocation.cpp 
b/flang/lib/Frontend/CompilerInvocation.cpp
index 3c6da4687f65d3..78d1199c19749b 100644
--- a/flang/lib/Frontend/CompilerInvocation.cpp
+++ b/flang/lib/Frontend/CompilerInvocation.cpp
@@ -246,10 +246,6 @@ static void 
parseCodeGenArgs(Fortran::frontend::CodeGenOptions &opts,
clang::driver::options::OPT_fno_loop_versioning, false))
 opts.LoopVersioning = 1;
 
-  opts.UnrollLoops = args.hasFlag(clang::driver::options::OPT_funroll_loops,
-  clang::driver::options::OPT_fno_unroll_loops,
-  (opts.OptimizationLevel > 1));
-
   opts.AliasAnalysis = opts.OptimizationLevel > 0;
 
   // -mframe-pointer=none/non-leaf/all option.
diff --git a/flang/lib/Frontend/FrontendActions.cpp 
b/flang/lib/Frontend/FrontendActions.cpp
index b0545a7ac2f99a..52a

[clang] [flang] Revert "[flang] Add -f[no-]unroll-loops flag (#122906)" (PR #123779)

2025-01-21 Thread Henry Jiang via cfe-commits 

https://github.com/mustartt closed 
https://github.com/llvm/llvm-project/pull/123779
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[clang] [flang] [flang] Add -f[no-]unroll-loops flag (PR #122906)

2025-01-20 Thread Henry Jiang via cfe-commits 

mustartt wrote:

Hi @DavidTruby, have are you investigating this failure on 
`ppc64le-flang-rhel-clang`? it has been failing for a few days, couldjust 
please update us on a possible fix for it. I can xfail and open an issue for 
this test case while you investigate in the meantime. Please let me know if 
there is anyway I can help.

https://github.com/llvm/llvm-project/pull/122906
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[clang] [llvm] [PowerPC] Enable indiviual crbits tracking at -O2 (PR #133617)

2025-04-04 Thread Henry Jiang via cfe-commits 

https://github.com/mustartt updated 
https://github.com/llvm/llvm-project/pull/133617

>From 8a71c3bb096045a10c8800d9abbc9bb9cb603ebe Mon Sep 17 00:00:00 2001
From: Henry Jiang 
Date: Sun, 30 Mar 2025 00:23:10 -0400
Subject: [PATCH] Enable indiviual crbits tracking at O2

---
 clang/lib/Basic/Targets/PPC.cpp  |  5 --
 llvm/lib/Target/PowerPC/PPC.td   | 82 ++--
 llvm/lib/Target/PowerPC/PPCSubtarget.cpp |  9 +++
 llvm/lib/Target/PowerPC/PPCSubtarget.h   |  1 +
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp |  7 --
 llvm/test/CodeGen/PowerPC/crbit-asm.ll   |  4 +-
 6 files changed, 55 insertions(+), 53 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 425ad68bb9098..61d567892b498 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -559,11 +559,6 @@ bool PPCTargetInfo::initFeatureMap(
 .Case("pwr9", true)
 .Case("pwr8", true)
 .Default(false);
-  Features["crbits"] = llvm::StringSwitch(CPU)
-.Case("ppc64le", true)
-.Case("pwr9", true)
-.Case("pwr8", true)
-.Default(false);
   Features["vsx"] = llvm::StringSwitch(CPU)
 .Case("ppc64le", true)
 .Case("pwr9", true)
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 39da428461393..9f0f271b619c7 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -74,7 +74,7 @@ def Feature64BitRegs : 
SubtargetFeature<"64bitregs","Use64BitRegs", "true",
 
 // Specify if we should store and manipulate i1 values in the individual
 // condition register bits.
-def FeatureCRBits: SubtargetFeature<"crbits", "UseCRBits", "true",
+def FeatureCRBits: SubtargetFeature<"crbits", "HasCRBits", "true",
   "Use condition-register bits individually">;
 def FeatureFPU   : SubtargetFeature<"fpu","HasFPU","true",
 "Enable classic FPU instructions",
@@ -390,6 +390,7 @@ def ProcessorFeatures {
   FeatureFPCVT,
   FeatureISEL,
   FeaturePOPCNTD,
+  FeatureCRBits,
   FeatureCMPB,
   FeatureLDBRX,
   Feature64Bit,
@@ -577,79 +578,82 @@ include "GISel/PPCRegisterBanks.td"
 //
 
 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
-   FeatureMFTB]>;
+   FeatureMFTB, FeatureCRBits]>;
 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
   FeatureFRES, FeatureFRSQRTE,
   FeatureICBT, FeatureBookE,
-  FeatureMSYNC, FeatureMFTB]>;
+  FeatureMSYNC, FeatureMFTB,
+  FeatureCRBits]>;
 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
   FeatureFRES, FeatureFRSQRTE,
   FeatureICBT, FeatureBookE,
-  FeatureMSYNC, FeatureMFTB]>;
-def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
+  FeatureMSYNC, FeatureMFTB,
+  FeatureCRBits]>;
+def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU,
+   FeatureCRBits]>;
 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
-   FeatureMFTB]>;
-def : Processor<"603", G3Itineraries, [Directive603,
-   FeatureFRES, FeatureFRSQRTE,
-   FeatureMFTB]>;
-def : Processor<"603e", G3Itineraries, [Directive603,
-FeatureFRES, FeatureFRSQRTE,
-FeatureMFTB]>;
+   FeatureMFTB, FeatureCRBits]>;
+def : Processor<"603", G3Itineraries, [Directive603, FeatureFRES,
+   FeatureFRSQRTE, FeatureMFTB,
+   FeatureCRBits]>;
+def : Processor<"603e", G3Itineraries, [Directive603, FeatureFRES,
+FeatureFRSQRTE, FeatureMFTB,
+FeatureCRBits]>;
 def : Processor<"603ev", G3Itinera

[clang] [llvm] [PowerPC] Enable indiviual crbits tracking at -O2 (PR #133617)

2025-04-05 Thread Henry Jiang via cfe-commits 

https://github.com/mustartt created 
https://github.com/llvm/llvm-project/pull/133617

https://reviews.llvm.org/D124060

>From d10bfa59ba468d1f3159aad66b532e4be0e56831 Mon Sep 17 00:00:00 2001
From: Henry Jiang 
Date: Sun, 30 Mar 2025 00:23:10 -0400
Subject: [PATCH] Enable indiviual crbits tracking at O2

---
 clang/lib/Basic/Targets/PPC.cpp  |  5 --
 llvm/lib/Target/PowerPC/PPC.td   | 82 ++--
 llvm/lib/Target/PowerPC/PPCSubtarget.cpp |  9 +++
 llvm/lib/Target/PowerPC/PPCSubtarget.h   |  1 +
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp |  7 --
 5 files changed, 53 insertions(+), 51 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 425ad68bb9098..61d567892b498 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -559,11 +559,6 @@ bool PPCTargetInfo::initFeatureMap(
 .Case("pwr9", true)
 .Case("pwr8", true)
 .Default(false);
-  Features["crbits"] = llvm::StringSwitch(CPU)
-.Case("ppc64le", true)
-.Case("pwr9", true)
-.Case("pwr8", true)
-.Default(false);
   Features["vsx"] = llvm::StringSwitch(CPU)
 .Case("ppc64le", true)
 .Case("pwr9", true)
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 39da428461393..9f0f271b619c7 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -74,7 +74,7 @@ def Feature64BitRegs : 
SubtargetFeature<"64bitregs","Use64BitRegs", "true",
 
 // Specify if we should store and manipulate i1 values in the individual
 // condition register bits.
-def FeatureCRBits: SubtargetFeature<"crbits", "UseCRBits", "true",
+def FeatureCRBits: SubtargetFeature<"crbits", "HasCRBits", "true",
   "Use condition-register bits individually">;
 def FeatureFPU   : SubtargetFeature<"fpu","HasFPU","true",
 "Enable classic FPU instructions",
@@ -390,6 +390,7 @@ def ProcessorFeatures {
   FeatureFPCVT,
   FeatureISEL,
   FeaturePOPCNTD,
+  FeatureCRBits,
   FeatureCMPB,
   FeatureLDBRX,
   Feature64Bit,
@@ -577,79 +578,82 @@ include "GISel/PPCRegisterBanks.td"
 //
 
 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
-   FeatureMFTB]>;
+   FeatureMFTB, FeatureCRBits]>;
 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
   FeatureFRES, FeatureFRSQRTE,
   FeatureICBT, FeatureBookE,
-  FeatureMSYNC, FeatureMFTB]>;
+  FeatureMSYNC, FeatureMFTB,
+  FeatureCRBits]>;
 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
   FeatureFRES, FeatureFRSQRTE,
   FeatureICBT, FeatureBookE,
-  FeatureMSYNC, FeatureMFTB]>;
-def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
+  FeatureMSYNC, FeatureMFTB,
+  FeatureCRBits]>;
+def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU,
+   FeatureCRBits]>;
 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
-   FeatureMFTB]>;
-def : Processor<"603", G3Itineraries, [Directive603,
-   FeatureFRES, FeatureFRSQRTE,
-   FeatureMFTB]>;
-def : Processor<"603e", G3Itineraries, [Directive603,
-FeatureFRES, FeatureFRSQRTE,
-FeatureMFTB]>;
+   FeatureMFTB, FeatureCRBits]>;
+def : Processor<"603", G3Itineraries, [Directive603, FeatureFRES,
+   FeatureFRSQRTE, FeatureMFTB,
+   FeatureCRBits]>;
+def : Processor<"603e", G3Itineraries, [Directive603, FeatureFRES,
+FeatureFRSQRTE, FeatureMFTB,
+FeatureCRBits]>;
 def : Processor<"603ev", G3Itineraries, [Directive603,

[clang] [llvm] [PowerPC] Enable indiviual crbits tracking at -O2 (PR #133617)

2025-03-31 Thread Henry Jiang via cfe-commits 

https://github.com/mustartt edited 
https://github.com/llvm/llvm-project/pull/133617
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[clang] [llvm] [PowerPC] Enable indiviual crbits tracking at -O2 (PR #133617)

2025-03-31 Thread Henry Jiang via cfe-commits 

https://github.com/mustartt edited 
https://github.com/llvm/llvm-project/pull/133617
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[clang] [llvm] [PowerPC] Enable indiviual crbits tracking at -O2 (PR #133617)

2025-04-04 Thread Henry Jiang via cfe-commits 

https://github.com/mustartt updated 
https://github.com/llvm/llvm-project/pull/133617

>From 8a71c3bb096045a10c8800d9abbc9bb9cb603ebe Mon Sep 17 00:00:00 2001
From: Henry Jiang 
Date: Sun, 30 Mar 2025 00:23:10 -0400
Subject: [PATCH 1/2] Enable indiviual crbits tracking at O2

---
 clang/lib/Basic/Targets/PPC.cpp  |  5 --
 llvm/lib/Target/PowerPC/PPC.td   | 82 ++--
 llvm/lib/Target/PowerPC/PPCSubtarget.cpp |  9 +++
 llvm/lib/Target/PowerPC/PPCSubtarget.h   |  1 +
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp |  7 --
 llvm/test/CodeGen/PowerPC/crbit-asm.ll   |  4 +-
 6 files changed, 55 insertions(+), 53 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 425ad68bb9098..61d567892b498 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -559,11 +559,6 @@ bool PPCTargetInfo::initFeatureMap(
 .Case("pwr9", true)
 .Case("pwr8", true)
 .Default(false);
-  Features["crbits"] = llvm::StringSwitch(CPU)
-.Case("ppc64le", true)
-.Case("pwr9", true)
-.Case("pwr8", true)
-.Default(false);
   Features["vsx"] = llvm::StringSwitch(CPU)
 .Case("ppc64le", true)
 .Case("pwr9", true)
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 39da428461393..9f0f271b619c7 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -74,7 +74,7 @@ def Feature64BitRegs : 
SubtargetFeature<"64bitregs","Use64BitRegs", "true",
 
 // Specify if we should store and manipulate i1 values in the individual
 // condition register bits.
-def FeatureCRBits: SubtargetFeature<"crbits", "UseCRBits", "true",
+def FeatureCRBits: SubtargetFeature<"crbits", "HasCRBits", "true",
   "Use condition-register bits individually">;
 def FeatureFPU   : SubtargetFeature<"fpu","HasFPU","true",
 "Enable classic FPU instructions",
@@ -390,6 +390,7 @@ def ProcessorFeatures {
   FeatureFPCVT,
   FeatureISEL,
   FeaturePOPCNTD,
+  FeatureCRBits,
   FeatureCMPB,
   FeatureLDBRX,
   Feature64Bit,
@@ -577,79 +578,82 @@ include "GISel/PPCRegisterBanks.td"
 //
 
 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
-   FeatureMFTB]>;
+   FeatureMFTB, FeatureCRBits]>;
 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
   FeatureFRES, FeatureFRSQRTE,
   FeatureICBT, FeatureBookE,
-  FeatureMSYNC, FeatureMFTB]>;
+  FeatureMSYNC, FeatureMFTB,
+  FeatureCRBits]>;
 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
   FeatureFRES, FeatureFRSQRTE,
   FeatureICBT, FeatureBookE,
-  FeatureMSYNC, FeatureMFTB]>;
-def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
+  FeatureMSYNC, FeatureMFTB,
+  FeatureCRBits]>;
+def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU,
+   FeatureCRBits]>;
 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
-   FeatureMFTB]>;
-def : Processor<"603", G3Itineraries, [Directive603,
-   FeatureFRES, FeatureFRSQRTE,
-   FeatureMFTB]>;
-def : Processor<"603e", G3Itineraries, [Directive603,
-FeatureFRES, FeatureFRSQRTE,
-FeatureMFTB]>;
+   FeatureMFTB, FeatureCRBits]>;
+def : Processor<"603", G3Itineraries, [Directive603, FeatureFRES,
+   FeatureFRSQRTE, FeatureMFTB,
+   FeatureCRBits]>;
+def : Processor<"603e", G3Itineraries, [Directive603, FeatureFRES,
+FeatureFRSQRTE, FeatureMFTB,
+FeatureCRBits]>;
 def : Processor<"603ev", G3Iti

[clang] [llvm] [PowerPC] Enable indiviual crbits tracking at -O2 (PR #133617)

2025-04-04 Thread Henry Jiang via cfe-commits 

https://github.com/mustartt edited 
https://github.com/llvm/llvm-project/pull/133617
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